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KVM: emulate: speed up emulated moves
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
9dac77fa 517static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 518{
9dac77fa
AK		 519 ctxt->has_seg_override = true;
520 ctxt->seg_override = seg;
7a5b56df
AK		 521}
522
7b105ca2 523static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 524{
525 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
526 return 0;
527
7b105ca2 528 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 529}
530
9dac77fa 531static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 532{
9dac77fa 533 if (!ctxt->has_seg_override)
7a5b56df
AK		 534 return 0;
535
9dac77fa 536 return ctxt->seg_override;
7a5b56df
AK		 537}
538
35d3d4a1
AK		 539static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
540 u32 error, bool valid)
54b8486f 541{
da9cb575
AK		 542 ctxt->exception.vector = vec;
543 ctxt->exception.error_code = error;
544 ctxt->exception.error_code_valid = valid;
35d3d4a1 545 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 546}
547
3b88e41a
JR		 548static int emulate_db(struct x86_emulate_ctxt *ctxt)
549{
550 return emulate_exception(ctxt, DB_VECTOR, 0, false);
551}
552
35d3d4a1 553static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 554{
35d3d4a1 555 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 556}
557
618ff15d
AK		 558static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
559{
560 return emulate_exception(ctxt, SS_VECTOR, err, true);
561}
562
35d3d4a1 563static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 566}
567
35d3d4a1 568static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 569{
35d3d4a1 570 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 571}
572
34d1f490
AK		 573static int emulate_de(struct x86_emulate_ctxt *ctxt)
574{
35d3d4a1 575 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 576}
577
1253791d
AK		 578static int emulate_nm(struct x86_emulate_ctxt *ctxt)
579{
580 return emulate_exception(ctxt, NM_VECTOR, 0, false);
581}
582
1aa36616
AK		 583static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
584{
585 u16 selector;
586 struct desc_struct desc;
587
588 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
589 return selector;
590}
591
592static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
593 unsigned seg)
594{
595 u16 dummy;
596 u32 base3;
597 struct desc_struct desc;
598
599 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
600 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
601}
602
1c11b376
AK		 603/*
604 * x86 defines three classes of vector instructions: explicitly
605 * aligned, explicitly unaligned, and the rest, which change behaviour
606 * depending on whether they're AVX encoded or not.
607 *
608 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
609 * subject to the same check.
610 */
611static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
612{
613 if (likely(size < 16))
614 return false;
615
616 if (ctxt->d & Aligned)
617 return true;
618 else if (ctxt->d & Unaligned)
619 return false;
620 else if (ctxt->d & Avx)
621 return false;
622 else
623 return true;
624}
625
3d9b938e 626static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 627 struct segmented_address addr,
3d9b938e 628 unsigned size, bool write, bool fetch,
52fd8b44
AK		 629 ulong *linear)
630{
618ff15d
AK		 631 struct desc_struct desc;
632 bool usable;
52fd8b44 633 ulong la;
618ff15d 634 u32 lim;
1aa36616 635 u16 sel;
3a78a4f4 636 unsigned cpl;
52fd8b44 637
7b105ca2 638 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 639 switch (ctxt->mode) {
618ff15d
AK		 640 case X86EMUL_MODE_PROT64:
641 if (((signed long)la << 16) >> 16 != la)
642 return emulate_gp(ctxt, 0);
643 break;
644 default:
1aa36616
AK		 645 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
646 addr.seg);
618ff15d
AK		 647 if (!usable)
648 goto bad;
58b7825b
GN		 649 /* code segment in protected mode or read-only data segment */
650 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
651 || !(desc.type & 2)) && write)
618ff15d
AK		 652 goto bad;
653 /* unreadable code segment */
3d9b938e 654 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 655 goto bad;
656 lim = desc_limit_scaled(&desc);
657 if ((desc.type & 8) || !(desc.type & 4)) {
658 /* expand-up segment */
659 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
660 goto bad;
661 } else {
fc058680 662 /* expand-down segment */
618ff15d
AK		 663 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
664 goto bad;
665 lim = desc.d ? 0xffffffff : 0xffff;
666 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
667 goto bad;
668 }
717746e3 669 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 670 if (!(desc.type & 8)) {
671 /* data segment */
672 if (cpl > desc.dpl)
673 goto bad;
674 } else if ((desc.type & 8) && !(desc.type & 4)) {
675 /* nonconforming code segment */
676 if (cpl != desc.dpl)
677 goto bad;
678 } else if ((desc.type & 8) && (desc.type & 4)) {
679 /* conforming code segment */
680 if (cpl < desc.dpl)
681 goto bad;
682 }
683 break;
684 }
9dac77fa 685 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 686 la &= (u32)-1;
1c11b376
AK		 687 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
688 return emulate_gp(ctxt, 0);
52fd8b44
AK		 689 *linear = la;
690 return X86EMUL_CONTINUE;
618ff15d
AK		 691bad:
692 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 693 return emulate_ss(ctxt, sel);
618ff15d 694 else
0afbe2f8 695 return emulate_gp(ctxt, sel);
52fd8b44
AK		 696}
697
3d9b938e
NE		 698static int linearize(struct x86_emulate_ctxt *ctxt,
699 struct segmented_address addr,
700 unsigned size, bool write,
701 ulong *linear)
702{
703 return __linearize(ctxt, addr, size, write, false, linear);
704}
705
706
3ca3ac4d
AK		 707static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
708 struct segmented_address addr,
709 void *data,
710 unsigned size)
711{
9fa088f4
AK		 712 int rc;
713 ulong linear;
714
83b8795a 715 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 716 if (rc != X86EMUL_CONTINUE)
717 return rc;
0f65dd70 718 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 719}
720
807941b1
TY		 721/*
722 * Fetch the next byte of the instruction being emulated which is pointed to
723 * by ctxt->_eip, then increment ctxt->_eip.
724 *
725 * Also prefetch the remaining bytes of the instruction without crossing page
726 * boundary if they are not in fetch_cache yet.
727 */
728static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 729{
9dac77fa 730 struct fetch_cache *fc = &ctxt->fetch;
62266869 731 int rc;
2fb53ad8 732 int size, cur_size;
62266869 733
807941b1 734 if (ctxt->_eip == fc->end) {
3d9b938e 735 unsigned long linear;
807941b1
TY		 736 struct segmented_address addr = { .seg = VCPU_SREG_CS,
737 .ea = ctxt->_eip };
2fb53ad8 738 cur_size = fc->end - fc->start;
807941b1
TY		 739 size = min(15UL - cur_size,
740 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 741 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 742 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 743 return rc;
ef5d75cc
TY		 744 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
745 size, &ctxt->exception);
7d88bb48 746 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 747 return rc;
2fb53ad8 748 fc->end += size;
62266869 749 }
807941b1
TY		 750 *dest = fc->data[ctxt->_eip - fc->start];
751 ctxt->_eip++;
3e2815e9 752 return X86EMUL_CONTINUE;
62266869
AK		 753}
754
755static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 756 void *dest, unsigned size)
62266869 757{
3e2815e9 758 int rc;
62266869 759
eb3c79e6 760 /* x86 instructions are limited to 15 bytes. */
7d88bb48 761 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 762 return X86EMUL_UNHANDLEABLE;
62266869 763 while (size--) {
807941b1 764 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 765 if (rc != X86EMUL_CONTINUE)
62266869
AK		 766 return rc;
767 }
3e2815e9 768 return X86EMUL_CONTINUE;
62266869
AK		 769}
770
67cbc90d 771/* Fetch next part of the instruction being emulated. */
e85a1085 772#define insn_fetch(_type, _ctxt) \
67cbc90d 773({ unsigned long _x; \
e85a1085 774 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 775 if (rc != X86EMUL_CONTINUE) \
776 goto done; \
67cbc90d
TY		 777 (_type)_x; \
778})
779
807941b1
TY		 780#define insn_fetch_arr(_arr, _size, _ctxt) \
781({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 782 if (rc != X86EMUL_CONTINUE) \
783 goto done; \
67cbc90d
TY		 784})
785
1e3c5cb0
RR		 786/*
787 * Given the 'reg' portion of a ModRM byte, and a register block, return a
788 * pointer into the block that addresses the relevant register.
789 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
790 */
dd856efa 791static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 792 int byteop)
6aa8b732
AK		 793{
794 void *p;
aa9ac1a6 795 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 796
6aa8b732 797 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 798 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
799 else
800 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 801 return p;
802}
803
804static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 805 struct segmented_address addr,
6aa8b732
AK		 806 u16 *size, unsigned long *address, int op_bytes)
807{
808 int rc;
809
810 if (op_bytes == 2)
811 op_bytes = 3;
812 *address = 0;
3ca3ac4d 813 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 814 if (rc != X86EMUL_CONTINUE)
6aa8b732 815 return rc;
30b31ab6 816 addr.ea += 2;
3ca3ac4d 817 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 818 return rc;
819}
820
34b77652
AK		 821FASTOP2(add);
822FASTOP2(or);
823FASTOP2(adc);
824FASTOP2(sbb);
825FASTOP2(and);
826FASTOP2(sub);
827FASTOP2(xor);
828FASTOP2(cmp);
829FASTOP2(test);
830
b9fa409b
AK		 831FASTOP1SRC2(mul, mul_ex);
832FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 833FASTOP1SRC2EX(div, div_ex);
834FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 835
34b77652
AK		 836FASTOP3WCL(shld);
837FASTOP3WCL(shrd);
838
839FASTOP2W(imul);
840
841FASTOP1(not);
842FASTOP1(neg);
843FASTOP1(inc);
844FASTOP1(dec);
845
846FASTOP2CL(rol);
847FASTOP2CL(ror);
848FASTOP2CL(rcl);
849FASTOP2CL(rcr);
850FASTOP2CL(shl);
851FASTOP2CL(shr);
852FASTOP2CL(sar);
853
854FASTOP2W(bsf);
855FASTOP2W(bsr);
856FASTOP2W(bt);
857FASTOP2W(bts);
858FASTOP2W(btr);
859FASTOP2W(btc);
860
e47a5f5f
AK		 861FASTOP2(xadd);
862
9ae9feba 863static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 864{
9ae9feba
AK		 865 u8 rc;
866 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 867
9ae9feba 868 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 869 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 870 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
871 return rc;
bbe9abbd
NK		 872}
873
91ff3cb4
AK		 874static void fetch_register_operand(struct operand *op)
875{
876 switch (op->bytes) {
877 case 1:
878 op->val = *(u8 *)op->addr.reg;
879 break;
880 case 2:
881 op->val = *(u16 *)op->addr.reg;
882 break;
883 case 4:
884 op->val = *(u32 *)op->addr.reg;
885 break;
886 case 8:
887 op->val = *(u64 *)op->addr.reg;
888 break;
889 }
890}
891
1253791d
AK		 892static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
893{
894 ctxt->ops->get_fpu(ctxt);
895 switch (reg) {
89a87c67
MK		 896 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
897 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
898 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
899 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
900 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
901 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
902 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
903 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 904#ifdef CONFIG_X86_64
89a87c67
MK		 905 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
906 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
907 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
908 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
909 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
910 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
911 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
912 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 913#endif
914 default: BUG();
915 }
916 ctxt->ops->put_fpu(ctxt);
917}
918
919static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
920 int reg)
921{
922 ctxt->ops->get_fpu(ctxt);
923 switch (reg) {
89a87c67
MK		 924 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
925 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
926 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
927 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
928 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
929 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
930 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
931 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 932#ifdef CONFIG_X86_64
89a87c67
MK		 933 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
934 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
935 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
936 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
937 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
938 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
939 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
940 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 941#endif
942 default: BUG();
943 }
944 ctxt->ops->put_fpu(ctxt);
945}
946
cbe2c9d3
AK		 947static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
948{
949 ctxt->ops->get_fpu(ctxt);
950 switch (reg) {
951 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
952 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
953 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
954 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
955 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
956 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
957 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
958 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
959 default: BUG();
960 }
961 ctxt->ops->put_fpu(ctxt);
962}
963
964static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
965{
966 ctxt->ops->get_fpu(ctxt);
967 switch (reg) {
968 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
969 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
970 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
971 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
972 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
973 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
974 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
975 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
976 default: BUG();
977 }
978 ctxt->ops->put_fpu(ctxt);
979}
980
045a282c
GN		 981static int em_fninit(struct x86_emulate_ctxt *ctxt)
982{
983 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
984 return emulate_nm(ctxt);
985
986 ctxt->ops->get_fpu(ctxt);
987 asm volatile("fninit");
988 ctxt->ops->put_fpu(ctxt);
989 return X86EMUL_CONTINUE;
990}
991
992static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
993{
994 u16 fcw;
995
996 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
997 return emulate_nm(ctxt);
998
999 ctxt->ops->get_fpu(ctxt);
1000 asm volatile("fnstcw %0": "+m"(fcw));
1001 ctxt->ops->put_fpu(ctxt);
1002
1003 /* force 2 byte destination */
1004 ctxt->dst.bytes = 2;
1005 ctxt->dst.val = fcw;
1006
1007 return X86EMUL_CONTINUE;
1008}
1009
1010static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1011{
1012 u16 fsw;
1013
1014 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1015 return emulate_nm(ctxt);
1016
1017 ctxt->ops->get_fpu(ctxt);
1018 asm volatile("fnstsw %0": "+m"(fsw));
1019 ctxt->ops->put_fpu(ctxt);
1020
1021 /* force 2 byte destination */
1022 ctxt->dst.bytes = 2;
1023 ctxt->dst.val = fsw;
1024
1025 return X86EMUL_CONTINUE;
1026}
1027
1253791d 1028static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1029 struct operand *op)
3c118e24 1030{
9dac77fa 1031 unsigned reg = ctxt->modrm_reg;
33615aa9 1032
9dac77fa
AK		 1033 if (!(ctxt->d & ModRM))
1034 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1035
9dac77fa 1036 if (ctxt->d & Sse) {
1253791d
AK		 1037 op->type = OP_XMM;
1038 op->bytes = 16;
1039 op->addr.xmm = reg;
1040 read_sse_reg(ctxt, &op->vec_val, reg);
1041 return;
1042 }
cbe2c9d3
AK		 1043 if (ctxt->d & Mmx) {
1044 reg &= 7;
1045 op->type = OP_MM;
1046 op->bytes = 8;
1047 op->addr.mm = reg;
1048 return;
1049 }
1253791d 1050
3c118e24 1051 op->type = OP_REG;
6d4d85ec
GN		 1052 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1053 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1054
91ff3cb4 1055 fetch_register_operand(op);
3c118e24
AK		 1056 op->orig_val = op->val;
1057}
1058
a6e3407b
AK		 1059static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1060{
1061 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1062 ctxt->modrm_seg = VCPU_SREG_SS;
1063}
1064
1c73ef66 1065static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1066 struct operand *op)
1c73ef66 1067{
1c73ef66 1068 u8 sib;
f5b4edcd 1069 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1070 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1071 ulong modrm_ea = 0;
1c73ef66 1072
9dac77fa
AK		 1073 if (ctxt->rex_prefix) {
1074 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1075 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1076 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1077 }
1078
9dac77fa
AK		 1079 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1080 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1081 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1082 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1083
9b88ae99 1084 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1085 op->type = OP_REG;
9dac77fa 1086 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1087 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1088 ctxt->d & ByteOp);
9dac77fa 1089 if (ctxt->d & Sse) {
1253791d
AK		 1090 op->type = OP_XMM;
1091 op->bytes = 16;
9dac77fa
AK		 1092 op->addr.xmm = ctxt->modrm_rm;
1093 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1094 return rc;
1095 }
cbe2c9d3
AK		 1096 if (ctxt->d & Mmx) {
1097 op->type = OP_MM;
1098 op->bytes = 8;
bdc90722 1099 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1100 return rc;
1101 }
2dbd0dd7 1102 fetch_register_operand(op);
1c73ef66
AK		 1103 return rc;
1104 }
1105
2dbd0dd7
AK		 1106 op->type = OP_MEM;
1107
9dac77fa 1108 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1109 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1110 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1111 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1112 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1113
1114 /* 16-bit ModR/M decode. */
9dac77fa 1115 switch (ctxt->modrm_mod) {
1c73ef66 1116 case 0:
9dac77fa 1117 if (ctxt->modrm_rm == 6)
e85a1085 1118 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1119 break;
1120 case 1:
e85a1085 1121 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1122 break;
1123 case 2:
e85a1085 1124 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1125 break;
1126 }
9dac77fa 1127 switch (ctxt->modrm_rm) {
1c73ef66 1128 case 0:
2dbd0dd7 1129 modrm_ea += bx + si;
1c73ef66
AK		 1130 break;
1131 case 1:
2dbd0dd7 1132 modrm_ea += bx + di;
1c73ef66
AK		 1133 break;
1134 case 2:
2dbd0dd7 1135 modrm_ea += bp + si;
1c73ef66
AK		 1136 break;
1137 case 3:
2dbd0dd7 1138 modrm_ea += bp + di;
1c73ef66
AK		 1139 break;
1140 case 4:
2dbd0dd7 1141 modrm_ea += si;
1c73ef66
AK		 1142 break;
1143 case 5:
2dbd0dd7 1144 modrm_ea += di;
1c73ef66
AK		 1145 break;
1146 case 6:
9dac77fa 1147 if (ctxt->modrm_mod != 0)
2dbd0dd7 1148 modrm_ea += bp;
1c73ef66
AK		 1149 break;
1150 case 7:
2dbd0dd7 1151 modrm_ea += bx;
1c73ef66
AK		 1152 break;
1153 }
9dac77fa
AK		 1154 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1155 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1156 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1157 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1158 } else {
1159 /* 32/64-bit ModR/M decode. */
9dac77fa 1160 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1161 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1162 index_reg |= (sib >> 3) & 7;
1163 base_reg |= sib & 7;
1164 scale = sib >> 6;
1165
9dac77fa 1166 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1167 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1168 else {
dd856efa 1169 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1170 adjust_modrm_seg(ctxt, base_reg);
1171 }
dc71d0f1 1172 if (index_reg != 4)
dd856efa 1173 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1174 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1175 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1176 ctxt->rip_relative = 1;
a6e3407b
AK		 1177 } else {
1178 base_reg = ctxt->modrm_rm;
dd856efa 1179 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1180 adjust_modrm_seg(ctxt, base_reg);
1181 }
9dac77fa 1182 switch (ctxt->modrm_mod) {
1c73ef66 1183 case 0:
9dac77fa 1184 if (ctxt->modrm_rm == 5)
e85a1085 1185 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1186 break;
1187 case 1:
e85a1085 1188 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1189 break;
1190 case 2:
e85a1085 1191 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1192 break;
1193 }
1194 }
90de84f5 1195 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1196done:
1197 return rc;
1198}
1199
1200static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1201 struct operand *op)
1c73ef66 1202{
3e2815e9 1203 int rc = X86EMUL_CONTINUE;
1c73ef66 1204
2dbd0dd7 1205 op->type = OP_MEM;
9dac77fa 1206 switch (ctxt->ad_bytes) {
1c73ef66 1207 case 2:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1209 break;
1210 case 4:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1212 break;
1213 case 8:
e85a1085 1214 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1215 break;
1216 }
1217done:
1218 return rc;
1219}
1220
9dac77fa 1221static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1222{
7129eeca 1223 long sv = 0, mask;
35c843c4 1224
9dac77fa 1225 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1226 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1227
9dac77fa
AK		 1228 if (ctxt->src.bytes == 2)
1229 sv = (s16)ctxt->src.val & (s16)mask;
1230 else if (ctxt->src.bytes == 4)
1231 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1232 else
1233 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1234
9dac77fa 1235 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1236 }
ba7ff2b7
WY		 1237
1238 /* only subword offset */
9dac77fa 1239 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1240}
1241
dde7e6d1 1242static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1243 unsigned long addr, void *dest, unsigned size)
6aa8b732 1244{
dde7e6d1 1245 int rc;
9dac77fa 1246 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1247
f23b070e
XG		 1248 if (mc->pos < mc->end)
1249 goto read_cached;
6aa8b732 1250
f23b070e
XG		 1251 WARN_ON((mc->end + size) >= sizeof(mc->data));
1252
1253 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1254 &ctxt->exception);
1255 if (rc != X86EMUL_CONTINUE)
1256 return rc;
1257
1258 mc->end += size;
1259
1260read_cached:
1261 memcpy(dest, mc->data + mc->pos, size);
1262 mc->pos += size;
dde7e6d1
AK		 1263 return X86EMUL_CONTINUE;
1264}
6aa8b732 1265
3ca3ac4d
AK		 1266static int segmented_read(struct x86_emulate_ctxt *ctxt,
1267 struct segmented_address addr,
1268 void *data,
1269 unsigned size)
1270{
9fa088f4
AK		 1271 int rc;
1272 ulong linear;
1273
83b8795a 1274 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
7b105ca2 1277 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1278}
1279
1280static int segmented_write(struct x86_emulate_ctxt *ctxt,
1281 struct segmented_address addr,
1282 const void *data,
1283 unsigned size)
1284{
9fa088f4
AK		 1285 int rc;
1286 ulong linear;
1287
83b8795a 1288 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1289 if (rc != X86EMUL_CONTINUE)
1290 return rc;
0f65dd70
AK		 1291 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1292 &ctxt->exception);
3ca3ac4d
AK		 1293}
1294
1295static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1296 struct segmented_address addr,
1297 const void *orig_data, const void *data,
1298 unsigned size)
1299{
9fa088f4
AK		 1300 int rc;
1301 ulong linear;
1302
83b8795a 1303 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1304 if (rc != X86EMUL_CONTINUE)
1305 return rc;
0f65dd70
AK		 1306 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1307 size, &ctxt->exception);
3ca3ac4d
AK		 1308}
1309
dde7e6d1 1310static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1311 unsigned int size, unsigned short port,
1312 void *dest)
1313{
9dac77fa 1314 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1315
dde7e6d1 1316 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1317 unsigned int in_page, n;
9dac77fa 1318 unsigned int count = ctxt->rep_prefix ?
dd856efa 1319 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1320 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1321 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1322 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1323 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1324 count);
1325 if (n == 0)
1326 n = 1;
1327 rc->pos = rc->end = 0;
7b105ca2 1328 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1329 return 0;
1330 rc->end = n * size;
6aa8b732
AK		 1331 }
1332
e6e39f04
NA		 1333 if (ctxt->rep_prefix && (ctxt->d & String) &&
1334 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1335 ctxt->dst.data = rc->data + rc->pos;
1336 ctxt->dst.type = OP_MEM_STR;
1337 ctxt->dst.count = (rc->end - rc->pos) / size;
1338 rc->pos = rc->end;
1339 } else {
1340 memcpy(dest, rc->data + rc->pos, size);
1341 rc->pos += size;
1342 }
dde7e6d1
AK		 1343 return 1;
1344}
6aa8b732 1345
7f3d35fd
KW		 1346static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1347 u16 index, struct desc_struct *desc)
1348{
1349 struct desc_ptr dt;
1350 ulong addr;
1351
1352 ctxt->ops->get_idt(ctxt, &dt);
1353
1354 if (dt.size < index * 8 + 7)
1355 return emulate_gp(ctxt, index << 3 | 0x2);
1356
1357 addr = dt.address + index * 8;
1358 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1359 &ctxt->exception);
1360}
1361
dde7e6d1 1362static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1363 u16 selector, struct desc_ptr *dt)
1364{
0225fb50 1365 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1366 u32 base3 = 0;
7b105ca2 1367
dde7e6d1
AK		 1368 if (selector & 1 << 2) {
1369 struct desc_struct desc;
1aa36616
AK		 1370 u16 sel;
1371
dde7e6d1 1372 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1373 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1374 VCPU_SREG_LDTR))
dde7e6d1 1375 return;
e09d082c 1376
dde7e6d1 1377 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1378 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1379 } else
4bff1e86 1380 ops->get_gdt(ctxt, dt);
dde7e6d1 1381}
120df890 1382
dde7e6d1
AK		 1383/* allowed just for 8 bytes segments */
1384static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1385 u16 selector, struct desc_struct *desc,
1386 ulong *desc_addr_p)
dde7e6d1
AK		 1387{
1388 struct desc_ptr dt;
1389 u16 index = selector >> 3;
dde7e6d1 1390 ulong addr;
120df890 1391
7b105ca2 1392 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1393
35d3d4a1
AK		 1394 if (dt.size < index * 8 + 7)
1395 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1396
e919464b 1397 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1398 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1399 &ctxt->exception);
dde7e6d1 1400}
ef65c889 1401
dde7e6d1
AK		 1402/* allowed just for 8 bytes segments */
1403static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1404 u16 selector, struct desc_struct *desc)
1405{
1406 struct desc_ptr dt;
1407 u16 index = selector >> 3;
dde7e6d1 1408 ulong addr;
6aa8b732 1409
7b105ca2 1410 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1411
35d3d4a1
AK		 1412 if (dt.size < index * 8 + 7)
1413 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1414
dde7e6d1 1415 addr = dt.address + index * 8;
7b105ca2
TY		 1416 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1417 &ctxt->exception);
dde7e6d1 1418}
c7e75a3d 1419
5601d05b 1420/* Does not support long mode */
2356aaeb 1421static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1422 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1423{
869be99c 1424 struct desc_struct seg_desc, old_desc;
2356aaeb 1425 u8 dpl, rpl;
dde7e6d1
AK		 1426 unsigned err_vec = GP_VECTOR;
1427 u32 err_code = 0;
1428 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1429 ulong desc_addr;
dde7e6d1 1430 int ret;
03ebebeb 1431 u16 dummy;
e37a75a1 1432 u32 base3 = 0;
69f55cb1 1433
dde7e6d1 1434 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1435
f8da94e9
KW		 1436 if (ctxt->mode == X86EMUL_MODE_REAL) {
1437 /* set real mode segment descriptor (keep limit etc. for
1438 * unreal mode) */
03ebebeb 1439 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1440 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1441 goto load;
f8da94e9
KW		 1442 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1443 /* VM86 needs a clean new segment descriptor */
1444 set_desc_base(&seg_desc, selector << 4);
1445 set_desc_limit(&seg_desc, 0xffff);
1446 seg_desc.type = 3;
1447 seg_desc.p = 1;
1448 seg_desc.s = 1;
1449 seg_desc.dpl = 3;
1450 goto load;
dde7e6d1
AK		 1451 }
1452
79d5b4c3 1453 rpl = selector & 3;
79d5b4c3
AK		 1454
1455 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1456 if ((seg == VCPU_SREG_CS
1457 || (seg == VCPU_SREG_SS
1458 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1459 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1460 && null_selector)
1461 goto exception;
1462
1463 /* TR should be in GDT only */
1464 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1465 goto exception;
1466
1467 if (null_selector) /* for NULL selector skip all following checks */
1468 goto load;
1469
e919464b 1470 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1471 if (ret != X86EMUL_CONTINUE)
1472 return ret;
1473
1474 err_code = selector & 0xfffc;
1475 err_vec = GP_VECTOR;
1476
fc058680 1477 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1478 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1479 goto exception;
1480
1481 if (!seg_desc.p) {
1482 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1483 goto exception;
1484 }
1485
dde7e6d1 1486 dpl = seg_desc.dpl;
dde7e6d1
AK		 1487
1488 switch (seg) {
1489 case VCPU_SREG_SS:
1490 /*
1491 * segment is not a writable data segment or segment
1492 * selector's RPL != CPL or segment selector's RPL != CPL
1493 */
1494 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1495 goto exception;
6aa8b732 1496 break;
dde7e6d1 1497 case VCPU_SREG_CS:
5045b468
PB		 1498 if (in_task_switch && rpl != dpl)
1499 goto exception;
1500
dde7e6d1
AK		 1501 if (!(seg_desc.type & 8))
1502 goto exception;
1503
1504 if (seg_desc.type & 4) {
1505 /* conforming */
1506 if (dpl > cpl)
1507 goto exception;
1508 } else {
1509 /* nonconforming */
1510 if (rpl > cpl || dpl != cpl)
1511 goto exception;
1512 }
1513 /* CS(RPL) <- CPL */
1514 selector = (selector & 0xfffc) | cpl;
6aa8b732 1515 break;
dde7e6d1
AK		 1516 case VCPU_SREG_TR:
1517 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1518 goto exception;
869be99c
AK		 1519 old_desc = seg_desc;
1520 seg_desc.type |= 2; /* busy */
1521 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1522 sizeof(seg_desc), &ctxt->exception);
1523 if (ret != X86EMUL_CONTINUE)
1524 return ret;
dde7e6d1
AK		 1525 break;
1526 case VCPU_SREG_LDTR:
1527 if (seg_desc.s || seg_desc.type != 2)
1528 goto exception;
1529 break;
1530 default: /* DS, ES, FS, or GS */
4e62417b 1531 /*
dde7e6d1
AK		 1532 * segment is not a data or readable code segment or
1533 * ((segment is a data or nonconforming code segment)
1534 * and (both RPL and CPL > DPL))
4e62417b 1535 */
dde7e6d1
AK		 1536 if ((seg_desc.type & 0xa) == 0x8 ||
1537 (((seg_desc.type & 0xc) != 0xc) &&
1538 (rpl > dpl && cpl > dpl)))
1539 goto exception;
6aa8b732 1540 break;
dde7e6d1
AK		 1541 }
1542
1543 if (seg_desc.s) {
1544 /* mark segment as accessed */
1545 seg_desc.type |= 1;
7b105ca2 1546 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1547 if (ret != X86EMUL_CONTINUE)
1548 return ret;
e37a75a1
NA		 1549 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1550 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1551 sizeof(base3), &ctxt->exception);
1552 if (ret != X86EMUL_CONTINUE)
1553 return ret;
dde7e6d1
AK		 1554 }
1555load:
e37a75a1 1556 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1557 return X86EMUL_CONTINUE;
1558exception:
1559 emulate_exception(ctxt, err_vec, err_code, true);
1560 return X86EMUL_PROPAGATE_FAULT;
1561}
1562
2356aaeb
PB		 1563static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1564 u16 selector, int seg)
1565{
1566 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1567 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1568}
1569
31be40b3
WY		 1570static void write_register_operand(struct operand *op)
1571{
1572 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1573 switch (op->bytes) {
1574 case 1:
1575 *(u8 *)op->addr.reg = (u8)op->val;
1576 break;
1577 case 2:
1578 *(u16 *)op->addr.reg = (u16)op->val;
1579 break;
1580 case 4:
1581 *op->addr.reg = (u32)op->val;
1582 break; /* 64b: zero-extend */
1583 case 8:
1584 *op->addr.reg = op->val;
1585 break;
1586 }
1587}
1588
fb32b1ed 1589static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1590{
1591 int rc;
dde7e6d1 1592
fb32b1ed 1593 switch (op->type) {
dde7e6d1 1594 case OP_REG:
fb32b1ed 1595 write_register_operand(op);
6aa8b732 1596 break;
dde7e6d1 1597 case OP_MEM:
9dac77fa 1598 if (ctxt->lock_prefix)
3ca3ac4d 1599 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1600 op->addr.mem,
1601 &op->orig_val,
1602 &op->val,
1603 op->bytes);
341de7e3 1604 else
3ca3ac4d 1605 rc = segmented_write(ctxt,
fb32b1ed
AK		 1606 op->addr.mem,
1607 &op->val,
1608 op->bytes);
dde7e6d1
AK		 1609 if (rc != X86EMUL_CONTINUE)
1610 return rc;
a682e354 1611 break;
b3356bf0
GN		 1612 case OP_MEM_STR:
1613 rc = segmented_write(ctxt,
fb32b1ed
AK		 1614 op->addr.mem,
1615 op->data,
1616 op->bytes * op->count);
b3356bf0
GN		 1617 if (rc != X86EMUL_CONTINUE)
1618 return rc;
1619 break;
1253791d 1620 case OP_XMM:
fb32b1ed 1621 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1622 break;
cbe2c9d3 1623 case OP_MM:
fb32b1ed 1624 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1625 break;
dde7e6d1
AK		 1626 case OP_NONE:
1627 /* no writeback */
414e6277 1628 break;
dde7e6d1 1629 default:
414e6277 1630 break;
6aa8b732 1631 }
dde7e6d1
AK		 1632 return X86EMUL_CONTINUE;
1633}
6aa8b732 1634
51ddff50 1635static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1636{
4179bb02 1637 struct segmented_address addr;
0dc8d10f 1638
5ad105e5 1639 rsp_increment(ctxt, -bytes);
dd856efa 1640 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1641 addr.seg = VCPU_SREG_SS;
1642
51ddff50
AK		 1643 return segmented_write(ctxt, addr, data, bytes);
1644}
1645
1646static int em_push(struct x86_emulate_ctxt *ctxt)
1647{
4179bb02 1648 /* Disable writeback. */
9dac77fa 1649 ctxt->dst.type = OP_NONE;
51ddff50 1650 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1651}
69f55cb1 1652
dde7e6d1 1653static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1654 void *dest, int len)
1655{
dde7e6d1 1656 int rc;
90de84f5 1657 struct segmented_address addr;
8b4caf66 1658
dd856efa 1659 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1660 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1661 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1662 if (rc != X86EMUL_CONTINUE)
1663 return rc;
1664
5ad105e5 1665 rsp_increment(ctxt, len);
dde7e6d1 1666 return rc;
8b4caf66
LV		 1667}
1668
c54fe504
TY		 1669static int em_pop(struct x86_emulate_ctxt *ctxt)
1670{
9dac77fa 1671 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1672}
1673
dde7e6d1 1674static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1675 void *dest, int len)
9de41573
GN		 1676{
1677 int rc;
dde7e6d1
AK		 1678 unsigned long val, change_mask;
1679 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1680 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1681
3b9be3bf 1682 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1683 if (rc != X86EMUL_CONTINUE)
1684 return rc;
9de41573 1685
dde7e6d1
AK		 1686 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1687 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1688
dde7e6d1
AK		 1689 switch(ctxt->mode) {
1690 case X86EMUL_MODE_PROT64:
1691 case X86EMUL_MODE_PROT32:
1692 case X86EMUL_MODE_PROT16:
1693 if (cpl == 0)
1694 change_mask |= EFLG_IOPL;
1695 if (cpl <= iopl)
1696 change_mask |= EFLG_IF;
1697 break;
1698 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1699 if (iopl < 3)
1700 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1701 change_mask |= EFLG_IF;
1702 break;
1703 default: /* real mode */
1704 change_mask |= (EFLG_IOPL | EFLG_IF);
1705 break;
9de41573 1706 }
dde7e6d1
AK		 1707
1708 *(unsigned long *)dest =
1709 (ctxt->eflags & ~change_mask) | (val & change_mask);
1710
1711 return rc;
9de41573
GN		 1712}
1713
62aaa2f0
TY		 1714static int em_popf(struct x86_emulate_ctxt *ctxt)
1715{
9dac77fa
AK		 1716 ctxt->dst.type = OP_REG;
1717 ctxt->dst.addr.reg = &ctxt->eflags;
1718 ctxt->dst.bytes = ctxt->op_bytes;
1719 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1720}
1721
612e89f0
AK		 1722static int em_enter(struct x86_emulate_ctxt *ctxt)
1723{
1724 int rc;
1725 unsigned frame_size = ctxt->src.val;
1726 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1727 ulong rbp;
612e89f0
AK		 1728
1729 if (nesting_level)
1730 return X86EMUL_UNHANDLEABLE;
1731
dd856efa
AK		 1732 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1733 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1734 if (rc != X86EMUL_CONTINUE)
1735 return rc;
dd856efa 1736 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1737 stack_mask(ctxt));
dd856efa
AK		 1738 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1739 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1740 stack_mask(ctxt));
1741 return X86EMUL_CONTINUE;
1742}
1743
f47cfa31
AK		 1744static int em_leave(struct x86_emulate_ctxt *ctxt)
1745{
dd856efa 1746 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1747 stack_mask(ctxt));
dd856efa 1748 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1749}
1750
1cd196ea 1751static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1752{
1cd196ea
AK		 1753 int seg = ctxt->src2.val;
1754
9dac77fa 1755 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1756
4487b3b4 1757 return em_push(ctxt);
7b262e90
GN		 1758}
1759
1cd196ea 1760static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1761{
1cd196ea 1762 int seg = ctxt->src2.val;
dde7e6d1
AK		 1763 unsigned long selector;
1764 int rc;
38ba30ba 1765
9dac77fa 1766 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1767 if (rc != X86EMUL_CONTINUE)
1768 return rc;
1769
a5457e7b
PB		 1770 if (ctxt->modrm_reg == VCPU_SREG_SS)
1771 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1772
7b105ca2 1773 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1774 return rc;
38ba30ba
GN		 1775}
1776
b96a7fad 1777static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1778{
dd856efa 1779 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1780 int rc = X86EMUL_CONTINUE;
1781 int reg = VCPU_REGS_RAX;
38ba30ba 1782
dde7e6d1
AK		 1783 while (reg <= VCPU_REGS_RDI) {
1784 (reg == VCPU_REGS_RSP) ?
dd856efa 1785 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1786
4487b3b4 1787 rc = em_push(ctxt);
dde7e6d1
AK		 1788 if (rc != X86EMUL_CONTINUE)
1789 return rc;
38ba30ba 1790
dde7e6d1 1791 ++reg;
38ba30ba 1792 }
38ba30ba 1793
dde7e6d1 1794 return rc;
38ba30ba
GN		 1795}
1796
62aaa2f0
TY		 1797static int em_pushf(struct x86_emulate_ctxt *ctxt)
1798{
9dac77fa 1799 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1800 return em_push(ctxt);
1801}
1802
b96a7fad 1803static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1804{
dde7e6d1
AK		 1805 int rc = X86EMUL_CONTINUE;
1806 int reg = VCPU_REGS_RDI;
38ba30ba 1807
dde7e6d1
AK		 1808 while (reg >= VCPU_REGS_RAX) {
1809 if (reg == VCPU_REGS_RSP) {
5ad105e5 1810 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1811 --reg;
1812 }
38ba30ba 1813
dd856efa 1814 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1815 if (rc != X86EMUL_CONTINUE)
1816 break;
1817 --reg;
38ba30ba 1818 }
dde7e6d1 1819 return rc;
38ba30ba
GN		 1820}
1821
dd856efa 1822static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1823{
0225fb50 1824 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1825 int rc;
6e154e56
MG		 1826 struct desc_ptr dt;
1827 gva_t cs_addr;
1828 gva_t eip_addr;
1829 u16 cs, eip;
6e154e56
MG		 1830
1831 /* TODO: Add limit checks */
9dac77fa 1832 ctxt->src.val = ctxt->eflags;
4487b3b4 1833 rc = em_push(ctxt);
5c56e1cf
AK		 1834 if (rc != X86EMUL_CONTINUE)
1835 return rc;
6e154e56
MG		 1836
1837 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1838
9dac77fa 1839 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1840 rc = em_push(ctxt);
5c56e1cf
AK		 1841 if (rc != X86EMUL_CONTINUE)
1842 return rc;
6e154e56 1843
9dac77fa 1844 ctxt->src.val = ctxt->_eip;
4487b3b4 1845 rc = em_push(ctxt);
5c56e1cf
AK		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
4bff1e86 1849 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1850
1851 eip_addr = dt.address + (irq << 2);
1852 cs_addr = dt.address + (irq << 2) + 2;
1853
0f65dd70 1854 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
1857
0f65dd70 1858 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1859 if (rc != X86EMUL_CONTINUE)
1860 return rc;
1861
7b105ca2 1862 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1863 if (rc != X86EMUL_CONTINUE)
1864 return rc;
1865
9dac77fa 1866 ctxt->_eip = eip;
6e154e56
MG		 1867
1868 return rc;
1869}
1870
dd856efa
AK		 1871int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1872{
1873 int rc;
1874
1875 invalidate_registers(ctxt);
1876 rc = __emulate_int_real(ctxt, irq);
1877 if (rc == X86EMUL_CONTINUE)
1878 writeback_registers(ctxt);
1879 return rc;
1880}
1881
7b105ca2 1882static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1883{
1884 switch(ctxt->mode) {
1885 case X86EMUL_MODE_REAL:
dd856efa 1886 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1887 case X86EMUL_MODE_VM86:
1888 case X86EMUL_MODE_PROT16:
1889 case X86EMUL_MODE_PROT32:
1890 case X86EMUL_MODE_PROT64:
1891 default:
1892 /* Protected mode interrupts unimplemented yet */
1893 return X86EMUL_UNHANDLEABLE;
1894 }
1895}
1896
7b105ca2 1897static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1898{
dde7e6d1
AK		 1899 int rc = X86EMUL_CONTINUE;
1900 unsigned long temp_eip = 0;
1901 unsigned long temp_eflags = 0;
1902 unsigned long cs = 0;
1903 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1904 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1905 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1906 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1907
dde7e6d1 1908 /* TODO: Add stack limit check */
38ba30ba 1909
9dac77fa 1910 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1911
dde7e6d1
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
38ba30ba 1914
35d3d4a1
AK		 1915 if (temp_eip & ~0xffff)
1916 return emulate_gp(ctxt, 0);
38ba30ba 1917
9dac77fa 1918 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1919
dde7e6d1
AK		 1920 if (rc != X86EMUL_CONTINUE)
1921 return rc;
38ba30ba 1922
9dac77fa 1923 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1924
dde7e6d1
AK		 1925 if (rc != X86EMUL_CONTINUE)
1926 return rc;
38ba30ba 1927
7b105ca2 1928 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1929
dde7e6d1
AK		 1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
38ba30ba 1932
9dac77fa 1933 ctxt->_eip = temp_eip;
38ba30ba 1934
38ba30ba 1935
9dac77fa 1936 if (ctxt->op_bytes == 4)
dde7e6d1 1937 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1938 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1939 ctxt->eflags &= ~0xffff;
1940 ctxt->eflags |= temp_eflags;
38ba30ba 1941 }
dde7e6d1
AK		 1942
1943 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1944 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1945
1946 return rc;
38ba30ba
GN		 1947}
1948
e01991e7 1949static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1950{
dde7e6d1
AK		 1951 switch(ctxt->mode) {
1952 case X86EMUL_MODE_REAL:
7b105ca2 1953 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1954 case X86EMUL_MODE_VM86:
1955 case X86EMUL_MODE_PROT16:
1956 case X86EMUL_MODE_PROT32:
1957 case X86EMUL_MODE_PROT64:
c37eda13 1958 default:
dde7e6d1
AK		 1959 /* iret from protected mode unimplemented yet */
1960 return X86EMUL_UNHANDLEABLE;
c37eda13 1961 }
c37eda13
WY		 1962}
1963
d2f62766
TY		 1964static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1965{
d2f62766
TY		 1966 int rc;
1967 unsigned short sel;
1968
9dac77fa 1969 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1970
7b105ca2 1971 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1972 if (rc != X86EMUL_CONTINUE)
1973 return rc;
1974
9dac77fa
AK		 1975 ctxt->_eip = 0;
1976 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1977 return X86EMUL_CONTINUE;
1978}
1979
51187683 1980static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1981{
4179bb02 1982 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1983
9dac77fa 1984 switch (ctxt->modrm_reg) {
d19292e4
MG		 1985 case 2: /* call near abs */ {
1986 long int old_eip;
9dac77fa
AK		 1987 old_eip = ctxt->_eip;
1988 ctxt->_eip = ctxt->src.val;
1989 ctxt->src.val = old_eip;
4487b3b4 1990 rc = em_push(ctxt);
d19292e4
MG		 1991 break;
1992 }
8cdbd2c9 1993 case 4: /* jmp abs */
9dac77fa 1994 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1995 break;
d2f62766
TY		 1996 case 5: /* jmp far */
1997 rc = em_jmp_far(ctxt);
1998 break;
8cdbd2c9 1999 case 6: /* push */
4487b3b4 2000 rc = em_push(ctxt);
8cdbd2c9 2001 break;
8cdbd2c9 2002 }
4179bb02 2003 return rc;
8cdbd2c9
LV		 2004}
2005
e0dac408 2006static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2007{
9dac77fa 2008 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2009
aaa05f24
NA		 2010 if (ctxt->dst.bytes == 16)
2011 return X86EMUL_UNHANDLEABLE;
2012
dd856efa
AK		 2013 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2014 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2015 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2016 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2017 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2018 } else {
dd856efa
AK		 2019 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2020 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2021
05f086f8 2022 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2023 }
1b30eaa8 2024 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2025}
2026
ebda02c2
TY		 2027static int em_ret(struct x86_emulate_ctxt *ctxt)
2028{
9dac77fa
AK		 2029 ctxt->dst.type = OP_REG;
2030 ctxt->dst.addr.reg = &ctxt->_eip;
2031 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2032 return em_pop(ctxt);
2033}
2034
e01991e7 2035static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2036{
a77ab5ea
AK		 2037 int rc;
2038 unsigned long cs;
9e8919ae 2039 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2040
9dac77fa 2041 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2042 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2043 return rc;
9dac77fa
AK		 2044 if (ctxt->op_bytes == 4)
2045 ctxt->_eip = (u32)ctxt->_eip;
2046 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2047 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2048 return rc;
9e8919ae
NA		 2049 /* Outer-privilege level return is not implemented */
2050 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2051 return X86EMUL_UNHANDLEABLE;
7b105ca2 2052 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2053 return rc;
2054}
2055
3261107e
BR		 2056static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2057{
2058 int rc;
2059
2060 rc = em_ret_far(ctxt);
2061 if (rc != X86EMUL_CONTINUE)
2062 return rc;
2063 rsp_increment(ctxt, ctxt->src.val);
2064 return X86EMUL_CONTINUE;
2065}
2066
e940b5c2
TY		 2067static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2068{
2069 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2070 ctxt->dst.orig_val = ctxt->dst.val;
2071 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2072 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2073 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2074 fastop(ctxt, em_cmp);
e940b5c2
TY		 2075
2076 if (ctxt->eflags & EFLG_ZF) {
2077 /* Success: write back to memory. */
2078 ctxt->dst.val = ctxt->src.orig_val;
2079 } else {
2080 /* Failure: write the value we saw to EAX. */
2081 ctxt->dst.type = OP_REG;
dd856efa 2082 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2083 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2084 }
2085 return X86EMUL_CONTINUE;
2086}
2087
d4b4325f 2088static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2089{
d4b4325f 2090 int seg = ctxt->src2.val;
09b5f4d3
WY		 2091 unsigned short sel;
2092 int rc;
2093
9dac77fa 2094 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2095
7b105ca2 2096 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2097 if (rc != X86EMUL_CONTINUE)
2098 return rc;
2099
9dac77fa 2100 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2101 return rc;
2102}
2103
7b105ca2 2104static void
e66bb2cc 2105setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2106 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2107{
e66bb2cc 2108 cs->l = 0; /* will be adjusted later */
79168fd1 2109 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2110 cs->g = 1; /* 4kb granularity */
79168fd1 2111 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2112 cs->type = 0x0b; /* Read, Execute, Accessed */
2113 cs->s = 1;
2114 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2115 cs->p = 1;
2116 cs->d = 1;
99245b50 2117 cs->avl = 0;
e66bb2cc 2118
79168fd1
GN		 2119 set_desc_base(ss, 0); /* flat segment */
2120 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2121 ss->g = 1; /* 4kb granularity */
2122 ss->s = 1;
2123 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2124 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2125 ss->dpl = 0;
79168fd1 2126 ss->p = 1;
99245b50
GN		 2127 ss->l = 0;
2128 ss->avl = 0;
e66bb2cc
AP		 2129}
2130
1a18a69b
AK		 2131static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2132{
2133 u32 eax, ebx, ecx, edx;
2134
2135 eax = ecx = 0;
0017f93a
AK		 2136 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2137 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2138 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2139 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2140}
2141
c2226fc9
SB		 2142static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2143{
0225fb50 2144 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2145 u32 eax, ebx, ecx, edx;
2146
2147 /*
2148 * syscall should always be enabled in longmode - so only become
2149 * vendor specific (cpuid) if other modes are active...
2150 */
2151 if (ctxt->mode == X86EMUL_MODE_PROT64)
2152 return true;
2153
2154 eax = 0x00000000;
2155 ecx = 0x00000000;
0017f93a
AK		 2156 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2157 /*
2158 * Intel ("GenuineIntel")
2159 * remark: Intel CPUs only support "syscall" in 64bit
2160 * longmode. Also an 64bit guest with a
2161 * 32bit compat-app running will #UD !! While this
2162 * behaviour can be fixed (by emulating) into AMD
2163 * response - CPUs of AMD can't behave like Intel.
2164 */
2165 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2166 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2167 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2168 return false;
2169
2170 /* AMD ("AuthenticAMD") */
2171 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2172 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2173 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2174 return true;
2175
2176 /* AMD ("AMDisbetter!") */
2177 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2178 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2179 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2180 return true;
c2226fc9
SB		 2181
2182 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2183 return false;
2184}
2185
e01991e7 2186static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2187{
0225fb50 2188 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2189 struct desc_struct cs, ss;
e66bb2cc 2190 u64 msr_data;
79168fd1 2191 u16 cs_sel, ss_sel;
c2ad2bb3 2192 u64 efer = 0;
e66bb2cc
AP		 2193
2194 /* syscall is not available in real mode */
2e901c4c 2195 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2196 ctxt->mode == X86EMUL_MODE_VM86)
2197 return emulate_ud(ctxt);
e66bb2cc 2198
c2226fc9
SB		 2199 if (!(em_syscall_is_enabled(ctxt)))
2200 return emulate_ud(ctxt);
2201
c2ad2bb3 2202 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2203 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2204
c2226fc9
SB		 2205 if (!(efer & EFER_SCE))
2206 return emulate_ud(ctxt);
2207
717746e3 2208 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2209 msr_data >>= 32;
79168fd1
GN		 2210 cs_sel = (u16)(msr_data & 0xfffc);
2211 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2212
c2ad2bb3 2213 if (efer & EFER_LMA) {
79168fd1 2214 cs.d = 0;
e66bb2cc
AP		 2215 cs.l = 1;
2216 }
1aa36616
AK		 2217 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2218 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2219
dd856efa 2220 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2221 if (efer & EFER_LMA) {
e66bb2cc 2222#ifdef CONFIG_X86_64
dd856efa 2223 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2224
717746e3 2225 ops->get_msr(ctxt,
3fb1b5db
GN		 2226 ctxt->mode == X86EMUL_MODE_PROT64 ?
2227 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2228 ctxt->_eip = msr_data;
e66bb2cc 2229
717746e3 2230 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2231 ctxt->eflags &= ~(msr_data | EFLG_RF);
2232#endif
2233 } else {
2234 /* legacy mode */
717746e3 2235 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2236 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2237
2238 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2239 }
2240
e54cfa97 2241 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2242}
2243
e01991e7 2244static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2245{
0225fb50 2246 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2247 struct desc_struct cs, ss;
8c604352 2248 u64 msr_data;
79168fd1 2249 u16 cs_sel, ss_sel;
c2ad2bb3 2250 u64 efer = 0;
8c604352 2251
7b105ca2 2252 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2253 /* inject #GP if in real mode */
35d3d4a1
AK		 2254 if (ctxt->mode == X86EMUL_MODE_REAL)
2255 return emulate_gp(ctxt, 0);
8c604352 2256
1a18a69b
AK		 2257 /*
2258 * Not recognized on AMD in compat mode (but is recognized in legacy
2259 * mode).
2260 */
2261 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2262 && !vendor_intel(ctxt))
2263 return emulate_ud(ctxt);
2264
8c604352
AP		 2265 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2266 * Therefore, we inject an #UD.
2267 */
35d3d4a1
AK		 2268 if (ctxt->mode == X86EMUL_MODE_PROT64)
2269 return emulate_ud(ctxt);
8c604352 2270
7b105ca2 2271 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2272
717746e3 2273 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2274 switch (ctxt->mode) {
2275 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2276 if ((msr_data & 0xfffc) == 0x0)
2277 return emulate_gp(ctxt, 0);
8c604352
AP		 2278 break;
2279 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2280 if (msr_data == 0x0)
2281 return emulate_gp(ctxt, 0);
8c604352 2282 break;
9d1b39a9
GN		 2283 default:
2284 break;
8c604352
AP		 2285 }
2286
2287 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2288 cs_sel = (u16)msr_data;
2289 cs_sel &= ~SELECTOR_RPL_MASK;
2290 ss_sel = cs_sel + 8;
2291 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2292 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2293 cs.d = 0;
8c604352
AP		 2294 cs.l = 1;
2295 }
2296
1aa36616
AK		 2297 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2298 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2299
717746e3 2300 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2301 ctxt->_eip = msr_data;
8c604352 2302
717746e3 2303 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2304 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2305
e54cfa97 2306 return X86EMUL_CONTINUE;
8c604352
AP		 2307}
2308
e01991e7 2309static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2310{
0225fb50 2311 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2312 struct desc_struct cs, ss;
4668f050
AP		 2313 u64 msr_data;
2314 int usermode;
1249b96e 2315 u16 cs_sel = 0, ss_sel = 0;
4668f050 2316
a0044755
GN		 2317 /* inject #GP if in real mode or Virtual 8086 mode */
2318 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2319 ctxt->mode == X86EMUL_MODE_VM86)
2320 return emulate_gp(ctxt, 0);
4668f050 2321
7b105ca2 2322 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2323
9dac77fa 2324 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2325 usermode = X86EMUL_MODE_PROT64;
2326 else
2327 usermode = X86EMUL_MODE_PROT32;
2328
2329 cs.dpl = 3;
2330 ss.dpl = 3;
717746e3 2331 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2332 switch (usermode) {
2333 case X86EMUL_MODE_PROT32:
79168fd1 2334 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2335 if ((msr_data & 0xfffc) == 0x0)
2336 return emulate_gp(ctxt, 0);
79168fd1 2337 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2338 break;
2339 case X86EMUL_MODE_PROT64:
79168fd1 2340 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2341 if (msr_data == 0x0)
2342 return emulate_gp(ctxt, 0);
79168fd1
GN		 2343 ss_sel = cs_sel + 8;
2344 cs.d = 0;
4668f050
AP		 2345 cs.l = 1;
2346 break;
2347 }
79168fd1
GN		 2348 cs_sel |= SELECTOR_RPL_MASK;
2349 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2350
1aa36616
AK		 2351 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2352 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2353
dd856efa
AK		 2354 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2355 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2356
e54cfa97 2357 return X86EMUL_CONTINUE;
4668f050
AP		 2358}
2359
7b105ca2 2360static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2361{
2362 int iopl;
2363 if (ctxt->mode == X86EMUL_MODE_REAL)
2364 return false;
2365 if (ctxt->mode == X86EMUL_MODE_VM86)
2366 return true;
2367 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2368 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2369}
2370
2371static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2372 u16 port, u16 len)
2373{
0225fb50 2374 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2375 struct desc_struct tr_seg;
5601d05b 2376 u32 base3;
f850e2e6 2377 int r;
1aa36616 2378 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2379 unsigned mask = (1 << len) - 1;
5601d05b 2380 unsigned long base;
f850e2e6 2381
1aa36616 2382 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2383 if (!tr_seg.p)
f850e2e6 2384 return false;
79168fd1 2385 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2386 return false;
5601d05b
GN		 2387 base = get_desc_base(&tr_seg);
2388#ifdef CONFIG_X86_64
2389 base |= ((u64)base3) << 32;
2390#endif
0f65dd70 2391 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2392 if (r != X86EMUL_CONTINUE)
2393 return false;
79168fd1 2394 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2395 return false;
0f65dd70 2396 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2397 if (r != X86EMUL_CONTINUE)
2398 return false;
2399 if ((perm >> bit_idx) & mask)
2400 return false;
2401 return true;
2402}
2403
2404static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2405 u16 port, u16 len)
2406{
4fc40f07
GN		 2407 if (ctxt->perm_ok)
2408 return true;
2409
7b105ca2
TY		 2410 if (emulator_bad_iopl(ctxt))
2411 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2412 return false;
4fc40f07
GN		 2413
2414 ctxt->perm_ok = true;
2415
f850e2e6
GN		 2416 return true;
2417}
2418
38ba30ba 2419static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2420 struct tss_segment_16 *tss)
2421{
9dac77fa 2422 tss->ip = ctxt->_eip;
38ba30ba 2423 tss->flag = ctxt->eflags;
dd856efa
AK		 2424 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2425 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2426 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2427 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2428 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2429 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2430 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2431 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2432
1aa36616
AK		 2433 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2434 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2435 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2436 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2437 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2438}
2439
2440static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2441 struct tss_segment_16 *tss)
2442{
38ba30ba 2443 int ret;
2356aaeb 2444 u8 cpl;
38ba30ba 2445
9dac77fa 2446 ctxt->_eip = tss->ip;
38ba30ba 2447 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2448 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2449 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2450 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2451 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2452 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2453 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2454 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2455 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2456
2457 /*
2458 * SDM says that segment selectors are loaded before segment
2459 * descriptors
2460 */
1aa36616
AK		 2461 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2462 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2463 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2464 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2465 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2466
2356aaeb
PB		 2467 cpl = tss->cs & 3;
2468
38ba30ba 2469 /*
fc058680 2470 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2471 * it is handled in a context of new task
2472 */
5045b468 2473 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
5045b468 2476 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
5045b468 2479 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2480 if (ret != X86EMUL_CONTINUE)
2481 return ret;
5045b468 2482 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2483 if (ret != X86EMUL_CONTINUE)
2484 return ret;
5045b468 2485 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2486 if (ret != X86EMUL_CONTINUE)
2487 return ret;
2488
2489 return X86EMUL_CONTINUE;
2490}
2491
2492static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2493 u16 tss_selector, u16 old_tss_sel,
2494 ulong old_tss_base, struct desc_struct *new_desc)
2495{
0225fb50 2496 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2497 struct tss_segment_16 tss_seg;
2498 int ret;
bcc55cba 2499 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2500
0f65dd70 2501 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2502 &ctxt->exception);
db297e3d 2503 if (ret != X86EMUL_CONTINUE)
38ba30ba 2504 /* FIXME: need to provide precise fault address */
38ba30ba 2505 return ret;
38ba30ba 2506
7b105ca2 2507 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2508
0f65dd70 2509 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2510 &ctxt->exception);
db297e3d 2511 if (ret != X86EMUL_CONTINUE)
38ba30ba 2512 /* FIXME: need to provide precise fault address */
38ba30ba 2513 return ret;
38ba30ba 2514
0f65dd70 2515 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2516 &ctxt->exception);
db297e3d 2517 if (ret != X86EMUL_CONTINUE)
38ba30ba 2518 /* FIXME: need to provide precise fault address */
38ba30ba 2519 return ret;
38ba30ba
GN		 2520
2521 if (old_tss_sel != 0xffff) {
2522 tss_seg.prev_task_link = old_tss_sel;
2523
0f65dd70 2524 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2525 &tss_seg.prev_task_link,
2526 sizeof tss_seg.prev_task_link,
0f65dd70 2527 &ctxt->exception);
db297e3d 2528 if (ret != X86EMUL_CONTINUE)
38ba30ba 2529 /* FIXME: need to provide precise fault address */
38ba30ba 2530 return ret;
38ba30ba
GN		 2531 }
2532
7b105ca2 2533 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2534}
2535
2536static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2537 struct tss_segment_32 *tss)
2538{
5c7411e2 2539 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2540 tss->eip = ctxt->_eip;
38ba30ba 2541 tss->eflags = ctxt->eflags;
dd856efa
AK		 2542 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2543 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2544 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2545 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2546 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2547 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2548 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2549 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2550
1aa36616
AK		 2551 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2552 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2553 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2554 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2555 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2556 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2557}
2558
2559static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2560 struct tss_segment_32 *tss)
2561{
38ba30ba 2562 int ret;
2356aaeb 2563 u8 cpl;
38ba30ba 2564
7b105ca2 2565 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2566 return emulate_gp(ctxt, 0);
9dac77fa 2567 ctxt->_eip = tss->eip;
38ba30ba 2568 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2569
2570 /* General purpose registers */
dd856efa
AK		 2571 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2572 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2573 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2574 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2575 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2576 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2577 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2578 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2579
2580 /*
2581 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2582 * descriptors. This is important because CPL checks will
2583 * use CS.RPL.
38ba30ba 2584 */
1aa36616
AK		 2585 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2586 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2587 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2588 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2589 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2590 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2591 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2592
4cee4798
KW		 2593 /*
2594 * If we're switching between Protected Mode and VM86, we need to make
2595 * sure to update the mode before loading the segment descriptors so
2596 * that the selectors are interpreted correctly.
4cee4798 2597 */
2356aaeb 2598 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2599 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2600 cpl = 3;
2601 } else {
4cee4798 2602 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2603 cpl = tss->cs & 3;
2604 }
4cee4798 2605
38ba30ba
GN		 2606 /*
2607 * Now load segment descriptors. If fault happenes at this stage
2608 * it is handled in a context of new task
2609 */
5045b468 2610 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2611 if (ret != X86EMUL_CONTINUE)
2612 return ret;
5045b468 2613 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
5045b468 2616 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
5045b468 2619 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2620 if (ret != X86EMUL_CONTINUE)
2621 return ret;
5045b468 2622 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2623 if (ret != X86EMUL_CONTINUE)
2624 return ret;
5045b468 2625 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2626 if (ret != X86EMUL_CONTINUE)
2627 return ret;
5045b468 2628 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2629 if (ret != X86EMUL_CONTINUE)
2630 return ret;
2631
2632 return X86EMUL_CONTINUE;
2633}
2634
2635static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2636 u16 tss_selector, u16 old_tss_sel,
2637 ulong old_tss_base, struct desc_struct *new_desc)
2638{
0225fb50 2639 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2640 struct tss_segment_32 tss_seg;
2641 int ret;
bcc55cba 2642 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2643 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2644 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2645
0f65dd70 2646 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2647 &ctxt->exception);
db297e3d 2648 if (ret != X86EMUL_CONTINUE)
38ba30ba 2649 /* FIXME: need to provide precise fault address */
38ba30ba 2650 return ret;
38ba30ba 2651
7b105ca2 2652 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2653
5c7411e2
NA		 2654 /* Only GP registers and segment selectors are saved */
2655 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2656 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2657 if (ret != X86EMUL_CONTINUE)
38ba30ba 2658 /* FIXME: need to provide precise fault address */
38ba30ba 2659 return ret;
38ba30ba 2660
0f65dd70 2661 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2662 &ctxt->exception);
db297e3d 2663 if (ret != X86EMUL_CONTINUE)
38ba30ba 2664 /* FIXME: need to provide precise fault address */
38ba30ba 2665 return ret;
38ba30ba
GN		 2666
2667 if (old_tss_sel != 0xffff) {
2668 tss_seg.prev_task_link = old_tss_sel;
2669
0f65dd70 2670 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2671 &tss_seg.prev_task_link,
2672 sizeof tss_seg.prev_task_link,
0f65dd70 2673 &ctxt->exception);
db297e3d 2674 if (ret != X86EMUL_CONTINUE)
38ba30ba 2675 /* FIXME: need to provide precise fault address */
38ba30ba 2676 return ret;
38ba30ba
GN		 2677 }
2678
7b105ca2 2679 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2680}
2681
2682static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2683 u16 tss_selector, int idt_index, int reason,
e269fb21 2684 bool has_error_code, u32 error_code)
38ba30ba 2685{
0225fb50 2686 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2687 struct desc_struct curr_tss_desc, next_tss_desc;
2688 int ret;
1aa36616 2689 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2690 ulong old_tss_base =
4bff1e86 2691 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2692 u32 desc_limit;
e919464b 2693 ulong desc_addr;
38ba30ba
GN		 2694
2695 /* FIXME: old_tss_base == ~0 ? */
2696
e919464b 2697 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2698 if (ret != X86EMUL_CONTINUE)
2699 return ret;
e919464b 2700 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2701 if (ret != X86EMUL_CONTINUE)
2702 return ret;
2703
2704 /* FIXME: check that next_tss_desc is tss */
2705
7f3d35fd
KW		 2706 /*
2707 * Check privileges. The three cases are task switch caused by...
2708 *
2709 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2710 * 2. Exception/IRQ/iret: No check is performed
fc058680 2711 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2712 */
2713 if (reason == TASK_SWITCH_GATE) {
2714 if (idt_index != -1) {
2715 /* Software interrupts */
2716 struct desc_struct task_gate_desc;
2717 int dpl;
2718
2719 ret = read_interrupt_descriptor(ctxt, idt_index,
2720 &task_gate_desc);
2721 if (ret != X86EMUL_CONTINUE)
2722 return ret;
2723
2724 dpl = task_gate_desc.dpl;
2725 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2726 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2727 }
2728 } else if (reason != TASK_SWITCH_IRET) {
2729 int dpl = next_tss_desc.dpl;
2730 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2731 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2732 }
2733
7f3d35fd 2734
ceffb459
GN		 2735 desc_limit = desc_limit_scaled(&next_tss_desc);
2736 if (!next_tss_desc.p ||
2737 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2738 desc_limit < 0x2b)) {
54b8486f 2739 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2740 return X86EMUL_PROPAGATE_FAULT;
2741 }
2742
2743 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2744 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2745 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2746 }
2747
2748 if (reason == TASK_SWITCH_IRET)
2749 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2750
2751 /* set back link to prev task only if NT bit is set in eflags
fc058680 2752 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2753 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2754 old_tss_sel = 0xffff;
2755
2756 if (next_tss_desc.type & 8)
7b105ca2 2757 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2758 old_tss_base, &next_tss_desc);
2759 else
7b105ca2 2760 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2761 old_tss_base, &next_tss_desc);
0760d448
JK		 2762 if (ret != X86EMUL_CONTINUE)
2763 return ret;
38ba30ba
GN		 2764
2765 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2766 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2767
2768 if (reason != TASK_SWITCH_IRET) {
2769 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2770 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2771 }
2772
717746e3 2773 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2774 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2775
e269fb21 2776 if (has_error_code) {
9dac77fa
AK		 2777 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2778 ctxt->lock_prefix = 0;
2779 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2780 ret = em_push(ctxt);
e269fb21
JK		 2781 }
2782
38ba30ba
GN		 2783 return ret;
2784}
2785
2786int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2787 u16 tss_selector, int idt_index, int reason,
e269fb21 2788 bool has_error_code, u32 error_code)
38ba30ba 2789{
38ba30ba
GN		 2790 int rc;
2791
dd856efa 2792 invalidate_registers(ctxt);
9dac77fa
AK		 2793 ctxt->_eip = ctxt->eip;
2794 ctxt->dst.type = OP_NONE;
38ba30ba 2795
7f3d35fd 2796 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2797 has_error_code, error_code);
38ba30ba 2798
dd856efa 2799 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2800 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2801 writeback_registers(ctxt);
2802 }
38ba30ba 2803
a0c0ab2f 2804 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2805}
2806
f3bd64c6
GN		 2807static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2808 struct operand *op)
a682e354 2809{
b3356bf0 2810 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2811
dd856efa
AK		 2812 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2813 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2814}
2815
7af04fc0
AK		 2816static int em_das(struct x86_emulate_ctxt *ctxt)
2817{
7af04fc0
AK		 2818 u8 al, old_al;
2819 bool af, cf, old_cf;
2820
2821 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2822 al = ctxt->dst.val;
7af04fc0
AK		 2823
2824 old_al = al;
2825 old_cf = cf;
2826 cf = false;
2827 af = ctxt->eflags & X86_EFLAGS_AF;
2828 if ((al & 0x0f) > 9 || af) {
2829 al -= 6;
2830 cf = old_cf | (al >= 250);
2831 af = true;
2832 } else {
2833 af = false;
2834 }
2835 if (old_al > 0x99 || old_cf) {
2836 al -= 0x60;
2837 cf = true;
2838 }
2839
9dac77fa 2840 ctxt->dst.val = al;
7af04fc0 2841 /* Set PF, ZF, SF */
9dac77fa
AK		 2842 ctxt->src.type = OP_IMM;
2843 ctxt->src.val = 0;
2844 ctxt->src.bytes = 1;
158de57f 2845 fastop(ctxt, em_or);
7af04fc0
AK		 2846 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2847 if (cf)
2848 ctxt->eflags |= X86_EFLAGS_CF;
2849 if (af)
2850 ctxt->eflags |= X86_EFLAGS_AF;
2851 return X86EMUL_CONTINUE;
2852}
2853
a035d5c6
PB		 2854static int em_aam(struct x86_emulate_ctxt *ctxt)
2855{
2856 u8 al, ah;
2857
2858 if (ctxt->src.val == 0)
2859 return emulate_de(ctxt);
2860
2861 al = ctxt->dst.val & 0xff;
2862 ah = al / ctxt->src.val;
2863 al %= ctxt->src.val;
2864
2865 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2866
2867 /* Set PF, ZF, SF */
2868 ctxt->src.type = OP_IMM;
2869 ctxt->src.val = 0;
2870 ctxt->src.bytes = 1;
2871 fastop(ctxt, em_or);
2872
2873 return X86EMUL_CONTINUE;
2874}
2875
7f662273
GN		 2876static int em_aad(struct x86_emulate_ctxt *ctxt)
2877{
2878 u8 al = ctxt->dst.val & 0xff;
2879 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2880
2881 al = (al + (ah * ctxt->src.val)) & 0xff;
2882
2883 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2884
f583c29b
GN		 2885 /* Set PF, ZF, SF */
2886 ctxt->src.type = OP_IMM;
2887 ctxt->src.val = 0;
2888 ctxt->src.bytes = 1;
2889 fastop(ctxt, em_or);
7f662273
GN		 2890
2891 return X86EMUL_CONTINUE;
2892}
2893
d4ddafcd
TY		 2894static int em_call(struct x86_emulate_ctxt *ctxt)
2895{
2896 long rel = ctxt->src.val;
2897
2898 ctxt->src.val = (unsigned long)ctxt->_eip;
2899 jmp_rel(ctxt, rel);
2900 return em_push(ctxt);
2901}
2902
0ef753b8
AK		 2903static int em_call_far(struct x86_emulate_ctxt *ctxt)
2904{
0ef753b8
AK		 2905 u16 sel, old_cs;
2906 ulong old_eip;
2907 int rc;
2908
1aa36616 2909 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2910 old_eip = ctxt->_eip;
0ef753b8 2911
9dac77fa 2912 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2913 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2914 return X86EMUL_CONTINUE;
2915
9dac77fa
AK		 2916 ctxt->_eip = 0;
2917 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2918
9dac77fa 2919 ctxt->src.val = old_cs;
4487b3b4 2920 rc = em_push(ctxt);
0ef753b8
AK		 2921 if (rc != X86EMUL_CONTINUE)
2922 return rc;
2923
9dac77fa 2924 ctxt->src.val = old_eip;
4487b3b4 2925 return em_push(ctxt);
0ef753b8
AK		 2926}
2927
40ece7c7
AK		 2928static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2929{
40ece7c7
AK		 2930 int rc;
2931
9dac77fa
AK		 2932 ctxt->dst.type = OP_REG;
2933 ctxt->dst.addr.reg = &ctxt->_eip;
2934 ctxt->dst.bytes = ctxt->op_bytes;
2935 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2936 if (rc != X86EMUL_CONTINUE)
2937 return rc;
5ad105e5 2938 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2939 return X86EMUL_CONTINUE;
2940}
2941
e4f973ae
TY		 2942static int em_xchg(struct x86_emulate_ctxt *ctxt)
2943{
e4f973ae 2944 /* Write back the register source. */
9dac77fa
AK		 2945 ctxt->src.val = ctxt->dst.val;
2946 write_register_operand(&ctxt->src);
e4f973ae
TY		 2947
2948 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2949 ctxt->dst.val = ctxt->src.orig_val;
2950 ctxt->lock_prefix = 1;
e4f973ae
TY		 2951 return X86EMUL_CONTINUE;
2952}
2953
5c82aa29
AK		 2954static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2955{
9dac77fa 2956 ctxt->dst.val = ctxt->src2.val;
4d758349 2957 return fastop(ctxt, em_imul);
5c82aa29
AK		 2958}
2959
61429142
AK		 2960static int em_cwd(struct x86_emulate_ctxt *ctxt)
2961{
9dac77fa
AK		 2962 ctxt->dst.type = OP_REG;
2963 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2964 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2965 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2966
2967 return X86EMUL_CONTINUE;
2968}
2969
48bb5d3c
AK		 2970static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2971{
48bb5d3c
AK		 2972 u64 tsc = 0;
2973
717746e3 2974 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2975 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2976 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2977 return X86EMUL_CONTINUE;
2978}
2979
222d21aa
AK		 2980static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2981{
2982 u64 pmc;
2983
dd856efa 2984 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2985 return emulate_gp(ctxt, 0);
dd856efa
AK		 2986 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2987 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2988 return X86EMUL_CONTINUE;
2989}
2990
b9eac5f4
AK		 2991static int em_mov(struct x86_emulate_ctxt *ctxt)
2992{
54cfdb3e 2993 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2994 return X86EMUL_CONTINUE;
2995}
2996
84cffe49
BP		 2997#define FFL(x) bit(X86_FEATURE_##x)
2998
2999static int em_movbe(struct x86_emulate_ctxt *ctxt)
3000{
3001 u32 ebx, ecx, edx, eax = 1;
3002 u16 tmp;
3003
3004 /*
3005 * Check MOVBE is set in the guest-visible CPUID leaf.
3006 */
3007 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3008 if (!(ecx & FFL(MOVBE)))
3009 return emulate_ud(ctxt);
3010
3011 switch (ctxt->op_bytes) {
3012 case 2:
3013 /*
3014 * From MOVBE definition: "...When the operand size is 16 bits,
3015 * the upper word of the destination register remains unchanged
3016 * ..."
3017 *
3018 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3019 * rules so we have to do the operation almost per hand.
3020 */
3021 tmp = (u16)ctxt->src.val;
3022 ctxt->dst.val &= ~0xffffUL;
3023 ctxt->dst.val |= (unsigned long)swab16(tmp);
3024 break;
3025 case 4:
3026 ctxt->dst.val = swab32((u32)ctxt->src.val);
3027 break;
3028 case 8:
3029 ctxt->dst.val = swab64(ctxt->src.val);
3030 break;
3031 default:
3032 return X86EMUL_PROPAGATE_FAULT;
3033 }
3034 return X86EMUL_CONTINUE;
3035}
3036
bc00f8d2
TY		 3037static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3038{
3039 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3040 return emulate_gp(ctxt, 0);
3041
3042 /* Disable writeback. */
3043 ctxt->dst.type = OP_NONE;
3044 return X86EMUL_CONTINUE;
3045}
3046
3047static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3048{
3049 unsigned long val;
3050
3051 if (ctxt->mode == X86EMUL_MODE_PROT64)
3052 val = ctxt->src.val & ~0ULL;
3053 else
3054 val = ctxt->src.val & ~0U;
3055
3056 /* #UD condition is already handled. */
3057 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3058 return emulate_gp(ctxt, 0);
3059
3060 /* Disable writeback. */
3061 ctxt->dst.type = OP_NONE;
3062 return X86EMUL_CONTINUE;
3063}
3064
e1e210b0
TY		 3065static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3066{
3067 u64 msr_data;
3068
dd856efa
AK		 3069 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3070 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3071 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3072 return emulate_gp(ctxt, 0);
3073
3074 return X86EMUL_CONTINUE;
3075}
3076
3077static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3078{
3079 u64 msr_data;
3080
dd856efa 3081 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3082 return emulate_gp(ctxt, 0);
3083
dd856efa
AK		 3084 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3085 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3086 return X86EMUL_CONTINUE;
3087}
3088
1bd5f469
TY		 3089static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3090{
9dac77fa 3091 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3092 return emulate_ud(ctxt);
3093
9dac77fa 3094 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3095 return X86EMUL_CONTINUE;
3096}
3097
3098static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3099{
9dac77fa 3100 u16 sel = ctxt->src.val;
1bd5f469 3101
9dac77fa 3102 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3103 return emulate_ud(ctxt);
3104
9dac77fa 3105 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3106 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3107
3108 /* Disable writeback. */
9dac77fa
AK		 3109 ctxt->dst.type = OP_NONE;
3110 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3111}
3112
a14e579f
AK		 3113static int em_lldt(struct x86_emulate_ctxt *ctxt)
3114{
3115 u16 sel = ctxt->src.val;
3116
3117 /* Disable writeback. */
3118 ctxt->dst.type = OP_NONE;
3119 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3120}
3121
80890006
AK		 3122static int em_ltr(struct x86_emulate_ctxt *ctxt)
3123{
3124 u16 sel = ctxt->src.val;
3125
3126 /* Disable writeback. */
3127 ctxt->dst.type = OP_NONE;
3128 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3129}
3130
38503911
AK		 3131static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3132{
9fa088f4
AK		 3133 int rc;
3134 ulong linear;
3135
9dac77fa 3136 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3137 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3138 ctxt->ops->invlpg(ctxt, linear);
38503911 3139 /* Disable writeback. */
9dac77fa 3140 ctxt->dst.type = OP_NONE;
38503911
AK		 3141 return X86EMUL_CONTINUE;
3142}
3143
2d04a05b
AK		 3144static int em_clts(struct x86_emulate_ctxt *ctxt)
3145{
3146 ulong cr0;
3147
3148 cr0 = ctxt->ops->get_cr(ctxt, 0);
3149 cr0 &= ~X86_CR0_TS;
3150 ctxt->ops->set_cr(ctxt, 0, cr0);
3151 return X86EMUL_CONTINUE;
3152}
3153
26d05cc7
AK		 3154static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3155{
26d05cc7
AK		 3156 int rc;
3157
9dac77fa 3158 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3159 return X86EMUL_UNHANDLEABLE;
3160
3161 rc = ctxt->ops->fix_hypercall(ctxt);
3162 if (rc != X86EMUL_CONTINUE)
3163 return rc;
3164
3165 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3166 ctxt->_eip = ctxt->eip;
26d05cc7 3167 /* Disable writeback. */
9dac77fa 3168 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3169 return X86EMUL_CONTINUE;
3170}
3171
96051572
AK		 3172static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3173 void (*get)(struct x86_emulate_ctxt *ctxt,
3174 struct desc_ptr *ptr))
3175{
3176 struct desc_ptr desc_ptr;
3177
3178 if (ctxt->mode == X86EMUL_MODE_PROT64)
3179 ctxt->op_bytes = 8;
3180 get(ctxt, &desc_ptr);
3181 if (ctxt->op_bytes == 2) {
3182 ctxt->op_bytes = 4;
3183 desc_ptr.address &= 0x00ffffff;
3184 }
3185 /* Disable writeback. */
3186 ctxt->dst.type = OP_NONE;
3187 return segmented_write(ctxt, ctxt->dst.addr.mem,
3188 &desc_ptr, 2 + ctxt->op_bytes);
3189}
3190
3191static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3192{
3193 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3194}
3195
3196static int em_sidt(struct x86_emulate_ctxt *ctxt)
3197{
3198 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3199}
3200
26d05cc7
AK		 3201static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3202{
26d05cc7
AK		 3203 struct desc_ptr desc_ptr;
3204 int rc;
3205
510425ff
AK		 3206 if (ctxt->mode == X86EMUL_MODE_PROT64)
3207 ctxt->op_bytes = 8;
9dac77fa 3208 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3209 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3210 ctxt->op_bytes);
26d05cc7
AK		 3211 if (rc != X86EMUL_CONTINUE)
3212 return rc;
3213 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3214 /* Disable writeback. */
9dac77fa 3215 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3216 return X86EMUL_CONTINUE;
3217}
3218
5ef39c71 3219static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3220{
26d05cc7
AK		 3221 int rc;
3222
5ef39c71
AK		 3223 rc = ctxt->ops->fix_hypercall(ctxt);
3224
26d05cc7 3225 /* Disable writeback. */
9dac77fa 3226 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3227 return rc;
3228}
3229
3230static int em_lidt(struct x86_emulate_ctxt *ctxt)
3231{
26d05cc7
AK		 3232 struct desc_ptr desc_ptr;
3233 int rc;
3234
510425ff
AK		 3235 if (ctxt->mode == X86EMUL_MODE_PROT64)
3236 ctxt->op_bytes = 8;
9dac77fa 3237 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3238 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3239 ctxt->op_bytes);
26d05cc7
AK		 3240 if (rc != X86EMUL_CONTINUE)
3241 return rc;
3242 ctxt->ops->set_idt(ctxt, &desc_ptr);
3243 /* Disable writeback. */
9dac77fa 3244 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3245 return X86EMUL_CONTINUE;
3246}
3247
3248static int em_smsw(struct x86_emulate_ctxt *ctxt)
3249{
32e94d06
NA		 3250 if (ctxt->dst.type == OP_MEM)
3251 ctxt->dst.bytes = 2;
9dac77fa 3252 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3253 return X86EMUL_CONTINUE;
3254}
3255
3256static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3257{
26d05cc7 3258 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3259 | (ctxt->src.val & 0x0f));
3260 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3261 return X86EMUL_CONTINUE;
3262}
3263
d06e03ad
TY		 3264static int em_loop(struct x86_emulate_ctxt *ctxt)
3265{
dd856efa
AK		 3266 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3267 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3268 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3269 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3270
3271 return X86EMUL_CONTINUE;
3272}
3273
3274static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3275{
dd856efa 3276 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3277 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3278
3279 return X86EMUL_CONTINUE;
3280}
3281
d7841a4b
TY		 3282static int em_in(struct x86_emulate_ctxt *ctxt)
3283{
3284 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3285 &ctxt->dst.val))
3286 return X86EMUL_IO_NEEDED;
3287
3288 return X86EMUL_CONTINUE;
3289}
3290
3291static int em_out(struct x86_emulate_ctxt *ctxt)
3292{
3293 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3294 &ctxt->src.val, 1);
3295 /* Disable writeback. */
3296 ctxt->dst.type = OP_NONE;
3297 return X86EMUL_CONTINUE;
3298}
3299
f411e6cd
TY		 3300static int em_cli(struct x86_emulate_ctxt *ctxt)
3301{
3302 if (emulator_bad_iopl(ctxt))
3303 return emulate_gp(ctxt, 0);
3304
3305 ctxt->eflags &= ~X86_EFLAGS_IF;
3306 return X86EMUL_CONTINUE;
3307}
3308
3309static int em_sti(struct x86_emulate_ctxt *ctxt)
3310{
3311 if (emulator_bad_iopl(ctxt))
3312 return emulate_gp(ctxt, 0);
3313
3314 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3315 ctxt->eflags |= X86_EFLAGS_IF;
3316 return X86EMUL_CONTINUE;
3317}
3318
6d6eede4
AK		 3319static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3320{
3321 u32 eax, ebx, ecx, edx;
3322
dd856efa
AK		 3323 eax = reg_read(ctxt, VCPU_REGS_RAX);
3324 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3325 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3326 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3327 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3328 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3329 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3330 return X86EMUL_CONTINUE;
3331}
3332
98f73630
PB		 3333static int em_sahf(struct x86_emulate_ctxt *ctxt)
3334{
3335 u32 flags;
3336
3337 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3338 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3339
3340 ctxt->eflags &= ~0xffUL;
3341 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3342 return X86EMUL_CONTINUE;
3343}
3344
2dd7caa0
AK		 3345static int em_lahf(struct x86_emulate_ctxt *ctxt)
3346{
dd856efa
AK		 3347 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3348 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3349 return X86EMUL_CONTINUE;
3350}
3351
9299836e
AK		 3352static int em_bswap(struct x86_emulate_ctxt *ctxt)
3353{
3354 switch (ctxt->op_bytes) {
3355#ifdef CONFIG_X86_64
3356 case 8:
3357 asm("bswap %0" : "+r"(ctxt->dst.val));
3358 break;
3359#endif
3360 default:
3361 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3362 break;
3363 }
3364 return X86EMUL_CONTINUE;
3365}
3366
cfec82cb
JR		 3367static bool valid_cr(int nr)
3368{
3369 switch (nr) {
3370 case 0:
3371 case 2 ... 4:
3372 case 8:
3373 return true;
3374 default:
3375 return false;
3376 }
3377}
3378
3379static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3380{
9dac77fa 3381 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3382 return emulate_ud(ctxt);
3383
3384 return X86EMUL_CONTINUE;
3385}
3386
3387static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3388{
9dac77fa
AK		 3389 u64 new_val = ctxt->src.val64;
3390 int cr = ctxt->modrm_reg;
c2ad2bb3 3391 u64 efer = 0;
cfec82cb
JR		 3392
3393 static u64 cr_reserved_bits[] = {
3394 0xffffffff00000000ULL,
3395 0, 0, 0, /* CR3 checked later */
3396 CR4_RESERVED_BITS,
3397 0, 0, 0,
3398 CR8_RESERVED_BITS,
3399 };
3400
3401 if (!valid_cr(cr))
3402 return emulate_ud(ctxt);
3403
3404 if (new_val & cr_reserved_bits[cr])
3405 return emulate_gp(ctxt, 0);
3406
3407 switch (cr) {
3408 case 0: {
c2ad2bb3 3409 u64 cr4;
cfec82cb
JR		 3410 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3411 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3412 return emulate_gp(ctxt, 0);
3413
717746e3
AK		 3414 cr4 = ctxt->ops->get_cr(ctxt, 4);
3415 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3416
3417 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3418 !(cr4 & X86_CR4_PAE))
3419 return emulate_gp(ctxt, 0);
3420
3421 break;
3422 }
3423 case 3: {
3424 u64 rsvd = 0;
3425
c2ad2bb3
AK		 3426 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3427 if (efer & EFER_LMA)
cfec82cb 3428 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3429
3430 if (new_val & rsvd)
3431 return emulate_gp(ctxt, 0);
3432
3433 break;
3434 }
3435 case 4: {
717746e3 3436 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3437
3438 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3439 return emulate_gp(ctxt, 0);
3440
3441 break;
3442 }
3443 }
3444
3445 return X86EMUL_CONTINUE;
3446}
3447
3b88e41a
JR		 3448static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3449{
3450 unsigned long dr7;
3451
717746e3 3452 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3453
3454 /* Check if DR7.Global_Enable is set */
3455 return dr7 & (1 << 13);
3456}
3457
3458static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3459{
9dac77fa 3460 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3461 u64 cr4;
3462
3463 if (dr > 7)
3464 return emulate_ud(ctxt);
3465
717746e3 3466 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3467 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3468 return emulate_ud(ctxt);
3469
3470 if (check_dr7_gd(ctxt))
3471 return emulate_db(ctxt);
3472
3473 return X86EMUL_CONTINUE;
3474}
3475
3476static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3477{
9dac77fa
AK		 3478 u64 new_val = ctxt->src.val64;
3479 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3480
3481 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3482 return emulate_gp(ctxt, 0);
3483
3484 return check_dr_read(ctxt);
3485}
3486
01de8b09
JR		 3487static int check_svme(struct x86_emulate_ctxt *ctxt)
3488{
3489 u64 efer;
3490
717746e3 3491 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3492
3493 if (!(efer & EFER_SVME))
3494 return emulate_ud(ctxt);
3495
3496 return X86EMUL_CONTINUE;
3497}
3498
3499static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3500{
dd856efa 3501 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3502
3503 /* Valid physical address? */
d4224449 3504 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3505 return emulate_gp(ctxt, 0);
3506
3507 return check_svme(ctxt);
3508}
3509
d7eb8203
JR		 3510static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3511{
717746e3 3512 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3513
717746e3 3514 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3515 return emulate_ud(ctxt);
3516
3517 return X86EMUL_CONTINUE;
3518}
3519
8061252e
JR		 3520static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3521{
717746e3 3522 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3523 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3524
717746e3 3525 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3526 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3527 return emulate_gp(ctxt, 0);
3528
3529 return X86EMUL_CONTINUE;
3530}
3531
f6511935
JR		 3532static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3533{
9dac77fa
AK		 3534 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3535 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3536 return emulate_gp(ctxt, 0);
3537
3538 return X86EMUL_CONTINUE;
3539}
3540
3541static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3542{
9dac77fa
AK		 3543 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3544 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3545 return emulate_gp(ctxt, 0);
3546
3547 return X86EMUL_CONTINUE;
3548}
3549
73fba5f4 3550#define D(_y) { .flags = (_y) }
d40a6898
PB		 3551#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3552#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3553 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3554#define N D(NotImpl)
01de8b09 3555#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3556#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3557#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3558#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3559#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3560#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3561#define II(_f, _e, _i) \
d40a6898 3562 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3563#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3564 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3565 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3566#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3567
8d8f4e9f 3568#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3569#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3570#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3571#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3572#define I2bvIP(_f, _e, _i, _p) \
3573 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3574
fb864fbc
AK		 3575#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3576 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3577 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3578
fd0a0d82 3579static const struct opcode group7_rm1[] = {
1c2545be
TY		 3580 DI(SrcNone | Priv, monitor),
3581 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3582 N, N, N, N, N, N,
3583};
3584
fd0a0d82 3585static const struct opcode group7_rm3[] = {
1c2545be 3586 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3587 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3588 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3589 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3590 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3591 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3592 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3593 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3594};
6230f7fc 3595
fd0a0d82 3596static const struct opcode group7_rm7[] = {
d7eb8203 3597 N,
1c2545be 3598 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3599 N, N, N, N, N, N,
3600};
d67fc27a 3601
fd0a0d82 3602static const struct opcode group1[] = {
fb864fbc
AK		 3603 F(Lock, em_add),
3604 F(Lock | PageTable, em_or),
3605 F(Lock, em_adc),
3606 F(Lock, em_sbb),
3607 F(Lock | PageTable, em_and),
3608 F(Lock, em_sub),
3609 F(Lock, em_xor),
3610 F(NoWrite, em_cmp),
73fba5f4
AK		 3611};
3612
fd0a0d82 3613static const struct opcode group1A[] = {
1c2545be 3614 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3615};
3616
007a3b54
AK		 3617static const struct opcode group2[] = {
3618 F(DstMem | ModRM, em_rol),
3619 F(DstMem | ModRM, em_ror),
3620 F(DstMem | ModRM, em_rcl),
3621 F(DstMem | ModRM, em_rcr),
3622 F(DstMem | ModRM, em_shl),
3623 F(DstMem | ModRM, em_shr),
3624 F(DstMem | ModRM, em_shl),
3625 F(DstMem | ModRM, em_sar),
3626};
3627
fd0a0d82 3628static const struct opcode group3[] = {
fb864fbc
AK		 3629 F(DstMem | SrcImm | NoWrite, em_test),
3630 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3631 F(DstMem | SrcNone | Lock, em_not),
3632 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3633 F(DstXacc | Src2Mem, em_mul_ex),
3634 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3635 F(DstXacc | Src2Mem, em_div_ex),
3636 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3637};
3638
fd0a0d82 3639static const struct opcode group4[] = {
95413dc4
AK		 3640 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3641 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3642 N, N, N, N, N, N,
3643};
3644
fd0a0d82 3645static const struct opcode group5[] = {
95413dc4
AK		 3646 F(DstMem | SrcNone | Lock, em_inc),
3647 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3648 I(SrcMem | Stack, em_grp45),
3649 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3650 I(SrcMem | Stack, em_grp45),
3651 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3652 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3653};
3654
fd0a0d82 3655static const struct opcode group6[] = {
1c2545be
TY		 3656 DI(Prot, sldt),
3657 DI(Prot, str),
a14e579f 3658 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3659 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3660 N, N, N, N,
3661};
3662
fd0a0d82 3663static const struct group_dual group7 = { {
606b1c3e
NA		 3664 II(Mov | DstMem, em_sgdt, sgdt),
3665 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3666 II(SrcMem | Priv, em_lgdt, lgdt),
3667 II(SrcMem | Priv, em_lidt, lidt),
3668 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3669 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3670 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3671}, {
b51e974f 3672 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3673 EXT(0, group7_rm1),
01de8b09 3674 N, EXT(0, group7_rm3),
1c2545be
TY		 3675 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3676 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3677 EXT(0, group7_rm7),
73fba5f4
AK		 3678} };
3679
fd0a0d82 3680static const struct opcode group8[] = {
73fba5f4 3681 N, N, N, N,
11c363ba
AK		 3682 F(DstMem | SrcImmByte | NoWrite, em_bt),
3683 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3684 F(DstMem | SrcImmByte | Lock, em_btr),
3685 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3686};
3687
fd0a0d82 3688static const struct group_dual group9 = { {
1c2545be 3689 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3690}, {
3691 N, N, N, N, N, N, N, N,
3692} };
3693
fd0a0d82 3694static const struct opcode group11[] = {
1c2545be 3695 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3696 X7(D(Undefined)),
a4d4a7c1
AK		 3697};
3698
fd0a0d82 3699static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3700 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3701};
3702
fd0a0d82 3703static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3704 I(0, em_mov), N, N, N,
3705};
3706
27ce8258 3707static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3708 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3709};
3710
045a282c
GN		 3711static const struct escape escape_d9 = { {
3712 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3713}, {
3714 /* 0xC0 - 0xC7 */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xC8 - 0xCF */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xD0 - 0xC7 */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xD8 - 0xDF */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xE0 - 0xE7 */
3723 N, N, N, N, N, N, N, N,
3724 /* 0xE8 - 0xEF */
3725 N, N, N, N, N, N, N, N,
3726 /* 0xF0 - 0xF7 */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xF8 - 0xFF */
3729 N, N, N, N, N, N, N, N,
3730} };
3731
3732static const struct escape escape_db = { {
3733 N, N, N, N, N, N, N, N,
3734}, {
3735 /* 0xC0 - 0xC7 */
3736 N, N, N, N, N, N, N, N,
3737 /* 0xC8 - 0xCF */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xD0 - 0xC7 */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xD8 - 0xDF */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xE0 - 0xE7 */
3744 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3745 /* 0xE8 - 0xEF */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xF0 - 0xF7 */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xF8 - 0xFF */
3750 N, N, N, N, N, N, N, N,
3751} };
3752
3753static const struct escape escape_dd = { {
3754 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3755}, {
3756 /* 0xC0 - 0xC7 */
3757 N, N, N, N, N, N, N, N,
3758 /* 0xC8 - 0xCF */
3759 N, N, N, N, N, N, N, N,
3760 /* 0xD0 - 0xC7 */
3761 N, N, N, N, N, N, N, N,
3762 /* 0xD8 - 0xDF */
3763 N, N, N, N, N, N, N, N,
3764 /* 0xE0 - 0xE7 */
3765 N, N, N, N, N, N, N, N,
3766 /* 0xE8 - 0xEF */
3767 N, N, N, N, N, N, N, N,
3768 /* 0xF0 - 0xF7 */
3769 N, N, N, N, N, N, N, N,
3770 /* 0xF8 - 0xFF */
3771 N, N, N, N, N, N, N, N,
3772} };
3773
fd0a0d82 3774static const struct opcode opcode_table[256] = {
73fba5f4 3775 /* 0x00 - 0x07 */
fb864fbc 3776 F6ALU(Lock, em_add),
1cd196ea
AK		 3777 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3778 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3779 /* 0x08 - 0x0F */
fb864fbc 3780 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3781 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3782 N,
73fba5f4 3783 /* 0x10 - 0x17 */
fb864fbc 3784 F6ALU(Lock, em_adc),
1cd196ea
AK		 3785 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3786 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3787 /* 0x18 - 0x1F */
fb864fbc 3788 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3789 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3790 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3791 /* 0x20 - 0x27 */
fb864fbc 3792 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3793 /* 0x28 - 0x2F */
fb864fbc 3794 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3795 /* 0x30 - 0x37 */
fb864fbc 3796 F6ALU(Lock, em_xor), N, N,
73fba5f4 3797 /* 0x38 - 0x3F */
fb864fbc 3798 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3799 /* 0x40 - 0x4F */
95413dc4 3800 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3801 /* 0x50 - 0x57 */
63540382 3802 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3803 /* 0x58 - 0x5F */
c54fe504 3804 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3805 /* 0x60 - 0x67 */
b96a7fad
TY		 3806 I(ImplicitOps | Stack | No64, em_pusha),
3807 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3808 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3809 N, N, N, N,
3810 /* 0x68 - 0x6F */
d46164db
AK		 3811 I(SrcImm | Mov | Stack, em_push),
3812 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3813 I(SrcImmByte | Mov | Stack, em_push),
3814 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3815 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3816 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3817 /* 0x70 - 0x7F */
3818 X16(D(SrcImmByte)),
3819 /* 0x80 - 0x87 */
1c2545be
TY		 3820 G(ByteOp | DstMem | SrcImm, group1),
3821 G(DstMem | SrcImm, group1),
3822 G(ByteOp | DstMem | SrcImm | No64, group1),
3823 G(DstMem | SrcImmByte, group1),
fb864fbc 3824 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3825 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3826 /* 0x88 - 0x8F */
d5ae7ce8 3827 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3828 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3829 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3830 D(ModRM | SrcMem | NoAccess | DstReg),
3831 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3832 G(0, group1A),
73fba5f4 3833 /* 0x90 - 0x97 */
bf608f88 3834 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3835 /* 0x98 - 0x9F */
61429142 3836 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3837 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3838 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3839 II(ImplicitOps | Stack, em_popf, popf),
3840 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3841 /* 0xA0 - 0xA7 */
b9eac5f4 3842 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3843 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3844 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3845 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3846 /* 0xA8 - 0xAF */
fb864fbc 3847 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3848 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3849 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3850 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3851 /* 0xB0 - 0xB7 */
b9eac5f4 3852 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3853 /* 0xB8 - 0xBF */
5e2c6883 3854 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3855 /* 0xC0 - 0xC7 */
007a3b54 3856 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3857 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3858 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3859 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3860 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3861 G(ByteOp, group11), G(0, group11),
73fba5f4 3862 /* 0xC8 - 0xCF */
612e89f0 3863 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3864 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3865 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3866 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3867 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3868 /* 0xD0 - 0xD7 */
007a3b54
AK		 3869 G(Src2One | ByteOp, group2), G(Src2One, group2),
3870 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3871 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3872 I(DstAcc | SrcImmUByte | No64, em_aad),
3873 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3874 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3875 /* 0xD8 - 0xDF */
045a282c 3876 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3877 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3878 X3(I(SrcImmByte, em_loop)),
3879 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3880 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3881 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3882 /* 0xE8 - 0xEF */
d4ddafcd 3883 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3884 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3885 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3886 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3887 /* 0xF0 - 0xF7 */
bf608f88 3888 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3889 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3890 G(ByteOp, group3), G(0, group3),
73fba5f4 3891 /* 0xF8 - 0xFF */
f411e6cd
TY		 3892 D(ImplicitOps), D(ImplicitOps),
3893 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3894 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3895};
3896
fd0a0d82 3897static const struct opcode twobyte_table[256] = {
73fba5f4 3898 /* 0x00 - 0x0F */
dee6bb70 3899 G(0, group6), GD(0, &group7), N, N,
b51e974f 3900 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3901 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3902 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3903 N, D(ImplicitOps | ModRM), N, N,
3904 /* 0x10 - 0x1F */
103f98ea
PB		 3905 N, N, N, N, N, N, N, N,
3906 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3907 /* 0x20 - 0x2F */
9b88ae99
NA		 3908 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3909 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3910 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3911 check_cr_write),
3912 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3913 check_dr_write),
73fba5f4 3914 N, N, N, N,
27ce8258
IM		 3915 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3916 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3917 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3918 N, N, N, N,
73fba5f4 3919 /* 0x30 - 0x3F */
e1e210b0 3920 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3921 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3922 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3923 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3924 I(ImplicitOps | EmulateOnUD, em_sysenter),
3925 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3926 N, N,
73fba5f4
AK		 3927 N, N, N, N, N, N, N, N,
3928 /* 0x40 - 0x4F */
140bad89 3929 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3930 /* 0x50 - 0x5F */
3931 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3932 /* 0x60 - 0x6F */
aa97bb48
AK		 3933 N, N, N, N,
3934 N, N, N, N,
3935 N, N, N, N,
3936 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3937 /* 0x70 - 0x7F */
aa97bb48
AK		 3938 N, N, N, N,
3939 N, N, N, N,
3940 N, N, N, N,
3941 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3942 /* 0x80 - 0x8F */
3943 X16(D(SrcImm)),
3944 /* 0x90 - 0x9F */
ee45b58e 3945 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3946 /* 0xA0 - 0xA7 */
1cd196ea 3947 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3948 II(ImplicitOps, em_cpuid, cpuid),
3949 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3950 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3951 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3952 /* 0xA8 - 0xAF */
1cd196ea 3953 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3954 DI(ImplicitOps, rsm),
11c363ba 3955 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3956 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3957 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3958 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3959 /* 0xB0 - 0xB7 */
e940b5c2 3960 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3961 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3962 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3963 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3964 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3965 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3966 /* 0xB8 - 0xBF */
3967 N, N,
ce7faab2 3968 G(BitOp, group8),
11c363ba
AK		 3969 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3970 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3971 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3972 /* 0xC0 - 0xC7 */
e47a5f5f 3973 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3974 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3975 N, N, N, GD(0, &group9),
9299836e
AK		 3976 /* 0xC8 - 0xCF */
3977 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3978 /* 0xD0 - 0xDF */
3979 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3980 /* 0xE0 - 0xEF */
3981 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3982 /* 0xF0 - 0xFF */
3983 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3984};
3985
0bc5eedb 3986static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3987 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3988};
3989
3990static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3991 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3992};
3993
3994/*
3995 * Insns below are selected by the prefix which indexed by the third opcode
3996 * byte.
3997 */
3998static const struct opcode opcode_map_0f_38[256] = {
3999 /* 0x00 - 0x7f */
4000 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4001 /* 0x80 - 0xef */
4002 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4003 /* 0xf0 - 0xf1 */
4004 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4005 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4006 /* 0xf2 - 0xff */
4007 N, N, X4(N), X8(N)
0bc5eedb
BP		 4008};
4009
73fba5f4
AK		 4010#undef D
4011#undef N
4012#undef G
4013#undef GD
4014#undef I
aa97bb48 4015#undef GP
01de8b09 4016#undef EXT
73fba5f4 4017
8d8f4e9f 4018#undef D2bv
f6511935 4019#undef D2bvIP
8d8f4e9f 4020#undef I2bv
d7841a4b 4021#undef I2bvIP
d67fc27a 4022#undef I6ALU
8d8f4e9f 4023
9dac77fa 4024static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4025{
4026 unsigned size;
4027
9dac77fa 4028 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4029 if (size == 8)
4030 size = 4;
4031 return size;
4032}
4033
4034static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4035 unsigned size, bool sign_extension)
4036{
39f21ee5
AK		 4037 int rc = X86EMUL_CONTINUE;
4038
4039 op->type = OP_IMM;
4040 op->bytes = size;
9dac77fa 4041 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4042 /* NB. Immediates are sign-extended as necessary. */
4043 switch (op->bytes) {
4044 case 1:
e85a1085 4045 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4046 break;
4047 case 2:
e85a1085 4048 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4049 break;
4050 case 4:
e85a1085 4051 op->val = insn_fetch(s32, ctxt);
39f21ee5 4052 break;
5e2c6883
NA		 4053 case 8:
4054 op->val = insn_fetch(s64, ctxt);
4055 break;
39f21ee5
AK		 4056 }
4057 if (!sign_extension) {
4058 switch (op->bytes) {
4059 case 1:
4060 op->val &= 0xff;
4061 break;
4062 case 2:
4063 op->val &= 0xffff;
4064 break;
4065 case 4:
4066 op->val &= 0xffffffff;
4067 break;
4068 }
4069 }
4070done:
4071 return rc;
4072}
4073
a9945549
AK		 4074static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4075 unsigned d)
4076{
4077 int rc = X86EMUL_CONTINUE;
4078
4079 switch (d) {
4080 case OpReg:
2adb5ad9 4081 decode_register_operand(ctxt, op);
a9945549
AK		 4082 break;
4083 case OpImmUByte:
608aabe3 4084 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4085 break;
4086 case OpMem:
41ddf978 4087 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4088 mem_common:
4089 *op = ctxt->memop;
4090 ctxt->memopp = op;
96888977 4091 if (ctxt->d & BitOp)
a9945549
AK		 4092 fetch_bit_operand(ctxt);
4093 op->orig_val = op->val;
4094 break;
41ddf978 4095 case OpMem64:
aaa05f24 4096 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4097 goto mem_common;
a9945549
AK		 4098 case OpAcc:
4099 op->type = OP_REG;
4100 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4101 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4102 fetch_register_operand(op);
4103 op->orig_val = op->val;
4104 break;
820207c8
AK		 4105 case OpAccLo:
4106 op->type = OP_REG;
4107 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4108 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4109 fetch_register_operand(op);
4110 op->orig_val = op->val;
4111 break;
4112 case OpAccHi:
4113 if (ctxt->d & ByteOp) {
4114 op->type = OP_NONE;
4115 break;
4116 }
4117 op->type = OP_REG;
4118 op->bytes = ctxt->op_bytes;
4119 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4120 fetch_register_operand(op);
4121 op->orig_val = op->val;
4122 break;
a9945549
AK		 4123 case OpDI:
4124 op->type = OP_MEM;
4125 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4126 op->addr.mem.ea =
dd856efa 4127 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4128 op->addr.mem.seg = VCPU_SREG_ES;
4129 op->val = 0;
b3356bf0 4130 op->count = 1;
a9945549
AK		 4131 break;
4132 case OpDX:
4133 op->type = OP_REG;
4134 op->bytes = 2;
dd856efa 4135 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4136 fetch_register_operand(op);
4137 break;
4dd6a57d
AK		 4138 case OpCL:
4139 op->bytes = 1;
dd856efa 4140 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4141 break;
4142 case OpImmByte:
4143 rc = decode_imm(ctxt, op, 1, true);
4144 break;
4145 case OpOne:
4146 op->bytes = 1;
4147 op->val = 1;
4148 break;
4149 case OpImm:
4150 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4151 break;
5e2c6883
NA		 4152 case OpImm64:
4153 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4154 break;
28867cee
AK		 4155 case OpMem8:
4156 ctxt->memop.bytes = 1;
660696d1 4157 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4158 ctxt->memop.addr.reg = decode_register(ctxt,
4159 ctxt->modrm_rm, true);
660696d1
GN		 4160 fetch_register_operand(&ctxt->memop);
4161 }
28867cee 4162 goto mem_common;
0fe59128
AK		 4163 case OpMem16:
4164 ctxt->memop.bytes = 2;
4165 goto mem_common;
4166 case OpMem32:
4167 ctxt->memop.bytes = 4;
4168 goto mem_common;
4169 case OpImmU16:
4170 rc = decode_imm(ctxt, op, 2, false);
4171 break;
4172 case OpImmU:
4173 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4174 break;
4175 case OpSI:
4176 op->type = OP_MEM;
4177 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4178 op->addr.mem.ea =
dd856efa 4179 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4180 op->addr.mem.seg = seg_override(ctxt);
4181 op->val = 0;
b3356bf0 4182 op->count = 1;
0fe59128 4183 break;
7fa57952
PB		 4184 case OpXLat:
4185 op->type = OP_MEM;
4186 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4187 op->addr.mem.ea =
4188 register_address(ctxt,
4189 reg_read(ctxt, VCPU_REGS_RBX) +
4190 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4191 op->addr.mem.seg = seg_override(ctxt);
4192 op->val = 0;
4193 break;
0fe59128
AK		 4194 case OpImmFAddr:
4195 op->type = OP_IMM;
4196 op->addr.mem.ea = ctxt->_eip;
4197 op->bytes = ctxt->op_bytes + 2;
4198 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4199 break;
4200 case OpMemFAddr:
4201 ctxt->memop.bytes = ctxt->op_bytes + 2;
4202 goto mem_common;
c191a7a0
AK		 4203 case OpES:
4204 op->val = VCPU_SREG_ES;
4205 break;
4206 case OpCS:
4207 op->val = VCPU_SREG_CS;
4208 break;
4209 case OpSS:
4210 op->val = VCPU_SREG_SS;
4211 break;
4212 case OpDS:
4213 op->val = VCPU_SREG_DS;
4214 break;
4215 case OpFS:
4216 op->val = VCPU_SREG_FS;
4217 break;
4218 case OpGS:
4219 op->val = VCPU_SREG_GS;
4220 break;
a9945549
AK		 4221 case OpImplicit:
4222 /* Special instructions do their own operand decoding. */
4223 default:
4224 op->type = OP_NONE; /* Disable writeback. */
4225 break;
4226 }
4227
4228done:
4229 return rc;
4230}
4231
ef5d75cc 4232int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4233{
dde7e6d1
AK		 4234 int rc = X86EMUL_CONTINUE;
4235 int mode = ctxt->mode;
46561646 4236 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4237 bool op_prefix = false;
46561646 4238 struct opcode opcode;
dde7e6d1 4239
f09ed83e
AK		 4240 ctxt->memop.type = OP_NONE;
4241 ctxt->memopp = NULL;
9dac77fa
AK		 4242 ctxt->_eip = ctxt->eip;
4243 ctxt->fetch.start = ctxt->_eip;
4244 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4245 ctxt->opcode_len = 1;
dc25e89e 4246 if (insn_len > 0)
9dac77fa 4247 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4248
4249 switch (mode) {
4250 case X86EMUL_MODE_REAL:
4251 case X86EMUL_MODE_VM86:
4252 case X86EMUL_MODE_PROT16:
4253 def_op_bytes = def_ad_bytes = 2;
4254 break;
4255 case X86EMUL_MODE_PROT32:
4256 def_op_bytes = def_ad_bytes = 4;
4257 break;
4258#ifdef CONFIG_X86_64
4259 case X86EMUL_MODE_PROT64:
4260 def_op_bytes = 4;
4261 def_ad_bytes = 8;
4262 break;
4263#endif
4264 default:
1d2887e2 4265 return EMULATION_FAILED;
dde7e6d1
AK		 4266 }
4267
9dac77fa
AK		 4268 ctxt->op_bytes = def_op_bytes;
4269 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4270
4271 /* Legacy prefixes. */
4272 for (;;) {
e85a1085 4273 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4274 case 0x66: /* operand-size override */
0d7cdee8 4275 op_prefix = true;
dde7e6d1 4276 /* switch between 2/4 bytes */
9dac77fa 4277 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4278 break;
4279 case 0x67: /* address-size override */
4280 if (mode == X86EMUL_MODE_PROT64)
4281 /* switch between 4/8 bytes */
9dac77fa 4282 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4283 else
4284 /* switch between 2/4 bytes */
9dac77fa 4285 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4286 break;
4287 case 0x26: /* ES override */
4288 case 0x2e: /* CS override */
4289 case 0x36: /* SS override */
4290 case 0x3e: /* DS override */
9dac77fa 4291 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4292 break;
4293 case 0x64: /* FS override */
4294 case 0x65: /* GS override */
9dac77fa 4295 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4296 break;
4297 case 0x40 ... 0x4f: /* REX */
4298 if (mode != X86EMUL_MODE_PROT64)
4299 goto done_prefixes;
9dac77fa 4300 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4301 continue;
4302 case 0xf0: /* LOCK */
9dac77fa 4303 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4304 break;
4305 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4306 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4307 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4308 break;
4309 default:
4310 goto done_prefixes;
4311 }
4312
4313 /* Any legacy prefix after a REX prefix nullifies its effect. */
4314
9dac77fa 4315 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4316 }
4317
4318done_prefixes:
4319
4320 /* REX prefix. */
9dac77fa
AK		 4321 if (ctxt->rex_prefix & 8)
4322 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4323
4324 /* Opcode byte(s). */
9dac77fa 4325 opcode = opcode_table[ctxt->b];
d3ad6243 4326 /* Two-byte opcode? */
9dac77fa 4327 if (ctxt->b == 0x0f) {
1ce19dc1 4328 ctxt->opcode_len = 2;
e85a1085 4329 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4330 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4331
4332 /* 0F_38 opcode map */
4333 if (ctxt->b == 0x38) {
4334 ctxt->opcode_len = 3;
4335 ctxt->b = insn_fetch(u8, ctxt);
4336 opcode = opcode_map_0f_38[ctxt->b];
4337 }
dde7e6d1 4338 }
9dac77fa 4339 ctxt->d = opcode.flags;
dde7e6d1 4340
9f4260e7
TY		 4341 if (ctxt->d & ModRM)
4342 ctxt->modrm = insn_fetch(u8, ctxt);
4343
7fe864dc
NA		 4344 /* vex-prefix instructions are not implemented */
4345 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4346 (mode == X86EMUL_MODE_PROT64 ||
4347 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4348 ctxt->d = NotImpl;
4349 }
4350
9dac77fa
AK		 4351 while (ctxt->d & GroupMask) {
4352 switch (ctxt->d & GroupMask) {
46561646 4353 case Group:
9dac77fa 4354 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4355 opcode = opcode.u.group[goffset];
4356 break;
4357 case GroupDual:
9dac77fa
AK		 4358 goffset = (ctxt->modrm >> 3) & 7;
4359 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4360 opcode = opcode.u.gdual->mod3[goffset];
4361 else
4362 opcode = opcode.u.gdual->mod012[goffset];
4363 break;
4364 case RMExt:
9dac77fa 4365 goffset = ctxt->modrm & 7;
01de8b09 4366 opcode = opcode.u.group[goffset];
46561646
AK		 4367 break;
4368 case Prefix:
9dac77fa 4369 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4370 return EMULATION_FAILED;
9dac77fa 4371 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4372 switch (simd_prefix) {
4373 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4374 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4375 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4376 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4377 }
4378 break;
045a282c
GN		 4379 case Escape:
4380 if (ctxt->modrm > 0xbf)
4381 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4382 else
4383 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4384 break;
46561646 4385 default:
1d2887e2 4386 return EMULATION_FAILED;
0d7cdee8 4387 }
46561646 4388
b1ea50b2 4389 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4390 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4391 }
4392
e24186e0
PB		 4393 /* Unrecognised? */
4394 if (ctxt->d == 0)
4395 return EMULATION_FAILED;
4396
9dac77fa 4397 ctxt->execute = opcode.u.execute;
dde7e6d1 4398
d40a6898
PB		 4399 if (unlikely(ctxt->d &
4400 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4401 /*
4402 * These are copied unconditionally here, and checked unconditionally
4403 * in x86_emulate_insn.
4404 */
4405 ctxt->check_perm = opcode.check_perm;
4406 ctxt->intercept = opcode.intercept;
dde7e6d1 4407
d40a6898
PB		 4408 if (ctxt->d & NotImpl)
4409 return EMULATION_FAILED;
d867162c 4410
d40a6898
PB		 4411 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4412 return EMULATION_FAILED;
dde7e6d1 4413
d40a6898 4414 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4415 ctxt->op_bytes = 8;
7f9b4b75 4416
d40a6898
PB		 4417 if (ctxt->d & Op3264) {
4418 if (mode == X86EMUL_MODE_PROT64)
4419 ctxt->op_bytes = 8;
4420 else
4421 ctxt->op_bytes = 4;
4422 }
4423
4424 if (ctxt->d & Sse)
4425 ctxt->op_bytes = 16;
4426 else if (ctxt->d & Mmx)
4427 ctxt->op_bytes = 8;
4428 }
1253791d 4429
dde7e6d1 4430 /* ModRM and SIB bytes. */
9dac77fa 4431 if (ctxt->d & ModRM) {
f09ed83e 4432 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4433 if (!ctxt->has_seg_override)
4434 set_seg_override(ctxt, ctxt->modrm_seg);
4435 } else if (ctxt->d & MemAbs)
f09ed83e 4436 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4437 if (rc != X86EMUL_CONTINUE)
4438 goto done;
4439
9dac77fa
AK		 4440 if (!ctxt->has_seg_override)
4441 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4442
f09ed83e 4443 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4444
f09ed83e
AK		 4445 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4446 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4447
dde7e6d1
AK		 4448 /*
4449 * Decode and fetch the source operand: register, memory
4450 * or immediate.
4451 */
0fe59128 4452 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4453 if (rc != X86EMUL_CONTINUE)
4454 goto done;
4455
dde7e6d1
AK		 4456 /*
4457 * Decode and fetch the second source operand: register, memory
4458 * or immediate.
4459 */
4dd6a57d 4460 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4461 if (rc != X86EMUL_CONTINUE)
4462 goto done;
4463
dde7e6d1 4464 /* Decode and fetch the destination operand: register or memory. */
a9945549 4465 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4466
4467done:
f09ed83e
AK		 4468 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4469 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4470
1d2887e2 4471 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4472}
4473
1cb3f3ae
XG		 4474bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4475{
4476 return ctxt->d & PageTable;
4477}
4478
3e2f65d5
GN		 4479static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4480{
3e2f65d5
GN		 4481 /* The second termination condition only applies for REPE
4482 * and REPNE. Test if the repeat string operation prefix is
4483 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4484 * corresponding termination condition according to:
4485 * - if REPE/REPZ and ZF = 0 then done
4486 * - if REPNE/REPNZ and ZF = 1 then done
4487 */
9dac77fa
AK		 4488 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4489 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4490 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4491 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4492 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4493 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4494 return true;
4495
4496 return false;
4497}
4498
cbe2c9d3
AK		 4499static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4500{
4501 bool fault = false;
4502
4503 ctxt->ops->get_fpu(ctxt);
4504 asm volatile("1: fwait \n\t"
4505 "2: \n\t"
4506 ".pushsection .fixup,\"ax\" \n\t"
4507 "3: \n\t"
4508 "movb $1, %[fault] \n\t"
4509 "jmp 2b \n\t"
4510 ".popsection \n\t"
4511 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4512 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4513 ctxt->ops->put_fpu(ctxt);
4514
4515 if (unlikely(fault))
4516 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4517
4518 return X86EMUL_CONTINUE;
4519}
4520
4521static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4522 struct operand *op)
4523{
4524 if (op->type == OP_MM)
4525 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4526}
4527
e28bbd44
AK		 4528static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4529{
4530 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4531 if (!(ctxt->d & ByteOp))
4532 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4533 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4534 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4535 [fastop]"+S"(fop)
4536 : "c"(ctxt->src2.val));
e28bbd44 4537 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4538 if (!fop) /* exception is returned in fop variable */
4539 return emulate_de(ctxt);
e28bbd44
AK		 4540 return X86EMUL_CONTINUE;
4541}
dd856efa 4542
7b105ca2 4543int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4544{
0225fb50 4545 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4546 int rc = X86EMUL_CONTINUE;
9dac77fa 4547 int saved_dst_type = ctxt->dst.type;
8b4caf66 4548
9dac77fa 4549 ctxt->mem_read.pos = 0;
310b5d30 4550
e24186e0
PB		 4551 /* LOCK prefix is allowed only with some instructions */
4552 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4553 rc = emulate_ud(ctxt);
1161624f
GN		 4554 goto done;
4555 }
4556
e24186e0 4557 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4558 rc = emulate_ud(ctxt);
d380a5e4
GN		 4559 goto done;
4560 }
4561
d40a6898
PB		 4562 if (unlikely(ctxt->d &
4563 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4564 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4565 (ctxt->d & Undefined)) {
4566 rc = emulate_ud(ctxt);
4567 goto done;
4568 }
1253791d 4569
d40a6898
PB		 4570 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4571 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4572 rc = emulate_ud(ctxt);
cbe2c9d3 4573 goto done;
d40a6898 4574 }
cbe2c9d3 4575
d40a6898
PB		 4576 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4577 rc = emulate_nm(ctxt);
c4f035c6 4578 goto done;
d40a6898 4579 }
c4f035c6 4580
d40a6898
PB		 4581 if (ctxt->d & Mmx) {
4582 rc = flush_pending_x87_faults(ctxt);
4583 if (rc != X86EMUL_CONTINUE)
4584 goto done;
4585 /*
4586 * Now that we know the fpu is exception safe, we can fetch
4587 * operands from it.
4588 */
4589 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4590 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4591 if (!(ctxt->d & Mov))
4592 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4593 }
e92805ac 4594
d40a6898
PB		 4595 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4596 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4597 X86_ICPT_PRE_EXCEPT);
4598 if (rc != X86EMUL_CONTINUE)
4599 goto done;
4600 }
8ea7d6ae 4601
d40a6898
PB		 4602 /* Privileged instruction can be executed only in CPL=0 */
4603 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4604 rc = emulate_gp(ctxt, 0);
d09beabd 4605 goto done;
d40a6898 4606 }
d09beabd 4607
d40a6898
PB		 4608 /* Instruction can only be executed in protected mode */
4609 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4610 rc = emulate_ud(ctxt);
c4f035c6 4611 goto done;
d40a6898 4612 }
c4f035c6 4613
d40a6898
PB		 4614 /* Do instruction specific permission checks */
4615 if (ctxt->check_perm) {
4616 rc = ctxt->check_perm(ctxt);
4617 if (rc != X86EMUL_CONTINUE)
4618 goto done;
4619 }
4620
4621 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4622 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4623 X86_ICPT_POST_EXCEPT);
4624 if (rc != X86EMUL_CONTINUE)
4625 goto done;
4626 }
4627
4628 if (ctxt->rep_prefix && (ctxt->d & String)) {
4629 /* All REP prefixes have the same first termination condition */
4630 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4631 ctxt->eip = ctxt->_eip;
4632 goto done;
4633 }
b9fa9d6b 4634 }
b9fa9d6b
AK		 4635 }
4636
9dac77fa
AK		 4637 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4638 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4639 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4640 if (rc != X86EMUL_CONTINUE)
8b4caf66 4641 goto done;
9dac77fa 4642 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4643 }
4644
9dac77fa
AK		 4645 if (ctxt->src2.type == OP_MEM) {
4646 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4647 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4648 if (rc != X86EMUL_CONTINUE)
4649 goto done;
4650 }
4651
9dac77fa 4652 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4653 goto special_insn;
4654
4655
9dac77fa 4656 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4657 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4658 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4659 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4660 if (rc != X86EMUL_CONTINUE)
4661 goto done;
038e51de 4662 }
9dac77fa 4663 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4664
018a98db
AK		 4665special_insn:
4666
9dac77fa
AK		 4667 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4668 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4669 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4670 if (rc != X86EMUL_CONTINUE)
4671 goto done;
4672 }
4673
9dac77fa 4674 if (ctxt->execute) {
e28bbd44
AK		 4675 if (ctxt->d & Fastop) {
4676 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4677 rc = fastop(ctxt, fop);
4678 if (rc != X86EMUL_CONTINUE)
4679 goto done;
4680 goto writeback;
4681 }
9dac77fa 4682 rc = ctxt->execute(ctxt);
ef65c889
AK		 4683 if (rc != X86EMUL_CONTINUE)
4684 goto done;
4685 goto writeback;
4686 }
4687
1ce19dc1 4688 if (ctxt->opcode_len == 2)
6aa8b732 4689 goto twobyte_insn;
0bc5eedb
BP		 4690 else if (ctxt->opcode_len == 3)
4691 goto threebyte_insn;
6aa8b732 4692
9dac77fa 4693 switch (ctxt->b) {
6aa8b732 4694 case 0x63: /* movsxd */
8b4caf66 4695 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4696 goto cannot_emulate;
9dac77fa 4697 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4698 break;
b2833e3c 4699 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4700 if (test_cc(ctxt->b, ctxt->eflags))
4701 jmp_rel(ctxt, ctxt->src.val);
018a98db 4702 break;
7e0b54b1 4703 case 0x8d: /* lea r16/r32, m */
9dac77fa 4704 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4705 break;
3d9e77df 4706 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4707 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4708 ctxt->dst.type = OP_NONE;
4709 else
4710 rc = em_xchg(ctxt);
e4f973ae 4711 break;
e8b6fa70 4712 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4713 switch (ctxt->op_bytes) {
4714 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4715 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4716 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4717 }
4718 break;
6e154e56 4719 case 0xcc: /* int3 */
5c5df76b
TY		 4720 rc = emulate_int(ctxt, 3);
4721 break;
6e154e56 4722 case 0xcd: /* int n */
9dac77fa 4723 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4724 break;
4725 case 0xce: /* into */
5c5df76b
TY		 4726 if (ctxt->eflags & EFLG_OF)
4727 rc = emulate_int(ctxt, 4);
6e154e56 4728 break;
1a52e051 4729 case 0xe9: /* jmp rel */
db5b0762 4730 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4731 jmp_rel(ctxt, ctxt->src.val);
4732 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4733 break;
111de5d6 4734 case 0xf4: /* hlt */
6c3287f7 4735 ctxt->ops->halt(ctxt);
19fdfa0d 4736 break;
111de5d6
AK		 4737 case 0xf5: /* cmc */
4738 /* complement carry flag from eflags reg */
4739 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4740 break;
4741 case 0xf8: /* clc */
4742 ctxt->eflags &= ~EFLG_CF;
111de5d6 4743 break;
8744aa9a
MG		 4744 case 0xf9: /* stc */
4745 ctxt->eflags |= EFLG_CF;
4746 break;
fb4616f4
MG		 4747 case 0xfc: /* cld */
4748 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4749 break;
4750 case 0xfd: /* std */
4751 ctxt->eflags |= EFLG_DF;
fb4616f4 4752 break;
91269b8f
AK		 4753 default:
4754 goto cannot_emulate;
6aa8b732 4755 }
018a98db 4756
7d9ddaed
AK		 4757 if (rc != X86EMUL_CONTINUE)
4758 goto done;
4759
018a98db 4760writeback:
fb32b1ed
AK		 4761 if (ctxt->d & SrcWrite) {
4762 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4763 rc = writeback(ctxt, &ctxt->src);
4764 if (rc != X86EMUL_CONTINUE)
4765 goto done;
4766 }
ee212297
NA		 4767 if (!(ctxt->d & NoWrite)) {
4768 rc = writeback(ctxt, &ctxt->dst);
4769 if (rc != X86EMUL_CONTINUE)
4770 goto done;
4771 }
018a98db 4772
5cd21917
GN		 4773 /*
4774 * restore dst type in case the decoding will be reused
4775 * (happens for string instruction )
4776 */
9dac77fa 4777 ctxt->dst.type = saved_dst_type;
5cd21917 4778
9dac77fa 4779 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4780 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4781
9dac77fa 4782 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4783 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4784
9dac77fa 4785 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4786 unsigned int count;
9dac77fa 4787 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4788 if ((ctxt->d & SrcMask) == SrcSI)
4789 count = ctxt->src.count;
4790 else
4791 count = ctxt->dst.count;
4792 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4793 -count);
3e2f65d5 4794
d2ddd1c4
GN		 4795 if (!string_insn_completed(ctxt)) {
4796 /*
4797 * Re-enter guest when pio read ahead buffer is empty
4798 * or, if it is not used, after each 1024 iteration.
4799 */
dd856efa 4800 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4801 (r->end == 0 || r->end != r->pos)) {
4802 /*
4803 * Reset read cache. Usually happens before
4804 * decode, but since instruction is restarted
4805 * we have to do it here.
4806 */
9dac77fa 4807 ctxt->mem_read.end = 0;
dd856efa 4808 writeback_registers(ctxt);
d2ddd1c4
GN		 4809 return EMULATION_RESTART;
4810 }
4811 goto done; /* skip rip writeback */
0fa6ccbd 4812 }
5cd21917 4813 }
d2ddd1c4 4814
9dac77fa 4815 ctxt->eip = ctxt->_eip;
018a98db
AK		 4816
4817done:
da9cb575
AK		 4818 if (rc == X86EMUL_PROPAGATE_FAULT)
4819 ctxt->have_exception = true;
775fde86
JR		 4820 if (rc == X86EMUL_INTERCEPTED)
4821 return EMULATION_INTERCEPTED;
4822
dd856efa
AK		 4823 if (rc == X86EMUL_CONTINUE)
4824 writeback_registers(ctxt);
4825
d2ddd1c4 4826 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4827
4828twobyte_insn:
9dac77fa 4829 switch (ctxt->b) {
018a98db 4830 case 0x09: /* wbinvd */
cfb22375 4831 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4832 break;
4833 case 0x08: /* invd */
018a98db
AK		 4834 case 0x0d: /* GrpP (prefetch) */
4835 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4836 case 0x1f: /* nop */
018a98db
AK		 4837 break;
4838 case 0x20: /* mov cr, reg */
9dac77fa 4839 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4840 break;
6aa8b732 4841 case 0x21: /* mov from dr to reg */
9dac77fa 4842 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4843 break;
6aa8b732 4844 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4845 if (test_cc(ctxt->b, ctxt->eflags))
4846 ctxt->dst.val = ctxt->src.val;
4847 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4848 ctxt->op_bytes != 4)
9dac77fa 4849 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4850 break;
b2833e3c 4851 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4852 if (test_cc(ctxt->b, ctxt->eflags))
4853 jmp_rel(ctxt, ctxt->src.val);
018a98db 4854 break;
ee45b58e 4855 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4856 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4857 break;
2a7c5b8b
GC		 4858 case 0xae: /* clflush */
4859 break;
6aa8b732 4860 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4861 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4862 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4863 : (u16) ctxt->src.val;
6aa8b732 4864 break;
6aa8b732 4865 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4866 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4867 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4868 (s16) ctxt->src.val;
6aa8b732 4869 break;
a012e65a 4870 case 0xc3: /* movnti */
9dac77fa 4871 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4872 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4873 (u32) ctxt->src.val;
a012e65a 4874 break;
91269b8f
AK		 4875 default:
4876 goto cannot_emulate;
6aa8b732 4877 }
7d9ddaed 4878
0bc5eedb
BP		 4879threebyte_insn:
4880
7d9ddaed
AK		 4881 if (rc != X86EMUL_CONTINUE)
4882 goto done;
4883
6aa8b732
AK		 4884 goto writeback;
4885
4886cannot_emulate:
a0c0ab2f 4887 return EMULATION_FAILED;
6aa8b732 4888}
dd856efa
AK		 4889
4890void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4891{
4892 invalidate_registers(ctxt);
4893}
4894
4895void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4896{
4897 writeback_registers(ctxt);
4898}
Linux kernel - Deliverables
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