projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: emulate: rework seg_override
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
7b105ca2 517static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 518{
519 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
520 return 0;
521
7b105ca2 522 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 523}
524
35d3d4a1
AK		 525static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
526 u32 error, bool valid)
54b8486f 527{
da9cb575
AK		 528 ctxt->exception.vector = vec;
529 ctxt->exception.error_code = error;
530 ctxt->exception.error_code_valid = valid;
35d3d4a1 531 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 532}
533
3b88e41a
JR		 534static int emulate_db(struct x86_emulate_ctxt *ctxt)
535{
536 return emulate_exception(ctxt, DB_VECTOR, 0, false);
537}
538
35d3d4a1 539static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 540{
35d3d4a1 541 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 542}
543
618ff15d
AK		 544static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
545{
546 return emulate_exception(ctxt, SS_VECTOR, err, true);
547}
548
35d3d4a1 549static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 552}
553
35d3d4a1 554static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 555{
35d3d4a1 556 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 557}
558
34d1f490
AK		 559static int emulate_de(struct x86_emulate_ctxt *ctxt)
560{
35d3d4a1 561 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 562}
563
1253791d
AK		 564static int emulate_nm(struct x86_emulate_ctxt *ctxt)
565{
566 return emulate_exception(ctxt, NM_VECTOR, 0, false);
567}
568
1aa36616
AK		 569static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
570{
571 u16 selector;
572 struct desc_struct desc;
573
574 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
575 return selector;
576}
577
578static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
579 unsigned seg)
580{
581 u16 dummy;
582 u32 base3;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
586 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
587}
588
1c11b376
AK		 589/*
590 * x86 defines three classes of vector instructions: explicitly
591 * aligned, explicitly unaligned, and the rest, which change behaviour
592 * depending on whether they're AVX encoded or not.
593 *
594 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
595 * subject to the same check.
596 */
597static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
598{
599 if (likely(size < 16))
600 return false;
601
602 if (ctxt->d & Aligned)
603 return true;
604 else if (ctxt->d & Unaligned)
605 return false;
606 else if (ctxt->d & Avx)
607 return false;
608 else
609 return true;
610}
611
3d9b938e 612static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 613 struct segmented_address addr,
3d9b938e 614 unsigned size, bool write, bool fetch,
52fd8b44
AK		 615 ulong *linear)
616{
618ff15d
AK		 617 struct desc_struct desc;
618 bool usable;
52fd8b44 619 ulong la;
618ff15d 620 u32 lim;
1aa36616 621 u16 sel;
3a78a4f4 622 unsigned cpl;
52fd8b44 623
7b105ca2 624 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 625 switch (ctxt->mode) {
618ff15d
AK		 626 case X86EMUL_MODE_PROT64:
627 if (((signed long)la << 16) >> 16 != la)
628 return emulate_gp(ctxt, 0);
629 break;
630 default:
1aa36616
AK		 631 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
632 addr.seg);
618ff15d
AK		 633 if (!usable)
634 goto bad;
58b7825b
GN		 635 /* code segment in protected mode or read-only data segment */
636 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
637 || !(desc.type & 2)) && write)
618ff15d
AK		 638 goto bad;
639 /* unreadable code segment */
3d9b938e 640 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 641 goto bad;
642 lim = desc_limit_scaled(&desc);
643 if ((desc.type & 8) || !(desc.type & 4)) {
644 /* expand-up segment */
645 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
646 goto bad;
647 } else {
fc058680 648 /* expand-down segment */
618ff15d
AK		 649 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
650 goto bad;
651 lim = desc.d ? 0xffffffff : 0xffff;
652 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
653 goto bad;
654 }
717746e3 655 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 656 if (!(desc.type & 8)) {
657 /* data segment */
658 if (cpl > desc.dpl)
659 goto bad;
660 } else if ((desc.type & 8) && !(desc.type & 4)) {
661 /* nonconforming code segment */
662 if (cpl != desc.dpl)
663 goto bad;
664 } else if ((desc.type & 8) && (desc.type & 4)) {
665 /* conforming code segment */
666 if (cpl < desc.dpl)
667 goto bad;
668 }
669 break;
670 }
9dac77fa 671 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 672 la &= (u32)-1;
1c11b376
AK		 673 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
674 return emulate_gp(ctxt, 0);
52fd8b44
AK		 675 *linear = la;
676 return X86EMUL_CONTINUE;
618ff15d
AK		 677bad:
678 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 679 return emulate_ss(ctxt, sel);
618ff15d 680 else
0afbe2f8 681 return emulate_gp(ctxt, sel);
52fd8b44
AK		 682}
683
3d9b938e
NE		 684static int linearize(struct x86_emulate_ctxt *ctxt,
685 struct segmented_address addr,
686 unsigned size, bool write,
687 ulong *linear)
688{
689 return __linearize(ctxt, addr, size, write, false, linear);
690}
691
692
3ca3ac4d
AK		 693static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
694 struct segmented_address addr,
695 void *data,
696 unsigned size)
697{
9fa088f4
AK		 698 int rc;
699 ulong linear;
700
83b8795a 701 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 702 if (rc != X86EMUL_CONTINUE)
703 return rc;
0f65dd70 704 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 705}
706
807941b1
TY		 707/*
708 * Fetch the next byte of the instruction being emulated which is pointed to
709 * by ctxt->_eip, then increment ctxt->_eip.
710 *
711 * Also prefetch the remaining bytes of the instruction without crossing page
712 * boundary if they are not in fetch_cache yet.
713 */
714static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 715{
9dac77fa 716 struct fetch_cache *fc = &ctxt->fetch;
62266869 717 int rc;
2fb53ad8 718 int size, cur_size;
62266869 719
807941b1 720 if (ctxt->_eip == fc->end) {
3d9b938e 721 unsigned long linear;
807941b1
TY		 722 struct segmented_address addr = { .seg = VCPU_SREG_CS,
723 .ea = ctxt->_eip };
2fb53ad8 724 cur_size = fc->end - fc->start;
807941b1
TY		 725 size = min(15UL - cur_size,
726 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 727 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 728 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 729 return rc;
ef5d75cc
TY		 730 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
731 size, &ctxt->exception);
7d88bb48 732 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 733 return rc;
2fb53ad8 734 fc->end += size;
62266869 735 }
807941b1
TY		 736 *dest = fc->data[ctxt->_eip - fc->start];
737 ctxt->_eip++;
3e2815e9 738 return X86EMUL_CONTINUE;
62266869
AK		 739}
740
741static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 742 void *dest, unsigned size)
62266869 743{
3e2815e9 744 int rc;
62266869 745
eb3c79e6 746 /* x86 instructions are limited to 15 bytes. */
7d88bb48 747 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 748 return X86EMUL_UNHANDLEABLE;
62266869 749 while (size--) {
807941b1 750 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 751 if (rc != X86EMUL_CONTINUE)
62266869
AK		 752 return rc;
753 }
3e2815e9 754 return X86EMUL_CONTINUE;
62266869
AK		 755}
756
67cbc90d 757/* Fetch next part of the instruction being emulated. */
e85a1085 758#define insn_fetch(_type, _ctxt) \
67cbc90d 759({ unsigned long _x; \
e85a1085 760 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 761 if (rc != X86EMUL_CONTINUE) \
762 goto done; \
67cbc90d
TY		 763 (_type)_x; \
764})
765
807941b1
TY		 766#define insn_fetch_arr(_arr, _size, _ctxt) \
767({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 768 if (rc != X86EMUL_CONTINUE) \
769 goto done; \
67cbc90d
TY		 770})
771
1e3c5cb0
RR		 772/*
773 * Given the 'reg' portion of a ModRM byte, and a register block, return a
774 * pointer into the block that addresses the relevant register.
775 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
776 */
dd856efa 777static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 778 int byteop)
6aa8b732
AK		 779{
780 void *p;
aa9ac1a6 781 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 782
6aa8b732 783 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 784 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
785 else
786 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 787 return p;
788}
789
790static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 791 struct segmented_address addr,
6aa8b732
AK		 792 u16 *size, unsigned long *address, int op_bytes)
793{
794 int rc;
795
796 if (op_bytes == 2)
797 op_bytes = 3;
798 *address = 0;
3ca3ac4d 799 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 800 if (rc != X86EMUL_CONTINUE)
6aa8b732 801 return rc;
30b31ab6 802 addr.ea += 2;
3ca3ac4d 803 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 804 return rc;
805}
806
34b77652
AK		 807FASTOP2(add);
808FASTOP2(or);
809FASTOP2(adc);
810FASTOP2(sbb);
811FASTOP2(and);
812FASTOP2(sub);
813FASTOP2(xor);
814FASTOP2(cmp);
815FASTOP2(test);
816
b9fa409b
AK		 817FASTOP1SRC2(mul, mul_ex);
818FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 819FASTOP1SRC2EX(div, div_ex);
820FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 821
34b77652
AK		 822FASTOP3WCL(shld);
823FASTOP3WCL(shrd);
824
825FASTOP2W(imul);
826
827FASTOP1(not);
828FASTOP1(neg);
829FASTOP1(inc);
830FASTOP1(dec);
831
832FASTOP2CL(rol);
833FASTOP2CL(ror);
834FASTOP2CL(rcl);
835FASTOP2CL(rcr);
836FASTOP2CL(shl);
837FASTOP2CL(shr);
838FASTOP2CL(sar);
839
840FASTOP2W(bsf);
841FASTOP2W(bsr);
842FASTOP2W(bt);
843FASTOP2W(bts);
844FASTOP2W(btr);
845FASTOP2W(btc);
846
e47a5f5f
AK		 847FASTOP2(xadd);
848
9ae9feba 849static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 850{
9ae9feba
AK		 851 u8 rc;
852 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 853
9ae9feba 854 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 855 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 856 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
857 return rc;
bbe9abbd
NK		 858}
859
91ff3cb4
AK		 860static void fetch_register_operand(struct operand *op)
861{
862 switch (op->bytes) {
863 case 1:
864 op->val = *(u8 *)op->addr.reg;
865 break;
866 case 2:
867 op->val = *(u16 *)op->addr.reg;
868 break;
869 case 4:
870 op->val = *(u32 *)op->addr.reg;
871 break;
872 case 8:
873 op->val = *(u64 *)op->addr.reg;
874 break;
875 }
876}
877
1253791d
AK		 878static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
879{
880 ctxt->ops->get_fpu(ctxt);
881 switch (reg) {
89a87c67
MK		 882 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
883 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
884 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
885 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
886 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
887 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
888 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
889 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 890#ifdef CONFIG_X86_64
89a87c67
MK		 891 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
892 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
893 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
894 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
895 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
896 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
897 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
898 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 899#endif
900 default: BUG();
901 }
902 ctxt->ops->put_fpu(ctxt);
903}
904
905static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
906 int reg)
907{
908 ctxt->ops->get_fpu(ctxt);
909 switch (reg) {
89a87c67
MK		 910 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
911 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
912 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
913 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
914 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
915 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
916 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
917 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 918#ifdef CONFIG_X86_64
89a87c67
MK		 919 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
920 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
921 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
922 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
923 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
924 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
925 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
926 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 927#endif
928 default: BUG();
929 }
930 ctxt->ops->put_fpu(ctxt);
931}
932
cbe2c9d3
AK		 933static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
934{
935 ctxt->ops->get_fpu(ctxt);
936 switch (reg) {
937 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
938 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
939 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
940 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
941 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
942 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
943 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
944 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
945 default: BUG();
946 }
947 ctxt->ops->put_fpu(ctxt);
948}
949
950static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
951{
952 ctxt->ops->get_fpu(ctxt);
953 switch (reg) {
954 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
955 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
956 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
957 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
958 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
959 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
960 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
961 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
962 default: BUG();
963 }
964 ctxt->ops->put_fpu(ctxt);
965}
966
045a282c
GN		 967static int em_fninit(struct x86_emulate_ctxt *ctxt)
968{
969 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
970 return emulate_nm(ctxt);
971
972 ctxt->ops->get_fpu(ctxt);
973 asm volatile("fninit");
974 ctxt->ops->put_fpu(ctxt);
975 return X86EMUL_CONTINUE;
976}
977
978static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
979{
980 u16 fcw;
981
982 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
983 return emulate_nm(ctxt);
984
985 ctxt->ops->get_fpu(ctxt);
986 asm volatile("fnstcw %0": "+m"(fcw));
987 ctxt->ops->put_fpu(ctxt);
988
989 /* force 2 byte destination */
990 ctxt->dst.bytes = 2;
991 ctxt->dst.val = fcw;
992
993 return X86EMUL_CONTINUE;
994}
995
996static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
997{
998 u16 fsw;
999
1000 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1001 return emulate_nm(ctxt);
1002
1003 ctxt->ops->get_fpu(ctxt);
1004 asm volatile("fnstsw %0": "+m"(fsw));
1005 ctxt->ops->put_fpu(ctxt);
1006
1007 /* force 2 byte destination */
1008 ctxt->dst.bytes = 2;
1009 ctxt->dst.val = fsw;
1010
1011 return X86EMUL_CONTINUE;
1012}
1013
1253791d 1014static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1015 struct operand *op)
3c118e24 1016{
9dac77fa 1017 unsigned reg = ctxt->modrm_reg;
33615aa9 1018
9dac77fa
AK		 1019 if (!(ctxt->d & ModRM))
1020 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1021
9dac77fa 1022 if (ctxt->d & Sse) {
1253791d
AK		 1023 op->type = OP_XMM;
1024 op->bytes = 16;
1025 op->addr.xmm = reg;
1026 read_sse_reg(ctxt, &op->vec_val, reg);
1027 return;
1028 }
cbe2c9d3
AK		 1029 if (ctxt->d & Mmx) {
1030 reg &= 7;
1031 op->type = OP_MM;
1032 op->bytes = 8;
1033 op->addr.mm = reg;
1034 return;
1035 }
1253791d 1036
3c118e24 1037 op->type = OP_REG;
6d4d85ec
GN		 1038 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1039 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1040
91ff3cb4 1041 fetch_register_operand(op);
3c118e24
AK		 1042 op->orig_val = op->val;
1043}
1044
a6e3407b
AK		 1045static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1046{
1047 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1048 ctxt->modrm_seg = VCPU_SREG_SS;
1049}
1050
1c73ef66 1051static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1052 struct operand *op)
1c73ef66 1053{
1c73ef66 1054 u8 sib;
02357bdc 1055 int index_reg, base_reg, scale;
3e2815e9 1056 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1057 ulong modrm_ea = 0;
1c73ef66 1058
02357bdc
BD		 1059 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1060 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1061 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1062
02357bdc 1063 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1064 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1065 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1066 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1067
9b88ae99 1068 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1069 op->type = OP_REG;
9dac77fa 1070 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1071 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1072 ctxt->d & ByteOp);
9dac77fa 1073 if (ctxt->d & Sse) {
1253791d
AK		 1074 op->type = OP_XMM;
1075 op->bytes = 16;
9dac77fa
AK		 1076 op->addr.xmm = ctxt->modrm_rm;
1077 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1078 return rc;
1079 }
cbe2c9d3
AK		 1080 if (ctxt->d & Mmx) {
1081 op->type = OP_MM;
1082 op->bytes = 8;
bdc90722 1083 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1084 return rc;
1085 }
2dbd0dd7 1086 fetch_register_operand(op);
1c73ef66
AK		 1087 return rc;
1088 }
1089
2dbd0dd7
AK		 1090 op->type = OP_MEM;
1091
9dac77fa 1092 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1093 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1094 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1095 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1096 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1097
1098 /* 16-bit ModR/M decode. */
9dac77fa 1099 switch (ctxt->modrm_mod) {
1c73ef66 1100 case 0:
9dac77fa 1101 if (ctxt->modrm_rm == 6)
e85a1085 1102 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1103 break;
1104 case 1:
e85a1085 1105 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1106 break;
1107 case 2:
e85a1085 1108 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1109 break;
1110 }
9dac77fa 1111 switch (ctxt->modrm_rm) {
1c73ef66 1112 case 0:
2dbd0dd7 1113 modrm_ea += bx + si;
1c73ef66
AK		 1114 break;
1115 case 1:
2dbd0dd7 1116 modrm_ea += bx + di;
1c73ef66
AK		 1117 break;
1118 case 2:
2dbd0dd7 1119 modrm_ea += bp + si;
1c73ef66
AK		 1120 break;
1121 case 3:
2dbd0dd7 1122 modrm_ea += bp + di;
1c73ef66
AK		 1123 break;
1124 case 4:
2dbd0dd7 1125 modrm_ea += si;
1c73ef66
AK		 1126 break;
1127 case 5:
2dbd0dd7 1128 modrm_ea += di;
1c73ef66
AK		 1129 break;
1130 case 6:
9dac77fa 1131 if (ctxt->modrm_mod != 0)
2dbd0dd7 1132 modrm_ea += bp;
1c73ef66
AK		 1133 break;
1134 case 7:
2dbd0dd7 1135 modrm_ea += bx;
1c73ef66
AK		 1136 break;
1137 }
9dac77fa
AK		 1138 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1139 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1140 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1141 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1142 } else {
1143 /* 32/64-bit ModR/M decode. */
9dac77fa 1144 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1145 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1146 index_reg |= (sib >> 3) & 7;
1147 base_reg |= sib & 7;
1148 scale = sib >> 6;
1149
9dac77fa 1150 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1151 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1152 else {
dd856efa 1153 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1154 adjust_modrm_seg(ctxt, base_reg);
1155 }
dc71d0f1 1156 if (index_reg != 4)
dd856efa 1157 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1158 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1159 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1160 ctxt->rip_relative = 1;
a6e3407b
AK		 1161 } else {
1162 base_reg = ctxt->modrm_rm;
dd856efa 1163 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1164 adjust_modrm_seg(ctxt, base_reg);
1165 }
9dac77fa 1166 switch (ctxt->modrm_mod) {
1c73ef66 1167 case 0:
9dac77fa 1168 if (ctxt->modrm_rm == 5)
e85a1085 1169 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1170 break;
1171 case 1:
e85a1085 1172 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1173 break;
1174 case 2:
e85a1085 1175 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1176 break;
1177 }
1178 }
90de84f5 1179 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1180done:
1181 return rc;
1182}
1183
1184static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1185 struct operand *op)
1c73ef66 1186{
3e2815e9 1187 int rc = X86EMUL_CONTINUE;
1c73ef66 1188
2dbd0dd7 1189 op->type = OP_MEM;
9dac77fa 1190 switch (ctxt->ad_bytes) {
1c73ef66 1191 case 2:
e85a1085 1192 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1193 break;
1194 case 4:
e85a1085 1195 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1196 break;
1197 case 8:
e85a1085 1198 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1199 break;
1200 }
1201done:
1202 return rc;
1203}
1204
9dac77fa 1205static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1206{
7129eeca 1207 long sv = 0, mask;
35c843c4 1208
9dac77fa 1209 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1210 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1211
9dac77fa
AK		 1212 if (ctxt->src.bytes == 2)
1213 sv = (s16)ctxt->src.val & (s16)mask;
1214 else if (ctxt->src.bytes == 4)
1215 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1216 else
1217 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1218
9dac77fa 1219 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1220 }
ba7ff2b7
WY		 1221
1222 /* only subword offset */
9dac77fa 1223 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1224}
1225
dde7e6d1 1226static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1227 unsigned long addr, void *dest, unsigned size)
6aa8b732 1228{
dde7e6d1 1229 int rc;
9dac77fa 1230 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1231
f23b070e
XG		 1232 if (mc->pos < mc->end)
1233 goto read_cached;
6aa8b732 1234
f23b070e
XG		 1235 WARN_ON((mc->end + size) >= sizeof(mc->data));
1236
1237 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1238 &ctxt->exception);
1239 if (rc != X86EMUL_CONTINUE)
1240 return rc;
1241
1242 mc->end += size;
1243
1244read_cached:
1245 memcpy(dest, mc->data + mc->pos, size);
1246 mc->pos += size;
dde7e6d1
AK		 1247 return X86EMUL_CONTINUE;
1248}
6aa8b732 1249
3ca3ac4d
AK		 1250static int segmented_read(struct x86_emulate_ctxt *ctxt,
1251 struct segmented_address addr,
1252 void *data,
1253 unsigned size)
1254{
9fa088f4
AK		 1255 int rc;
1256 ulong linear;
1257
83b8795a 1258 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1259 if (rc != X86EMUL_CONTINUE)
1260 return rc;
7b105ca2 1261 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1262}
1263
1264static int segmented_write(struct x86_emulate_ctxt *ctxt,
1265 struct segmented_address addr,
1266 const void *data,
1267 unsigned size)
1268{
9fa088f4
AK		 1269 int rc;
1270 ulong linear;
1271
83b8795a 1272 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1273 if (rc != X86EMUL_CONTINUE)
1274 return rc;
0f65dd70
AK		 1275 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1276 &ctxt->exception);
3ca3ac4d
AK		 1277}
1278
1279static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1280 struct segmented_address addr,
1281 const void *orig_data, const void *data,
1282 unsigned size)
1283{
9fa088f4
AK		 1284 int rc;
1285 ulong linear;
1286
83b8795a 1287 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1288 if (rc != X86EMUL_CONTINUE)
1289 return rc;
0f65dd70
AK		 1290 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1291 size, &ctxt->exception);
3ca3ac4d
AK		 1292}
1293
dde7e6d1 1294static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1295 unsigned int size, unsigned short port,
1296 void *dest)
1297{
9dac77fa 1298 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1299
dde7e6d1 1300 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1301 unsigned int in_page, n;
9dac77fa 1302 unsigned int count = ctxt->rep_prefix ?
dd856efa 1303 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1304 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1305 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1306 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1307 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1308 count);
1309 if (n == 0)
1310 n = 1;
1311 rc->pos = rc->end = 0;
7b105ca2 1312 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1313 return 0;
1314 rc->end = n * size;
6aa8b732
AK		 1315 }
1316
e6e39f04
NA		 1317 if (ctxt->rep_prefix && (ctxt->d & String) &&
1318 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1319 ctxt->dst.data = rc->data + rc->pos;
1320 ctxt->dst.type = OP_MEM_STR;
1321 ctxt->dst.count = (rc->end - rc->pos) / size;
1322 rc->pos = rc->end;
1323 } else {
1324 memcpy(dest, rc->data + rc->pos, size);
1325 rc->pos += size;
1326 }
dde7e6d1
AK		 1327 return 1;
1328}
6aa8b732 1329
7f3d35fd
KW		 1330static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1331 u16 index, struct desc_struct *desc)
1332{
1333 struct desc_ptr dt;
1334 ulong addr;
1335
1336 ctxt->ops->get_idt(ctxt, &dt);
1337
1338 if (dt.size < index * 8 + 7)
1339 return emulate_gp(ctxt, index << 3 | 0x2);
1340
1341 addr = dt.address + index * 8;
1342 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1343 &ctxt->exception);
1344}
1345
dde7e6d1 1346static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1347 u16 selector, struct desc_ptr *dt)
1348{
0225fb50 1349 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1350 u32 base3 = 0;
7b105ca2 1351
dde7e6d1
AK		 1352 if (selector & 1 << 2) {
1353 struct desc_struct desc;
1aa36616
AK		 1354 u16 sel;
1355
dde7e6d1 1356 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1357 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1358 VCPU_SREG_LDTR))
dde7e6d1 1359 return;
e09d082c 1360
dde7e6d1 1361 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1362 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1363 } else
4bff1e86 1364 ops->get_gdt(ctxt, dt);
dde7e6d1 1365}
120df890 1366
dde7e6d1
AK		 1367/* allowed just for 8 bytes segments */
1368static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1369 u16 selector, struct desc_struct *desc,
1370 ulong *desc_addr_p)
dde7e6d1
AK		 1371{
1372 struct desc_ptr dt;
1373 u16 index = selector >> 3;
dde7e6d1 1374 ulong addr;
120df890 1375
7b105ca2 1376 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1377
35d3d4a1
AK		 1378 if (dt.size < index * 8 + 7)
1379 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1380
e919464b 1381 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1382 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1383 &ctxt->exception);
dde7e6d1 1384}
ef65c889 1385
dde7e6d1
AK		 1386/* allowed just for 8 bytes segments */
1387static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1388 u16 selector, struct desc_struct *desc)
1389{
1390 struct desc_ptr dt;
1391 u16 index = selector >> 3;
dde7e6d1 1392 ulong addr;
6aa8b732 1393
7b105ca2 1394 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1395
35d3d4a1
AK		 1396 if (dt.size < index * 8 + 7)
1397 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1398
dde7e6d1 1399 addr = dt.address + index * 8;
7b105ca2
TY		 1400 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1401 &ctxt->exception);
dde7e6d1 1402}
c7e75a3d 1403
5601d05b 1404/* Does not support long mode */
2356aaeb 1405static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1406 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1407{
869be99c 1408 struct desc_struct seg_desc, old_desc;
2356aaeb 1409 u8 dpl, rpl;
dde7e6d1
AK		 1410 unsigned err_vec = GP_VECTOR;
1411 u32 err_code = 0;
1412 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1413 ulong desc_addr;
dde7e6d1 1414 int ret;
03ebebeb 1415 u16 dummy;
e37a75a1 1416 u32 base3 = 0;
69f55cb1 1417
dde7e6d1 1418 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1419
f8da94e9
KW		 1420 if (ctxt->mode == X86EMUL_MODE_REAL) {
1421 /* set real mode segment descriptor (keep limit etc. for
1422 * unreal mode) */
03ebebeb 1423 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1424 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1425 goto load;
f8da94e9
KW		 1426 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1427 /* VM86 needs a clean new segment descriptor */
1428 set_desc_base(&seg_desc, selector << 4);
1429 set_desc_limit(&seg_desc, 0xffff);
1430 seg_desc.type = 3;
1431 seg_desc.p = 1;
1432 seg_desc.s = 1;
1433 seg_desc.dpl = 3;
1434 goto load;
dde7e6d1
AK		 1435 }
1436
79d5b4c3 1437 rpl = selector & 3;
79d5b4c3
AK		 1438
1439 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1440 if ((seg == VCPU_SREG_CS
1441 || (seg == VCPU_SREG_SS
1442 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1443 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1444 && null_selector)
1445 goto exception;
1446
1447 /* TR should be in GDT only */
1448 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1449 goto exception;
1450
1451 if (null_selector) /* for NULL selector skip all following checks */
1452 goto load;
1453
e919464b 1454 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1455 if (ret != X86EMUL_CONTINUE)
1456 return ret;
1457
1458 err_code = selector & 0xfffc;
1459 err_vec = GP_VECTOR;
1460
fc058680 1461 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1462 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1463 goto exception;
1464
1465 if (!seg_desc.p) {
1466 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1467 goto exception;
1468 }
1469
dde7e6d1 1470 dpl = seg_desc.dpl;
dde7e6d1
AK		 1471
1472 switch (seg) {
1473 case VCPU_SREG_SS:
1474 /*
1475 * segment is not a writable data segment or segment
1476 * selector's RPL != CPL or segment selector's RPL != CPL
1477 */
1478 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1479 goto exception;
6aa8b732 1480 break;
dde7e6d1 1481 case VCPU_SREG_CS:
5045b468
PB		 1482 if (in_task_switch && rpl != dpl)
1483 goto exception;
1484
dde7e6d1
AK		 1485 if (!(seg_desc.type & 8))
1486 goto exception;
1487
1488 if (seg_desc.type & 4) {
1489 /* conforming */
1490 if (dpl > cpl)
1491 goto exception;
1492 } else {
1493 /* nonconforming */
1494 if (rpl > cpl || dpl != cpl)
1495 goto exception;
1496 }
1497 /* CS(RPL) <- CPL */
1498 selector = (selector & 0xfffc) | cpl;
6aa8b732 1499 break;
dde7e6d1
AK		 1500 case VCPU_SREG_TR:
1501 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1502 goto exception;
869be99c
AK		 1503 old_desc = seg_desc;
1504 seg_desc.type |= 2; /* busy */
1505 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1506 sizeof(seg_desc), &ctxt->exception);
1507 if (ret != X86EMUL_CONTINUE)
1508 return ret;
dde7e6d1
AK		 1509 break;
1510 case VCPU_SREG_LDTR:
1511 if (seg_desc.s || seg_desc.type != 2)
1512 goto exception;
1513 break;
1514 default: /* DS, ES, FS, or GS */
4e62417b 1515 /*
dde7e6d1
AK		 1516 * segment is not a data or readable code segment or
1517 * ((segment is a data or nonconforming code segment)
1518 * and (both RPL and CPL > DPL))
4e62417b 1519 */
dde7e6d1
AK		 1520 if ((seg_desc.type & 0xa) == 0x8 ||
1521 (((seg_desc.type & 0xc) != 0xc) &&
1522 (rpl > dpl && cpl > dpl)))
1523 goto exception;
6aa8b732 1524 break;
dde7e6d1
AK		 1525 }
1526
1527 if (seg_desc.s) {
1528 /* mark segment as accessed */
1529 seg_desc.type |= 1;
7b105ca2 1530 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1531 if (ret != X86EMUL_CONTINUE)
1532 return ret;
e37a75a1
NA		 1533 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1534 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1535 sizeof(base3), &ctxt->exception);
1536 if (ret != X86EMUL_CONTINUE)
1537 return ret;
dde7e6d1
AK		 1538 }
1539load:
e37a75a1 1540 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1541 return X86EMUL_CONTINUE;
1542exception:
1543 emulate_exception(ctxt, err_vec, err_code, true);
1544 return X86EMUL_PROPAGATE_FAULT;
1545}
1546
2356aaeb
PB		 1547static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1548 u16 selector, int seg)
1549{
1550 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1551 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1552}
1553
31be40b3
WY		 1554static void write_register_operand(struct operand *op)
1555{
1556 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1557 switch (op->bytes) {
1558 case 1:
1559 *(u8 *)op->addr.reg = (u8)op->val;
1560 break;
1561 case 2:
1562 *(u16 *)op->addr.reg = (u16)op->val;
1563 break;
1564 case 4:
1565 *op->addr.reg = (u32)op->val;
1566 break; /* 64b: zero-extend */
1567 case 8:
1568 *op->addr.reg = op->val;
1569 break;
1570 }
1571}
1572
fb32b1ed 1573static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1574{
fb32b1ed 1575 switch (op->type) {
dde7e6d1 1576 case OP_REG:
fb32b1ed 1577 write_register_operand(op);
6aa8b732 1578 break;
dde7e6d1 1579 case OP_MEM:
9dac77fa 1580 if (ctxt->lock_prefix)
f5f87dfb
PB		 1581 return segmented_cmpxchg(ctxt,
1582 op->addr.mem,
1583 &op->orig_val,
1584 &op->val,
1585 op->bytes);
1586 else
1587 return segmented_write(ctxt,
fb32b1ed 1588 op->addr.mem,
fb32b1ed
AK		 1589 &op->val,
1590 op->bytes);
a682e354 1591 break;
b3356bf0 1592 case OP_MEM_STR:
f5f87dfb
PB		 1593 return segmented_write(ctxt,
1594 op->addr.mem,
1595 op->data,
1596 op->bytes * op->count);
b3356bf0 1597 break;
1253791d 1598 case OP_XMM:
fb32b1ed 1599 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1600 break;
cbe2c9d3 1601 case OP_MM:
fb32b1ed 1602 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1603 break;
dde7e6d1
AK		 1604 case OP_NONE:
1605 /* no writeback */
414e6277 1606 break;
dde7e6d1 1607 default:
414e6277 1608 break;
6aa8b732 1609 }
dde7e6d1
AK		 1610 return X86EMUL_CONTINUE;
1611}
6aa8b732 1612
51ddff50 1613static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1614{
4179bb02 1615 struct segmented_address addr;
0dc8d10f 1616
5ad105e5 1617 rsp_increment(ctxt, -bytes);
dd856efa 1618 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1619 addr.seg = VCPU_SREG_SS;
1620
51ddff50
AK		 1621 return segmented_write(ctxt, addr, data, bytes);
1622}
1623
1624static int em_push(struct x86_emulate_ctxt *ctxt)
1625{
4179bb02 1626 /* Disable writeback. */
9dac77fa 1627 ctxt->dst.type = OP_NONE;
51ddff50 1628 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1629}
69f55cb1 1630
dde7e6d1 1631static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1632 void *dest, int len)
1633{
dde7e6d1 1634 int rc;
90de84f5 1635 struct segmented_address addr;
8b4caf66 1636
dd856efa 1637 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1638 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1639 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1640 if (rc != X86EMUL_CONTINUE)
1641 return rc;
1642
5ad105e5 1643 rsp_increment(ctxt, len);
dde7e6d1 1644 return rc;
8b4caf66
LV		 1645}
1646
c54fe504
TY		 1647static int em_pop(struct x86_emulate_ctxt *ctxt)
1648{
9dac77fa 1649 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1650}
1651
dde7e6d1 1652static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1653 void *dest, int len)
9de41573
GN		 1654{
1655 int rc;
dde7e6d1
AK		 1656 unsigned long val, change_mask;
1657 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1658 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1659
3b9be3bf 1660 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1661 if (rc != X86EMUL_CONTINUE)
1662 return rc;
9de41573 1663
dde7e6d1
AK		 1664 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1665 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1666
dde7e6d1
AK		 1667 switch(ctxt->mode) {
1668 case X86EMUL_MODE_PROT64:
1669 case X86EMUL_MODE_PROT32:
1670 case X86EMUL_MODE_PROT16:
1671 if (cpl == 0)
1672 change_mask |= EFLG_IOPL;
1673 if (cpl <= iopl)
1674 change_mask |= EFLG_IF;
1675 break;
1676 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1677 if (iopl < 3)
1678 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1679 change_mask |= EFLG_IF;
1680 break;
1681 default: /* real mode */
1682 change_mask |= (EFLG_IOPL | EFLG_IF);
1683 break;
9de41573 1684 }
dde7e6d1
AK		 1685
1686 *(unsigned long *)dest =
1687 (ctxt->eflags & ~change_mask) | (val & change_mask);
1688
1689 return rc;
9de41573
GN		 1690}
1691
62aaa2f0
TY		 1692static int em_popf(struct x86_emulate_ctxt *ctxt)
1693{
9dac77fa
AK		 1694 ctxt->dst.type = OP_REG;
1695 ctxt->dst.addr.reg = &ctxt->eflags;
1696 ctxt->dst.bytes = ctxt->op_bytes;
1697 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1698}
1699
612e89f0
AK		 1700static int em_enter(struct x86_emulate_ctxt *ctxt)
1701{
1702 int rc;
1703 unsigned frame_size = ctxt->src.val;
1704 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1705 ulong rbp;
612e89f0
AK		 1706
1707 if (nesting_level)
1708 return X86EMUL_UNHANDLEABLE;
1709
dd856efa
AK		 1710 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1711 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1712 if (rc != X86EMUL_CONTINUE)
1713 return rc;
dd856efa 1714 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1715 stack_mask(ctxt));
dd856efa
AK		 1716 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1717 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1718 stack_mask(ctxt));
1719 return X86EMUL_CONTINUE;
1720}
1721
f47cfa31
AK		 1722static int em_leave(struct x86_emulate_ctxt *ctxt)
1723{
dd856efa 1724 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1725 stack_mask(ctxt));
dd856efa 1726 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1727}
1728
1cd196ea 1729static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1730{
1cd196ea
AK		 1731 int seg = ctxt->src2.val;
1732
9dac77fa 1733 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1734
4487b3b4 1735 return em_push(ctxt);
7b262e90
GN		 1736}
1737
1cd196ea 1738static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1739{
1cd196ea 1740 int seg = ctxt->src2.val;
dde7e6d1
AK		 1741 unsigned long selector;
1742 int rc;
38ba30ba 1743
9dac77fa 1744 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1745 if (rc != X86EMUL_CONTINUE)
1746 return rc;
1747
a5457e7b
PB		 1748 if (ctxt->modrm_reg == VCPU_SREG_SS)
1749 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1750
7b105ca2 1751 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1752 return rc;
38ba30ba
GN		 1753}
1754
b96a7fad 1755static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1756{
dd856efa 1757 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1758 int rc = X86EMUL_CONTINUE;
1759 int reg = VCPU_REGS_RAX;
38ba30ba 1760
dde7e6d1
AK		 1761 while (reg <= VCPU_REGS_RDI) {
1762 (reg == VCPU_REGS_RSP) ?
dd856efa 1763 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1764
4487b3b4 1765 rc = em_push(ctxt);
dde7e6d1
AK		 1766 if (rc != X86EMUL_CONTINUE)
1767 return rc;
38ba30ba 1768
dde7e6d1 1769 ++reg;
38ba30ba 1770 }
38ba30ba 1771
dde7e6d1 1772 return rc;
38ba30ba
GN		 1773}
1774
62aaa2f0
TY		 1775static int em_pushf(struct x86_emulate_ctxt *ctxt)
1776{
9dac77fa 1777 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1778 return em_push(ctxt);
1779}
1780
b96a7fad 1781static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1782{
dde7e6d1
AK		 1783 int rc = X86EMUL_CONTINUE;
1784 int reg = VCPU_REGS_RDI;
38ba30ba 1785
dde7e6d1
AK		 1786 while (reg >= VCPU_REGS_RAX) {
1787 if (reg == VCPU_REGS_RSP) {
5ad105e5 1788 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1789 --reg;
1790 }
38ba30ba 1791
dd856efa 1792 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1793 if (rc != X86EMUL_CONTINUE)
1794 break;
1795 --reg;
38ba30ba 1796 }
dde7e6d1 1797 return rc;
38ba30ba
GN		 1798}
1799
dd856efa 1800static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1801{
0225fb50 1802 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1803 int rc;
6e154e56
MG		 1804 struct desc_ptr dt;
1805 gva_t cs_addr;
1806 gva_t eip_addr;
1807 u16 cs, eip;
6e154e56
MG		 1808
1809 /* TODO: Add limit checks */
9dac77fa 1810 ctxt->src.val = ctxt->eflags;
4487b3b4 1811 rc = em_push(ctxt);
5c56e1cf
AK		 1812 if (rc != X86EMUL_CONTINUE)
1813 return rc;
6e154e56
MG		 1814
1815 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1816
9dac77fa 1817 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1818 rc = em_push(ctxt);
5c56e1cf
AK		 1819 if (rc != X86EMUL_CONTINUE)
1820 return rc;
6e154e56 1821
9dac77fa 1822 ctxt->src.val = ctxt->_eip;
4487b3b4 1823 rc = em_push(ctxt);
5c56e1cf
AK		 1824 if (rc != X86EMUL_CONTINUE)
1825 return rc;
1826
4bff1e86 1827 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1828
1829 eip_addr = dt.address + (irq << 2);
1830 cs_addr = dt.address + (irq << 2) + 2;
1831
0f65dd70 1832 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
1835
0f65dd70 1836 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1837 if (rc != X86EMUL_CONTINUE)
1838 return rc;
1839
7b105ca2 1840 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1841 if (rc != X86EMUL_CONTINUE)
1842 return rc;
1843
9dac77fa 1844 ctxt->_eip = eip;
6e154e56
MG		 1845
1846 return rc;
1847}
1848
dd856efa
AK		 1849int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1850{
1851 int rc;
1852
1853 invalidate_registers(ctxt);
1854 rc = __emulate_int_real(ctxt, irq);
1855 if (rc == X86EMUL_CONTINUE)
1856 writeback_registers(ctxt);
1857 return rc;
1858}
1859
7b105ca2 1860static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1861{
1862 switch(ctxt->mode) {
1863 case X86EMUL_MODE_REAL:
dd856efa 1864 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1865 case X86EMUL_MODE_VM86:
1866 case X86EMUL_MODE_PROT16:
1867 case X86EMUL_MODE_PROT32:
1868 case X86EMUL_MODE_PROT64:
1869 default:
1870 /* Protected mode interrupts unimplemented yet */
1871 return X86EMUL_UNHANDLEABLE;
1872 }
1873}
1874
7b105ca2 1875static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1876{
dde7e6d1
AK		 1877 int rc = X86EMUL_CONTINUE;
1878 unsigned long temp_eip = 0;
1879 unsigned long temp_eflags = 0;
1880 unsigned long cs = 0;
1881 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1882 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1883 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1884 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1885
dde7e6d1 1886 /* TODO: Add stack limit check */
38ba30ba 1887
9dac77fa 1888 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1889
dde7e6d1
AK		 1890 if (rc != X86EMUL_CONTINUE)
1891 return rc;
38ba30ba 1892
35d3d4a1
AK		 1893 if (temp_eip & ~0xffff)
1894 return emulate_gp(ctxt, 0);
38ba30ba 1895
9dac77fa 1896 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1897
dde7e6d1
AK		 1898 if (rc != X86EMUL_CONTINUE)
1899 return rc;
38ba30ba 1900
9dac77fa 1901 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1902
dde7e6d1
AK		 1903 if (rc != X86EMUL_CONTINUE)
1904 return rc;
38ba30ba 1905
7b105ca2 1906 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1907
dde7e6d1
AK		 1908 if (rc != X86EMUL_CONTINUE)
1909 return rc;
38ba30ba 1910
9dac77fa 1911 ctxt->_eip = temp_eip;
38ba30ba 1912
38ba30ba 1913
9dac77fa 1914 if (ctxt->op_bytes == 4)
dde7e6d1 1915 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1916 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1917 ctxt->eflags &= ~0xffff;
1918 ctxt->eflags |= temp_eflags;
38ba30ba 1919 }
dde7e6d1
AK		 1920
1921 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1922 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1923
1924 return rc;
38ba30ba
GN		 1925}
1926
e01991e7 1927static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1928{
dde7e6d1
AK		 1929 switch(ctxt->mode) {
1930 case X86EMUL_MODE_REAL:
7b105ca2 1931 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1932 case X86EMUL_MODE_VM86:
1933 case X86EMUL_MODE_PROT16:
1934 case X86EMUL_MODE_PROT32:
1935 case X86EMUL_MODE_PROT64:
c37eda13 1936 default:
dde7e6d1
AK		 1937 /* iret from protected mode unimplemented yet */
1938 return X86EMUL_UNHANDLEABLE;
c37eda13 1939 }
c37eda13
WY		 1940}
1941
d2f62766
TY		 1942static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1943{
d2f62766
TY		 1944 int rc;
1945 unsigned short sel;
1946
9dac77fa 1947 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1948
7b105ca2 1949 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1950 if (rc != X86EMUL_CONTINUE)
1951 return rc;
1952
9dac77fa
AK		 1953 ctxt->_eip = 0;
1954 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1955 return X86EMUL_CONTINUE;
1956}
1957
51187683 1958static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1959{
4179bb02 1960 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1961
9dac77fa 1962 switch (ctxt->modrm_reg) {
d19292e4
MG		 1963 case 2: /* call near abs */ {
1964 long int old_eip;
9dac77fa
AK		 1965 old_eip = ctxt->_eip;
1966 ctxt->_eip = ctxt->src.val;
1967 ctxt->src.val = old_eip;
4487b3b4 1968 rc = em_push(ctxt);
d19292e4
MG		 1969 break;
1970 }
8cdbd2c9 1971 case 4: /* jmp abs */
9dac77fa 1972 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1973 break;
d2f62766
TY		 1974 case 5: /* jmp far */
1975 rc = em_jmp_far(ctxt);
1976 break;
8cdbd2c9 1977 case 6: /* push */
4487b3b4 1978 rc = em_push(ctxt);
8cdbd2c9 1979 break;
8cdbd2c9 1980 }
4179bb02 1981 return rc;
8cdbd2c9
LV		 1982}
1983
e0dac408 1984static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1985{
9dac77fa 1986 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1987
aaa05f24
NA		 1988 if (ctxt->dst.bytes == 16)
1989 return X86EMUL_UNHANDLEABLE;
1990
dd856efa
AK		 1991 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1992 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1993 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1994 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 1995 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1996 } else {
dd856efa
AK		 1997 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
1998 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 1999
05f086f8 2000 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2001 }
1b30eaa8 2002 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2003}
2004
ebda02c2
TY		 2005static int em_ret(struct x86_emulate_ctxt *ctxt)
2006{
9dac77fa
AK		 2007 ctxt->dst.type = OP_REG;
2008 ctxt->dst.addr.reg = &ctxt->_eip;
2009 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2010 return em_pop(ctxt);
2011}
2012
e01991e7 2013static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2014{
a77ab5ea
AK		 2015 int rc;
2016 unsigned long cs;
9e8919ae 2017 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2018
9dac77fa 2019 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2020 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2021 return rc;
9dac77fa
AK		 2022 if (ctxt->op_bytes == 4)
2023 ctxt->_eip = (u32)ctxt->_eip;
2024 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2025 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2026 return rc;
9e8919ae
NA		 2027 /* Outer-privilege level return is not implemented */
2028 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2029 return X86EMUL_UNHANDLEABLE;
7b105ca2 2030 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2031 return rc;
2032}
2033
3261107e
BR		 2034static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2035{
2036 int rc;
2037
2038 rc = em_ret_far(ctxt);
2039 if (rc != X86EMUL_CONTINUE)
2040 return rc;
2041 rsp_increment(ctxt, ctxt->src.val);
2042 return X86EMUL_CONTINUE;
2043}
2044
e940b5c2
TY		 2045static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2046{
2047 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2048 ctxt->dst.orig_val = ctxt->dst.val;
2049 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2050 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2051 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2052 fastop(ctxt, em_cmp);
e940b5c2
TY		 2053
2054 if (ctxt->eflags & EFLG_ZF) {
2055 /* Success: write back to memory. */
2056 ctxt->dst.val = ctxt->src.orig_val;
2057 } else {
2058 /* Failure: write the value we saw to EAX. */
2059 ctxt->dst.type = OP_REG;
dd856efa 2060 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2061 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2062 }
2063 return X86EMUL_CONTINUE;
2064}
2065
d4b4325f 2066static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2067{
d4b4325f 2068 int seg = ctxt->src2.val;
09b5f4d3
WY		 2069 unsigned short sel;
2070 int rc;
2071
9dac77fa 2072 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2073
7b105ca2 2074 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2075 if (rc != X86EMUL_CONTINUE)
2076 return rc;
2077
9dac77fa 2078 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2079 return rc;
2080}
2081
7b105ca2 2082static void
e66bb2cc 2083setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2084 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2085{
e66bb2cc 2086 cs->l = 0; /* will be adjusted later */
79168fd1 2087 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2088 cs->g = 1; /* 4kb granularity */
79168fd1 2089 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2090 cs->type = 0x0b; /* Read, Execute, Accessed */
2091 cs->s = 1;
2092 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2093 cs->p = 1;
2094 cs->d = 1;
99245b50 2095 cs->avl = 0;
e66bb2cc 2096
79168fd1
GN		 2097 set_desc_base(ss, 0); /* flat segment */
2098 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2099 ss->g = 1; /* 4kb granularity */
2100 ss->s = 1;
2101 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2102 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2103 ss->dpl = 0;
79168fd1 2104 ss->p = 1;
99245b50
GN		 2105 ss->l = 0;
2106 ss->avl = 0;
e66bb2cc
AP		 2107}
2108
1a18a69b
AK		 2109static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2110{
2111 u32 eax, ebx, ecx, edx;
2112
2113 eax = ecx = 0;
0017f93a
AK		 2114 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2115 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2116 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2117 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2118}
2119
c2226fc9
SB		 2120static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2121{
0225fb50 2122 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2123 u32 eax, ebx, ecx, edx;
2124
2125 /*
2126 * syscall should always be enabled in longmode - so only become
2127 * vendor specific (cpuid) if other modes are active...
2128 */
2129 if (ctxt->mode == X86EMUL_MODE_PROT64)
2130 return true;
2131
2132 eax = 0x00000000;
2133 ecx = 0x00000000;
0017f93a
AK		 2134 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2135 /*
2136 * Intel ("GenuineIntel")
2137 * remark: Intel CPUs only support "syscall" in 64bit
2138 * longmode. Also an 64bit guest with a
2139 * 32bit compat-app running will #UD !! While this
2140 * behaviour can be fixed (by emulating) into AMD
2141 * response - CPUs of AMD can't behave like Intel.
2142 */
2143 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2144 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2145 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2146 return false;
2147
2148 /* AMD ("AuthenticAMD") */
2149 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2150 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2151 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2152 return true;
2153
2154 /* AMD ("AMDisbetter!") */
2155 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2156 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2157 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2158 return true;
c2226fc9
SB		 2159
2160 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2161 return false;
2162}
2163
e01991e7 2164static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2165{
0225fb50 2166 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2167 struct desc_struct cs, ss;
e66bb2cc 2168 u64 msr_data;
79168fd1 2169 u16 cs_sel, ss_sel;
c2ad2bb3 2170 u64 efer = 0;
e66bb2cc
AP		 2171
2172 /* syscall is not available in real mode */
2e901c4c 2173 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2174 ctxt->mode == X86EMUL_MODE_VM86)
2175 return emulate_ud(ctxt);
e66bb2cc 2176
c2226fc9
SB		 2177 if (!(em_syscall_is_enabled(ctxt)))
2178 return emulate_ud(ctxt);
2179
c2ad2bb3 2180 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2181 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2182
c2226fc9
SB		 2183 if (!(efer & EFER_SCE))
2184 return emulate_ud(ctxt);
2185
717746e3 2186 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2187 msr_data >>= 32;
79168fd1
GN		 2188 cs_sel = (u16)(msr_data & 0xfffc);
2189 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2190
c2ad2bb3 2191 if (efer & EFER_LMA) {
79168fd1 2192 cs.d = 0;
e66bb2cc
AP		 2193 cs.l = 1;
2194 }
1aa36616
AK		 2195 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2196 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2197
dd856efa 2198 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2199 if (efer & EFER_LMA) {
e66bb2cc 2200#ifdef CONFIG_X86_64
dd856efa 2201 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2202
717746e3 2203 ops->get_msr(ctxt,
3fb1b5db
GN		 2204 ctxt->mode == X86EMUL_MODE_PROT64 ?
2205 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2206 ctxt->_eip = msr_data;
e66bb2cc 2207
717746e3 2208 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2209 ctxt->eflags &= ~(msr_data | EFLG_RF);
2210#endif
2211 } else {
2212 /* legacy mode */
717746e3 2213 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2214 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2215
2216 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2217 }
2218
e54cfa97 2219 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2220}
2221
e01991e7 2222static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2223{
0225fb50 2224 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2225 struct desc_struct cs, ss;
8c604352 2226 u64 msr_data;
79168fd1 2227 u16 cs_sel, ss_sel;
c2ad2bb3 2228 u64 efer = 0;
8c604352 2229
7b105ca2 2230 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2231 /* inject #GP if in real mode */
35d3d4a1
AK		 2232 if (ctxt->mode == X86EMUL_MODE_REAL)
2233 return emulate_gp(ctxt, 0);
8c604352 2234
1a18a69b
AK		 2235 /*
2236 * Not recognized on AMD in compat mode (but is recognized in legacy
2237 * mode).
2238 */
2239 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2240 && !vendor_intel(ctxt))
2241 return emulate_ud(ctxt);
2242
8c604352
AP		 2243 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2244 * Therefore, we inject an #UD.
2245 */
35d3d4a1
AK		 2246 if (ctxt->mode == X86EMUL_MODE_PROT64)
2247 return emulate_ud(ctxt);
8c604352 2248
7b105ca2 2249 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2250
717746e3 2251 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2252 switch (ctxt->mode) {
2253 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2254 if ((msr_data & 0xfffc) == 0x0)
2255 return emulate_gp(ctxt, 0);
8c604352
AP		 2256 break;
2257 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2258 if (msr_data == 0x0)
2259 return emulate_gp(ctxt, 0);
8c604352 2260 break;
9d1b39a9
GN		 2261 default:
2262 break;
8c604352
AP		 2263 }
2264
2265 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2266 cs_sel = (u16)msr_data;
2267 cs_sel &= ~SELECTOR_RPL_MASK;
2268 ss_sel = cs_sel + 8;
2269 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2270 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2271 cs.d = 0;
8c604352
AP		 2272 cs.l = 1;
2273 }
2274
1aa36616
AK		 2275 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2276 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2277
717746e3 2278 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2279 ctxt->_eip = msr_data;
8c604352 2280
717746e3 2281 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2282 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2283
e54cfa97 2284 return X86EMUL_CONTINUE;
8c604352
AP		 2285}
2286
e01991e7 2287static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2288{
0225fb50 2289 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2290 struct desc_struct cs, ss;
4668f050
AP		 2291 u64 msr_data;
2292 int usermode;
1249b96e 2293 u16 cs_sel = 0, ss_sel = 0;
4668f050 2294
a0044755
GN		 2295 /* inject #GP if in real mode or Virtual 8086 mode */
2296 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2297 ctxt->mode == X86EMUL_MODE_VM86)
2298 return emulate_gp(ctxt, 0);
4668f050 2299
7b105ca2 2300 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2301
9dac77fa 2302 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2303 usermode = X86EMUL_MODE_PROT64;
2304 else
2305 usermode = X86EMUL_MODE_PROT32;
2306
2307 cs.dpl = 3;
2308 ss.dpl = 3;
717746e3 2309 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2310 switch (usermode) {
2311 case X86EMUL_MODE_PROT32:
79168fd1 2312 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2313 if ((msr_data & 0xfffc) == 0x0)
2314 return emulate_gp(ctxt, 0);
79168fd1 2315 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2316 break;
2317 case X86EMUL_MODE_PROT64:
79168fd1 2318 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2319 if (msr_data == 0x0)
2320 return emulate_gp(ctxt, 0);
79168fd1
GN		 2321 ss_sel = cs_sel + 8;
2322 cs.d = 0;
4668f050
AP		 2323 cs.l = 1;
2324 break;
2325 }
79168fd1
GN		 2326 cs_sel |= SELECTOR_RPL_MASK;
2327 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2328
1aa36616
AK		 2329 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2330 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2331
dd856efa
AK		 2332 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2333 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2334
e54cfa97 2335 return X86EMUL_CONTINUE;
4668f050
AP		 2336}
2337
7b105ca2 2338static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2339{
2340 int iopl;
2341 if (ctxt->mode == X86EMUL_MODE_REAL)
2342 return false;
2343 if (ctxt->mode == X86EMUL_MODE_VM86)
2344 return true;
2345 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2346 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2347}
2348
2349static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2350 u16 port, u16 len)
2351{
0225fb50 2352 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2353 struct desc_struct tr_seg;
5601d05b 2354 u32 base3;
f850e2e6 2355 int r;
1aa36616 2356 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2357 unsigned mask = (1 << len) - 1;
5601d05b 2358 unsigned long base;
f850e2e6 2359
1aa36616 2360 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2361 if (!tr_seg.p)
f850e2e6 2362 return false;
79168fd1 2363 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2364 return false;
5601d05b
GN		 2365 base = get_desc_base(&tr_seg);
2366#ifdef CONFIG_X86_64
2367 base |= ((u64)base3) << 32;
2368#endif
0f65dd70 2369 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2370 if (r != X86EMUL_CONTINUE)
2371 return false;
79168fd1 2372 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2373 return false;
0f65dd70 2374 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2375 if (r != X86EMUL_CONTINUE)
2376 return false;
2377 if ((perm >> bit_idx) & mask)
2378 return false;
2379 return true;
2380}
2381
2382static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2383 u16 port, u16 len)
2384{
4fc40f07
GN		 2385 if (ctxt->perm_ok)
2386 return true;
2387
7b105ca2
TY		 2388 if (emulator_bad_iopl(ctxt))
2389 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2390 return false;
4fc40f07
GN		 2391
2392 ctxt->perm_ok = true;
2393
f850e2e6
GN		 2394 return true;
2395}
2396
38ba30ba 2397static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2398 struct tss_segment_16 *tss)
2399{
9dac77fa 2400 tss->ip = ctxt->_eip;
38ba30ba 2401 tss->flag = ctxt->eflags;
dd856efa
AK		 2402 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2403 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2404 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2405 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2406 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2407 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2408 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2409 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2410
1aa36616
AK		 2411 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2412 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2413 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2414 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2415 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2416}
2417
2418static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2419 struct tss_segment_16 *tss)
2420{
38ba30ba 2421 int ret;
2356aaeb 2422 u8 cpl;
38ba30ba 2423
9dac77fa 2424 ctxt->_eip = tss->ip;
38ba30ba 2425 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2426 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2427 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2428 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2429 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2430 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2431 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2432 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2433 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2434
2435 /*
2436 * SDM says that segment selectors are loaded before segment
2437 * descriptors
2438 */
1aa36616
AK		 2439 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2440 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2441 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2442 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2443 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2444
2356aaeb
PB		 2445 cpl = tss->cs & 3;
2446
38ba30ba 2447 /*
fc058680 2448 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2449 * it is handled in a context of new task
2450 */
5045b468 2451 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2452 if (ret != X86EMUL_CONTINUE)
2453 return ret;
5045b468 2454 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2455 if (ret != X86EMUL_CONTINUE)
2456 return ret;
5045b468 2457 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2458 if (ret != X86EMUL_CONTINUE)
2459 return ret;
5045b468 2460 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2461 if (ret != X86EMUL_CONTINUE)
2462 return ret;
5045b468 2463 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2464 if (ret != X86EMUL_CONTINUE)
2465 return ret;
2466
2467 return X86EMUL_CONTINUE;
2468}
2469
2470static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2471 u16 tss_selector, u16 old_tss_sel,
2472 ulong old_tss_base, struct desc_struct *new_desc)
2473{
0225fb50 2474 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2475 struct tss_segment_16 tss_seg;
2476 int ret;
bcc55cba 2477 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2478
0f65dd70 2479 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2480 &ctxt->exception);
db297e3d 2481 if (ret != X86EMUL_CONTINUE)
38ba30ba 2482 /* FIXME: need to provide precise fault address */
38ba30ba 2483 return ret;
38ba30ba 2484
7b105ca2 2485 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2486
0f65dd70 2487 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2488 &ctxt->exception);
db297e3d 2489 if (ret != X86EMUL_CONTINUE)
38ba30ba 2490 /* FIXME: need to provide precise fault address */
38ba30ba 2491 return ret;
38ba30ba 2492
0f65dd70 2493 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2494 &ctxt->exception);
db297e3d 2495 if (ret != X86EMUL_CONTINUE)
38ba30ba 2496 /* FIXME: need to provide precise fault address */
38ba30ba 2497 return ret;
38ba30ba
GN		 2498
2499 if (old_tss_sel != 0xffff) {
2500 tss_seg.prev_task_link = old_tss_sel;
2501
0f65dd70 2502 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2503 &tss_seg.prev_task_link,
2504 sizeof tss_seg.prev_task_link,
0f65dd70 2505 &ctxt->exception);
db297e3d 2506 if (ret != X86EMUL_CONTINUE)
38ba30ba 2507 /* FIXME: need to provide precise fault address */
38ba30ba 2508 return ret;
38ba30ba
GN		 2509 }
2510
7b105ca2 2511 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2512}
2513
2514static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2515 struct tss_segment_32 *tss)
2516{
5c7411e2 2517 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2518 tss->eip = ctxt->_eip;
38ba30ba 2519 tss->eflags = ctxt->eflags;
dd856efa
AK		 2520 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2521 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2522 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2523 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2524 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2525 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2526 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2527 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2528
1aa36616
AK		 2529 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2530 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2531 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2532 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2533 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2534 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2535}
2536
2537static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2538 struct tss_segment_32 *tss)
2539{
38ba30ba 2540 int ret;
2356aaeb 2541 u8 cpl;
38ba30ba 2542
7b105ca2 2543 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2544 return emulate_gp(ctxt, 0);
9dac77fa 2545 ctxt->_eip = tss->eip;
38ba30ba 2546 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2547
2548 /* General purpose registers */
dd856efa
AK		 2549 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2550 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2551 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2552 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2553 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2554 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2555 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2556 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2557
2558 /*
2559 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2560 * descriptors. This is important because CPL checks will
2561 * use CS.RPL.
38ba30ba 2562 */
1aa36616
AK		 2563 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2564 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2565 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2566 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2567 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2568 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2569 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2570
4cee4798
KW		 2571 /*
2572 * If we're switching between Protected Mode and VM86, we need to make
2573 * sure to update the mode before loading the segment descriptors so
2574 * that the selectors are interpreted correctly.
4cee4798 2575 */
2356aaeb 2576 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2577 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2578 cpl = 3;
2579 } else {
4cee4798 2580 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2581 cpl = tss->cs & 3;
2582 }
4cee4798 2583
38ba30ba
GN		 2584 /*
2585 * Now load segment descriptors. If fault happenes at this stage
2586 * it is handled in a context of new task
2587 */
5045b468 2588 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2589 if (ret != X86EMUL_CONTINUE)
2590 return ret;
5045b468 2591 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2592 if (ret != X86EMUL_CONTINUE)
2593 return ret;
5045b468 2594 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2595 if (ret != X86EMUL_CONTINUE)
2596 return ret;
5045b468 2597 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2598 if (ret != X86EMUL_CONTINUE)
2599 return ret;
5045b468 2600 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
5045b468 2603 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
5045b468 2606 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2607 if (ret != X86EMUL_CONTINUE)
2608 return ret;
2609
2610 return X86EMUL_CONTINUE;
2611}
2612
2613static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2614 u16 tss_selector, u16 old_tss_sel,
2615 ulong old_tss_base, struct desc_struct *new_desc)
2616{
0225fb50 2617 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2618 struct tss_segment_32 tss_seg;
2619 int ret;
bcc55cba 2620 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2621 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2622 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2623
0f65dd70 2624 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2625 &ctxt->exception);
db297e3d 2626 if (ret != X86EMUL_CONTINUE)
38ba30ba 2627 /* FIXME: need to provide precise fault address */
38ba30ba 2628 return ret;
38ba30ba 2629
7b105ca2 2630 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2631
5c7411e2
NA		 2632 /* Only GP registers and segment selectors are saved */
2633 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2634 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2635 if (ret != X86EMUL_CONTINUE)
38ba30ba 2636 /* FIXME: need to provide precise fault address */
38ba30ba 2637 return ret;
38ba30ba 2638
0f65dd70 2639 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2640 &ctxt->exception);
db297e3d 2641 if (ret != X86EMUL_CONTINUE)
38ba30ba 2642 /* FIXME: need to provide precise fault address */
38ba30ba 2643 return ret;
38ba30ba
GN		 2644
2645 if (old_tss_sel != 0xffff) {
2646 tss_seg.prev_task_link = old_tss_sel;
2647
0f65dd70 2648 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2649 &tss_seg.prev_task_link,
2650 sizeof tss_seg.prev_task_link,
0f65dd70 2651 &ctxt->exception);
db297e3d 2652 if (ret != X86EMUL_CONTINUE)
38ba30ba 2653 /* FIXME: need to provide precise fault address */
38ba30ba 2654 return ret;
38ba30ba
GN		 2655 }
2656
7b105ca2 2657 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2658}
2659
2660static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2661 u16 tss_selector, int idt_index, int reason,
e269fb21 2662 bool has_error_code, u32 error_code)
38ba30ba 2663{
0225fb50 2664 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2665 struct desc_struct curr_tss_desc, next_tss_desc;
2666 int ret;
1aa36616 2667 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2668 ulong old_tss_base =
4bff1e86 2669 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2670 u32 desc_limit;
e919464b 2671 ulong desc_addr;
38ba30ba
GN		 2672
2673 /* FIXME: old_tss_base == ~0 ? */
2674
e919464b 2675 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2676 if (ret != X86EMUL_CONTINUE)
2677 return ret;
e919464b 2678 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2679 if (ret != X86EMUL_CONTINUE)
2680 return ret;
2681
2682 /* FIXME: check that next_tss_desc is tss */
2683
7f3d35fd
KW		 2684 /*
2685 * Check privileges. The three cases are task switch caused by...
2686 *
2687 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2688 * 2. Exception/IRQ/iret: No check is performed
fc058680 2689 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2690 */
2691 if (reason == TASK_SWITCH_GATE) {
2692 if (idt_index != -1) {
2693 /* Software interrupts */
2694 struct desc_struct task_gate_desc;
2695 int dpl;
2696
2697 ret = read_interrupt_descriptor(ctxt, idt_index,
2698 &task_gate_desc);
2699 if (ret != X86EMUL_CONTINUE)
2700 return ret;
2701
2702 dpl = task_gate_desc.dpl;
2703 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2704 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2705 }
2706 } else if (reason != TASK_SWITCH_IRET) {
2707 int dpl = next_tss_desc.dpl;
2708 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2709 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2710 }
2711
7f3d35fd 2712
ceffb459
GN		 2713 desc_limit = desc_limit_scaled(&next_tss_desc);
2714 if (!next_tss_desc.p ||
2715 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2716 desc_limit < 0x2b)) {
54b8486f 2717 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2718 return X86EMUL_PROPAGATE_FAULT;
2719 }
2720
2721 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2722 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2723 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2724 }
2725
2726 if (reason == TASK_SWITCH_IRET)
2727 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2728
2729 /* set back link to prev task only if NT bit is set in eflags
fc058680 2730 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2731 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2732 old_tss_sel = 0xffff;
2733
2734 if (next_tss_desc.type & 8)
7b105ca2 2735 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2736 old_tss_base, &next_tss_desc);
2737 else
7b105ca2 2738 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2739 old_tss_base, &next_tss_desc);
0760d448
JK		 2740 if (ret != X86EMUL_CONTINUE)
2741 return ret;
38ba30ba
GN		 2742
2743 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2744 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2745
2746 if (reason != TASK_SWITCH_IRET) {
2747 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2748 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2749 }
2750
717746e3 2751 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2752 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2753
e269fb21 2754 if (has_error_code) {
9dac77fa
AK		 2755 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2756 ctxt->lock_prefix = 0;
2757 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2758 ret = em_push(ctxt);
e269fb21
JK		 2759 }
2760
38ba30ba
GN		 2761 return ret;
2762}
2763
2764int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2765 u16 tss_selector, int idt_index, int reason,
e269fb21 2766 bool has_error_code, u32 error_code)
38ba30ba 2767{
38ba30ba
GN		 2768 int rc;
2769
dd856efa 2770 invalidate_registers(ctxt);
9dac77fa
AK		 2771 ctxt->_eip = ctxt->eip;
2772 ctxt->dst.type = OP_NONE;
38ba30ba 2773
7f3d35fd 2774 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2775 has_error_code, error_code);
38ba30ba 2776
dd856efa 2777 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2778 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2779 writeback_registers(ctxt);
2780 }
38ba30ba 2781
a0c0ab2f 2782 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2783}
2784
f3bd64c6
GN		 2785static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2786 struct operand *op)
a682e354 2787{
b3356bf0 2788 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2789
dd856efa
AK		 2790 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2791 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2792}
2793
7af04fc0
AK		 2794static int em_das(struct x86_emulate_ctxt *ctxt)
2795{
7af04fc0
AK		 2796 u8 al, old_al;
2797 bool af, cf, old_cf;
2798
2799 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2800 al = ctxt->dst.val;
7af04fc0
AK		 2801
2802 old_al = al;
2803 old_cf = cf;
2804 cf = false;
2805 af = ctxt->eflags & X86_EFLAGS_AF;
2806 if ((al & 0x0f) > 9 || af) {
2807 al -= 6;
2808 cf = old_cf | (al >= 250);
2809 af = true;
2810 } else {
2811 af = false;
2812 }
2813 if (old_al > 0x99 || old_cf) {
2814 al -= 0x60;
2815 cf = true;
2816 }
2817
9dac77fa 2818 ctxt->dst.val = al;
7af04fc0 2819 /* Set PF, ZF, SF */
9dac77fa
AK		 2820 ctxt->src.type = OP_IMM;
2821 ctxt->src.val = 0;
2822 ctxt->src.bytes = 1;
158de57f 2823 fastop(ctxt, em_or);
7af04fc0
AK		 2824 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2825 if (cf)
2826 ctxt->eflags |= X86_EFLAGS_CF;
2827 if (af)
2828 ctxt->eflags |= X86_EFLAGS_AF;
2829 return X86EMUL_CONTINUE;
2830}
2831
a035d5c6
PB		 2832static int em_aam(struct x86_emulate_ctxt *ctxt)
2833{
2834 u8 al, ah;
2835
2836 if (ctxt->src.val == 0)
2837 return emulate_de(ctxt);
2838
2839 al = ctxt->dst.val & 0xff;
2840 ah = al / ctxt->src.val;
2841 al %= ctxt->src.val;
2842
2843 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2844
2845 /* Set PF, ZF, SF */
2846 ctxt->src.type = OP_IMM;
2847 ctxt->src.val = 0;
2848 ctxt->src.bytes = 1;
2849 fastop(ctxt, em_or);
2850
2851 return X86EMUL_CONTINUE;
2852}
2853
7f662273
GN		 2854static int em_aad(struct x86_emulate_ctxt *ctxt)
2855{
2856 u8 al = ctxt->dst.val & 0xff;
2857 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2858
2859 al = (al + (ah * ctxt->src.val)) & 0xff;
2860
2861 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2862
f583c29b
GN		 2863 /* Set PF, ZF, SF */
2864 ctxt->src.type = OP_IMM;
2865 ctxt->src.val = 0;
2866 ctxt->src.bytes = 1;
2867 fastop(ctxt, em_or);
7f662273
GN		 2868
2869 return X86EMUL_CONTINUE;
2870}
2871
d4ddafcd
TY		 2872static int em_call(struct x86_emulate_ctxt *ctxt)
2873{
2874 long rel = ctxt->src.val;
2875
2876 ctxt->src.val = (unsigned long)ctxt->_eip;
2877 jmp_rel(ctxt, rel);
2878 return em_push(ctxt);
2879}
2880
0ef753b8
AK		 2881static int em_call_far(struct x86_emulate_ctxt *ctxt)
2882{
0ef753b8
AK		 2883 u16 sel, old_cs;
2884 ulong old_eip;
2885 int rc;
2886
1aa36616 2887 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2888 old_eip = ctxt->_eip;
0ef753b8 2889
9dac77fa 2890 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2891 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2892 return X86EMUL_CONTINUE;
2893
9dac77fa
AK		 2894 ctxt->_eip = 0;
2895 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2896
9dac77fa 2897 ctxt->src.val = old_cs;
4487b3b4 2898 rc = em_push(ctxt);
0ef753b8
AK		 2899 if (rc != X86EMUL_CONTINUE)
2900 return rc;
2901
9dac77fa 2902 ctxt->src.val = old_eip;
4487b3b4 2903 return em_push(ctxt);
0ef753b8
AK		 2904}
2905
40ece7c7
AK		 2906static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2907{
40ece7c7
AK		 2908 int rc;
2909
9dac77fa
AK		 2910 ctxt->dst.type = OP_REG;
2911 ctxt->dst.addr.reg = &ctxt->_eip;
2912 ctxt->dst.bytes = ctxt->op_bytes;
2913 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2914 if (rc != X86EMUL_CONTINUE)
2915 return rc;
5ad105e5 2916 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2917 return X86EMUL_CONTINUE;
2918}
2919
e4f973ae
TY		 2920static int em_xchg(struct x86_emulate_ctxt *ctxt)
2921{
e4f973ae 2922 /* Write back the register source. */
9dac77fa
AK		 2923 ctxt->src.val = ctxt->dst.val;
2924 write_register_operand(&ctxt->src);
e4f973ae
TY		 2925
2926 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2927 ctxt->dst.val = ctxt->src.orig_val;
2928 ctxt->lock_prefix = 1;
e4f973ae
TY		 2929 return X86EMUL_CONTINUE;
2930}
2931
5c82aa29
AK		 2932static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2933{
9dac77fa 2934 ctxt->dst.val = ctxt->src2.val;
4d758349 2935 return fastop(ctxt, em_imul);
5c82aa29
AK		 2936}
2937
61429142
AK		 2938static int em_cwd(struct x86_emulate_ctxt *ctxt)
2939{
9dac77fa
AK		 2940 ctxt->dst.type = OP_REG;
2941 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2942 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2943 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2944
2945 return X86EMUL_CONTINUE;
2946}
2947
48bb5d3c
AK		 2948static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2949{
48bb5d3c
AK		 2950 u64 tsc = 0;
2951
717746e3 2952 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2953 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2954 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2955 return X86EMUL_CONTINUE;
2956}
2957
222d21aa
AK		 2958static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2959{
2960 u64 pmc;
2961
dd856efa 2962 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2963 return emulate_gp(ctxt, 0);
dd856efa
AK		 2964 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2965 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2966 return X86EMUL_CONTINUE;
2967}
2968
b9eac5f4
AK		 2969static int em_mov(struct x86_emulate_ctxt *ctxt)
2970{
54cfdb3e 2971 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2972 return X86EMUL_CONTINUE;
2973}
2974
84cffe49
BP		 2975#define FFL(x) bit(X86_FEATURE_##x)
2976
2977static int em_movbe(struct x86_emulate_ctxt *ctxt)
2978{
2979 u32 ebx, ecx, edx, eax = 1;
2980 u16 tmp;
2981
2982 /*
2983 * Check MOVBE is set in the guest-visible CPUID leaf.
2984 */
2985 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2986 if (!(ecx & FFL(MOVBE)))
2987 return emulate_ud(ctxt);
2988
2989 switch (ctxt->op_bytes) {
2990 case 2:
2991 /*
2992 * From MOVBE definition: "...When the operand size is 16 bits,
2993 * the upper word of the destination register remains unchanged
2994 * ..."
2995 *
2996 * Both casting ->valptr and ->val to u16 breaks strict aliasing
2997 * rules so we have to do the operation almost per hand.
2998 */
2999 tmp = (u16)ctxt->src.val;
3000 ctxt->dst.val &= ~0xffffUL;
3001 ctxt->dst.val |= (unsigned long)swab16(tmp);
3002 break;
3003 case 4:
3004 ctxt->dst.val = swab32((u32)ctxt->src.val);
3005 break;
3006 case 8:
3007 ctxt->dst.val = swab64(ctxt->src.val);
3008 break;
3009 default:
3010 return X86EMUL_PROPAGATE_FAULT;
3011 }
3012 return X86EMUL_CONTINUE;
3013}
3014
bc00f8d2
TY		 3015static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3016{
3017 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3018 return emulate_gp(ctxt, 0);
3019
3020 /* Disable writeback. */
3021 ctxt->dst.type = OP_NONE;
3022 return X86EMUL_CONTINUE;
3023}
3024
3025static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3026{
3027 unsigned long val;
3028
3029 if (ctxt->mode == X86EMUL_MODE_PROT64)
3030 val = ctxt->src.val & ~0ULL;
3031 else
3032 val = ctxt->src.val & ~0U;
3033
3034 /* #UD condition is already handled. */
3035 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3036 return emulate_gp(ctxt, 0);
3037
3038 /* Disable writeback. */
3039 ctxt->dst.type = OP_NONE;
3040 return X86EMUL_CONTINUE;
3041}
3042
e1e210b0
TY		 3043static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3044{
3045 u64 msr_data;
3046
dd856efa
AK		 3047 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3048 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3049 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3050 return emulate_gp(ctxt, 0);
3051
3052 return X86EMUL_CONTINUE;
3053}
3054
3055static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3056{
3057 u64 msr_data;
3058
dd856efa 3059 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3060 return emulate_gp(ctxt, 0);
3061
dd856efa
AK		 3062 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3063 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3064 return X86EMUL_CONTINUE;
3065}
3066
1bd5f469
TY		 3067static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3068{
9dac77fa 3069 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3070 return emulate_ud(ctxt);
3071
9dac77fa 3072 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3073 return X86EMUL_CONTINUE;
3074}
3075
3076static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3077{
9dac77fa 3078 u16 sel = ctxt->src.val;
1bd5f469 3079
9dac77fa 3080 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3081 return emulate_ud(ctxt);
3082
9dac77fa 3083 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3084 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3085
3086 /* Disable writeback. */
9dac77fa
AK		 3087 ctxt->dst.type = OP_NONE;
3088 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3089}
3090
a14e579f
AK		 3091static int em_lldt(struct x86_emulate_ctxt *ctxt)
3092{
3093 u16 sel = ctxt->src.val;
3094
3095 /* Disable writeback. */
3096 ctxt->dst.type = OP_NONE;
3097 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3098}
3099
80890006
AK		 3100static int em_ltr(struct x86_emulate_ctxt *ctxt)
3101{
3102 u16 sel = ctxt->src.val;
3103
3104 /* Disable writeback. */
3105 ctxt->dst.type = OP_NONE;
3106 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3107}
3108
38503911
AK		 3109static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3110{
9fa088f4
AK		 3111 int rc;
3112 ulong linear;
3113
9dac77fa 3114 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3115 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3116 ctxt->ops->invlpg(ctxt, linear);
38503911 3117 /* Disable writeback. */
9dac77fa 3118 ctxt->dst.type = OP_NONE;
38503911
AK		 3119 return X86EMUL_CONTINUE;
3120}
3121
2d04a05b
AK		 3122static int em_clts(struct x86_emulate_ctxt *ctxt)
3123{
3124 ulong cr0;
3125
3126 cr0 = ctxt->ops->get_cr(ctxt, 0);
3127 cr0 &= ~X86_CR0_TS;
3128 ctxt->ops->set_cr(ctxt, 0, cr0);
3129 return X86EMUL_CONTINUE;
3130}
3131
26d05cc7
AK		 3132static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3133{
26d05cc7
AK		 3134 int rc;
3135
9dac77fa 3136 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3137 return X86EMUL_UNHANDLEABLE;
3138
3139 rc = ctxt->ops->fix_hypercall(ctxt);
3140 if (rc != X86EMUL_CONTINUE)
3141 return rc;
3142
3143 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3144 ctxt->_eip = ctxt->eip;
26d05cc7 3145 /* Disable writeback. */
9dac77fa 3146 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3147 return X86EMUL_CONTINUE;
3148}
3149
96051572
AK		 3150static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3151 void (*get)(struct x86_emulate_ctxt *ctxt,
3152 struct desc_ptr *ptr))
3153{
3154 struct desc_ptr desc_ptr;
3155
3156 if (ctxt->mode == X86EMUL_MODE_PROT64)
3157 ctxt->op_bytes = 8;
3158 get(ctxt, &desc_ptr);
3159 if (ctxt->op_bytes == 2) {
3160 ctxt->op_bytes = 4;
3161 desc_ptr.address &= 0x00ffffff;
3162 }
3163 /* Disable writeback. */
3164 ctxt->dst.type = OP_NONE;
3165 return segmented_write(ctxt, ctxt->dst.addr.mem,
3166 &desc_ptr, 2 + ctxt->op_bytes);
3167}
3168
3169static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3170{
3171 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3172}
3173
3174static int em_sidt(struct x86_emulate_ctxt *ctxt)
3175{
3176 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3177}
3178
26d05cc7
AK		 3179static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3180{
26d05cc7
AK		 3181 struct desc_ptr desc_ptr;
3182 int rc;
3183
510425ff
AK		 3184 if (ctxt->mode == X86EMUL_MODE_PROT64)
3185 ctxt->op_bytes = 8;
9dac77fa 3186 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3187 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3188 ctxt->op_bytes);
26d05cc7
AK		 3189 if (rc != X86EMUL_CONTINUE)
3190 return rc;
3191 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3192 /* Disable writeback. */
9dac77fa 3193 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3194 return X86EMUL_CONTINUE;
3195}
3196
5ef39c71 3197static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3198{
26d05cc7
AK		 3199 int rc;
3200
5ef39c71
AK		 3201 rc = ctxt->ops->fix_hypercall(ctxt);
3202
26d05cc7 3203 /* Disable writeback. */
9dac77fa 3204 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3205 return rc;
3206}
3207
3208static int em_lidt(struct x86_emulate_ctxt *ctxt)
3209{
26d05cc7
AK		 3210 struct desc_ptr desc_ptr;
3211 int rc;
3212
510425ff
AK		 3213 if (ctxt->mode == X86EMUL_MODE_PROT64)
3214 ctxt->op_bytes = 8;
9dac77fa 3215 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3216 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3217 ctxt->op_bytes);
26d05cc7
AK		 3218 if (rc != X86EMUL_CONTINUE)
3219 return rc;
3220 ctxt->ops->set_idt(ctxt, &desc_ptr);
3221 /* Disable writeback. */
9dac77fa 3222 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3223 return X86EMUL_CONTINUE;
3224}
3225
3226static int em_smsw(struct x86_emulate_ctxt *ctxt)
3227{
32e94d06
NA		 3228 if (ctxt->dst.type == OP_MEM)
3229 ctxt->dst.bytes = 2;
9dac77fa 3230 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3231 return X86EMUL_CONTINUE;
3232}
3233
3234static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3235{
26d05cc7 3236 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3237 | (ctxt->src.val & 0x0f));
3238 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3239 return X86EMUL_CONTINUE;
3240}
3241
d06e03ad
TY		 3242static int em_loop(struct x86_emulate_ctxt *ctxt)
3243{
dd856efa
AK		 3244 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3245 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3246 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3247 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3248
3249 return X86EMUL_CONTINUE;
3250}
3251
3252static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3253{
dd856efa 3254 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3255 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3256
3257 return X86EMUL_CONTINUE;
3258}
3259
d7841a4b
TY		 3260static int em_in(struct x86_emulate_ctxt *ctxt)
3261{
3262 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3263 &ctxt->dst.val))
3264 return X86EMUL_IO_NEEDED;
3265
3266 return X86EMUL_CONTINUE;
3267}
3268
3269static int em_out(struct x86_emulate_ctxt *ctxt)
3270{
3271 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3272 &ctxt->src.val, 1);
3273 /* Disable writeback. */
3274 ctxt->dst.type = OP_NONE;
3275 return X86EMUL_CONTINUE;
3276}
3277
f411e6cd
TY		 3278static int em_cli(struct x86_emulate_ctxt *ctxt)
3279{
3280 if (emulator_bad_iopl(ctxt))
3281 return emulate_gp(ctxt, 0);
3282
3283 ctxt->eflags &= ~X86_EFLAGS_IF;
3284 return X86EMUL_CONTINUE;
3285}
3286
3287static int em_sti(struct x86_emulate_ctxt *ctxt)
3288{
3289 if (emulator_bad_iopl(ctxt))
3290 return emulate_gp(ctxt, 0);
3291
3292 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3293 ctxt->eflags |= X86_EFLAGS_IF;
3294 return X86EMUL_CONTINUE;
3295}
3296
6d6eede4
AK		 3297static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3298{
3299 u32 eax, ebx, ecx, edx;
3300
dd856efa
AK		 3301 eax = reg_read(ctxt, VCPU_REGS_RAX);
3302 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3303 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3304 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3305 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3306 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3307 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3308 return X86EMUL_CONTINUE;
3309}
3310
98f73630
PB		 3311static int em_sahf(struct x86_emulate_ctxt *ctxt)
3312{
3313 u32 flags;
3314
3315 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3316 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3317
3318 ctxt->eflags &= ~0xffUL;
3319 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3320 return X86EMUL_CONTINUE;
3321}
3322
2dd7caa0
AK		 3323static int em_lahf(struct x86_emulate_ctxt *ctxt)
3324{
dd856efa
AK		 3325 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3326 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3327 return X86EMUL_CONTINUE;
3328}
3329
9299836e
AK		 3330static int em_bswap(struct x86_emulate_ctxt *ctxt)
3331{
3332 switch (ctxt->op_bytes) {
3333#ifdef CONFIG_X86_64
3334 case 8:
3335 asm("bswap %0" : "+r"(ctxt->dst.val));
3336 break;
3337#endif
3338 default:
3339 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3340 break;
3341 }
3342 return X86EMUL_CONTINUE;
3343}
3344
cfec82cb
JR		 3345static bool valid_cr(int nr)
3346{
3347 switch (nr) {
3348 case 0:
3349 case 2 ... 4:
3350 case 8:
3351 return true;
3352 default:
3353 return false;
3354 }
3355}
3356
3357static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3358{
9dac77fa 3359 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3360 return emulate_ud(ctxt);
3361
3362 return X86EMUL_CONTINUE;
3363}
3364
3365static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3366{
9dac77fa
AK		 3367 u64 new_val = ctxt->src.val64;
3368 int cr = ctxt->modrm_reg;
c2ad2bb3 3369 u64 efer = 0;
cfec82cb
JR		 3370
3371 static u64 cr_reserved_bits[] = {
3372 0xffffffff00000000ULL,
3373 0, 0, 0, /* CR3 checked later */
3374 CR4_RESERVED_BITS,
3375 0, 0, 0,
3376 CR8_RESERVED_BITS,
3377 };
3378
3379 if (!valid_cr(cr))
3380 return emulate_ud(ctxt);
3381
3382 if (new_val & cr_reserved_bits[cr])
3383 return emulate_gp(ctxt, 0);
3384
3385 switch (cr) {
3386 case 0: {
c2ad2bb3 3387 u64 cr4;
cfec82cb
JR		 3388 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3389 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3390 return emulate_gp(ctxt, 0);
3391
717746e3
AK		 3392 cr4 = ctxt->ops->get_cr(ctxt, 4);
3393 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3394
3395 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3396 !(cr4 & X86_CR4_PAE))
3397 return emulate_gp(ctxt, 0);
3398
3399 break;
3400 }
3401 case 3: {
3402 u64 rsvd = 0;
3403
c2ad2bb3
AK		 3404 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3405 if (efer & EFER_LMA)
cfec82cb 3406 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3407
3408 if (new_val & rsvd)
3409 return emulate_gp(ctxt, 0);
3410
3411 break;
3412 }
3413 case 4: {
717746e3 3414 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3415
3416 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3417 return emulate_gp(ctxt, 0);
3418
3419 break;
3420 }
3421 }
3422
3423 return X86EMUL_CONTINUE;
3424}
3425
3b88e41a
JR		 3426static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3427{
3428 unsigned long dr7;
3429
717746e3 3430 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3431
3432 /* Check if DR7.Global_Enable is set */
3433 return dr7 & (1 << 13);
3434}
3435
3436static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3437{
9dac77fa 3438 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3439 u64 cr4;
3440
3441 if (dr > 7)
3442 return emulate_ud(ctxt);
3443
717746e3 3444 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3445 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3446 return emulate_ud(ctxt);
3447
3448 if (check_dr7_gd(ctxt))
3449 return emulate_db(ctxt);
3450
3451 return X86EMUL_CONTINUE;
3452}
3453
3454static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3455{
9dac77fa
AK		 3456 u64 new_val = ctxt->src.val64;
3457 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3458
3459 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3460 return emulate_gp(ctxt, 0);
3461
3462 return check_dr_read(ctxt);
3463}
3464
01de8b09
JR		 3465static int check_svme(struct x86_emulate_ctxt *ctxt)
3466{
3467 u64 efer;
3468
717746e3 3469 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3470
3471 if (!(efer & EFER_SVME))
3472 return emulate_ud(ctxt);
3473
3474 return X86EMUL_CONTINUE;
3475}
3476
3477static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3478{
dd856efa 3479 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3480
3481 /* Valid physical address? */
d4224449 3482 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3483 return emulate_gp(ctxt, 0);
3484
3485 return check_svme(ctxt);
3486}
3487
d7eb8203
JR		 3488static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3489{
717746e3 3490 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3491
717746e3 3492 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3493 return emulate_ud(ctxt);
3494
3495 return X86EMUL_CONTINUE;
3496}
3497
8061252e
JR		 3498static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3499{
717746e3 3500 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3501 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3502
717746e3 3503 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3504 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3505 return emulate_gp(ctxt, 0);
3506
3507 return X86EMUL_CONTINUE;
3508}
3509
f6511935
JR		 3510static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3511{
9dac77fa
AK		 3512 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3513 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3514 return emulate_gp(ctxt, 0);
3515
3516 return X86EMUL_CONTINUE;
3517}
3518
3519static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3520{
9dac77fa
AK		 3521 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3522 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3523 return emulate_gp(ctxt, 0);
3524
3525 return X86EMUL_CONTINUE;
3526}
3527
73fba5f4 3528#define D(_y) { .flags = (_y) }
d40a6898
PB		 3529#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3530#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3531 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3532#define N D(NotImpl)
01de8b09 3533#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3534#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3535#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3536#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3537#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3538#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3539#define II(_f, _e, _i) \
d40a6898 3540 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3541#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3542 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3543 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3544#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3545
8d8f4e9f 3546#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3547#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3548#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3549#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3550#define I2bvIP(_f, _e, _i, _p) \
3551 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3552
fb864fbc
AK		 3553#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3554 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3555 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3556
fd0a0d82 3557static const struct opcode group7_rm1[] = {
1c2545be
TY		 3558 DI(SrcNone | Priv, monitor),
3559 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3560 N, N, N, N, N, N,
3561};
3562
fd0a0d82 3563static const struct opcode group7_rm3[] = {
1c2545be 3564 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3565 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3566 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3567 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3568 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3569 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3570 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3571 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3572};
6230f7fc 3573
fd0a0d82 3574static const struct opcode group7_rm7[] = {
d7eb8203 3575 N,
1c2545be 3576 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3577 N, N, N, N, N, N,
3578};
d67fc27a 3579
fd0a0d82 3580static const struct opcode group1[] = {
fb864fbc
AK		 3581 F(Lock, em_add),
3582 F(Lock | PageTable, em_or),
3583 F(Lock, em_adc),
3584 F(Lock, em_sbb),
3585 F(Lock | PageTable, em_and),
3586 F(Lock, em_sub),
3587 F(Lock, em_xor),
3588 F(NoWrite, em_cmp),
73fba5f4
AK		 3589};
3590
fd0a0d82 3591static const struct opcode group1A[] = {
1c2545be 3592 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3593};
3594
007a3b54
AK		 3595static const struct opcode group2[] = {
3596 F(DstMem | ModRM, em_rol),
3597 F(DstMem | ModRM, em_ror),
3598 F(DstMem | ModRM, em_rcl),
3599 F(DstMem | ModRM, em_rcr),
3600 F(DstMem | ModRM, em_shl),
3601 F(DstMem | ModRM, em_shr),
3602 F(DstMem | ModRM, em_shl),
3603 F(DstMem | ModRM, em_sar),
3604};
3605
fd0a0d82 3606static const struct opcode group3[] = {
fb864fbc
AK		 3607 F(DstMem | SrcImm | NoWrite, em_test),
3608 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3609 F(DstMem | SrcNone | Lock, em_not),
3610 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3611 F(DstXacc | Src2Mem, em_mul_ex),
3612 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3613 F(DstXacc | Src2Mem, em_div_ex),
3614 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3615};
3616
fd0a0d82 3617static const struct opcode group4[] = {
95413dc4
AK		 3618 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3619 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3620 N, N, N, N, N, N,
3621};
3622
fd0a0d82 3623static const struct opcode group5[] = {
95413dc4
AK		 3624 F(DstMem | SrcNone | Lock, em_inc),
3625 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3626 I(SrcMem | Stack, em_grp45),
3627 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3628 I(SrcMem | Stack, em_grp45),
3629 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3630 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3631};
3632
fd0a0d82 3633static const struct opcode group6[] = {
1c2545be
TY		 3634 DI(Prot, sldt),
3635 DI(Prot, str),
a14e579f 3636 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3637 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3638 N, N, N, N,
3639};
3640
fd0a0d82 3641static const struct group_dual group7 = { {
606b1c3e
NA		 3642 II(Mov | DstMem, em_sgdt, sgdt),
3643 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3644 II(SrcMem | Priv, em_lgdt, lgdt),
3645 II(SrcMem | Priv, em_lidt, lidt),
3646 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3647 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3648 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3649}, {
b51e974f 3650 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3651 EXT(0, group7_rm1),
01de8b09 3652 N, EXT(0, group7_rm3),
1c2545be
TY		 3653 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3654 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3655 EXT(0, group7_rm7),
73fba5f4
AK		 3656} };
3657
fd0a0d82 3658static const struct opcode group8[] = {
73fba5f4 3659 N, N, N, N,
11c363ba
AK		 3660 F(DstMem | SrcImmByte | NoWrite, em_bt),
3661 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3662 F(DstMem | SrcImmByte | Lock, em_btr),
3663 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3664};
3665
fd0a0d82 3666static const struct group_dual group9 = { {
1c2545be 3667 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3668}, {
3669 N, N, N, N, N, N, N, N,
3670} };
3671
fd0a0d82 3672static const struct opcode group11[] = {
1c2545be 3673 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3674 X7(D(Undefined)),
a4d4a7c1
AK		 3675};
3676
fd0a0d82 3677static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3678 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3679};
3680
fd0a0d82 3681static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3682 I(0, em_mov), N, N, N,
3683};
3684
27ce8258 3685static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3686 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3687};
3688
045a282c
GN		 3689static const struct escape escape_d9 = { {
3690 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3691}, {
3692 /* 0xC0 - 0xC7 */
3693 N, N, N, N, N, N, N, N,
3694 /* 0xC8 - 0xCF */
3695 N, N, N, N, N, N, N, N,
3696 /* 0xD0 - 0xC7 */
3697 N, N, N, N, N, N, N, N,
3698 /* 0xD8 - 0xDF */
3699 N, N, N, N, N, N, N, N,
3700 /* 0xE0 - 0xE7 */
3701 N, N, N, N, N, N, N, N,
3702 /* 0xE8 - 0xEF */
3703 N, N, N, N, N, N, N, N,
3704 /* 0xF0 - 0xF7 */
3705 N, N, N, N, N, N, N, N,
3706 /* 0xF8 - 0xFF */
3707 N, N, N, N, N, N, N, N,
3708} };
3709
3710static const struct escape escape_db = { {
3711 N, N, N, N, N, N, N, N,
3712}, {
3713 /* 0xC0 - 0xC7 */
3714 N, N, N, N, N, N, N, N,
3715 /* 0xC8 - 0xCF */
3716 N, N, N, N, N, N, N, N,
3717 /* 0xD0 - 0xC7 */
3718 N, N, N, N, N, N, N, N,
3719 /* 0xD8 - 0xDF */
3720 N, N, N, N, N, N, N, N,
3721 /* 0xE0 - 0xE7 */
3722 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3723 /* 0xE8 - 0xEF */
3724 N, N, N, N, N, N, N, N,
3725 /* 0xF0 - 0xF7 */
3726 N, N, N, N, N, N, N, N,
3727 /* 0xF8 - 0xFF */
3728 N, N, N, N, N, N, N, N,
3729} };
3730
3731static const struct escape escape_dd = { {
3732 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3733}, {
3734 /* 0xC0 - 0xC7 */
3735 N, N, N, N, N, N, N, N,
3736 /* 0xC8 - 0xCF */
3737 N, N, N, N, N, N, N, N,
3738 /* 0xD0 - 0xC7 */
3739 N, N, N, N, N, N, N, N,
3740 /* 0xD8 - 0xDF */
3741 N, N, N, N, N, N, N, N,
3742 /* 0xE0 - 0xE7 */
3743 N, N, N, N, N, N, N, N,
3744 /* 0xE8 - 0xEF */
3745 N, N, N, N, N, N, N, N,
3746 /* 0xF0 - 0xF7 */
3747 N, N, N, N, N, N, N, N,
3748 /* 0xF8 - 0xFF */
3749 N, N, N, N, N, N, N, N,
3750} };
3751
fd0a0d82 3752static const struct opcode opcode_table[256] = {
73fba5f4 3753 /* 0x00 - 0x07 */
fb864fbc 3754 F6ALU(Lock, em_add),
1cd196ea
AK		 3755 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3756 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3757 /* 0x08 - 0x0F */
fb864fbc 3758 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3759 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3760 N,
73fba5f4 3761 /* 0x10 - 0x17 */
fb864fbc 3762 F6ALU(Lock, em_adc),
1cd196ea
AK		 3763 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3764 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3765 /* 0x18 - 0x1F */
fb864fbc 3766 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3767 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3768 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3769 /* 0x20 - 0x27 */
fb864fbc 3770 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3771 /* 0x28 - 0x2F */
fb864fbc 3772 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3773 /* 0x30 - 0x37 */
fb864fbc 3774 F6ALU(Lock, em_xor), N, N,
73fba5f4 3775 /* 0x38 - 0x3F */
fb864fbc 3776 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3777 /* 0x40 - 0x4F */
95413dc4 3778 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3779 /* 0x50 - 0x57 */
63540382 3780 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3781 /* 0x58 - 0x5F */
c54fe504 3782 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3783 /* 0x60 - 0x67 */
b96a7fad
TY		 3784 I(ImplicitOps | Stack | No64, em_pusha),
3785 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3786 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3787 N, N, N, N,
3788 /* 0x68 - 0x6F */
d46164db
AK		 3789 I(SrcImm | Mov | Stack, em_push),
3790 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3791 I(SrcImmByte | Mov | Stack, em_push),
3792 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3793 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3794 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3795 /* 0x70 - 0x7F */
3796 X16(D(SrcImmByte)),
3797 /* 0x80 - 0x87 */
1c2545be
TY		 3798 G(ByteOp | DstMem | SrcImm, group1),
3799 G(DstMem | SrcImm, group1),
3800 G(ByteOp | DstMem | SrcImm | No64, group1),
3801 G(DstMem | SrcImmByte, group1),
fb864fbc 3802 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3803 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3804 /* 0x88 - 0x8F */
d5ae7ce8 3805 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3806 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3807 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3808 D(ModRM | SrcMem | NoAccess | DstReg),
3809 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3810 G(0, group1A),
73fba5f4 3811 /* 0x90 - 0x97 */
bf608f88 3812 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3813 /* 0x98 - 0x9F */
61429142 3814 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3815 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3816 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3817 II(ImplicitOps | Stack, em_popf, popf),
3818 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3819 /* 0xA0 - 0xA7 */
b9eac5f4 3820 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3821 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3822 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3823 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3824 /* 0xA8 - 0xAF */
fb864fbc 3825 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3826 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3827 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3828 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3829 /* 0xB0 - 0xB7 */
b9eac5f4 3830 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3831 /* 0xB8 - 0xBF */
5e2c6883 3832 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3833 /* 0xC0 - 0xC7 */
007a3b54 3834 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3835 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3836 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3837 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3838 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3839 G(ByteOp, group11), G(0, group11),
73fba5f4 3840 /* 0xC8 - 0xCF */
612e89f0 3841 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3842 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3843 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3844 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3845 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3846 /* 0xD0 - 0xD7 */
007a3b54
AK		 3847 G(Src2One | ByteOp, group2), G(Src2One, group2),
3848 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3849 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3850 I(DstAcc | SrcImmUByte | No64, em_aad),
3851 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3852 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3853 /* 0xD8 - 0xDF */
045a282c 3854 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3855 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3856 X3(I(SrcImmByte, em_loop)),
3857 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3858 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3859 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3860 /* 0xE8 - 0xEF */
d4ddafcd 3861 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3862 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3863 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3864 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3865 /* 0xF0 - 0xF7 */
bf608f88 3866 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3867 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3868 G(ByteOp, group3), G(0, group3),
73fba5f4 3869 /* 0xF8 - 0xFF */
f411e6cd
TY		 3870 D(ImplicitOps), D(ImplicitOps),
3871 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3872 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3873};
3874
fd0a0d82 3875static const struct opcode twobyte_table[256] = {
73fba5f4 3876 /* 0x00 - 0x0F */
dee6bb70 3877 G(0, group6), GD(0, &group7), N, N,
b51e974f 3878 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3879 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3880 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3881 N, D(ImplicitOps | ModRM), N, N,
3882 /* 0x10 - 0x1F */
103f98ea
PB		 3883 N, N, N, N, N, N, N, N,
3884 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3885 /* 0x20 - 0x2F */
9b88ae99
NA		 3886 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3887 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3888 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3889 check_cr_write),
3890 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3891 check_dr_write),
73fba5f4 3892 N, N, N, N,
27ce8258
IM		 3893 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3894 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3895 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3896 N, N, N, N,
73fba5f4 3897 /* 0x30 - 0x3F */
e1e210b0 3898 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3899 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3900 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3901 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3902 I(ImplicitOps | EmulateOnUD, em_sysenter),
3903 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3904 N, N,
73fba5f4
AK		 3905 N, N, N, N, N, N, N, N,
3906 /* 0x40 - 0x4F */
140bad89 3907 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3908 /* 0x50 - 0x5F */
3909 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3910 /* 0x60 - 0x6F */
aa97bb48
AK		 3911 N, N, N, N,
3912 N, N, N, N,
3913 N, N, N, N,
3914 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3915 /* 0x70 - 0x7F */
aa97bb48
AK		 3916 N, N, N, N,
3917 N, N, N, N,
3918 N, N, N, N,
3919 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3920 /* 0x80 - 0x8F */
3921 X16(D(SrcImm)),
3922 /* 0x90 - 0x9F */
ee45b58e 3923 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3924 /* 0xA0 - 0xA7 */
1cd196ea 3925 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3926 II(ImplicitOps, em_cpuid, cpuid),
3927 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3928 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3929 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3930 /* 0xA8 - 0xAF */
1cd196ea 3931 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3932 DI(ImplicitOps, rsm),
11c363ba 3933 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3934 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3935 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3936 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3937 /* 0xB0 - 0xB7 */
e940b5c2 3938 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3939 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3940 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3941 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3942 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3943 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3944 /* 0xB8 - 0xBF */
3945 N, N,
ce7faab2 3946 G(BitOp, group8),
11c363ba
AK		 3947 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3948 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3949 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3950 /* 0xC0 - 0xC7 */
e47a5f5f 3951 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3952 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3953 N, N, N, GD(0, &group9),
9299836e
AK		 3954 /* 0xC8 - 0xCF */
3955 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3956 /* 0xD0 - 0xDF */
3957 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3958 /* 0xE0 - 0xEF */
3959 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3960 /* 0xF0 - 0xFF */
3961 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3962};
3963
0bc5eedb 3964static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3965 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3966};
3967
3968static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3969 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3970};
3971
3972/*
3973 * Insns below are selected by the prefix which indexed by the third opcode
3974 * byte.
3975 */
3976static const struct opcode opcode_map_0f_38[256] = {
3977 /* 0x00 - 0x7f */
3978 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3979 /* 0x80 - 0xef */
3980 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3981 /* 0xf0 - 0xf1 */
3982 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3983 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3984 /* 0xf2 - 0xff */
3985 N, N, X4(N), X8(N)
0bc5eedb
BP		 3986};
3987
73fba5f4
AK		 3988#undef D
3989#undef N
3990#undef G
3991#undef GD
3992#undef I
aa97bb48 3993#undef GP
01de8b09 3994#undef EXT
73fba5f4 3995
8d8f4e9f 3996#undef D2bv
f6511935 3997#undef D2bvIP
8d8f4e9f 3998#undef I2bv
d7841a4b 3999#undef I2bvIP
d67fc27a 4000#undef I6ALU
8d8f4e9f 4001
9dac77fa 4002static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4003{
4004 unsigned size;
4005
9dac77fa 4006 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4007 if (size == 8)
4008 size = 4;
4009 return size;
4010}
4011
4012static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4013 unsigned size, bool sign_extension)
4014{
39f21ee5
AK		 4015 int rc = X86EMUL_CONTINUE;
4016
4017 op->type = OP_IMM;
4018 op->bytes = size;
9dac77fa 4019 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4020 /* NB. Immediates are sign-extended as necessary. */
4021 switch (op->bytes) {
4022 case 1:
e85a1085 4023 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4024 break;
4025 case 2:
e85a1085 4026 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4027 break;
4028 case 4:
e85a1085 4029 op->val = insn_fetch(s32, ctxt);
39f21ee5 4030 break;
5e2c6883
NA		 4031 case 8:
4032 op->val = insn_fetch(s64, ctxt);
4033 break;
39f21ee5
AK		 4034 }
4035 if (!sign_extension) {
4036 switch (op->bytes) {
4037 case 1:
4038 op->val &= 0xff;
4039 break;
4040 case 2:
4041 op->val &= 0xffff;
4042 break;
4043 case 4:
4044 op->val &= 0xffffffff;
4045 break;
4046 }
4047 }
4048done:
4049 return rc;
4050}
4051
a9945549
AK		 4052static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4053 unsigned d)
4054{
4055 int rc = X86EMUL_CONTINUE;
4056
4057 switch (d) {
4058 case OpReg:
2adb5ad9 4059 decode_register_operand(ctxt, op);
a9945549
AK		 4060 break;
4061 case OpImmUByte:
608aabe3 4062 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4063 break;
4064 case OpMem:
41ddf978 4065 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4066 mem_common:
4067 *op = ctxt->memop;
4068 ctxt->memopp = op;
96888977 4069 if (ctxt->d & BitOp)
a9945549
AK		 4070 fetch_bit_operand(ctxt);
4071 op->orig_val = op->val;
4072 break;
41ddf978 4073 case OpMem64:
aaa05f24 4074 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4075 goto mem_common;
a9945549
AK		 4076 case OpAcc:
4077 op->type = OP_REG;
4078 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4079 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4080 fetch_register_operand(op);
4081 op->orig_val = op->val;
4082 break;
820207c8
AK		 4083 case OpAccLo:
4084 op->type = OP_REG;
4085 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4086 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4087 fetch_register_operand(op);
4088 op->orig_val = op->val;
4089 break;
4090 case OpAccHi:
4091 if (ctxt->d & ByteOp) {
4092 op->type = OP_NONE;
4093 break;
4094 }
4095 op->type = OP_REG;
4096 op->bytes = ctxt->op_bytes;
4097 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4098 fetch_register_operand(op);
4099 op->orig_val = op->val;
4100 break;
a9945549
AK		 4101 case OpDI:
4102 op->type = OP_MEM;
4103 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4104 op->addr.mem.ea =
dd856efa 4105 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4106 op->addr.mem.seg = VCPU_SREG_ES;
4107 op->val = 0;
b3356bf0 4108 op->count = 1;
a9945549
AK		 4109 break;
4110 case OpDX:
4111 op->type = OP_REG;
4112 op->bytes = 2;
dd856efa 4113 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4114 fetch_register_operand(op);
4115 break;
4dd6a57d
AK		 4116 case OpCL:
4117 op->bytes = 1;
dd856efa 4118 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4119 break;
4120 case OpImmByte:
4121 rc = decode_imm(ctxt, op, 1, true);
4122 break;
4123 case OpOne:
4124 op->bytes = 1;
4125 op->val = 1;
4126 break;
4127 case OpImm:
4128 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4129 break;
5e2c6883
NA		 4130 case OpImm64:
4131 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4132 break;
28867cee
AK		 4133 case OpMem8:
4134 ctxt->memop.bytes = 1;
660696d1 4135 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4136 ctxt->memop.addr.reg = decode_register(ctxt,
4137 ctxt->modrm_rm, true);
660696d1
GN		 4138 fetch_register_operand(&ctxt->memop);
4139 }
28867cee 4140 goto mem_common;
0fe59128
AK		 4141 case OpMem16:
4142 ctxt->memop.bytes = 2;
4143 goto mem_common;
4144 case OpMem32:
4145 ctxt->memop.bytes = 4;
4146 goto mem_common;
4147 case OpImmU16:
4148 rc = decode_imm(ctxt, op, 2, false);
4149 break;
4150 case OpImmU:
4151 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4152 break;
4153 case OpSI:
4154 op->type = OP_MEM;
4155 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4156 op->addr.mem.ea =
dd856efa 4157 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4158 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4159 op->val = 0;
b3356bf0 4160 op->count = 1;
0fe59128 4161 break;
7fa57952
PB		 4162 case OpXLat:
4163 op->type = OP_MEM;
4164 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4165 op->addr.mem.ea =
4166 register_address(ctxt,
4167 reg_read(ctxt, VCPU_REGS_RBX) +
4168 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4169 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4170 op->val = 0;
4171 break;
0fe59128
AK		 4172 case OpImmFAddr:
4173 op->type = OP_IMM;
4174 op->addr.mem.ea = ctxt->_eip;
4175 op->bytes = ctxt->op_bytes + 2;
4176 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4177 break;
4178 case OpMemFAddr:
4179 ctxt->memop.bytes = ctxt->op_bytes + 2;
4180 goto mem_common;
c191a7a0
AK		 4181 case OpES:
4182 op->val = VCPU_SREG_ES;
4183 break;
4184 case OpCS:
4185 op->val = VCPU_SREG_CS;
4186 break;
4187 case OpSS:
4188 op->val = VCPU_SREG_SS;
4189 break;
4190 case OpDS:
4191 op->val = VCPU_SREG_DS;
4192 break;
4193 case OpFS:
4194 op->val = VCPU_SREG_FS;
4195 break;
4196 case OpGS:
4197 op->val = VCPU_SREG_GS;
4198 break;
a9945549
AK		 4199 case OpImplicit:
4200 /* Special instructions do their own operand decoding. */
4201 default:
4202 op->type = OP_NONE; /* Disable writeback. */
4203 break;
4204 }
4205
4206done:
4207 return rc;
4208}
4209
ef5d75cc 4210int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4211{
dde7e6d1
AK		 4212 int rc = X86EMUL_CONTINUE;
4213 int mode = ctxt->mode;
46561646 4214 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4215 bool op_prefix = false;
573e80fe 4216 bool has_seg_override = false;
46561646 4217 struct opcode opcode;
dde7e6d1 4218
f09ed83e
AK		 4219 ctxt->memop.type = OP_NONE;
4220 ctxt->memopp = NULL;
9dac77fa
AK		 4221 ctxt->_eip = ctxt->eip;
4222 ctxt->fetch.start = ctxt->_eip;
4223 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4224 ctxt->opcode_len = 1;
dc25e89e 4225 if (insn_len > 0)
9dac77fa 4226 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4227
4228 switch (mode) {
4229 case X86EMUL_MODE_REAL:
4230 case X86EMUL_MODE_VM86:
4231 case X86EMUL_MODE_PROT16:
4232 def_op_bytes = def_ad_bytes = 2;
4233 break;
4234 case X86EMUL_MODE_PROT32:
4235 def_op_bytes = def_ad_bytes = 4;
4236 break;
4237#ifdef CONFIG_X86_64
4238 case X86EMUL_MODE_PROT64:
4239 def_op_bytes = 4;
4240 def_ad_bytes = 8;
4241 break;
4242#endif
4243 default:
1d2887e2 4244 return EMULATION_FAILED;
dde7e6d1
AK		 4245 }
4246
9dac77fa
AK		 4247 ctxt->op_bytes = def_op_bytes;
4248 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4249
4250 /* Legacy prefixes. */
4251 for (;;) {
e85a1085 4252 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4253 case 0x66: /* operand-size override */
0d7cdee8 4254 op_prefix = true;
dde7e6d1 4255 /* switch between 2/4 bytes */
9dac77fa 4256 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4257 break;
4258 case 0x67: /* address-size override */
4259 if (mode == X86EMUL_MODE_PROT64)
4260 /* switch between 4/8 bytes */
9dac77fa 4261 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4262 else
4263 /* switch between 2/4 bytes */
9dac77fa 4264 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4265 break;
4266 case 0x26: /* ES override */
4267 case 0x2e: /* CS override */
4268 case 0x36: /* SS override */
4269 case 0x3e: /* DS override */
573e80fe
BD		 4270 has_seg_override = true;
4271 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4272 break;
4273 case 0x64: /* FS override */
4274 case 0x65: /* GS override */
573e80fe
BD		 4275 has_seg_override = true;
4276 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4277 break;
4278 case 0x40 ... 0x4f: /* REX */
4279 if (mode != X86EMUL_MODE_PROT64)
4280 goto done_prefixes;
9dac77fa 4281 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4282 continue;
4283 case 0xf0: /* LOCK */
9dac77fa 4284 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4285 break;
4286 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4287 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4288 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4289 break;
4290 default:
4291 goto done_prefixes;
4292 }
4293
4294 /* Any legacy prefix after a REX prefix nullifies its effect. */
4295
9dac77fa 4296 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4297 }
4298
4299done_prefixes:
4300
4301 /* REX prefix. */
9dac77fa
AK		 4302 if (ctxt->rex_prefix & 8)
4303 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4304
4305 /* Opcode byte(s). */
9dac77fa 4306 opcode = opcode_table[ctxt->b];
d3ad6243 4307 /* Two-byte opcode? */
9dac77fa 4308 if (ctxt->b == 0x0f) {
1ce19dc1 4309 ctxt->opcode_len = 2;
e85a1085 4310 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4311 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4312
4313 /* 0F_38 opcode map */
4314 if (ctxt->b == 0x38) {
4315 ctxt->opcode_len = 3;
4316 ctxt->b = insn_fetch(u8, ctxt);
4317 opcode = opcode_map_0f_38[ctxt->b];
4318 }
dde7e6d1 4319 }
9dac77fa 4320 ctxt->d = opcode.flags;
dde7e6d1 4321
9f4260e7
TY		 4322 if (ctxt->d & ModRM)
4323 ctxt->modrm = insn_fetch(u8, ctxt);
4324
7fe864dc
NA		 4325 /* vex-prefix instructions are not implemented */
4326 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4327 (mode == X86EMUL_MODE_PROT64 ||
4328 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4329 ctxt->d = NotImpl;
4330 }
4331
9dac77fa
AK		 4332 while (ctxt->d & GroupMask) {
4333 switch (ctxt->d & GroupMask) {
46561646 4334 case Group:
9dac77fa 4335 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4336 opcode = opcode.u.group[goffset];
4337 break;
4338 case GroupDual:
9dac77fa
AK		 4339 goffset = (ctxt->modrm >> 3) & 7;
4340 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4341 opcode = opcode.u.gdual->mod3[goffset];
4342 else
4343 opcode = opcode.u.gdual->mod012[goffset];
4344 break;
4345 case RMExt:
9dac77fa 4346 goffset = ctxt->modrm & 7;
01de8b09 4347 opcode = opcode.u.group[goffset];
46561646
AK		 4348 break;
4349 case Prefix:
9dac77fa 4350 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4351 return EMULATION_FAILED;
9dac77fa 4352 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4353 switch (simd_prefix) {
4354 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4355 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4356 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4357 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4358 }
4359 break;
045a282c
GN		 4360 case Escape:
4361 if (ctxt->modrm > 0xbf)
4362 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4363 else
4364 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4365 break;
46561646 4366 default:
1d2887e2 4367 return EMULATION_FAILED;
0d7cdee8 4368 }
46561646 4369
b1ea50b2 4370 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4371 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4372 }
4373
e24186e0
PB		 4374 /* Unrecognised? */
4375 if (ctxt->d == 0)
4376 return EMULATION_FAILED;
4377
9dac77fa 4378 ctxt->execute = opcode.u.execute;
dde7e6d1 4379
d40a6898
PB		 4380 if (unlikely(ctxt->d &
4381 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4382 /*
4383 * These are copied unconditionally here, and checked unconditionally
4384 * in x86_emulate_insn.
4385 */
4386 ctxt->check_perm = opcode.check_perm;
4387 ctxt->intercept = opcode.intercept;
dde7e6d1 4388
d40a6898
PB		 4389 if (ctxt->d & NotImpl)
4390 return EMULATION_FAILED;
d867162c 4391
d40a6898
PB		 4392 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4393 return EMULATION_FAILED;
dde7e6d1 4394
d40a6898 4395 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4396 ctxt->op_bytes = 8;
7f9b4b75 4397
d40a6898
PB		 4398 if (ctxt->d & Op3264) {
4399 if (mode == X86EMUL_MODE_PROT64)
4400 ctxt->op_bytes = 8;
4401 else
4402 ctxt->op_bytes = 4;
4403 }
4404
4405 if (ctxt->d & Sse)
4406 ctxt->op_bytes = 16;
4407 else if (ctxt->d & Mmx)
4408 ctxt->op_bytes = 8;
4409 }
1253791d 4410
dde7e6d1 4411 /* ModRM and SIB bytes. */
9dac77fa 4412 if (ctxt->d & ModRM) {
f09ed83e 4413 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4414 if (!has_seg_override) {
4415 has_seg_override = true;
4416 ctxt->seg_override = ctxt->modrm_seg;
4417 }
9dac77fa 4418 } else if (ctxt->d & MemAbs)
f09ed83e 4419 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4420 if (rc != X86EMUL_CONTINUE)
4421 goto done;
4422
573e80fe
BD		 4423 if (!has_seg_override)
4424 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4425
573e80fe 4426 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4427
f09ed83e
AK		 4428 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4429 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4430
dde7e6d1
AK		 4431 /*
4432 * Decode and fetch the source operand: register, memory
4433 * or immediate.
4434 */
0fe59128 4435 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4436 if (rc != X86EMUL_CONTINUE)
4437 goto done;
4438
dde7e6d1
AK		 4439 /*
4440 * Decode and fetch the second source operand: register, memory
4441 * or immediate.
4442 */
4dd6a57d 4443 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4444 if (rc != X86EMUL_CONTINUE)
4445 goto done;
4446
dde7e6d1 4447 /* Decode and fetch the destination operand: register or memory. */
a9945549 4448 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4449
4450done:
f09ed83e
AK		 4451 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4452 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4453
1d2887e2 4454 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4455}
4456
1cb3f3ae
XG		 4457bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4458{
4459 return ctxt->d & PageTable;
4460}
4461
3e2f65d5
GN		 4462static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4463{
3e2f65d5
GN		 4464 /* The second termination condition only applies for REPE
4465 * and REPNE. Test if the repeat string operation prefix is
4466 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4467 * corresponding termination condition according to:
4468 * - if REPE/REPZ and ZF = 0 then done
4469 * - if REPNE/REPNZ and ZF = 1 then done
4470 */
9dac77fa
AK		 4471 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4472 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4473 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4474 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4475 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4476 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4477 return true;
4478
4479 return false;
4480}
4481
cbe2c9d3
AK		 4482static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4483{
4484 bool fault = false;
4485
4486 ctxt->ops->get_fpu(ctxt);
4487 asm volatile("1: fwait \n\t"
4488 "2: \n\t"
4489 ".pushsection .fixup,\"ax\" \n\t"
4490 "3: \n\t"
4491 "movb $1, %[fault] \n\t"
4492 "jmp 2b \n\t"
4493 ".popsection \n\t"
4494 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4495 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4496 ctxt->ops->put_fpu(ctxt);
4497
4498 if (unlikely(fault))
4499 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4500
4501 return X86EMUL_CONTINUE;
4502}
4503
4504static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4505 struct operand *op)
4506{
4507 if (op->type == OP_MM)
4508 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4509}
4510
e28bbd44
AK		 4511static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4512{
4513 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4514 if (!(ctxt->d & ByteOp))
4515 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4516 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4517 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4518 [fastop]"+S"(fop)
4519 : "c"(ctxt->src2.val));
e28bbd44 4520 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4521 if (!fop) /* exception is returned in fop variable */
4522 return emulate_de(ctxt);
e28bbd44
AK		 4523 return X86EMUL_CONTINUE;
4524}
dd856efa 4525
1498507a
BD		 4526void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4527{
573e80fe
BD		 4528 memset(&ctxt->rip_relative, 0,
4529 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4530
1498507a
BD		 4531 ctxt->io_read.pos = 0;
4532 ctxt->io_read.end = 0;
1498507a
BD		 4533 ctxt->mem_read.end = 0;
4534}
4535
7b105ca2 4536int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4537{
0225fb50 4538 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4539 int rc = X86EMUL_CONTINUE;
9dac77fa 4540 int saved_dst_type = ctxt->dst.type;
8b4caf66 4541
9dac77fa 4542 ctxt->mem_read.pos = 0;
310b5d30 4543
e24186e0
PB		 4544 /* LOCK prefix is allowed only with some instructions */
4545 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4546 rc = emulate_ud(ctxt);
1161624f
GN		 4547 goto done;
4548 }
4549
e24186e0 4550 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4551 rc = emulate_ud(ctxt);
d380a5e4
GN		 4552 goto done;
4553 }
4554
d40a6898
PB		 4555 if (unlikely(ctxt->d &
4556 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4557 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4558 (ctxt->d & Undefined)) {
4559 rc = emulate_ud(ctxt);
4560 goto done;
4561 }
1253791d 4562
d40a6898
PB		 4563 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4564 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4565 rc = emulate_ud(ctxt);
cbe2c9d3 4566 goto done;
d40a6898 4567 }
cbe2c9d3 4568
d40a6898
PB		 4569 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4570 rc = emulate_nm(ctxt);
c4f035c6 4571 goto done;
d40a6898 4572 }
c4f035c6 4573
d40a6898
PB		 4574 if (ctxt->d & Mmx) {
4575 rc = flush_pending_x87_faults(ctxt);
4576 if (rc != X86EMUL_CONTINUE)
4577 goto done;
4578 /*
4579 * Now that we know the fpu is exception safe, we can fetch
4580 * operands from it.
4581 */
4582 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4583 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4584 if (!(ctxt->d & Mov))
4585 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4586 }
e92805ac 4587
685bbf4a 4588 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4589 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4590 X86_ICPT_PRE_EXCEPT);
4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593 }
8ea7d6ae 4594
d40a6898
PB		 4595 /* Privileged instruction can be executed only in CPL=0 */
4596 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4597 rc = emulate_gp(ctxt, 0);
d09beabd 4598 goto done;
d40a6898 4599 }
d09beabd 4600
d40a6898
PB		 4601 /* Instruction can only be executed in protected mode */
4602 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4603 rc = emulate_ud(ctxt);
c4f035c6 4604 goto done;
d40a6898 4605 }
c4f035c6 4606
d40a6898 4607 /* Do instruction specific permission checks */
685bbf4a 4608 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4609 rc = ctxt->check_perm(ctxt);
4610 if (rc != X86EMUL_CONTINUE)
4611 goto done;
4612 }
4613
685bbf4a 4614 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4615 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4616 X86_ICPT_POST_EXCEPT);
4617 if (rc != X86EMUL_CONTINUE)
4618 goto done;
4619 }
4620
4621 if (ctxt->rep_prefix && (ctxt->d & String)) {
4622 /* All REP prefixes have the same first termination condition */
4623 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4624 ctxt->eip = ctxt->_eip;
4625 goto done;
4626 }
b9fa9d6b 4627 }
b9fa9d6b
AK		 4628 }
4629
9dac77fa
AK		 4630 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4631 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4632 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4633 if (rc != X86EMUL_CONTINUE)
8b4caf66 4634 goto done;
9dac77fa 4635 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4636 }
4637
9dac77fa
AK		 4638 if (ctxt->src2.type == OP_MEM) {
4639 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4640 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4641 if (rc != X86EMUL_CONTINUE)
4642 goto done;
4643 }
4644
9dac77fa 4645 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4646 goto special_insn;
4647
4648
9dac77fa 4649 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4650 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4651 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4652 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4653 if (rc != X86EMUL_CONTINUE)
4654 goto done;
038e51de 4655 }
9dac77fa 4656 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4657
018a98db
AK		 4658special_insn:
4659
685bbf4a 4660 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4661 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4662 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4663 if (rc != X86EMUL_CONTINUE)
4664 goto done;
4665 }
4666
9dac77fa 4667 if (ctxt->execute) {
e28bbd44
AK		 4668 if (ctxt->d & Fastop) {
4669 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4670 rc = fastop(ctxt, fop);
4671 if (rc != X86EMUL_CONTINUE)
4672 goto done;
4673 goto writeback;
4674 }
9dac77fa 4675 rc = ctxt->execute(ctxt);
ef65c889
AK		 4676 if (rc != X86EMUL_CONTINUE)
4677 goto done;
4678 goto writeback;
4679 }
4680
1ce19dc1 4681 if (ctxt->opcode_len == 2)
6aa8b732 4682 goto twobyte_insn;
0bc5eedb
BP		 4683 else if (ctxt->opcode_len == 3)
4684 goto threebyte_insn;
6aa8b732 4685
9dac77fa 4686 switch (ctxt->b) {
6aa8b732 4687 case 0x63: /* movsxd */
8b4caf66 4688 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4689 goto cannot_emulate;
9dac77fa 4690 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4691 break;
b2833e3c 4692 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4693 if (test_cc(ctxt->b, ctxt->eflags))
4694 jmp_rel(ctxt, ctxt->src.val);
018a98db 4695 break;
7e0b54b1 4696 case 0x8d: /* lea r16/r32, m */
9dac77fa 4697 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4698 break;
3d9e77df 4699 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4700 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4701 ctxt->dst.type = OP_NONE;
4702 else
4703 rc = em_xchg(ctxt);
e4f973ae 4704 break;
e8b6fa70 4705 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4706 switch (ctxt->op_bytes) {
4707 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4708 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4709 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4710 }
4711 break;
6e154e56 4712 case 0xcc: /* int3 */
5c5df76b
TY		 4713 rc = emulate_int(ctxt, 3);
4714 break;
6e154e56 4715 case 0xcd: /* int n */
9dac77fa 4716 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4717 break;
4718 case 0xce: /* into */
5c5df76b
TY		 4719 if (ctxt->eflags & EFLG_OF)
4720 rc = emulate_int(ctxt, 4);
6e154e56 4721 break;
1a52e051 4722 case 0xe9: /* jmp rel */
db5b0762 4723 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4724 jmp_rel(ctxt, ctxt->src.val);
4725 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4726 break;
111de5d6 4727 case 0xf4: /* hlt */
6c3287f7 4728 ctxt->ops->halt(ctxt);
19fdfa0d 4729 break;
111de5d6
AK		 4730 case 0xf5: /* cmc */
4731 /* complement carry flag from eflags reg */
4732 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4733 break;
4734 case 0xf8: /* clc */
4735 ctxt->eflags &= ~EFLG_CF;
111de5d6 4736 break;
8744aa9a
MG		 4737 case 0xf9: /* stc */
4738 ctxt->eflags |= EFLG_CF;
4739 break;
fb4616f4
MG		 4740 case 0xfc: /* cld */
4741 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4742 break;
4743 case 0xfd: /* std */
4744 ctxt->eflags |= EFLG_DF;
fb4616f4 4745 break;
91269b8f
AK		 4746 default:
4747 goto cannot_emulate;
6aa8b732 4748 }
018a98db 4749
7d9ddaed
AK		 4750 if (rc != X86EMUL_CONTINUE)
4751 goto done;
4752
018a98db 4753writeback:
fb32b1ed
AK		 4754 if (ctxt->d & SrcWrite) {
4755 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4756 rc = writeback(ctxt, &ctxt->src);
4757 if (rc != X86EMUL_CONTINUE)
4758 goto done;
4759 }
ee212297
NA		 4760 if (!(ctxt->d & NoWrite)) {
4761 rc = writeback(ctxt, &ctxt->dst);
4762 if (rc != X86EMUL_CONTINUE)
4763 goto done;
4764 }
018a98db 4765
5cd21917
GN		 4766 /*
4767 * restore dst type in case the decoding will be reused
4768 * (happens for string instruction )
4769 */
9dac77fa 4770 ctxt->dst.type = saved_dst_type;
5cd21917 4771
9dac77fa 4772 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4773 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4774
9dac77fa 4775 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4776 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4777
9dac77fa 4778 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4779 unsigned int count;
9dac77fa 4780 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4781 if ((ctxt->d & SrcMask) == SrcSI)
4782 count = ctxt->src.count;
4783 else
4784 count = ctxt->dst.count;
4785 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4786 -count);
3e2f65d5 4787
d2ddd1c4
GN		 4788 if (!string_insn_completed(ctxt)) {
4789 /*
4790 * Re-enter guest when pio read ahead buffer is empty
4791 * or, if it is not used, after each 1024 iteration.
4792 */
dd856efa 4793 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4794 (r->end == 0 || r->end != r->pos)) {
4795 /*
4796 * Reset read cache. Usually happens before
4797 * decode, but since instruction is restarted
4798 * we have to do it here.
4799 */
9dac77fa 4800 ctxt->mem_read.end = 0;
dd856efa 4801 writeback_registers(ctxt);
d2ddd1c4
GN		 4802 return EMULATION_RESTART;
4803 }
4804 goto done; /* skip rip writeback */
0fa6ccbd 4805 }
5cd21917 4806 }
d2ddd1c4 4807
9dac77fa 4808 ctxt->eip = ctxt->_eip;
018a98db
AK		 4809
4810done:
da9cb575
AK		 4811 if (rc == X86EMUL_PROPAGATE_FAULT)
4812 ctxt->have_exception = true;
775fde86
JR		 4813 if (rc == X86EMUL_INTERCEPTED)
4814 return EMULATION_INTERCEPTED;
4815
dd856efa
AK		 4816 if (rc == X86EMUL_CONTINUE)
4817 writeback_registers(ctxt);
4818
d2ddd1c4 4819 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4820
4821twobyte_insn:
9dac77fa 4822 switch (ctxt->b) {
018a98db 4823 case 0x09: /* wbinvd */
cfb22375 4824 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4825 break;
4826 case 0x08: /* invd */
018a98db
AK		 4827 case 0x0d: /* GrpP (prefetch) */
4828 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4829 case 0x1f: /* nop */
018a98db
AK		 4830 break;
4831 case 0x20: /* mov cr, reg */
9dac77fa 4832 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4833 break;
6aa8b732 4834 case 0x21: /* mov from dr to reg */
9dac77fa 4835 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4836 break;
6aa8b732 4837 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4838 if (test_cc(ctxt->b, ctxt->eflags))
4839 ctxt->dst.val = ctxt->src.val;
4840 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4841 ctxt->op_bytes != 4)
9dac77fa 4842 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4843 break;
b2833e3c 4844 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4845 if (test_cc(ctxt->b, ctxt->eflags))
4846 jmp_rel(ctxt, ctxt->src.val);
018a98db 4847 break;
ee45b58e 4848 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4849 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4850 break;
2a7c5b8b
GC		 4851 case 0xae: /* clflush */
4852 break;
6aa8b732 4853 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4854 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4855 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4856 : (u16) ctxt->src.val;
6aa8b732 4857 break;
6aa8b732 4858 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4859 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4860 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4861 (s16) ctxt->src.val;
6aa8b732 4862 break;
a012e65a 4863 case 0xc3: /* movnti */
9dac77fa 4864 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4865 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4866 (u32) ctxt->src.val;
a012e65a 4867 break;
91269b8f
AK		 4868 default:
4869 goto cannot_emulate;
6aa8b732 4870 }
7d9ddaed 4871
0bc5eedb
BP		 4872threebyte_insn:
4873
7d9ddaed
AK		 4874 if (rc != X86EMUL_CONTINUE)
4875 goto done;
4876
6aa8b732
AK		 4877 goto writeback;
4878
4879cannot_emulate:
a0c0ab2f 4880 return EMULATION_FAILED;
6aa8b732 4881}
dd856efa
AK		 4882
4883void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4884{
4885 invalidate_registers(ctxt);
4886}
4887
4888void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4889{
4890 writeback_registers(ctxt);
4891}
Linux kernel - Deliverables
This page took 1.092787 seconds and 5 git commands to generate.