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KVM: x86 emulator: convert group 4 to new style
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
ea9ef04e
AK		 98#define X2(x) x, x
99#define X3(x) X2(x), x
83babbca 100#define X4(x) X2(x), X2(x)
ea9ef04e 101#define X5(x) X4(x), x
83babbca
AK		 102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
591c9d20 108 NoGrp, Group5, Group7, Group8, Group9,
43bb19cd
AK		 109};
110
d65b1dee
AK		 111struct opcode {
112 u32 flags;
120df890
AK		 113 union {
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
fd853310
AK		 124#define D(_y) { .flags = (_y) }
125#define N D(0)
120df890
AK		 126#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
127#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
fd853310 128
5b92b5fa
AK		 129static struct opcode group1[] = {
130 X7(D(Lock)), N
131};
132
99880c5c 133static struct opcode group1A[] = {
42a1c520 134 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
99880c5c
AK		 135};
136
ee70ea30 137static struct opcode group3[] = {
42a1c520
AK		 138 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
139 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
140 X4(D(Undefined)),
ee70ea30
AK		 141};
142
591c9d20 143static struct opcode group4[] = {
42a1c520
AK		 144 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
145 N, N, N, N, N, N,
591c9d20
AK		 146};
147
148static struct opcode group_table[] = {
42a1c520
AK		 149 [Group5*8] =
150 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
151 D(SrcMem | ModRM | Stack), N,
152 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
153 D(SrcMem | ModRM | Stack), N,
154 [Group7*8] =
155 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
156 D(SrcNone | ModRM | DstMem | Mov), N,
157 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
158 [Group8*8] =
159 N, N, N, N,
160 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
161 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
162 [Group9*8] =
163 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
164};
165
166static struct opcode group2_table[] = {
167 [Group7*8] =
168 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
169 D(SrcNone | ModRM | DstMem | Mov), N,
170 D(SrcMem16 | ModRM | Mov | Priv), N,
171 [Group9*8] =
172 N, N, N, N, N, N, N, N,
173};
174
d65b1dee 175static struct opcode opcode_table[256] = {
6aa8b732 176 /* 0x00 - 0x07 */
fd853310
AK		 177 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
178 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
179 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
180 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 181 /* 0x08 - 0x0F */
fd853310
AK		 182 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
183 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
184 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
185 D(ImplicitOps | Stack | No64), N,
6aa8b732 186 /* 0x10 - 0x17 */
fd853310
AK		 187 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
188 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
189 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
190 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 191 /* 0x18 - 0x1F */
fd853310
AK		 192 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
193 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
194 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
195 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 196 /* 0x20 - 0x27 */
fd853310
AK		 197 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
198 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
199 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 200 /* 0x28 - 0x2F */
fd853310
AK		 201 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
202 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
203 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 204 /* 0x30 - 0x37 */
fd853310
AK		 205 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
206 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
207 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 208 /* 0x38 - 0x3F */
fd853310
AK		 209 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
210 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
211 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
212 N, N,
749358a6 213 /* 0x40 - 0x4F */
fd853310 214 X16(D(DstReg)),
7f0aaee0 215 /* 0x50 - 0x57 */
fd853310 216 X8(D(SrcReg | Stack)),
7f0aaee0 217 /* 0x58 - 0x5F */
fd853310 218 X8(D(DstReg | Stack)),
7d316911 219 /* 0x60 - 0x67 */
fd853310
AK		 220 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
221 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
222 N, N, N, N,
7d316911 223 /* 0x68 - 0x6F */
fd853310
AK		 224 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
225 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
226 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 227 /* 0x70 - 0x7F */
fd853310 228 X16(D(SrcImmByte)),
6aa8b732 229 /* 0x80 - 0x87 */
5b92b5fa
AK		 230 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
231 G(DstMem | SrcImm | ModRM | Group, group1),
232 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
233 G(DstMem | SrcImmByte | ModRM | Group, group1),
fd853310
AK		 234 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
235 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 236 /* 0x88 - 0x8F */
fd853310
AK		 237 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
238 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
239 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
99880c5c 240 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
b13354f8 241 /* 0x90 - 0x97 */
fd853310 242 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 243 /* 0x98 - 0x9F */
fd853310
AK		 244 N, N, D(SrcImmFAddr | No64), N,
245 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 246 /* 0xA0 - 0xA7 */
fd853310
AK		 247 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
248 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
249 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
250 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 251 /* 0xA8 - 0xAF */
fd853310
AK		 252 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
253 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
254 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 255 /* 0xB0 - 0xB7 */
fd853310 256 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 257 /* 0xB8 - 0xBF */
fd853310 258 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 259 /* 0xC0 - 0xC7 */
fd853310
AK		 260 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
261 N, D(ImplicitOps | Stack), N, N,
262 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 263 /* 0xC8 - 0xCF */
fd853310
AK		 264 N, N, N, D(ImplicitOps | Stack),
265 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 266 /* 0xD0 - 0xD7 */
fd853310
AK		 267 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
268 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
269 N, N, N, N,
6aa8b732 270 /* 0xD8 - 0xDF */
fd853310 271 N, N, N, N, N, N, N, N,
098c937b 272 /* 0xE0 - 0xE7 */
fd853310
AK		 273 N, N, N, N,
274 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
275 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 276 /* 0xE8 - 0xEF */
fd853310
AK		 277 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
278 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
279 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
280 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 281 /* 0xF0 - 0xF7 */
fd853310 282 N, N, N, N,
ee70ea30 283 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
6aa8b732 284 /* 0xF8 - 0xFF */
fd853310 285 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
591c9d20 286 D(ImplicitOps), D(ImplicitOps), G(0, group4), D(Group | Group5),
6aa8b732
AK		 287};
288
d65b1dee 289static struct opcode twobyte_table[256] = {
6aa8b732 290 /* 0x00 - 0x0F */
fd853310
AK		 291 N, D(Group | GroupDual | Group7), N, N,
292 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
293 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
294 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 295 /* 0x10 - 0x1F */
fd853310 296 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 297 /* 0x20 - 0x2F */
fd853310
AK		 298 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
299 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
300 N, N, N, N,
301 N, N, N, N, N, N, N, N,
6aa8b732 302 /* 0x30 - 0x3F */
fd853310
AK		 303 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
304 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
305 N, N, N, N, N, N, N, N,
be8eacdd 306 /* 0x40 - 0x4F */
fd853310 307 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 308 /* 0x50 - 0x5F */
fd853310 309 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 310 /* 0x60 - 0x6F */
fd853310 311 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 312 /* 0x70 - 0x7F */
fd853310 313 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 314 /* 0x80 - 0x8F */
fd853310 315 X16(D(SrcImm)),
6aa8b732 316 /* 0x90 - 0x9F */
fd853310 317 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 318 /* 0xA0 - 0xA7 */
fd853310
AK		 319 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
320 N, D(DstMem | SrcReg | ModRM | BitOp),
321 D(DstMem | SrcReg | Src2ImmByte | ModRM),
322 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 323 /* 0xA8 - 0xAF */
fd853310
AK		 324 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
325 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
326 D(DstMem | SrcReg | Src2ImmByte | ModRM),
327 D(DstMem | SrcReg | Src2CL | ModRM),
328 D(ModRM), N,
6aa8b732 329 /* 0xB0 - 0xB7 */
fd853310
AK		 330 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
331 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
332 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
333 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 334 /* 0xB8 - 0xBF */
fd853310
AK		 335 N, N,
336 D(Group | Group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
337 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
338 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 339 /* 0xC0 - 0xCF */
fd853310
AK		 340 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
341 N, N, N, D(Group | GroupDual | Group9),
342 N, N, N, N, N, N, N, N,
6aa8b732 343 /* 0xD0 - 0xDF */
fd853310 344 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 345 /* 0xE0 - 0xEF */
fd853310 346 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 347 /* 0xF0 - 0xFF */
fd853310 348 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 349};
350
fd853310
AK		 351#undef D
352#undef N
120df890
AK		 353#undef G
354#undef GD
fd853310 355
6aa8b732 356/* EFLAGS bit definitions. */
d4c6a154
GN		 357#define EFLG_ID (1<<21)
358#define EFLG_VIP (1<<20)
359#define EFLG_VIF (1<<19)
360#define EFLG_AC (1<<18)
b1d86143
AP		 361#define EFLG_VM (1<<17)
362#define EFLG_RF (1<<16)
d4c6a154
GN		 363#define EFLG_IOPL (3<<12)
364#define EFLG_NT (1<<14)
6aa8b732
AK		 365#define EFLG_OF (1<<11)
366#define EFLG_DF (1<<10)
b1d86143 367#define EFLG_IF (1<<9)
d4c6a154 368#define EFLG_TF (1<<8)
6aa8b732
AK		 369#define EFLG_SF (1<<7)
370#define EFLG_ZF (1<<6)
371#define EFLG_AF (1<<4)
372#define EFLG_PF (1<<2)
373#define EFLG_CF (1<<0)
374
62bd430e
MG		 375#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
376#define EFLG_RESERVED_ONE_MASK 2
377
6aa8b732
AK		 378/*
379 * Instruction emulation:
380 * Most instructions are emulated directly via a fragment of inline assembly
381 * code. This allows us to save/restore EFLAGS and thus very easily pick up
382 * any modified flags.
383 */
384
05b3e0c2 385#if defined(CONFIG_X86_64)
6aa8b732
AK		 386#define _LO32 "k" /* force 32-bit operand */
387#define _STK "%%rsp" /* stack pointer */
388#elif defined(__i386__)
389#define _LO32 "" /* force 32-bit operand */
390#define _STK "%%esp" /* stack pointer */
391#endif
392
393/*
394 * These EFLAGS bits are restored from saved value during emulation, and
395 * any changes are written back to the saved value after emulation.
396 */
397#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
398
399/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 400#define _PRE_EFLAGS(_sav, _msk, _tmp) \
401 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
402 "movl %"_sav",%"_LO32 _tmp"; " \
403 "push %"_tmp"; " \
404 "push %"_tmp"; " \
405 "movl %"_msk",%"_LO32 _tmp"; " \
406 "andl %"_LO32 _tmp",("_STK"); " \
407 "pushf; " \
408 "notl %"_LO32 _tmp"; " \
409 "andl %"_LO32 _tmp",("_STK"); " \
410 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
411 "pop %"_tmp"; " \
412 "orl %"_LO32 _tmp",("_STK"); " \
413 "popf; " \
414 "pop %"_sav"; "
6aa8b732
AK		 415
416/* After executing instruction: write-back necessary bits in EFLAGS. */
417#define _POST_EFLAGS(_sav, _msk, _tmp) \
418 /* _sav |= EFLAGS & _msk; */ \
419 "pushf; " \
420 "pop %"_tmp"; " \
421 "andl %"_msk",%"_LO32 _tmp"; " \
422 "orl %"_LO32 _tmp",%"_sav"; "
423
dda96d8f
AK		 424#ifdef CONFIG_X86_64
425#define ON64(x) x
426#else
427#define ON64(x)
428#endif
429
6b7ad61f
AK		 430#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
431 do { \
432 __asm__ __volatile__ ( \
433 _PRE_EFLAGS("0", "4", "2") \
434 _op _suffix " %"_x"3,%1; " \
435 _POST_EFLAGS("0", "4", "2") \
436 : "=m" (_eflags), "=m" ((_dst).val), \
437 "=&r" (_tmp) \
438 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 439 } while (0)
6b7ad61f
AK		 440
441
6aa8b732
AK		 442/* Raw emulation: instruction has two explicit operands. */
443#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 444 do { \
445 unsigned long _tmp; \
446 \
447 switch ((_dst).bytes) { \
448 case 2: \
449 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
450 break; \
451 case 4: \
452 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
453 break; \
454 case 8: \
455 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
456 break; \
457 } \
6aa8b732
AK		 458 } while (0)
459
460#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
461 do { \
6b7ad61f 462 unsigned long _tmp; \
d77c26fc 463 switch ((_dst).bytes) { \
6aa8b732 464 case 1: \
6b7ad61f 465 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 466 break; \
467 default: \
468 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
469 _wx, _wy, _lx, _ly, _qx, _qy); \
470 break; \
471 } \
472 } while (0)
473
474/* Source operand is byte-sized and may be restricted to just %cl. */
475#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
476 __emulate_2op(_op, _src, _dst, _eflags, \
477 "b", "c", "b", "c", "b", "c", "b", "c")
478
479/* Source operand is byte, word, long or quad sized. */
480#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
481 __emulate_2op(_op, _src, _dst, _eflags, \
482 "b", "q", "w", "r", _LO32, "r", "", "r")
483
484/* Source operand is word, long or quad sized. */
485#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
486 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
487 "w", "r", _LO32, "r", "", "r")
488
d175226a
GT		 489/* Instruction has three operands and one operand is stored in ECX register */
490#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
491 do { \
492 unsigned long _tmp; \
493 _type _clv = (_cl).val; \
494 _type _srcv = (_src).val; \
495 _type _dstv = (_dst).val; \
496 \
497 __asm__ __volatile__ ( \
498 _PRE_EFLAGS("0", "5", "2") \
499 _op _suffix " %4,%1 \n" \
500 _POST_EFLAGS("0", "5", "2") \
501 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
502 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
503 ); \
504 \
505 (_cl).val = (unsigned long) _clv; \
506 (_src).val = (unsigned long) _srcv; \
507 (_dst).val = (unsigned long) _dstv; \
508 } while (0)
509
510#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
511 do { \
512 switch ((_dst).bytes) { \
513 case 2: \
514 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
515 "w", unsigned short); \
516 break; \
517 case 4: \
518 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
519 "l", unsigned int); \
520 break; \
521 case 8: \
522 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
523 "q", unsigned long)); \
524 break; \
525 } \
526 } while (0)
527
dda96d8f 528#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 529 do { \
530 unsigned long _tmp; \
531 \
dda96d8f
AK		 532 __asm__ __volatile__ ( \
533 _PRE_EFLAGS("0", "3", "2") \
534 _op _suffix " %1; " \
535 _POST_EFLAGS("0", "3", "2") \
536 : "=m" (_eflags), "+m" ((_dst).val), \
537 "=&r" (_tmp) \
538 : "i" (EFLAGS_MASK)); \
539 } while (0)
540
541/* Instruction has only one explicit operand (no source operand). */
542#define emulate_1op(_op, _dst, _eflags) \
543 do { \
d77c26fc 544 switch ((_dst).bytes) { \
dda96d8f
AK		 545 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
546 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
547 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
548 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 549 } \
550 } while (0)
551
6aa8b732
AK		 552/* Fetch next part of the instruction being emulated. */
553#define insn_fetch(_type, _size, _eip) \
554({ unsigned long _x; \
62266869 555 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 556 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 557 goto done; \
558 (_eip) += (_size); \
559 (_type)_x; \
560})
561
414e6277
GN		 562#define insn_fetch_arr(_arr, _size, _eip) \
563({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
564 if (rc != X86EMUL_CONTINUE) \
565 goto done; \
566 (_eip) += (_size); \
567})
568
ddcb2885
HH		 569static inline unsigned long ad_mask(struct decode_cache *c)
570{
571 return (1UL << (c->ad_bytes << 3)) - 1;
572}
573
6aa8b732 574/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 575static inline unsigned long
576address_mask(struct decode_cache *c, unsigned long reg)
577{
578 if (c->ad_bytes == sizeof(unsigned long))
579 return reg;
580 else
581 return reg & ad_mask(c);
582}
583
584static inline unsigned long
585register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
586{
587 return base + address_mask(c, reg);
588}
589
7a957275
HH		 590static inline void
591register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
592{
593 if (c->ad_bytes == sizeof(unsigned long))
594 *reg += inc;
595 else
596 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
597}
6aa8b732 598
7a957275
HH		 599static inline void jmp_rel(struct decode_cache *c, int rel)
600{
601 register_address_increment(c, &c->eip, rel);
602}
098c937b 603
7a5b56df
AK		 604static void set_seg_override(struct decode_cache *c, int seg)
605{
606 c->has_seg_override = true;
607 c->seg_override = seg;
608}
609
79168fd1
GN		 610static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
611 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 612{
613 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
614 return 0;
615
79168fd1 616 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 617}
618
619static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 620 struct x86_emulate_ops *ops,
7a5b56df
AK		 621 struct decode_cache *c)
622{
623 if (!c->has_seg_override)
624 return 0;
625
79168fd1 626 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 627}
628
79168fd1
GN		 629static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
630 struct x86_emulate_ops *ops)
7a5b56df 631{
79168fd1 632 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 633}
634
79168fd1
GN		 635static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
636 struct x86_emulate_ops *ops)
7a5b56df 637{
79168fd1 638 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 639}
640
54b8486f
GN		 641static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
642 u32 error, bool valid)
643{
644 ctxt->exception = vec;
645 ctxt->error_code = error;
646 ctxt->error_code_valid = valid;
647 ctxt->restart = false;
648}
649
650static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
651{
652 emulate_exception(ctxt, GP_VECTOR, err, true);
653}
654
655static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
656 int err)
657{
658 ctxt->cr2 = addr;
659 emulate_exception(ctxt, PF_VECTOR, err, true);
660}
661
662static void emulate_ud(struct x86_emulate_ctxt *ctxt)
663{
664 emulate_exception(ctxt, UD_VECTOR, 0, false);
665}
666
667static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
668{
669 emulate_exception(ctxt, TS_VECTOR, err, true);
670}
671
62266869
AK		 672static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
2fb53ad8 674 unsigned long eip, u8 *dest)
62266869
AK		 675{
676 struct fetch_cache *fc = &ctxt->decode.fetch;
677 int rc;
2fb53ad8 678 int size, cur_size;
62266869 679
2fb53ad8
AK		 680 if (eip == fc->end) {
681 cur_size = fc->end - fc->start;
682 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
683 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
684 size, ctxt->vcpu, NULL);
3e2815e9 685 if (rc != X86EMUL_CONTINUE)
62266869 686 return rc;
2fb53ad8 687 fc->end += size;
62266869 688 }
2fb53ad8 689 *dest = fc->data[eip - fc->start];
3e2815e9 690 return X86EMUL_CONTINUE;
62266869
AK		 691}
692
693static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
694 struct x86_emulate_ops *ops,
695 unsigned long eip, void *dest, unsigned size)
696{
3e2815e9 697 int rc;
62266869 698
eb3c79e6 699 /* x86 instructions are limited to 15 bytes. */
063db061 700 if (eip + size - ctxt->eip > 15)
eb3c79e6 701 return X86EMUL_UNHANDLEABLE;
62266869
AK		 702 while (size--) {
703 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 704 if (rc != X86EMUL_CONTINUE)
62266869
AK		 705 return rc;
706 }
3e2815e9 707 return X86EMUL_CONTINUE;
62266869
AK		 708}
709
1e3c5cb0
RR		 710/*
711 * Given the 'reg' portion of a ModRM byte, and a register block, return a
712 * pointer into the block that addresses the relevant register.
713 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
714 */
715static void *decode_register(u8 modrm_reg, unsigned long *regs,
716 int highbyte_regs)
6aa8b732
AK		 717{
718 void *p;
719
720 p = &regs[modrm_reg];
721 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
722 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
723 return p;
724}
725
726static int read_descriptor(struct x86_emulate_ctxt *ctxt,
727 struct x86_emulate_ops *ops,
728 void *ptr,
729 u16 *size, unsigned long *address, int op_bytes)
730{
731 int rc;
732
733 if (op_bytes == 2)
734 op_bytes = 3;
735 *address = 0;
cebff02b 736 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 737 ctxt->vcpu, NULL);
1b30eaa8 738 if (rc != X86EMUL_CONTINUE)
6aa8b732 739 return rc;
cebff02b 740 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 741 ctxt->vcpu, NULL);
6aa8b732
AK		 742 return rc;
743}
744
bbe9abbd
NK		 745static int test_cc(unsigned int condition, unsigned int flags)
746{
747 int rc = 0;
748
749 switch ((condition & 15) >> 1) {
750 case 0: /* o */
751 rc |= (flags & EFLG_OF);
752 break;
753 case 1: /* b/c/nae */
754 rc |= (flags & EFLG_CF);
755 break;
756 case 2: /* z/e */
757 rc |= (flags & EFLG_ZF);
758 break;
759 case 3: /* be/na */
760 rc |= (flags & (EFLG_CF|EFLG_ZF));
761 break;
762 case 4: /* s */
763 rc |= (flags & EFLG_SF);
764 break;
765 case 5: /* p/pe */
766 rc |= (flags & EFLG_PF);
767 break;
768 case 7: /* le/ng */
769 rc |= (flags & EFLG_ZF);
770 /* fall through */
771 case 6: /* l/nge */
772 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
773 break;
774 }
775
776 /* Odd condition identifiers (lsb == 1) have inverted sense. */
777 return (!!rc ^ (condition & 1));
778}
779
3c118e24
AK		 780static void decode_register_operand(struct operand *op,
781 struct decode_cache *c,
3c118e24
AK		 782 int inhibit_bytereg)
783{
33615aa9 784 unsigned reg = c->modrm_reg;
9f1ef3f8 785 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 786
787 if (!(c->d & ModRM))
788 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 789 op->type = OP_REG;
790 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 791 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 792 op->val = *(u8 *)op->ptr;
793 op->bytes = 1;
794 } else {
33615aa9 795 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 796 op->bytes = c->op_bytes;
797 switch (op->bytes) {
798 case 2:
799 op->val = *(u16 *)op->ptr;
800 break;
801 case 4:
802 op->val = *(u32 *)op->ptr;
803 break;
804 case 8:
805 op->val = *(u64 *) op->ptr;
806 break;
807 }
808 }
809 op->orig_val = op->val;
810}
811
1c73ef66
AK		 812static int decode_modrm(struct x86_emulate_ctxt *ctxt,
813 struct x86_emulate_ops *ops)
814{
815 struct decode_cache *c = &ctxt->decode;
816 u8 sib;
f5b4edcd 817 int index_reg = 0, base_reg = 0, scale;
3e2815e9 818 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 819
820 if (c->rex_prefix) {
821 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
822 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
823 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
824 }
825
826 c->modrm = insn_fetch(u8, 1, c->eip);
827 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
828 c->modrm_reg |= (c->modrm & 0x38) >> 3;
829 c->modrm_rm |= (c->modrm & 0x07);
830 c->modrm_ea = 0;
831 c->use_modrm_ea = 1;
832
833 if (c->modrm_mod == 3) {
107d6d2e
AK		 834 c->modrm_ptr = decode_register(c->modrm_rm,
835 c->regs, c->d & ByteOp);
836 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 837 return rc;
838 }
839
840 if (c->ad_bytes == 2) {
841 unsigned bx = c->regs[VCPU_REGS_RBX];
842 unsigned bp = c->regs[VCPU_REGS_RBP];
843 unsigned si = c->regs[VCPU_REGS_RSI];
844 unsigned di = c->regs[VCPU_REGS_RDI];
845
846 /* 16-bit ModR/M decode. */
847 switch (c->modrm_mod) {
848 case 0:
849 if (c->modrm_rm == 6)
850 c->modrm_ea += insn_fetch(u16, 2, c->eip);
851 break;
852 case 1:
853 c->modrm_ea += insn_fetch(s8, 1, c->eip);
854 break;
855 case 2:
856 c->modrm_ea += insn_fetch(u16, 2, c->eip);
857 break;
858 }
859 switch (c->modrm_rm) {
860 case 0:
861 c->modrm_ea += bx + si;
862 break;
863 case 1:
864 c->modrm_ea += bx + di;
865 break;
866 case 2:
867 c->modrm_ea += bp + si;
868 break;
869 case 3:
870 c->modrm_ea += bp + di;
871 break;
872 case 4:
873 c->modrm_ea += si;
874 break;
875 case 5:
876 c->modrm_ea += di;
877 break;
878 case 6:
879 if (c->modrm_mod != 0)
880 c->modrm_ea += bp;
881 break;
882 case 7:
883 c->modrm_ea += bx;
884 break;
885 }
886 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
887 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 888 if (!c->has_seg_override)
889 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 890 c->modrm_ea = (u16)c->modrm_ea;
891 } else {
892 /* 32/64-bit ModR/M decode. */
84411d85 893 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 894 sib = insn_fetch(u8, 1, c->eip);
895 index_reg |= (sib >> 3) & 7;
896 base_reg |= sib & 7;
897 scale = sib >> 6;
898
dc71d0f1
AK		 899 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
900 c->modrm_ea += insn_fetch(s32, 4, c->eip);
901 else
1c73ef66 902 c->modrm_ea += c->regs[base_reg];
dc71d0f1 903 if (index_reg != 4)
1c73ef66 904 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 905 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
906 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 907 c->rip_relative = 1;
84411d85 908 } else
1c73ef66 909 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 910 switch (c->modrm_mod) {
911 case 0:
912 if (c->modrm_rm == 5)
913 c->modrm_ea += insn_fetch(s32, 4, c->eip);
914 break;
915 case 1:
916 c->modrm_ea += insn_fetch(s8, 1, c->eip);
917 break;
918 case 2:
919 c->modrm_ea += insn_fetch(s32, 4, c->eip);
920 break;
921 }
922 }
1c73ef66
AK		 923done:
924 return rc;
925}
926
927static int decode_abs(struct x86_emulate_ctxt *ctxt,
928 struct x86_emulate_ops *ops)
929{
930 struct decode_cache *c = &ctxt->decode;
3e2815e9 931 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 932
933 switch (c->ad_bytes) {
934 case 2:
935 c->modrm_ea = insn_fetch(u16, 2, c->eip);
936 break;
937 case 4:
938 c->modrm_ea = insn_fetch(u32, 4, c->eip);
939 break;
940 case 8:
941 c->modrm_ea = insn_fetch(u64, 8, c->eip);
942 break;
943 }
944done:
945 return rc;
946}
947
6aa8b732 948int
8b4caf66 949x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 950{
e4e03ded 951 struct decode_cache *c = &ctxt->decode;
3e2815e9 952 int rc = X86EMUL_CONTINUE;
6aa8b732 953 int mode = ctxt->mode;
120df890
AK		 954 int def_op_bytes, def_ad_bytes, group, dual, goffset;
955 struct opcode opcode, *g_mod012, *g_mod3;
6aa8b732 956
5cd21917
GN		 957 /* we cannot decode insn before we complete previous rep insn */
958 WARN_ON(ctxt->restart);
959
063db061 960 c->eip = ctxt->eip;
2fb53ad8 961 c->fetch.start = c->fetch.end = c->eip;
79168fd1 962 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 963
964 switch (mode) {
965 case X86EMUL_MODE_REAL:
a0044755 966 case X86EMUL_MODE_VM86:
6aa8b732 967 case X86EMUL_MODE_PROT16:
f21b8bf4 968 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 969 break;
970 case X86EMUL_MODE_PROT32:
f21b8bf4 971 def_op_bytes = def_ad_bytes = 4;
6aa8b732 972 break;
05b3e0c2 973#ifdef CONFIG_X86_64
6aa8b732 974 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 975 def_op_bytes = 4;
976 def_ad_bytes = 8;
6aa8b732
AK		 977 break;
978#endif
979 default:
980 return -1;
981 }
982
f21b8bf4
AK		 983 c->op_bytes = def_op_bytes;
984 c->ad_bytes = def_ad_bytes;
985
6aa8b732 986 /* Legacy prefixes. */
b4c6abfe 987 for (;;) {
e4e03ded 988 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 989 case 0x66: /* operand-size override */
f21b8bf4
AK		 990 /* switch between 2/4 bytes */
991 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 992 break;
993 case 0x67: /* address-size override */
994 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 995 /* switch between 4/8 bytes */
f21b8bf4 996 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 997 else
e4e03ded 998 /* switch between 2/4 bytes */
f21b8bf4 999 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 1000 break;
7a5b56df 1001 case 0x26: /* ES override */
6aa8b732 1002 case 0x2e: /* CS override */
7a5b56df 1003 case 0x36: /* SS override */
6aa8b732 1004 case 0x3e: /* DS override */
7a5b56df 1005 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1006 break;
1007 case 0x64: /* FS override */
6aa8b732 1008 case 0x65: /* GS override */
7a5b56df 1009 set_seg_override(c, c->b & 7);
6aa8b732 1010 break;
b4c6abfe
LV		 1011 case 0x40 ... 0x4f: /* REX */
1012 if (mode != X86EMUL_MODE_PROT64)
1013 goto done_prefixes;
33615aa9 1014 c->rex_prefix = c->b;
b4c6abfe 1015 continue;
6aa8b732 1016 case 0xf0: /* LOCK */
e4e03ded 1017 c->lock_prefix = 1;
6aa8b732 1018 break;
ae6200ba 1019 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1020 c->rep_prefix = REPNE_PREFIX;
1021 break;
6aa8b732 1022 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1023 c->rep_prefix = REPE_PREFIX;
6aa8b732 1024 break;
6aa8b732
AK		 1025 default:
1026 goto done_prefixes;
1027 }
b4c6abfe
LV		 1028
1029 /* Any legacy prefix after a REX prefix nullifies its effect. */
1030
33615aa9 1031 c->rex_prefix = 0;
6aa8b732
AK		 1032 }
1033
1034done_prefixes:
1035
1036 /* REX prefix. */
1c73ef66 1037 if (c->rex_prefix)
33615aa9 1038 if (c->rex_prefix & 8)
e4e03ded 1039 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1040
1041 /* Opcode byte(s). */
120df890
AK		 1042 opcode = opcode_table[c->b];
1043 if (opcode.flags == 0) {
6aa8b732 1044 /* Two-byte opcode? */
e4e03ded
LV		 1045 if (c->b == 0x0f) {
1046 c->twobyte = 1;
1047 c->b = insn_fetch(u8, 1, c->eip);
120df890 1048 opcode = twobyte_table[c->b];
6aa8b732 1049 }
e09d082c 1050 }
120df890 1051 c->d = opcode.flags;
6aa8b732 1052
e09d082c
AK		 1053 if (c->d & Group) {
1054 group = c->d & GroupMask;
52811d7d 1055 dual = c->d & GroupDual;
e09d082c
AK		 1056 c->modrm = insn_fetch(u8, 1, c->eip);
1057 --c->eip;
1058
120df890
AK		 1059 if (group) {
1060 g_mod012 = g_mod3 = &group_table[group * 8];
1061 if (c->d & GroupDual)
1062 g_mod3 = &group2_table[group * 8];
1063 } else {
1064 if (c->d & GroupDual) {
1065 g_mod012 = opcode.u.gdual->mod012;
1066 g_mod3 = opcode.u.gdual->mod3;
1067 } else
1068 g_mod012 = g_mod3 = opcode.u.group;
1069 }
1070
52811d7d 1071 c->d &= ~(Group | GroupDual | GroupMask);
120df890
AK		 1072
1073 goffset = (c->modrm >> 3) & 7;
1074
1075 if ((c->modrm >> 6) == 3)
1076 opcode = g_mod3[goffset];
e09d082c 1077 else
120df890
AK		 1078 opcode = g_mod012[goffset];
1079 c->d |= opcode.flags;
e09d082c
AK		 1080 }
1081
1082 /* Unrecognised? */
047a4818 1083 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1084 DPRINTF("Cannot emulate %02x\n", c->b);
1085 return -1;
6aa8b732
AK		 1086 }
1087
6e3d5dfb
AK		 1088 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1089 c->op_bytes = 8;
1090
6aa8b732 1091 /* ModRM and SIB bytes. */
1c73ef66
AK		 1092 if (c->d & ModRM)
1093 rc = decode_modrm(ctxt, ops);
1094 else if (c->d & MemAbs)
1095 rc = decode_abs(ctxt, ops);
3e2815e9 1096 if (rc != X86EMUL_CONTINUE)
1c73ef66 1097 goto done;
6aa8b732 1098
7a5b56df
AK		 1099 if (!c->has_seg_override)
1100 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1101
7a5b56df 1102 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1103 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1104
1105 if (c->ad_bytes != 8)
1106 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1107
1108 if (c->rip_relative)
1109 c->modrm_ea += c->eip;
1110
6aa8b732
AK		 1111 /*
1112 * Decode and fetch the source operand: register, memory
1113 * or immediate.
1114 */
e4e03ded 1115 switch (c->d & SrcMask) {
6aa8b732
AK		 1116 case SrcNone:
1117 break;
1118 case SrcReg:
9f1ef3f8 1119 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1120 break;
1121 case SrcMem16:
e4e03ded 1122 c->src.bytes = 2;
6aa8b732
AK		 1123 goto srcmem_common;
1124 case SrcMem32:
e4e03ded 1125 c->src.bytes = 4;
6aa8b732
AK		 1126 goto srcmem_common;
1127 case SrcMem:
e4e03ded
LV		 1128 c->src.bytes = (c->d & ByteOp) ? 1 :
1129 c->op_bytes;
b85b9ee9 1130 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1131 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1132 break;
d77c26fc 1133 srcmem_common:
4e62417b
AJ		 1134 /*
1135 * For instructions with a ModR/M byte, switch to register
1136 * access if Mod = 3.
1137 */
e4e03ded
LV		 1138 if ((c->d & ModRM) && c->modrm_mod == 3) {
1139 c->src.type = OP_REG;
66b85505 1140 c->src.val = c->modrm_val;
107d6d2e 1141 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1142 break;
1143 }
e4e03ded 1144 c->src.type = OP_MEM;
69f55cb1
GN		 1145 c->src.ptr = (unsigned long *)c->modrm_ea;
1146 c->src.val = 0;
6aa8b732
AK		 1147 break;
1148 case SrcImm:
c9eaf20f 1149 case SrcImmU:
e4e03ded
LV		 1150 c->src.type = OP_IMM;
1151 c->src.ptr = (unsigned long *)c->eip;
1152 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1153 if (c->src.bytes == 8)
1154 c->src.bytes = 4;
6aa8b732 1155 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1156 switch (c->src.bytes) {
6aa8b732 1157 case 1:
e4e03ded 1158 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1159 break;
1160 case 2:
e4e03ded 1161 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1162 break;
1163 case 4:
e4e03ded 1164 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1165 break;
1166 }
c9eaf20f
AK		 1167 if ((c->d & SrcMask) == SrcImmU) {
1168 switch (c->src.bytes) {
1169 case 1:
1170 c->src.val &= 0xff;
1171 break;
1172 case 2:
1173 c->src.val &= 0xffff;
1174 break;
1175 case 4:
1176 c->src.val &= 0xffffffff;
1177 break;
1178 }
1179 }
6aa8b732
AK		 1180 break;
1181 case SrcImmByte:
341de7e3 1182 case SrcImmUByte:
e4e03ded
LV		 1183 c->src.type = OP_IMM;
1184 c->src.ptr = (unsigned long *)c->eip;
1185 c->src.bytes = 1;
341de7e3
GN		 1186 if ((c->d & SrcMask) == SrcImmByte)
1187 c->src.val = insn_fetch(s8, 1, c->eip);
1188 else
1189 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1190 break;
5d55f299
WY		 1191 case SrcAcc:
1192 c->src.type = OP_REG;
1193 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1194 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1195 switch (c->src.bytes) {
1196 case 1:
1197 c->src.val = *(u8 *)c->src.ptr;
1198 break;
1199 case 2:
1200 c->src.val = *(u16 *)c->src.ptr;
1201 break;
1202 case 4:
1203 c->src.val = *(u32 *)c->src.ptr;
1204 break;
1205 case 8:
1206 c->src.val = *(u64 *)c->src.ptr;
1207 break;
1208 }
1209 break;
bfcadf83
GT		 1210 case SrcOne:
1211 c->src.bytes = 1;
1212 c->src.val = 1;
1213 break;
a682e354
GN		 1214 case SrcSI:
1215 c->src.type = OP_MEM;
1216 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1217 c->src.ptr = (unsigned long *)
79168fd1 1218 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1219 c->regs[VCPU_REGS_RSI]);
1220 c->src.val = 0;
1221 break;
414e6277
GN		 1222 case SrcImmFAddr:
1223 c->src.type = OP_IMM;
1224 c->src.ptr = (unsigned long *)c->eip;
1225 c->src.bytes = c->op_bytes + 2;
1226 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1227 break;
1228 case SrcMemFAddr:
1229 c->src.type = OP_MEM;
1230 c->src.ptr = (unsigned long *)c->modrm_ea;
1231 c->src.bytes = c->op_bytes + 2;
1232 break;
6aa8b732
AK		 1233 }
1234
0dc8d10f
GT		 1235 /*
1236 * Decode and fetch the second source operand: register, memory
1237 * or immediate.
1238 */
1239 switch (c->d & Src2Mask) {
1240 case Src2None:
1241 break;
1242 case Src2CL:
1243 c->src2.bytes = 1;
1244 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1245 break;
1246 case Src2ImmByte:
1247 c->src2.type = OP_IMM;
1248 c->src2.ptr = (unsigned long *)c->eip;
1249 c->src2.bytes = 1;
1250 c->src2.val = insn_fetch(u8, 1, c->eip);
1251 break;
1252 case Src2One:
1253 c->src2.bytes = 1;
1254 c->src2.val = 1;
1255 break;
1256 }
1257
038e51de 1258 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1259 switch (c->d & DstMask) {
038e51de
AK		 1260 case ImplicitOps:
1261 /* Special instructions do their own operand decoding. */
8b4caf66 1262 return 0;
038e51de 1263 case DstReg:
9f1ef3f8 1264 decode_register_operand(&c->dst, c,
3c118e24 1265 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1266 break;
1267 case DstMem:
6550e1f1 1268 case DstMem64:
e4e03ded 1269 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1270 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1271 c->dst.type = OP_REG;
66b85505 1272 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1273 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1274 break;
1275 }
8b4caf66 1276 c->dst.type = OP_MEM;
69f55cb1 1277 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1278 if ((c->d & DstMask) == DstMem64)
1279 c->dst.bytes = 8;
1280 else
1281 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1282 c->dst.val = 0;
1283 if (c->d & BitOp) {
1284 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1285
1286 c->dst.ptr = (void *)c->dst.ptr +
1287 (c->src.val & mask) / 8;
1288 }
8b4caf66 1289 break;
9c9fddd0
GT		 1290 case DstAcc:
1291 c->dst.type = OP_REG;
d6d367d6 1292 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1293 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1294 switch (c->dst.bytes) {
9c9fddd0
GT		 1295 case 1:
1296 c->dst.val = *(u8 *)c->dst.ptr;
1297 break;
1298 case 2:
1299 c->dst.val = *(u16 *)c->dst.ptr;
1300 break;
1301 case 4:
1302 c->dst.val = *(u32 *)c->dst.ptr;
1303 break;
d6d367d6
GN		 1304 case 8:
1305 c->dst.val = *(u64 *)c->dst.ptr;
1306 break;
9c9fddd0
GT		 1307 }
1308 c->dst.orig_val = c->dst.val;
1309 break;
a682e354
GN		 1310 case DstDI:
1311 c->dst.type = OP_MEM;
1312 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1313 c->dst.ptr = (unsigned long *)
79168fd1 1314 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1315 c->regs[VCPU_REGS_RDI]);
1316 c->dst.val = 0;
1317 break;
8b4caf66
LV		 1318 }
1319
1320done:
1321 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1322}
1323
9de41573
GN		 1324static int read_emulated(struct x86_emulate_ctxt *ctxt,
1325 struct x86_emulate_ops *ops,
1326 unsigned long addr, void *dest, unsigned size)
1327{
1328 int rc;
1329 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1330 u32 err;
9de41573
GN		 1331
1332 while (size) {
1333 int n = min(size, 8u);
1334 size -= n;
1335 if (mc->pos < mc->end)
1336 goto read_cached;
1337
8fe681e9
GN		 1338 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1339 ctxt->vcpu);
1340 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1341 emulate_pf(ctxt, addr, err);
9de41573
GN		 1342 if (rc != X86EMUL_CONTINUE)
1343 return rc;
1344 mc->end += n;
1345
1346 read_cached:
1347 memcpy(dest, mc->data + mc->pos, n);
1348 mc->pos += n;
1349 dest += n;
1350 addr += n;
1351 }
1352 return X86EMUL_CONTINUE;
1353}
1354
7b262e90
GN		 1355static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1356 struct x86_emulate_ops *ops,
1357 unsigned int size, unsigned short port,
1358 void *dest)
1359{
1360 struct read_cache *rc = &ctxt->decode.io_read;
1361
1362 if (rc->pos == rc->end) { /* refill pio read ahead */
1363 struct decode_cache *c = &ctxt->decode;
1364 unsigned int in_page, n;
1365 unsigned int count = c->rep_prefix ?
1366 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1367 in_page = (ctxt->eflags & EFLG_DF) ?
1368 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1369 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1370 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1371 count);
1372 if (n == 0)
1373 n = 1;
1374 rc->pos = rc->end = 0;
1375 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1376 return 0;
1377 rc->end = n * size;
1378 }
1379
1380 memcpy(dest, rc->data + rc->pos, size);
1381 rc->pos += size;
1382 return 1;
1383}
1384
38ba30ba
GN		 1385static u32 desc_limit_scaled(struct desc_struct *desc)
1386{
1387 u32 limit = get_desc_limit(desc);
1388
1389 return desc->g ? (limit << 12) | 0xfff : limit;
1390}
1391
1392static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1393 struct x86_emulate_ops *ops,
1394 u16 selector, struct desc_ptr *dt)
1395{
1396 if (selector & 1 << 2) {
1397 struct desc_struct desc;
1398 memset (dt, 0, sizeof *dt);
1399 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1400 return;
1401
1402 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1403 dt->address = get_desc_base(&desc);
1404 } else
1405 ops->get_gdt(dt, ctxt->vcpu);
1406}
1407
1408/* allowed just for 8 bytes segments */
1409static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1410 struct x86_emulate_ops *ops,
1411 u16 selector, struct desc_struct *desc)
1412{
1413 struct desc_ptr dt;
1414 u16 index = selector >> 3;
1415 int ret;
1416 u32 err;
1417 ulong addr;
1418
1419 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1420
1421 if (dt.size < index * 8 + 7) {
54b8486f 1422 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1423 return X86EMUL_PROPAGATE_FAULT;
1424 }
1425 addr = dt.address + index * 8;
1426 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1427 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1428 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1429
1430 return ret;
1431}
1432
1433/* allowed just for 8 bytes segments */
1434static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1435 struct x86_emulate_ops *ops,
1436 u16 selector, struct desc_struct *desc)
1437{
1438 struct desc_ptr dt;
1439 u16 index = selector >> 3;
1440 u32 err;
1441 ulong addr;
1442 int ret;
1443
1444 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1445
1446 if (dt.size < index * 8 + 7) {
54b8486f 1447 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1448 return X86EMUL_PROPAGATE_FAULT;
1449 }
1450
1451 addr = dt.address + index * 8;
1452 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1453 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1454 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1455
1456 return ret;
1457}
1458
1459static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1460 struct x86_emulate_ops *ops,
1461 u16 selector, int seg)
1462{
1463 struct desc_struct seg_desc;
1464 u8 dpl, rpl, cpl;
1465 unsigned err_vec = GP_VECTOR;
1466 u32 err_code = 0;
1467 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1468 int ret;
1469
1470 memset(&seg_desc, 0, sizeof seg_desc);
1471
1472 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1473 || ctxt->mode == X86EMUL_MODE_REAL) {
1474 /* set real mode segment descriptor */
1475 set_desc_base(&seg_desc, selector << 4);
1476 set_desc_limit(&seg_desc, 0xffff);
1477 seg_desc.type = 3;
1478 seg_desc.p = 1;
1479 seg_desc.s = 1;
1480 goto load;
1481 }
1482
1483 /* NULL selector is not valid for TR, CS and SS */
1484 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1485 && null_selector)
1486 goto exception;
1487
1488 /* TR should be in GDT only */
1489 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1490 goto exception;
1491
1492 if (null_selector) /* for NULL selector skip all following checks */
1493 goto load;
1494
1495 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1496 if (ret != X86EMUL_CONTINUE)
1497 return ret;
1498
1499 err_code = selector & 0xfffc;
1500 err_vec = GP_VECTOR;
1501
1502 /* can't load system descriptor into segment selecor */
1503 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1504 goto exception;
1505
1506 if (!seg_desc.p) {
1507 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1508 goto exception;
1509 }
1510
1511 rpl = selector & 3;
1512 dpl = seg_desc.dpl;
1513 cpl = ops->cpl(ctxt->vcpu);
1514
1515 switch (seg) {
1516 case VCPU_SREG_SS:
1517 /*
1518 * segment is not a writable data segment or segment
1519 * selector's RPL != CPL or segment selector's RPL != CPL
1520 */
1521 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1522 goto exception;
1523 break;
1524 case VCPU_SREG_CS:
1525 if (!(seg_desc.type & 8))
1526 goto exception;
1527
1528 if (seg_desc.type & 4) {
1529 /* conforming */
1530 if (dpl > cpl)
1531 goto exception;
1532 } else {
1533 /* nonconforming */
1534 if (rpl > cpl || dpl != cpl)
1535 goto exception;
1536 }
1537 /* CS(RPL) <- CPL */
1538 selector = (selector & 0xfffc) | cpl;
1539 break;
1540 case VCPU_SREG_TR:
1541 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1542 goto exception;
1543 break;
1544 case VCPU_SREG_LDTR:
1545 if (seg_desc.s || seg_desc.type != 2)
1546 goto exception;
1547 break;
1548 default: /* DS, ES, FS, or GS */
1549 /*
1550 * segment is not a data or readable code segment or
1551 * ((segment is a data or nonconforming code segment)
1552 * and (both RPL and CPL > DPL))
1553 */
1554 if ((seg_desc.type & 0xa) == 0x8 ||
1555 (((seg_desc.type & 0xc) != 0xc) &&
1556 (rpl > dpl && cpl > dpl)))
1557 goto exception;
1558 break;
1559 }
1560
1561 if (seg_desc.s) {
1562 /* mark segment as accessed */
1563 seg_desc.type |= 1;
1564 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1565 if (ret != X86EMUL_CONTINUE)
1566 return ret;
1567 }
1568load:
1569 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1570 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1571 return X86EMUL_CONTINUE;
1572exception:
54b8486f 1573 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1574 return X86EMUL_PROPAGATE_FAULT;
1575}
1576
c37eda13
WY		 1577static inline int writeback(struct x86_emulate_ctxt *ctxt,
1578 struct x86_emulate_ops *ops)
1579{
1580 int rc;
1581 struct decode_cache *c = &ctxt->decode;
1582 u32 err;
1583
1584 switch (c->dst.type) {
1585 case OP_REG:
1586 /* The 4-byte case *is* correct:
1587 * in 64-bit mode we zero-extend.
1588 */
1589 switch (c->dst.bytes) {
1590 case 1:
1591 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1592 break;
1593 case 2:
1594 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1595 break;
1596 case 4:
1597 *c->dst.ptr = (u32)c->dst.val;
1598 break; /* 64b: zero-ext */
1599 case 8:
1600 *c->dst.ptr = c->dst.val;
1601 break;
1602 }
1603 break;
1604 case OP_MEM:
1605 if (c->lock_prefix)
1606 rc = ops->cmpxchg_emulated(
1607 (unsigned long)c->dst.ptr,
1608 &c->dst.orig_val,
1609 &c->dst.val,
1610 c->dst.bytes,
1611 &err,
1612 ctxt->vcpu);
1613 else
1614 rc = ops->write_emulated(
1615 (unsigned long)c->dst.ptr,
1616 &c->dst.val,
1617 c->dst.bytes,
1618 &err,
1619 ctxt->vcpu);
1620 if (rc == X86EMUL_PROPAGATE_FAULT)
1621 emulate_pf(ctxt,
1622 (unsigned long)c->dst.ptr, err);
1623 if (rc != X86EMUL_CONTINUE)
1624 return rc;
1625 break;
1626 case OP_NONE:
1627 /* no writeback */
1628 break;
1629 default:
1630 break;
1631 }
1632 return X86EMUL_CONTINUE;
1633}
1634
79168fd1
GN		 1635static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1636 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1637{
1638 struct decode_cache *c = &ctxt->decode;
1639
1640 c->dst.type = OP_MEM;
1641 c->dst.bytes = c->op_bytes;
1642 c->dst.val = c->src.val;
7a957275 1643 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1644 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1645 c->regs[VCPU_REGS_RSP]);
1646}
1647
faa5a3ae 1648static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1649 struct x86_emulate_ops *ops,
1650 void *dest, int len)
8cdbd2c9
LV		 1651{
1652 struct decode_cache *c = &ctxt->decode;
1653 int rc;
1654
79168fd1 1655 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1656 c->regs[VCPU_REGS_RSP]),
1657 dest, len);
b60d513c 1658 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1659 return rc;
1660
350f69dc 1661 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1662 return rc;
1663}
8cdbd2c9 1664
d4c6a154
GN		 1665static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1666 struct x86_emulate_ops *ops,
1667 void *dest, int len)
1668{
1669 int rc;
1670 unsigned long val, change_mask;
1671 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1672 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1673
1674 rc = emulate_pop(ctxt, ops, &val, len);
1675 if (rc != X86EMUL_CONTINUE)
1676 return rc;
1677
1678 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1679 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1680
1681 switch(ctxt->mode) {
1682 case X86EMUL_MODE_PROT64:
1683 case X86EMUL_MODE_PROT32:
1684 case X86EMUL_MODE_PROT16:
1685 if (cpl == 0)
1686 change_mask |= EFLG_IOPL;
1687 if (cpl <= iopl)
1688 change_mask |= EFLG_IF;
1689 break;
1690 case X86EMUL_MODE_VM86:
1691 if (iopl < 3) {
54b8486f 1692 emulate_gp(ctxt, 0);
d4c6a154
GN		 1693 return X86EMUL_PROPAGATE_FAULT;
1694 }
1695 change_mask |= EFLG_IF;
1696 break;
1697 default: /* real mode */
1698 change_mask |= (EFLG_IOPL | EFLG_IF);
1699 break;
1700 }
1701
1702 *(unsigned long *)dest =
1703 (ctxt->eflags & ~change_mask) | (val & change_mask);
1704
1705 return rc;
1706}
1707
79168fd1
GN		 1708static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1709 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1710{
1711 struct decode_cache *c = &ctxt->decode;
0934ac9d 1712
79168fd1 1713 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1714
79168fd1 1715 emulate_push(ctxt, ops);
0934ac9d
MG		 1716}
1717
1718static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1719 struct x86_emulate_ops *ops, int seg)
1720{
1721 struct decode_cache *c = &ctxt->decode;
1722 unsigned long selector;
1723 int rc;
1724
1725 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1726 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1727 return rc;
1728
2e873022 1729 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1730 return rc;
1731}
1732
c37eda13 1733static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1734 struct x86_emulate_ops *ops)
abcf14b5
MG		 1735{
1736 struct decode_cache *c = &ctxt->decode;
1737 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1738 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1739 int reg = VCPU_REGS_RAX;
1740
1741 while (reg <= VCPU_REGS_RDI) {
1742 (reg == VCPU_REGS_RSP) ?
1743 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1744
79168fd1 1745 emulate_push(ctxt, ops);
c37eda13
WY		 1746
1747 rc = writeback(ctxt, ops);
1748 if (rc != X86EMUL_CONTINUE)
1749 return rc;
1750
abcf14b5
MG		 1751 ++reg;
1752 }
c37eda13
WY		 1753
1754 /* Disable writeback. */
1755 c->dst.type = OP_NONE;
1756
1757 return rc;
abcf14b5
MG		 1758}
1759
1760static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1761 struct x86_emulate_ops *ops)
1762{
1763 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1764 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1765 int reg = VCPU_REGS_RDI;
1766
1767 while (reg >= VCPU_REGS_RAX) {
1768 if (reg == VCPU_REGS_RSP) {
1769 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1770 c->op_bytes);
1771 --reg;
1772 }
1773
1774 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1775 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1776 break;
1777 --reg;
1778 }
1779 return rc;
1780}
1781
62bd430e
MG		 1782static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1783 struct x86_emulate_ops *ops)
1784{
1785 struct decode_cache *c = &ctxt->decode;
1786 int rc = X86EMUL_CONTINUE;
1787 unsigned long temp_eip = 0;
1788 unsigned long temp_eflags = 0;
1789 unsigned long cs = 0;
1790 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1791 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1792 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1793 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1794
1795 /* TODO: Add stack limit check */
1796
1797 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1798
1799 if (rc != X86EMUL_CONTINUE)
1800 return rc;
1801
1802 if (temp_eip & ~0xffff) {
1803 emulate_gp(ctxt, 0);
1804 return X86EMUL_PROPAGATE_FAULT;
1805 }
1806
1807 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1808
1809 if (rc != X86EMUL_CONTINUE)
1810 return rc;
1811
1812 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1813
1814 if (rc != X86EMUL_CONTINUE)
1815 return rc;
1816
1817 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1818
1819 if (rc != X86EMUL_CONTINUE)
1820 return rc;
1821
1822 c->eip = temp_eip;
1823
1824
1825 if (c->op_bytes == 4)
1826 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1827 else if (c->op_bytes == 2) {
1828 ctxt->eflags &= ~0xffff;
1829 ctxt->eflags |= temp_eflags;
1830 }
1831
1832 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1833 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1834
1835 return rc;
1836}
1837
1838static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1839 struct x86_emulate_ops* ops)
1840{
1841 switch(ctxt->mode) {
1842 case X86EMUL_MODE_REAL:
1843 return emulate_iret_real(ctxt, ops);
1844 case X86EMUL_MODE_VM86:
1845 case X86EMUL_MODE_PROT16:
1846 case X86EMUL_MODE_PROT32:
1847 case X86EMUL_MODE_PROT64:
1848 default:
1849 /* iret from protected mode unimplemented yet */
1850 return X86EMUL_UNHANDLEABLE;
1851 }
1852}
1853
faa5a3ae
AK		 1854static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1855 struct x86_emulate_ops *ops)
1856{
1857 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1858
1b30eaa8 1859 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1860}
1861
05f086f8 1862static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1863{
05f086f8 1864 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1865 switch (c->modrm_reg) {
1866 case 0: /* rol */
05f086f8 1867 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1868 break;
1869 case 1: /* ror */
05f086f8 1870 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1871 break;
1872 case 2: /* rcl */
05f086f8 1873 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1874 break;
1875 case 3: /* rcr */
05f086f8 1876 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1877 break;
1878 case 4: /* sal/shl */
1879 case 6: /* sal/shl */
05f086f8 1880 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1881 break;
1882 case 5: /* shr */
05f086f8 1883 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1884 break;
1885 case 7: /* sar */
05f086f8 1886 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1887 break;
1888 }
1889}
1890
1891static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1892 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1893{
1894 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1895
1896 switch (c->modrm_reg) {
1897 case 0 ... 1: /* test */
05f086f8 1898 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1899 break;
1900 case 2: /* not */
1901 c->dst.val = ~c->dst.val;
1902 break;
1903 case 3: /* neg */
05f086f8 1904 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1905 break;
1906 default:
aca06a83 1907 return 0;
8cdbd2c9 1908 }
aca06a83 1909 return 1;
8cdbd2c9
LV		 1910}
1911
1912static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1913 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1914{
1915 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1916
1917 switch (c->modrm_reg) {
1918 case 0: /* inc */
05f086f8 1919 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1920 break;
1921 case 1: /* dec */
05f086f8 1922 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1923 break;
d19292e4
MG		 1924 case 2: /* call near abs */ {
1925 long int old_eip;
1926 old_eip = c->eip;
1927 c->eip = c->src.val;
1928 c->src.val = old_eip;
79168fd1 1929 emulate_push(ctxt, ops);
d19292e4
MG		 1930 break;
1931 }
8cdbd2c9 1932 case 4: /* jmp abs */
fd60754e 1933 c->eip = c->src.val;
8cdbd2c9
LV		 1934 break;
1935 case 6: /* push */
79168fd1 1936 emulate_push(ctxt, ops);
8cdbd2c9 1937 break;
8cdbd2c9 1938 }
1b30eaa8 1939 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1940}
1941
1942static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1943 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1944{
1945 struct decode_cache *c = &ctxt->decode;
16518d5a 1946 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1947
1948 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1949 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1950 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1951 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1952 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1953 } else {
16518d5a
AK		 1954 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1955 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1956
05f086f8 1957 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1958 }
1b30eaa8 1959 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1960}
1961
a77ab5ea
AK		 1962static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1963 struct x86_emulate_ops *ops)
1964{
1965 struct decode_cache *c = &ctxt->decode;
1966 int rc;
1967 unsigned long cs;
1968
1969 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1970 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1971 return rc;
1972 if (c->op_bytes == 4)
1973 c->eip = (u32)c->eip;
1974 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1975 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1976 return rc;
2e873022 1977 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1978 return rc;
1979}
1980
e66bb2cc
AP		 1981static inline void
1982setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1983 struct x86_emulate_ops *ops, struct desc_struct *cs,
1984 struct desc_struct *ss)
e66bb2cc 1985{
79168fd1
GN		 1986 memset(cs, 0, sizeof(struct desc_struct));
1987 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1988 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1989
1990 cs->l = 0; /* will be adjusted later */
79168fd1 1991 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1992 cs->g = 1; /* 4kb granularity */
79168fd1 1993 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1994 cs->type = 0x0b; /* Read, Execute, Accessed */
1995 cs->s = 1;
1996 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1997 cs->p = 1;
1998 cs->d = 1;
e66bb2cc 1999
79168fd1
GN		 2000 set_desc_base(ss, 0); /* flat segment */
2001 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2002 ss->g = 1; /* 4kb granularity */
2003 ss->s = 1;
2004 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2005 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2006 ss->dpl = 0;
79168fd1 2007 ss->p = 1;
e66bb2cc
AP		 2008}
2009
2010static int
3fb1b5db 2011emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 2012{
2013 struct decode_cache *c = &ctxt->decode;
79168fd1 2014 struct desc_struct cs, ss;
e66bb2cc 2015 u64 msr_data;
79168fd1 2016 u16 cs_sel, ss_sel;
e66bb2cc
AP		 2017
2018 /* syscall is not available in real mode */
2e901c4c
GN		 2019 if (ctxt->mode == X86EMUL_MODE_REAL ||
2020 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2021 emulate_ud(ctxt);
2e901c4c
GN		 2022 return X86EMUL_PROPAGATE_FAULT;
2023 }
e66bb2cc 2024
79168fd1 2025 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 2026
3fb1b5db 2027 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 2028 msr_data >>= 32;
79168fd1
GN		 2029 cs_sel = (u16)(msr_data & 0xfffc);
2030 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 2031
2032 if (is_long_mode(ctxt->vcpu)) {
79168fd1 2033 cs.d = 0;
e66bb2cc
AP		 2034 cs.l = 1;
2035 }
79168fd1
GN		 2036 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2037 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2038 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2039 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2040
2041 c->regs[VCPU_REGS_RCX] = c->eip;
2042 if (is_long_mode(ctxt->vcpu)) {
2043#ifdef CONFIG_X86_64
2044 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2045
3fb1b5db
GN		 2046 ops->get_msr(ctxt->vcpu,
2047 ctxt->mode == X86EMUL_MODE_PROT64 ?
2048 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2049 c->eip = msr_data;
2050
3fb1b5db 2051 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2052 ctxt->eflags &= ~(msr_data | EFLG_RF);
2053#endif
2054 } else {
2055 /* legacy mode */
3fb1b5db 2056 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2057 c->eip = (u32)msr_data;
2058
2059 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2060 }
2061
e54cfa97 2062 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2063}
2064
8c604352 2065static int
3fb1b5db 2066emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2067{
2068 struct decode_cache *c = &ctxt->decode;
79168fd1 2069 struct desc_struct cs, ss;
8c604352 2070 u64 msr_data;
79168fd1 2071 u16 cs_sel, ss_sel;
8c604352 2072
a0044755
GN		 2073 /* inject #GP if in real mode */
2074 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2075 emulate_gp(ctxt, 0);
2e901c4c 2076 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2077 }
2078
2079 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2080 * Therefore, we inject an #UD.
2081 */
2e901c4c 2082 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2083 emulate_ud(ctxt);
2e901c4c
GN		 2084 return X86EMUL_PROPAGATE_FAULT;
2085 }
8c604352 2086
79168fd1 2087 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2088
3fb1b5db 2089 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2090 switch (ctxt->mode) {
2091 case X86EMUL_MODE_PROT32:
2092 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2093 emulate_gp(ctxt, 0);
e54cfa97 2094 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2095 }
2096 break;
2097 case X86EMUL_MODE_PROT64:
2098 if (msr_data == 0x0) {
54b8486f 2099 emulate_gp(ctxt, 0);
e54cfa97 2100 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2101 }
2102 break;
2103 }
2104
2105 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2106 cs_sel = (u16)msr_data;
2107 cs_sel &= ~SELECTOR_RPL_MASK;
2108 ss_sel = cs_sel + 8;
2109 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2110 if (ctxt->mode == X86EMUL_MODE_PROT64
2111 || is_long_mode(ctxt->vcpu)) {
79168fd1 2112 cs.d = 0;
8c604352
AP		 2113 cs.l = 1;
2114 }
2115
79168fd1
GN		 2116 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2117 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2118 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2119 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2120
3fb1b5db 2121 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2122 c->eip = msr_data;
2123
3fb1b5db 2124 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2125 c->regs[VCPU_REGS_RSP] = msr_data;
2126
e54cfa97 2127 return X86EMUL_CONTINUE;
8c604352
AP		 2128}
2129
4668f050 2130static int
3fb1b5db 2131emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2132{
2133 struct decode_cache *c = &ctxt->decode;
79168fd1 2134 struct desc_struct cs, ss;
4668f050
AP		 2135 u64 msr_data;
2136 int usermode;
79168fd1 2137 u16 cs_sel, ss_sel;
4668f050 2138
a0044755
GN		 2139 /* inject #GP if in real mode or Virtual 8086 mode */
2140 if (ctxt->mode == X86EMUL_MODE_REAL ||
2141 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2142 emulate_gp(ctxt, 0);
2e901c4c 2143 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2144 }
2145
79168fd1 2146 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2147
2148 if ((c->rex_prefix & 0x8) != 0x0)
2149 usermode = X86EMUL_MODE_PROT64;
2150 else
2151 usermode = X86EMUL_MODE_PROT32;
2152
2153 cs.dpl = 3;
2154 ss.dpl = 3;
3fb1b5db 2155 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2156 switch (usermode) {
2157 case X86EMUL_MODE_PROT32:
79168fd1 2158 cs_sel = (u16)(msr_data + 16);
4668f050 2159 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2160 emulate_gp(ctxt, 0);
e54cfa97 2161 return X86EMUL_PROPAGATE_FAULT;
4668f050 2162 }
79168fd1 2163 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2164 break;
2165 case X86EMUL_MODE_PROT64:
79168fd1 2166 cs_sel = (u16)(msr_data + 32);
4668f050 2167 if (msr_data == 0x0) {
54b8486f 2168 emulate_gp(ctxt, 0);
e54cfa97 2169 return X86EMUL_PROPAGATE_FAULT;
4668f050 2170 }
79168fd1
GN		 2171 ss_sel = cs_sel + 8;
2172 cs.d = 0;
4668f050
AP		 2173 cs.l = 1;
2174 break;
2175 }
79168fd1
GN		 2176 cs_sel |= SELECTOR_RPL_MASK;
2177 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2178
79168fd1
GN		 2179 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2180 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2181 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2182 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2183
bdb475a3
GN		 2184 c->eip = c->regs[VCPU_REGS_RDX];
2185 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2186
e54cfa97 2187 return X86EMUL_CONTINUE;
4668f050
AP		 2188}
2189
9c537244
GN		 2190static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2191 struct x86_emulate_ops *ops)
f850e2e6
GN		 2192{
2193 int iopl;
2194 if (ctxt->mode == X86EMUL_MODE_REAL)
2195 return false;
2196 if (ctxt->mode == X86EMUL_MODE_VM86)
2197 return true;
2198 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2199 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2200}
2201
2202static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2203 struct x86_emulate_ops *ops,
2204 u16 port, u16 len)
2205{
79168fd1 2206 struct desc_struct tr_seg;
f850e2e6
GN		 2207 int r;
2208 u16 io_bitmap_ptr;
2209 u8 perm, bit_idx = port & 0x7;
2210 unsigned mask = (1 << len) - 1;
2211
79168fd1
GN		 2212 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2213 if (!tr_seg.p)
f850e2e6 2214 return false;
79168fd1 2215 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2216 return false;
79168fd1
GN		 2217 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2218 ctxt->vcpu, NULL);
f850e2e6
GN		 2219 if (r != X86EMUL_CONTINUE)
2220 return false;
79168fd1 2221 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2222 return false;
79168fd1
GN		 2223 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2224 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2225 if (r != X86EMUL_CONTINUE)
2226 return false;
2227 if ((perm >> bit_idx) & mask)
2228 return false;
2229 return true;
2230}
2231
2232static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2233 struct x86_emulate_ops *ops,
2234 u16 port, u16 len)
2235{
9c537244 2236 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2237 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2238 return false;
2239 return true;
2240}
2241
38ba30ba
GN		 2242static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2243 struct x86_emulate_ops *ops,
2244 struct tss_segment_16 *tss)
2245{
2246 struct decode_cache *c = &ctxt->decode;
2247
2248 tss->ip = c->eip;
2249 tss->flag = ctxt->eflags;
2250 tss->ax = c->regs[VCPU_REGS_RAX];
2251 tss->cx = c->regs[VCPU_REGS_RCX];
2252 tss->dx = c->regs[VCPU_REGS_RDX];
2253 tss->bx = c->regs[VCPU_REGS_RBX];
2254 tss->sp = c->regs[VCPU_REGS_RSP];
2255 tss->bp = c->regs[VCPU_REGS_RBP];
2256 tss->si = c->regs[VCPU_REGS_RSI];
2257 tss->di = c->regs[VCPU_REGS_RDI];
2258
2259 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2260 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2261 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2262 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2263 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2264}
2265
2266static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2267 struct x86_emulate_ops *ops,
2268 struct tss_segment_16 *tss)
2269{
2270 struct decode_cache *c = &ctxt->decode;
2271 int ret;
2272
2273 c->eip = tss->ip;
2274 ctxt->eflags = tss->flag | 2;
2275 c->regs[VCPU_REGS_RAX] = tss->ax;
2276 c->regs[VCPU_REGS_RCX] = tss->cx;
2277 c->regs[VCPU_REGS_RDX] = tss->dx;
2278 c->regs[VCPU_REGS_RBX] = tss->bx;
2279 c->regs[VCPU_REGS_RSP] = tss->sp;
2280 c->regs[VCPU_REGS_RBP] = tss->bp;
2281 c->regs[VCPU_REGS_RSI] = tss->si;
2282 c->regs[VCPU_REGS_RDI] = tss->di;
2283
2284 /*
2285 * SDM says that segment selectors are loaded before segment
2286 * descriptors
2287 */
2288 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2289 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2290 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2291 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2292 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2293
2294 /*
2295 * Now load segment descriptors. If fault happenes at this stage
2296 * it is handled in a context of new task
2297 */
2298 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2299 if (ret != X86EMUL_CONTINUE)
2300 return ret;
2301 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2302 if (ret != X86EMUL_CONTINUE)
2303 return ret;
2304 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2308 if (ret != X86EMUL_CONTINUE)
2309 return ret;
2310 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2311 if (ret != X86EMUL_CONTINUE)
2312 return ret;
2313
2314 return X86EMUL_CONTINUE;
2315}
2316
2317static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2318 struct x86_emulate_ops *ops,
2319 u16 tss_selector, u16 old_tss_sel,
2320 ulong old_tss_base, struct desc_struct *new_desc)
2321{
2322 struct tss_segment_16 tss_seg;
2323 int ret;
2324 u32 err, new_tss_base = get_desc_base(new_desc);
2325
2326 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2327 &err);
2328 if (ret == X86EMUL_PROPAGATE_FAULT) {
2329 /* FIXME: need to provide precise fault address */
54b8486f 2330 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2331 return ret;
2332 }
2333
2334 save_state_to_tss16(ctxt, ops, &tss_seg);
2335
2336 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2337 &err);
2338 if (ret == X86EMUL_PROPAGATE_FAULT) {
2339 /* FIXME: need to provide precise fault address */
54b8486f 2340 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2341 return ret;
2342 }
2343
2344 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2345 &err);
2346 if (ret == X86EMUL_PROPAGATE_FAULT) {
2347 /* FIXME: need to provide precise fault address */
54b8486f 2348 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2349 return ret;
2350 }
2351
2352 if (old_tss_sel != 0xffff) {
2353 tss_seg.prev_task_link = old_tss_sel;
2354
2355 ret = ops->write_std(new_tss_base,
2356 &tss_seg.prev_task_link,
2357 sizeof tss_seg.prev_task_link,
2358 ctxt->vcpu, &err);
2359 if (ret == X86EMUL_PROPAGATE_FAULT) {
2360 /* FIXME: need to provide precise fault address */
54b8486f 2361 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2362 return ret;
2363 }
2364 }
2365
2366 return load_state_from_tss16(ctxt, ops, &tss_seg);
2367}
2368
2369static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2370 struct x86_emulate_ops *ops,
2371 struct tss_segment_32 *tss)
2372{
2373 struct decode_cache *c = &ctxt->decode;
2374
2375 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2376 tss->eip = c->eip;
2377 tss->eflags = ctxt->eflags;
2378 tss->eax = c->regs[VCPU_REGS_RAX];
2379 tss->ecx = c->regs[VCPU_REGS_RCX];
2380 tss->edx = c->regs[VCPU_REGS_RDX];
2381 tss->ebx = c->regs[VCPU_REGS_RBX];
2382 tss->esp = c->regs[VCPU_REGS_RSP];
2383 tss->ebp = c->regs[VCPU_REGS_RBP];
2384 tss->esi = c->regs[VCPU_REGS_RSI];
2385 tss->edi = c->regs[VCPU_REGS_RDI];
2386
2387 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2388 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2389 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2390 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2391 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2392 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2393 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2394}
2395
2396static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2397 struct x86_emulate_ops *ops,
2398 struct tss_segment_32 *tss)
2399{
2400 struct decode_cache *c = &ctxt->decode;
2401 int ret;
2402
0f12244f 2403 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2404 emulate_gp(ctxt, 0);
0f12244f
GN		 2405 return X86EMUL_PROPAGATE_FAULT;
2406 }
38ba30ba
GN		 2407 c->eip = tss->eip;
2408 ctxt->eflags = tss->eflags | 2;
2409 c->regs[VCPU_REGS_RAX] = tss->eax;
2410 c->regs[VCPU_REGS_RCX] = tss->ecx;
2411 c->regs[VCPU_REGS_RDX] = tss->edx;
2412 c->regs[VCPU_REGS_RBX] = tss->ebx;
2413 c->regs[VCPU_REGS_RSP] = tss->esp;
2414 c->regs[VCPU_REGS_RBP] = tss->ebp;
2415 c->regs[VCPU_REGS_RSI] = tss->esi;
2416 c->regs[VCPU_REGS_RDI] = tss->edi;
2417
2418 /*
2419 * SDM says that segment selectors are loaded before segment
2420 * descriptors
2421 */
2422 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2423 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2424 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2425 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2426 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2427 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2428 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2429
2430 /*
2431 * Now load segment descriptors. If fault happenes at this stage
2432 * it is handled in a context of new task
2433 */
2434 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2435 if (ret != X86EMUL_CONTINUE)
2436 return ret;
2437 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2438 if (ret != X86EMUL_CONTINUE)
2439 return ret;
2440 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2441 if (ret != X86EMUL_CONTINUE)
2442 return ret;
2443 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2444 if (ret != X86EMUL_CONTINUE)
2445 return ret;
2446 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2447 if (ret != X86EMUL_CONTINUE)
2448 return ret;
2449 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2450 if (ret != X86EMUL_CONTINUE)
2451 return ret;
2452 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
2455
2456 return X86EMUL_CONTINUE;
2457}
2458
2459static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2460 struct x86_emulate_ops *ops,
2461 u16 tss_selector, u16 old_tss_sel,
2462 ulong old_tss_base, struct desc_struct *new_desc)
2463{
2464 struct tss_segment_32 tss_seg;
2465 int ret;
2466 u32 err, new_tss_base = get_desc_base(new_desc);
2467
2468 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2469 &err);
2470 if (ret == X86EMUL_PROPAGATE_FAULT) {
2471 /* FIXME: need to provide precise fault address */
54b8486f 2472 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2473 return ret;
2474 }
2475
2476 save_state_to_tss32(ctxt, ops, &tss_seg);
2477
2478 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2479 &err);
2480 if (ret == X86EMUL_PROPAGATE_FAULT) {
2481 /* FIXME: need to provide precise fault address */
54b8486f 2482 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2483 return ret;
2484 }
2485
2486 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2487 &err);
2488 if (ret == X86EMUL_PROPAGATE_FAULT) {
2489 /* FIXME: need to provide precise fault address */
54b8486f 2490 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2491 return ret;
2492 }
2493
2494 if (old_tss_sel != 0xffff) {
2495 tss_seg.prev_task_link = old_tss_sel;
2496
2497 ret = ops->write_std(new_tss_base,
2498 &tss_seg.prev_task_link,
2499 sizeof tss_seg.prev_task_link,
2500 ctxt->vcpu, &err);
2501 if (ret == X86EMUL_PROPAGATE_FAULT) {
2502 /* FIXME: need to provide precise fault address */
54b8486f 2503 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2504 return ret;
2505 }
2506 }
2507
2508 return load_state_from_tss32(ctxt, ops, &tss_seg);
2509}
2510
2511static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2512 struct x86_emulate_ops *ops,
2513 u16 tss_selector, int reason,
2514 bool has_error_code, u32 error_code)
38ba30ba
GN		 2515{
2516 struct desc_struct curr_tss_desc, next_tss_desc;
2517 int ret;
2518 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2519 ulong old_tss_base =
5951c442 2520 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2521 u32 desc_limit;
38ba30ba
GN		 2522
2523 /* FIXME: old_tss_base == ~0 ? */
2524
2525 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2526 if (ret != X86EMUL_CONTINUE)
2527 return ret;
2528 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2529 if (ret != X86EMUL_CONTINUE)
2530 return ret;
2531
2532 /* FIXME: check that next_tss_desc is tss */
2533
2534 if (reason != TASK_SWITCH_IRET) {
2535 if ((tss_selector & 3) > next_tss_desc.dpl ||
2536 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2537 emulate_gp(ctxt, 0);
38ba30ba
GN		 2538 return X86EMUL_PROPAGATE_FAULT;
2539 }
2540 }
2541
ceffb459
GN		 2542 desc_limit = desc_limit_scaled(&next_tss_desc);
2543 if (!next_tss_desc.p ||
2544 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2545 desc_limit < 0x2b)) {
54b8486f 2546 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2547 return X86EMUL_PROPAGATE_FAULT;
2548 }
2549
2550 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2551 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2552 write_segment_descriptor(ctxt, ops, old_tss_sel,
2553 &curr_tss_desc);
2554 }
2555
2556 if (reason == TASK_SWITCH_IRET)
2557 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2558
2559 /* set back link to prev task only if NT bit is set in eflags
2560 note that old_tss_sel is not used afetr this point */
2561 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2562 old_tss_sel = 0xffff;
2563
2564 if (next_tss_desc.type & 8)
2565 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2566 old_tss_base, &next_tss_desc);
2567 else
2568 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2569 old_tss_base, &next_tss_desc);
0760d448
JK		 2570 if (ret != X86EMUL_CONTINUE)
2571 return ret;
38ba30ba
GN		 2572
2573 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2574 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2575
2576 if (reason != TASK_SWITCH_IRET) {
2577 next_tss_desc.type |= (1 << 1); /* set busy flag */
2578 write_segment_descriptor(ctxt, ops, tss_selector,
2579 &next_tss_desc);
2580 }
2581
2582 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2583 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2584 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2585
e269fb21
JK		 2586 if (has_error_code) {
2587 struct decode_cache *c = &ctxt->decode;
2588
2589 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2590 c->lock_prefix = 0;
2591 c->src.val = (unsigned long) error_code;
79168fd1 2592 emulate_push(ctxt, ops);
e269fb21
JK		 2593 }
2594
38ba30ba
GN		 2595 return ret;
2596}
2597
2598int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2599 struct x86_emulate_ops *ops,
e269fb21
JK		 2600 u16 tss_selector, int reason,
2601 bool has_error_code, u32 error_code)
38ba30ba
GN		 2602{
2603 struct decode_cache *c = &ctxt->decode;
2604 int rc;
2605
38ba30ba 2606 c->eip = ctxt->eip;
e269fb21 2607 c->dst.type = OP_NONE;
38ba30ba 2608
e269fb21
JK		 2609 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2610 has_error_code, error_code);
38ba30ba
GN		 2611
2612 if (rc == X86EMUL_CONTINUE) {
e269fb21 2613 rc = writeback(ctxt, ops);
95c55886
GN		 2614 if (rc == X86EMUL_CONTINUE)
2615 ctxt->eip = c->eip;
38ba30ba
GN		 2616 }
2617
19d04437 2618 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2619}
2620
a682e354 2621static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2622 int reg, struct operand *op)
a682e354
GN		 2623{
2624 struct decode_cache *c = &ctxt->decode;
2625 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2626
d9271123
GN		 2627 register_address_increment(c, &c->regs[reg], df * op->bytes);
2628 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2629}
2630
8b4caf66 2631int
1be3aa47 2632x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2633{
8b4caf66 2634 u64 msr_data;
8b4caf66 2635 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2636 int rc = X86EMUL_CONTINUE;
5cd21917 2637 int saved_dst_type = c->dst.type;
8b4caf66 2638
9de41573 2639 ctxt->decode.mem_read.pos = 0;
310b5d30 2640
1161624f 2641 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2642 emulate_ud(ctxt);
1161624f
GN		 2643 goto done;
2644 }
2645
d380a5e4 2646 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2647 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2648 emulate_ud(ctxt);
d380a5e4
GN		 2649 goto done;
2650 }
2651
e92805ac 2652 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2653 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2654 emulate_gp(ctxt, 0);
e92805ac
GN		 2655 goto done;
2656 }
2657
b9fa9d6b 2658 if (c->rep_prefix && (c->d & String)) {
5cd21917 2659 ctxt->restart = true;
b9fa9d6b 2660 /* All REP prefixes have the same first termination condition */
c73e197b 2661 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2662 string_done:
2663 ctxt->restart = false;
95c55886 2664 ctxt->eip = c->eip;
b9fa9d6b
AK		 2665 goto done;
2666 }
2667 /* The second termination condition only applies for REPE
2668 * and REPNE. Test if the repeat string operation prefix is
2669 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2670 * corresponding termination condition according to:
2671 * - if REPE/REPZ and ZF = 0 then done
2672 * - if REPNE/REPNZ and ZF = 1 then done
2673 */
2674 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2675 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2676 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2677 ((ctxt->eflags & EFLG_ZF) == 0))
2678 goto string_done;
b9fa9d6b 2679 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2680 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2681 goto string_done;
b9fa9d6b 2682 }
063db061 2683 c->eip = ctxt->eip;
b9fa9d6b
AK		 2684 }
2685
8b4caf66 2686 if (c->src.type == OP_MEM) {
9de41573 2687 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2688 c->src.valptr, c->src.bytes);
b60d513c 2689 if (rc != X86EMUL_CONTINUE)
8b4caf66 2690 goto done;
16518d5a 2691 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2692 }
2693
e35b7b9c 2694 if (c->src2.type == OP_MEM) {
9de41573
GN		 2695 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2696 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2697 if (rc != X86EMUL_CONTINUE)
2698 goto done;
2699 }
2700
8b4caf66
LV		 2701 if ((c->d & DstMask) == ImplicitOps)
2702 goto special_insn;
2703
2704
69f55cb1
GN		 2705 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2706 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2707 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2708 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2709 if (rc != X86EMUL_CONTINUE)
2710 goto done;
038e51de 2711 }
e4e03ded 2712 c->dst.orig_val = c->dst.val;
038e51de 2713
018a98db
AK		 2714special_insn:
2715
e4e03ded 2716 if (c->twobyte)
6aa8b732
AK		 2717 goto twobyte_insn;
2718
e4e03ded 2719 switch (c->b) {
6aa8b732
AK		 2720 case 0x00 ... 0x05:
2721 add: /* add */
05f086f8 2722 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2723 break;
0934ac9d 2724 case 0x06: /* push es */
79168fd1 2725 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2726 break;
2727 case 0x07: /* pop es */
0934ac9d 2728 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2729 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2730 goto done;
2731 break;
6aa8b732
AK		 2732 case 0x08 ... 0x0d:
2733 or: /* or */
05f086f8 2734 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2735 break;
0934ac9d 2736 case 0x0e: /* push cs */
79168fd1 2737 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2738 break;
6aa8b732
AK		 2739 case 0x10 ... 0x15:
2740 adc: /* adc */
05f086f8 2741 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2742 break;
0934ac9d 2743 case 0x16: /* push ss */
79168fd1 2744 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2745 break;
2746 case 0x17: /* pop ss */
0934ac9d 2747 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2748 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2749 goto done;
2750 break;
6aa8b732
AK		 2751 case 0x18 ... 0x1d:
2752 sbb: /* sbb */
05f086f8 2753 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2754 break;
0934ac9d 2755 case 0x1e: /* push ds */
79168fd1 2756 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2757 break;
2758 case 0x1f: /* pop ds */
0934ac9d 2759 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2760 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2761 goto done;
2762 break;
aa3a816b 2763 case 0x20 ... 0x25:
6aa8b732 2764 and: /* and */
05f086f8 2765 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2766 break;
2767 case 0x28 ... 0x2d:
2768 sub: /* sub */
05f086f8 2769 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2770 break;
2771 case 0x30 ... 0x35:
2772 xor: /* xor */
05f086f8 2773 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2774 break;
2775 case 0x38 ... 0x3d:
2776 cmp: /* cmp */
05f086f8 2777 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2778 break;
33615aa9
AK		 2779 case 0x40 ... 0x47: /* inc r16/r32 */
2780 emulate_1op("inc", c->dst, ctxt->eflags);
2781 break;
2782 case 0x48 ... 0x4f: /* dec r16/r32 */
2783 emulate_1op("dec", c->dst, ctxt->eflags);
2784 break;
2785 case 0x50 ... 0x57: /* push reg */
79168fd1 2786 emulate_push(ctxt, ops);
33615aa9
AK		 2787 break;
2788 case 0x58 ... 0x5f: /* pop reg */
2789 pop_instruction:
350f69dc 2790 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2791 if (rc != X86EMUL_CONTINUE)
33615aa9 2792 goto done;
33615aa9 2793 break;
abcf14b5 2794 case 0x60: /* pusha */
c37eda13
WY		 2795 rc = emulate_pusha(ctxt, ops);
2796 if (rc != X86EMUL_CONTINUE)
2797 goto done;
abcf14b5
MG		 2798 break;
2799 case 0x61: /* popa */
2800 rc = emulate_popa(ctxt, ops);
1b30eaa8 2801 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2802 goto done;
2803 break;
6aa8b732 2804 case 0x63: /* movsxd */
8b4caf66 2805 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2806 goto cannot_emulate;
e4e03ded 2807 c->dst.val = (s32) c->src.val;
6aa8b732 2808 break;
91ed7a0e 2809 case 0x68: /* push imm */
018a98db 2810 case 0x6a: /* push imm8 */
79168fd1 2811 emulate_push(ctxt, ops);
018a98db
AK		 2812 break;
2813 case 0x6c: /* insb */
2814 case 0x6d: /* insw/insd */
7972995b 2815 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2816 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2817 c->dst.bytes)) {
54b8486f 2818 emulate_gp(ctxt, 0);
f850e2e6
GN		 2819 goto done;
2820 }
7b262e90
GN		 2821 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2822 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2823 goto done; /* IO is needed, skip writeback */
2824 break;
018a98db
AK		 2825 case 0x6e: /* outsb */
2826 case 0x6f: /* outsw/outsd */
7972995b 2827 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2828 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2829 c->src.bytes)) {
54b8486f 2830 emulate_gp(ctxt, 0);
f850e2e6
GN		 2831 goto done;
2832 }
7972995b
GN		 2833 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2834 &c->src.val, 1, ctxt->vcpu);
2835
2836 c->dst.type = OP_NONE; /* nothing to writeback */
2837 break;
b2833e3c 2838 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2839 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2840 jmp_rel(c, c->src.val);
018a98db 2841 break;
6aa8b732 2842 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2843 switch (c->modrm_reg) {
6aa8b732
AK		 2844 case 0:
2845 goto add;
2846 case 1:
2847 goto or;
2848 case 2:
2849 goto adc;
2850 case 3:
2851 goto sbb;
2852 case 4:
2853 goto and;
2854 case 5:
2855 goto sub;
2856 case 6:
2857 goto xor;
2858 case 7:
2859 goto cmp;
2860 }
2861 break;
2862 case 0x84 ... 0x85:
dfb507c4 2863 test:
05f086f8 2864 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2865 break;
2866 case 0x86 ... 0x87: /* xchg */
b13354f8 2867 xchg:
6aa8b732 2868 /* Write back the register source. */
e4e03ded 2869 switch (c->dst.bytes) {
6aa8b732 2870 case 1:
e4e03ded 2871 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2872 break;
2873 case 2:
e4e03ded 2874 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2875 break;
2876 case 4:
e4e03ded 2877 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2878 break; /* 64b reg: zero-extend */
2879 case 8:
e4e03ded 2880 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2881 break;
2882 }
2883 /*
2884 * Write back the memory destination with implicit LOCK
2885 * prefix.
2886 */
e4e03ded
LV		 2887 c->dst.val = c->src.val;
2888 c->lock_prefix = 1;
6aa8b732 2889 break;
6aa8b732 2890 case 0x88 ... 0x8b: /* mov */
7de75248 2891 goto mov;
79168fd1
GN		 2892 case 0x8c: /* mov r/m, sreg */
2893 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2894 emulate_ud(ctxt);
5e3ae6c5 2895 goto done;
38d5bc6d 2896 }
79168fd1 2897 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2898 break;
7e0b54b1 2899 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2900 c->dst.val = c->modrm_ea;
7e0b54b1 2901 break;
4257198a
GT		 2902 case 0x8e: { /* mov seg, r/m16 */
2903 uint16_t sel;
4257198a
GT		 2904
2905 sel = c->src.val;
8b9f4414 2906
c697518a
GN		 2907 if (c->modrm_reg == VCPU_SREG_CS ||
2908 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2909 emulate_ud(ctxt);
8b9f4414
GN		 2910 goto done;
2911 }
2912
310b5d30 2913 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2914 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2915
2e873022 2916 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2917
2918 c->dst.type = OP_NONE; /* Disable writeback. */
2919 break;
2920 }
6aa8b732 2921 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2922 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2923 if (rc != X86EMUL_CONTINUE)
6aa8b732 2924 goto done;
6aa8b732 2925 break;
b13354f8 2926 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2927 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2928 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2929 break;
2930 }
2931 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2932 c->src.type = OP_REG;
2933 c->src.bytes = c->op_bytes;
b13354f8
MG		 2934 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2935 c->src.val = *(c->src.ptr);
2936 goto xchg;
fd2a7608 2937 case 0x9c: /* pushf */
05f086f8 2938 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2939 emulate_push(ctxt, ops);
8cdbd2c9 2940 break;
535eabcf 2941 case 0x9d: /* popf */
2b48cc75 2942 c->dst.type = OP_REG;
05f086f8 2943 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2944 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2945 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2946 if (rc != X86EMUL_CONTINUE)
2947 goto done;
2948 break;
5d55f299 2949 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2950 case 0xa4 ... 0xa5: /* movs */
a682e354 2951 goto mov;
6aa8b732 2952 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2953 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2954 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2955 goto cmp;
dfb507c4
MG		 2956 case 0xa8 ... 0xa9: /* test ax, imm */
2957 goto test;
6aa8b732 2958 case 0xaa ... 0xab: /* stos */
e4e03ded 2959 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2960 break;
2961 case 0xac ... 0xad: /* lods */
a682e354 2962 goto mov;
6aa8b732
AK		 2963 case 0xae ... 0xaf: /* scas */
2964 DPRINTF("Urk! I don't handle SCAS.\n");
2965 goto cannot_emulate;
a5e2e82b 2966 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2967 goto mov;
018a98db
AK		 2968 case 0xc0 ... 0xc1:
2969 emulate_grp2(ctxt);
2970 break;
111de5d6 2971 case 0xc3: /* ret */
cf5de4f8 2972 c->dst.type = OP_REG;
111de5d6 2973 c->dst.ptr = &c->eip;
cf5de4f8 2974 c->dst.bytes = c->op_bytes;
111de5d6 2975 goto pop_instruction;
018a98db
AK		 2976 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2977 mov:
2978 c->dst.val = c->src.val;
2979 break;
a77ab5ea
AK		 2980 case 0xcb: /* ret far */
2981 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2982 if (rc != X86EMUL_CONTINUE)
2983 goto done;
2984 break;
2985 case 0xcf: /* iret */
2986 rc = emulate_iret(ctxt, ops);
2987
1b30eaa8 2988 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2989 goto done;
2990 break;
018a98db
AK		 2991 case 0xd0 ... 0xd1: /* Grp2 */
2992 c->src.val = 1;
2993 emulate_grp2(ctxt);
2994 break;
2995 case 0xd2 ... 0xd3: /* Grp2 */
2996 c->src.val = c->regs[VCPU_REGS_RCX];
2997 emulate_grp2(ctxt);
2998 break;
a6a3034c
MG		 2999 case 0xe4: /* inb */
3000 case 0xe5: /* in */
cf8f70bf 3001 goto do_io_in;
a6a3034c
MG		 3002 case 0xe6: /* outb */
3003 case 0xe7: /* out */
cf8f70bf 3004 goto do_io_out;
1a52e051 3005 case 0xe8: /* call (near) */ {
d53c4777 3006 long int rel = c->src.val;
e4e03ded 3007 c->src.val = (unsigned long) c->eip;
7a957275 3008 jmp_rel(c, rel);
79168fd1 3009 emulate_push(ctxt, ops);
8cdbd2c9 3010 break;
1a52e051
NK		 3011 }
3012 case 0xe9: /* jmp rel */
954cd36f 3013 goto jmp;
414e6277
GN		 3014 case 0xea: { /* jmp far */
3015 unsigned short sel;
ea79849d 3016 jump_far:
414e6277
GN		 3017 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3018
3019 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3020 goto done;
954cd36f 3021
414e6277
GN		 3022 c->eip = 0;
3023 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3024 break;
414e6277 3025 }
954cd36f
GT		 3026 case 0xeb:
3027 jmp: /* jmp rel short */
7a957275 3028 jmp_rel(c, c->src.val);
a01af5ec 3029 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3030 break;
a6a3034c
MG		 3031 case 0xec: /* in al,dx */
3032 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3033 c->src.val = c->regs[VCPU_REGS_RDX];
3034 do_io_in:
3035 c->dst.bytes = min(c->dst.bytes, 4u);
3036 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3037 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3038 goto done;
3039 }
7b262e90
GN		 3040 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3041 &c->dst.val))
cf8f70bf
GN		 3042 goto done; /* IO is needed */
3043 break;
ce7a0ad3
WY		 3044 case 0xee: /* out dx,al */
3045 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3046 c->src.val = c->regs[VCPU_REGS_RDX];
3047 do_io_out:
3048 c->dst.bytes = min(c->dst.bytes, 4u);
3049 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3050 emulate_gp(ctxt, 0);
f850e2e6
GN		 3051 goto done;
3052 }
cf8f70bf
GN		 3053 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3054 ctxt->vcpu);
3055 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3056 break;
111de5d6 3057 case 0xf4: /* hlt */
ad312c7c 3058 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3059 break;
111de5d6
AK		 3060 case 0xf5: /* cmc */
3061 /* complement carry flag from eflags reg */
3062 ctxt->eflags ^= EFLG_CF;
3063 c->dst.type = OP_NONE; /* Disable writeback. */
3064 break;
018a98db 3065 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3066 if (!emulate_grp3(ctxt, ops))
3067 goto cannot_emulate;
018a98db 3068 break;
111de5d6
AK		 3069 case 0xf8: /* clc */
3070 ctxt->eflags &= ~EFLG_CF;
3071 c->dst.type = OP_NONE; /* Disable writeback. */
3072 break;
3073 case 0xfa: /* cli */
07cbc6c1 3074 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3075 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3076 goto done;
3077 } else {
f850e2e6
GN		 3078 ctxt->eflags &= ~X86_EFLAGS_IF;
3079 c->dst.type = OP_NONE; /* Disable writeback. */
3080 }
111de5d6
AK		 3081 break;
3082 case 0xfb: /* sti */
07cbc6c1 3083 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3084 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3085 goto done;
3086 } else {
95cb2295 3087 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3088 ctxt->eflags |= X86_EFLAGS_IF;
3089 c->dst.type = OP_NONE; /* Disable writeback. */
3090 }
111de5d6 3091 break;
fb4616f4
MG		 3092 case 0xfc: /* cld */
3093 ctxt->eflags &= ~EFLG_DF;
3094 c->dst.type = OP_NONE; /* Disable writeback. */
3095 break;
3096 case 0xfd: /* std */
3097 ctxt->eflags |= EFLG_DF;
3098 c->dst.type = OP_NONE; /* Disable writeback. */
3099 break;
ea79849d
GN		 3100 case 0xfe: /* Grp4 */
3101 grp45:
018a98db 3102 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3103 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3104 goto done;
3105 break;
ea79849d
GN		 3106 case 0xff: /* Grp5 */
3107 if (c->modrm_reg == 5)
3108 goto jump_far;
3109 goto grp45;
91269b8f
AK		 3110 default:
3111 goto cannot_emulate;
6aa8b732 3112 }
018a98db
AK		 3113
3114writeback:
3115 rc = writeback(ctxt, ops);
1b30eaa8 3116 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3117 goto done;
3118
5cd21917
GN		 3119 /*
3120 * restore dst type in case the decoding will be reused
3121 * (happens for string instruction )
3122 */
3123 c->dst.type = saved_dst_type;
3124
a682e354 3125 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3126 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3127 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3128
3129 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3130 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3131 &c->dst);
d9271123 3132
5cd21917 3133 if (c->rep_prefix && (c->d & String)) {
7b262e90 3134 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3135 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3136 /*
3137 * Re-enter guest when pio read ahead buffer is empty or,
3138 * if it is not used, after each 1024 iteration.
3139 */
3140 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3141 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3142 ctxt->restart = false;
3143 }
9de41573
GN		 3144 /*
3145 * reset read cache here in case string instruction is restared
3146 * without decoding
3147 */
3148 ctxt->decode.mem_read.end = 0;
95c55886 3149 ctxt->eip = c->eip;
018a98db
AK		 3150
3151done:
cb404fe0 3152 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3153
3154twobyte_insn:
e4e03ded 3155 switch (c->b) {
6aa8b732 3156 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3157 switch (c->modrm_reg) {
6aa8b732
AK		 3158 u16 size;
3159 unsigned long address;
3160
aca7f966 3161 case 0: /* vmcall */
e4e03ded 3162 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3163 goto cannot_emulate;
3164
7aa81cc0 3165 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3166 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3167 goto done;
3168
33e3885d 3169 /* Let the processor re-execute the fixed hypercall */
063db061 3170 c->eip = ctxt->eip;
16286d08
AK		 3171 /* Disable writeback. */
3172 c->dst.type = OP_NONE;
aca7f966 3173 break;
6aa8b732 3174 case 2: /* lgdt */
e4e03ded
LV		 3175 rc = read_descriptor(ctxt, ops, c->src.ptr,
3176 &size, &address, c->op_bytes);
1b30eaa8 3177 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3178 goto done;
3179 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3180 /* Disable writeback. */
3181 c->dst.type = OP_NONE;
6aa8b732 3182 break;
aca7f966 3183 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3184 if (c->modrm_mod == 3) {
3185 switch (c->modrm_rm) {
3186 case 1:
3187 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3188 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3189 goto done;
3190 break;
3191 default:
3192 goto cannot_emulate;
3193 }
aca7f966 3194 } else {
e4e03ded 3195 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3196 &size, &address,
e4e03ded 3197 c->op_bytes);
1b30eaa8 3198 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3199 goto done;
3200 realmode_lidt(ctxt->vcpu, size, address);
3201 }
16286d08
AK		 3202 /* Disable writeback. */
3203 c->dst.type = OP_NONE;
6aa8b732
AK		 3204 break;
3205 case 4: /* smsw */
16286d08 3206 c->dst.bytes = 2;
52a46617 3207 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3208 break;
3209 case 6: /* lmsw */
93a152be
GN		 3210 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3211 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3212 c->dst.type = OP_NONE;
6aa8b732 3213 break;
6e1e5ffe 3214 case 5: /* not defined */
54b8486f 3215 emulate_ud(ctxt);
6e1e5ffe 3216 goto done;
6aa8b732 3217 case 7: /* invlpg*/
69f55cb1 3218 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3219 /* Disable writeback. */
3220 c->dst.type = OP_NONE;
6aa8b732
AK		 3221 break;
3222 default:
3223 goto cannot_emulate;
3224 }
3225 break;
e99f0507 3226 case 0x05: /* syscall */
3fb1b5db 3227 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3228 if (rc != X86EMUL_CONTINUE)
3229 goto done;
e66bb2cc
AP		 3230 else
3231 goto writeback;
e99f0507 3232 break;
018a98db
AK		 3233 case 0x06:
3234 emulate_clts(ctxt->vcpu);
3235 c->dst.type = OP_NONE;
3236 break;
018a98db 3237 case 0x09: /* wbinvd */
f5f48ee1
SY		 3238 kvm_emulate_wbinvd(ctxt->vcpu);
3239 c->dst.type = OP_NONE;
3240 break;
3241 case 0x08: /* invd */
018a98db
AK		 3242 case 0x0d: /* GrpP (prefetch) */
3243 case 0x18: /* Grp16 (prefetch/nop) */
3244 c->dst.type = OP_NONE;
3245 break;
3246 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3247 switch (c->modrm_reg) {
3248 case 1:
3249 case 5 ... 7:
3250 case 9 ... 15:
54b8486f 3251 emulate_ud(ctxt);
6aebfa6e
GN		 3252 goto done;
3253 }
52a46617 3254 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3255 c->dst.type = OP_NONE; /* no writeback */
3256 break;
6aa8b732 3257 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3258 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3259 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3260 emulate_ud(ctxt);
1e470be5
GN		 3261 goto done;
3262 }
35aa5375 3263 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3264 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3265 break;
018a98db 3266 case 0x22: /* mov reg, cr */
0f12244f 3267 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3268 emulate_gp(ctxt, 0);
0f12244f
GN		 3269 goto done;
3270 }
018a98db
AK		 3271 c->dst.type = OP_NONE;
3272 break;
6aa8b732 3273 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3274 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3275 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3276 emulate_ud(ctxt);
1e470be5
GN		 3277 goto done;
3278 }
35aa5375 3279
338dbc97
GN		 3280 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3281 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3282 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3283 /* #UD condition is already handled by the code above */
54b8486f 3284 emulate_gp(ctxt, 0);
338dbc97
GN		 3285 goto done;
3286 }
3287
a01af5ec 3288 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3289 break;
018a98db
AK		 3290 case 0x30:
3291 /* wrmsr */
3292 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3293 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3294 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3295 emulate_gp(ctxt, 0);
fd525365 3296 goto done;
018a98db
AK		 3297 }
3298 rc = X86EMUL_CONTINUE;
3299 c->dst.type = OP_NONE;
3300 break;
3301 case 0x32:
3302 /* rdmsr */
3fb1b5db 3303 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3304 emulate_gp(ctxt, 0);
fd525365 3305 goto done;
018a98db
AK		 3306 } else {
3307 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3308 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3309 }
3310 rc = X86EMUL_CONTINUE;
3311 c->dst.type = OP_NONE;
3312 break;
e99f0507 3313 case 0x34: /* sysenter */
3fb1b5db 3314 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3315 if (rc != X86EMUL_CONTINUE)
3316 goto done;
8c604352
AP		 3317 else
3318 goto writeback;
e99f0507
AP		 3319 break;
3320 case 0x35: /* sysexit */
3fb1b5db 3321 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3322 if (rc != X86EMUL_CONTINUE)
3323 goto done;
4668f050
AP		 3324 else
3325 goto writeback;
e99f0507 3326 break;
6aa8b732 3327 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3328 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3329 if (!test_cc(c->b, ctxt->eflags))
3330 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3331 break;
b2833e3c 3332 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3333 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3334 jmp_rel(c, c->src.val);
018a98db
AK		 3335 c->dst.type = OP_NONE;
3336 break;
0934ac9d 3337 case 0xa0: /* push fs */
79168fd1 3338 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3339 break;
3340 case 0xa1: /* pop fs */
3341 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3342 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3343 goto done;
3344 break;
7de75248
NK		 3345 case 0xa3:
3346 bt: /* bt */
e4f8e039 3347 c->dst.type = OP_NONE;
e4e03ded
LV		 3348 /* only subword offset */
3349 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3350 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3351 break;
9bf8ea42
GT		 3352 case 0xa4: /* shld imm8, r, r/m */
3353 case 0xa5: /* shld cl, r, r/m */
3354 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3355 break;
0934ac9d 3356 case 0xa8: /* push gs */
79168fd1 3357 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3358 break;
3359 case 0xa9: /* pop gs */
3360 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3361 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3362 goto done;
3363 break;
7de75248
NK		 3364 case 0xab:
3365 bts: /* bts */
e4e03ded
LV		 3366 /* only subword offset */
3367 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3368 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3369 break;
9bf8ea42
GT		 3370 case 0xac: /* shrd imm8, r, r/m */
3371 case 0xad: /* shrd cl, r, r/m */
3372 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3373 break;
2a7c5b8b
GC		 3374 case 0xae: /* clflush */
3375 break;
6aa8b732
AK		 3376 case 0xb0 ... 0xb1: /* cmpxchg */
3377 /*
3378 * Save real source value, then compare EAX against
3379 * destination.
3380 */
e4e03ded
LV		 3381 c->src.orig_val = c->src.val;
3382 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3383 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3384 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3385 /* Success: write back to memory. */
e4e03ded 3386 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3387 } else {
3388 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3389 c->dst.type = OP_REG;
3390 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3391 }
3392 break;
6aa8b732
AK		 3393 case 0xb3:
3394 btr: /* btr */
e4e03ded
LV		 3395 /* only subword offset */
3396 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3397 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3398 break;
6aa8b732 3399 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3400 c->dst.bytes = c->op_bytes;
3401 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3402 : (u16) c->src.val;
6aa8b732 3403 break;
6aa8b732 3404 case 0xba: /* Grp8 */
e4e03ded 3405 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3406 case 0:
3407 goto bt;
3408 case 1:
3409 goto bts;
3410 case 2:
3411 goto btr;
3412 case 3:
3413 goto btc;
3414 }
3415 break;
7de75248
NK		 3416 case 0xbb:
3417 btc: /* btc */
e4e03ded
LV		 3418 /* only subword offset */
3419 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3420 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3421 break;
6aa8b732 3422 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3423 c->dst.bytes = c->op_bytes;
3424 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3425 (s16) c->src.val;
6aa8b732 3426 break;
a012e65a 3427 case 0xc3: /* movnti */
e4e03ded
LV		 3428 c->dst.bytes = c->op_bytes;
3429 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3430 (u64) c->src.val;
a012e65a 3431 break;
6aa8b732 3432 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3433 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3434 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3435 goto done;
3436 break;
91269b8f
AK		 3437 default:
3438 goto cannot_emulate;
6aa8b732
AK		 3439 }
3440 goto writeback;
3441
3442cannot_emulate:
e4e03ded 3443 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3444 return -1;
3445}
Linux kernel - Deliverables
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