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KVM: x86 emulator: convert group 1 to new style
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
ea9ef04e
AK		 98#define X2(x) x, x
99#define X3(x) X2(x), x
83babbca 100#define X4(x) X2(x), X2(x)
ea9ef04e 101#define X5(x) X4(x), x
83babbca
AK		 102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
5b92b5fa 108 NoGrp, Group1A, Group3, Group4, Group5, Group7, Group8, Group9,
43bb19cd
AK		 109};
110
d65b1dee
AK		 111struct opcode {
112 u32 flags;
120df890
AK		 113 union {
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
fd853310
AK		 124#define D(_y) { .flags = (_y) }
125#define N D(0)
120df890
AK		 126#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
127#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
fd853310 128
5b92b5fa
AK		 129static struct opcode group1[] = {
130 X7(D(Lock)), N
131};
132
42a1c520 133static struct opcode group_table[] = {
42a1c520
AK		 134 [Group1A*8] =
135 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
136 [Group3*8] =
137 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
138 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
139 X4(D(Undefined)),
140 [Group4*8] =
141 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
142 N, N, N, N, N, N,
143 [Group5*8] =
144 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
145 D(SrcMem | ModRM | Stack), N,
146 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
147 D(SrcMem | ModRM | Stack), N,
148 [Group7*8] =
149 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
150 D(SrcNone | ModRM | DstMem | Mov), N,
151 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
152 [Group8*8] =
153 N, N, N, N,
154 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
155 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
156 [Group9*8] =
157 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
158};
159
160static struct opcode group2_table[] = {
161 [Group7*8] =
162 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
163 D(SrcNone | ModRM | DstMem | Mov), N,
164 D(SrcMem16 | ModRM | Mov | Priv), N,
165 [Group9*8] =
166 N, N, N, N, N, N, N, N,
167};
168
d65b1dee 169static struct opcode opcode_table[256] = {
6aa8b732 170 /* 0x00 - 0x07 */
fd853310
AK		 171 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
172 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
173 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
174 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 175 /* 0x08 - 0x0F */
fd853310
AK		 176 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
177 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
178 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
179 D(ImplicitOps | Stack | No64), N,
6aa8b732 180 /* 0x10 - 0x17 */
fd853310
AK		 181 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
182 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
183 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
184 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 185 /* 0x18 - 0x1F */
fd853310
AK		 186 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
187 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
188 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
189 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 190 /* 0x20 - 0x27 */
fd853310
AK		 191 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
192 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
193 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 194 /* 0x28 - 0x2F */
fd853310
AK		 195 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
196 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
197 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 198 /* 0x30 - 0x37 */
fd853310
AK		 199 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
200 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
201 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 202 /* 0x38 - 0x3F */
fd853310
AK		 203 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
204 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
205 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
206 N, N,
749358a6 207 /* 0x40 - 0x4F */
fd853310 208 X16(D(DstReg)),
7f0aaee0 209 /* 0x50 - 0x57 */
fd853310 210 X8(D(SrcReg | Stack)),
7f0aaee0 211 /* 0x58 - 0x5F */
fd853310 212 X8(D(DstReg | Stack)),
7d316911 213 /* 0x60 - 0x67 */
fd853310
AK		 214 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
215 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
216 N, N, N, N,
7d316911 217 /* 0x68 - 0x6F */
fd853310
AK		 218 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
219 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
220 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 221 /* 0x70 - 0x7F */
fd853310 222 X16(D(SrcImmByte)),
6aa8b732 223 /* 0x80 - 0x87 */
5b92b5fa
AK		 224 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
225 G(DstMem | SrcImm | ModRM | Group, group1),
226 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
227 G(DstMem | SrcImmByte | ModRM | Group, group1),
fd853310
AK		 228 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
229 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 230 /* 0x88 - 0x8F */
fd853310
AK		 231 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
232 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
233 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
234 D(ImplicitOps | SrcMem16 | ModRM), D(Group | Group1A),
b13354f8 235 /* 0x90 - 0x97 */
fd853310 236 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 237 /* 0x98 - 0x9F */
fd853310
AK		 238 N, N, D(SrcImmFAddr | No64), N,
239 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 240 /* 0xA0 - 0xA7 */
fd853310
AK		 241 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
242 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
243 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
244 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 245 /* 0xA8 - 0xAF */
fd853310
AK		 246 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
247 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
248 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 249 /* 0xB0 - 0xB7 */
fd853310 250 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 251 /* 0xB8 - 0xBF */
fd853310 252 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 253 /* 0xC0 - 0xC7 */
fd853310
AK		 254 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
255 N, D(ImplicitOps | Stack), N, N,
256 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 257 /* 0xC8 - 0xCF */
fd853310
AK		 258 N, N, N, D(ImplicitOps | Stack),
259 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 260 /* 0xD0 - 0xD7 */
fd853310
AK		 261 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
262 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
263 N, N, N, N,
6aa8b732 264 /* 0xD8 - 0xDF */
fd853310 265 N, N, N, N, N, N, N, N,
098c937b 266 /* 0xE0 - 0xE7 */
fd853310
AK		 267 N, N, N, N,
268 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
269 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 270 /* 0xE8 - 0xEF */
fd853310
AK		 271 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
272 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
273 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
274 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 275 /* 0xF0 - 0xF7 */
fd853310
AK		 276 N, N, N, N,
277 D(ImplicitOps | Priv), D(ImplicitOps), D(ByteOp | Group | Group3), D(Group | Group3),
6aa8b732 278 /* 0xF8 - 0xFF */
fd853310
AK		 279 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
280 D(ImplicitOps), D(ImplicitOps), D(Group | Group4), D(Group | Group5),
6aa8b732
AK		 281};
282
d65b1dee 283static struct opcode twobyte_table[256] = {
6aa8b732 284 /* 0x00 - 0x0F */
fd853310
AK		 285 N, D(Group | GroupDual | Group7), N, N,
286 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
287 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
288 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 289 /* 0x10 - 0x1F */
fd853310 290 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 291 /* 0x20 - 0x2F */
fd853310
AK		 292 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
293 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
294 N, N, N, N,
295 N, N, N, N, N, N, N, N,
6aa8b732 296 /* 0x30 - 0x3F */
fd853310
AK		 297 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
298 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
299 N, N, N, N, N, N, N, N,
be8eacdd 300 /* 0x40 - 0x4F */
fd853310 301 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 302 /* 0x50 - 0x5F */
fd853310 303 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 304 /* 0x60 - 0x6F */
fd853310 305 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 306 /* 0x70 - 0x7F */
fd853310 307 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 308 /* 0x80 - 0x8F */
fd853310 309 X16(D(SrcImm)),
6aa8b732 310 /* 0x90 - 0x9F */
fd853310 311 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 312 /* 0xA0 - 0xA7 */
fd853310
AK		 313 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
314 N, D(DstMem | SrcReg | ModRM | BitOp),
315 D(DstMem | SrcReg | Src2ImmByte | ModRM),
316 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 317 /* 0xA8 - 0xAF */
fd853310
AK		 318 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
319 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
320 D(DstMem | SrcReg | Src2ImmByte | ModRM),
321 D(DstMem | SrcReg | Src2CL | ModRM),
322 D(ModRM), N,
6aa8b732 323 /* 0xB0 - 0xB7 */
fd853310
AK		 324 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
325 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
326 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
327 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 328 /* 0xB8 - 0xBF */
fd853310
AK		 329 N, N,
330 D(Group | Group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
331 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
332 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 333 /* 0xC0 - 0xCF */
fd853310
AK		 334 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
335 N, N, N, D(Group | GroupDual | Group9),
336 N, N, N, N, N, N, N, N,
6aa8b732 337 /* 0xD0 - 0xDF */
fd853310 338 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 339 /* 0xE0 - 0xEF */
fd853310 340 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 341 /* 0xF0 - 0xFF */
fd853310 342 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 343};
344
fd853310
AK		 345#undef D
346#undef N
120df890
AK		 347#undef G
348#undef GD
fd853310 349
6aa8b732 350/* EFLAGS bit definitions. */
d4c6a154
GN		 351#define EFLG_ID (1<<21)
352#define EFLG_VIP (1<<20)
353#define EFLG_VIF (1<<19)
354#define EFLG_AC (1<<18)
b1d86143
AP		 355#define EFLG_VM (1<<17)
356#define EFLG_RF (1<<16)
d4c6a154
GN		 357#define EFLG_IOPL (3<<12)
358#define EFLG_NT (1<<14)
6aa8b732
AK		 359#define EFLG_OF (1<<11)
360#define EFLG_DF (1<<10)
b1d86143 361#define EFLG_IF (1<<9)
d4c6a154 362#define EFLG_TF (1<<8)
6aa8b732
AK		 363#define EFLG_SF (1<<7)
364#define EFLG_ZF (1<<6)
365#define EFLG_AF (1<<4)
366#define EFLG_PF (1<<2)
367#define EFLG_CF (1<<0)
368
62bd430e
MG		 369#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
370#define EFLG_RESERVED_ONE_MASK 2
371
6aa8b732
AK		 372/*
373 * Instruction emulation:
374 * Most instructions are emulated directly via a fragment of inline assembly
375 * code. This allows us to save/restore EFLAGS and thus very easily pick up
376 * any modified flags.
377 */
378
05b3e0c2 379#if defined(CONFIG_X86_64)
6aa8b732
AK		 380#define _LO32 "k" /* force 32-bit operand */
381#define _STK "%%rsp" /* stack pointer */
382#elif defined(__i386__)
383#define _LO32 "" /* force 32-bit operand */
384#define _STK "%%esp" /* stack pointer */
385#endif
386
387/*
388 * These EFLAGS bits are restored from saved value during emulation, and
389 * any changes are written back to the saved value after emulation.
390 */
391#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
392
393/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 394#define _PRE_EFLAGS(_sav, _msk, _tmp) \
395 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
396 "movl %"_sav",%"_LO32 _tmp"; " \
397 "push %"_tmp"; " \
398 "push %"_tmp"; " \
399 "movl %"_msk",%"_LO32 _tmp"; " \
400 "andl %"_LO32 _tmp",("_STK"); " \
401 "pushf; " \
402 "notl %"_LO32 _tmp"; " \
403 "andl %"_LO32 _tmp",("_STK"); " \
404 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
405 "pop %"_tmp"; " \
406 "orl %"_LO32 _tmp",("_STK"); " \
407 "popf; " \
408 "pop %"_sav"; "
6aa8b732
AK		 409
410/* After executing instruction: write-back necessary bits in EFLAGS. */
411#define _POST_EFLAGS(_sav, _msk, _tmp) \
412 /* _sav |= EFLAGS & _msk; */ \
413 "pushf; " \
414 "pop %"_tmp"; " \
415 "andl %"_msk",%"_LO32 _tmp"; " \
416 "orl %"_LO32 _tmp",%"_sav"; "
417
dda96d8f
AK		 418#ifdef CONFIG_X86_64
419#define ON64(x) x
420#else
421#define ON64(x)
422#endif
423
6b7ad61f
AK		 424#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
425 do { \
426 __asm__ __volatile__ ( \
427 _PRE_EFLAGS("0", "4", "2") \
428 _op _suffix " %"_x"3,%1; " \
429 _POST_EFLAGS("0", "4", "2") \
430 : "=m" (_eflags), "=m" ((_dst).val), \
431 "=&r" (_tmp) \
432 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 433 } while (0)
6b7ad61f
AK		 434
435
6aa8b732
AK		 436/* Raw emulation: instruction has two explicit operands. */
437#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 438 do { \
439 unsigned long _tmp; \
440 \
441 switch ((_dst).bytes) { \
442 case 2: \
443 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
444 break; \
445 case 4: \
446 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
447 break; \
448 case 8: \
449 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
450 break; \
451 } \
6aa8b732
AK		 452 } while (0)
453
454#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
455 do { \
6b7ad61f 456 unsigned long _tmp; \
d77c26fc 457 switch ((_dst).bytes) { \
6aa8b732 458 case 1: \
6b7ad61f 459 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 460 break; \
461 default: \
462 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
463 _wx, _wy, _lx, _ly, _qx, _qy); \
464 break; \
465 } \
466 } while (0)
467
468/* Source operand is byte-sized and may be restricted to just %cl. */
469#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
470 __emulate_2op(_op, _src, _dst, _eflags, \
471 "b", "c", "b", "c", "b", "c", "b", "c")
472
473/* Source operand is byte, word, long or quad sized. */
474#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
475 __emulate_2op(_op, _src, _dst, _eflags, \
476 "b", "q", "w", "r", _LO32, "r", "", "r")
477
478/* Source operand is word, long or quad sized. */
479#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
480 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
481 "w", "r", _LO32, "r", "", "r")
482
d175226a
GT		 483/* Instruction has three operands and one operand is stored in ECX register */
484#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
485 do { \
486 unsigned long _tmp; \
487 _type _clv = (_cl).val; \
488 _type _srcv = (_src).val; \
489 _type _dstv = (_dst).val; \
490 \
491 __asm__ __volatile__ ( \
492 _PRE_EFLAGS("0", "5", "2") \
493 _op _suffix " %4,%1 \n" \
494 _POST_EFLAGS("0", "5", "2") \
495 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
496 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
497 ); \
498 \
499 (_cl).val = (unsigned long) _clv; \
500 (_src).val = (unsigned long) _srcv; \
501 (_dst).val = (unsigned long) _dstv; \
502 } while (0)
503
504#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
505 do { \
506 switch ((_dst).bytes) { \
507 case 2: \
508 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
509 "w", unsigned short); \
510 break; \
511 case 4: \
512 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
513 "l", unsigned int); \
514 break; \
515 case 8: \
516 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
517 "q", unsigned long)); \
518 break; \
519 } \
520 } while (0)
521
dda96d8f 522#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 523 do { \
524 unsigned long _tmp; \
525 \
dda96d8f
AK		 526 __asm__ __volatile__ ( \
527 _PRE_EFLAGS("0", "3", "2") \
528 _op _suffix " %1; " \
529 _POST_EFLAGS("0", "3", "2") \
530 : "=m" (_eflags), "+m" ((_dst).val), \
531 "=&r" (_tmp) \
532 : "i" (EFLAGS_MASK)); \
533 } while (0)
534
535/* Instruction has only one explicit operand (no source operand). */
536#define emulate_1op(_op, _dst, _eflags) \
537 do { \
d77c26fc 538 switch ((_dst).bytes) { \
dda96d8f
AK		 539 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
540 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
541 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
542 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 543 } \
544 } while (0)
545
6aa8b732
AK		 546/* Fetch next part of the instruction being emulated. */
547#define insn_fetch(_type, _size, _eip) \
548({ unsigned long _x; \
62266869 549 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 550 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 551 goto done; \
552 (_eip) += (_size); \
553 (_type)_x; \
554})
555
414e6277
GN		 556#define insn_fetch_arr(_arr, _size, _eip) \
557({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
558 if (rc != X86EMUL_CONTINUE) \
559 goto done; \
560 (_eip) += (_size); \
561})
562
ddcb2885
HH		 563static inline unsigned long ad_mask(struct decode_cache *c)
564{
565 return (1UL << (c->ad_bytes << 3)) - 1;
566}
567
6aa8b732 568/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 569static inline unsigned long
570address_mask(struct decode_cache *c, unsigned long reg)
571{
572 if (c->ad_bytes == sizeof(unsigned long))
573 return reg;
574 else
575 return reg & ad_mask(c);
576}
577
578static inline unsigned long
579register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
580{
581 return base + address_mask(c, reg);
582}
583
7a957275
HH		 584static inline void
585register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
586{
587 if (c->ad_bytes == sizeof(unsigned long))
588 *reg += inc;
589 else
590 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
591}
6aa8b732 592
7a957275
HH		 593static inline void jmp_rel(struct decode_cache *c, int rel)
594{
595 register_address_increment(c, &c->eip, rel);
596}
098c937b 597
7a5b56df
AK		 598static void set_seg_override(struct decode_cache *c, int seg)
599{
600 c->has_seg_override = true;
601 c->seg_override = seg;
602}
603
79168fd1
GN		 604static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
605 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 606{
607 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
608 return 0;
609
79168fd1 610 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 611}
612
613static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 614 struct x86_emulate_ops *ops,
7a5b56df
AK		 615 struct decode_cache *c)
616{
617 if (!c->has_seg_override)
618 return 0;
619
79168fd1 620 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 621}
622
79168fd1
GN		 623static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
624 struct x86_emulate_ops *ops)
7a5b56df 625{
79168fd1 626 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 627}
628
79168fd1
GN		 629static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
630 struct x86_emulate_ops *ops)
7a5b56df 631{
79168fd1 632 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 633}
634
54b8486f
GN		 635static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
636 u32 error, bool valid)
637{
638 ctxt->exception = vec;
639 ctxt->error_code = error;
640 ctxt->error_code_valid = valid;
641 ctxt->restart = false;
642}
643
644static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
645{
646 emulate_exception(ctxt, GP_VECTOR, err, true);
647}
648
649static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
650 int err)
651{
652 ctxt->cr2 = addr;
653 emulate_exception(ctxt, PF_VECTOR, err, true);
654}
655
656static void emulate_ud(struct x86_emulate_ctxt *ctxt)
657{
658 emulate_exception(ctxt, UD_VECTOR, 0, false);
659}
660
661static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
662{
663 emulate_exception(ctxt, TS_VECTOR, err, true);
664}
665
62266869
AK		 666static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
667 struct x86_emulate_ops *ops,
2fb53ad8 668 unsigned long eip, u8 *dest)
62266869
AK		 669{
670 struct fetch_cache *fc = &ctxt->decode.fetch;
671 int rc;
2fb53ad8 672 int size, cur_size;
62266869 673
2fb53ad8
AK		 674 if (eip == fc->end) {
675 cur_size = fc->end - fc->start;
676 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
677 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
678 size, ctxt->vcpu, NULL);
3e2815e9 679 if (rc != X86EMUL_CONTINUE)
62266869 680 return rc;
2fb53ad8 681 fc->end += size;
62266869 682 }
2fb53ad8 683 *dest = fc->data[eip - fc->start];
3e2815e9 684 return X86EMUL_CONTINUE;
62266869
AK		 685}
686
687static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
688 struct x86_emulate_ops *ops,
689 unsigned long eip, void *dest, unsigned size)
690{
3e2815e9 691 int rc;
62266869 692
eb3c79e6 693 /* x86 instructions are limited to 15 bytes. */
063db061 694 if (eip + size - ctxt->eip > 15)
eb3c79e6 695 return X86EMUL_UNHANDLEABLE;
62266869
AK		 696 while (size--) {
697 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 698 if (rc != X86EMUL_CONTINUE)
62266869
AK		 699 return rc;
700 }
3e2815e9 701 return X86EMUL_CONTINUE;
62266869
AK		 702}
703
1e3c5cb0
RR		 704/*
705 * Given the 'reg' portion of a ModRM byte, and a register block, return a
706 * pointer into the block that addresses the relevant register.
707 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
708 */
709static void *decode_register(u8 modrm_reg, unsigned long *regs,
710 int highbyte_regs)
6aa8b732
AK		 711{
712 void *p;
713
714 p = &regs[modrm_reg];
715 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
716 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
717 return p;
718}
719
720static int read_descriptor(struct x86_emulate_ctxt *ctxt,
721 struct x86_emulate_ops *ops,
722 void *ptr,
723 u16 *size, unsigned long *address, int op_bytes)
724{
725 int rc;
726
727 if (op_bytes == 2)
728 op_bytes = 3;
729 *address = 0;
cebff02b 730 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 731 ctxt->vcpu, NULL);
1b30eaa8 732 if (rc != X86EMUL_CONTINUE)
6aa8b732 733 return rc;
cebff02b 734 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 735 ctxt->vcpu, NULL);
6aa8b732
AK		 736 return rc;
737}
738
bbe9abbd
NK		 739static int test_cc(unsigned int condition, unsigned int flags)
740{
741 int rc = 0;
742
743 switch ((condition & 15) >> 1) {
744 case 0: /* o */
745 rc |= (flags & EFLG_OF);
746 break;
747 case 1: /* b/c/nae */
748 rc |= (flags & EFLG_CF);
749 break;
750 case 2: /* z/e */
751 rc |= (flags & EFLG_ZF);
752 break;
753 case 3: /* be/na */
754 rc |= (flags & (EFLG_CF|EFLG_ZF));
755 break;
756 case 4: /* s */
757 rc |= (flags & EFLG_SF);
758 break;
759 case 5: /* p/pe */
760 rc |= (flags & EFLG_PF);
761 break;
762 case 7: /* le/ng */
763 rc |= (flags & EFLG_ZF);
764 /* fall through */
765 case 6: /* l/nge */
766 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
767 break;
768 }
769
770 /* Odd condition identifiers (lsb == 1) have inverted sense. */
771 return (!!rc ^ (condition & 1));
772}
773
3c118e24
AK		 774static void decode_register_operand(struct operand *op,
775 struct decode_cache *c,
3c118e24
AK		 776 int inhibit_bytereg)
777{
33615aa9 778 unsigned reg = c->modrm_reg;
9f1ef3f8 779 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 780
781 if (!(c->d & ModRM))
782 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 783 op->type = OP_REG;
784 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 785 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 786 op->val = *(u8 *)op->ptr;
787 op->bytes = 1;
788 } else {
33615aa9 789 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 790 op->bytes = c->op_bytes;
791 switch (op->bytes) {
792 case 2:
793 op->val = *(u16 *)op->ptr;
794 break;
795 case 4:
796 op->val = *(u32 *)op->ptr;
797 break;
798 case 8:
799 op->val = *(u64 *) op->ptr;
800 break;
801 }
802 }
803 op->orig_val = op->val;
804}
805
1c73ef66
AK		 806static int decode_modrm(struct x86_emulate_ctxt *ctxt,
807 struct x86_emulate_ops *ops)
808{
809 struct decode_cache *c = &ctxt->decode;
810 u8 sib;
f5b4edcd 811 int index_reg = 0, base_reg = 0, scale;
3e2815e9 812 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 813
814 if (c->rex_prefix) {
815 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
816 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
817 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
818 }
819
820 c->modrm = insn_fetch(u8, 1, c->eip);
821 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
822 c->modrm_reg |= (c->modrm & 0x38) >> 3;
823 c->modrm_rm |= (c->modrm & 0x07);
824 c->modrm_ea = 0;
825 c->use_modrm_ea = 1;
826
827 if (c->modrm_mod == 3) {
107d6d2e
AK		 828 c->modrm_ptr = decode_register(c->modrm_rm,
829 c->regs, c->d & ByteOp);
830 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 831 return rc;
832 }
833
834 if (c->ad_bytes == 2) {
835 unsigned bx = c->regs[VCPU_REGS_RBX];
836 unsigned bp = c->regs[VCPU_REGS_RBP];
837 unsigned si = c->regs[VCPU_REGS_RSI];
838 unsigned di = c->regs[VCPU_REGS_RDI];
839
840 /* 16-bit ModR/M decode. */
841 switch (c->modrm_mod) {
842 case 0:
843 if (c->modrm_rm == 6)
844 c->modrm_ea += insn_fetch(u16, 2, c->eip);
845 break;
846 case 1:
847 c->modrm_ea += insn_fetch(s8, 1, c->eip);
848 break;
849 case 2:
850 c->modrm_ea += insn_fetch(u16, 2, c->eip);
851 break;
852 }
853 switch (c->modrm_rm) {
854 case 0:
855 c->modrm_ea += bx + si;
856 break;
857 case 1:
858 c->modrm_ea += bx + di;
859 break;
860 case 2:
861 c->modrm_ea += bp + si;
862 break;
863 case 3:
864 c->modrm_ea += bp + di;
865 break;
866 case 4:
867 c->modrm_ea += si;
868 break;
869 case 5:
870 c->modrm_ea += di;
871 break;
872 case 6:
873 if (c->modrm_mod != 0)
874 c->modrm_ea += bp;
875 break;
876 case 7:
877 c->modrm_ea += bx;
878 break;
879 }
880 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
881 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 882 if (!c->has_seg_override)
883 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 884 c->modrm_ea = (u16)c->modrm_ea;
885 } else {
886 /* 32/64-bit ModR/M decode. */
84411d85 887 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 888 sib = insn_fetch(u8, 1, c->eip);
889 index_reg |= (sib >> 3) & 7;
890 base_reg |= sib & 7;
891 scale = sib >> 6;
892
dc71d0f1
AK		 893 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
894 c->modrm_ea += insn_fetch(s32, 4, c->eip);
895 else
1c73ef66 896 c->modrm_ea += c->regs[base_reg];
dc71d0f1 897 if (index_reg != 4)
1c73ef66 898 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 899 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
900 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 901 c->rip_relative = 1;
84411d85 902 } else
1c73ef66 903 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 904 switch (c->modrm_mod) {
905 case 0:
906 if (c->modrm_rm == 5)
907 c->modrm_ea += insn_fetch(s32, 4, c->eip);
908 break;
909 case 1:
910 c->modrm_ea += insn_fetch(s8, 1, c->eip);
911 break;
912 case 2:
913 c->modrm_ea += insn_fetch(s32, 4, c->eip);
914 break;
915 }
916 }
1c73ef66
AK		 917done:
918 return rc;
919}
920
921static int decode_abs(struct x86_emulate_ctxt *ctxt,
922 struct x86_emulate_ops *ops)
923{
924 struct decode_cache *c = &ctxt->decode;
3e2815e9 925 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 926
927 switch (c->ad_bytes) {
928 case 2:
929 c->modrm_ea = insn_fetch(u16, 2, c->eip);
930 break;
931 case 4:
932 c->modrm_ea = insn_fetch(u32, 4, c->eip);
933 break;
934 case 8:
935 c->modrm_ea = insn_fetch(u64, 8, c->eip);
936 break;
937 }
938done:
939 return rc;
940}
941
6aa8b732 942int
8b4caf66 943x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 944{
e4e03ded 945 struct decode_cache *c = &ctxt->decode;
3e2815e9 946 int rc = X86EMUL_CONTINUE;
6aa8b732 947 int mode = ctxt->mode;
120df890
AK		 948 int def_op_bytes, def_ad_bytes, group, dual, goffset;
949 struct opcode opcode, *g_mod012, *g_mod3;
6aa8b732 950
5cd21917
GN		 951 /* we cannot decode insn before we complete previous rep insn */
952 WARN_ON(ctxt->restart);
953
063db061 954 c->eip = ctxt->eip;
2fb53ad8 955 c->fetch.start = c->fetch.end = c->eip;
79168fd1 956 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 957
958 switch (mode) {
959 case X86EMUL_MODE_REAL:
a0044755 960 case X86EMUL_MODE_VM86:
6aa8b732 961 case X86EMUL_MODE_PROT16:
f21b8bf4 962 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 963 break;
964 case X86EMUL_MODE_PROT32:
f21b8bf4 965 def_op_bytes = def_ad_bytes = 4;
6aa8b732 966 break;
05b3e0c2 967#ifdef CONFIG_X86_64
6aa8b732 968 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 969 def_op_bytes = 4;
970 def_ad_bytes = 8;
6aa8b732
AK		 971 break;
972#endif
973 default:
974 return -1;
975 }
976
f21b8bf4
AK		 977 c->op_bytes = def_op_bytes;
978 c->ad_bytes = def_ad_bytes;
979
6aa8b732 980 /* Legacy prefixes. */
b4c6abfe 981 for (;;) {
e4e03ded 982 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 983 case 0x66: /* operand-size override */
f21b8bf4
AK		 984 /* switch between 2/4 bytes */
985 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 986 break;
987 case 0x67: /* address-size override */
988 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 989 /* switch between 4/8 bytes */
f21b8bf4 990 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 991 else
e4e03ded 992 /* switch between 2/4 bytes */
f21b8bf4 993 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 994 break;
7a5b56df 995 case 0x26: /* ES override */
6aa8b732 996 case 0x2e: /* CS override */
7a5b56df 997 case 0x36: /* SS override */
6aa8b732 998 case 0x3e: /* DS override */
7a5b56df 999 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1000 break;
1001 case 0x64: /* FS override */
6aa8b732 1002 case 0x65: /* GS override */
7a5b56df 1003 set_seg_override(c, c->b & 7);
6aa8b732 1004 break;
b4c6abfe
LV		 1005 case 0x40 ... 0x4f: /* REX */
1006 if (mode != X86EMUL_MODE_PROT64)
1007 goto done_prefixes;
33615aa9 1008 c->rex_prefix = c->b;
b4c6abfe 1009 continue;
6aa8b732 1010 case 0xf0: /* LOCK */
e4e03ded 1011 c->lock_prefix = 1;
6aa8b732 1012 break;
ae6200ba 1013 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1014 c->rep_prefix = REPNE_PREFIX;
1015 break;
6aa8b732 1016 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1017 c->rep_prefix = REPE_PREFIX;
6aa8b732 1018 break;
6aa8b732
AK		 1019 default:
1020 goto done_prefixes;
1021 }
b4c6abfe
LV		 1022
1023 /* Any legacy prefix after a REX prefix nullifies its effect. */
1024
33615aa9 1025 c->rex_prefix = 0;
6aa8b732
AK		 1026 }
1027
1028done_prefixes:
1029
1030 /* REX prefix. */
1c73ef66 1031 if (c->rex_prefix)
33615aa9 1032 if (c->rex_prefix & 8)
e4e03ded 1033 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1034
1035 /* Opcode byte(s). */
120df890
AK		 1036 opcode = opcode_table[c->b];
1037 if (opcode.flags == 0) {
6aa8b732 1038 /* Two-byte opcode? */
e4e03ded
LV		 1039 if (c->b == 0x0f) {
1040 c->twobyte = 1;
1041 c->b = insn_fetch(u8, 1, c->eip);
120df890 1042 opcode = twobyte_table[c->b];
6aa8b732 1043 }
e09d082c 1044 }
120df890 1045 c->d = opcode.flags;
6aa8b732 1046
e09d082c
AK		 1047 if (c->d & Group) {
1048 group = c->d & GroupMask;
52811d7d 1049 dual = c->d & GroupDual;
e09d082c
AK		 1050 c->modrm = insn_fetch(u8, 1, c->eip);
1051 --c->eip;
1052
120df890
AK		 1053 if (group) {
1054 g_mod012 = g_mod3 = &group_table[group * 8];
1055 if (c->d & GroupDual)
1056 g_mod3 = &group2_table[group * 8];
1057 } else {
1058 if (c->d & GroupDual) {
1059 g_mod012 = opcode.u.gdual->mod012;
1060 g_mod3 = opcode.u.gdual->mod3;
1061 } else
1062 g_mod012 = g_mod3 = opcode.u.group;
1063 }
1064
52811d7d 1065 c->d &= ~(Group | GroupDual | GroupMask);
120df890
AK		 1066
1067 goffset = (c->modrm >> 3) & 7;
1068
1069 if ((c->modrm >> 6) == 3)
1070 opcode = g_mod3[goffset];
e09d082c 1071 else
120df890
AK		 1072 opcode = g_mod012[goffset];
1073 c->d |= opcode.flags;
e09d082c
AK		 1074 }
1075
1076 /* Unrecognised? */
047a4818 1077 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1078 DPRINTF("Cannot emulate %02x\n", c->b);
1079 return -1;
6aa8b732
AK		 1080 }
1081
6e3d5dfb
AK		 1082 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1083 c->op_bytes = 8;
1084
6aa8b732 1085 /* ModRM and SIB bytes. */
1c73ef66
AK		 1086 if (c->d & ModRM)
1087 rc = decode_modrm(ctxt, ops);
1088 else if (c->d & MemAbs)
1089 rc = decode_abs(ctxt, ops);
3e2815e9 1090 if (rc != X86EMUL_CONTINUE)
1c73ef66 1091 goto done;
6aa8b732 1092
7a5b56df
AK		 1093 if (!c->has_seg_override)
1094 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1095
7a5b56df 1096 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1097 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1098
1099 if (c->ad_bytes != 8)
1100 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1101
1102 if (c->rip_relative)
1103 c->modrm_ea += c->eip;
1104
6aa8b732
AK		 1105 /*
1106 * Decode and fetch the source operand: register, memory
1107 * or immediate.
1108 */
e4e03ded 1109 switch (c->d & SrcMask) {
6aa8b732
AK		 1110 case SrcNone:
1111 break;
1112 case SrcReg:
9f1ef3f8 1113 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1114 break;
1115 case SrcMem16:
e4e03ded 1116 c->src.bytes = 2;
6aa8b732
AK		 1117 goto srcmem_common;
1118 case SrcMem32:
e4e03ded 1119 c->src.bytes = 4;
6aa8b732
AK		 1120 goto srcmem_common;
1121 case SrcMem:
e4e03ded
LV		 1122 c->src.bytes = (c->d & ByteOp) ? 1 :
1123 c->op_bytes;
b85b9ee9 1124 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1125 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1126 break;
d77c26fc 1127 srcmem_common:
4e62417b
AJ		 1128 /*
1129 * For instructions with a ModR/M byte, switch to register
1130 * access if Mod = 3.
1131 */
e4e03ded
LV		 1132 if ((c->d & ModRM) && c->modrm_mod == 3) {
1133 c->src.type = OP_REG;
66b85505 1134 c->src.val = c->modrm_val;
107d6d2e 1135 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1136 break;
1137 }
e4e03ded 1138 c->src.type = OP_MEM;
69f55cb1
GN		 1139 c->src.ptr = (unsigned long *)c->modrm_ea;
1140 c->src.val = 0;
6aa8b732
AK		 1141 break;
1142 case SrcImm:
c9eaf20f 1143 case SrcImmU:
e4e03ded
LV		 1144 c->src.type = OP_IMM;
1145 c->src.ptr = (unsigned long *)c->eip;
1146 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1147 if (c->src.bytes == 8)
1148 c->src.bytes = 4;
6aa8b732 1149 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1150 switch (c->src.bytes) {
6aa8b732 1151 case 1:
e4e03ded 1152 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1153 break;
1154 case 2:
e4e03ded 1155 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1156 break;
1157 case 4:
e4e03ded 1158 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1159 break;
1160 }
c9eaf20f
AK		 1161 if ((c->d & SrcMask) == SrcImmU) {
1162 switch (c->src.bytes) {
1163 case 1:
1164 c->src.val &= 0xff;
1165 break;
1166 case 2:
1167 c->src.val &= 0xffff;
1168 break;
1169 case 4:
1170 c->src.val &= 0xffffffff;
1171 break;
1172 }
1173 }
6aa8b732
AK		 1174 break;
1175 case SrcImmByte:
341de7e3 1176 case SrcImmUByte:
e4e03ded
LV		 1177 c->src.type = OP_IMM;
1178 c->src.ptr = (unsigned long *)c->eip;
1179 c->src.bytes = 1;
341de7e3
GN		 1180 if ((c->d & SrcMask) == SrcImmByte)
1181 c->src.val = insn_fetch(s8, 1, c->eip);
1182 else
1183 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1184 break;
5d55f299
WY		 1185 case SrcAcc:
1186 c->src.type = OP_REG;
1187 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1188 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1189 switch (c->src.bytes) {
1190 case 1:
1191 c->src.val = *(u8 *)c->src.ptr;
1192 break;
1193 case 2:
1194 c->src.val = *(u16 *)c->src.ptr;
1195 break;
1196 case 4:
1197 c->src.val = *(u32 *)c->src.ptr;
1198 break;
1199 case 8:
1200 c->src.val = *(u64 *)c->src.ptr;
1201 break;
1202 }
1203 break;
bfcadf83
GT		 1204 case SrcOne:
1205 c->src.bytes = 1;
1206 c->src.val = 1;
1207 break;
a682e354
GN		 1208 case SrcSI:
1209 c->src.type = OP_MEM;
1210 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1211 c->src.ptr = (unsigned long *)
79168fd1 1212 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1213 c->regs[VCPU_REGS_RSI]);
1214 c->src.val = 0;
1215 break;
414e6277
GN		 1216 case SrcImmFAddr:
1217 c->src.type = OP_IMM;
1218 c->src.ptr = (unsigned long *)c->eip;
1219 c->src.bytes = c->op_bytes + 2;
1220 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1221 break;
1222 case SrcMemFAddr:
1223 c->src.type = OP_MEM;
1224 c->src.ptr = (unsigned long *)c->modrm_ea;
1225 c->src.bytes = c->op_bytes + 2;
1226 break;
6aa8b732
AK		 1227 }
1228
0dc8d10f
GT		 1229 /*
1230 * Decode and fetch the second source operand: register, memory
1231 * or immediate.
1232 */
1233 switch (c->d & Src2Mask) {
1234 case Src2None:
1235 break;
1236 case Src2CL:
1237 c->src2.bytes = 1;
1238 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1239 break;
1240 case Src2ImmByte:
1241 c->src2.type = OP_IMM;
1242 c->src2.ptr = (unsigned long *)c->eip;
1243 c->src2.bytes = 1;
1244 c->src2.val = insn_fetch(u8, 1, c->eip);
1245 break;
1246 case Src2One:
1247 c->src2.bytes = 1;
1248 c->src2.val = 1;
1249 break;
1250 }
1251
038e51de 1252 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1253 switch (c->d & DstMask) {
038e51de
AK		 1254 case ImplicitOps:
1255 /* Special instructions do their own operand decoding. */
8b4caf66 1256 return 0;
038e51de 1257 case DstReg:
9f1ef3f8 1258 decode_register_operand(&c->dst, c,
3c118e24 1259 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1260 break;
1261 case DstMem:
6550e1f1 1262 case DstMem64:
e4e03ded 1263 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1264 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1265 c->dst.type = OP_REG;
66b85505 1266 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1267 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1268 break;
1269 }
8b4caf66 1270 c->dst.type = OP_MEM;
69f55cb1 1271 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1272 if ((c->d & DstMask) == DstMem64)
1273 c->dst.bytes = 8;
1274 else
1275 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1276 c->dst.val = 0;
1277 if (c->d & BitOp) {
1278 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1279
1280 c->dst.ptr = (void *)c->dst.ptr +
1281 (c->src.val & mask) / 8;
1282 }
8b4caf66 1283 break;
9c9fddd0
GT		 1284 case DstAcc:
1285 c->dst.type = OP_REG;
d6d367d6 1286 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1287 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1288 switch (c->dst.bytes) {
9c9fddd0
GT		 1289 case 1:
1290 c->dst.val = *(u8 *)c->dst.ptr;
1291 break;
1292 case 2:
1293 c->dst.val = *(u16 *)c->dst.ptr;
1294 break;
1295 case 4:
1296 c->dst.val = *(u32 *)c->dst.ptr;
1297 break;
d6d367d6
GN		 1298 case 8:
1299 c->dst.val = *(u64 *)c->dst.ptr;
1300 break;
9c9fddd0
GT		 1301 }
1302 c->dst.orig_val = c->dst.val;
1303 break;
a682e354
GN		 1304 case DstDI:
1305 c->dst.type = OP_MEM;
1306 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1307 c->dst.ptr = (unsigned long *)
79168fd1 1308 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1309 c->regs[VCPU_REGS_RDI]);
1310 c->dst.val = 0;
1311 break;
8b4caf66
LV		 1312 }
1313
1314done:
1315 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1316}
1317
9de41573
GN		 1318static int read_emulated(struct x86_emulate_ctxt *ctxt,
1319 struct x86_emulate_ops *ops,
1320 unsigned long addr, void *dest, unsigned size)
1321{
1322 int rc;
1323 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1324 u32 err;
9de41573
GN		 1325
1326 while (size) {
1327 int n = min(size, 8u);
1328 size -= n;
1329 if (mc->pos < mc->end)
1330 goto read_cached;
1331
8fe681e9
GN		 1332 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1333 ctxt->vcpu);
1334 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1335 emulate_pf(ctxt, addr, err);
9de41573
GN		 1336 if (rc != X86EMUL_CONTINUE)
1337 return rc;
1338 mc->end += n;
1339
1340 read_cached:
1341 memcpy(dest, mc->data + mc->pos, n);
1342 mc->pos += n;
1343 dest += n;
1344 addr += n;
1345 }
1346 return X86EMUL_CONTINUE;
1347}
1348
7b262e90
GN		 1349static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1350 struct x86_emulate_ops *ops,
1351 unsigned int size, unsigned short port,
1352 void *dest)
1353{
1354 struct read_cache *rc = &ctxt->decode.io_read;
1355
1356 if (rc->pos == rc->end) { /* refill pio read ahead */
1357 struct decode_cache *c = &ctxt->decode;
1358 unsigned int in_page, n;
1359 unsigned int count = c->rep_prefix ?
1360 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1361 in_page = (ctxt->eflags & EFLG_DF) ?
1362 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1363 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1364 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1365 count);
1366 if (n == 0)
1367 n = 1;
1368 rc->pos = rc->end = 0;
1369 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1370 return 0;
1371 rc->end = n * size;
1372 }
1373
1374 memcpy(dest, rc->data + rc->pos, size);
1375 rc->pos += size;
1376 return 1;
1377}
1378
38ba30ba
GN		 1379static u32 desc_limit_scaled(struct desc_struct *desc)
1380{
1381 u32 limit = get_desc_limit(desc);
1382
1383 return desc->g ? (limit << 12) | 0xfff : limit;
1384}
1385
1386static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1387 struct x86_emulate_ops *ops,
1388 u16 selector, struct desc_ptr *dt)
1389{
1390 if (selector & 1 << 2) {
1391 struct desc_struct desc;
1392 memset (dt, 0, sizeof *dt);
1393 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1394 return;
1395
1396 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1397 dt->address = get_desc_base(&desc);
1398 } else
1399 ops->get_gdt(dt, ctxt->vcpu);
1400}
1401
1402/* allowed just for 8 bytes segments */
1403static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1404 struct x86_emulate_ops *ops,
1405 u16 selector, struct desc_struct *desc)
1406{
1407 struct desc_ptr dt;
1408 u16 index = selector >> 3;
1409 int ret;
1410 u32 err;
1411 ulong addr;
1412
1413 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1414
1415 if (dt.size < index * 8 + 7) {
54b8486f 1416 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1417 return X86EMUL_PROPAGATE_FAULT;
1418 }
1419 addr = dt.address + index * 8;
1420 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1421 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1422 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1423
1424 return ret;
1425}
1426
1427/* allowed just for 8 bytes segments */
1428static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1429 struct x86_emulate_ops *ops,
1430 u16 selector, struct desc_struct *desc)
1431{
1432 struct desc_ptr dt;
1433 u16 index = selector >> 3;
1434 u32 err;
1435 ulong addr;
1436 int ret;
1437
1438 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1439
1440 if (dt.size < index * 8 + 7) {
54b8486f 1441 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1442 return X86EMUL_PROPAGATE_FAULT;
1443 }
1444
1445 addr = dt.address + index * 8;
1446 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1447 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1448 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1449
1450 return ret;
1451}
1452
1453static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1454 struct x86_emulate_ops *ops,
1455 u16 selector, int seg)
1456{
1457 struct desc_struct seg_desc;
1458 u8 dpl, rpl, cpl;
1459 unsigned err_vec = GP_VECTOR;
1460 u32 err_code = 0;
1461 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1462 int ret;
1463
1464 memset(&seg_desc, 0, sizeof seg_desc);
1465
1466 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1467 || ctxt->mode == X86EMUL_MODE_REAL) {
1468 /* set real mode segment descriptor */
1469 set_desc_base(&seg_desc, selector << 4);
1470 set_desc_limit(&seg_desc, 0xffff);
1471 seg_desc.type = 3;
1472 seg_desc.p = 1;
1473 seg_desc.s = 1;
1474 goto load;
1475 }
1476
1477 /* NULL selector is not valid for TR, CS and SS */
1478 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1479 && null_selector)
1480 goto exception;
1481
1482 /* TR should be in GDT only */
1483 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1484 goto exception;
1485
1486 if (null_selector) /* for NULL selector skip all following checks */
1487 goto load;
1488
1489 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1490 if (ret != X86EMUL_CONTINUE)
1491 return ret;
1492
1493 err_code = selector & 0xfffc;
1494 err_vec = GP_VECTOR;
1495
1496 /* can't load system descriptor into segment selecor */
1497 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1498 goto exception;
1499
1500 if (!seg_desc.p) {
1501 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1502 goto exception;
1503 }
1504
1505 rpl = selector & 3;
1506 dpl = seg_desc.dpl;
1507 cpl = ops->cpl(ctxt->vcpu);
1508
1509 switch (seg) {
1510 case VCPU_SREG_SS:
1511 /*
1512 * segment is not a writable data segment or segment
1513 * selector's RPL != CPL or segment selector's RPL != CPL
1514 */
1515 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1516 goto exception;
1517 break;
1518 case VCPU_SREG_CS:
1519 if (!(seg_desc.type & 8))
1520 goto exception;
1521
1522 if (seg_desc.type & 4) {
1523 /* conforming */
1524 if (dpl > cpl)
1525 goto exception;
1526 } else {
1527 /* nonconforming */
1528 if (rpl > cpl || dpl != cpl)
1529 goto exception;
1530 }
1531 /* CS(RPL) <- CPL */
1532 selector = (selector & 0xfffc) | cpl;
1533 break;
1534 case VCPU_SREG_TR:
1535 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1536 goto exception;
1537 break;
1538 case VCPU_SREG_LDTR:
1539 if (seg_desc.s || seg_desc.type != 2)
1540 goto exception;
1541 break;
1542 default: /* DS, ES, FS, or GS */
1543 /*
1544 * segment is not a data or readable code segment or
1545 * ((segment is a data or nonconforming code segment)
1546 * and (both RPL and CPL > DPL))
1547 */
1548 if ((seg_desc.type & 0xa) == 0x8 ||
1549 (((seg_desc.type & 0xc) != 0xc) &&
1550 (rpl > dpl && cpl > dpl)))
1551 goto exception;
1552 break;
1553 }
1554
1555 if (seg_desc.s) {
1556 /* mark segment as accessed */
1557 seg_desc.type |= 1;
1558 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1559 if (ret != X86EMUL_CONTINUE)
1560 return ret;
1561 }
1562load:
1563 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1564 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1565 return X86EMUL_CONTINUE;
1566exception:
54b8486f 1567 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1568 return X86EMUL_PROPAGATE_FAULT;
1569}
1570
c37eda13
WY		 1571static inline int writeback(struct x86_emulate_ctxt *ctxt,
1572 struct x86_emulate_ops *ops)
1573{
1574 int rc;
1575 struct decode_cache *c = &ctxt->decode;
1576 u32 err;
1577
1578 switch (c->dst.type) {
1579 case OP_REG:
1580 /* The 4-byte case *is* correct:
1581 * in 64-bit mode we zero-extend.
1582 */
1583 switch (c->dst.bytes) {
1584 case 1:
1585 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1586 break;
1587 case 2:
1588 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1589 break;
1590 case 4:
1591 *c->dst.ptr = (u32)c->dst.val;
1592 break; /* 64b: zero-ext */
1593 case 8:
1594 *c->dst.ptr = c->dst.val;
1595 break;
1596 }
1597 break;
1598 case OP_MEM:
1599 if (c->lock_prefix)
1600 rc = ops->cmpxchg_emulated(
1601 (unsigned long)c->dst.ptr,
1602 &c->dst.orig_val,
1603 &c->dst.val,
1604 c->dst.bytes,
1605 &err,
1606 ctxt->vcpu);
1607 else
1608 rc = ops->write_emulated(
1609 (unsigned long)c->dst.ptr,
1610 &c->dst.val,
1611 c->dst.bytes,
1612 &err,
1613 ctxt->vcpu);
1614 if (rc == X86EMUL_PROPAGATE_FAULT)
1615 emulate_pf(ctxt,
1616 (unsigned long)c->dst.ptr, err);
1617 if (rc != X86EMUL_CONTINUE)
1618 return rc;
1619 break;
1620 case OP_NONE:
1621 /* no writeback */
1622 break;
1623 default:
1624 break;
1625 }
1626 return X86EMUL_CONTINUE;
1627}
1628
79168fd1
GN		 1629static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1630 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1631{
1632 struct decode_cache *c = &ctxt->decode;
1633
1634 c->dst.type = OP_MEM;
1635 c->dst.bytes = c->op_bytes;
1636 c->dst.val = c->src.val;
7a957275 1637 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1638 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1639 c->regs[VCPU_REGS_RSP]);
1640}
1641
faa5a3ae 1642static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1643 struct x86_emulate_ops *ops,
1644 void *dest, int len)
8cdbd2c9
LV		 1645{
1646 struct decode_cache *c = &ctxt->decode;
1647 int rc;
1648
79168fd1 1649 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1650 c->regs[VCPU_REGS_RSP]),
1651 dest, len);
b60d513c 1652 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1653 return rc;
1654
350f69dc 1655 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1656 return rc;
1657}
8cdbd2c9 1658
d4c6a154
GN		 1659static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1660 struct x86_emulate_ops *ops,
1661 void *dest, int len)
1662{
1663 int rc;
1664 unsigned long val, change_mask;
1665 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1666 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1667
1668 rc = emulate_pop(ctxt, ops, &val, len);
1669 if (rc != X86EMUL_CONTINUE)
1670 return rc;
1671
1672 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1673 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1674
1675 switch(ctxt->mode) {
1676 case X86EMUL_MODE_PROT64:
1677 case X86EMUL_MODE_PROT32:
1678 case X86EMUL_MODE_PROT16:
1679 if (cpl == 0)
1680 change_mask |= EFLG_IOPL;
1681 if (cpl <= iopl)
1682 change_mask |= EFLG_IF;
1683 break;
1684 case X86EMUL_MODE_VM86:
1685 if (iopl < 3) {
54b8486f 1686 emulate_gp(ctxt, 0);
d4c6a154
GN		 1687 return X86EMUL_PROPAGATE_FAULT;
1688 }
1689 change_mask |= EFLG_IF;
1690 break;
1691 default: /* real mode */
1692 change_mask |= (EFLG_IOPL | EFLG_IF);
1693 break;
1694 }
1695
1696 *(unsigned long *)dest =
1697 (ctxt->eflags & ~change_mask) | (val & change_mask);
1698
1699 return rc;
1700}
1701
79168fd1
GN		 1702static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1703 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1704{
1705 struct decode_cache *c = &ctxt->decode;
0934ac9d 1706
79168fd1 1707 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1708
79168fd1 1709 emulate_push(ctxt, ops);
0934ac9d
MG		 1710}
1711
1712static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1713 struct x86_emulate_ops *ops, int seg)
1714{
1715 struct decode_cache *c = &ctxt->decode;
1716 unsigned long selector;
1717 int rc;
1718
1719 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1720 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1721 return rc;
1722
2e873022 1723 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1724 return rc;
1725}
1726
c37eda13 1727static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1728 struct x86_emulate_ops *ops)
abcf14b5
MG		 1729{
1730 struct decode_cache *c = &ctxt->decode;
1731 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1732 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1733 int reg = VCPU_REGS_RAX;
1734
1735 while (reg <= VCPU_REGS_RDI) {
1736 (reg == VCPU_REGS_RSP) ?
1737 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1738
79168fd1 1739 emulate_push(ctxt, ops);
c37eda13
WY		 1740
1741 rc = writeback(ctxt, ops);
1742 if (rc != X86EMUL_CONTINUE)
1743 return rc;
1744
abcf14b5
MG		 1745 ++reg;
1746 }
c37eda13
WY		 1747
1748 /* Disable writeback. */
1749 c->dst.type = OP_NONE;
1750
1751 return rc;
abcf14b5
MG		 1752}
1753
1754static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1755 struct x86_emulate_ops *ops)
1756{
1757 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1758 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1759 int reg = VCPU_REGS_RDI;
1760
1761 while (reg >= VCPU_REGS_RAX) {
1762 if (reg == VCPU_REGS_RSP) {
1763 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1764 c->op_bytes);
1765 --reg;
1766 }
1767
1768 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1769 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1770 break;
1771 --reg;
1772 }
1773 return rc;
1774}
1775
62bd430e
MG		 1776static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1777 struct x86_emulate_ops *ops)
1778{
1779 struct decode_cache *c = &ctxt->decode;
1780 int rc = X86EMUL_CONTINUE;
1781 unsigned long temp_eip = 0;
1782 unsigned long temp_eflags = 0;
1783 unsigned long cs = 0;
1784 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1785 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1786 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1787 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1788
1789 /* TODO: Add stack limit check */
1790
1791 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1792
1793 if (rc != X86EMUL_CONTINUE)
1794 return rc;
1795
1796 if (temp_eip & ~0xffff) {
1797 emulate_gp(ctxt, 0);
1798 return X86EMUL_PROPAGATE_FAULT;
1799 }
1800
1801 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1802
1803 if (rc != X86EMUL_CONTINUE)
1804 return rc;
1805
1806 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1807
1808 if (rc != X86EMUL_CONTINUE)
1809 return rc;
1810
1811 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1812
1813 if (rc != X86EMUL_CONTINUE)
1814 return rc;
1815
1816 c->eip = temp_eip;
1817
1818
1819 if (c->op_bytes == 4)
1820 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1821 else if (c->op_bytes == 2) {
1822 ctxt->eflags &= ~0xffff;
1823 ctxt->eflags |= temp_eflags;
1824 }
1825
1826 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1827 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1828
1829 return rc;
1830}
1831
1832static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1833 struct x86_emulate_ops* ops)
1834{
1835 switch(ctxt->mode) {
1836 case X86EMUL_MODE_REAL:
1837 return emulate_iret_real(ctxt, ops);
1838 case X86EMUL_MODE_VM86:
1839 case X86EMUL_MODE_PROT16:
1840 case X86EMUL_MODE_PROT32:
1841 case X86EMUL_MODE_PROT64:
1842 default:
1843 /* iret from protected mode unimplemented yet */
1844 return X86EMUL_UNHANDLEABLE;
1845 }
1846}
1847
faa5a3ae
AK		 1848static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1849 struct x86_emulate_ops *ops)
1850{
1851 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1852
1b30eaa8 1853 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1854}
1855
05f086f8 1856static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1857{
05f086f8 1858 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1859 switch (c->modrm_reg) {
1860 case 0: /* rol */
05f086f8 1861 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1862 break;
1863 case 1: /* ror */
05f086f8 1864 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1865 break;
1866 case 2: /* rcl */
05f086f8 1867 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1868 break;
1869 case 3: /* rcr */
05f086f8 1870 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1871 break;
1872 case 4: /* sal/shl */
1873 case 6: /* sal/shl */
05f086f8 1874 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1875 break;
1876 case 5: /* shr */
05f086f8 1877 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1878 break;
1879 case 7: /* sar */
05f086f8 1880 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1881 break;
1882 }
1883}
1884
1885static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1886 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1887{
1888 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1889
1890 switch (c->modrm_reg) {
1891 case 0 ... 1: /* test */
05f086f8 1892 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1893 break;
1894 case 2: /* not */
1895 c->dst.val = ~c->dst.val;
1896 break;
1897 case 3: /* neg */
05f086f8 1898 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1899 break;
1900 default:
aca06a83 1901 return 0;
8cdbd2c9 1902 }
aca06a83 1903 return 1;
8cdbd2c9
LV		 1904}
1905
1906static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1907 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1908{
1909 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1910
1911 switch (c->modrm_reg) {
1912 case 0: /* inc */
05f086f8 1913 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1914 break;
1915 case 1: /* dec */
05f086f8 1916 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1917 break;
d19292e4
MG		 1918 case 2: /* call near abs */ {
1919 long int old_eip;
1920 old_eip = c->eip;
1921 c->eip = c->src.val;
1922 c->src.val = old_eip;
79168fd1 1923 emulate_push(ctxt, ops);
d19292e4
MG		 1924 break;
1925 }
8cdbd2c9 1926 case 4: /* jmp abs */
fd60754e 1927 c->eip = c->src.val;
8cdbd2c9
LV		 1928 break;
1929 case 6: /* push */
79168fd1 1930 emulate_push(ctxt, ops);
8cdbd2c9 1931 break;
8cdbd2c9 1932 }
1b30eaa8 1933 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1934}
1935
1936static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1937 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1938{
1939 struct decode_cache *c = &ctxt->decode;
16518d5a 1940 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1941
1942 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1943 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1944 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1945 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1946 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1947 } else {
16518d5a
AK		 1948 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1949 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1950
05f086f8 1951 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1952 }
1b30eaa8 1953 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1954}
1955
a77ab5ea
AK		 1956static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1957 struct x86_emulate_ops *ops)
1958{
1959 struct decode_cache *c = &ctxt->decode;
1960 int rc;
1961 unsigned long cs;
1962
1963 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1964 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1965 return rc;
1966 if (c->op_bytes == 4)
1967 c->eip = (u32)c->eip;
1968 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1969 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1970 return rc;
2e873022 1971 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1972 return rc;
1973}
1974
e66bb2cc
AP		 1975static inline void
1976setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1977 struct x86_emulate_ops *ops, struct desc_struct *cs,
1978 struct desc_struct *ss)
e66bb2cc 1979{
79168fd1
GN		 1980 memset(cs, 0, sizeof(struct desc_struct));
1981 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1982 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1983
1984 cs->l = 0; /* will be adjusted later */
79168fd1 1985 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1986 cs->g = 1; /* 4kb granularity */
79168fd1 1987 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1988 cs->type = 0x0b; /* Read, Execute, Accessed */
1989 cs->s = 1;
1990 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1991 cs->p = 1;
1992 cs->d = 1;
e66bb2cc 1993
79168fd1
GN		 1994 set_desc_base(ss, 0); /* flat segment */
1995 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1996 ss->g = 1; /* 4kb granularity */
1997 ss->s = 1;
1998 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1999 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2000 ss->dpl = 0;
79168fd1 2001 ss->p = 1;
e66bb2cc
AP		 2002}
2003
2004static int
3fb1b5db 2005emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 2006{
2007 struct decode_cache *c = &ctxt->decode;
79168fd1 2008 struct desc_struct cs, ss;
e66bb2cc 2009 u64 msr_data;
79168fd1 2010 u16 cs_sel, ss_sel;
e66bb2cc
AP		 2011
2012 /* syscall is not available in real mode */
2e901c4c
GN		 2013 if (ctxt->mode == X86EMUL_MODE_REAL ||
2014 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2015 emulate_ud(ctxt);
2e901c4c
GN		 2016 return X86EMUL_PROPAGATE_FAULT;
2017 }
e66bb2cc 2018
79168fd1 2019 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 2020
3fb1b5db 2021 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 2022 msr_data >>= 32;
79168fd1
GN		 2023 cs_sel = (u16)(msr_data & 0xfffc);
2024 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 2025
2026 if (is_long_mode(ctxt->vcpu)) {
79168fd1 2027 cs.d = 0;
e66bb2cc
AP		 2028 cs.l = 1;
2029 }
79168fd1
GN		 2030 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2031 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2032 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2033 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2034
2035 c->regs[VCPU_REGS_RCX] = c->eip;
2036 if (is_long_mode(ctxt->vcpu)) {
2037#ifdef CONFIG_X86_64
2038 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2039
3fb1b5db
GN		 2040 ops->get_msr(ctxt->vcpu,
2041 ctxt->mode == X86EMUL_MODE_PROT64 ?
2042 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2043 c->eip = msr_data;
2044
3fb1b5db 2045 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2046 ctxt->eflags &= ~(msr_data | EFLG_RF);
2047#endif
2048 } else {
2049 /* legacy mode */
3fb1b5db 2050 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2051 c->eip = (u32)msr_data;
2052
2053 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2054 }
2055
e54cfa97 2056 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2057}
2058
8c604352 2059static int
3fb1b5db 2060emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2061{
2062 struct decode_cache *c = &ctxt->decode;
79168fd1 2063 struct desc_struct cs, ss;
8c604352 2064 u64 msr_data;
79168fd1 2065 u16 cs_sel, ss_sel;
8c604352 2066
a0044755
GN		 2067 /* inject #GP if in real mode */
2068 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2069 emulate_gp(ctxt, 0);
2e901c4c 2070 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2071 }
2072
2073 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2074 * Therefore, we inject an #UD.
2075 */
2e901c4c 2076 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2077 emulate_ud(ctxt);
2e901c4c
GN		 2078 return X86EMUL_PROPAGATE_FAULT;
2079 }
8c604352 2080
79168fd1 2081 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2082
3fb1b5db 2083 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2084 switch (ctxt->mode) {
2085 case X86EMUL_MODE_PROT32:
2086 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2087 emulate_gp(ctxt, 0);
e54cfa97 2088 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2089 }
2090 break;
2091 case X86EMUL_MODE_PROT64:
2092 if (msr_data == 0x0) {
54b8486f 2093 emulate_gp(ctxt, 0);
e54cfa97 2094 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2095 }
2096 break;
2097 }
2098
2099 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2100 cs_sel = (u16)msr_data;
2101 cs_sel &= ~SELECTOR_RPL_MASK;
2102 ss_sel = cs_sel + 8;
2103 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2104 if (ctxt->mode == X86EMUL_MODE_PROT64
2105 || is_long_mode(ctxt->vcpu)) {
79168fd1 2106 cs.d = 0;
8c604352
AP		 2107 cs.l = 1;
2108 }
2109
79168fd1
GN		 2110 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2111 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2112 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2113 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2114
3fb1b5db 2115 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2116 c->eip = msr_data;
2117
3fb1b5db 2118 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2119 c->regs[VCPU_REGS_RSP] = msr_data;
2120
e54cfa97 2121 return X86EMUL_CONTINUE;
8c604352
AP		 2122}
2123
4668f050 2124static int
3fb1b5db 2125emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2126{
2127 struct decode_cache *c = &ctxt->decode;
79168fd1 2128 struct desc_struct cs, ss;
4668f050
AP		 2129 u64 msr_data;
2130 int usermode;
79168fd1 2131 u16 cs_sel, ss_sel;
4668f050 2132
a0044755
GN		 2133 /* inject #GP if in real mode or Virtual 8086 mode */
2134 if (ctxt->mode == X86EMUL_MODE_REAL ||
2135 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2136 emulate_gp(ctxt, 0);
2e901c4c 2137 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2138 }
2139
79168fd1 2140 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2141
2142 if ((c->rex_prefix & 0x8) != 0x0)
2143 usermode = X86EMUL_MODE_PROT64;
2144 else
2145 usermode = X86EMUL_MODE_PROT32;
2146
2147 cs.dpl = 3;
2148 ss.dpl = 3;
3fb1b5db 2149 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2150 switch (usermode) {
2151 case X86EMUL_MODE_PROT32:
79168fd1 2152 cs_sel = (u16)(msr_data + 16);
4668f050 2153 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2154 emulate_gp(ctxt, 0);
e54cfa97 2155 return X86EMUL_PROPAGATE_FAULT;
4668f050 2156 }
79168fd1 2157 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2158 break;
2159 case X86EMUL_MODE_PROT64:
79168fd1 2160 cs_sel = (u16)(msr_data + 32);
4668f050 2161 if (msr_data == 0x0) {
54b8486f 2162 emulate_gp(ctxt, 0);
e54cfa97 2163 return X86EMUL_PROPAGATE_FAULT;
4668f050 2164 }
79168fd1
GN		 2165 ss_sel = cs_sel + 8;
2166 cs.d = 0;
4668f050
AP		 2167 cs.l = 1;
2168 break;
2169 }
79168fd1
GN		 2170 cs_sel |= SELECTOR_RPL_MASK;
2171 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2172
79168fd1
GN		 2173 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2174 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2175 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2176 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2177
bdb475a3
GN		 2178 c->eip = c->regs[VCPU_REGS_RDX];
2179 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2180
e54cfa97 2181 return X86EMUL_CONTINUE;
4668f050
AP		 2182}
2183
9c537244
GN		 2184static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2185 struct x86_emulate_ops *ops)
f850e2e6
GN		 2186{
2187 int iopl;
2188 if (ctxt->mode == X86EMUL_MODE_REAL)
2189 return false;
2190 if (ctxt->mode == X86EMUL_MODE_VM86)
2191 return true;
2192 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2193 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2194}
2195
2196static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2197 struct x86_emulate_ops *ops,
2198 u16 port, u16 len)
2199{
79168fd1 2200 struct desc_struct tr_seg;
f850e2e6
GN		 2201 int r;
2202 u16 io_bitmap_ptr;
2203 u8 perm, bit_idx = port & 0x7;
2204 unsigned mask = (1 << len) - 1;
2205
79168fd1
GN		 2206 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2207 if (!tr_seg.p)
f850e2e6 2208 return false;
79168fd1 2209 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2210 return false;
79168fd1
GN		 2211 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2212 ctxt->vcpu, NULL);
f850e2e6
GN		 2213 if (r != X86EMUL_CONTINUE)
2214 return false;
79168fd1 2215 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2216 return false;
79168fd1
GN		 2217 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2218 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2219 if (r != X86EMUL_CONTINUE)
2220 return false;
2221 if ((perm >> bit_idx) & mask)
2222 return false;
2223 return true;
2224}
2225
2226static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2227 struct x86_emulate_ops *ops,
2228 u16 port, u16 len)
2229{
9c537244 2230 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2231 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2232 return false;
2233 return true;
2234}
2235
38ba30ba
GN		 2236static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2237 struct x86_emulate_ops *ops,
2238 struct tss_segment_16 *tss)
2239{
2240 struct decode_cache *c = &ctxt->decode;
2241
2242 tss->ip = c->eip;
2243 tss->flag = ctxt->eflags;
2244 tss->ax = c->regs[VCPU_REGS_RAX];
2245 tss->cx = c->regs[VCPU_REGS_RCX];
2246 tss->dx = c->regs[VCPU_REGS_RDX];
2247 tss->bx = c->regs[VCPU_REGS_RBX];
2248 tss->sp = c->regs[VCPU_REGS_RSP];
2249 tss->bp = c->regs[VCPU_REGS_RBP];
2250 tss->si = c->regs[VCPU_REGS_RSI];
2251 tss->di = c->regs[VCPU_REGS_RDI];
2252
2253 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2254 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2255 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2256 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2257 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2258}
2259
2260static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2261 struct x86_emulate_ops *ops,
2262 struct tss_segment_16 *tss)
2263{
2264 struct decode_cache *c = &ctxt->decode;
2265 int ret;
2266
2267 c->eip = tss->ip;
2268 ctxt->eflags = tss->flag | 2;
2269 c->regs[VCPU_REGS_RAX] = tss->ax;
2270 c->regs[VCPU_REGS_RCX] = tss->cx;
2271 c->regs[VCPU_REGS_RDX] = tss->dx;
2272 c->regs[VCPU_REGS_RBX] = tss->bx;
2273 c->regs[VCPU_REGS_RSP] = tss->sp;
2274 c->regs[VCPU_REGS_RBP] = tss->bp;
2275 c->regs[VCPU_REGS_RSI] = tss->si;
2276 c->regs[VCPU_REGS_RDI] = tss->di;
2277
2278 /*
2279 * SDM says that segment selectors are loaded before segment
2280 * descriptors
2281 */
2282 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2283 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2284 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2285 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2286 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2287
2288 /*
2289 * Now load segment descriptors. If fault happenes at this stage
2290 * it is handled in a context of new task
2291 */
2292 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2293 if (ret != X86EMUL_CONTINUE)
2294 return ret;
2295 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2296 if (ret != X86EMUL_CONTINUE)
2297 return ret;
2298 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2299 if (ret != X86EMUL_CONTINUE)
2300 return ret;
2301 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2302 if (ret != X86EMUL_CONTINUE)
2303 return ret;
2304 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307
2308 return X86EMUL_CONTINUE;
2309}
2310
2311static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2312 struct x86_emulate_ops *ops,
2313 u16 tss_selector, u16 old_tss_sel,
2314 ulong old_tss_base, struct desc_struct *new_desc)
2315{
2316 struct tss_segment_16 tss_seg;
2317 int ret;
2318 u32 err, new_tss_base = get_desc_base(new_desc);
2319
2320 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2321 &err);
2322 if (ret == X86EMUL_PROPAGATE_FAULT) {
2323 /* FIXME: need to provide precise fault address */
54b8486f 2324 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2325 return ret;
2326 }
2327
2328 save_state_to_tss16(ctxt, ops, &tss_seg);
2329
2330 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2331 &err);
2332 if (ret == X86EMUL_PROPAGATE_FAULT) {
2333 /* FIXME: need to provide precise fault address */
54b8486f 2334 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2335 return ret;
2336 }
2337
2338 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2339 &err);
2340 if (ret == X86EMUL_PROPAGATE_FAULT) {
2341 /* FIXME: need to provide precise fault address */
54b8486f 2342 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2343 return ret;
2344 }
2345
2346 if (old_tss_sel != 0xffff) {
2347 tss_seg.prev_task_link = old_tss_sel;
2348
2349 ret = ops->write_std(new_tss_base,
2350 &tss_seg.prev_task_link,
2351 sizeof tss_seg.prev_task_link,
2352 ctxt->vcpu, &err);
2353 if (ret == X86EMUL_PROPAGATE_FAULT) {
2354 /* FIXME: need to provide precise fault address */
54b8486f 2355 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2356 return ret;
2357 }
2358 }
2359
2360 return load_state_from_tss16(ctxt, ops, &tss_seg);
2361}
2362
2363static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2364 struct x86_emulate_ops *ops,
2365 struct tss_segment_32 *tss)
2366{
2367 struct decode_cache *c = &ctxt->decode;
2368
2369 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2370 tss->eip = c->eip;
2371 tss->eflags = ctxt->eflags;
2372 tss->eax = c->regs[VCPU_REGS_RAX];
2373 tss->ecx = c->regs[VCPU_REGS_RCX];
2374 tss->edx = c->regs[VCPU_REGS_RDX];
2375 tss->ebx = c->regs[VCPU_REGS_RBX];
2376 tss->esp = c->regs[VCPU_REGS_RSP];
2377 tss->ebp = c->regs[VCPU_REGS_RBP];
2378 tss->esi = c->regs[VCPU_REGS_RSI];
2379 tss->edi = c->regs[VCPU_REGS_RDI];
2380
2381 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2382 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2383 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2384 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2385 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2386 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2387 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2388}
2389
2390static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2391 struct x86_emulate_ops *ops,
2392 struct tss_segment_32 *tss)
2393{
2394 struct decode_cache *c = &ctxt->decode;
2395 int ret;
2396
0f12244f 2397 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2398 emulate_gp(ctxt, 0);
0f12244f
GN		 2399 return X86EMUL_PROPAGATE_FAULT;
2400 }
38ba30ba
GN		 2401 c->eip = tss->eip;
2402 ctxt->eflags = tss->eflags | 2;
2403 c->regs[VCPU_REGS_RAX] = tss->eax;
2404 c->regs[VCPU_REGS_RCX] = tss->ecx;
2405 c->regs[VCPU_REGS_RDX] = tss->edx;
2406 c->regs[VCPU_REGS_RBX] = tss->ebx;
2407 c->regs[VCPU_REGS_RSP] = tss->esp;
2408 c->regs[VCPU_REGS_RBP] = tss->ebp;
2409 c->regs[VCPU_REGS_RSI] = tss->esi;
2410 c->regs[VCPU_REGS_RDI] = tss->edi;
2411
2412 /*
2413 * SDM says that segment selectors are loaded before segment
2414 * descriptors
2415 */
2416 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2417 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2418 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2419 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2420 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2421 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2422 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2423
2424 /*
2425 * Now load segment descriptors. If fault happenes at this stage
2426 * it is handled in a context of new task
2427 */
2428 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2429 if (ret != X86EMUL_CONTINUE)
2430 return ret;
2431 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2432 if (ret != X86EMUL_CONTINUE)
2433 return ret;
2434 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2435 if (ret != X86EMUL_CONTINUE)
2436 return ret;
2437 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2438 if (ret != X86EMUL_CONTINUE)
2439 return ret;
2440 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2441 if (ret != X86EMUL_CONTINUE)
2442 return ret;
2443 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2444 if (ret != X86EMUL_CONTINUE)
2445 return ret;
2446 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2447 if (ret != X86EMUL_CONTINUE)
2448 return ret;
2449
2450 return X86EMUL_CONTINUE;
2451}
2452
2453static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2454 struct x86_emulate_ops *ops,
2455 u16 tss_selector, u16 old_tss_sel,
2456 ulong old_tss_base, struct desc_struct *new_desc)
2457{
2458 struct tss_segment_32 tss_seg;
2459 int ret;
2460 u32 err, new_tss_base = get_desc_base(new_desc);
2461
2462 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2463 &err);
2464 if (ret == X86EMUL_PROPAGATE_FAULT) {
2465 /* FIXME: need to provide precise fault address */
54b8486f 2466 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2467 return ret;
2468 }
2469
2470 save_state_to_tss32(ctxt, ops, &tss_seg);
2471
2472 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2473 &err);
2474 if (ret == X86EMUL_PROPAGATE_FAULT) {
2475 /* FIXME: need to provide precise fault address */
54b8486f 2476 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2477 return ret;
2478 }
2479
2480 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2481 &err);
2482 if (ret == X86EMUL_PROPAGATE_FAULT) {
2483 /* FIXME: need to provide precise fault address */
54b8486f 2484 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2485 return ret;
2486 }
2487
2488 if (old_tss_sel != 0xffff) {
2489 tss_seg.prev_task_link = old_tss_sel;
2490
2491 ret = ops->write_std(new_tss_base,
2492 &tss_seg.prev_task_link,
2493 sizeof tss_seg.prev_task_link,
2494 ctxt->vcpu, &err);
2495 if (ret == X86EMUL_PROPAGATE_FAULT) {
2496 /* FIXME: need to provide precise fault address */
54b8486f 2497 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2498 return ret;
2499 }
2500 }
2501
2502 return load_state_from_tss32(ctxt, ops, &tss_seg);
2503}
2504
2505static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2506 struct x86_emulate_ops *ops,
2507 u16 tss_selector, int reason,
2508 bool has_error_code, u32 error_code)
38ba30ba
GN		 2509{
2510 struct desc_struct curr_tss_desc, next_tss_desc;
2511 int ret;
2512 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2513 ulong old_tss_base =
5951c442 2514 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2515 u32 desc_limit;
38ba30ba
GN		 2516
2517 /* FIXME: old_tss_base == ~0 ? */
2518
2519 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2520 if (ret != X86EMUL_CONTINUE)
2521 return ret;
2522 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2523 if (ret != X86EMUL_CONTINUE)
2524 return ret;
2525
2526 /* FIXME: check that next_tss_desc is tss */
2527
2528 if (reason != TASK_SWITCH_IRET) {
2529 if ((tss_selector & 3) > next_tss_desc.dpl ||
2530 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2531 emulate_gp(ctxt, 0);
38ba30ba
GN		 2532 return X86EMUL_PROPAGATE_FAULT;
2533 }
2534 }
2535
ceffb459
GN		 2536 desc_limit = desc_limit_scaled(&next_tss_desc);
2537 if (!next_tss_desc.p ||
2538 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2539 desc_limit < 0x2b)) {
54b8486f 2540 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2541 return X86EMUL_PROPAGATE_FAULT;
2542 }
2543
2544 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2545 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2546 write_segment_descriptor(ctxt, ops, old_tss_sel,
2547 &curr_tss_desc);
2548 }
2549
2550 if (reason == TASK_SWITCH_IRET)
2551 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2552
2553 /* set back link to prev task only if NT bit is set in eflags
2554 note that old_tss_sel is not used afetr this point */
2555 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2556 old_tss_sel = 0xffff;
2557
2558 if (next_tss_desc.type & 8)
2559 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2560 old_tss_base, &next_tss_desc);
2561 else
2562 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2563 old_tss_base, &next_tss_desc);
0760d448
JK		 2564 if (ret != X86EMUL_CONTINUE)
2565 return ret;
38ba30ba
GN		 2566
2567 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2568 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2569
2570 if (reason != TASK_SWITCH_IRET) {
2571 next_tss_desc.type |= (1 << 1); /* set busy flag */
2572 write_segment_descriptor(ctxt, ops, tss_selector,
2573 &next_tss_desc);
2574 }
2575
2576 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2577 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2578 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2579
e269fb21
JK		 2580 if (has_error_code) {
2581 struct decode_cache *c = &ctxt->decode;
2582
2583 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2584 c->lock_prefix = 0;
2585 c->src.val = (unsigned long) error_code;
79168fd1 2586 emulate_push(ctxt, ops);
e269fb21
JK		 2587 }
2588
38ba30ba
GN		 2589 return ret;
2590}
2591
2592int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2593 struct x86_emulate_ops *ops,
e269fb21
JK		 2594 u16 tss_selector, int reason,
2595 bool has_error_code, u32 error_code)
38ba30ba
GN		 2596{
2597 struct decode_cache *c = &ctxt->decode;
2598 int rc;
2599
38ba30ba 2600 c->eip = ctxt->eip;
e269fb21 2601 c->dst.type = OP_NONE;
38ba30ba 2602
e269fb21
JK		 2603 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2604 has_error_code, error_code);
38ba30ba
GN		 2605
2606 if (rc == X86EMUL_CONTINUE) {
e269fb21 2607 rc = writeback(ctxt, ops);
95c55886
GN		 2608 if (rc == X86EMUL_CONTINUE)
2609 ctxt->eip = c->eip;
38ba30ba
GN		 2610 }
2611
19d04437 2612 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2613}
2614
a682e354 2615static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2616 int reg, struct operand *op)
a682e354
GN		 2617{
2618 struct decode_cache *c = &ctxt->decode;
2619 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2620
d9271123
GN		 2621 register_address_increment(c, &c->regs[reg], df * op->bytes);
2622 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2623}
2624
8b4caf66 2625int
1be3aa47 2626x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2627{
8b4caf66 2628 u64 msr_data;
8b4caf66 2629 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2630 int rc = X86EMUL_CONTINUE;
5cd21917 2631 int saved_dst_type = c->dst.type;
8b4caf66 2632
9de41573 2633 ctxt->decode.mem_read.pos = 0;
310b5d30 2634
1161624f 2635 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2636 emulate_ud(ctxt);
1161624f
GN		 2637 goto done;
2638 }
2639
d380a5e4 2640 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2641 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2642 emulate_ud(ctxt);
d380a5e4
GN		 2643 goto done;
2644 }
2645
e92805ac 2646 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2647 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2648 emulate_gp(ctxt, 0);
e92805ac
GN		 2649 goto done;
2650 }
2651
b9fa9d6b 2652 if (c->rep_prefix && (c->d & String)) {
5cd21917 2653 ctxt->restart = true;
b9fa9d6b 2654 /* All REP prefixes have the same first termination condition */
c73e197b 2655 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2656 string_done:
2657 ctxt->restart = false;
95c55886 2658 ctxt->eip = c->eip;
b9fa9d6b
AK		 2659 goto done;
2660 }
2661 /* The second termination condition only applies for REPE
2662 * and REPNE. Test if the repeat string operation prefix is
2663 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2664 * corresponding termination condition according to:
2665 * - if REPE/REPZ and ZF = 0 then done
2666 * - if REPNE/REPNZ and ZF = 1 then done
2667 */
2668 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2669 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2670 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2671 ((ctxt->eflags & EFLG_ZF) == 0))
2672 goto string_done;
b9fa9d6b 2673 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2674 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2675 goto string_done;
b9fa9d6b 2676 }
063db061 2677 c->eip = ctxt->eip;
b9fa9d6b
AK		 2678 }
2679
8b4caf66 2680 if (c->src.type == OP_MEM) {
9de41573 2681 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2682 c->src.valptr, c->src.bytes);
b60d513c 2683 if (rc != X86EMUL_CONTINUE)
8b4caf66 2684 goto done;
16518d5a 2685 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2686 }
2687
e35b7b9c 2688 if (c->src2.type == OP_MEM) {
9de41573
GN		 2689 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2690 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2691 if (rc != X86EMUL_CONTINUE)
2692 goto done;
2693 }
2694
8b4caf66
LV		 2695 if ((c->d & DstMask) == ImplicitOps)
2696 goto special_insn;
2697
2698
69f55cb1
GN		 2699 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2700 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2701 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2702 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2703 if (rc != X86EMUL_CONTINUE)
2704 goto done;
038e51de 2705 }
e4e03ded 2706 c->dst.orig_val = c->dst.val;
038e51de 2707
018a98db
AK		 2708special_insn:
2709
e4e03ded 2710 if (c->twobyte)
6aa8b732
AK		 2711 goto twobyte_insn;
2712
e4e03ded 2713 switch (c->b) {
6aa8b732
AK		 2714 case 0x00 ... 0x05:
2715 add: /* add */
05f086f8 2716 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2717 break;
0934ac9d 2718 case 0x06: /* push es */
79168fd1 2719 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2720 break;
2721 case 0x07: /* pop es */
0934ac9d 2722 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2723 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2724 goto done;
2725 break;
6aa8b732
AK		 2726 case 0x08 ... 0x0d:
2727 or: /* or */
05f086f8 2728 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2729 break;
0934ac9d 2730 case 0x0e: /* push cs */
79168fd1 2731 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2732 break;
6aa8b732
AK		 2733 case 0x10 ... 0x15:
2734 adc: /* adc */
05f086f8 2735 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2736 break;
0934ac9d 2737 case 0x16: /* push ss */
79168fd1 2738 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2739 break;
2740 case 0x17: /* pop ss */
0934ac9d 2741 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2742 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2743 goto done;
2744 break;
6aa8b732
AK		 2745 case 0x18 ... 0x1d:
2746 sbb: /* sbb */
05f086f8 2747 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2748 break;
0934ac9d 2749 case 0x1e: /* push ds */
79168fd1 2750 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2751 break;
2752 case 0x1f: /* pop ds */
0934ac9d 2753 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2754 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2755 goto done;
2756 break;
aa3a816b 2757 case 0x20 ... 0x25:
6aa8b732 2758 and: /* and */
05f086f8 2759 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2760 break;
2761 case 0x28 ... 0x2d:
2762 sub: /* sub */
05f086f8 2763 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2764 break;
2765 case 0x30 ... 0x35:
2766 xor: /* xor */
05f086f8 2767 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2768 break;
2769 case 0x38 ... 0x3d:
2770 cmp: /* cmp */
05f086f8 2771 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2772 break;
33615aa9
AK		 2773 case 0x40 ... 0x47: /* inc r16/r32 */
2774 emulate_1op("inc", c->dst, ctxt->eflags);
2775 break;
2776 case 0x48 ... 0x4f: /* dec r16/r32 */
2777 emulate_1op("dec", c->dst, ctxt->eflags);
2778 break;
2779 case 0x50 ... 0x57: /* push reg */
79168fd1 2780 emulate_push(ctxt, ops);
33615aa9
AK		 2781 break;
2782 case 0x58 ... 0x5f: /* pop reg */
2783 pop_instruction:
350f69dc 2784 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2785 if (rc != X86EMUL_CONTINUE)
33615aa9 2786 goto done;
33615aa9 2787 break;
abcf14b5 2788 case 0x60: /* pusha */
c37eda13
WY		 2789 rc = emulate_pusha(ctxt, ops);
2790 if (rc != X86EMUL_CONTINUE)
2791 goto done;
abcf14b5
MG		 2792 break;
2793 case 0x61: /* popa */
2794 rc = emulate_popa(ctxt, ops);
1b30eaa8 2795 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2796 goto done;
2797 break;
6aa8b732 2798 case 0x63: /* movsxd */
8b4caf66 2799 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2800 goto cannot_emulate;
e4e03ded 2801 c->dst.val = (s32) c->src.val;
6aa8b732 2802 break;
91ed7a0e 2803 case 0x68: /* push imm */
018a98db 2804 case 0x6a: /* push imm8 */
79168fd1 2805 emulate_push(ctxt, ops);
018a98db
AK		 2806 break;
2807 case 0x6c: /* insb */
2808 case 0x6d: /* insw/insd */
7972995b 2809 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2810 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2811 c->dst.bytes)) {
54b8486f 2812 emulate_gp(ctxt, 0);
f850e2e6
GN		 2813 goto done;
2814 }
7b262e90
GN		 2815 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2816 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2817 goto done; /* IO is needed, skip writeback */
2818 break;
018a98db
AK		 2819 case 0x6e: /* outsb */
2820 case 0x6f: /* outsw/outsd */
7972995b 2821 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2822 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2823 c->src.bytes)) {
54b8486f 2824 emulate_gp(ctxt, 0);
f850e2e6
GN		 2825 goto done;
2826 }
7972995b
GN		 2827 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2828 &c->src.val, 1, ctxt->vcpu);
2829
2830 c->dst.type = OP_NONE; /* nothing to writeback */
2831 break;
b2833e3c 2832 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2833 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2834 jmp_rel(c, c->src.val);
018a98db 2835 break;
6aa8b732 2836 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2837 switch (c->modrm_reg) {
6aa8b732
AK		 2838 case 0:
2839 goto add;
2840 case 1:
2841 goto or;
2842 case 2:
2843 goto adc;
2844 case 3:
2845 goto sbb;
2846 case 4:
2847 goto and;
2848 case 5:
2849 goto sub;
2850 case 6:
2851 goto xor;
2852 case 7:
2853 goto cmp;
2854 }
2855 break;
2856 case 0x84 ... 0x85:
dfb507c4 2857 test:
05f086f8 2858 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2859 break;
2860 case 0x86 ... 0x87: /* xchg */
b13354f8 2861 xchg:
6aa8b732 2862 /* Write back the register source. */
e4e03ded 2863 switch (c->dst.bytes) {
6aa8b732 2864 case 1:
e4e03ded 2865 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2866 break;
2867 case 2:
e4e03ded 2868 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2869 break;
2870 case 4:
e4e03ded 2871 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2872 break; /* 64b reg: zero-extend */
2873 case 8:
e4e03ded 2874 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2875 break;
2876 }
2877 /*
2878 * Write back the memory destination with implicit LOCK
2879 * prefix.
2880 */
e4e03ded
LV		 2881 c->dst.val = c->src.val;
2882 c->lock_prefix = 1;
6aa8b732 2883 break;
6aa8b732 2884 case 0x88 ... 0x8b: /* mov */
7de75248 2885 goto mov;
79168fd1
GN		 2886 case 0x8c: /* mov r/m, sreg */
2887 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2888 emulate_ud(ctxt);
5e3ae6c5 2889 goto done;
38d5bc6d 2890 }
79168fd1 2891 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2892 break;
7e0b54b1 2893 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2894 c->dst.val = c->modrm_ea;
7e0b54b1 2895 break;
4257198a
GT		 2896 case 0x8e: { /* mov seg, r/m16 */
2897 uint16_t sel;
4257198a
GT		 2898
2899 sel = c->src.val;
8b9f4414 2900
c697518a
GN		 2901 if (c->modrm_reg == VCPU_SREG_CS ||
2902 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2903 emulate_ud(ctxt);
8b9f4414
GN		 2904 goto done;
2905 }
2906
310b5d30 2907 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2908 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2909
2e873022 2910 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2911
2912 c->dst.type = OP_NONE; /* Disable writeback. */
2913 break;
2914 }
6aa8b732 2915 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2916 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2917 if (rc != X86EMUL_CONTINUE)
6aa8b732 2918 goto done;
6aa8b732 2919 break;
b13354f8 2920 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2921 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2922 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2923 break;
2924 }
2925 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2926 c->src.type = OP_REG;
2927 c->src.bytes = c->op_bytes;
b13354f8
MG		 2928 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2929 c->src.val = *(c->src.ptr);
2930 goto xchg;
fd2a7608 2931 case 0x9c: /* pushf */
05f086f8 2932 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2933 emulate_push(ctxt, ops);
8cdbd2c9 2934 break;
535eabcf 2935 case 0x9d: /* popf */
2b48cc75 2936 c->dst.type = OP_REG;
05f086f8 2937 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2938 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2939 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2940 if (rc != X86EMUL_CONTINUE)
2941 goto done;
2942 break;
5d55f299 2943 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2944 case 0xa4 ... 0xa5: /* movs */
a682e354 2945 goto mov;
6aa8b732 2946 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2947 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2948 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2949 goto cmp;
dfb507c4
MG		 2950 case 0xa8 ... 0xa9: /* test ax, imm */
2951 goto test;
6aa8b732 2952 case 0xaa ... 0xab: /* stos */
e4e03ded 2953 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2954 break;
2955 case 0xac ... 0xad: /* lods */
a682e354 2956 goto mov;
6aa8b732
AK		 2957 case 0xae ... 0xaf: /* scas */
2958 DPRINTF("Urk! I don't handle SCAS.\n");
2959 goto cannot_emulate;
a5e2e82b 2960 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2961 goto mov;
018a98db
AK		 2962 case 0xc0 ... 0xc1:
2963 emulate_grp2(ctxt);
2964 break;
111de5d6 2965 case 0xc3: /* ret */
cf5de4f8 2966 c->dst.type = OP_REG;
111de5d6 2967 c->dst.ptr = &c->eip;
cf5de4f8 2968 c->dst.bytes = c->op_bytes;
111de5d6 2969 goto pop_instruction;
018a98db
AK		 2970 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2971 mov:
2972 c->dst.val = c->src.val;
2973 break;
a77ab5ea
AK		 2974 case 0xcb: /* ret far */
2975 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2976 if (rc != X86EMUL_CONTINUE)
2977 goto done;
2978 break;
2979 case 0xcf: /* iret */
2980 rc = emulate_iret(ctxt, ops);
2981
1b30eaa8 2982 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2983 goto done;
2984 break;
018a98db
AK		 2985 case 0xd0 ... 0xd1: /* Grp2 */
2986 c->src.val = 1;
2987 emulate_grp2(ctxt);
2988 break;
2989 case 0xd2 ... 0xd3: /* Grp2 */
2990 c->src.val = c->regs[VCPU_REGS_RCX];
2991 emulate_grp2(ctxt);
2992 break;
a6a3034c
MG		 2993 case 0xe4: /* inb */
2994 case 0xe5: /* in */
cf8f70bf 2995 goto do_io_in;
a6a3034c
MG		 2996 case 0xe6: /* outb */
2997 case 0xe7: /* out */
cf8f70bf 2998 goto do_io_out;
1a52e051 2999 case 0xe8: /* call (near) */ {
d53c4777 3000 long int rel = c->src.val;
e4e03ded 3001 c->src.val = (unsigned long) c->eip;
7a957275 3002 jmp_rel(c, rel);
79168fd1 3003 emulate_push(ctxt, ops);
8cdbd2c9 3004 break;
1a52e051
NK		 3005 }
3006 case 0xe9: /* jmp rel */
954cd36f 3007 goto jmp;
414e6277
GN		 3008 case 0xea: { /* jmp far */
3009 unsigned short sel;
ea79849d 3010 jump_far:
414e6277
GN		 3011 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3012
3013 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3014 goto done;
954cd36f 3015
414e6277
GN		 3016 c->eip = 0;
3017 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3018 break;
414e6277 3019 }
954cd36f
GT		 3020 case 0xeb:
3021 jmp: /* jmp rel short */
7a957275 3022 jmp_rel(c, c->src.val);
a01af5ec 3023 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3024 break;
a6a3034c
MG		 3025 case 0xec: /* in al,dx */
3026 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3027 c->src.val = c->regs[VCPU_REGS_RDX];
3028 do_io_in:
3029 c->dst.bytes = min(c->dst.bytes, 4u);
3030 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3031 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3032 goto done;
3033 }
7b262e90
GN		 3034 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3035 &c->dst.val))
cf8f70bf
GN		 3036 goto done; /* IO is needed */
3037 break;
ce7a0ad3
WY		 3038 case 0xee: /* out dx,al */
3039 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3040 c->src.val = c->regs[VCPU_REGS_RDX];
3041 do_io_out:
3042 c->dst.bytes = min(c->dst.bytes, 4u);
3043 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3044 emulate_gp(ctxt, 0);
f850e2e6
GN		 3045 goto done;
3046 }
cf8f70bf
GN		 3047 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3048 ctxt->vcpu);
3049 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3050 break;
111de5d6 3051 case 0xf4: /* hlt */
ad312c7c 3052 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3053 break;
111de5d6
AK		 3054 case 0xf5: /* cmc */
3055 /* complement carry flag from eflags reg */
3056 ctxt->eflags ^= EFLG_CF;
3057 c->dst.type = OP_NONE; /* Disable writeback. */
3058 break;
018a98db 3059 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3060 if (!emulate_grp3(ctxt, ops))
3061 goto cannot_emulate;
018a98db 3062 break;
111de5d6
AK		 3063 case 0xf8: /* clc */
3064 ctxt->eflags &= ~EFLG_CF;
3065 c->dst.type = OP_NONE; /* Disable writeback. */
3066 break;
3067 case 0xfa: /* cli */
07cbc6c1 3068 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3069 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3070 goto done;
3071 } else {
f850e2e6
GN		 3072 ctxt->eflags &= ~X86_EFLAGS_IF;
3073 c->dst.type = OP_NONE; /* Disable writeback. */
3074 }
111de5d6
AK		 3075 break;
3076 case 0xfb: /* sti */
07cbc6c1 3077 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3078 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3079 goto done;
3080 } else {
95cb2295 3081 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3082 ctxt->eflags |= X86_EFLAGS_IF;
3083 c->dst.type = OP_NONE; /* Disable writeback. */
3084 }
111de5d6 3085 break;
fb4616f4
MG		 3086 case 0xfc: /* cld */
3087 ctxt->eflags &= ~EFLG_DF;
3088 c->dst.type = OP_NONE; /* Disable writeback. */
3089 break;
3090 case 0xfd: /* std */
3091 ctxt->eflags |= EFLG_DF;
3092 c->dst.type = OP_NONE; /* Disable writeback. */
3093 break;
ea79849d
GN		 3094 case 0xfe: /* Grp4 */
3095 grp45:
018a98db 3096 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3097 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3098 goto done;
3099 break;
ea79849d
GN		 3100 case 0xff: /* Grp5 */
3101 if (c->modrm_reg == 5)
3102 goto jump_far;
3103 goto grp45;
91269b8f
AK		 3104 default:
3105 goto cannot_emulate;
6aa8b732 3106 }
018a98db
AK		 3107
3108writeback:
3109 rc = writeback(ctxt, ops);
1b30eaa8 3110 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3111 goto done;
3112
5cd21917
GN		 3113 /*
3114 * restore dst type in case the decoding will be reused
3115 * (happens for string instruction )
3116 */
3117 c->dst.type = saved_dst_type;
3118
a682e354 3119 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3120 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3121 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3122
3123 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3124 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3125 &c->dst);
d9271123 3126
5cd21917 3127 if (c->rep_prefix && (c->d & String)) {
7b262e90 3128 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3129 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3130 /*
3131 * Re-enter guest when pio read ahead buffer is empty or,
3132 * if it is not used, after each 1024 iteration.
3133 */
3134 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3135 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3136 ctxt->restart = false;
3137 }
9de41573
GN		 3138 /*
3139 * reset read cache here in case string instruction is restared
3140 * without decoding
3141 */
3142 ctxt->decode.mem_read.end = 0;
95c55886 3143 ctxt->eip = c->eip;
018a98db
AK		 3144
3145done:
cb404fe0 3146 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3147
3148twobyte_insn:
e4e03ded 3149 switch (c->b) {
6aa8b732 3150 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3151 switch (c->modrm_reg) {
6aa8b732
AK		 3152 u16 size;
3153 unsigned long address;
3154
aca7f966 3155 case 0: /* vmcall */
e4e03ded 3156 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3157 goto cannot_emulate;
3158
7aa81cc0 3159 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3160 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3161 goto done;
3162
33e3885d 3163 /* Let the processor re-execute the fixed hypercall */
063db061 3164 c->eip = ctxt->eip;
16286d08
AK		 3165 /* Disable writeback. */
3166 c->dst.type = OP_NONE;
aca7f966 3167 break;
6aa8b732 3168 case 2: /* lgdt */
e4e03ded
LV		 3169 rc = read_descriptor(ctxt, ops, c->src.ptr,
3170 &size, &address, c->op_bytes);
1b30eaa8 3171 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3172 goto done;
3173 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3174 /* Disable writeback. */
3175 c->dst.type = OP_NONE;
6aa8b732 3176 break;
aca7f966 3177 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3178 if (c->modrm_mod == 3) {
3179 switch (c->modrm_rm) {
3180 case 1:
3181 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3182 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3183 goto done;
3184 break;
3185 default:
3186 goto cannot_emulate;
3187 }
aca7f966 3188 } else {
e4e03ded 3189 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3190 &size, &address,
e4e03ded 3191 c->op_bytes);
1b30eaa8 3192 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3193 goto done;
3194 realmode_lidt(ctxt->vcpu, size, address);
3195 }
16286d08
AK		 3196 /* Disable writeback. */
3197 c->dst.type = OP_NONE;
6aa8b732
AK		 3198 break;
3199 case 4: /* smsw */
16286d08 3200 c->dst.bytes = 2;
52a46617 3201 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3202 break;
3203 case 6: /* lmsw */
93a152be
GN		 3204 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3205 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3206 c->dst.type = OP_NONE;
6aa8b732 3207 break;
6e1e5ffe 3208 case 5: /* not defined */
54b8486f 3209 emulate_ud(ctxt);
6e1e5ffe 3210 goto done;
6aa8b732 3211 case 7: /* invlpg*/
69f55cb1 3212 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3213 /* Disable writeback. */
3214 c->dst.type = OP_NONE;
6aa8b732
AK		 3215 break;
3216 default:
3217 goto cannot_emulate;
3218 }
3219 break;
e99f0507 3220 case 0x05: /* syscall */
3fb1b5db 3221 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3222 if (rc != X86EMUL_CONTINUE)
3223 goto done;
e66bb2cc
AP		 3224 else
3225 goto writeback;
e99f0507 3226 break;
018a98db
AK		 3227 case 0x06:
3228 emulate_clts(ctxt->vcpu);
3229 c->dst.type = OP_NONE;
3230 break;
018a98db 3231 case 0x09: /* wbinvd */
f5f48ee1
SY		 3232 kvm_emulate_wbinvd(ctxt->vcpu);
3233 c->dst.type = OP_NONE;
3234 break;
3235 case 0x08: /* invd */
018a98db
AK		 3236 case 0x0d: /* GrpP (prefetch) */
3237 case 0x18: /* Grp16 (prefetch/nop) */
3238 c->dst.type = OP_NONE;
3239 break;
3240 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3241 switch (c->modrm_reg) {
3242 case 1:
3243 case 5 ... 7:
3244 case 9 ... 15:
54b8486f 3245 emulate_ud(ctxt);
6aebfa6e
GN		 3246 goto done;
3247 }
52a46617 3248 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3249 c->dst.type = OP_NONE; /* no writeback */
3250 break;
6aa8b732 3251 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3252 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3253 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3254 emulate_ud(ctxt);
1e470be5
GN		 3255 goto done;
3256 }
35aa5375 3257 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3258 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3259 break;
018a98db 3260 case 0x22: /* mov reg, cr */
0f12244f 3261 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3262 emulate_gp(ctxt, 0);
0f12244f
GN		 3263 goto done;
3264 }
018a98db
AK		 3265 c->dst.type = OP_NONE;
3266 break;
6aa8b732 3267 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3268 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3269 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3270 emulate_ud(ctxt);
1e470be5
GN		 3271 goto done;
3272 }
35aa5375 3273
338dbc97
GN		 3274 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3275 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3276 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3277 /* #UD condition is already handled by the code above */
54b8486f 3278 emulate_gp(ctxt, 0);
338dbc97
GN		 3279 goto done;
3280 }
3281
a01af5ec 3282 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3283 break;
018a98db
AK		 3284 case 0x30:
3285 /* wrmsr */
3286 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3287 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3288 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3289 emulate_gp(ctxt, 0);
fd525365 3290 goto done;
018a98db
AK		 3291 }
3292 rc = X86EMUL_CONTINUE;
3293 c->dst.type = OP_NONE;
3294 break;
3295 case 0x32:
3296 /* rdmsr */
3fb1b5db 3297 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3298 emulate_gp(ctxt, 0);
fd525365 3299 goto done;
018a98db
AK		 3300 } else {
3301 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3302 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3303 }
3304 rc = X86EMUL_CONTINUE;
3305 c->dst.type = OP_NONE;
3306 break;
e99f0507 3307 case 0x34: /* sysenter */
3fb1b5db 3308 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3309 if (rc != X86EMUL_CONTINUE)
3310 goto done;
8c604352
AP		 3311 else
3312 goto writeback;
e99f0507
AP		 3313 break;
3314 case 0x35: /* sysexit */
3fb1b5db 3315 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3316 if (rc != X86EMUL_CONTINUE)
3317 goto done;
4668f050
AP		 3318 else
3319 goto writeback;
e99f0507 3320 break;
6aa8b732 3321 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3322 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3323 if (!test_cc(c->b, ctxt->eflags))
3324 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3325 break;
b2833e3c 3326 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3327 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3328 jmp_rel(c, c->src.val);
018a98db
AK		 3329 c->dst.type = OP_NONE;
3330 break;
0934ac9d 3331 case 0xa0: /* push fs */
79168fd1 3332 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3333 break;
3334 case 0xa1: /* pop fs */
3335 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3336 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3337 goto done;
3338 break;
7de75248
NK		 3339 case 0xa3:
3340 bt: /* bt */
e4f8e039 3341 c->dst.type = OP_NONE;
e4e03ded
LV		 3342 /* only subword offset */
3343 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3344 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3345 break;
9bf8ea42
GT		 3346 case 0xa4: /* shld imm8, r, r/m */
3347 case 0xa5: /* shld cl, r, r/m */
3348 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3349 break;
0934ac9d 3350 case 0xa8: /* push gs */
79168fd1 3351 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3352 break;
3353 case 0xa9: /* pop gs */
3354 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3355 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3356 goto done;
3357 break;
7de75248
NK		 3358 case 0xab:
3359 bts: /* bts */
e4e03ded
LV		 3360 /* only subword offset */
3361 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3362 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3363 break;
9bf8ea42
GT		 3364 case 0xac: /* shrd imm8, r, r/m */
3365 case 0xad: /* shrd cl, r, r/m */
3366 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3367 break;
2a7c5b8b
GC		 3368 case 0xae: /* clflush */
3369 break;
6aa8b732
AK		 3370 case 0xb0 ... 0xb1: /* cmpxchg */
3371 /*
3372 * Save real source value, then compare EAX against
3373 * destination.
3374 */
e4e03ded
LV		 3375 c->src.orig_val = c->src.val;
3376 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3377 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3378 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3379 /* Success: write back to memory. */
e4e03ded 3380 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3381 } else {
3382 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3383 c->dst.type = OP_REG;
3384 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3385 }
3386 break;
6aa8b732
AK		 3387 case 0xb3:
3388 btr: /* btr */
e4e03ded
LV		 3389 /* only subword offset */
3390 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3391 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3392 break;
6aa8b732 3393 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3394 c->dst.bytes = c->op_bytes;
3395 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3396 : (u16) c->src.val;
6aa8b732 3397 break;
6aa8b732 3398 case 0xba: /* Grp8 */
e4e03ded 3399 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3400 case 0:
3401 goto bt;
3402 case 1:
3403 goto bts;
3404 case 2:
3405 goto btr;
3406 case 3:
3407 goto btc;
3408 }
3409 break;
7de75248
NK		 3410 case 0xbb:
3411 btc: /* btc */
e4e03ded
LV		 3412 /* only subword offset */
3413 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3414 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3415 break;
6aa8b732 3416 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3417 c->dst.bytes = c->op_bytes;
3418 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3419 (s16) c->src.val;
6aa8b732 3420 break;
a012e65a 3421 case 0xc3: /* movnti */
e4e03ded
LV		 3422 c->dst.bytes = c->op_bytes;
3423 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3424 (u64) c->src.val;
a012e65a 3425 break;
6aa8b732 3426 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3427 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3428 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3429 goto done;
3430 break;
91269b8f
AK		 3431 default:
3432 goto cannot_emulate;
6aa8b732
AK		 3433 }
3434 goto writeback;
3435
3436cannot_emulate:
e4e03ded 3437 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3438 return -1;
3439}
Linux kernel - Deliverables
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