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Linux 3.16-rc1
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
6aa8b732 165
820207c8 166#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 167
d0e53325
AK		 168#define X2(x...) x, x
169#define X3(x...) X2(x), x
170#define X4(x...) X2(x), X2(x)
171#define X5(x...) X4(x), x
172#define X6(x...) X4(x), X2(x)
173#define X7(x...) X4(x), X3(x)
174#define X8(x...) X4(x), X4(x)
175#define X16(x...) X8(x), X8(x)
83babbca 176
e28bbd44
AK		 177#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
178#define FASTOP_SIZE 8
179
180/*
181 * fastop functions have a special calling convention:
182 *
017da7b6
AK		 183 * dst: rax (in/out)
184 * src: rdx (in/out)
e28bbd44
AK		 185 * src2: rcx (in)
186 * flags: rflags (in/out)
b8c0b6ae 187 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 188 *
189 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
190 * different operand sizes can be reached by calculation, rather than a jump
191 * table (which would be bigger than the code).
192 *
193 * fastop functions are declared as taking a never-defined fastop parameter,
194 * so they can't be called from C directly.
195 */
196
197struct fastop;
198
d65b1dee 199struct opcode {
b1ea50b2
AK		 200 u64 flags : 56;
201 u64 intercept : 8;
120df890 202 union {
ef65c889 203 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 204 const struct opcode *group;
205 const struct group_dual *gdual;
206 const struct gprefix *gprefix;
045a282c 207 const struct escape *esc;
e28bbd44 208 void (*fastop)(struct fastop *fake);
120df890 209 } u;
d09beabd 210 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 211};
212
213struct group_dual {
214 struct opcode mod012[8];
215 struct opcode mod3[8];
d65b1dee
AK		 216};
217
0d7cdee8
AK		 218struct gprefix {
219 struct opcode pfx_no;
220 struct opcode pfx_66;
221 struct opcode pfx_f2;
222 struct opcode pfx_f3;
223};
224
045a282c
GN		 225struct escape {
226 struct opcode op[8];
227 struct opcode high[64];
228};
229
6aa8b732 230/* EFLAGS bit definitions. */
d4c6a154
GN		 231#define EFLG_ID (1<<21)
232#define EFLG_VIP (1<<20)
233#define EFLG_VIF (1<<19)
234#define EFLG_AC (1<<18)
b1d86143
AP		 235#define EFLG_VM (1<<17)
236#define EFLG_RF (1<<16)
d4c6a154
GN		 237#define EFLG_IOPL (3<<12)
238#define EFLG_NT (1<<14)
6aa8b732
AK		 239#define EFLG_OF (1<<11)
240#define EFLG_DF (1<<10)
b1d86143 241#define EFLG_IF (1<<9)
d4c6a154 242#define EFLG_TF (1<<8)
6aa8b732
AK		 243#define EFLG_SF (1<<7)
244#define EFLG_ZF (1<<6)
245#define EFLG_AF (1<<4)
246#define EFLG_PF (1<<2)
247#define EFLG_CF (1<<0)
248
62bd430e
MG		 249#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
250#define EFLG_RESERVED_ONE_MASK 2
251
dd856efa
AK		 252static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
253{
254 if (!(ctxt->regs_valid & (1 << nr))) {
255 ctxt->regs_valid |= 1 << nr;
256 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
257 }
258 return ctxt->_regs[nr];
259}
260
261static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 ctxt->regs_valid |= 1 << nr;
264 ctxt->regs_dirty |= 1 << nr;
265 return &ctxt->_regs[nr];
266}
267
268static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
269{
270 reg_read(ctxt, nr);
271 return reg_write(ctxt, nr);
272}
273
274static void writeback_registers(struct x86_emulate_ctxt *ctxt)
275{
276 unsigned reg;
277
278 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
279 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
280}
281
282static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
283{
284 ctxt->regs_dirty = 0;
285 ctxt->regs_valid = 0;
286}
287
6aa8b732
AK		 288/*
289 * These EFLAGS bits are restored from saved value during emulation, and
290 * any changes are written back to the saved value after emulation.
291 */
292#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
293
dda96d8f
AK		 294#ifdef CONFIG_X86_64
295#define ON64(x) x
296#else
297#define ON64(x)
298#endif
299
4d758349
AK		 300static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
301
b7d491e7
AK		 302#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
303#define FOP_RET "ret \n\t"
304
305#define FOP_START(op) \
306 extern void em_##op(struct fastop *fake); \
307 asm(".pushsection .text, \"ax\" \n\t" \
308 ".global em_" #op " \n\t" \
309 FOP_ALIGN \
310 "em_" #op ": \n\t"
311
312#define FOP_END \
313 ".popsection")
314
0bdea068
AK		 315#define FOPNOP() FOP_ALIGN FOP_RET
316
b7d491e7 317#define FOP1E(op, dst) \
b8c0b6ae
AK		 318 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
319
320#define FOP1EEX(op, dst) \
321 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 322
323#define FASTOP1(op) \
324 FOP_START(op) \
325 FOP1E(op##b, al) \
326 FOP1E(op##w, ax) \
327 FOP1E(op##l, eax) \
328 ON64(FOP1E(op##q, rax)) \
329 FOP_END
330
b9fa409b
AK		 331/* 1-operand, using src2 (for MUL/DIV r/m) */
332#define FASTOP1SRC2(op, name) \
333 FOP_START(name) \
334 FOP1E(op, cl) \
335 FOP1E(op, cx) \
336 FOP1E(op, ecx) \
337 ON64(FOP1E(op, rcx)) \
338 FOP_END
339
b8c0b6ae
AK		 340/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
341#define FASTOP1SRC2EX(op, name) \
342 FOP_START(name) \
343 FOP1EEX(op, cl) \
344 FOP1EEX(op, cx) \
345 FOP1EEX(op, ecx) \
346 ON64(FOP1EEX(op, rcx)) \
347 FOP_END
348
f7857f35
AK		 349#define FOP2E(op, dst, src) \
350 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
351
352#define FASTOP2(op) \
353 FOP_START(op) \
017da7b6
AK		 354 FOP2E(op##b, al, dl) \
355 FOP2E(op##w, ax, dx) \
356 FOP2E(op##l, eax, edx) \
357 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 358 FOP_END
359
11c363ba
AK		 360/* 2 operand, word only */
361#define FASTOP2W(op) \
362 FOP_START(op) \
363 FOPNOP() \
017da7b6
AK		 364 FOP2E(op##w, ax, dx) \
365 FOP2E(op##l, eax, edx) \
366 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 367 FOP_END
368
007a3b54
AK		 369/* 2 operand, src is CL */
370#define FASTOP2CL(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, cl) \
373 FOP2E(op##w, ax, cl) \
374 FOP2E(op##l, eax, cl) \
375 ON64(FOP2E(op##q, rax, cl)) \
376 FOP_END
377
0bdea068
AK		 378#define FOP3E(op, dst, src, src2) \
379 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
380
381/* 3-operand, word-only, src2=cl */
382#define FASTOP3WCL(op) \
383 FOP_START(op) \
384 FOPNOP() \
017da7b6
AK		 385 FOP3E(op##w, ax, dx, cl) \
386 FOP3E(op##l, eax, edx, cl) \
387 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 388 FOP_END
389
9ae9feba
AK		 390/* Special case for SETcc - 1 instruction per cc */
391#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
392
b8c0b6ae
AK		 393asm(".global kvm_fastop_exception \n"
394 "kvm_fastop_exception: xor %esi, %esi; ret");
395
9ae9feba
AK		 396FOP_START(setcc)
397FOP_SETCC(seto)
398FOP_SETCC(setno)
399FOP_SETCC(setc)
400FOP_SETCC(setnc)
401FOP_SETCC(setz)
402FOP_SETCC(setnz)
403FOP_SETCC(setbe)
404FOP_SETCC(setnbe)
405FOP_SETCC(sets)
406FOP_SETCC(setns)
407FOP_SETCC(setp)
408FOP_SETCC(setnp)
409FOP_SETCC(setl)
410FOP_SETCC(setnl)
411FOP_SETCC(setle)
412FOP_SETCC(setnle)
413FOP_END;
414
326f578f
PB		 415FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
416FOP_END;
417
8a76d7f2
JR		 418static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
419 enum x86_intercept intercept,
420 enum x86_intercept_stage stage)
421{
422 struct x86_instruction_info info = {
423 .intercept = intercept,
9dac77fa
AK		 424 .rep_prefix = ctxt->rep_prefix,
425 .modrm_mod = ctxt->modrm_mod,
426 .modrm_reg = ctxt->modrm_reg,
427 .modrm_rm = ctxt->modrm_rm,
428 .src_val = ctxt->src.val64,
429 .src_bytes = ctxt->src.bytes,
430 .dst_bytes = ctxt->dst.bytes,
431 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 432 .next_rip = ctxt->eip,
433 };
434
2953538e 435 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 436}
437
f47cfa31
AK		 438static void assign_masked(ulong *dest, ulong src, ulong mask)
439{
440 *dest = (*dest & ~mask) | (src & mask);
441}
442
9dac77fa 443static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 444{
9dac77fa 445 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 446}
447
f47cfa31
AK		 448static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
449{
450 u16 sel;
451 struct desc_struct ss;
452
453 if (ctxt->mode == X86EMUL_MODE_PROT64)
454 return ~0UL;
455 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
456 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
457}
458
612e89f0
AK		 459static int stack_size(struct x86_emulate_ctxt *ctxt)
460{
461 return (__fls(stack_mask(ctxt)) + 1) >> 3;
462}
463
6aa8b732 464/* Access/update address held in a register, based on addressing mode. */
e4706772 465static inline unsigned long
9dac77fa 466address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 467{
9dac77fa 468 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 469 return reg;
470 else
9dac77fa 471 return reg & ad_mask(ctxt);
e4706772
HH		 472}
473
474static inline unsigned long
9dac77fa 475register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 476{
9dac77fa 477 return address_mask(ctxt, reg);
e4706772
HH		 478}
479
5ad105e5
AK		 480static void masked_increment(ulong *reg, ulong mask, int inc)
481{
482 assign_masked(reg, *reg + inc, mask);
483}
484
7a957275 485static inline void
9dac77fa 486register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 487{
5ad105e5
AK		 488 ulong mask;
489
9dac77fa 490 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 491 mask = ~0UL;
7a957275 492 else
5ad105e5
AK		 493 mask = ad_mask(ctxt);
494 masked_increment(reg, mask, inc);
495}
496
497static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
498{
dd856efa 499 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 500}
6aa8b732 501
9dac77fa 502static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 503{
9dac77fa 504 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 505}
098c937b 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
9dac77fa 514static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 515{
9dac77fa
AK		 516 ctxt->has_seg_override = true;
517 ctxt->seg_override = seg;
7a5b56df
AK		 518}
519
7b105ca2 520static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 521{
522 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
523 return 0;
524
7b105ca2 525 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 526}
527
9dac77fa 528static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 529{
9dac77fa 530 if (!ctxt->has_seg_override)
7a5b56df
AK		 531 return 0;
532
9dac77fa 533 return ctxt->seg_override;
7a5b56df
AK		 534}
535
35d3d4a1
AK		 536static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
537 u32 error, bool valid)
54b8486f 538{
da9cb575
AK		 539 ctxt->exception.vector = vec;
540 ctxt->exception.error_code = error;
541 ctxt->exception.error_code_valid = valid;
35d3d4a1 542 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 543}
544
3b88e41a
JR		 545static int emulate_db(struct x86_emulate_ctxt *ctxt)
546{
547 return emulate_exception(ctxt, DB_VECTOR, 0, false);
548}
549
35d3d4a1 550static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 551{
35d3d4a1 552 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 553}
554
618ff15d
AK		 555static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
556{
557 return emulate_exception(ctxt, SS_VECTOR, err, true);
558}
559
35d3d4a1 560static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 561{
35d3d4a1 562 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 563}
564
35d3d4a1 565static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 566{
35d3d4a1 567 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 568}
569
34d1f490
AK		 570static int emulate_de(struct x86_emulate_ctxt *ctxt)
571{
35d3d4a1 572 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 573}
574
1253791d
AK		 575static int emulate_nm(struct x86_emulate_ctxt *ctxt)
576{
577 return emulate_exception(ctxt, NM_VECTOR, 0, false);
578}
579
1aa36616
AK		 580static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
581{
582 u16 selector;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
586 return selector;
587}
588
589static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
590 unsigned seg)
591{
592 u16 dummy;
593 u32 base3;
594 struct desc_struct desc;
595
596 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
597 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
598}
599
1c11b376
AK		 600/*
601 * x86 defines three classes of vector instructions: explicitly
602 * aligned, explicitly unaligned, and the rest, which change behaviour
603 * depending on whether they're AVX encoded or not.
604 *
605 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
606 * subject to the same check.
607 */
608static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
609{
610 if (likely(size < 16))
611 return false;
612
613 if (ctxt->d & Aligned)
614 return true;
615 else if (ctxt->d & Unaligned)
616 return false;
617 else if (ctxt->d & Avx)
618 return false;
619 else
620 return true;
621}
622
3d9b938e 623static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 624 struct segmented_address addr,
3d9b938e 625 unsigned size, bool write, bool fetch,
52fd8b44
AK		 626 ulong *linear)
627{
618ff15d
AK		 628 struct desc_struct desc;
629 bool usable;
52fd8b44 630 ulong la;
618ff15d 631 u32 lim;
1aa36616 632 u16 sel;
3a78a4f4 633 unsigned cpl;
52fd8b44 634
7b105ca2 635 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 636 switch (ctxt->mode) {
618ff15d
AK		 637 case X86EMUL_MODE_PROT64:
638 if (((signed long)la << 16) >> 16 != la)
639 return emulate_gp(ctxt, 0);
640 break;
641 default:
1aa36616
AK		 642 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
643 addr.seg);
618ff15d
AK		 644 if (!usable)
645 goto bad;
58b7825b
GN		 646 /* code segment in protected mode or read-only data segment */
647 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
648 || !(desc.type & 2)) && write)
618ff15d
AK		 649 goto bad;
650 /* unreadable code segment */
3d9b938e 651 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 652 goto bad;
653 lim = desc_limit_scaled(&desc);
654 if ((desc.type & 8) || !(desc.type & 4)) {
655 /* expand-up segment */
656 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
657 goto bad;
658 } else {
fc058680 659 /* expand-down segment */
618ff15d
AK		 660 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
661 goto bad;
662 lim = desc.d ? 0xffffffff : 0xffff;
663 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
664 goto bad;
665 }
717746e3 666 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 667 if (!(desc.type & 8)) {
668 /* data segment */
669 if (cpl > desc.dpl)
670 goto bad;
671 } else if ((desc.type & 8) && !(desc.type & 4)) {
672 /* nonconforming code segment */
673 if (cpl != desc.dpl)
674 goto bad;
675 } else if ((desc.type & 8) && (desc.type & 4)) {
676 /* conforming code segment */
677 if (cpl < desc.dpl)
678 goto bad;
679 }
680 break;
681 }
9dac77fa 682 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 683 la &= (u32)-1;
1c11b376
AK		 684 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
685 return emulate_gp(ctxt, 0);
52fd8b44
AK		 686 *linear = la;
687 return X86EMUL_CONTINUE;
618ff15d
AK		 688bad:
689 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 690 return emulate_ss(ctxt, sel);
618ff15d 691 else
0afbe2f8 692 return emulate_gp(ctxt, sel);
52fd8b44
AK		 693}
694
3d9b938e
NE		 695static int linearize(struct x86_emulate_ctxt *ctxt,
696 struct segmented_address addr,
697 unsigned size, bool write,
698 ulong *linear)
699{
700 return __linearize(ctxt, addr, size, write, false, linear);
701}
702
703
3ca3ac4d
AK		 704static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
705 struct segmented_address addr,
706 void *data,
707 unsigned size)
708{
9fa088f4
AK		 709 int rc;
710 ulong linear;
711
83b8795a 712 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 713 if (rc != X86EMUL_CONTINUE)
714 return rc;
0f65dd70 715 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 716}
717
807941b1
TY		 718/*
719 * Fetch the next byte of the instruction being emulated which is pointed to
720 * by ctxt->_eip, then increment ctxt->_eip.
721 *
722 * Also prefetch the remaining bytes of the instruction without crossing page
723 * boundary if they are not in fetch_cache yet.
724 */
725static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 726{
9dac77fa 727 struct fetch_cache *fc = &ctxt->fetch;
62266869 728 int rc;
2fb53ad8 729 int size, cur_size;
62266869 730
807941b1 731 if (ctxt->_eip == fc->end) {
3d9b938e 732 unsigned long linear;
807941b1
TY		 733 struct segmented_address addr = { .seg = VCPU_SREG_CS,
734 .ea = ctxt->_eip };
2fb53ad8 735 cur_size = fc->end - fc->start;
807941b1
TY		 736 size = min(15UL - cur_size,
737 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 738 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 739 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 740 return rc;
ef5d75cc
TY		 741 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
742 size, &ctxt->exception);
7d88bb48 743 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 744 return rc;
2fb53ad8 745 fc->end += size;
62266869 746 }
807941b1
TY		 747 *dest = fc->data[ctxt->_eip - fc->start];
748 ctxt->_eip++;
3e2815e9 749 return X86EMUL_CONTINUE;
62266869
AK		 750}
751
752static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 753 void *dest, unsigned size)
62266869 754{
3e2815e9 755 int rc;
62266869 756
eb3c79e6 757 /* x86 instructions are limited to 15 bytes. */
7d88bb48 758 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 759 return X86EMUL_UNHANDLEABLE;
62266869 760 while (size--) {
807941b1 761 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 762 if (rc != X86EMUL_CONTINUE)
62266869
AK		 763 return rc;
764 }
3e2815e9 765 return X86EMUL_CONTINUE;
62266869
AK		 766}
767
67cbc90d 768/* Fetch next part of the instruction being emulated. */
e85a1085 769#define insn_fetch(_type, _ctxt) \
67cbc90d 770({ unsigned long _x; \
e85a1085 771 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 772 if (rc != X86EMUL_CONTINUE) \
773 goto done; \
67cbc90d
TY		 774 (_type)_x; \
775})
776
807941b1
TY		 777#define insn_fetch_arr(_arr, _size, _ctxt) \
778({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 779 if (rc != X86EMUL_CONTINUE) \
780 goto done; \
67cbc90d
TY		 781})
782
1e3c5cb0
RR		 783/*
784 * Given the 'reg' portion of a ModRM byte, and a register block, return a
785 * pointer into the block that addresses the relevant register.
786 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
787 */
dd856efa 788static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 789 int byteop)
6aa8b732
AK		 790{
791 void *p;
aa9ac1a6 792 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 793
6aa8b732 794 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 795 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
796 else
797 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 798 return p;
799}
800
801static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 802 struct segmented_address addr,
6aa8b732
AK		 803 u16 *size, unsigned long *address, int op_bytes)
804{
805 int rc;
806
807 if (op_bytes == 2)
808 op_bytes = 3;
809 *address = 0;
3ca3ac4d 810 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 811 if (rc != X86EMUL_CONTINUE)
6aa8b732 812 return rc;
30b31ab6 813 addr.ea += 2;
3ca3ac4d 814 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 815 return rc;
816}
817
34b77652
AK		 818FASTOP2(add);
819FASTOP2(or);
820FASTOP2(adc);
821FASTOP2(sbb);
822FASTOP2(and);
823FASTOP2(sub);
824FASTOP2(xor);
825FASTOP2(cmp);
826FASTOP2(test);
827
b9fa409b
AK		 828FASTOP1SRC2(mul, mul_ex);
829FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 830FASTOP1SRC2EX(div, div_ex);
831FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 832
34b77652
AK		 833FASTOP3WCL(shld);
834FASTOP3WCL(shrd);
835
836FASTOP2W(imul);
837
838FASTOP1(not);
839FASTOP1(neg);
840FASTOP1(inc);
841FASTOP1(dec);
842
843FASTOP2CL(rol);
844FASTOP2CL(ror);
845FASTOP2CL(rcl);
846FASTOP2CL(rcr);
847FASTOP2CL(shl);
848FASTOP2CL(shr);
849FASTOP2CL(sar);
850
851FASTOP2W(bsf);
852FASTOP2W(bsr);
853FASTOP2W(bt);
854FASTOP2W(bts);
855FASTOP2W(btr);
856FASTOP2W(btc);
857
e47a5f5f
AK		 858FASTOP2(xadd);
859
9ae9feba 860static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 861{
9ae9feba
AK		 862 u8 rc;
863 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 864
9ae9feba 865 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 866 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 867 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
868 return rc;
bbe9abbd
NK		 869}
870
91ff3cb4
AK		 871static void fetch_register_operand(struct operand *op)
872{
873 switch (op->bytes) {
874 case 1:
875 op->val = *(u8 *)op->addr.reg;
876 break;
877 case 2:
878 op->val = *(u16 *)op->addr.reg;
879 break;
880 case 4:
881 op->val = *(u32 *)op->addr.reg;
882 break;
883 case 8:
884 op->val = *(u64 *)op->addr.reg;
885 break;
886 }
887}
888
1253791d
AK		 889static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
890{
891 ctxt->ops->get_fpu(ctxt);
892 switch (reg) {
89a87c67
MK		 893 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
894 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
895 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
896 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
897 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
898 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
899 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
900 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 901#ifdef CONFIG_X86_64
89a87c67
MK		 902 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
903 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
904 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
905 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
906 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
907 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
908 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
909 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 910#endif
911 default: BUG();
912 }
913 ctxt->ops->put_fpu(ctxt);
914}
915
916static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
917 int reg)
918{
919 ctxt->ops->get_fpu(ctxt);
920 switch (reg) {
89a87c67
MK		 921 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
922 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
923 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
924 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
925 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
926 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
927 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
928 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 929#ifdef CONFIG_X86_64
89a87c67
MK		 930 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
931 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
932 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
933 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
934 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
935 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
936 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
937 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 938#endif
939 default: BUG();
940 }
941 ctxt->ops->put_fpu(ctxt);
942}
943
cbe2c9d3
AK		 944static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
948 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
949 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
950 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
951 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
952 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
953 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
954 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
955 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
956 default: BUG();
957 }
958 ctxt->ops->put_fpu(ctxt);
959}
960
961static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
965 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
966 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
967 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
968 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
969 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
970 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
971 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
972 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
045a282c
GN		 978static int em_fninit(struct x86_emulate_ctxt *ctxt)
979{
980 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
981 return emulate_nm(ctxt);
982
983 ctxt->ops->get_fpu(ctxt);
984 asm volatile("fninit");
985 ctxt->ops->put_fpu(ctxt);
986 return X86EMUL_CONTINUE;
987}
988
989static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
990{
991 u16 fcw;
992
993 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
994 return emulate_nm(ctxt);
995
996 ctxt->ops->get_fpu(ctxt);
997 asm volatile("fnstcw %0": "+m"(fcw));
998 ctxt->ops->put_fpu(ctxt);
999
1000 /* force 2 byte destination */
1001 ctxt->dst.bytes = 2;
1002 ctxt->dst.val = fcw;
1003
1004 return X86EMUL_CONTINUE;
1005}
1006
1007static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1008{
1009 u16 fsw;
1010
1011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1012 return emulate_nm(ctxt);
1013
1014 ctxt->ops->get_fpu(ctxt);
1015 asm volatile("fnstsw %0": "+m"(fsw));
1016 ctxt->ops->put_fpu(ctxt);
1017
1018 /* force 2 byte destination */
1019 ctxt->dst.bytes = 2;
1020 ctxt->dst.val = fsw;
1021
1022 return X86EMUL_CONTINUE;
1023}
1024
1253791d 1025static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1026 struct operand *op)
3c118e24 1027{
9dac77fa 1028 unsigned reg = ctxt->modrm_reg;
33615aa9 1029
9dac77fa
AK		 1030 if (!(ctxt->d & ModRM))
1031 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1032
9dac77fa 1033 if (ctxt->d & Sse) {
1253791d
AK		 1034 op->type = OP_XMM;
1035 op->bytes = 16;
1036 op->addr.xmm = reg;
1037 read_sse_reg(ctxt, &op->vec_val, reg);
1038 return;
1039 }
cbe2c9d3
AK		 1040 if (ctxt->d & Mmx) {
1041 reg &= 7;
1042 op->type = OP_MM;
1043 op->bytes = 8;
1044 op->addr.mm = reg;
1045 return;
1046 }
1253791d 1047
3c118e24 1048 op->type = OP_REG;
6d4d85ec
GN		 1049 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1050 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1051
91ff3cb4 1052 fetch_register_operand(op);
3c118e24
AK		 1053 op->orig_val = op->val;
1054}
1055
a6e3407b
AK		 1056static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1057{
1058 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1059 ctxt->modrm_seg = VCPU_SREG_SS;
1060}
1061
1c73ef66 1062static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1063 struct operand *op)
1c73ef66 1064{
1c73ef66 1065 u8 sib;
f5b4edcd 1066 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1067 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1068 ulong modrm_ea = 0;
1c73ef66 1069
9dac77fa
AK		 1070 if (ctxt->rex_prefix) {
1071 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1072 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1073 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1074 }
1075
9dac77fa
AK		 1076 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1077 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1078 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1079 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1080
9b88ae99 1081 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1082 op->type = OP_REG;
9dac77fa 1083 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1084 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1085 ctxt->d & ByteOp);
9dac77fa 1086 if (ctxt->d & Sse) {
1253791d
AK		 1087 op->type = OP_XMM;
1088 op->bytes = 16;
9dac77fa
AK		 1089 op->addr.xmm = ctxt->modrm_rm;
1090 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1091 return rc;
1092 }
cbe2c9d3
AK		 1093 if (ctxt->d & Mmx) {
1094 op->type = OP_MM;
1095 op->bytes = 8;
1096 op->addr.xmm = ctxt->modrm_rm & 7;
1097 return rc;
1098 }
2dbd0dd7 1099 fetch_register_operand(op);
1c73ef66
AK		 1100 return rc;
1101 }
1102
2dbd0dd7
AK		 1103 op->type = OP_MEM;
1104
9dac77fa 1105 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1106 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1107 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1108 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1109 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1110
1111 /* 16-bit ModR/M decode. */
9dac77fa 1112 switch (ctxt->modrm_mod) {
1c73ef66 1113 case 0:
9dac77fa 1114 if (ctxt->modrm_rm == 6)
e85a1085 1115 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1116 break;
1117 case 1:
e85a1085 1118 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1119 break;
1120 case 2:
e85a1085 1121 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1122 break;
1123 }
9dac77fa 1124 switch (ctxt->modrm_rm) {
1c73ef66 1125 case 0:
2dbd0dd7 1126 modrm_ea += bx + si;
1c73ef66
AK		 1127 break;
1128 case 1:
2dbd0dd7 1129 modrm_ea += bx + di;
1c73ef66
AK		 1130 break;
1131 case 2:
2dbd0dd7 1132 modrm_ea += bp + si;
1c73ef66
AK		 1133 break;
1134 case 3:
2dbd0dd7 1135 modrm_ea += bp + di;
1c73ef66
AK		 1136 break;
1137 case 4:
2dbd0dd7 1138 modrm_ea += si;
1c73ef66
AK		 1139 break;
1140 case 5:
2dbd0dd7 1141 modrm_ea += di;
1c73ef66
AK		 1142 break;
1143 case 6:
9dac77fa 1144 if (ctxt->modrm_mod != 0)
2dbd0dd7 1145 modrm_ea += bp;
1c73ef66
AK		 1146 break;
1147 case 7:
2dbd0dd7 1148 modrm_ea += bx;
1c73ef66
AK		 1149 break;
1150 }
9dac77fa
AK		 1151 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1152 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1153 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1154 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1155 } else {
1156 /* 32/64-bit ModR/M decode. */
9dac77fa 1157 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1158 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1159 index_reg |= (sib >> 3) & 7;
1160 base_reg |= sib & 7;
1161 scale = sib >> 6;
1162
9dac77fa 1163 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1165 else {
dd856efa 1166 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1167 adjust_modrm_seg(ctxt, base_reg);
1168 }
dc71d0f1 1169 if (index_reg != 4)
dd856efa 1170 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1171 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1172 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1173 ctxt->rip_relative = 1;
a6e3407b
AK		 1174 } else {
1175 base_reg = ctxt->modrm_rm;
dd856efa 1176 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1177 adjust_modrm_seg(ctxt, base_reg);
1178 }
9dac77fa 1179 switch (ctxt->modrm_mod) {
1c73ef66 1180 case 0:
9dac77fa 1181 if (ctxt->modrm_rm == 5)
e85a1085 1182 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1183 break;
1184 case 1:
e85a1085 1185 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1186 break;
1187 case 2:
e85a1085 1188 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1189 break;
1190 }
1191 }
90de84f5 1192 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1193done:
1194 return rc;
1195}
1196
1197static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1198 struct operand *op)
1c73ef66 1199{
3e2815e9 1200 int rc = X86EMUL_CONTINUE;
1c73ef66 1201
2dbd0dd7 1202 op->type = OP_MEM;
9dac77fa 1203 switch (ctxt->ad_bytes) {
1c73ef66 1204 case 2:
e85a1085 1205 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1206 break;
1207 case 4:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1209 break;
1210 case 8:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1212 break;
1213 }
1214done:
1215 return rc;
1216}
1217
9dac77fa 1218static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1219{
7129eeca 1220 long sv = 0, mask;
35c843c4 1221
9dac77fa
AK		 1222 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1223 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1224
9dac77fa
AK		 1225 if (ctxt->src.bytes == 2)
1226 sv = (s16)ctxt->src.val & (s16)mask;
1227 else if (ctxt->src.bytes == 4)
1228 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1229
9dac77fa 1230 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1231 }
ba7ff2b7
WY		 1232
1233 /* only subword offset */
9dac77fa 1234 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1235}
1236
dde7e6d1 1237static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1238 unsigned long addr, void *dest, unsigned size)
6aa8b732 1239{
dde7e6d1 1240 int rc;
9dac77fa 1241 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1242
f23b070e
XG		 1243 if (mc->pos < mc->end)
1244 goto read_cached;
6aa8b732 1245
f23b070e
XG		 1246 WARN_ON((mc->end + size) >= sizeof(mc->data));
1247
1248 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1249 &ctxt->exception);
1250 if (rc != X86EMUL_CONTINUE)
1251 return rc;
1252
1253 mc->end += size;
1254
1255read_cached:
1256 memcpy(dest, mc->data + mc->pos, size);
1257 mc->pos += size;
dde7e6d1
AK		 1258 return X86EMUL_CONTINUE;
1259}
6aa8b732 1260
3ca3ac4d
AK		 1261static int segmented_read(struct x86_emulate_ctxt *ctxt,
1262 struct segmented_address addr,
1263 void *data,
1264 unsigned size)
1265{
9fa088f4
AK		 1266 int rc;
1267 ulong linear;
1268
83b8795a 1269 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
7b105ca2 1272 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1273}
1274
1275static int segmented_write(struct x86_emulate_ctxt *ctxt,
1276 struct segmented_address addr,
1277 const void *data,
1278 unsigned size)
1279{
9fa088f4
AK		 1280 int rc;
1281 ulong linear;
1282
83b8795a 1283 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
0f65dd70
AK		 1286 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1287 &ctxt->exception);
3ca3ac4d
AK		 1288}
1289
1290static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1291 struct segmented_address addr,
1292 const void *orig_data, const void *data,
1293 unsigned size)
1294{
9fa088f4
AK		 1295 int rc;
1296 ulong linear;
1297
83b8795a 1298 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
0f65dd70
AK		 1301 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1302 size, &ctxt->exception);
3ca3ac4d
AK		 1303}
1304
dde7e6d1 1305static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1306 unsigned int size, unsigned short port,
1307 void *dest)
1308{
9dac77fa 1309 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1310
dde7e6d1 1311 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1312 unsigned int in_page, n;
9dac77fa 1313 unsigned int count = ctxt->rep_prefix ?
dd856efa 1314 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1315 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1316 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1317 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1318 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1319 count);
1320 if (n == 0)
1321 n = 1;
1322 rc->pos = rc->end = 0;
7b105ca2 1323 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1324 return 0;
1325 rc->end = n * size;
6aa8b732
AK		 1326 }
1327
e6e39f04
NA		 1328 if (ctxt->rep_prefix && (ctxt->d & String) &&
1329 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1330 ctxt->dst.data = rc->data + rc->pos;
1331 ctxt->dst.type = OP_MEM_STR;
1332 ctxt->dst.count = (rc->end - rc->pos) / size;
1333 rc->pos = rc->end;
1334 } else {
1335 memcpy(dest, rc->data + rc->pos, size);
1336 rc->pos += size;
1337 }
dde7e6d1
AK		 1338 return 1;
1339}
6aa8b732 1340
7f3d35fd
KW		 1341static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1342 u16 index, struct desc_struct *desc)
1343{
1344 struct desc_ptr dt;
1345 ulong addr;
1346
1347 ctxt->ops->get_idt(ctxt, &dt);
1348
1349 if (dt.size < index * 8 + 7)
1350 return emulate_gp(ctxt, index << 3 | 0x2);
1351
1352 addr = dt.address + index * 8;
1353 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1354 &ctxt->exception);
1355}
1356
dde7e6d1 1357static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1358 u16 selector, struct desc_ptr *dt)
1359{
0225fb50 1360 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1361
dde7e6d1
AK		 1362 if (selector & 1 << 2) {
1363 struct desc_struct desc;
1aa36616
AK		 1364 u16 sel;
1365
dde7e6d1 1366 memset (dt, 0, sizeof *dt);
1aa36616 1367 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1368 return;
e09d082c 1369
dde7e6d1
AK		 1370 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1371 dt->address = get_desc_base(&desc);
1372 } else
4bff1e86 1373 ops->get_gdt(ctxt, dt);
dde7e6d1 1374}
120df890 1375
dde7e6d1
AK		 1376/* allowed just for 8 bytes segments */
1377static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1378 u16 selector, struct desc_struct *desc,
1379 ulong *desc_addr_p)
dde7e6d1
AK		 1380{
1381 struct desc_ptr dt;
1382 u16 index = selector >> 3;
dde7e6d1 1383 ulong addr;
120df890 1384
7b105ca2 1385 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1386
35d3d4a1
AK		 1387 if (dt.size < index * 8 + 7)
1388 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1389
e919464b 1390 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1391 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1392 &ctxt->exception);
dde7e6d1 1393}
ef65c889 1394
dde7e6d1
AK		 1395/* allowed just for 8 bytes segments */
1396static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1397 u16 selector, struct desc_struct *desc)
1398{
1399 struct desc_ptr dt;
1400 u16 index = selector >> 3;
dde7e6d1 1401 ulong addr;
6aa8b732 1402
7b105ca2 1403 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1404
35d3d4a1
AK		 1405 if (dt.size < index * 8 + 7)
1406 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1407
dde7e6d1 1408 addr = dt.address + index * 8;
7b105ca2
TY		 1409 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1410 &ctxt->exception);
dde7e6d1 1411}
c7e75a3d 1412
5601d05b 1413/* Does not support long mode */
2356aaeb 1414static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1415 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1416{
869be99c 1417 struct desc_struct seg_desc, old_desc;
2356aaeb 1418 u8 dpl, rpl;
dde7e6d1
AK		 1419 unsigned err_vec = GP_VECTOR;
1420 u32 err_code = 0;
1421 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1422 ulong desc_addr;
dde7e6d1 1423 int ret;
03ebebeb 1424 u16 dummy;
69f55cb1 1425
dde7e6d1 1426 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1427
f8da94e9
KW		 1428 if (ctxt->mode == X86EMUL_MODE_REAL) {
1429 /* set real mode segment descriptor (keep limit etc. for
1430 * unreal mode) */
03ebebeb 1431 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1432 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1433 goto load;
f8da94e9
KW		 1434 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1435 /* VM86 needs a clean new segment descriptor */
1436 set_desc_base(&seg_desc, selector << 4);
1437 set_desc_limit(&seg_desc, 0xffff);
1438 seg_desc.type = 3;
1439 seg_desc.p = 1;
1440 seg_desc.s = 1;
1441 seg_desc.dpl = 3;
1442 goto load;
dde7e6d1
AK		 1443 }
1444
79d5b4c3 1445 rpl = selector & 3;
79d5b4c3
AK		 1446
1447 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1448 if ((seg == VCPU_SREG_CS
1449 || (seg == VCPU_SREG_SS
1450 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1451 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1452 && null_selector)
1453 goto exception;
1454
1455 /* TR should be in GDT only */
1456 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1457 goto exception;
1458
1459 if (null_selector) /* for NULL selector skip all following checks */
1460 goto load;
1461
e919464b 1462 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1463 if (ret != X86EMUL_CONTINUE)
1464 return ret;
1465
1466 err_code = selector & 0xfffc;
1467 err_vec = GP_VECTOR;
1468
fc058680 1469 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1470 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1471 goto exception;
1472
1473 if (!seg_desc.p) {
1474 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1475 goto exception;
1476 }
1477
dde7e6d1 1478 dpl = seg_desc.dpl;
dde7e6d1
AK		 1479
1480 switch (seg) {
1481 case VCPU_SREG_SS:
1482 /*
1483 * segment is not a writable data segment or segment
1484 * selector's RPL != CPL or segment selector's RPL != CPL
1485 */
1486 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1487 goto exception;
6aa8b732 1488 break;
dde7e6d1 1489 case VCPU_SREG_CS:
5045b468
PB		 1490 if (in_task_switch && rpl != dpl)
1491 goto exception;
1492
dde7e6d1
AK		 1493 if (!(seg_desc.type & 8))
1494 goto exception;
1495
1496 if (seg_desc.type & 4) {
1497 /* conforming */
1498 if (dpl > cpl)
1499 goto exception;
1500 } else {
1501 /* nonconforming */
1502 if (rpl > cpl || dpl != cpl)
1503 goto exception;
1504 }
1505 /* CS(RPL) <- CPL */
1506 selector = (selector & 0xfffc) | cpl;
6aa8b732 1507 break;
dde7e6d1
AK		 1508 case VCPU_SREG_TR:
1509 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1510 goto exception;
869be99c
AK		 1511 old_desc = seg_desc;
1512 seg_desc.type |= 2; /* busy */
1513 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1514 sizeof(seg_desc), &ctxt->exception);
1515 if (ret != X86EMUL_CONTINUE)
1516 return ret;
dde7e6d1
AK		 1517 break;
1518 case VCPU_SREG_LDTR:
1519 if (seg_desc.s || seg_desc.type != 2)
1520 goto exception;
1521 break;
1522 default: /* DS, ES, FS, or GS */
4e62417b 1523 /*
dde7e6d1
AK		 1524 * segment is not a data or readable code segment or
1525 * ((segment is a data or nonconforming code segment)
1526 * and (both RPL and CPL > DPL))
4e62417b 1527 */
dde7e6d1
AK		 1528 if ((seg_desc.type & 0xa) == 0x8 ||
1529 (((seg_desc.type & 0xc) != 0xc) &&
1530 (rpl > dpl && cpl > dpl)))
1531 goto exception;
6aa8b732 1532 break;
dde7e6d1
AK		 1533 }
1534
1535 if (seg_desc.s) {
1536 /* mark segment as accessed */
1537 seg_desc.type |= 1;
7b105ca2 1538 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1539 if (ret != X86EMUL_CONTINUE)
1540 return ret;
1541 }
1542load:
7b105ca2 1543 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1544 return X86EMUL_CONTINUE;
1545exception:
1546 emulate_exception(ctxt, err_vec, err_code, true);
1547 return X86EMUL_PROPAGATE_FAULT;
1548}
1549
2356aaeb
PB		 1550static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1551 u16 selector, int seg)
1552{
1553 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1554 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1555}
1556
31be40b3
WY		 1557static void write_register_operand(struct operand *op)
1558{
1559 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1560 switch (op->bytes) {
1561 case 1:
1562 *(u8 *)op->addr.reg = (u8)op->val;
1563 break;
1564 case 2:
1565 *(u16 *)op->addr.reg = (u16)op->val;
1566 break;
1567 case 4:
1568 *op->addr.reg = (u32)op->val;
1569 break; /* 64b: zero-extend */
1570 case 8:
1571 *op->addr.reg = op->val;
1572 break;
1573 }
1574}
1575
fb32b1ed 1576static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1577{
1578 int rc;
dde7e6d1 1579
fb32b1ed 1580 switch (op->type) {
dde7e6d1 1581 case OP_REG:
fb32b1ed 1582 write_register_operand(op);
6aa8b732 1583 break;
dde7e6d1 1584 case OP_MEM:
9dac77fa 1585 if (ctxt->lock_prefix)
3ca3ac4d 1586 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1587 op->addr.mem,
1588 &op->orig_val,
1589 &op->val,
1590 op->bytes);
341de7e3 1591 else
3ca3ac4d 1592 rc = segmented_write(ctxt,
fb32b1ed
AK		 1593 op->addr.mem,
1594 &op->val,
1595 op->bytes);
dde7e6d1
AK		 1596 if (rc != X86EMUL_CONTINUE)
1597 return rc;
a682e354 1598 break;
b3356bf0
GN		 1599 case OP_MEM_STR:
1600 rc = segmented_write(ctxt,
fb32b1ed
AK		 1601 op->addr.mem,
1602 op->data,
1603 op->bytes * op->count);
b3356bf0
GN		 1604 if (rc != X86EMUL_CONTINUE)
1605 return rc;
1606 break;
1253791d 1607 case OP_XMM:
fb32b1ed 1608 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1609 break;
cbe2c9d3 1610 case OP_MM:
fb32b1ed 1611 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1612 break;
dde7e6d1
AK		 1613 case OP_NONE:
1614 /* no writeback */
414e6277 1615 break;
dde7e6d1 1616 default:
414e6277 1617 break;
6aa8b732 1618 }
dde7e6d1
AK		 1619 return X86EMUL_CONTINUE;
1620}
6aa8b732 1621
51ddff50 1622static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1623{
4179bb02 1624 struct segmented_address addr;
0dc8d10f 1625
5ad105e5 1626 rsp_increment(ctxt, -bytes);
dd856efa 1627 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1628 addr.seg = VCPU_SREG_SS;
1629
51ddff50
AK		 1630 return segmented_write(ctxt, addr, data, bytes);
1631}
1632
1633static int em_push(struct x86_emulate_ctxt *ctxt)
1634{
4179bb02 1635 /* Disable writeback. */
9dac77fa 1636 ctxt->dst.type = OP_NONE;
51ddff50 1637 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1638}
69f55cb1 1639
dde7e6d1 1640static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1641 void *dest, int len)
1642{
dde7e6d1 1643 int rc;
90de84f5 1644 struct segmented_address addr;
8b4caf66 1645
dd856efa 1646 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1647 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1648 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1649 if (rc != X86EMUL_CONTINUE)
1650 return rc;
1651
5ad105e5 1652 rsp_increment(ctxt, len);
dde7e6d1 1653 return rc;
8b4caf66
LV		 1654}
1655
c54fe504
TY		 1656static int em_pop(struct x86_emulate_ctxt *ctxt)
1657{
9dac77fa 1658 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1659}
1660
dde7e6d1 1661static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1662 void *dest, int len)
9de41573
GN		 1663{
1664 int rc;
dde7e6d1
AK		 1665 unsigned long val, change_mask;
1666 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1667 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1668
3b9be3bf 1669 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1670 if (rc != X86EMUL_CONTINUE)
1671 return rc;
9de41573 1672
dde7e6d1
AK		 1673 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1674 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1675
dde7e6d1
AK		 1676 switch(ctxt->mode) {
1677 case X86EMUL_MODE_PROT64:
1678 case X86EMUL_MODE_PROT32:
1679 case X86EMUL_MODE_PROT16:
1680 if (cpl == 0)
1681 change_mask |= EFLG_IOPL;
1682 if (cpl <= iopl)
1683 change_mask |= EFLG_IF;
1684 break;
1685 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1686 if (iopl < 3)
1687 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1688 change_mask |= EFLG_IF;
1689 break;
1690 default: /* real mode */
1691 change_mask |= (EFLG_IOPL | EFLG_IF);
1692 break;
9de41573 1693 }
dde7e6d1
AK		 1694
1695 *(unsigned long *)dest =
1696 (ctxt->eflags & ~change_mask) | (val & change_mask);
1697
1698 return rc;
9de41573
GN		 1699}
1700
62aaa2f0
TY		 1701static int em_popf(struct x86_emulate_ctxt *ctxt)
1702{
9dac77fa
AK		 1703 ctxt->dst.type = OP_REG;
1704 ctxt->dst.addr.reg = &ctxt->eflags;
1705 ctxt->dst.bytes = ctxt->op_bytes;
1706 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1707}
1708
612e89f0
AK		 1709static int em_enter(struct x86_emulate_ctxt *ctxt)
1710{
1711 int rc;
1712 unsigned frame_size = ctxt->src.val;
1713 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1714 ulong rbp;
612e89f0
AK		 1715
1716 if (nesting_level)
1717 return X86EMUL_UNHANDLEABLE;
1718
dd856efa
AK		 1719 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1720 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1721 if (rc != X86EMUL_CONTINUE)
1722 return rc;
dd856efa 1723 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1724 stack_mask(ctxt));
dd856efa
AK		 1725 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1726 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1727 stack_mask(ctxt));
1728 return X86EMUL_CONTINUE;
1729}
1730
f47cfa31
AK		 1731static int em_leave(struct x86_emulate_ctxt *ctxt)
1732{
dd856efa 1733 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1734 stack_mask(ctxt));
dd856efa 1735 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1736}
1737
1cd196ea 1738static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1739{
1cd196ea
AK		 1740 int seg = ctxt->src2.val;
1741
9dac77fa 1742 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1743
4487b3b4 1744 return em_push(ctxt);
7b262e90
GN		 1745}
1746
1cd196ea 1747static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1748{
1cd196ea 1749 int seg = ctxt->src2.val;
dde7e6d1
AK		 1750 unsigned long selector;
1751 int rc;
38ba30ba 1752
9dac77fa 1753 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
1756
7b105ca2 1757 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1758 return rc;
38ba30ba
GN		 1759}
1760
b96a7fad 1761static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1762{
dd856efa 1763 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1764 int rc = X86EMUL_CONTINUE;
1765 int reg = VCPU_REGS_RAX;
38ba30ba 1766
dde7e6d1
AK		 1767 while (reg <= VCPU_REGS_RDI) {
1768 (reg == VCPU_REGS_RSP) ?
dd856efa 1769 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1770
4487b3b4 1771 rc = em_push(ctxt);
dde7e6d1
AK		 1772 if (rc != X86EMUL_CONTINUE)
1773 return rc;
38ba30ba 1774
dde7e6d1 1775 ++reg;
38ba30ba 1776 }
38ba30ba 1777
dde7e6d1 1778 return rc;
38ba30ba
GN		 1779}
1780
62aaa2f0
TY		 1781static int em_pushf(struct x86_emulate_ctxt *ctxt)
1782{
9dac77fa 1783 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1784 return em_push(ctxt);
1785}
1786
b96a7fad 1787static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1788{
dde7e6d1
AK		 1789 int rc = X86EMUL_CONTINUE;
1790 int reg = VCPU_REGS_RDI;
38ba30ba 1791
dde7e6d1
AK		 1792 while (reg >= VCPU_REGS_RAX) {
1793 if (reg == VCPU_REGS_RSP) {
5ad105e5 1794 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1795 --reg;
1796 }
38ba30ba 1797
dd856efa 1798 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1799 if (rc != X86EMUL_CONTINUE)
1800 break;
1801 --reg;
38ba30ba 1802 }
dde7e6d1 1803 return rc;
38ba30ba
GN		 1804}
1805
dd856efa 1806static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1807{
0225fb50 1808 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1809 int rc;
6e154e56
MG		 1810 struct desc_ptr dt;
1811 gva_t cs_addr;
1812 gva_t eip_addr;
1813 u16 cs, eip;
6e154e56
MG		 1814
1815 /* TODO: Add limit checks */
9dac77fa 1816 ctxt->src.val = ctxt->eflags;
4487b3b4 1817 rc = em_push(ctxt);
5c56e1cf
AK		 1818 if (rc != X86EMUL_CONTINUE)
1819 return rc;
6e154e56
MG		 1820
1821 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1822
9dac77fa 1823 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1824 rc = em_push(ctxt);
5c56e1cf
AK		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
6e154e56 1827
9dac77fa 1828 ctxt->src.val = ctxt->_eip;
4487b3b4 1829 rc = em_push(ctxt);
5c56e1cf
AK		 1830 if (rc != X86EMUL_CONTINUE)
1831 return rc;
1832
4bff1e86 1833 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1834
1835 eip_addr = dt.address + (irq << 2);
1836 cs_addr = dt.address + (irq << 2) + 2;
1837
0f65dd70 1838 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1839 if (rc != X86EMUL_CONTINUE)
1840 return rc;
1841
0f65dd70 1842 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1843 if (rc != X86EMUL_CONTINUE)
1844 return rc;
1845
7b105ca2 1846 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
1849
9dac77fa 1850 ctxt->_eip = eip;
6e154e56
MG		 1851
1852 return rc;
1853}
1854
dd856efa
AK		 1855int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1856{
1857 int rc;
1858
1859 invalidate_registers(ctxt);
1860 rc = __emulate_int_real(ctxt, irq);
1861 if (rc == X86EMUL_CONTINUE)
1862 writeback_registers(ctxt);
1863 return rc;
1864}
1865
7b105ca2 1866static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1867{
1868 switch(ctxt->mode) {
1869 case X86EMUL_MODE_REAL:
dd856efa 1870 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1871 case X86EMUL_MODE_VM86:
1872 case X86EMUL_MODE_PROT16:
1873 case X86EMUL_MODE_PROT32:
1874 case X86EMUL_MODE_PROT64:
1875 default:
1876 /* Protected mode interrupts unimplemented yet */
1877 return X86EMUL_UNHANDLEABLE;
1878 }
1879}
1880
7b105ca2 1881static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1882{
dde7e6d1
AK		 1883 int rc = X86EMUL_CONTINUE;
1884 unsigned long temp_eip = 0;
1885 unsigned long temp_eflags = 0;
1886 unsigned long cs = 0;
1887 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1888 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1889 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1890 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1891
dde7e6d1 1892 /* TODO: Add stack limit check */
38ba30ba 1893
9dac77fa 1894 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1895
dde7e6d1
AK		 1896 if (rc != X86EMUL_CONTINUE)
1897 return rc;
38ba30ba 1898
35d3d4a1
AK		 1899 if (temp_eip & ~0xffff)
1900 return emulate_gp(ctxt, 0);
38ba30ba 1901
9dac77fa 1902 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1903
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
38ba30ba 1906
9dac77fa 1907 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1908
dde7e6d1
AK		 1909 if (rc != X86EMUL_CONTINUE)
1910 return rc;
38ba30ba 1911
7b105ca2 1912 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1913
dde7e6d1
AK		 1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
38ba30ba 1916
9dac77fa 1917 ctxt->_eip = temp_eip;
38ba30ba 1918
38ba30ba 1919
9dac77fa 1920 if (ctxt->op_bytes == 4)
dde7e6d1 1921 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1922 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1923 ctxt->eflags &= ~0xffff;
1924 ctxt->eflags |= temp_eflags;
38ba30ba 1925 }
dde7e6d1
AK		 1926
1927 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1928 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1929
1930 return rc;
38ba30ba
GN		 1931}
1932
e01991e7 1933static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1934{
dde7e6d1
AK		 1935 switch(ctxt->mode) {
1936 case X86EMUL_MODE_REAL:
7b105ca2 1937 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1938 case X86EMUL_MODE_VM86:
1939 case X86EMUL_MODE_PROT16:
1940 case X86EMUL_MODE_PROT32:
1941 case X86EMUL_MODE_PROT64:
c37eda13 1942 default:
dde7e6d1
AK		 1943 /* iret from protected mode unimplemented yet */
1944 return X86EMUL_UNHANDLEABLE;
c37eda13 1945 }
c37eda13
WY		 1946}
1947
d2f62766
TY		 1948static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1949{
d2f62766
TY		 1950 int rc;
1951 unsigned short sel;
1952
9dac77fa 1953 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1954
7b105ca2 1955 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1956 if (rc != X86EMUL_CONTINUE)
1957 return rc;
1958
9dac77fa
AK		 1959 ctxt->_eip = 0;
1960 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1961 return X86EMUL_CONTINUE;
1962}
1963
51187683 1964static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1965{
4179bb02 1966 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1967
9dac77fa 1968 switch (ctxt->modrm_reg) {
d19292e4
MG		 1969 case 2: /* call near abs */ {
1970 long int old_eip;
9dac77fa
AK		 1971 old_eip = ctxt->_eip;
1972 ctxt->_eip = ctxt->src.val;
1973 ctxt->src.val = old_eip;
4487b3b4 1974 rc = em_push(ctxt);
d19292e4
MG		 1975 break;
1976 }
8cdbd2c9 1977 case 4: /* jmp abs */
9dac77fa 1978 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1979 break;
d2f62766
TY		 1980 case 5: /* jmp far */
1981 rc = em_jmp_far(ctxt);
1982 break;
8cdbd2c9 1983 case 6: /* push */
4487b3b4 1984 rc = em_push(ctxt);
8cdbd2c9 1985 break;
8cdbd2c9 1986 }
4179bb02 1987 return rc;
8cdbd2c9
LV		 1988}
1989
e0dac408 1990static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1991{
9dac77fa 1992 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1993
dd856efa
AK		 1994 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1995 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1996 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1997 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 1998 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1999 } else {
dd856efa
AK		 2000 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2001 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2002
05f086f8 2003 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2004 }
1b30eaa8 2005 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2006}
2007
ebda02c2
TY		 2008static int em_ret(struct x86_emulate_ctxt *ctxt)
2009{
9dac77fa
AK		 2010 ctxt->dst.type = OP_REG;
2011 ctxt->dst.addr.reg = &ctxt->_eip;
2012 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2013 return em_pop(ctxt);
2014}
2015
e01991e7 2016static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2017{
a77ab5ea
AK		 2018 int rc;
2019 unsigned long cs;
2020
9dac77fa 2021 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2022 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2023 return rc;
9dac77fa
AK		 2024 if (ctxt->op_bytes == 4)
2025 ctxt->_eip = (u32)ctxt->_eip;
2026 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2027 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2028 return rc;
7b105ca2 2029 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2030 return rc;
2031}
2032
3261107e
BR		 2033static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2034{
2035 int rc;
2036
2037 rc = em_ret_far(ctxt);
2038 if (rc != X86EMUL_CONTINUE)
2039 return rc;
2040 rsp_increment(ctxt, ctxt->src.val);
2041 return X86EMUL_CONTINUE;
2042}
2043
e940b5c2
TY		 2044static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2045{
2046 /* Save real source value, then compare EAX against destination. */
2047 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2048 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2049 fastop(ctxt, em_cmp);
e940b5c2
TY		 2050
2051 if (ctxt->eflags & EFLG_ZF) {
2052 /* Success: write back to memory. */
2053 ctxt->dst.val = ctxt->src.orig_val;
2054 } else {
2055 /* Failure: write the value we saw to EAX. */
2056 ctxt->dst.type = OP_REG;
dd856efa 2057 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2058 }
2059 return X86EMUL_CONTINUE;
2060}
2061
d4b4325f 2062static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2063{
d4b4325f 2064 int seg = ctxt->src2.val;
09b5f4d3
WY		 2065 unsigned short sel;
2066 int rc;
2067
9dac77fa 2068 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2069
7b105ca2 2070 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2071 if (rc != X86EMUL_CONTINUE)
2072 return rc;
2073
9dac77fa 2074 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2075 return rc;
2076}
2077
7b105ca2 2078static void
e66bb2cc 2079setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2080 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2081{
e66bb2cc 2082 cs->l = 0; /* will be adjusted later */
79168fd1 2083 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2084 cs->g = 1; /* 4kb granularity */
79168fd1 2085 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2086 cs->type = 0x0b; /* Read, Execute, Accessed */
2087 cs->s = 1;
2088 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2089 cs->p = 1;
2090 cs->d = 1;
99245b50 2091 cs->avl = 0;
e66bb2cc 2092
79168fd1
GN		 2093 set_desc_base(ss, 0); /* flat segment */
2094 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2095 ss->g = 1; /* 4kb granularity */
2096 ss->s = 1;
2097 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2098 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2099 ss->dpl = 0;
79168fd1 2100 ss->p = 1;
99245b50
GN		 2101 ss->l = 0;
2102 ss->avl = 0;
e66bb2cc
AP		 2103}
2104
1a18a69b
AK		 2105static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2106{
2107 u32 eax, ebx, ecx, edx;
2108
2109 eax = ecx = 0;
0017f93a
AK		 2110 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2111 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2112 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2113 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2114}
2115
c2226fc9
SB		 2116static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2117{
0225fb50 2118 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2119 u32 eax, ebx, ecx, edx;
2120
2121 /*
2122 * syscall should always be enabled in longmode - so only become
2123 * vendor specific (cpuid) if other modes are active...
2124 */
2125 if (ctxt->mode == X86EMUL_MODE_PROT64)
2126 return true;
2127
2128 eax = 0x00000000;
2129 ecx = 0x00000000;
0017f93a
AK		 2130 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2131 /*
2132 * Intel ("GenuineIntel")
2133 * remark: Intel CPUs only support "syscall" in 64bit
2134 * longmode. Also an 64bit guest with a
2135 * 32bit compat-app running will #UD !! While this
2136 * behaviour can be fixed (by emulating) into AMD
2137 * response - CPUs of AMD can't behave like Intel.
2138 */
2139 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2140 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2141 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2142 return false;
2143
2144 /* AMD ("AuthenticAMD") */
2145 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2146 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2147 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2148 return true;
2149
2150 /* AMD ("AMDisbetter!") */
2151 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2152 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2153 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2154 return true;
c2226fc9
SB		 2155
2156 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2157 return false;
2158}
2159
e01991e7 2160static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2161{
0225fb50 2162 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2163 struct desc_struct cs, ss;
e66bb2cc 2164 u64 msr_data;
79168fd1 2165 u16 cs_sel, ss_sel;
c2ad2bb3 2166 u64 efer = 0;
e66bb2cc
AP		 2167
2168 /* syscall is not available in real mode */
2e901c4c 2169 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2170 ctxt->mode == X86EMUL_MODE_VM86)
2171 return emulate_ud(ctxt);
e66bb2cc 2172
c2226fc9
SB		 2173 if (!(em_syscall_is_enabled(ctxt)))
2174 return emulate_ud(ctxt);
2175
c2ad2bb3 2176 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2177 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2178
c2226fc9
SB		 2179 if (!(efer & EFER_SCE))
2180 return emulate_ud(ctxt);
2181
717746e3 2182 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2183 msr_data >>= 32;
79168fd1
GN		 2184 cs_sel = (u16)(msr_data & 0xfffc);
2185 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2186
c2ad2bb3 2187 if (efer & EFER_LMA) {
79168fd1 2188 cs.d = 0;
e66bb2cc
AP		 2189 cs.l = 1;
2190 }
1aa36616
AK		 2191 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2192 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2193
dd856efa 2194 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2195 if (efer & EFER_LMA) {
e66bb2cc 2196#ifdef CONFIG_X86_64
dd856efa 2197 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2198
717746e3 2199 ops->get_msr(ctxt,
3fb1b5db
GN		 2200 ctxt->mode == X86EMUL_MODE_PROT64 ?
2201 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2202 ctxt->_eip = msr_data;
e66bb2cc 2203
717746e3 2204 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2205 ctxt->eflags &= ~(msr_data | EFLG_RF);
2206#endif
2207 } else {
2208 /* legacy mode */
717746e3 2209 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2210 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2211
2212 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2213 }
2214
e54cfa97 2215 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2216}
2217
e01991e7 2218static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2219{
0225fb50 2220 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2221 struct desc_struct cs, ss;
8c604352 2222 u64 msr_data;
79168fd1 2223 u16 cs_sel, ss_sel;
c2ad2bb3 2224 u64 efer = 0;
8c604352 2225
7b105ca2 2226 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2227 /* inject #GP if in real mode */
35d3d4a1
AK		 2228 if (ctxt->mode == X86EMUL_MODE_REAL)
2229 return emulate_gp(ctxt, 0);
8c604352 2230
1a18a69b
AK		 2231 /*
2232 * Not recognized on AMD in compat mode (but is recognized in legacy
2233 * mode).
2234 */
2235 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2236 && !vendor_intel(ctxt))
2237 return emulate_ud(ctxt);
2238
8c604352
AP		 2239 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2240 * Therefore, we inject an #UD.
2241 */
35d3d4a1
AK		 2242 if (ctxt->mode == X86EMUL_MODE_PROT64)
2243 return emulate_ud(ctxt);
8c604352 2244
7b105ca2 2245 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2246
717746e3 2247 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2248 switch (ctxt->mode) {
2249 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2250 if ((msr_data & 0xfffc) == 0x0)
2251 return emulate_gp(ctxt, 0);
8c604352
AP		 2252 break;
2253 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2254 if (msr_data == 0x0)
2255 return emulate_gp(ctxt, 0);
8c604352 2256 break;
9d1b39a9
GN		 2257 default:
2258 break;
8c604352
AP		 2259 }
2260
2261 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2262 cs_sel = (u16)msr_data;
2263 cs_sel &= ~SELECTOR_RPL_MASK;
2264 ss_sel = cs_sel + 8;
2265 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2266 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2267 cs.d = 0;
8c604352
AP		 2268 cs.l = 1;
2269 }
2270
1aa36616
AK		 2271 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2272 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2273
717746e3 2274 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2275 ctxt->_eip = msr_data;
8c604352 2276
717746e3 2277 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2278 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2279
e54cfa97 2280 return X86EMUL_CONTINUE;
8c604352
AP		 2281}
2282
e01991e7 2283static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2284{
0225fb50 2285 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2286 struct desc_struct cs, ss;
4668f050
AP		 2287 u64 msr_data;
2288 int usermode;
1249b96e 2289 u16 cs_sel = 0, ss_sel = 0;
4668f050 2290
a0044755
GN		 2291 /* inject #GP if in real mode or Virtual 8086 mode */
2292 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2293 ctxt->mode == X86EMUL_MODE_VM86)
2294 return emulate_gp(ctxt, 0);
4668f050 2295
7b105ca2 2296 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2297
9dac77fa 2298 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2299 usermode = X86EMUL_MODE_PROT64;
2300 else
2301 usermode = X86EMUL_MODE_PROT32;
2302
2303 cs.dpl = 3;
2304 ss.dpl = 3;
717746e3 2305 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2306 switch (usermode) {
2307 case X86EMUL_MODE_PROT32:
79168fd1 2308 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2309 if ((msr_data & 0xfffc) == 0x0)
2310 return emulate_gp(ctxt, 0);
79168fd1 2311 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2312 break;
2313 case X86EMUL_MODE_PROT64:
79168fd1 2314 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2315 if (msr_data == 0x0)
2316 return emulate_gp(ctxt, 0);
79168fd1
GN		 2317 ss_sel = cs_sel + 8;
2318 cs.d = 0;
4668f050
AP		 2319 cs.l = 1;
2320 break;
2321 }
79168fd1
GN		 2322 cs_sel |= SELECTOR_RPL_MASK;
2323 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2324
1aa36616
AK		 2325 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2326 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2327
dd856efa
AK		 2328 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2329 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2330
e54cfa97 2331 return X86EMUL_CONTINUE;
4668f050
AP		 2332}
2333
7b105ca2 2334static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2335{
2336 int iopl;
2337 if (ctxt->mode == X86EMUL_MODE_REAL)
2338 return false;
2339 if (ctxt->mode == X86EMUL_MODE_VM86)
2340 return true;
2341 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2342 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2343}
2344
2345static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2346 u16 port, u16 len)
2347{
0225fb50 2348 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2349 struct desc_struct tr_seg;
5601d05b 2350 u32 base3;
f850e2e6 2351 int r;
1aa36616 2352 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2353 unsigned mask = (1 << len) - 1;
5601d05b 2354 unsigned long base;
f850e2e6 2355
1aa36616 2356 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2357 if (!tr_seg.p)
f850e2e6 2358 return false;
79168fd1 2359 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2360 return false;
5601d05b
GN		 2361 base = get_desc_base(&tr_seg);
2362#ifdef CONFIG_X86_64
2363 base |= ((u64)base3) << 32;
2364#endif
0f65dd70 2365 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2366 if (r != X86EMUL_CONTINUE)
2367 return false;
79168fd1 2368 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2369 return false;
0f65dd70 2370 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2371 if (r != X86EMUL_CONTINUE)
2372 return false;
2373 if ((perm >> bit_idx) & mask)
2374 return false;
2375 return true;
2376}
2377
2378static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2379 u16 port, u16 len)
2380{
4fc40f07
GN		 2381 if (ctxt->perm_ok)
2382 return true;
2383
7b105ca2
TY		 2384 if (emulator_bad_iopl(ctxt))
2385 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2386 return false;
4fc40f07
GN		 2387
2388 ctxt->perm_ok = true;
2389
f850e2e6
GN		 2390 return true;
2391}
2392
38ba30ba 2393static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2394 struct tss_segment_16 *tss)
2395{
9dac77fa 2396 tss->ip = ctxt->_eip;
38ba30ba 2397 tss->flag = ctxt->eflags;
dd856efa
AK		 2398 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2399 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2400 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2401 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2402 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2403 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2404 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2405 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2406
1aa36616
AK		 2407 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2408 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2409 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2410 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2411 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2412}
2413
2414static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2415 struct tss_segment_16 *tss)
2416{
38ba30ba 2417 int ret;
2356aaeb 2418 u8 cpl;
38ba30ba 2419
9dac77fa 2420 ctxt->_eip = tss->ip;
38ba30ba 2421 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2422 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2423 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2424 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2425 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2426 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2427 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2428 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2429 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2430
2431 /*
2432 * SDM says that segment selectors are loaded before segment
2433 * descriptors
2434 */
1aa36616
AK		 2435 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2436 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2437 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2438 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2439 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2440
2356aaeb
PB		 2441 cpl = tss->cs & 3;
2442
38ba30ba 2443 /*
fc058680 2444 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2445 * it is handled in a context of new task
2446 */
5045b468 2447 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2448 if (ret != X86EMUL_CONTINUE)
2449 return ret;
5045b468 2450 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2451 if (ret != X86EMUL_CONTINUE)
2452 return ret;
5045b468 2453 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2454 if (ret != X86EMUL_CONTINUE)
2455 return ret;
5045b468 2456 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2457 if (ret != X86EMUL_CONTINUE)
2458 return ret;
5045b468 2459 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2460 if (ret != X86EMUL_CONTINUE)
2461 return ret;
2462
2463 return X86EMUL_CONTINUE;
2464}
2465
2466static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2467 u16 tss_selector, u16 old_tss_sel,
2468 ulong old_tss_base, struct desc_struct *new_desc)
2469{
0225fb50 2470 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2471 struct tss_segment_16 tss_seg;
2472 int ret;
bcc55cba 2473 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2474
0f65dd70 2475 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2476 &ctxt->exception);
db297e3d 2477 if (ret != X86EMUL_CONTINUE)
38ba30ba 2478 /* FIXME: need to provide precise fault address */
38ba30ba 2479 return ret;
38ba30ba 2480
7b105ca2 2481 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2482
0f65dd70 2483 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2484 &ctxt->exception);
db297e3d 2485 if (ret != X86EMUL_CONTINUE)
38ba30ba 2486 /* FIXME: need to provide precise fault address */
38ba30ba 2487 return ret;
38ba30ba 2488
0f65dd70 2489 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2490 &ctxt->exception);
db297e3d 2491 if (ret != X86EMUL_CONTINUE)
38ba30ba 2492 /* FIXME: need to provide precise fault address */
38ba30ba 2493 return ret;
38ba30ba
GN		 2494
2495 if (old_tss_sel != 0xffff) {
2496 tss_seg.prev_task_link = old_tss_sel;
2497
0f65dd70 2498 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2499 &tss_seg.prev_task_link,
2500 sizeof tss_seg.prev_task_link,
0f65dd70 2501 &ctxt->exception);
db297e3d 2502 if (ret != X86EMUL_CONTINUE)
38ba30ba 2503 /* FIXME: need to provide precise fault address */
38ba30ba 2504 return ret;
38ba30ba
GN		 2505 }
2506
7b105ca2 2507 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2508}
2509
2510static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2511 struct tss_segment_32 *tss)
2512{
5c7411e2 2513 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2514 tss->eip = ctxt->_eip;
38ba30ba 2515 tss->eflags = ctxt->eflags;
dd856efa
AK		 2516 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2517 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2518 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2519 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2520 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2521 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2522 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2523 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2524
1aa36616
AK		 2525 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2526 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2527 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2528 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2529 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2530 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2531}
2532
2533static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2534 struct tss_segment_32 *tss)
2535{
38ba30ba 2536 int ret;
2356aaeb 2537 u8 cpl;
38ba30ba 2538
7b105ca2 2539 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2540 return emulate_gp(ctxt, 0);
9dac77fa 2541 ctxt->_eip = tss->eip;
38ba30ba 2542 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2543
2544 /* General purpose registers */
dd856efa
AK		 2545 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2546 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2547 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2548 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2549 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2550 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2551 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2552 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2553
2554 /*
2555 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2556 * descriptors. This is important because CPL checks will
2557 * use CS.RPL.
38ba30ba 2558 */
1aa36616
AK		 2559 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2560 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2561 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2562 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2563 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2564 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2565 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2566
4cee4798
KW		 2567 /*
2568 * If we're switching between Protected Mode and VM86, we need to make
2569 * sure to update the mode before loading the segment descriptors so
2570 * that the selectors are interpreted correctly.
4cee4798 2571 */
2356aaeb 2572 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2573 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2574 cpl = 3;
2575 } else {
4cee4798 2576 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2577 cpl = tss->cs & 3;
2578 }
4cee4798 2579
38ba30ba
GN		 2580 /*
2581 * Now load segment descriptors. If fault happenes at this stage
2582 * it is handled in a context of new task
2583 */
5045b468 2584 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
5045b468 2587 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2588 if (ret != X86EMUL_CONTINUE)
2589 return ret;
5045b468 2590 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
5045b468 2593 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2594 if (ret != X86EMUL_CONTINUE)
2595 return ret;
5045b468 2596 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2597 if (ret != X86EMUL_CONTINUE)
2598 return ret;
5045b468 2599 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2600 if (ret != X86EMUL_CONTINUE)
2601 return ret;
5045b468 2602 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2603 if (ret != X86EMUL_CONTINUE)
2604 return ret;
2605
2606 return X86EMUL_CONTINUE;
2607}
2608
2609static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2610 u16 tss_selector, u16 old_tss_sel,
2611 ulong old_tss_base, struct desc_struct *new_desc)
2612{
0225fb50 2613 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2614 struct tss_segment_32 tss_seg;
2615 int ret;
bcc55cba 2616 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2617 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2618 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2619
0f65dd70 2620 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2621 &ctxt->exception);
db297e3d 2622 if (ret != X86EMUL_CONTINUE)
38ba30ba 2623 /* FIXME: need to provide precise fault address */
38ba30ba 2624 return ret;
38ba30ba 2625
7b105ca2 2626 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2627
5c7411e2
NA		 2628 /* Only GP registers and segment selectors are saved */
2629 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2630 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2631 if (ret != X86EMUL_CONTINUE)
38ba30ba 2632 /* FIXME: need to provide precise fault address */
38ba30ba 2633 return ret;
38ba30ba 2634
0f65dd70 2635 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2636 &ctxt->exception);
db297e3d 2637 if (ret != X86EMUL_CONTINUE)
38ba30ba 2638 /* FIXME: need to provide precise fault address */
38ba30ba 2639 return ret;
38ba30ba
GN		 2640
2641 if (old_tss_sel != 0xffff) {
2642 tss_seg.prev_task_link = old_tss_sel;
2643
0f65dd70 2644 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2645 &tss_seg.prev_task_link,
2646 sizeof tss_seg.prev_task_link,
0f65dd70 2647 &ctxt->exception);
db297e3d 2648 if (ret != X86EMUL_CONTINUE)
38ba30ba 2649 /* FIXME: need to provide precise fault address */
38ba30ba 2650 return ret;
38ba30ba
GN		 2651 }
2652
7b105ca2 2653 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2654}
2655
2656static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2657 u16 tss_selector, int idt_index, int reason,
e269fb21 2658 bool has_error_code, u32 error_code)
38ba30ba 2659{
0225fb50 2660 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2661 struct desc_struct curr_tss_desc, next_tss_desc;
2662 int ret;
1aa36616 2663 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2664 ulong old_tss_base =
4bff1e86 2665 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2666 u32 desc_limit;
e919464b 2667 ulong desc_addr;
38ba30ba
GN		 2668
2669 /* FIXME: old_tss_base == ~0 ? */
2670
e919464b 2671 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2672 if (ret != X86EMUL_CONTINUE)
2673 return ret;
e919464b 2674 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2675 if (ret != X86EMUL_CONTINUE)
2676 return ret;
2677
2678 /* FIXME: check that next_tss_desc is tss */
2679
7f3d35fd
KW		 2680 /*
2681 * Check privileges. The three cases are task switch caused by...
2682 *
2683 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2684 * 2. Exception/IRQ/iret: No check is performed
fc058680 2685 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2686 */
2687 if (reason == TASK_SWITCH_GATE) {
2688 if (idt_index != -1) {
2689 /* Software interrupts */
2690 struct desc_struct task_gate_desc;
2691 int dpl;
2692
2693 ret = read_interrupt_descriptor(ctxt, idt_index,
2694 &task_gate_desc);
2695 if (ret != X86EMUL_CONTINUE)
2696 return ret;
2697
2698 dpl = task_gate_desc.dpl;
2699 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2700 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2701 }
2702 } else if (reason != TASK_SWITCH_IRET) {
2703 int dpl = next_tss_desc.dpl;
2704 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2705 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2706 }
2707
7f3d35fd 2708
ceffb459
GN		 2709 desc_limit = desc_limit_scaled(&next_tss_desc);
2710 if (!next_tss_desc.p ||
2711 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2712 desc_limit < 0x2b)) {
54b8486f 2713 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2714 return X86EMUL_PROPAGATE_FAULT;
2715 }
2716
2717 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2718 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2719 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2720 }
2721
2722 if (reason == TASK_SWITCH_IRET)
2723 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2724
2725 /* set back link to prev task only if NT bit is set in eflags
fc058680 2726 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2727 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2728 old_tss_sel = 0xffff;
2729
2730 if (next_tss_desc.type & 8)
7b105ca2 2731 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2732 old_tss_base, &next_tss_desc);
2733 else
7b105ca2 2734 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2735 old_tss_base, &next_tss_desc);
0760d448
JK		 2736 if (ret != X86EMUL_CONTINUE)
2737 return ret;
38ba30ba
GN		 2738
2739 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2740 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2741
2742 if (reason != TASK_SWITCH_IRET) {
2743 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2744 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2745 }
2746
717746e3 2747 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2748 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2749
e269fb21 2750 if (has_error_code) {
9dac77fa
AK		 2751 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2752 ctxt->lock_prefix = 0;
2753 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2754 ret = em_push(ctxt);
e269fb21
JK		 2755 }
2756
38ba30ba
GN		 2757 return ret;
2758}
2759
2760int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2761 u16 tss_selector, int idt_index, int reason,
e269fb21 2762 bool has_error_code, u32 error_code)
38ba30ba 2763{
38ba30ba
GN		 2764 int rc;
2765
dd856efa 2766 invalidate_registers(ctxt);
9dac77fa
AK		 2767 ctxt->_eip = ctxt->eip;
2768 ctxt->dst.type = OP_NONE;
38ba30ba 2769
7f3d35fd 2770 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2771 has_error_code, error_code);
38ba30ba 2772
dd856efa 2773 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2774 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2775 writeback_registers(ctxt);
2776 }
38ba30ba 2777
a0c0ab2f 2778 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2779}
2780
f3bd64c6
GN		 2781static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2782 struct operand *op)
a682e354 2783{
b3356bf0 2784 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2785
dd856efa
AK		 2786 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2787 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2788}
2789
7af04fc0
AK		 2790static int em_das(struct x86_emulate_ctxt *ctxt)
2791{
7af04fc0
AK		 2792 u8 al, old_al;
2793 bool af, cf, old_cf;
2794
2795 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2796 al = ctxt->dst.val;
7af04fc0
AK		 2797
2798 old_al = al;
2799 old_cf = cf;
2800 cf = false;
2801 af = ctxt->eflags & X86_EFLAGS_AF;
2802 if ((al & 0x0f) > 9 || af) {
2803 al -= 6;
2804 cf = old_cf | (al >= 250);
2805 af = true;
2806 } else {
2807 af = false;
2808 }
2809 if (old_al > 0x99 || old_cf) {
2810 al -= 0x60;
2811 cf = true;
2812 }
2813
9dac77fa 2814 ctxt->dst.val = al;
7af04fc0 2815 /* Set PF, ZF, SF */
9dac77fa
AK		 2816 ctxt->src.type = OP_IMM;
2817 ctxt->src.val = 0;
2818 ctxt->src.bytes = 1;
158de57f 2819 fastop(ctxt, em_or);
7af04fc0
AK		 2820 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2821 if (cf)
2822 ctxt->eflags |= X86_EFLAGS_CF;
2823 if (af)
2824 ctxt->eflags |= X86_EFLAGS_AF;
2825 return X86EMUL_CONTINUE;
2826}
2827
a035d5c6
PB		 2828static int em_aam(struct x86_emulate_ctxt *ctxt)
2829{
2830 u8 al, ah;
2831
2832 if (ctxt->src.val == 0)
2833 return emulate_de(ctxt);
2834
2835 al = ctxt->dst.val & 0xff;
2836 ah = al / ctxt->src.val;
2837 al %= ctxt->src.val;
2838
2839 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2840
2841 /* Set PF, ZF, SF */
2842 ctxt->src.type = OP_IMM;
2843 ctxt->src.val = 0;
2844 ctxt->src.bytes = 1;
2845 fastop(ctxt, em_or);
2846
2847 return X86EMUL_CONTINUE;
2848}
2849
7f662273
GN		 2850static int em_aad(struct x86_emulate_ctxt *ctxt)
2851{
2852 u8 al = ctxt->dst.val & 0xff;
2853 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2854
2855 al = (al + (ah * ctxt->src.val)) & 0xff;
2856
2857 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2858
f583c29b
GN		 2859 /* Set PF, ZF, SF */
2860 ctxt->src.type = OP_IMM;
2861 ctxt->src.val = 0;
2862 ctxt->src.bytes = 1;
2863 fastop(ctxt, em_or);
7f662273
GN		 2864
2865 return X86EMUL_CONTINUE;
2866}
2867
d4ddafcd
TY		 2868static int em_call(struct x86_emulate_ctxt *ctxt)
2869{
2870 long rel = ctxt->src.val;
2871
2872 ctxt->src.val = (unsigned long)ctxt->_eip;
2873 jmp_rel(ctxt, rel);
2874 return em_push(ctxt);
2875}
2876
0ef753b8
AK		 2877static int em_call_far(struct x86_emulate_ctxt *ctxt)
2878{
0ef753b8
AK		 2879 u16 sel, old_cs;
2880 ulong old_eip;
2881 int rc;
2882
1aa36616 2883 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2884 old_eip = ctxt->_eip;
0ef753b8 2885
9dac77fa 2886 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2887 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2888 return X86EMUL_CONTINUE;
2889
9dac77fa
AK		 2890 ctxt->_eip = 0;
2891 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2892
9dac77fa 2893 ctxt->src.val = old_cs;
4487b3b4 2894 rc = em_push(ctxt);
0ef753b8
AK		 2895 if (rc != X86EMUL_CONTINUE)
2896 return rc;
2897
9dac77fa 2898 ctxt->src.val = old_eip;
4487b3b4 2899 return em_push(ctxt);
0ef753b8
AK		 2900}
2901
40ece7c7
AK		 2902static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2903{
40ece7c7
AK		 2904 int rc;
2905
9dac77fa
AK		 2906 ctxt->dst.type = OP_REG;
2907 ctxt->dst.addr.reg = &ctxt->_eip;
2908 ctxt->dst.bytes = ctxt->op_bytes;
2909 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2910 if (rc != X86EMUL_CONTINUE)
2911 return rc;
5ad105e5 2912 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2913 return X86EMUL_CONTINUE;
2914}
2915
e4f973ae
TY		 2916static int em_xchg(struct x86_emulate_ctxt *ctxt)
2917{
e4f973ae 2918 /* Write back the register source. */
9dac77fa
AK		 2919 ctxt->src.val = ctxt->dst.val;
2920 write_register_operand(&ctxt->src);
e4f973ae
TY		 2921
2922 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2923 ctxt->dst.val = ctxt->src.orig_val;
2924 ctxt->lock_prefix = 1;
e4f973ae
TY		 2925 return X86EMUL_CONTINUE;
2926}
2927
5c82aa29
AK		 2928static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2929{
9dac77fa 2930 ctxt->dst.val = ctxt->src2.val;
4d758349 2931 return fastop(ctxt, em_imul);
5c82aa29
AK		 2932}
2933
61429142
AK		 2934static int em_cwd(struct x86_emulate_ctxt *ctxt)
2935{
9dac77fa
AK		 2936 ctxt->dst.type = OP_REG;
2937 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2938 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2939 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2940
2941 return X86EMUL_CONTINUE;
2942}
2943
48bb5d3c
AK		 2944static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2945{
48bb5d3c
AK		 2946 u64 tsc = 0;
2947
717746e3 2948 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2949 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2950 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2951 return X86EMUL_CONTINUE;
2952}
2953
222d21aa
AK		 2954static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2955{
2956 u64 pmc;
2957
dd856efa 2958 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2959 return emulate_gp(ctxt, 0);
dd856efa
AK		 2960 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2961 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2962 return X86EMUL_CONTINUE;
2963}
2964
b9eac5f4
AK		 2965static int em_mov(struct x86_emulate_ctxt *ctxt)
2966{
49597d81 2967 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2968 return X86EMUL_CONTINUE;
2969}
2970
84cffe49
BP		 2971#define FFL(x) bit(X86_FEATURE_##x)
2972
2973static int em_movbe(struct x86_emulate_ctxt *ctxt)
2974{
2975 u32 ebx, ecx, edx, eax = 1;
2976 u16 tmp;
2977
2978 /*
2979 * Check MOVBE is set in the guest-visible CPUID leaf.
2980 */
2981 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2982 if (!(ecx & FFL(MOVBE)))
2983 return emulate_ud(ctxt);
2984
2985 switch (ctxt->op_bytes) {
2986 case 2:
2987 /*
2988 * From MOVBE definition: "...When the operand size is 16 bits,
2989 * the upper word of the destination register remains unchanged
2990 * ..."
2991 *
2992 * Both casting ->valptr and ->val to u16 breaks strict aliasing
2993 * rules so we have to do the operation almost per hand.
2994 */
2995 tmp = (u16)ctxt->src.val;
2996 ctxt->dst.val &= ~0xffffUL;
2997 ctxt->dst.val |= (unsigned long)swab16(tmp);
2998 break;
2999 case 4:
3000 ctxt->dst.val = swab32((u32)ctxt->src.val);
3001 break;
3002 case 8:
3003 ctxt->dst.val = swab64(ctxt->src.val);
3004 break;
3005 default:
3006 return X86EMUL_PROPAGATE_FAULT;
3007 }
3008 return X86EMUL_CONTINUE;
3009}
3010
bc00f8d2
TY		 3011static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3012{
3013 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3014 return emulate_gp(ctxt, 0);
3015
3016 /* Disable writeback. */
3017 ctxt->dst.type = OP_NONE;
3018 return X86EMUL_CONTINUE;
3019}
3020
3021static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3022{
3023 unsigned long val;
3024
3025 if (ctxt->mode == X86EMUL_MODE_PROT64)
3026 val = ctxt->src.val & ~0ULL;
3027 else
3028 val = ctxt->src.val & ~0U;
3029
3030 /* #UD condition is already handled. */
3031 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3032 return emulate_gp(ctxt, 0);
3033
3034 /* Disable writeback. */
3035 ctxt->dst.type = OP_NONE;
3036 return X86EMUL_CONTINUE;
3037}
3038
e1e210b0
TY		 3039static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3040{
3041 u64 msr_data;
3042
dd856efa
AK		 3043 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3044 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3045 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3046 return emulate_gp(ctxt, 0);
3047
3048 return X86EMUL_CONTINUE;
3049}
3050
3051static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3052{
3053 u64 msr_data;
3054
dd856efa 3055 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3056 return emulate_gp(ctxt, 0);
3057
dd856efa
AK		 3058 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3059 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3060 return X86EMUL_CONTINUE;
3061}
3062
1bd5f469
TY		 3063static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3064{
9dac77fa 3065 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3066 return emulate_ud(ctxt);
3067
9dac77fa 3068 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3069 return X86EMUL_CONTINUE;
3070}
3071
3072static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3073{
9dac77fa 3074 u16 sel = ctxt->src.val;
1bd5f469 3075
9dac77fa 3076 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3077 return emulate_ud(ctxt);
3078
9dac77fa 3079 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3080 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3081
3082 /* Disable writeback. */
9dac77fa
AK		 3083 ctxt->dst.type = OP_NONE;
3084 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3085}
3086
a14e579f
AK		 3087static int em_lldt(struct x86_emulate_ctxt *ctxt)
3088{
3089 u16 sel = ctxt->src.val;
3090
3091 /* Disable writeback. */
3092 ctxt->dst.type = OP_NONE;
3093 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3094}
3095
80890006
AK		 3096static int em_ltr(struct x86_emulate_ctxt *ctxt)
3097{
3098 u16 sel = ctxt->src.val;
3099
3100 /* Disable writeback. */
3101 ctxt->dst.type = OP_NONE;
3102 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3103}
3104
38503911
AK		 3105static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3106{
9fa088f4
AK		 3107 int rc;
3108 ulong linear;
3109
9dac77fa 3110 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3111 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3112 ctxt->ops->invlpg(ctxt, linear);
38503911 3113 /* Disable writeback. */
9dac77fa 3114 ctxt->dst.type = OP_NONE;
38503911
AK		 3115 return X86EMUL_CONTINUE;
3116}
3117
2d04a05b
AK		 3118static int em_clts(struct x86_emulate_ctxt *ctxt)
3119{
3120 ulong cr0;
3121
3122 cr0 = ctxt->ops->get_cr(ctxt, 0);
3123 cr0 &= ~X86_CR0_TS;
3124 ctxt->ops->set_cr(ctxt, 0, cr0);
3125 return X86EMUL_CONTINUE;
3126}
3127
26d05cc7
AK		 3128static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3129{
26d05cc7
AK		 3130 int rc;
3131
9dac77fa 3132 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3133 return X86EMUL_UNHANDLEABLE;
3134
3135 rc = ctxt->ops->fix_hypercall(ctxt);
3136 if (rc != X86EMUL_CONTINUE)
3137 return rc;
3138
3139 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3140 ctxt->_eip = ctxt->eip;
26d05cc7 3141 /* Disable writeback. */
9dac77fa 3142 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3143 return X86EMUL_CONTINUE;
3144}
3145
96051572
AK		 3146static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3147 void (*get)(struct x86_emulate_ctxt *ctxt,
3148 struct desc_ptr *ptr))
3149{
3150 struct desc_ptr desc_ptr;
3151
3152 if (ctxt->mode == X86EMUL_MODE_PROT64)
3153 ctxt->op_bytes = 8;
3154 get(ctxt, &desc_ptr);
3155 if (ctxt->op_bytes == 2) {
3156 ctxt->op_bytes = 4;
3157 desc_ptr.address &= 0x00ffffff;
3158 }
3159 /* Disable writeback. */
3160 ctxt->dst.type = OP_NONE;
3161 return segmented_write(ctxt, ctxt->dst.addr.mem,
3162 &desc_ptr, 2 + ctxt->op_bytes);
3163}
3164
3165static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3166{
3167 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3168}
3169
3170static int em_sidt(struct x86_emulate_ctxt *ctxt)
3171{
3172 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3173}
3174
26d05cc7
AK		 3175static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3176{
26d05cc7
AK		 3177 struct desc_ptr desc_ptr;
3178 int rc;
3179
510425ff
AK		 3180 if (ctxt->mode == X86EMUL_MODE_PROT64)
3181 ctxt->op_bytes = 8;
9dac77fa 3182 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3183 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3184 ctxt->op_bytes);
26d05cc7
AK		 3185 if (rc != X86EMUL_CONTINUE)
3186 return rc;
3187 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3188 /* Disable writeback. */
9dac77fa 3189 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3190 return X86EMUL_CONTINUE;
3191}
3192
5ef39c71 3193static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3194{
26d05cc7
AK		 3195 int rc;
3196
5ef39c71
AK		 3197 rc = ctxt->ops->fix_hypercall(ctxt);
3198
26d05cc7 3199 /* Disable writeback. */
9dac77fa 3200 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3201 return rc;
3202}
3203
3204static int em_lidt(struct x86_emulate_ctxt *ctxt)
3205{
26d05cc7
AK		 3206 struct desc_ptr desc_ptr;
3207 int rc;
3208
510425ff
AK		 3209 if (ctxt->mode == X86EMUL_MODE_PROT64)
3210 ctxt->op_bytes = 8;
9dac77fa 3211 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3212 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3213 ctxt->op_bytes);
26d05cc7
AK		 3214 if (rc != X86EMUL_CONTINUE)
3215 return rc;
3216 ctxt->ops->set_idt(ctxt, &desc_ptr);
3217 /* Disable writeback. */
9dac77fa 3218 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3219 return X86EMUL_CONTINUE;
3220}
3221
3222static int em_smsw(struct x86_emulate_ctxt *ctxt)
3223{
9dac77fa
AK		 3224 ctxt->dst.bytes = 2;
3225 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3226 return X86EMUL_CONTINUE;
3227}
3228
3229static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3230{
26d05cc7 3231 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3232 | (ctxt->src.val & 0x0f));
3233 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3234 return X86EMUL_CONTINUE;
3235}
3236
d06e03ad
TY		 3237static int em_loop(struct x86_emulate_ctxt *ctxt)
3238{
dd856efa
AK		 3239 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3240 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3241 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3242 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3243
3244 return X86EMUL_CONTINUE;
3245}
3246
3247static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3248{
dd856efa 3249 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3250 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3251
3252 return X86EMUL_CONTINUE;
3253}
3254
d7841a4b
TY		 3255static int em_in(struct x86_emulate_ctxt *ctxt)
3256{
3257 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3258 &ctxt->dst.val))
3259 return X86EMUL_IO_NEEDED;
3260
3261 return X86EMUL_CONTINUE;
3262}
3263
3264static int em_out(struct x86_emulate_ctxt *ctxt)
3265{
3266 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3267 &ctxt->src.val, 1);
3268 /* Disable writeback. */
3269 ctxt->dst.type = OP_NONE;
3270 return X86EMUL_CONTINUE;
3271}
3272
f411e6cd
TY		 3273static int em_cli(struct x86_emulate_ctxt *ctxt)
3274{
3275 if (emulator_bad_iopl(ctxt))
3276 return emulate_gp(ctxt, 0);
3277
3278 ctxt->eflags &= ~X86_EFLAGS_IF;
3279 return X86EMUL_CONTINUE;
3280}
3281
3282static int em_sti(struct x86_emulate_ctxt *ctxt)
3283{
3284 if (emulator_bad_iopl(ctxt))
3285 return emulate_gp(ctxt, 0);
3286
3287 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3288 ctxt->eflags |= X86_EFLAGS_IF;
3289 return X86EMUL_CONTINUE;
3290}
3291
6d6eede4
AK		 3292static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3293{
3294 u32 eax, ebx, ecx, edx;
3295
dd856efa
AK		 3296 eax = reg_read(ctxt, VCPU_REGS_RAX);
3297 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3298 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3299 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3300 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3301 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3302 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3303 return X86EMUL_CONTINUE;
3304}
3305
98f73630
PB		 3306static int em_sahf(struct x86_emulate_ctxt *ctxt)
3307{
3308 u32 flags;
3309
3310 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3311 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3312
3313 ctxt->eflags &= ~0xffUL;
3314 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3315 return X86EMUL_CONTINUE;
3316}
3317
2dd7caa0
AK		 3318static int em_lahf(struct x86_emulate_ctxt *ctxt)
3319{
dd856efa
AK		 3320 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3321 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3322 return X86EMUL_CONTINUE;
3323}
3324
9299836e
AK		 3325static int em_bswap(struct x86_emulate_ctxt *ctxt)
3326{
3327 switch (ctxt->op_bytes) {
3328#ifdef CONFIG_X86_64
3329 case 8:
3330 asm("bswap %0" : "+r"(ctxt->dst.val));
3331 break;
3332#endif
3333 default:
3334 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3335 break;
3336 }
3337 return X86EMUL_CONTINUE;
3338}
3339
cfec82cb
JR		 3340static bool valid_cr(int nr)
3341{
3342 switch (nr) {
3343 case 0:
3344 case 2 ... 4:
3345 case 8:
3346 return true;
3347 default:
3348 return false;
3349 }
3350}
3351
3352static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3353{
9dac77fa 3354 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3355 return emulate_ud(ctxt);
3356
3357 return X86EMUL_CONTINUE;
3358}
3359
3360static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3361{
9dac77fa
AK		 3362 u64 new_val = ctxt->src.val64;
3363 int cr = ctxt->modrm_reg;
c2ad2bb3 3364 u64 efer = 0;
cfec82cb
JR		 3365
3366 static u64 cr_reserved_bits[] = {
3367 0xffffffff00000000ULL,
3368 0, 0, 0, /* CR3 checked later */
3369 CR4_RESERVED_BITS,
3370 0, 0, 0,
3371 CR8_RESERVED_BITS,
3372 };
3373
3374 if (!valid_cr(cr))
3375 return emulate_ud(ctxt);
3376
3377 if (new_val & cr_reserved_bits[cr])
3378 return emulate_gp(ctxt, 0);
3379
3380 switch (cr) {
3381 case 0: {
c2ad2bb3 3382 u64 cr4;
cfec82cb
JR		 3383 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3384 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3385 return emulate_gp(ctxt, 0);
3386
717746e3
AK		 3387 cr4 = ctxt->ops->get_cr(ctxt, 4);
3388 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3389
3390 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3391 !(cr4 & X86_CR4_PAE))
3392 return emulate_gp(ctxt, 0);
3393
3394 break;
3395 }
3396 case 3: {
3397 u64 rsvd = 0;
3398
c2ad2bb3
AK		 3399 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3400 if (efer & EFER_LMA)
cfec82cb 3401 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3402
3403 if (new_val & rsvd)
3404 return emulate_gp(ctxt, 0);
3405
3406 break;
3407 }
3408 case 4: {
717746e3 3409 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3410
3411 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3412 return emulate_gp(ctxt, 0);
3413
3414 break;
3415 }
3416 }
3417
3418 return X86EMUL_CONTINUE;
3419}
3420
3b88e41a
JR		 3421static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3422{
3423 unsigned long dr7;
3424
717746e3 3425 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3426
3427 /* Check if DR7.Global_Enable is set */
3428 return dr7 & (1 << 13);
3429}
3430
3431static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3432{
9dac77fa 3433 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3434 u64 cr4;
3435
3436 if (dr > 7)
3437 return emulate_ud(ctxt);
3438
717746e3 3439 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3440 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3441 return emulate_ud(ctxt);
3442
3443 if (check_dr7_gd(ctxt))
3444 return emulate_db(ctxt);
3445
3446 return X86EMUL_CONTINUE;
3447}
3448
3449static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3450{
9dac77fa
AK		 3451 u64 new_val = ctxt->src.val64;
3452 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3453
3454 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3455 return emulate_gp(ctxt, 0);
3456
3457 return check_dr_read(ctxt);
3458}
3459
01de8b09
JR		 3460static int check_svme(struct x86_emulate_ctxt *ctxt)
3461{
3462 u64 efer;
3463
717746e3 3464 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3465
3466 if (!(efer & EFER_SVME))
3467 return emulate_ud(ctxt);
3468
3469 return X86EMUL_CONTINUE;
3470}
3471
3472static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3473{
dd856efa 3474 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3475
3476 /* Valid physical address? */
d4224449 3477 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3478 return emulate_gp(ctxt, 0);
3479
3480 return check_svme(ctxt);
3481}
3482
d7eb8203
JR		 3483static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3484{
717746e3 3485 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3486
717746e3 3487 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3488 return emulate_ud(ctxt);
3489
3490 return X86EMUL_CONTINUE;
3491}
3492
8061252e
JR		 3493static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3494{
717746e3 3495 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3496 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3497
717746e3 3498 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3499 (rcx > 3))
3500 return emulate_gp(ctxt, 0);
3501
3502 return X86EMUL_CONTINUE;
3503}
3504
f6511935
JR		 3505static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3506{
9dac77fa
AK		 3507 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3508 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3509 return emulate_gp(ctxt, 0);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
3514static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3515{
9dac77fa
AK		 3516 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3517 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3518 return emulate_gp(ctxt, 0);
3519
3520 return X86EMUL_CONTINUE;
3521}
3522
73fba5f4 3523#define D(_y) { .flags = (_y) }
c4f035c6 3524#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3525#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3526 .check_perm = (_p) }
0b789eee 3527#define N D(NotImpl)
01de8b09 3528#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3529#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3530#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3531#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3532#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3533#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3534#define II(_f, _e, _i) \
3535 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3536#define IIP(_f, _e, _i, _p) \
3537 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3538 .check_perm = (_p) }
aa97bb48 3539#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3540
8d8f4e9f 3541#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3542#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3543#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3544#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3545#define I2bvIP(_f, _e, _i, _p) \
3546 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3547
fb864fbc
AK		 3548#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3549 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3550 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3551
fd0a0d82 3552static const struct opcode group7_rm1[] = {
1c2545be
TY		 3553 DI(SrcNone | Priv, monitor),
3554 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3555 N, N, N, N, N, N,
3556};
3557
fd0a0d82 3558static const struct opcode group7_rm3[] = {
1c2545be 3559 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3560 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3561 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3562 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3563 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3564 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3565 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3566 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3567};
6230f7fc 3568
fd0a0d82 3569static const struct opcode group7_rm7[] = {
d7eb8203 3570 N,
1c2545be 3571 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3572 N, N, N, N, N, N,
3573};
d67fc27a 3574
fd0a0d82 3575static const struct opcode group1[] = {
fb864fbc
AK		 3576 F(Lock, em_add),
3577 F(Lock | PageTable, em_or),
3578 F(Lock, em_adc),
3579 F(Lock, em_sbb),
3580 F(Lock | PageTable, em_and),
3581 F(Lock, em_sub),
3582 F(Lock, em_xor),
3583 F(NoWrite, em_cmp),
73fba5f4
AK		 3584};
3585
fd0a0d82 3586static const struct opcode group1A[] = {
1c2545be 3587 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3588};
3589
007a3b54
AK		 3590static const struct opcode group2[] = {
3591 F(DstMem | ModRM, em_rol),
3592 F(DstMem | ModRM, em_ror),
3593 F(DstMem | ModRM, em_rcl),
3594 F(DstMem | ModRM, em_rcr),
3595 F(DstMem | ModRM, em_shl),
3596 F(DstMem | ModRM, em_shr),
3597 F(DstMem | ModRM, em_shl),
3598 F(DstMem | ModRM, em_sar),
3599};
3600
fd0a0d82 3601static const struct opcode group3[] = {
fb864fbc
AK		 3602 F(DstMem | SrcImm | NoWrite, em_test),
3603 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3604 F(DstMem | SrcNone | Lock, em_not),
3605 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3606 F(DstXacc | Src2Mem, em_mul_ex),
3607 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3608 F(DstXacc | Src2Mem, em_div_ex),
3609 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3610};
3611
fd0a0d82 3612static const struct opcode group4[] = {
95413dc4
AK		 3613 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3614 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3615 N, N, N, N, N, N,
3616};
3617
fd0a0d82 3618static const struct opcode group5[] = {
95413dc4
AK		 3619 F(DstMem | SrcNone | Lock, em_inc),
3620 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3621 I(SrcMem | Stack, em_grp45),
3622 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3623 I(SrcMem | Stack, em_grp45),
3624 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3625 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3626};
3627
fd0a0d82 3628static const struct opcode group6[] = {
1c2545be
TY		 3629 DI(Prot, sldt),
3630 DI(Prot, str),
a14e579f 3631 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3632 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3633 N, N, N, N,
3634};
3635
fd0a0d82 3636static const struct group_dual group7 = { {
96051572
AK		 3637 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3638 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3639 II(SrcMem | Priv, em_lgdt, lgdt),
3640 II(SrcMem | Priv, em_lidt, lidt),
3641 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3642 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3643 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3644}, {
b51e974f 3645 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3646 EXT(0, group7_rm1),
01de8b09 3647 N, EXT(0, group7_rm3),
1c2545be
TY		 3648 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3649 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3650 EXT(0, group7_rm7),
73fba5f4
AK		 3651} };
3652
fd0a0d82 3653static const struct opcode group8[] = {
73fba5f4 3654 N, N, N, N,
11c363ba
AK		 3655 F(DstMem | SrcImmByte | NoWrite, em_bt),
3656 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3657 F(DstMem | SrcImmByte | Lock, em_btr),
3658 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3659};
3660
fd0a0d82 3661static const struct group_dual group9 = { {
1c2545be 3662 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3663}, {
3664 N, N, N, N, N, N, N, N,
3665} };
3666
fd0a0d82 3667static const struct opcode group11[] = {
1c2545be 3668 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3669 X7(D(Undefined)),
a4d4a7c1
AK		 3670};
3671
fd0a0d82 3672static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3673 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3674};
3675
fd0a0d82 3676static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3677 I(0, em_mov), N, N, N,
3678};
3679
27ce8258 3680static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3681 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3682};
3683
045a282c
GN		 3684static const struct escape escape_d9 = { {
3685 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3686}, {
3687 /* 0xC0 - 0xC7 */
3688 N, N, N, N, N, N, N, N,
3689 /* 0xC8 - 0xCF */
3690 N, N, N, N, N, N, N, N,
3691 /* 0xD0 - 0xC7 */
3692 N, N, N, N, N, N, N, N,
3693 /* 0xD8 - 0xDF */
3694 N, N, N, N, N, N, N, N,
3695 /* 0xE0 - 0xE7 */
3696 N, N, N, N, N, N, N, N,
3697 /* 0xE8 - 0xEF */
3698 N, N, N, N, N, N, N, N,
3699 /* 0xF0 - 0xF7 */
3700 N, N, N, N, N, N, N, N,
3701 /* 0xF8 - 0xFF */
3702 N, N, N, N, N, N, N, N,
3703} };
3704
3705static const struct escape escape_db = { {
3706 N, N, N, N, N, N, N, N,
3707}, {
3708 /* 0xC0 - 0xC7 */
3709 N, N, N, N, N, N, N, N,
3710 /* 0xC8 - 0xCF */
3711 N, N, N, N, N, N, N, N,
3712 /* 0xD0 - 0xC7 */
3713 N, N, N, N, N, N, N, N,
3714 /* 0xD8 - 0xDF */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xE0 - 0xE7 */
3717 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3718 /* 0xE8 - 0xEF */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xF0 - 0xF7 */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xF8 - 0xFF */
3723 N, N, N, N, N, N, N, N,
3724} };
3725
3726static const struct escape escape_dd = { {
3727 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3728}, {
3729 /* 0xC0 - 0xC7 */
3730 N, N, N, N, N, N, N, N,
3731 /* 0xC8 - 0xCF */
3732 N, N, N, N, N, N, N, N,
3733 /* 0xD0 - 0xC7 */
3734 N, N, N, N, N, N, N, N,
3735 /* 0xD8 - 0xDF */
3736 N, N, N, N, N, N, N, N,
3737 /* 0xE0 - 0xE7 */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xE8 - 0xEF */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xF0 - 0xF7 */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xF8 - 0xFF */
3744 N, N, N, N, N, N, N, N,
3745} };
3746
fd0a0d82 3747static const struct opcode opcode_table[256] = {
73fba5f4 3748 /* 0x00 - 0x07 */
fb864fbc 3749 F6ALU(Lock, em_add),
1cd196ea
AK		 3750 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3751 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3752 /* 0x08 - 0x0F */
fb864fbc 3753 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3754 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3755 N,
73fba5f4 3756 /* 0x10 - 0x17 */
fb864fbc 3757 F6ALU(Lock, em_adc),
1cd196ea
AK		 3758 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3759 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3760 /* 0x18 - 0x1F */
fb864fbc 3761 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3762 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3763 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3764 /* 0x20 - 0x27 */
fb864fbc 3765 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3766 /* 0x28 - 0x2F */
fb864fbc 3767 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3768 /* 0x30 - 0x37 */
fb864fbc 3769 F6ALU(Lock, em_xor), N, N,
73fba5f4 3770 /* 0x38 - 0x3F */
fb864fbc 3771 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3772 /* 0x40 - 0x4F */
95413dc4 3773 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3774 /* 0x50 - 0x57 */
63540382 3775 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3776 /* 0x58 - 0x5F */
c54fe504 3777 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3778 /* 0x60 - 0x67 */
b96a7fad
TY		 3779 I(ImplicitOps | Stack | No64, em_pusha),
3780 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3781 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3782 N, N, N, N,
3783 /* 0x68 - 0x6F */
d46164db
AK		 3784 I(SrcImm | Mov | Stack, em_push),
3785 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3786 I(SrcImmByte | Mov | Stack, em_push),
3787 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3788 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3789 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3790 /* 0x70 - 0x7F */
3791 X16(D(SrcImmByte)),
3792 /* 0x80 - 0x87 */
1c2545be
TY		 3793 G(ByteOp | DstMem | SrcImm, group1),
3794 G(DstMem | SrcImm, group1),
3795 G(ByteOp | DstMem | SrcImm | No64, group1),
3796 G(DstMem | SrcImmByte, group1),
fb864fbc 3797 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3798 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3799 /* 0x88 - 0x8F */
d5ae7ce8 3800 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3801 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3802 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3803 D(ModRM | SrcMem | NoAccess | DstReg),
3804 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3805 G(0, group1A),
73fba5f4 3806 /* 0x90 - 0x97 */
bf608f88 3807 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3808 /* 0x98 - 0x9F */
61429142 3809 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3810 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3811 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3812 II(ImplicitOps | Stack, em_popf, popf),
3813 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3814 /* 0xA0 - 0xA7 */
b9eac5f4 3815 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3816 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3817 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3818 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3819 /* 0xA8 - 0xAF */
fb864fbc 3820 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3821 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3822 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3823 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3824 /* 0xB0 - 0xB7 */
b9eac5f4 3825 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3826 /* 0xB8 - 0xBF */
5e2c6883 3827 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3828 /* 0xC0 - 0xC7 */
007a3b54 3829 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3830 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3831 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3832 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3833 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3834 G(ByteOp, group11), G(0, group11),
73fba5f4 3835 /* 0xC8 - 0xCF */
612e89f0 3836 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3837 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3838 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3839 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3840 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3841 /* 0xD0 - 0xD7 */
007a3b54
AK		 3842 G(Src2One | ByteOp, group2), G(Src2One, group2),
3843 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3844 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3845 I(DstAcc | SrcImmUByte | No64, em_aad),
3846 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3847 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3848 /* 0xD8 - 0xDF */
045a282c 3849 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3850 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3851 X3(I(SrcImmByte, em_loop)),
3852 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3853 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3854 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3855 /* 0xE8 - 0xEF */
d4ddafcd 3856 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3857 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3858 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3859 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3860 /* 0xF0 - 0xF7 */
bf608f88 3861 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3862 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3863 G(ByteOp, group3), G(0, group3),
73fba5f4 3864 /* 0xF8 - 0xFF */
f411e6cd
TY		 3865 D(ImplicitOps), D(ImplicitOps),
3866 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3867 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3868};
3869
fd0a0d82 3870static const struct opcode twobyte_table[256] = {
73fba5f4 3871 /* 0x00 - 0x0F */
dee6bb70 3872 G(0, group6), GD(0, &group7), N, N,
b51e974f 3873 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3874 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3875 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3876 N, D(ImplicitOps | ModRM), N, N,
3877 /* 0x10 - 0x1F */
103f98ea
PB		 3878 N, N, N, N, N, N, N, N,
3879 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3880 /* 0x20 - 0x2F */
9b88ae99
NA		 3881 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3882 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3883 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3884 check_cr_write),
3885 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3886 check_dr_write),
73fba5f4 3887 N, N, N, N,
27ce8258
IM		 3888 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3889 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3890 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3891 N, N, N, N,
73fba5f4 3892 /* 0x30 - 0x3F */
e1e210b0 3893 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3894 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3895 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3896 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3897 I(ImplicitOps | EmulateOnUD, em_sysenter),
3898 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3899 N, N,
73fba5f4
AK		 3900 N, N, N, N, N, N, N, N,
3901 /* 0x40 - 0x4F */
3902 X16(D(DstReg | SrcMem | ModRM | Mov)),
3903 /* 0x50 - 0x5F */
3904 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3905 /* 0x60 - 0x6F */
aa97bb48
AK		 3906 N, N, N, N,
3907 N, N, N, N,
3908 N, N, N, N,
3909 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3910 /* 0x70 - 0x7F */
aa97bb48
AK		 3911 N, N, N, N,
3912 N, N, N, N,
3913 N, N, N, N,
3914 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3915 /* 0x80 - 0x8F */
3916 X16(D(SrcImm)),
3917 /* 0x90 - 0x9F */
ee45b58e 3918 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3919 /* 0xA0 - 0xA7 */
1cd196ea 3920 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3921 II(ImplicitOps, em_cpuid, cpuid),
3922 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3923 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3924 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3925 /* 0xA8 - 0xAF */
1cd196ea 3926 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3927 DI(ImplicitOps, rsm),
11c363ba 3928 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3929 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3930 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3931 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3932 /* 0xB0 - 0xB7 */
e940b5c2 3933 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3934 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3935 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3936 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3937 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3938 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3939 /* 0xB8 - 0xBF */
3940 N, N,
ce7faab2 3941 G(BitOp, group8),
11c363ba
AK		 3942 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3943 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3944 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3945 /* 0xC0 - 0xC7 */
e47a5f5f 3946 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3947 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3948 N, N, N, GD(0, &group9),
9299836e
AK		 3949 /* 0xC8 - 0xCF */
3950 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3951 /* 0xD0 - 0xDF */
3952 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3953 /* 0xE0 - 0xEF */
3954 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3955 /* 0xF0 - 0xFF */
3956 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3957};
3958
0bc5eedb 3959static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3960 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3961};
3962
3963static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3964 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3965};
3966
3967/*
3968 * Insns below are selected by the prefix which indexed by the third opcode
3969 * byte.
3970 */
3971static const struct opcode opcode_map_0f_38[256] = {
3972 /* 0x00 - 0x7f */
3973 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3974 /* 0x80 - 0xef */
3975 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3976 /* 0xf0 - 0xf1 */
3977 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3978 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3979 /* 0xf2 - 0xff */
3980 N, N, X4(N), X8(N)
0bc5eedb
BP		 3981};
3982
73fba5f4
AK		 3983#undef D
3984#undef N
3985#undef G
3986#undef GD
3987#undef I
aa97bb48 3988#undef GP
01de8b09 3989#undef EXT
73fba5f4 3990
8d8f4e9f 3991#undef D2bv
f6511935 3992#undef D2bvIP
8d8f4e9f 3993#undef I2bv
d7841a4b 3994#undef I2bvIP
d67fc27a 3995#undef I6ALU
8d8f4e9f 3996
9dac77fa 3997static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3998{
3999 unsigned size;
4000
9dac77fa 4001 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4002 if (size == 8)
4003 size = 4;
4004 return size;
4005}
4006
4007static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4008 unsigned size, bool sign_extension)
4009{
39f21ee5
AK		 4010 int rc = X86EMUL_CONTINUE;
4011
4012 op->type = OP_IMM;
4013 op->bytes = size;
9dac77fa 4014 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4015 /* NB. Immediates are sign-extended as necessary. */
4016 switch (op->bytes) {
4017 case 1:
e85a1085 4018 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4019 break;
4020 case 2:
e85a1085 4021 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4022 break;
4023 case 4:
e85a1085 4024 op->val = insn_fetch(s32, ctxt);
39f21ee5 4025 break;
5e2c6883
NA		 4026 case 8:
4027 op->val = insn_fetch(s64, ctxt);
4028 break;
39f21ee5
AK		 4029 }
4030 if (!sign_extension) {
4031 switch (op->bytes) {
4032 case 1:
4033 op->val &= 0xff;
4034 break;
4035 case 2:
4036 op->val &= 0xffff;
4037 break;
4038 case 4:
4039 op->val &= 0xffffffff;
4040 break;
4041 }
4042 }
4043done:
4044 return rc;
4045}
4046
a9945549
AK		 4047static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4048 unsigned d)
4049{
4050 int rc = X86EMUL_CONTINUE;
4051
4052 switch (d) {
4053 case OpReg:
2adb5ad9 4054 decode_register_operand(ctxt, op);
a9945549
AK		 4055 break;
4056 case OpImmUByte:
608aabe3 4057 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4058 break;
4059 case OpMem:
41ddf978 4060 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4061 mem_common:
4062 *op = ctxt->memop;
4063 ctxt->memopp = op;
4064 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4065 fetch_bit_operand(ctxt);
4066 op->orig_val = op->val;
4067 break;
41ddf978
AK		 4068 case OpMem64:
4069 ctxt->memop.bytes = 8;
4070 goto mem_common;
a9945549
AK		 4071 case OpAcc:
4072 op->type = OP_REG;
4073 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4074 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4075 fetch_register_operand(op);
4076 op->orig_val = op->val;
4077 break;
820207c8
AK		 4078 case OpAccLo:
4079 op->type = OP_REG;
4080 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4081 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4082 fetch_register_operand(op);
4083 op->orig_val = op->val;
4084 break;
4085 case OpAccHi:
4086 if (ctxt->d & ByteOp) {
4087 op->type = OP_NONE;
4088 break;
4089 }
4090 op->type = OP_REG;
4091 op->bytes = ctxt->op_bytes;
4092 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4093 fetch_register_operand(op);
4094 op->orig_val = op->val;
4095 break;
a9945549
AK		 4096 case OpDI:
4097 op->type = OP_MEM;
4098 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4099 op->addr.mem.ea =
dd856efa 4100 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4101 op->addr.mem.seg = VCPU_SREG_ES;
4102 op->val = 0;
b3356bf0 4103 op->count = 1;
a9945549
AK		 4104 break;
4105 case OpDX:
4106 op->type = OP_REG;
4107 op->bytes = 2;
dd856efa 4108 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4109 fetch_register_operand(op);
4110 break;
4dd6a57d
AK		 4111 case OpCL:
4112 op->bytes = 1;
dd856efa 4113 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4114 break;
4115 case OpImmByte:
4116 rc = decode_imm(ctxt, op, 1, true);
4117 break;
4118 case OpOne:
4119 op->bytes = 1;
4120 op->val = 1;
4121 break;
4122 case OpImm:
4123 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4124 break;
5e2c6883
NA		 4125 case OpImm64:
4126 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4127 break;
28867cee
AK		 4128 case OpMem8:
4129 ctxt->memop.bytes = 1;
660696d1 4130 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4131 ctxt->memop.addr.reg = decode_register(ctxt,
4132 ctxt->modrm_rm, true);
660696d1
GN		 4133 fetch_register_operand(&ctxt->memop);
4134 }
28867cee 4135 goto mem_common;
0fe59128
AK		 4136 case OpMem16:
4137 ctxt->memop.bytes = 2;
4138 goto mem_common;
4139 case OpMem32:
4140 ctxt->memop.bytes = 4;
4141 goto mem_common;
4142 case OpImmU16:
4143 rc = decode_imm(ctxt, op, 2, false);
4144 break;
4145 case OpImmU:
4146 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4147 break;
4148 case OpSI:
4149 op->type = OP_MEM;
4150 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4151 op->addr.mem.ea =
dd856efa 4152 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4153 op->addr.mem.seg = seg_override(ctxt);
4154 op->val = 0;
b3356bf0 4155 op->count = 1;
0fe59128 4156 break;
7fa57952
PB		 4157 case OpXLat:
4158 op->type = OP_MEM;
4159 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4160 op->addr.mem.ea =
4161 register_address(ctxt,
4162 reg_read(ctxt, VCPU_REGS_RBX) +
4163 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4164 op->addr.mem.seg = seg_override(ctxt);
4165 op->val = 0;
4166 break;
0fe59128
AK		 4167 case OpImmFAddr:
4168 op->type = OP_IMM;
4169 op->addr.mem.ea = ctxt->_eip;
4170 op->bytes = ctxt->op_bytes + 2;
4171 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4172 break;
4173 case OpMemFAddr:
4174 ctxt->memop.bytes = ctxt->op_bytes + 2;
4175 goto mem_common;
c191a7a0
AK		 4176 case OpES:
4177 op->val = VCPU_SREG_ES;
4178 break;
4179 case OpCS:
4180 op->val = VCPU_SREG_CS;
4181 break;
4182 case OpSS:
4183 op->val = VCPU_SREG_SS;
4184 break;
4185 case OpDS:
4186 op->val = VCPU_SREG_DS;
4187 break;
4188 case OpFS:
4189 op->val = VCPU_SREG_FS;
4190 break;
4191 case OpGS:
4192 op->val = VCPU_SREG_GS;
4193 break;
a9945549
AK		 4194 case OpImplicit:
4195 /* Special instructions do their own operand decoding. */
4196 default:
4197 op->type = OP_NONE; /* Disable writeback. */
4198 break;
4199 }
4200
4201done:
4202 return rc;
4203}
4204
ef5d75cc 4205int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4206{
dde7e6d1
AK		 4207 int rc = X86EMUL_CONTINUE;
4208 int mode = ctxt->mode;
46561646 4209 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4210 bool op_prefix = false;
46561646 4211 struct opcode opcode;
dde7e6d1 4212
f09ed83e
AK		 4213 ctxt->memop.type = OP_NONE;
4214 ctxt->memopp = NULL;
9dac77fa
AK		 4215 ctxt->_eip = ctxt->eip;
4216 ctxt->fetch.start = ctxt->_eip;
4217 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4218 ctxt->opcode_len = 1;
dc25e89e 4219 if (insn_len > 0)
9dac77fa 4220 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4221
4222 switch (mode) {
4223 case X86EMUL_MODE_REAL:
4224 case X86EMUL_MODE_VM86:
4225 case X86EMUL_MODE_PROT16:
4226 def_op_bytes = def_ad_bytes = 2;
4227 break;
4228 case X86EMUL_MODE_PROT32:
4229 def_op_bytes = def_ad_bytes = 4;
4230 break;
4231#ifdef CONFIG_X86_64
4232 case X86EMUL_MODE_PROT64:
4233 def_op_bytes = 4;
4234 def_ad_bytes = 8;
4235 break;
4236#endif
4237 default:
1d2887e2 4238 return EMULATION_FAILED;
dde7e6d1
AK		 4239 }
4240
9dac77fa
AK		 4241 ctxt->op_bytes = def_op_bytes;
4242 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4243
4244 /* Legacy prefixes. */
4245 for (;;) {
e85a1085 4246 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4247 case 0x66: /* operand-size override */
0d7cdee8 4248 op_prefix = true;
dde7e6d1 4249 /* switch between 2/4 bytes */
9dac77fa 4250 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4251 break;
4252 case 0x67: /* address-size override */
4253 if (mode == X86EMUL_MODE_PROT64)
4254 /* switch between 4/8 bytes */
9dac77fa 4255 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4256 else
4257 /* switch between 2/4 bytes */
9dac77fa 4258 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4259 break;
4260 case 0x26: /* ES override */
4261 case 0x2e: /* CS override */
4262 case 0x36: /* SS override */
4263 case 0x3e: /* DS override */
9dac77fa 4264 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4265 break;
4266 case 0x64: /* FS override */
4267 case 0x65: /* GS override */
9dac77fa 4268 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4269 break;
4270 case 0x40 ... 0x4f: /* REX */
4271 if (mode != X86EMUL_MODE_PROT64)
4272 goto done_prefixes;
9dac77fa 4273 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4274 continue;
4275 case 0xf0: /* LOCK */
9dac77fa 4276 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4277 break;
4278 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4279 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4280 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4281 break;
4282 default:
4283 goto done_prefixes;
4284 }
4285
4286 /* Any legacy prefix after a REX prefix nullifies its effect. */
4287
9dac77fa 4288 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4289 }
4290
4291done_prefixes:
4292
4293 /* REX prefix. */
9dac77fa
AK		 4294 if (ctxt->rex_prefix & 8)
4295 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4296
4297 /* Opcode byte(s). */
9dac77fa 4298 opcode = opcode_table[ctxt->b];
d3ad6243 4299 /* Two-byte opcode? */
9dac77fa 4300 if (ctxt->b == 0x0f) {
1ce19dc1 4301 ctxt->opcode_len = 2;
e85a1085 4302 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4303 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4304
4305 /* 0F_38 opcode map */
4306 if (ctxt->b == 0x38) {
4307 ctxt->opcode_len = 3;
4308 ctxt->b = insn_fetch(u8, ctxt);
4309 opcode = opcode_map_0f_38[ctxt->b];
4310 }
dde7e6d1 4311 }
9dac77fa 4312 ctxt->d = opcode.flags;
dde7e6d1 4313
9f4260e7
TY		 4314 if (ctxt->d & ModRM)
4315 ctxt->modrm = insn_fetch(u8, ctxt);
4316
9dac77fa
AK		 4317 while (ctxt->d & GroupMask) {
4318 switch (ctxt->d & GroupMask) {
46561646 4319 case Group:
9dac77fa 4320 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4321 opcode = opcode.u.group[goffset];
4322 break;
4323 case GroupDual:
9dac77fa
AK		 4324 goffset = (ctxt->modrm >> 3) & 7;
4325 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4326 opcode = opcode.u.gdual->mod3[goffset];
4327 else
4328 opcode = opcode.u.gdual->mod012[goffset];
4329 break;
4330 case RMExt:
9dac77fa 4331 goffset = ctxt->modrm & 7;
01de8b09 4332 opcode = opcode.u.group[goffset];
46561646
AK		 4333 break;
4334 case Prefix:
9dac77fa 4335 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4336 return EMULATION_FAILED;
9dac77fa 4337 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4338 switch (simd_prefix) {
4339 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4340 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4341 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4342 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4343 }
4344 break;
045a282c
GN		 4345 case Escape:
4346 if (ctxt->modrm > 0xbf)
4347 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4348 else
4349 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4350 break;
46561646 4351 default:
1d2887e2 4352 return EMULATION_FAILED;
0d7cdee8 4353 }
46561646 4354
b1ea50b2 4355 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4356 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4357 }
4358
9dac77fa
AK		 4359 ctxt->execute = opcode.u.execute;
4360 ctxt->check_perm = opcode.check_perm;
4361 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4362
4363 /* Unrecognised? */
1146a78b 4364 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4365 return EMULATION_FAILED;
dde7e6d1 4366
b51e974f 4367 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
1d2887e2 4368 return EMULATION_FAILED;
d867162c 4369
9dac77fa
AK		 4370 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4371 ctxt->op_bytes = 8;
dde7e6d1 4372
9dac77fa 4373 if (ctxt->d & Op3264) {
7f9b4b75 4374 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4375 ctxt->op_bytes = 8;
7f9b4b75 4376 else
9dac77fa 4377 ctxt->op_bytes = 4;
7f9b4b75
AK		 4378 }
4379
9dac77fa
AK		 4380 if (ctxt->d & Sse)
4381 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4382 else if (ctxt->d & Mmx)
4383 ctxt->op_bytes = 8;
1253791d 4384
dde7e6d1 4385 /* ModRM and SIB bytes. */
9dac77fa 4386 if (ctxt->d & ModRM) {
f09ed83e 4387 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4388 if (!ctxt->has_seg_override)
4389 set_seg_override(ctxt, ctxt->modrm_seg);
4390 } else if (ctxt->d & MemAbs)
f09ed83e 4391 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4392 if (rc != X86EMUL_CONTINUE)
4393 goto done;
4394
9dac77fa
AK		 4395 if (!ctxt->has_seg_override)
4396 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4397
f09ed83e 4398 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4399
f09ed83e
AK		 4400 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4401 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4402
dde7e6d1
AK		 4403 /*
4404 * Decode and fetch the source operand: register, memory
4405 * or immediate.
4406 */
0fe59128 4407 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4408 if (rc != X86EMUL_CONTINUE)
4409 goto done;
4410
dde7e6d1
AK		 4411 /*
4412 * Decode and fetch the second source operand: register, memory
4413 * or immediate.
4414 */
4dd6a57d 4415 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4416 if (rc != X86EMUL_CONTINUE)
4417 goto done;
4418
dde7e6d1 4419 /* Decode and fetch the destination operand: register or memory. */
a9945549 4420 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4421
4422done:
f09ed83e
AK		 4423 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4424 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4425
1d2887e2 4426 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4427}
4428
1cb3f3ae
XG		 4429bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4430{
4431 return ctxt->d & PageTable;
4432}
4433
3e2f65d5
GN		 4434static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4435{
3e2f65d5
GN		 4436 /* The second termination condition only applies for REPE
4437 * and REPNE. Test if the repeat string operation prefix is
4438 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4439 * corresponding termination condition according to:
4440 * - if REPE/REPZ and ZF = 0 then done
4441 * - if REPNE/REPNZ and ZF = 1 then done
4442 */
9dac77fa
AK		 4443 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4444 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4445 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4446 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4447 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4448 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4449 return true;
4450
4451 return false;
4452}
4453
cbe2c9d3
AK		 4454static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4455{
4456 bool fault = false;
4457
4458 ctxt->ops->get_fpu(ctxt);
4459 asm volatile("1: fwait \n\t"
4460 "2: \n\t"
4461 ".pushsection .fixup,\"ax\" \n\t"
4462 "3: \n\t"
4463 "movb $1, %[fault] \n\t"
4464 "jmp 2b \n\t"
4465 ".popsection \n\t"
4466 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4467 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4468 ctxt->ops->put_fpu(ctxt);
4469
4470 if (unlikely(fault))
4471 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4472
4473 return X86EMUL_CONTINUE;
4474}
4475
4476static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4477 struct operand *op)
4478{
4479 if (op->type == OP_MM)
4480 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4481}
4482
e28bbd44
AK		 4483static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4484{
4485 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4486 if (!(ctxt->d & ByteOp))
4487 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4488 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4489 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4490 [fastop]"+S"(fop)
4491 : "c"(ctxt->src2.val));
e28bbd44 4492 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4493 if (!fop) /* exception is returned in fop variable */
4494 return emulate_de(ctxt);
e28bbd44
AK		 4495 return X86EMUL_CONTINUE;
4496}
dd856efa 4497
7b105ca2 4498int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4499{
0225fb50 4500 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4501 int rc = X86EMUL_CONTINUE;
9dac77fa 4502 int saved_dst_type = ctxt->dst.type;
8b4caf66 4503
9dac77fa 4504 ctxt->mem_read.pos = 0;
310b5d30 4505
1146a78b
GN		 4506 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4507 (ctxt->d & Undefined)) {
35d3d4a1 4508 rc = emulate_ud(ctxt);
1161624f
GN		 4509 goto done;
4510 }
4511
d380a5e4 4512 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4513 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4514 rc = emulate_ud(ctxt);
d380a5e4
GN		 4515 goto done;
4516 }
4517
9dac77fa 4518 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4519 rc = emulate_ud(ctxt);
081bca0e
AK		 4520 goto done;
4521 }
4522
cbe2c9d3
AK		 4523 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4524 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4525 rc = emulate_ud(ctxt);
4526 goto done;
4527 }
4528
cbe2c9d3 4529 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4530 rc = emulate_nm(ctxt);
4531 goto done;
4532 }
4533
cbe2c9d3
AK		 4534 if (ctxt->d & Mmx) {
4535 rc = flush_pending_x87_faults(ctxt);
4536 if (rc != X86EMUL_CONTINUE)
4537 goto done;
4538 /*
4539 * Now that we know the fpu is exception safe, we can fetch
4540 * operands from it.
4541 */
4542 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4543 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4544 if (!(ctxt->d & Mov))
4545 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4546 }
4547
9dac77fa
AK		 4548 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4549 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4550 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4551 if (rc != X86EMUL_CONTINUE)
4552 goto done;
4553 }
4554
e92805ac 4555 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4556 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4557 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4558 goto done;
4559 }
4560
8ea7d6ae 4561 /* Instruction can only be executed in protected mode */
9d1b39a9 4562 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4563 rc = emulate_ud(ctxt);
4564 goto done;
4565 }
4566
d09beabd 4567 /* Do instruction specific permission checks */
9dac77fa
AK		 4568 if (ctxt->check_perm) {
4569 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4570 if (rc != X86EMUL_CONTINUE)
4571 goto done;
4572 }
4573
9dac77fa
AK		 4574 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4575 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4576 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4577 if (rc != X86EMUL_CONTINUE)
4578 goto done;
4579 }
4580
9dac77fa 4581 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4582 /* All REP prefixes have the same first termination condition */
dd856efa 4583 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4584 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4585 goto done;
4586 }
b9fa9d6b
AK		 4587 }
4588
9dac77fa
AK		 4589 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4590 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4591 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4592 if (rc != X86EMUL_CONTINUE)
8b4caf66 4593 goto done;
9dac77fa 4594 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4595 }
4596
9dac77fa
AK		 4597 if (ctxt->src2.type == OP_MEM) {
4598 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4599 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4600 if (rc != X86EMUL_CONTINUE)
4601 goto done;
4602 }
4603
9dac77fa 4604 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4605 goto special_insn;
4606
4607
9dac77fa 4608 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4609 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4610 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4611 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4612 if (rc != X86EMUL_CONTINUE)
4613 goto done;
038e51de 4614 }
9dac77fa 4615 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4616
018a98db
AK		 4617special_insn:
4618
9dac77fa
AK		 4619 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4620 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4621 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4622 if (rc != X86EMUL_CONTINUE)
4623 goto done;
4624 }
4625
9dac77fa 4626 if (ctxt->execute) {
e28bbd44
AK		 4627 if (ctxt->d & Fastop) {
4628 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4629 rc = fastop(ctxt, fop);
4630 if (rc != X86EMUL_CONTINUE)
4631 goto done;
4632 goto writeback;
4633 }
9dac77fa 4634 rc = ctxt->execute(ctxt);
ef65c889
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637 goto writeback;
4638 }
4639
1ce19dc1 4640 if (ctxt->opcode_len == 2)
6aa8b732 4641 goto twobyte_insn;
0bc5eedb
BP		 4642 else if (ctxt->opcode_len == 3)
4643 goto threebyte_insn;
6aa8b732 4644
9dac77fa 4645 switch (ctxt->b) {
6aa8b732 4646 case 0x63: /* movsxd */
8b4caf66 4647 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4648 goto cannot_emulate;
9dac77fa 4649 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4650 break;
b2833e3c 4651 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4652 if (test_cc(ctxt->b, ctxt->eflags))
4653 jmp_rel(ctxt, ctxt->src.val);
018a98db 4654 break;
7e0b54b1 4655 case 0x8d: /* lea r16/r32, m */
9dac77fa 4656 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4657 break;
3d9e77df 4658 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4659 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4660 break;
e4f973ae
TY		 4661 rc = em_xchg(ctxt);
4662 break;
e8b6fa70 4663 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4664 switch (ctxt->op_bytes) {
4665 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4666 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4667 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4668 }
4669 break;
6e154e56 4670 case 0xcc: /* int3 */
5c5df76b
TY		 4671 rc = emulate_int(ctxt, 3);
4672 break;
6e154e56 4673 case 0xcd: /* int n */
9dac77fa 4674 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4675 break;
4676 case 0xce: /* into */
5c5df76b
TY		 4677 if (ctxt->eflags & EFLG_OF)
4678 rc = emulate_int(ctxt, 4);
6e154e56 4679 break;
1a52e051 4680 case 0xe9: /* jmp rel */
db5b0762 4681 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4682 jmp_rel(ctxt, ctxt->src.val);
4683 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4684 break;
111de5d6 4685 case 0xf4: /* hlt */
6c3287f7 4686 ctxt->ops->halt(ctxt);
19fdfa0d 4687 break;
111de5d6
AK		 4688 case 0xf5: /* cmc */
4689 /* complement carry flag from eflags reg */
4690 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4691 break;
4692 case 0xf8: /* clc */
4693 ctxt->eflags &= ~EFLG_CF;
111de5d6 4694 break;
8744aa9a
MG		 4695 case 0xf9: /* stc */
4696 ctxt->eflags |= EFLG_CF;
4697 break;
fb4616f4
MG		 4698 case 0xfc: /* cld */
4699 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4700 break;
4701 case 0xfd: /* std */
4702 ctxt->eflags |= EFLG_DF;
fb4616f4 4703 break;
91269b8f
AK		 4704 default:
4705 goto cannot_emulate;
6aa8b732 4706 }
018a98db 4707
7d9ddaed
AK		 4708 if (rc != X86EMUL_CONTINUE)
4709 goto done;
4710
018a98db 4711writeback:
fb32b1ed
AK		 4712 if (!(ctxt->d & NoWrite)) {
4713 rc = writeback(ctxt, &ctxt->dst);
4714 if (rc != X86EMUL_CONTINUE)
4715 goto done;
4716 }
4717 if (ctxt->d & SrcWrite) {
4718 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4719 rc = writeback(ctxt, &ctxt->src);
4720 if (rc != X86EMUL_CONTINUE)
4721 goto done;
4722 }
018a98db 4723
5cd21917
GN		 4724 /*
4725 * restore dst type in case the decoding will be reused
4726 * (happens for string instruction )
4727 */
9dac77fa 4728 ctxt->dst.type = saved_dst_type;
5cd21917 4729
9dac77fa 4730 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4731 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4732
9dac77fa 4733 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4734 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4735
9dac77fa 4736 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4737 unsigned int count;
9dac77fa 4738 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4739 if ((ctxt->d & SrcMask) == SrcSI)
4740 count = ctxt->src.count;
4741 else
4742 count = ctxt->dst.count;
4743 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4744 -count);
3e2f65d5 4745
d2ddd1c4
GN		 4746 if (!string_insn_completed(ctxt)) {
4747 /*
4748 * Re-enter guest when pio read ahead buffer is empty
4749 * or, if it is not used, after each 1024 iteration.
4750 */
dd856efa 4751 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4752 (r->end == 0 || r->end != r->pos)) {
4753 /*
4754 * Reset read cache. Usually happens before
4755 * decode, but since instruction is restarted
4756 * we have to do it here.
4757 */
9dac77fa 4758 ctxt->mem_read.end = 0;
dd856efa 4759 writeback_registers(ctxt);
d2ddd1c4
GN		 4760 return EMULATION_RESTART;
4761 }
4762 goto done; /* skip rip writeback */
0fa6ccbd 4763 }
5cd21917 4764 }
d2ddd1c4 4765
9dac77fa 4766 ctxt->eip = ctxt->_eip;
018a98db
AK		 4767
4768done:
da9cb575
AK		 4769 if (rc == X86EMUL_PROPAGATE_FAULT)
4770 ctxt->have_exception = true;
775fde86
JR		 4771 if (rc == X86EMUL_INTERCEPTED)
4772 return EMULATION_INTERCEPTED;
4773
dd856efa
AK		 4774 if (rc == X86EMUL_CONTINUE)
4775 writeback_registers(ctxt);
4776
d2ddd1c4 4777 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4778
4779twobyte_insn:
9dac77fa 4780 switch (ctxt->b) {
018a98db 4781 case 0x09: /* wbinvd */
cfb22375 4782 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4783 break;
4784 case 0x08: /* invd */
018a98db
AK		 4785 case 0x0d: /* GrpP (prefetch) */
4786 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4787 case 0x1f: /* nop */
018a98db
AK		 4788 break;
4789 case 0x20: /* mov cr, reg */
9dac77fa 4790 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4791 break;
6aa8b732 4792 case 0x21: /* mov from dr to reg */
9dac77fa 4793 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4794 break;
6aa8b732 4795 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4796 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4797 if (!test_cc(ctxt->b, ctxt->eflags))
4798 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4799 break;
b2833e3c 4800 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4801 if (test_cc(ctxt->b, ctxt->eflags))
4802 jmp_rel(ctxt, ctxt->src.val);
018a98db 4803 break;
ee45b58e 4804 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4805 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4806 break;
2a7c5b8b
GC		 4807 case 0xae: /* clflush */
4808 break;
6aa8b732 4809 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4810 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4811 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4812 : (u16) ctxt->src.val;
6aa8b732 4813 break;
6aa8b732 4814 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4815 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4816 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4817 (s16) ctxt->src.val;
6aa8b732 4818 break;
a012e65a 4819 case 0xc3: /* movnti */
9dac77fa
AK		 4820 ctxt->dst.bytes = ctxt->op_bytes;
4821 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4822 (u64) ctxt->src.val;
a012e65a 4823 break;
91269b8f
AK		 4824 default:
4825 goto cannot_emulate;
6aa8b732 4826 }
7d9ddaed 4827
0bc5eedb
BP		 4828threebyte_insn:
4829
7d9ddaed
AK		 4830 if (rc != X86EMUL_CONTINUE)
4831 goto done;
4832
6aa8b732
AK		 4833 goto writeback;
4834
4835cannot_emulate:
a0c0ab2f 4836 return EMULATION_FAILED;
6aa8b732 4837}
dd856efa
AK		 4838
4839void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4840{
4841 invalidate_registers(ctxt);
4842}
4843
4844void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4845{
4846 writeback_registers(ctxt);
4847}
Linux kernel - Deliverables
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