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KVM: x86 emulator: mark CMP, CMPS, SCAS, TEST as NoWrite
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 135/* Source 2 operand type */
d5ae7ce8 136#define Src2Shift (30)
4dd6a57d
AK		 137#define Src2None (OpNone << Src2Shift)
138#define Src2CL (OpCL << Src2Shift)
139#define Src2ImmByte (OpImmByte << Src2Shift)
140#define Src2One (OpOne << Src2Shift)
141#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 142#define Src2ES (OpES << Src2Shift)
143#define Src2CS (OpCS << Src2Shift)
144#define Src2SS (OpSS << Src2Shift)
145#define Src2DS (OpDS << Src2Shift)
146#define Src2FS (OpFS << Src2Shift)
147#define Src2GS (OpGS << Src2Shift)
4dd6a57d 148#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 149#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 150#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
151#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
152#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 153#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 154#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 155
d0e53325
AK		 156#define X2(x...) x, x
157#define X3(x...) X2(x), x
158#define X4(x...) X2(x), X2(x)
159#define X5(x...) X4(x), x
160#define X6(x...) X4(x), X2(x)
161#define X7(x...) X4(x), X3(x)
162#define X8(x...) X4(x), X4(x)
163#define X16(x...) X8(x), X8(x)
83babbca 164
e28bbd44
AK		 165#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
166#define FASTOP_SIZE 8
167
168/*
169 * fastop functions have a special calling convention:
170 *
171 * dst: [rdx]:rax (in/out)
172 * src: rbx (in/out)
173 * src2: rcx (in)
174 * flags: rflags (in/out)
175 *
176 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
177 * different operand sizes can be reached by calculation, rather than a jump
178 * table (which would be bigger than the code).
179 *
180 * fastop functions are declared as taking a never-defined fastop parameter,
181 * so they can't be called from C directly.
182 */
183
184struct fastop;
185
d65b1dee 186struct opcode {
b1ea50b2
AK		 187 u64 flags : 56;
188 u64 intercept : 8;
120df890 189 union {
ef65c889 190 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 191 const struct opcode *group;
192 const struct group_dual *gdual;
193 const struct gprefix *gprefix;
045a282c 194 const struct escape *esc;
e28bbd44 195 void (*fastop)(struct fastop *fake);
120df890 196 } u;
d09beabd 197 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 198};
199
200struct group_dual {
201 struct opcode mod012[8];
202 struct opcode mod3[8];
d65b1dee
AK		 203};
204
0d7cdee8
AK		 205struct gprefix {
206 struct opcode pfx_no;
207 struct opcode pfx_66;
208 struct opcode pfx_f2;
209 struct opcode pfx_f3;
210};
211
045a282c
GN		 212struct escape {
213 struct opcode op[8];
214 struct opcode high[64];
215};
216
6aa8b732 217/* EFLAGS bit definitions. */
d4c6a154
GN		 218#define EFLG_ID (1<<21)
219#define EFLG_VIP (1<<20)
220#define EFLG_VIF (1<<19)
221#define EFLG_AC (1<<18)
b1d86143
AP		 222#define EFLG_VM (1<<17)
223#define EFLG_RF (1<<16)
d4c6a154
GN		 224#define EFLG_IOPL (3<<12)
225#define EFLG_NT (1<<14)
6aa8b732
AK		 226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
b1d86143 228#define EFLG_IF (1<<9)
d4c6a154 229#define EFLG_TF (1<<8)
6aa8b732
AK		 230#define EFLG_SF (1<<7)
231#define EFLG_ZF (1<<6)
232#define EFLG_AF (1<<4)
233#define EFLG_PF (1<<2)
234#define EFLG_CF (1<<0)
235
62bd430e
MG		 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
237#define EFLG_RESERVED_ONE_MASK 2
238
dd856efa
AK		 239static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
240{
241 if (!(ctxt->regs_valid & (1 << nr))) {
242 ctxt->regs_valid |= 1 << nr;
243 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
244 }
245 return ctxt->_regs[nr];
246}
247
248static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
249{
250 ctxt->regs_valid |= 1 << nr;
251 ctxt->regs_dirty |= 1 << nr;
252 return &ctxt->_regs[nr];
253}
254
255static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 reg_read(ctxt, nr);
258 return reg_write(ctxt, nr);
259}
260
261static void writeback_registers(struct x86_emulate_ctxt *ctxt)
262{
263 unsigned reg;
264
265 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
266 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
267}
268
269static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
270{
271 ctxt->regs_dirty = 0;
272 ctxt->regs_valid = 0;
273}
274
6aa8b732
AK		 275/*
276 * Instruction emulation:
277 * Most instructions are emulated directly via a fragment of inline assembly
278 * code. This allows us to save/restore EFLAGS and thus very easily pick up
279 * any modified flags.
280 */
281
05b3e0c2 282#if defined(CONFIG_X86_64)
6aa8b732
AK		 283#define _LO32 "k" /* force 32-bit operand */
284#define _STK "%%rsp" /* stack pointer */
285#elif defined(__i386__)
286#define _LO32 "" /* force 32-bit operand */
287#define _STK "%%esp" /* stack pointer */
288#endif
289
290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
296/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 297#define _PRE_EFLAGS(_sav, _msk, _tmp) \
298 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
299 "movl %"_sav",%"_LO32 _tmp"; " \
300 "push %"_tmp"; " \
301 "push %"_tmp"; " \
302 "movl %"_msk",%"_LO32 _tmp"; " \
303 "andl %"_LO32 _tmp",("_STK"); " \
304 "pushf; " \
305 "notl %"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
308 "pop %"_tmp"; " \
309 "orl %"_LO32 _tmp",("_STK"); " \
310 "popf; " \
311 "pop %"_sav"; "
6aa8b732
AK		 312
313/* After executing instruction: write-back necessary bits in EFLAGS. */
314#define _POST_EFLAGS(_sav, _msk, _tmp) \
315 /* _sav |= EFLAGS & _msk; */ \
316 "pushf; " \
317 "pop %"_tmp"; " \
318 "andl %"_msk",%"_LO32 _tmp"; " \
319 "orl %"_LO32 _tmp",%"_sav"; "
320
dda96d8f
AK		 321#ifdef CONFIG_X86_64
322#define ON64(x) x
323#else
324#define ON64(x)
325#endif
326
a31b9cea 327#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 328 do { \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "2") \
331 _op _suffix " %"_x"3,%1; " \
332 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 333 : "=m" ((ctxt)->eflags), \
334 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 335 "=&r" (_tmp) \
a31b9cea 336 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 337 } while (0)
6b7ad61f
AK		 338
339
6aa8b732 340/* Raw emulation: instruction has two explicit operands. */
a31b9cea 341#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 342 do { \
343 unsigned long _tmp; \
344 \
a31b9cea 345 switch ((ctxt)->dst.bytes) { \
6b7ad61f 346 case 2: \
a31b9cea 347 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 348 break; \
349 case 4: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 351 break; \
352 case 8: \
a31b9cea 353 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 354 break; \
355 } \
6aa8b732
AK		 356 } while (0)
357
a31b9cea 358#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 359 do { \
6b7ad61f 360 unsigned long _tmp; \
a31b9cea 361 switch ((ctxt)->dst.bytes) { \
6aa8b732 362 case 1: \
a31b9cea 363 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 364 break; \
365 default: \
a31b9cea 366 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 367 _wx, _wy, _lx, _ly, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 373#define emulate_2op_SrcB(ctxt, _op) \
374 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 375
376/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 377#define emulate_2op_SrcV(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 379
380/* Source operand is word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV_nobyte(ctxt, _op) \
382 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 383
d175226a 384/* Instruction has three operands and one operand is stored in ECX register */
29053a60 385#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 386 do { \
387 unsigned long _tmp; \
761441b9
AK		 388 _type _clv = (ctxt)->src2.val; \
389 _type _srcv = (ctxt)->src.val; \
390 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 391 \
392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "5", "2") \
394 _op _suffix " %4,%1 \n" \
395 _POST_EFLAGS("0", "5", "2") \
761441b9 396 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 397 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
398 ); \
399 \
761441b9
AK		 400 (ctxt)->src2.val = (unsigned long) _clv; \
401 (ctxt)->src2.val = (unsigned long) _srcv; \
402 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 403 } while (0)
404
761441b9 405#define emulate_2op_cl(ctxt, _op) \
7295261c 406 do { \
761441b9 407 switch ((ctxt)->dst.bytes) { \
7295261c 408 case 2: \
29053a60 409 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 410 break; \
411 case 4: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 413 break; \
414 case 8: \
29053a60 415 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 416 break; \
417 } \
d175226a
GT		 418 } while (0)
419
d1eef45d 420#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 421 do { \
422 unsigned long _tmp; \
423 \
dda96d8f
AK		 424 __asm__ __volatile__ ( \
425 _PRE_EFLAGS("0", "3", "2") \
426 _op _suffix " %1; " \
427 _POST_EFLAGS("0", "3", "2") \
d1eef45d 428 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 429 "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK)); \
431 } while (0)
432
433/* Instruction has only one explicit operand (no source operand). */
d1eef45d 434#define emulate_1op(ctxt, _op) \
dda96d8f 435 do { \
d1eef45d
AK		 436 switch ((ctxt)->dst.bytes) { \
437 case 1: __emulate_1op(ctxt, _op, "b"); break; \
438 case 2: __emulate_1op(ctxt, _op, "w"); break; \
439 case 4: __emulate_1op(ctxt, _op, "l"); break; \
440 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 441 } \
442 } while (0)
443
b7d491e7
AK		 444#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
445#define FOP_RET "ret \n\t"
446
447#define FOP_START(op) \
448 extern void em_##op(struct fastop *fake); \
449 asm(".pushsection .text, \"ax\" \n\t" \
450 ".global em_" #op " \n\t" \
451 FOP_ALIGN \
452 "em_" #op ": \n\t"
453
454#define FOP_END \
455 ".popsection")
456
457#define FOP1E(op, dst) \
458 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
459
460#define FASTOP1(op) \
461 FOP_START(op) \
462 FOP1E(op##b, al) \
463 FOP1E(op##w, ax) \
464 FOP1E(op##l, eax) \
465 ON64(FOP1E(op##q, rax)) \
466 FOP_END
467
e8f2b1d6 468#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 469 do { \
470 unsigned long _tmp; \
dd856efa
AK		 471 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
472 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 473 \
474 __asm__ __volatile__ ( \
475 _PRE_EFLAGS("0", "5", "1") \
476 "1: \n\t" \
477 _op _suffix " %6; " \
478 "2: \n\t" \
479 _POST_EFLAGS("0", "5", "1") \
480 ".pushsection .fixup,\"ax\" \n\t" \
481 "3: movb $1, %4 \n\t" \
482 "jmp 2b \n\t" \
483 ".popsection \n\t" \
484 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 485 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
486 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 487 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 488 } while (0)
489
3f9f53b0 490/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 491#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 492 do { \
e8f2b1d6 493 switch((ctxt)->src.bytes) { \
7295261c 494 case 1: \
e8f2b1d6 495 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 496 break; \
497 case 2: \
e8f2b1d6 498 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 499 break; \
500 case 4: \
e8f2b1d6 501 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 502 break; \
503 case 8: ON64( \
e8f2b1d6 504 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 505 break; \
506 } \
507 } while (0)
508
8a76d7f2
JR		 509static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
510 enum x86_intercept intercept,
511 enum x86_intercept_stage stage)
512{
513 struct x86_instruction_info info = {
514 .intercept = intercept,
9dac77fa
AK		 515 .rep_prefix = ctxt->rep_prefix,
516 .modrm_mod = ctxt->modrm_mod,
517 .modrm_reg = ctxt->modrm_reg,
518 .modrm_rm = ctxt->modrm_rm,
519 .src_val = ctxt->src.val64,
520 .src_bytes = ctxt->src.bytes,
521 .dst_bytes = ctxt->dst.bytes,
522 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 523 .next_rip = ctxt->eip,
524 };
525
2953538e 526 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 527}
528
f47cfa31
AK		 529static void assign_masked(ulong *dest, ulong src, ulong mask)
530{
531 *dest = (*dest & ~mask) | (src & mask);
532}
533
9dac77fa 534static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 535{
9dac77fa 536 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 537}
538
f47cfa31
AK		 539static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
540{
541 u16 sel;
542 struct desc_struct ss;
543
544 if (ctxt->mode == X86EMUL_MODE_PROT64)
545 return ~0UL;
546 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
547 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
548}
549
612e89f0
AK		 550static int stack_size(struct x86_emulate_ctxt *ctxt)
551{
552 return (__fls(stack_mask(ctxt)) + 1) >> 3;
553}
554
6aa8b732 555/* Access/update address held in a register, based on addressing mode. */
e4706772 556static inline unsigned long
9dac77fa 557address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 558{
9dac77fa 559 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 560 return reg;
561 else
9dac77fa 562 return reg & ad_mask(ctxt);
e4706772
HH		 563}
564
565static inline unsigned long
9dac77fa 566register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 567{
9dac77fa 568 return address_mask(ctxt, reg);
e4706772
HH		 569}
570
5ad105e5
AK		 571static void masked_increment(ulong *reg, ulong mask, int inc)
572{
573 assign_masked(reg, *reg + inc, mask);
574}
575
7a957275 576static inline void
9dac77fa 577register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 578{
5ad105e5
AK		 579 ulong mask;
580
9dac77fa 581 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 582 mask = ~0UL;
7a957275 583 else
5ad105e5
AK		 584 mask = ad_mask(ctxt);
585 masked_increment(reg, mask, inc);
586}
587
588static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
589{
dd856efa 590 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 591}
6aa8b732 592
9dac77fa 593static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 594{
9dac77fa 595 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 596}
098c937b 597
56697687
AK		 598static u32 desc_limit_scaled(struct desc_struct *desc)
599{
600 u32 limit = get_desc_limit(desc);
601
602 return desc->g ? (limit << 12) | 0xfff : limit;
603}
604
9dac77fa 605static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 606{
9dac77fa
AK		 607 ctxt->has_seg_override = true;
608 ctxt->seg_override = seg;
7a5b56df
AK		 609}
610
7b105ca2 611static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 612{
613 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
614 return 0;
615
7b105ca2 616 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 617}
618
9dac77fa 619static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 620{
9dac77fa 621 if (!ctxt->has_seg_override)
7a5b56df
AK		 622 return 0;
623
9dac77fa 624 return ctxt->seg_override;
7a5b56df
AK		 625}
626
35d3d4a1
AK		 627static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
628 u32 error, bool valid)
54b8486f 629{
da9cb575
AK		 630 ctxt->exception.vector = vec;
631 ctxt->exception.error_code = error;
632 ctxt->exception.error_code_valid = valid;
35d3d4a1 633 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 634}
635
3b88e41a
JR		 636static int emulate_db(struct x86_emulate_ctxt *ctxt)
637{
638 return emulate_exception(ctxt, DB_VECTOR, 0, false);
639}
640
35d3d4a1 641static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 642{
35d3d4a1 643 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 644}
645
618ff15d
AK		 646static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
647{
648 return emulate_exception(ctxt, SS_VECTOR, err, true);
649}
650
35d3d4a1 651static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 652{
35d3d4a1 653 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 654}
655
35d3d4a1 656static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 657{
35d3d4a1 658 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 659}
660
34d1f490
AK		 661static int emulate_de(struct x86_emulate_ctxt *ctxt)
662{
35d3d4a1 663 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 664}
665
1253791d
AK		 666static int emulate_nm(struct x86_emulate_ctxt *ctxt)
667{
668 return emulate_exception(ctxt, NM_VECTOR, 0, false);
669}
670
1aa36616
AK		 671static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
672{
673 u16 selector;
674 struct desc_struct desc;
675
676 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
677 return selector;
678}
679
680static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
681 unsigned seg)
682{
683 u16 dummy;
684 u32 base3;
685 struct desc_struct desc;
686
687 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
688 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
689}
690
1c11b376
AK		 691/*
692 * x86 defines three classes of vector instructions: explicitly
693 * aligned, explicitly unaligned, and the rest, which change behaviour
694 * depending on whether they're AVX encoded or not.
695 *
696 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
697 * subject to the same check.
698 */
699static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
700{
701 if (likely(size < 16))
702 return false;
703
704 if (ctxt->d & Aligned)
705 return true;
706 else if (ctxt->d & Unaligned)
707 return false;
708 else if (ctxt->d & Avx)
709 return false;
710 else
711 return true;
712}
713
3d9b938e 714static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 715 struct segmented_address addr,
3d9b938e 716 unsigned size, bool write, bool fetch,
52fd8b44
AK		 717 ulong *linear)
718{
618ff15d
AK		 719 struct desc_struct desc;
720 bool usable;
52fd8b44 721 ulong la;
618ff15d 722 u32 lim;
1aa36616 723 u16 sel;
3a78a4f4 724 unsigned cpl;
52fd8b44 725
7b105ca2 726 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 727 switch (ctxt->mode) {
618ff15d
AK		 728 case X86EMUL_MODE_PROT64:
729 if (((signed long)la << 16) >> 16 != la)
730 return emulate_gp(ctxt, 0);
731 break;
732 default:
1aa36616
AK		 733 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
734 addr.seg);
618ff15d
AK		 735 if (!usable)
736 goto bad;
58b7825b
GN		 737 /* code segment in protected mode or read-only data segment */
738 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
739 || !(desc.type & 2)) && write)
618ff15d
AK		 740 goto bad;
741 /* unreadable code segment */
3d9b938e 742 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 743 goto bad;
744 lim = desc_limit_scaled(&desc);
745 if ((desc.type & 8) || !(desc.type & 4)) {
746 /* expand-up segment */
747 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
748 goto bad;
749 } else {
fc058680 750 /* expand-down segment */
618ff15d
AK		 751 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
752 goto bad;
753 lim = desc.d ? 0xffffffff : 0xffff;
754 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
755 goto bad;
756 }
717746e3 757 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 758 if (!(desc.type & 8)) {
759 /* data segment */
760 if (cpl > desc.dpl)
761 goto bad;
762 } else if ((desc.type & 8) && !(desc.type & 4)) {
763 /* nonconforming code segment */
764 if (cpl != desc.dpl)
765 goto bad;
766 } else if ((desc.type & 8) && (desc.type & 4)) {
767 /* conforming code segment */
768 if (cpl < desc.dpl)
769 goto bad;
770 }
771 break;
772 }
9dac77fa 773 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 774 la &= (u32)-1;
1c11b376
AK		 775 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
776 return emulate_gp(ctxt, 0);
52fd8b44
AK		 777 *linear = la;
778 return X86EMUL_CONTINUE;
618ff15d
AK		 779bad:
780 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 781 return emulate_ss(ctxt, sel);
618ff15d 782 else
0afbe2f8 783 return emulate_gp(ctxt, sel);
52fd8b44
AK		 784}
785
3d9b938e
NE		 786static int linearize(struct x86_emulate_ctxt *ctxt,
787 struct segmented_address addr,
788 unsigned size, bool write,
789 ulong *linear)
790{
791 return __linearize(ctxt, addr, size, write, false, linear);
792}
793
794
3ca3ac4d
AK		 795static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
796 struct segmented_address addr,
797 void *data,
798 unsigned size)
799{
9fa088f4
AK		 800 int rc;
801 ulong linear;
802
83b8795a 803 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 804 if (rc != X86EMUL_CONTINUE)
805 return rc;
0f65dd70 806 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 807}
808
807941b1
TY		 809/*
810 * Fetch the next byte of the instruction being emulated which is pointed to
811 * by ctxt->_eip, then increment ctxt->_eip.
812 *
813 * Also prefetch the remaining bytes of the instruction without crossing page
814 * boundary if they are not in fetch_cache yet.
815 */
816static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 817{
9dac77fa 818 struct fetch_cache *fc = &ctxt->fetch;
62266869 819 int rc;
2fb53ad8 820 int size, cur_size;
62266869 821
807941b1 822 if (ctxt->_eip == fc->end) {
3d9b938e 823 unsigned long linear;
807941b1
TY		 824 struct segmented_address addr = { .seg = VCPU_SREG_CS,
825 .ea = ctxt->_eip };
2fb53ad8 826 cur_size = fc->end - fc->start;
807941b1
TY		 827 size = min(15UL - cur_size,
828 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 829 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 830 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 831 return rc;
ef5d75cc
TY		 832 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
833 size, &ctxt->exception);
7d88bb48 834 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 835 return rc;
2fb53ad8 836 fc->end += size;
62266869 837 }
807941b1
TY		 838 *dest = fc->data[ctxt->_eip - fc->start];
839 ctxt->_eip++;
3e2815e9 840 return X86EMUL_CONTINUE;
62266869
AK		 841}
842
843static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 844 void *dest, unsigned size)
62266869 845{
3e2815e9 846 int rc;
62266869 847
eb3c79e6 848 /* x86 instructions are limited to 15 bytes. */
7d88bb48 849 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 850 return X86EMUL_UNHANDLEABLE;
62266869 851 while (size--) {
807941b1 852 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 853 if (rc != X86EMUL_CONTINUE)
62266869
AK		 854 return rc;
855 }
3e2815e9 856 return X86EMUL_CONTINUE;
62266869
AK		 857}
858
67cbc90d 859/* Fetch next part of the instruction being emulated. */
e85a1085 860#define insn_fetch(_type, _ctxt) \
67cbc90d 861({ unsigned long _x; \
e85a1085 862 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 863 if (rc != X86EMUL_CONTINUE) \
864 goto done; \
67cbc90d
TY		 865 (_type)_x; \
866})
867
807941b1
TY		 868#define insn_fetch_arr(_arr, _size, _ctxt) \
869({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 870 if (rc != X86EMUL_CONTINUE) \
871 goto done; \
67cbc90d
TY		 872})
873
1e3c5cb0
RR		 874/*
875 * Given the 'reg' portion of a ModRM byte, and a register block, return a
876 * pointer into the block that addresses the relevant register.
877 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
878 */
dd856efa 879static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 880 int highbyte_regs)
6aa8b732
AK		 881{
882 void *p;
883
6aa8b732 884 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 885 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
886 else
887 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 888 return p;
889}
890
891static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 892 struct segmented_address addr,
6aa8b732
AK		 893 u16 *size, unsigned long *address, int op_bytes)
894{
895 int rc;
896
897 if (op_bytes == 2)
898 op_bytes = 3;
899 *address = 0;
3ca3ac4d 900 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 901 if (rc != X86EMUL_CONTINUE)
6aa8b732 902 return rc;
30b31ab6 903 addr.ea += 2;
3ca3ac4d 904 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 905 return rc;
906}
907
bbe9abbd
NK		 908static int test_cc(unsigned int condition, unsigned int flags)
909{
910 int rc = 0;
911
912 switch ((condition & 15) >> 1) {
913 case 0: /* o */
914 rc |= (flags & EFLG_OF);
915 break;
916 case 1: /* b/c/nae */
917 rc |= (flags & EFLG_CF);
918 break;
919 case 2: /* z/e */
920 rc |= (flags & EFLG_ZF);
921 break;
922 case 3: /* be/na */
923 rc |= (flags & (EFLG_CF|EFLG_ZF));
924 break;
925 case 4: /* s */
926 rc |= (flags & EFLG_SF);
927 break;
928 case 5: /* p/pe */
929 rc |= (flags & EFLG_PF);
930 break;
931 case 7: /* le/ng */
932 rc |= (flags & EFLG_ZF);
933 /* fall through */
934 case 6: /* l/nge */
935 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
936 break;
937 }
938
939 /* Odd condition identifiers (lsb == 1) have inverted sense. */
940 return (!!rc ^ (condition & 1));
941}
942
91ff3cb4
AK		 943static void fetch_register_operand(struct operand *op)
944{
945 switch (op->bytes) {
946 case 1:
947 op->val = *(u8 *)op->addr.reg;
948 break;
949 case 2:
950 op->val = *(u16 *)op->addr.reg;
951 break;
952 case 4:
953 op->val = *(u32 *)op->addr.reg;
954 break;
955 case 8:
956 op->val = *(u64 *)op->addr.reg;
957 break;
958 }
959}
960
1253791d
AK		 961static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
89a87c67
MK		 965 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
966 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
967 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
968 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
969 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
970 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
971 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
972 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 973#ifdef CONFIG_X86_64
89a87c67
MK		 974 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
975 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
976 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
977 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
978 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
979 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
980 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
981 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 982#endif
983 default: BUG();
984 }
985 ctxt->ops->put_fpu(ctxt);
986}
987
988static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
989 int reg)
990{
991 ctxt->ops->get_fpu(ctxt);
992 switch (reg) {
89a87c67
MK		 993 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
994 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
995 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
996 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
997 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
998 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
999 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1000 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1001#ifdef CONFIG_X86_64
89a87c67
MK		 1002 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1003 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1004 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1005 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1006 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1007 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1008 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1009 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1010#endif
1011 default: BUG();
1012 }
1013 ctxt->ops->put_fpu(ctxt);
1014}
1015
cbe2c9d3
AK		 1016static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1017{
1018 ctxt->ops->get_fpu(ctxt);
1019 switch (reg) {
1020 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1021 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1022 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1023 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1024 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1025 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1026 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1027 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1028 default: BUG();
1029 }
1030 ctxt->ops->put_fpu(ctxt);
1031}
1032
1033static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1034{
1035 ctxt->ops->get_fpu(ctxt);
1036 switch (reg) {
1037 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1038 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1039 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1040 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1041 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1042 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1043 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1044 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1045 default: BUG();
1046 }
1047 ctxt->ops->put_fpu(ctxt);
1048}
1049
045a282c
GN		 1050static int em_fninit(struct x86_emulate_ctxt *ctxt)
1051{
1052 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1053 return emulate_nm(ctxt);
1054
1055 ctxt->ops->get_fpu(ctxt);
1056 asm volatile("fninit");
1057 ctxt->ops->put_fpu(ctxt);
1058 return X86EMUL_CONTINUE;
1059}
1060
1061static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1062{
1063 u16 fcw;
1064
1065 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1066 return emulate_nm(ctxt);
1067
1068 ctxt->ops->get_fpu(ctxt);
1069 asm volatile("fnstcw %0": "+m"(fcw));
1070 ctxt->ops->put_fpu(ctxt);
1071
1072 /* force 2 byte destination */
1073 ctxt->dst.bytes = 2;
1074 ctxt->dst.val = fcw;
1075
1076 return X86EMUL_CONTINUE;
1077}
1078
1079static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1080{
1081 u16 fsw;
1082
1083 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1084 return emulate_nm(ctxt);
1085
1086 ctxt->ops->get_fpu(ctxt);
1087 asm volatile("fnstsw %0": "+m"(fsw));
1088 ctxt->ops->put_fpu(ctxt);
1089
1090 /* force 2 byte destination */
1091 ctxt->dst.bytes = 2;
1092 ctxt->dst.val = fsw;
1093
1094 return X86EMUL_CONTINUE;
1095}
1096
1253791d 1097static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1098 struct operand *op)
3c118e24 1099{
9dac77fa
AK		 1100 unsigned reg = ctxt->modrm_reg;
1101 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1102
9dac77fa
AK		 1103 if (!(ctxt->d & ModRM))
1104 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1105
9dac77fa 1106 if (ctxt->d & Sse) {
1253791d
AK		 1107 op->type = OP_XMM;
1108 op->bytes = 16;
1109 op->addr.xmm = reg;
1110 read_sse_reg(ctxt, &op->vec_val, reg);
1111 return;
1112 }
cbe2c9d3
AK		 1113 if (ctxt->d & Mmx) {
1114 reg &= 7;
1115 op->type = OP_MM;
1116 op->bytes = 8;
1117 op->addr.mm = reg;
1118 return;
1119 }
1253791d 1120
3c118e24 1121 op->type = OP_REG;
2adb5ad9 1122 if (ctxt->d & ByteOp) {
dd856efa 1123 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1124 op->bytes = 1;
1125 } else {
dd856efa 1126 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1127 op->bytes = ctxt->op_bytes;
3c118e24 1128 }
91ff3cb4 1129 fetch_register_operand(op);
3c118e24
AK		 1130 op->orig_val = op->val;
1131}
1132
a6e3407b
AK		 1133static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1134{
1135 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1136 ctxt->modrm_seg = VCPU_SREG_SS;
1137}
1138
1c73ef66 1139static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1140 struct operand *op)
1c73ef66 1141{
1c73ef66 1142 u8 sib;
f5b4edcd 1143 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1144 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1145 ulong modrm_ea = 0;
1c73ef66 1146
9dac77fa
AK		 1147 if (ctxt->rex_prefix) {
1148 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1149 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1150 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1151 }
1152
9dac77fa
AK		 1153 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1154 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1155 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1156 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1157
9dac77fa 1158 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1159 op->type = OP_REG;
9dac77fa 1160 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1161 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1162 if (ctxt->d & Sse) {
1253791d
AK		 1163 op->type = OP_XMM;
1164 op->bytes = 16;
9dac77fa
AK		 1165 op->addr.xmm = ctxt->modrm_rm;
1166 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1167 return rc;
1168 }
cbe2c9d3
AK		 1169 if (ctxt->d & Mmx) {
1170 op->type = OP_MM;
1171 op->bytes = 8;
1172 op->addr.xmm = ctxt->modrm_rm & 7;
1173 return rc;
1174 }
2dbd0dd7 1175 fetch_register_operand(op);
1c73ef66
AK		 1176 return rc;
1177 }
1178
2dbd0dd7
AK		 1179 op->type = OP_MEM;
1180
9dac77fa 1181 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1182 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1183 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1184 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1185 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1186
1187 /* 16-bit ModR/M decode. */
9dac77fa 1188 switch (ctxt->modrm_mod) {
1c73ef66 1189 case 0:
9dac77fa 1190 if (ctxt->modrm_rm == 6)
e85a1085 1191 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1192 break;
1193 case 1:
e85a1085 1194 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1195 break;
1196 case 2:
e85a1085 1197 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1198 break;
1199 }
9dac77fa 1200 switch (ctxt->modrm_rm) {
1c73ef66 1201 case 0:
2dbd0dd7 1202 modrm_ea += bx + si;
1c73ef66
AK		 1203 break;
1204 case 1:
2dbd0dd7 1205 modrm_ea += bx + di;
1c73ef66
AK		 1206 break;
1207 case 2:
2dbd0dd7 1208 modrm_ea += bp + si;
1c73ef66
AK		 1209 break;
1210 case 3:
2dbd0dd7 1211 modrm_ea += bp + di;
1c73ef66
AK		 1212 break;
1213 case 4:
2dbd0dd7 1214 modrm_ea += si;
1c73ef66
AK		 1215 break;
1216 case 5:
2dbd0dd7 1217 modrm_ea += di;
1c73ef66
AK		 1218 break;
1219 case 6:
9dac77fa 1220 if (ctxt->modrm_mod != 0)
2dbd0dd7 1221 modrm_ea += bp;
1c73ef66
AK		 1222 break;
1223 case 7:
2dbd0dd7 1224 modrm_ea += bx;
1c73ef66
AK		 1225 break;
1226 }
9dac77fa
AK		 1227 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1228 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1229 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1230 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1231 } else {
1232 /* 32/64-bit ModR/M decode. */
9dac77fa 1233 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1234 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1235 index_reg |= (sib >> 3) & 7;
1236 base_reg |= sib & 7;
1237 scale = sib >> 6;
1238
9dac77fa 1239 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1240 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1241 else {
dd856efa 1242 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1243 adjust_modrm_seg(ctxt, base_reg);
1244 }
dc71d0f1 1245 if (index_reg != 4)
dd856efa 1246 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1247 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1248 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1249 ctxt->rip_relative = 1;
a6e3407b
AK		 1250 } else {
1251 base_reg = ctxt->modrm_rm;
dd856efa 1252 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1253 adjust_modrm_seg(ctxt, base_reg);
1254 }
9dac77fa 1255 switch (ctxt->modrm_mod) {
1c73ef66 1256 case 0:
9dac77fa 1257 if (ctxt->modrm_rm == 5)
e85a1085 1258 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1259 break;
1260 case 1:
e85a1085 1261 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1262 break;
1263 case 2:
e85a1085 1264 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1265 break;
1266 }
1267 }
90de84f5 1268 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1269done:
1270 return rc;
1271}
1272
1273static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1274 struct operand *op)
1c73ef66 1275{
3e2815e9 1276 int rc = X86EMUL_CONTINUE;
1c73ef66 1277
2dbd0dd7 1278 op->type = OP_MEM;
9dac77fa 1279 switch (ctxt->ad_bytes) {
1c73ef66 1280 case 2:
e85a1085 1281 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1282 break;
1283 case 4:
e85a1085 1284 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1285 break;
1286 case 8:
e85a1085 1287 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1288 break;
1289 }
1290done:
1291 return rc;
1292}
1293
9dac77fa 1294static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1295{
7129eeca 1296 long sv = 0, mask;
35c843c4 1297
9dac77fa
AK		 1298 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1299 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1300
9dac77fa
AK		 1301 if (ctxt->src.bytes == 2)
1302 sv = (s16)ctxt->src.val & (s16)mask;
1303 else if (ctxt->src.bytes == 4)
1304 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1305
9dac77fa 1306 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1307 }
ba7ff2b7
WY		 1308
1309 /* only subword offset */
9dac77fa 1310 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1311}
1312
dde7e6d1 1313static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1314 unsigned long addr, void *dest, unsigned size)
6aa8b732 1315{
dde7e6d1 1316 int rc;
9dac77fa 1317 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1318
f23b070e
XG		 1319 if (mc->pos < mc->end)
1320 goto read_cached;
6aa8b732 1321
f23b070e
XG		 1322 WARN_ON((mc->end + size) >= sizeof(mc->data));
1323
1324 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1325 &ctxt->exception);
1326 if (rc != X86EMUL_CONTINUE)
1327 return rc;
1328
1329 mc->end += size;
1330
1331read_cached:
1332 memcpy(dest, mc->data + mc->pos, size);
1333 mc->pos += size;
dde7e6d1
AK		 1334 return X86EMUL_CONTINUE;
1335}
6aa8b732 1336
3ca3ac4d
AK		 1337static int segmented_read(struct x86_emulate_ctxt *ctxt,
1338 struct segmented_address addr,
1339 void *data,
1340 unsigned size)
1341{
9fa088f4
AK		 1342 int rc;
1343 ulong linear;
1344
83b8795a 1345 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1346 if (rc != X86EMUL_CONTINUE)
1347 return rc;
7b105ca2 1348 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1349}
1350
1351static int segmented_write(struct x86_emulate_ctxt *ctxt,
1352 struct segmented_address addr,
1353 const void *data,
1354 unsigned size)
1355{
9fa088f4
AK		 1356 int rc;
1357 ulong linear;
1358
83b8795a 1359 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1360 if (rc != X86EMUL_CONTINUE)
1361 return rc;
0f65dd70
AK		 1362 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1363 &ctxt->exception);
3ca3ac4d
AK		 1364}
1365
1366static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1367 struct segmented_address addr,
1368 const void *orig_data, const void *data,
1369 unsigned size)
1370{
9fa088f4
AK		 1371 int rc;
1372 ulong linear;
1373
83b8795a 1374 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1375 if (rc != X86EMUL_CONTINUE)
1376 return rc;
0f65dd70
AK		 1377 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1378 size, &ctxt->exception);
3ca3ac4d
AK		 1379}
1380
dde7e6d1 1381static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1382 unsigned int size, unsigned short port,
1383 void *dest)
1384{
9dac77fa 1385 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1386
dde7e6d1 1387 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1388 unsigned int in_page, n;
9dac77fa 1389 unsigned int count = ctxt->rep_prefix ?
dd856efa 1390 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1391 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1392 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1393 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1394 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1395 count);
1396 if (n == 0)
1397 n = 1;
1398 rc->pos = rc->end = 0;
7b105ca2 1399 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1400 return 0;
1401 rc->end = n * size;
6aa8b732
AK		 1402 }
1403
b3356bf0
GN		 1404 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1405 ctxt->dst.data = rc->data + rc->pos;
1406 ctxt->dst.type = OP_MEM_STR;
1407 ctxt->dst.count = (rc->end - rc->pos) / size;
1408 rc->pos = rc->end;
1409 } else {
1410 memcpy(dest, rc->data + rc->pos, size);
1411 rc->pos += size;
1412 }
dde7e6d1
AK		 1413 return 1;
1414}
6aa8b732 1415
7f3d35fd
KW		 1416static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1417 u16 index, struct desc_struct *desc)
1418{
1419 struct desc_ptr dt;
1420 ulong addr;
1421
1422 ctxt->ops->get_idt(ctxt, &dt);
1423
1424 if (dt.size < index * 8 + 7)
1425 return emulate_gp(ctxt, index << 3 | 0x2);
1426
1427 addr = dt.address + index * 8;
1428 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1429 &ctxt->exception);
1430}
1431
dde7e6d1 1432static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1433 u16 selector, struct desc_ptr *dt)
1434{
0225fb50 1435 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1436
dde7e6d1
AK		 1437 if (selector & 1 << 2) {
1438 struct desc_struct desc;
1aa36616
AK		 1439 u16 sel;
1440
dde7e6d1 1441 memset (dt, 0, sizeof *dt);
1aa36616 1442 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1443 return;
e09d082c 1444
dde7e6d1
AK		 1445 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1446 dt->address = get_desc_base(&desc);
1447 } else
4bff1e86 1448 ops->get_gdt(ctxt, dt);
dde7e6d1 1449}
120df890 1450
dde7e6d1
AK		 1451/* allowed just for 8 bytes segments */
1452static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1453 u16 selector, struct desc_struct *desc,
1454 ulong *desc_addr_p)
dde7e6d1
AK		 1455{
1456 struct desc_ptr dt;
1457 u16 index = selector >> 3;
dde7e6d1 1458 ulong addr;
120df890 1459
7b105ca2 1460 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1461
35d3d4a1
AK		 1462 if (dt.size < index * 8 + 7)
1463 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1464
e919464b 1465 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1466 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1467 &ctxt->exception);
dde7e6d1 1468}
ef65c889 1469
dde7e6d1
AK		 1470/* allowed just for 8 bytes segments */
1471static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1472 u16 selector, struct desc_struct *desc)
1473{
1474 struct desc_ptr dt;
1475 u16 index = selector >> 3;
dde7e6d1 1476 ulong addr;
6aa8b732 1477
7b105ca2 1478 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1479
35d3d4a1
AK		 1480 if (dt.size < index * 8 + 7)
1481 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1482
dde7e6d1 1483 addr = dt.address + index * 8;
7b105ca2
TY		 1484 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1485 &ctxt->exception);
dde7e6d1 1486}
c7e75a3d 1487
5601d05b 1488/* Does not support long mode */
dde7e6d1 1489static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1490 u16 selector, int seg)
1491{
869be99c 1492 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1493 u8 dpl, rpl, cpl;
1494 unsigned err_vec = GP_VECTOR;
1495 u32 err_code = 0;
1496 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1497 ulong desc_addr;
dde7e6d1 1498 int ret;
03ebebeb 1499 u16 dummy;
69f55cb1 1500
dde7e6d1 1501 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1502
dde7e6d1
AK		 1503 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1504 || ctxt->mode == X86EMUL_MODE_REAL) {
1505 /* set real mode segment descriptor */
03ebebeb 1506 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1507 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1508 goto load;
1509 }
1510
79d5b4c3
AK		 1511 rpl = selector & 3;
1512 cpl = ctxt->ops->cpl(ctxt);
1513
1514 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1515 if ((seg == VCPU_SREG_CS
1516 || (seg == VCPU_SREG_SS
1517 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1518 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1519 && null_selector)
1520 goto exception;
1521
1522 /* TR should be in GDT only */
1523 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1524 goto exception;
1525
1526 if (null_selector) /* for NULL selector skip all following checks */
1527 goto load;
1528
e919464b 1529 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1530 if (ret != X86EMUL_CONTINUE)
1531 return ret;
1532
1533 err_code = selector & 0xfffc;
1534 err_vec = GP_VECTOR;
1535
fc058680 1536 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1537 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1538 goto exception;
1539
1540 if (!seg_desc.p) {
1541 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1542 goto exception;
1543 }
1544
dde7e6d1 1545 dpl = seg_desc.dpl;
dde7e6d1
AK		 1546
1547 switch (seg) {
1548 case VCPU_SREG_SS:
1549 /*
1550 * segment is not a writable data segment or segment
1551 * selector's RPL != CPL or segment selector's RPL != CPL
1552 */
1553 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1554 goto exception;
6aa8b732 1555 break;
dde7e6d1
AK		 1556 case VCPU_SREG_CS:
1557 if (!(seg_desc.type & 8))
1558 goto exception;
1559
1560 if (seg_desc.type & 4) {
1561 /* conforming */
1562 if (dpl > cpl)
1563 goto exception;
1564 } else {
1565 /* nonconforming */
1566 if (rpl > cpl || dpl != cpl)
1567 goto exception;
1568 }
1569 /* CS(RPL) <- CPL */
1570 selector = (selector & 0xfffc) | cpl;
6aa8b732 1571 break;
dde7e6d1
AK		 1572 case VCPU_SREG_TR:
1573 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1574 goto exception;
869be99c
AK		 1575 old_desc = seg_desc;
1576 seg_desc.type |= 2; /* busy */
1577 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1578 sizeof(seg_desc), &ctxt->exception);
1579 if (ret != X86EMUL_CONTINUE)
1580 return ret;
dde7e6d1
AK		 1581 break;
1582 case VCPU_SREG_LDTR:
1583 if (seg_desc.s || seg_desc.type != 2)
1584 goto exception;
1585 break;
1586 default: /* DS, ES, FS, or GS */
4e62417b 1587 /*
dde7e6d1
AK		 1588 * segment is not a data or readable code segment or
1589 * ((segment is a data or nonconforming code segment)
1590 * and (both RPL and CPL > DPL))
4e62417b 1591 */
dde7e6d1
AK		 1592 if ((seg_desc.type & 0xa) == 0x8 ||
1593 (((seg_desc.type & 0xc) != 0xc) &&
1594 (rpl > dpl && cpl > dpl)))
1595 goto exception;
6aa8b732 1596 break;
dde7e6d1
AK		 1597 }
1598
1599 if (seg_desc.s) {
1600 /* mark segment as accessed */
1601 seg_desc.type |= 1;
7b105ca2 1602 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1603 if (ret != X86EMUL_CONTINUE)
1604 return ret;
1605 }
1606load:
7b105ca2 1607 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1608 return X86EMUL_CONTINUE;
1609exception:
1610 emulate_exception(ctxt, err_vec, err_code, true);
1611 return X86EMUL_PROPAGATE_FAULT;
1612}
1613
31be40b3
WY		 1614static void write_register_operand(struct operand *op)
1615{
1616 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1617 switch (op->bytes) {
1618 case 1:
1619 *(u8 *)op->addr.reg = (u8)op->val;
1620 break;
1621 case 2:
1622 *(u16 *)op->addr.reg = (u16)op->val;
1623 break;
1624 case 4:
1625 *op->addr.reg = (u32)op->val;
1626 break; /* 64b: zero-extend */
1627 case 8:
1628 *op->addr.reg = op->val;
1629 break;
1630 }
1631}
1632
adddcecf 1633static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1634{
1635 int rc;
dde7e6d1 1636
b6744dc3
AK		 1637 if (ctxt->d & NoWrite)
1638 return X86EMUL_CONTINUE;
1639
9dac77fa 1640 switch (ctxt->dst.type) {
dde7e6d1 1641 case OP_REG:
9dac77fa 1642 write_register_operand(&ctxt->dst);
6aa8b732 1643 break;
dde7e6d1 1644 case OP_MEM:
9dac77fa 1645 if (ctxt->lock_prefix)
3ca3ac4d 1646 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1647 ctxt->dst.addr.mem,
1648 &ctxt->dst.orig_val,
1649 &ctxt->dst.val,
1650 ctxt->dst.bytes);
341de7e3 1651 else
3ca3ac4d 1652 rc = segmented_write(ctxt,
9dac77fa
AK		 1653 ctxt->dst.addr.mem,
1654 &ctxt->dst.val,
1655 ctxt->dst.bytes);
dde7e6d1
AK		 1656 if (rc != X86EMUL_CONTINUE)
1657 return rc;
a682e354 1658 break;
b3356bf0
GN		 1659 case OP_MEM_STR:
1660 rc = segmented_write(ctxt,
1661 ctxt->dst.addr.mem,
1662 ctxt->dst.data,
1663 ctxt->dst.bytes * ctxt->dst.count);
1664 if (rc != X86EMUL_CONTINUE)
1665 return rc;
1666 break;
1253791d 1667 case OP_XMM:
9dac77fa 1668 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1669 break;
cbe2c9d3
AK		 1670 case OP_MM:
1671 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1672 break;
dde7e6d1
AK		 1673 case OP_NONE:
1674 /* no writeback */
414e6277 1675 break;
dde7e6d1 1676 default:
414e6277 1677 break;
6aa8b732 1678 }
dde7e6d1
AK		 1679 return X86EMUL_CONTINUE;
1680}
6aa8b732 1681
51ddff50 1682static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1683{
4179bb02 1684 struct segmented_address addr;
0dc8d10f 1685
5ad105e5 1686 rsp_increment(ctxt, -bytes);
dd856efa 1687 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1688 addr.seg = VCPU_SREG_SS;
1689
51ddff50
AK		 1690 return segmented_write(ctxt, addr, data, bytes);
1691}
1692
1693static int em_push(struct x86_emulate_ctxt *ctxt)
1694{
4179bb02 1695 /* Disable writeback. */
9dac77fa 1696 ctxt->dst.type = OP_NONE;
51ddff50 1697 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1698}
69f55cb1 1699
dde7e6d1 1700static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1701 void *dest, int len)
1702{
dde7e6d1 1703 int rc;
90de84f5 1704 struct segmented_address addr;
8b4caf66 1705
dd856efa 1706 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1707 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1708 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1709 if (rc != X86EMUL_CONTINUE)
1710 return rc;
1711
5ad105e5 1712 rsp_increment(ctxt, len);
dde7e6d1 1713 return rc;
8b4caf66
LV		 1714}
1715
c54fe504
TY		 1716static int em_pop(struct x86_emulate_ctxt *ctxt)
1717{
9dac77fa 1718 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1719}
1720
dde7e6d1 1721static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1722 void *dest, int len)
9de41573
GN		 1723{
1724 int rc;
dde7e6d1
AK		 1725 unsigned long val, change_mask;
1726 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1727 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1728
3b9be3bf 1729 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1730 if (rc != X86EMUL_CONTINUE)
1731 return rc;
9de41573 1732
dde7e6d1
AK		 1733 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1734 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1735
dde7e6d1
AK		 1736 switch(ctxt->mode) {
1737 case X86EMUL_MODE_PROT64:
1738 case X86EMUL_MODE_PROT32:
1739 case X86EMUL_MODE_PROT16:
1740 if (cpl == 0)
1741 change_mask |= EFLG_IOPL;
1742 if (cpl <= iopl)
1743 change_mask |= EFLG_IF;
1744 break;
1745 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1746 if (iopl < 3)
1747 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1748 change_mask |= EFLG_IF;
1749 break;
1750 default: /* real mode */
1751 change_mask |= (EFLG_IOPL | EFLG_IF);
1752 break;
9de41573 1753 }
dde7e6d1
AK		 1754
1755 *(unsigned long *)dest =
1756 (ctxt->eflags & ~change_mask) | (val & change_mask);
1757
1758 return rc;
9de41573
GN		 1759}
1760
62aaa2f0
TY		 1761static int em_popf(struct x86_emulate_ctxt *ctxt)
1762{
9dac77fa
AK		 1763 ctxt->dst.type = OP_REG;
1764 ctxt->dst.addr.reg = &ctxt->eflags;
1765 ctxt->dst.bytes = ctxt->op_bytes;
1766 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1767}
1768
612e89f0
AK		 1769static int em_enter(struct x86_emulate_ctxt *ctxt)
1770{
1771 int rc;
1772 unsigned frame_size = ctxt->src.val;
1773 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1774 ulong rbp;
612e89f0
AK		 1775
1776 if (nesting_level)
1777 return X86EMUL_UNHANDLEABLE;
1778
dd856efa
AK		 1779 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1780 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1781 if (rc != X86EMUL_CONTINUE)
1782 return rc;
dd856efa 1783 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1784 stack_mask(ctxt));
dd856efa
AK		 1785 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1786 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1787 stack_mask(ctxt));
1788 return X86EMUL_CONTINUE;
1789}
1790
f47cfa31
AK		 1791static int em_leave(struct x86_emulate_ctxt *ctxt)
1792{
dd856efa 1793 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1794 stack_mask(ctxt));
dd856efa 1795 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1796}
1797
1cd196ea 1798static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1799{
1cd196ea
AK		 1800 int seg = ctxt->src2.val;
1801
9dac77fa 1802 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1803
4487b3b4 1804 return em_push(ctxt);
7b262e90
GN		 1805}
1806
1cd196ea 1807static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1808{
1cd196ea 1809 int seg = ctxt->src2.val;
dde7e6d1
AK		 1810 unsigned long selector;
1811 int rc;
38ba30ba 1812
9dac77fa 1813 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1814 if (rc != X86EMUL_CONTINUE)
1815 return rc;
1816
7b105ca2 1817 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1818 return rc;
38ba30ba
GN		 1819}
1820
b96a7fad 1821static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1822{
dd856efa 1823 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1824 int rc = X86EMUL_CONTINUE;
1825 int reg = VCPU_REGS_RAX;
38ba30ba 1826
dde7e6d1
AK		 1827 while (reg <= VCPU_REGS_RDI) {
1828 (reg == VCPU_REGS_RSP) ?
dd856efa 1829 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1830
4487b3b4 1831 rc = em_push(ctxt);
dde7e6d1
AK		 1832 if (rc != X86EMUL_CONTINUE)
1833 return rc;
38ba30ba 1834
dde7e6d1 1835 ++reg;
38ba30ba 1836 }
38ba30ba 1837
dde7e6d1 1838 return rc;
38ba30ba
GN		 1839}
1840
62aaa2f0
TY		 1841static int em_pushf(struct x86_emulate_ctxt *ctxt)
1842{
9dac77fa 1843 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1844 return em_push(ctxt);
1845}
1846
b96a7fad 1847static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1848{
dde7e6d1
AK		 1849 int rc = X86EMUL_CONTINUE;
1850 int reg = VCPU_REGS_RDI;
38ba30ba 1851
dde7e6d1
AK		 1852 while (reg >= VCPU_REGS_RAX) {
1853 if (reg == VCPU_REGS_RSP) {
5ad105e5 1854 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1855 --reg;
1856 }
38ba30ba 1857
dd856efa 1858 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1859 if (rc != X86EMUL_CONTINUE)
1860 break;
1861 --reg;
38ba30ba 1862 }
dde7e6d1 1863 return rc;
38ba30ba
GN		 1864}
1865
dd856efa 1866static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1867{
0225fb50 1868 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1869 int rc;
6e154e56
MG		 1870 struct desc_ptr dt;
1871 gva_t cs_addr;
1872 gva_t eip_addr;
1873 u16 cs, eip;
6e154e56
MG		 1874
1875 /* TODO: Add limit checks */
9dac77fa 1876 ctxt->src.val = ctxt->eflags;
4487b3b4 1877 rc = em_push(ctxt);
5c56e1cf
AK		 1878 if (rc != X86EMUL_CONTINUE)
1879 return rc;
6e154e56
MG		 1880
1881 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1882
9dac77fa 1883 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1884 rc = em_push(ctxt);
5c56e1cf
AK		 1885 if (rc != X86EMUL_CONTINUE)
1886 return rc;
6e154e56 1887
9dac77fa 1888 ctxt->src.val = ctxt->_eip;
4487b3b4 1889 rc = em_push(ctxt);
5c56e1cf
AK		 1890 if (rc != X86EMUL_CONTINUE)
1891 return rc;
1892
4bff1e86 1893 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1894
1895 eip_addr = dt.address + (irq << 2);
1896 cs_addr = dt.address + (irq << 2) + 2;
1897
0f65dd70 1898 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
1901
0f65dd70 1902 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1903 if (rc != X86EMUL_CONTINUE)
1904 return rc;
1905
7b105ca2 1906 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1907 if (rc != X86EMUL_CONTINUE)
1908 return rc;
1909
9dac77fa 1910 ctxt->_eip = eip;
6e154e56
MG		 1911
1912 return rc;
1913}
1914
dd856efa
AK		 1915int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1916{
1917 int rc;
1918
1919 invalidate_registers(ctxt);
1920 rc = __emulate_int_real(ctxt, irq);
1921 if (rc == X86EMUL_CONTINUE)
1922 writeback_registers(ctxt);
1923 return rc;
1924}
1925
7b105ca2 1926static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1927{
1928 switch(ctxt->mode) {
1929 case X86EMUL_MODE_REAL:
dd856efa 1930 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1931 case X86EMUL_MODE_VM86:
1932 case X86EMUL_MODE_PROT16:
1933 case X86EMUL_MODE_PROT32:
1934 case X86EMUL_MODE_PROT64:
1935 default:
1936 /* Protected mode interrupts unimplemented yet */
1937 return X86EMUL_UNHANDLEABLE;
1938 }
1939}
1940
7b105ca2 1941static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1942{
dde7e6d1
AK		 1943 int rc = X86EMUL_CONTINUE;
1944 unsigned long temp_eip = 0;
1945 unsigned long temp_eflags = 0;
1946 unsigned long cs = 0;
1947 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1948 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1949 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1950 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1951
dde7e6d1 1952 /* TODO: Add stack limit check */
38ba30ba 1953
9dac77fa 1954 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1955
dde7e6d1
AK		 1956 if (rc != X86EMUL_CONTINUE)
1957 return rc;
38ba30ba 1958
35d3d4a1
AK		 1959 if (temp_eip & ~0xffff)
1960 return emulate_gp(ctxt, 0);
38ba30ba 1961
9dac77fa 1962 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1963
dde7e6d1
AK		 1964 if (rc != X86EMUL_CONTINUE)
1965 return rc;
38ba30ba 1966
9dac77fa 1967 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1968
dde7e6d1
AK		 1969 if (rc != X86EMUL_CONTINUE)
1970 return rc;
38ba30ba 1971
7b105ca2 1972 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1973
dde7e6d1
AK		 1974 if (rc != X86EMUL_CONTINUE)
1975 return rc;
38ba30ba 1976
9dac77fa 1977 ctxt->_eip = temp_eip;
38ba30ba 1978
38ba30ba 1979
9dac77fa 1980 if (ctxt->op_bytes == 4)
dde7e6d1 1981 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1982 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1983 ctxt->eflags &= ~0xffff;
1984 ctxt->eflags |= temp_eflags;
38ba30ba 1985 }
dde7e6d1
AK		 1986
1987 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1988 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1989
1990 return rc;
38ba30ba
GN		 1991}
1992
e01991e7 1993static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1994{
dde7e6d1
AK		 1995 switch(ctxt->mode) {
1996 case X86EMUL_MODE_REAL:
7b105ca2 1997 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1998 case X86EMUL_MODE_VM86:
1999 case X86EMUL_MODE_PROT16:
2000 case X86EMUL_MODE_PROT32:
2001 case X86EMUL_MODE_PROT64:
c37eda13 2002 default:
dde7e6d1
AK		 2003 /* iret from protected mode unimplemented yet */
2004 return X86EMUL_UNHANDLEABLE;
c37eda13 2005 }
c37eda13
WY		 2006}
2007
d2f62766
TY		 2008static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2009{
d2f62766
TY		 2010 int rc;
2011 unsigned short sel;
2012
9dac77fa 2013 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2014
7b105ca2 2015 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2016 if (rc != X86EMUL_CONTINUE)
2017 return rc;
2018
9dac77fa
AK		 2019 ctxt->_eip = 0;
2020 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2021 return X86EMUL_CONTINUE;
2022}
2023
51187683 2024static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2025{
9dac77fa 2026 switch (ctxt->modrm_reg) {
8cdbd2c9 2027 case 0: /* rol */
a31b9cea 2028 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 2029 break;
2030 case 1: /* ror */
a31b9cea 2031 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 2032 break;
2033 case 2: /* rcl */
a31b9cea 2034 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 2035 break;
2036 case 3: /* rcr */
a31b9cea 2037 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 2038 break;
2039 case 4: /* sal/shl */
2040 case 6: /* sal/shl */
a31b9cea 2041 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 2042 break;
2043 case 5: /* shr */
a31b9cea 2044 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 2045 break;
2046 case 7: /* sar */
a31b9cea 2047 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 2048 break;
2049 }
51187683 2050 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2051}
2052
3329ece1
AK		 2053static int em_not(struct x86_emulate_ctxt *ctxt)
2054{
2055 ctxt->dst.val = ~ctxt->dst.val;
2056 return X86EMUL_CONTINUE;
2057}
2058
2059static int em_neg(struct x86_emulate_ctxt *ctxt)
2060{
2061 emulate_1op(ctxt, "neg");
2062 return X86EMUL_CONTINUE;
2063}
2064
2065static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2066{
2067 u8 ex = 0;
2068
2069 emulate_1op_rax_rdx(ctxt, "mul", ex);
2070 return X86EMUL_CONTINUE;
2071}
2072
2073static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2074{
2075 u8 ex = 0;
2076
2077 emulate_1op_rax_rdx(ctxt, "imul", ex);
2078 return X86EMUL_CONTINUE;
2079}
2080
2081static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2082{
34d1f490 2083 u8 de = 0;
8cdbd2c9 2084
3329ece1
AK		 2085 emulate_1op_rax_rdx(ctxt, "div", de);
2086 if (de)
2087 return emulate_de(ctxt);
2088 return X86EMUL_CONTINUE;
2089}
2090
2091static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2092{
2093 u8 de = 0;
2094
2095 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2096 if (de)
2097 return emulate_de(ctxt);
8c5eee30 2098 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2099}
2100
51187683 2101static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2102{
4179bb02 2103 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2104
9dac77fa 2105 switch (ctxt->modrm_reg) {
8cdbd2c9 2106 case 0: /* inc */
d1eef45d 2107 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2108 break;
2109 case 1: /* dec */
d1eef45d 2110 emulate_1op(ctxt, "dec");
8cdbd2c9 2111 break;
d19292e4
MG		 2112 case 2: /* call near abs */ {
2113 long int old_eip;
9dac77fa
AK		 2114 old_eip = ctxt->_eip;
2115 ctxt->_eip = ctxt->src.val;
2116 ctxt->src.val = old_eip;
4487b3b4 2117 rc = em_push(ctxt);
d19292e4
MG		 2118 break;
2119 }
8cdbd2c9 2120 case 4: /* jmp abs */
9dac77fa 2121 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2122 break;
d2f62766
TY		 2123 case 5: /* jmp far */
2124 rc = em_jmp_far(ctxt);
2125 break;
8cdbd2c9 2126 case 6: /* push */
4487b3b4 2127 rc = em_push(ctxt);
8cdbd2c9 2128 break;
8cdbd2c9 2129 }
4179bb02 2130 return rc;
8cdbd2c9
LV		 2131}
2132
e0dac408 2133static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2134{
9dac77fa 2135 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2136
dd856efa
AK		 2137 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2138 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2139 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2140 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2141 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2142 } else {
dd856efa
AK		 2143 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2144 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2145
05f086f8 2146 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2147 }
1b30eaa8 2148 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2149}
2150
ebda02c2
TY		 2151static int em_ret(struct x86_emulate_ctxt *ctxt)
2152{
9dac77fa
AK		 2153 ctxt->dst.type = OP_REG;
2154 ctxt->dst.addr.reg = &ctxt->_eip;
2155 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2156 return em_pop(ctxt);
2157}
2158
e01991e7 2159static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2160{
a77ab5ea
AK		 2161 int rc;
2162 unsigned long cs;
2163
9dac77fa 2164 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2165 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2166 return rc;
9dac77fa
AK		 2167 if (ctxt->op_bytes == 4)
2168 ctxt->_eip = (u32)ctxt->_eip;
2169 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2170 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2171 return rc;
7b105ca2 2172 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2173 return rc;
2174}
2175
e940b5c2
TY		 2176static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2177{
2178 /* Save real source value, then compare EAX against destination. */
2179 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2180 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2181 emulate_2op_SrcV(ctxt, "cmp");
2182
2183 if (ctxt->eflags & EFLG_ZF) {
2184 /* Success: write back to memory. */
2185 ctxt->dst.val = ctxt->src.orig_val;
2186 } else {
2187 /* Failure: write the value we saw to EAX. */
2188 ctxt->dst.type = OP_REG;
dd856efa 2189 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2190 }
2191 return X86EMUL_CONTINUE;
2192}
2193
d4b4325f 2194static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2195{
d4b4325f 2196 int seg = ctxt->src2.val;
09b5f4d3
WY		 2197 unsigned short sel;
2198 int rc;
2199
9dac77fa 2200 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2201
7b105ca2 2202 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2203 if (rc != X86EMUL_CONTINUE)
2204 return rc;
2205
9dac77fa 2206 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2207 return rc;
2208}
2209
7b105ca2 2210static void
e66bb2cc 2211setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2212 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2213{
e66bb2cc 2214 cs->l = 0; /* will be adjusted later */
79168fd1 2215 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2216 cs->g = 1; /* 4kb granularity */
79168fd1 2217 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2218 cs->type = 0x0b; /* Read, Execute, Accessed */
2219 cs->s = 1;
2220 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2221 cs->p = 1;
2222 cs->d = 1;
99245b50 2223 cs->avl = 0;
e66bb2cc 2224
79168fd1
GN		 2225 set_desc_base(ss, 0); /* flat segment */
2226 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2227 ss->g = 1; /* 4kb granularity */
2228 ss->s = 1;
2229 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2230 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2231 ss->dpl = 0;
79168fd1 2232 ss->p = 1;
99245b50
GN		 2233 ss->l = 0;
2234 ss->avl = 0;
e66bb2cc
AP		 2235}
2236
1a18a69b
AK		 2237static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2238{
2239 u32 eax, ebx, ecx, edx;
2240
2241 eax = ecx = 0;
0017f93a
AK		 2242 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2243 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2244 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2245 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2246}
2247
c2226fc9
SB		 2248static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2249{
0225fb50 2250 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2251 u32 eax, ebx, ecx, edx;
2252
2253 /*
2254 * syscall should always be enabled in longmode - so only become
2255 * vendor specific (cpuid) if other modes are active...
2256 */
2257 if (ctxt->mode == X86EMUL_MODE_PROT64)
2258 return true;
2259
2260 eax = 0x00000000;
2261 ecx = 0x00000000;
0017f93a
AK		 2262 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2263 /*
2264 * Intel ("GenuineIntel")
2265 * remark: Intel CPUs only support "syscall" in 64bit
2266 * longmode. Also an 64bit guest with a
2267 * 32bit compat-app running will #UD !! While this
2268 * behaviour can be fixed (by emulating) into AMD
2269 * response - CPUs of AMD can't behave like Intel.
2270 */
2271 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2272 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2273 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2274 return false;
2275
2276 /* AMD ("AuthenticAMD") */
2277 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2278 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2279 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2280 return true;
2281
2282 /* AMD ("AMDisbetter!") */
2283 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2284 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2285 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2286 return true;
c2226fc9
SB		 2287
2288 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2289 return false;
2290}
2291
e01991e7 2292static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2293{
0225fb50 2294 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2295 struct desc_struct cs, ss;
e66bb2cc 2296 u64 msr_data;
79168fd1 2297 u16 cs_sel, ss_sel;
c2ad2bb3 2298 u64 efer = 0;
e66bb2cc
AP		 2299
2300 /* syscall is not available in real mode */
2e901c4c 2301 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2302 ctxt->mode == X86EMUL_MODE_VM86)
2303 return emulate_ud(ctxt);
e66bb2cc 2304
c2226fc9
SB		 2305 if (!(em_syscall_is_enabled(ctxt)))
2306 return emulate_ud(ctxt);
2307
c2ad2bb3 2308 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2309 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2310
c2226fc9
SB		 2311 if (!(efer & EFER_SCE))
2312 return emulate_ud(ctxt);
2313
717746e3 2314 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2315 msr_data >>= 32;
79168fd1
GN		 2316 cs_sel = (u16)(msr_data & 0xfffc);
2317 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2318
c2ad2bb3 2319 if (efer & EFER_LMA) {
79168fd1 2320 cs.d = 0;
e66bb2cc
AP		 2321 cs.l = 1;
2322 }
1aa36616
AK		 2323 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2324 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2325
dd856efa 2326 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2327 if (efer & EFER_LMA) {
e66bb2cc 2328#ifdef CONFIG_X86_64
dd856efa 2329 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2330
717746e3 2331 ops->get_msr(ctxt,
3fb1b5db
GN		 2332 ctxt->mode == X86EMUL_MODE_PROT64 ?
2333 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2334 ctxt->_eip = msr_data;
e66bb2cc 2335
717746e3 2336 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2337 ctxt->eflags &= ~(msr_data | EFLG_RF);
2338#endif
2339 } else {
2340 /* legacy mode */
717746e3 2341 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2342 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2343
2344 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2345 }
2346
e54cfa97 2347 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2348}
2349
e01991e7 2350static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2351{
0225fb50 2352 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2353 struct desc_struct cs, ss;
8c604352 2354 u64 msr_data;
79168fd1 2355 u16 cs_sel, ss_sel;
c2ad2bb3 2356 u64 efer = 0;
8c604352 2357
7b105ca2 2358 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2359 /* inject #GP if in real mode */
35d3d4a1
AK		 2360 if (ctxt->mode == X86EMUL_MODE_REAL)
2361 return emulate_gp(ctxt, 0);
8c604352 2362
1a18a69b
AK		 2363 /*
2364 * Not recognized on AMD in compat mode (but is recognized in legacy
2365 * mode).
2366 */
2367 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2368 && !vendor_intel(ctxt))
2369 return emulate_ud(ctxt);
2370
8c604352
AP		 2371 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2372 * Therefore, we inject an #UD.
2373 */
35d3d4a1
AK		 2374 if (ctxt->mode == X86EMUL_MODE_PROT64)
2375 return emulate_ud(ctxt);
8c604352 2376
7b105ca2 2377 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2378
717746e3 2379 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2380 switch (ctxt->mode) {
2381 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2382 if ((msr_data & 0xfffc) == 0x0)
2383 return emulate_gp(ctxt, 0);
8c604352
AP		 2384 break;
2385 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2386 if (msr_data == 0x0)
2387 return emulate_gp(ctxt, 0);
8c604352 2388 break;
9d1b39a9
GN		 2389 default:
2390 break;
8c604352
AP		 2391 }
2392
2393 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2394 cs_sel = (u16)msr_data;
2395 cs_sel &= ~SELECTOR_RPL_MASK;
2396 ss_sel = cs_sel + 8;
2397 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2398 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2399 cs.d = 0;
8c604352
AP		 2400 cs.l = 1;
2401 }
2402
1aa36616
AK		 2403 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2404 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2405
717746e3 2406 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2407 ctxt->_eip = msr_data;
8c604352 2408
717746e3 2409 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2410 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2411
e54cfa97 2412 return X86EMUL_CONTINUE;
8c604352
AP		 2413}
2414
e01991e7 2415static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2416{
0225fb50 2417 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2418 struct desc_struct cs, ss;
4668f050
AP		 2419 u64 msr_data;
2420 int usermode;
1249b96e 2421 u16 cs_sel = 0, ss_sel = 0;
4668f050 2422
a0044755
GN		 2423 /* inject #GP if in real mode or Virtual 8086 mode */
2424 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2425 ctxt->mode == X86EMUL_MODE_VM86)
2426 return emulate_gp(ctxt, 0);
4668f050 2427
7b105ca2 2428 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2429
9dac77fa 2430 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2431 usermode = X86EMUL_MODE_PROT64;
2432 else
2433 usermode = X86EMUL_MODE_PROT32;
2434
2435 cs.dpl = 3;
2436 ss.dpl = 3;
717746e3 2437 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2438 switch (usermode) {
2439 case X86EMUL_MODE_PROT32:
79168fd1 2440 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2441 if ((msr_data & 0xfffc) == 0x0)
2442 return emulate_gp(ctxt, 0);
79168fd1 2443 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2444 break;
2445 case X86EMUL_MODE_PROT64:
79168fd1 2446 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2447 if (msr_data == 0x0)
2448 return emulate_gp(ctxt, 0);
79168fd1
GN		 2449 ss_sel = cs_sel + 8;
2450 cs.d = 0;
4668f050
AP		 2451 cs.l = 1;
2452 break;
2453 }
79168fd1
GN		 2454 cs_sel |= SELECTOR_RPL_MASK;
2455 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2456
1aa36616
AK		 2457 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2458 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2459
dd856efa
AK		 2460 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2461 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2462
e54cfa97 2463 return X86EMUL_CONTINUE;
4668f050
AP		 2464}
2465
7b105ca2 2466static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2467{
2468 int iopl;
2469 if (ctxt->mode == X86EMUL_MODE_REAL)
2470 return false;
2471 if (ctxt->mode == X86EMUL_MODE_VM86)
2472 return true;
2473 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2474 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2475}
2476
2477static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2478 u16 port, u16 len)
2479{
0225fb50 2480 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2481 struct desc_struct tr_seg;
5601d05b 2482 u32 base3;
f850e2e6 2483 int r;
1aa36616 2484 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2485 unsigned mask = (1 << len) - 1;
5601d05b 2486 unsigned long base;
f850e2e6 2487
1aa36616 2488 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2489 if (!tr_seg.p)
f850e2e6 2490 return false;
79168fd1 2491 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2492 return false;
5601d05b
GN		 2493 base = get_desc_base(&tr_seg);
2494#ifdef CONFIG_X86_64
2495 base |= ((u64)base3) << 32;
2496#endif
0f65dd70 2497 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2498 if (r != X86EMUL_CONTINUE)
2499 return false;
79168fd1 2500 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2501 return false;
0f65dd70 2502 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2503 if (r != X86EMUL_CONTINUE)
2504 return false;
2505 if ((perm >> bit_idx) & mask)
2506 return false;
2507 return true;
2508}
2509
2510static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2511 u16 port, u16 len)
2512{
4fc40f07
GN		 2513 if (ctxt->perm_ok)
2514 return true;
2515
7b105ca2
TY		 2516 if (emulator_bad_iopl(ctxt))
2517 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2518 return false;
4fc40f07
GN		 2519
2520 ctxt->perm_ok = true;
2521
f850e2e6
GN		 2522 return true;
2523}
2524
38ba30ba 2525static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2526 struct tss_segment_16 *tss)
2527{
9dac77fa 2528 tss->ip = ctxt->_eip;
38ba30ba 2529 tss->flag = ctxt->eflags;
dd856efa
AK		 2530 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2531 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2532 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2533 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2534 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2535 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2536 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2537 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2538
1aa36616
AK		 2539 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2540 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2541 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2542 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2543 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2544}
2545
2546static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2547 struct tss_segment_16 *tss)
2548{
38ba30ba
GN		 2549 int ret;
2550
9dac77fa 2551 ctxt->_eip = tss->ip;
38ba30ba 2552 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2553 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2554 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2555 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2556 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2557 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2558 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2559 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2560 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2561
2562 /*
2563 * SDM says that segment selectors are loaded before segment
2564 * descriptors
2565 */
1aa36616
AK		 2566 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2567 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2568 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2569 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2570 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2571
2572 /*
fc058680 2573 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2574 * it is handled in a context of new task
2575 */
7b105ca2 2576 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2577 if (ret != X86EMUL_CONTINUE)
2578 return ret;
7b105ca2 2579 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
7b105ca2 2582 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2583 if (ret != X86EMUL_CONTINUE)
2584 return ret;
7b105ca2 2585 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2586 if (ret != X86EMUL_CONTINUE)
2587 return ret;
7b105ca2 2588 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2589 if (ret != X86EMUL_CONTINUE)
2590 return ret;
2591
2592 return X86EMUL_CONTINUE;
2593}
2594
2595static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2596 u16 tss_selector, u16 old_tss_sel,
2597 ulong old_tss_base, struct desc_struct *new_desc)
2598{
0225fb50 2599 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2600 struct tss_segment_16 tss_seg;
2601 int ret;
bcc55cba 2602 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2603
0f65dd70 2604 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2605 &ctxt->exception);
db297e3d 2606 if (ret != X86EMUL_CONTINUE)
38ba30ba 2607 /* FIXME: need to provide precise fault address */
38ba30ba 2608 return ret;
38ba30ba 2609
7b105ca2 2610 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2611
0f65dd70 2612 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2613 &ctxt->exception);
db297e3d 2614 if (ret != X86EMUL_CONTINUE)
38ba30ba 2615 /* FIXME: need to provide precise fault address */
38ba30ba 2616 return ret;
38ba30ba 2617
0f65dd70 2618 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2619 &ctxt->exception);
db297e3d 2620 if (ret != X86EMUL_CONTINUE)
38ba30ba 2621 /* FIXME: need to provide precise fault address */
38ba30ba 2622 return ret;
38ba30ba
GN		 2623
2624 if (old_tss_sel != 0xffff) {
2625 tss_seg.prev_task_link = old_tss_sel;
2626
0f65dd70 2627 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2628 &tss_seg.prev_task_link,
2629 sizeof tss_seg.prev_task_link,
0f65dd70 2630 &ctxt->exception);
db297e3d 2631 if (ret != X86EMUL_CONTINUE)
38ba30ba 2632 /* FIXME: need to provide precise fault address */
38ba30ba 2633 return ret;
38ba30ba
GN		 2634 }
2635
7b105ca2 2636 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2637}
2638
2639static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2640 struct tss_segment_32 *tss)
2641{
7b105ca2 2642 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2643 tss->eip = ctxt->_eip;
38ba30ba 2644 tss->eflags = ctxt->eflags;
dd856efa
AK		 2645 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2646 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2647 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2648 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2649 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2650 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2651 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2652 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2653
1aa36616
AK		 2654 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2655 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2656 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2657 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2658 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2659 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2660 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2661}
2662
2663static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2664 struct tss_segment_32 *tss)
2665{
38ba30ba
GN		 2666 int ret;
2667
7b105ca2 2668 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2669 return emulate_gp(ctxt, 0);
9dac77fa 2670 ctxt->_eip = tss->eip;
38ba30ba 2671 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2672
2673 /* General purpose registers */
dd856efa
AK		 2674 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2675 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2676 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2677 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2678 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2679 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2680 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2681 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2682
2683 /*
2684 * SDM says that segment selectors are loaded before segment
2685 * descriptors
2686 */
1aa36616
AK		 2687 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2688 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2689 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2690 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2691 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2692 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2693 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2694
4cee4798
KW		 2695 /*
2696 * If we're switching between Protected Mode and VM86, we need to make
2697 * sure to update the mode before loading the segment descriptors so
2698 * that the selectors are interpreted correctly.
2699 *
2700 * Need to get rflags to the vcpu struct immediately because it
2701 * influences the CPL which is checked at least when loading the segment
2702 * descriptors and when pushing an error code to the new kernel stack.
2703 *
2704 * TODO Introduce a separate ctxt->ops->set_cpl callback
2705 */
2706 if (ctxt->eflags & X86_EFLAGS_VM)
2707 ctxt->mode = X86EMUL_MODE_VM86;
2708 else
2709 ctxt->mode = X86EMUL_MODE_PROT32;
2710
2711 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2712
38ba30ba
GN		 2713 /*
2714 * Now load segment descriptors. If fault happenes at this stage
2715 * it is handled in a context of new task
2716 */
7b105ca2 2717 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2718 if (ret != X86EMUL_CONTINUE)
2719 return ret;
7b105ca2 2720 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2721 if (ret != X86EMUL_CONTINUE)
2722 return ret;
7b105ca2 2723 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2724 if (ret != X86EMUL_CONTINUE)
2725 return ret;
7b105ca2 2726 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2727 if (ret != X86EMUL_CONTINUE)
2728 return ret;
7b105ca2 2729 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2730 if (ret != X86EMUL_CONTINUE)
2731 return ret;
7b105ca2 2732 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2733 if (ret != X86EMUL_CONTINUE)
2734 return ret;
7b105ca2 2735 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2736 if (ret != X86EMUL_CONTINUE)
2737 return ret;
2738
2739 return X86EMUL_CONTINUE;
2740}
2741
2742static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2743 u16 tss_selector, u16 old_tss_sel,
2744 ulong old_tss_base, struct desc_struct *new_desc)
2745{
0225fb50 2746 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2747 struct tss_segment_32 tss_seg;
2748 int ret;
bcc55cba 2749 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2750
0f65dd70 2751 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2752 &ctxt->exception);
db297e3d 2753 if (ret != X86EMUL_CONTINUE)
38ba30ba 2754 /* FIXME: need to provide precise fault address */
38ba30ba 2755 return ret;
38ba30ba 2756
7b105ca2 2757 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2758
0f65dd70 2759 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2760 &ctxt->exception);
db297e3d 2761 if (ret != X86EMUL_CONTINUE)
38ba30ba 2762 /* FIXME: need to provide precise fault address */
38ba30ba 2763 return ret;
38ba30ba 2764
0f65dd70 2765 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2766 &ctxt->exception);
db297e3d 2767 if (ret != X86EMUL_CONTINUE)
38ba30ba 2768 /* FIXME: need to provide precise fault address */
38ba30ba 2769 return ret;
38ba30ba
GN		 2770
2771 if (old_tss_sel != 0xffff) {
2772 tss_seg.prev_task_link = old_tss_sel;
2773
0f65dd70 2774 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2775 &tss_seg.prev_task_link,
2776 sizeof tss_seg.prev_task_link,
0f65dd70 2777 &ctxt->exception);
db297e3d 2778 if (ret != X86EMUL_CONTINUE)
38ba30ba 2779 /* FIXME: need to provide precise fault address */
38ba30ba 2780 return ret;
38ba30ba
GN		 2781 }
2782
7b105ca2 2783 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2784}
2785
2786static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2787 u16 tss_selector, int idt_index, int reason,
e269fb21 2788 bool has_error_code, u32 error_code)
38ba30ba 2789{
0225fb50 2790 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2791 struct desc_struct curr_tss_desc, next_tss_desc;
2792 int ret;
1aa36616 2793 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2794 ulong old_tss_base =
4bff1e86 2795 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2796 u32 desc_limit;
e919464b 2797 ulong desc_addr;
38ba30ba
GN		 2798
2799 /* FIXME: old_tss_base == ~0 ? */
2800
e919464b 2801 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2802 if (ret != X86EMUL_CONTINUE)
2803 return ret;
e919464b 2804 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2805 if (ret != X86EMUL_CONTINUE)
2806 return ret;
2807
2808 /* FIXME: check that next_tss_desc is tss */
2809
7f3d35fd
KW		 2810 /*
2811 * Check privileges. The three cases are task switch caused by...
2812 *
2813 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2814 * 2. Exception/IRQ/iret: No check is performed
fc058680 2815 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2816 */
2817 if (reason == TASK_SWITCH_GATE) {
2818 if (idt_index != -1) {
2819 /* Software interrupts */
2820 struct desc_struct task_gate_desc;
2821 int dpl;
2822
2823 ret = read_interrupt_descriptor(ctxt, idt_index,
2824 &task_gate_desc);
2825 if (ret != X86EMUL_CONTINUE)
2826 return ret;
2827
2828 dpl = task_gate_desc.dpl;
2829 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2830 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2831 }
2832 } else if (reason != TASK_SWITCH_IRET) {
2833 int dpl = next_tss_desc.dpl;
2834 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2835 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2836 }
2837
7f3d35fd 2838
ceffb459
GN		 2839 desc_limit = desc_limit_scaled(&next_tss_desc);
2840 if (!next_tss_desc.p ||
2841 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2842 desc_limit < 0x2b)) {
54b8486f 2843 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2844 return X86EMUL_PROPAGATE_FAULT;
2845 }
2846
2847 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2848 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2849 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2850 }
2851
2852 if (reason == TASK_SWITCH_IRET)
2853 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2854
2855 /* set back link to prev task only if NT bit is set in eflags
fc058680 2856 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2857 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2858 old_tss_sel = 0xffff;
2859
2860 if (next_tss_desc.type & 8)
7b105ca2 2861 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2862 old_tss_base, &next_tss_desc);
2863 else
7b105ca2 2864 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2865 old_tss_base, &next_tss_desc);
0760d448
JK		 2866 if (ret != X86EMUL_CONTINUE)
2867 return ret;
38ba30ba
GN		 2868
2869 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2870 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2871
2872 if (reason != TASK_SWITCH_IRET) {
2873 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2874 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2875 }
2876
717746e3 2877 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2878 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2879
e269fb21 2880 if (has_error_code) {
9dac77fa
AK		 2881 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2882 ctxt->lock_prefix = 0;
2883 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2884 ret = em_push(ctxt);
e269fb21
JK		 2885 }
2886
38ba30ba
GN		 2887 return ret;
2888}
2889
2890int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2891 u16 tss_selector, int idt_index, int reason,
e269fb21 2892 bool has_error_code, u32 error_code)
38ba30ba 2893{
38ba30ba
GN		 2894 int rc;
2895
dd856efa 2896 invalidate_registers(ctxt);
9dac77fa
AK		 2897 ctxt->_eip = ctxt->eip;
2898 ctxt->dst.type = OP_NONE;
38ba30ba 2899
7f3d35fd 2900 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2901 has_error_code, error_code);
38ba30ba 2902
dd856efa 2903 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2904 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2905 writeback_registers(ctxt);
2906 }
38ba30ba 2907
a0c0ab2f 2908 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2909}
2910
f3bd64c6
GN		 2911static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2912 struct operand *op)
a682e354 2913{
b3356bf0 2914 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2915
dd856efa
AK		 2916 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2917 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2918}
2919
7af04fc0
AK		 2920static int em_das(struct x86_emulate_ctxt *ctxt)
2921{
7af04fc0
AK		 2922 u8 al, old_al;
2923 bool af, cf, old_cf;
2924
2925 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2926 al = ctxt->dst.val;
7af04fc0
AK		 2927
2928 old_al = al;
2929 old_cf = cf;
2930 cf = false;
2931 af = ctxt->eflags & X86_EFLAGS_AF;
2932 if ((al & 0x0f) > 9 || af) {
2933 al -= 6;
2934 cf = old_cf | (al >= 250);
2935 af = true;
2936 } else {
2937 af = false;
2938 }
2939 if (old_al > 0x99 || old_cf) {
2940 al -= 0x60;
2941 cf = true;
2942 }
2943
9dac77fa 2944 ctxt->dst.val = al;
7af04fc0 2945 /* Set PF, ZF, SF */
9dac77fa
AK		 2946 ctxt->src.type = OP_IMM;
2947 ctxt->src.val = 0;
2948 ctxt->src.bytes = 1;
a31b9cea 2949 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2950 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2951 if (cf)
2952 ctxt->eflags |= X86_EFLAGS_CF;
2953 if (af)
2954 ctxt->eflags |= X86_EFLAGS_AF;
2955 return X86EMUL_CONTINUE;
2956}
2957
7f662273
GN		 2958static int em_aad(struct x86_emulate_ctxt *ctxt)
2959{
2960 u8 al = ctxt->dst.val & 0xff;
2961 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2962
2963 al = (al + (ah * ctxt->src.val)) & 0xff;
2964
2965 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2966
2967 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2968
2969 if (!al)
2970 ctxt->eflags |= X86_EFLAGS_ZF;
2971 if (!(al & 1))
2972 ctxt->eflags |= X86_EFLAGS_PF;
2973 if (al & 0x80)
2974 ctxt->eflags |= X86_EFLAGS_SF;
2975
2976 return X86EMUL_CONTINUE;
2977}
2978
d4ddafcd
TY		 2979static int em_call(struct x86_emulate_ctxt *ctxt)
2980{
2981 long rel = ctxt->src.val;
2982
2983 ctxt->src.val = (unsigned long)ctxt->_eip;
2984 jmp_rel(ctxt, rel);
2985 return em_push(ctxt);
2986}
2987
0ef753b8
AK		 2988static int em_call_far(struct x86_emulate_ctxt *ctxt)
2989{
0ef753b8
AK		 2990 u16 sel, old_cs;
2991 ulong old_eip;
2992 int rc;
2993
1aa36616 2994 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2995 old_eip = ctxt->_eip;
0ef753b8 2996
9dac77fa 2997 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2998 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2999 return X86EMUL_CONTINUE;
3000
9dac77fa
AK		 3001 ctxt->_eip = 0;
3002 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3003
9dac77fa 3004 ctxt->src.val = old_cs;
4487b3b4 3005 rc = em_push(ctxt);
0ef753b8
AK		 3006 if (rc != X86EMUL_CONTINUE)
3007 return rc;
3008
9dac77fa 3009 ctxt->src.val = old_eip;
4487b3b4 3010 return em_push(ctxt);
0ef753b8
AK		 3011}
3012
40ece7c7
AK		 3013static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3014{
40ece7c7
AK		 3015 int rc;
3016
9dac77fa
AK		 3017 ctxt->dst.type = OP_REG;
3018 ctxt->dst.addr.reg = &ctxt->_eip;
3019 ctxt->dst.bytes = ctxt->op_bytes;
3020 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3021 if (rc != X86EMUL_CONTINUE)
3022 return rc;
5ad105e5 3023 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3024 return X86EMUL_CONTINUE;
3025}
3026
d67fc27a
TY		 3027static int em_add(struct x86_emulate_ctxt *ctxt)
3028{
a31b9cea 3029 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 3030 return X86EMUL_CONTINUE;
3031}
3032
3033static int em_or(struct x86_emulate_ctxt *ctxt)
3034{
a31b9cea 3035 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 3036 return X86EMUL_CONTINUE;
3037}
3038
3039static int em_adc(struct x86_emulate_ctxt *ctxt)
3040{
a31b9cea 3041 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 3042 return X86EMUL_CONTINUE;
3043}
3044
3045static int em_sbb(struct x86_emulate_ctxt *ctxt)
3046{
a31b9cea 3047 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 3048 return X86EMUL_CONTINUE;
3049}
3050
3051static int em_and(struct x86_emulate_ctxt *ctxt)
3052{
a31b9cea 3053 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 3054 return X86EMUL_CONTINUE;
3055}
3056
3057static int em_sub(struct x86_emulate_ctxt *ctxt)
3058{
a31b9cea 3059 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 3060 return X86EMUL_CONTINUE;
3061}
3062
3063static int em_xor(struct x86_emulate_ctxt *ctxt)
3064{
a31b9cea 3065 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 3066 return X86EMUL_CONTINUE;
3067}
3068
3069static int em_cmp(struct x86_emulate_ctxt *ctxt)
3070{
a31b9cea 3071 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a
TY		 3072 return X86EMUL_CONTINUE;
3073}
3074
9f21ca59
TY		 3075static int em_test(struct x86_emulate_ctxt *ctxt)
3076{
a31b9cea 3077 emulate_2op_SrcV(ctxt, "test");
9f21ca59
TY		 3078 return X86EMUL_CONTINUE;
3079}
3080
e4f973ae
TY		 3081static int em_xchg(struct x86_emulate_ctxt *ctxt)
3082{
e4f973ae 3083 /* Write back the register source. */
9dac77fa
AK		 3084 ctxt->src.val = ctxt->dst.val;
3085 write_register_operand(&ctxt->src);
e4f973ae
TY		 3086
3087 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3088 ctxt->dst.val = ctxt->src.orig_val;
3089 ctxt->lock_prefix = 1;
e4f973ae
TY		 3090 return X86EMUL_CONTINUE;
3091}
3092
5c82aa29 3093static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 3094{
a31b9cea 3095 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 3096 return X86EMUL_CONTINUE;
3097}
3098
5c82aa29
AK		 3099static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3100{
9dac77fa 3101 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3102 return em_imul(ctxt);
3103}
3104
61429142
AK		 3105static int em_cwd(struct x86_emulate_ctxt *ctxt)
3106{
9dac77fa
AK		 3107 ctxt->dst.type = OP_REG;
3108 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3109 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3110 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3111
3112 return X86EMUL_CONTINUE;
3113}
3114
48bb5d3c
AK		 3115static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3116{
48bb5d3c
AK		 3117 u64 tsc = 0;
3118
717746e3 3119 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3120 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3121 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3122 return X86EMUL_CONTINUE;
3123}
3124
222d21aa
AK		 3125static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3126{
3127 u64 pmc;
3128
dd856efa 3129 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3130 return emulate_gp(ctxt, 0);
dd856efa
AK		 3131 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3132 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3133 return X86EMUL_CONTINUE;
3134}
3135
b9eac5f4
AK		 3136static int em_mov(struct x86_emulate_ctxt *ctxt)
3137{
49597d81 3138 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3139 return X86EMUL_CONTINUE;
3140}
3141
bc00f8d2
TY		 3142static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3143{
3144 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3145 return emulate_gp(ctxt, 0);
3146
3147 /* Disable writeback. */
3148 ctxt->dst.type = OP_NONE;
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3153{
3154 unsigned long val;
3155
3156 if (ctxt->mode == X86EMUL_MODE_PROT64)
3157 val = ctxt->src.val & ~0ULL;
3158 else
3159 val = ctxt->src.val & ~0U;
3160
3161 /* #UD condition is already handled. */
3162 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3163 return emulate_gp(ctxt, 0);
3164
3165 /* Disable writeback. */
3166 ctxt->dst.type = OP_NONE;
3167 return X86EMUL_CONTINUE;
3168}
3169
e1e210b0
TY		 3170static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3171{
3172 u64 msr_data;
3173
dd856efa
AK		 3174 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3175 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3176 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3177 return emulate_gp(ctxt, 0);
3178
3179 return X86EMUL_CONTINUE;
3180}
3181
3182static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3183{
3184 u64 msr_data;
3185
dd856efa 3186 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3187 return emulate_gp(ctxt, 0);
3188
dd856efa
AK		 3189 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3190 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3191 return X86EMUL_CONTINUE;
3192}
3193
1bd5f469
TY		 3194static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3195{
9dac77fa 3196 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3197 return emulate_ud(ctxt);
3198
9dac77fa 3199 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3200 return X86EMUL_CONTINUE;
3201}
3202
3203static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3204{
9dac77fa 3205 u16 sel = ctxt->src.val;
1bd5f469 3206
9dac77fa 3207 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3208 return emulate_ud(ctxt);
3209
9dac77fa 3210 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3211 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3212
3213 /* Disable writeback. */
9dac77fa
AK		 3214 ctxt->dst.type = OP_NONE;
3215 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3216}
3217
a14e579f
AK		 3218static int em_lldt(struct x86_emulate_ctxt *ctxt)
3219{
3220 u16 sel = ctxt->src.val;
3221
3222 /* Disable writeback. */
3223 ctxt->dst.type = OP_NONE;
3224 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3225}
3226
80890006
AK		 3227static int em_ltr(struct x86_emulate_ctxt *ctxt)
3228{
3229 u16 sel = ctxt->src.val;
3230
3231 /* Disable writeback. */
3232 ctxt->dst.type = OP_NONE;
3233 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3234}
3235
38503911
AK		 3236static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3237{
9fa088f4
AK		 3238 int rc;
3239 ulong linear;
3240
9dac77fa 3241 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3242 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3243 ctxt->ops->invlpg(ctxt, linear);
38503911 3244 /* Disable writeback. */
9dac77fa 3245 ctxt->dst.type = OP_NONE;
38503911
AK		 3246 return X86EMUL_CONTINUE;
3247}
3248
2d04a05b
AK		 3249static int em_clts(struct x86_emulate_ctxt *ctxt)
3250{
3251 ulong cr0;
3252
3253 cr0 = ctxt->ops->get_cr(ctxt, 0);
3254 cr0 &= ~X86_CR0_TS;
3255 ctxt->ops->set_cr(ctxt, 0, cr0);
3256 return X86EMUL_CONTINUE;
3257}
3258
26d05cc7
AK		 3259static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3260{
26d05cc7
AK		 3261 int rc;
3262
9dac77fa 3263 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3264 return X86EMUL_UNHANDLEABLE;
3265
3266 rc = ctxt->ops->fix_hypercall(ctxt);
3267 if (rc != X86EMUL_CONTINUE)
3268 return rc;
3269
3270 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3271 ctxt->_eip = ctxt->eip;
26d05cc7 3272 /* Disable writeback. */
9dac77fa 3273 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3274 return X86EMUL_CONTINUE;
3275}
3276
96051572
AK		 3277static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3278 void (*get)(struct x86_emulate_ctxt *ctxt,
3279 struct desc_ptr *ptr))
3280{
3281 struct desc_ptr desc_ptr;
3282
3283 if (ctxt->mode == X86EMUL_MODE_PROT64)
3284 ctxt->op_bytes = 8;
3285 get(ctxt, &desc_ptr);
3286 if (ctxt->op_bytes == 2) {
3287 ctxt->op_bytes = 4;
3288 desc_ptr.address &= 0x00ffffff;
3289 }
3290 /* Disable writeback. */
3291 ctxt->dst.type = OP_NONE;
3292 return segmented_write(ctxt, ctxt->dst.addr.mem,
3293 &desc_ptr, 2 + ctxt->op_bytes);
3294}
3295
3296static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3297{
3298 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3299}
3300
3301static int em_sidt(struct x86_emulate_ctxt *ctxt)
3302{
3303 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3304}
3305
26d05cc7
AK		 3306static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3307{
26d05cc7
AK		 3308 struct desc_ptr desc_ptr;
3309 int rc;
3310
510425ff
AK		 3311 if (ctxt->mode == X86EMUL_MODE_PROT64)
3312 ctxt->op_bytes = 8;
9dac77fa 3313 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3314 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3315 ctxt->op_bytes);
26d05cc7
AK		 3316 if (rc != X86EMUL_CONTINUE)
3317 return rc;
3318 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3319 /* Disable writeback. */
9dac77fa 3320 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3321 return X86EMUL_CONTINUE;
3322}
3323
5ef39c71 3324static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3325{
26d05cc7
AK		 3326 int rc;
3327
5ef39c71
AK		 3328 rc = ctxt->ops->fix_hypercall(ctxt);
3329
26d05cc7 3330 /* Disable writeback. */
9dac77fa 3331 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3332 return rc;
3333}
3334
3335static int em_lidt(struct x86_emulate_ctxt *ctxt)
3336{
26d05cc7
AK		 3337 struct desc_ptr desc_ptr;
3338 int rc;
3339
510425ff
AK		 3340 if (ctxt->mode == X86EMUL_MODE_PROT64)
3341 ctxt->op_bytes = 8;
9dac77fa 3342 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3343 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3344 ctxt->op_bytes);
26d05cc7
AK		 3345 if (rc != X86EMUL_CONTINUE)
3346 return rc;
3347 ctxt->ops->set_idt(ctxt, &desc_ptr);
3348 /* Disable writeback. */
9dac77fa 3349 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3350 return X86EMUL_CONTINUE;
3351}
3352
3353static int em_smsw(struct x86_emulate_ctxt *ctxt)
3354{
9dac77fa
AK		 3355 ctxt->dst.bytes = 2;
3356 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3357 return X86EMUL_CONTINUE;
3358}
3359
3360static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3361{
26d05cc7 3362 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3363 | (ctxt->src.val & 0x0f));
3364 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3365 return X86EMUL_CONTINUE;
3366}
3367
d06e03ad
TY		 3368static int em_loop(struct x86_emulate_ctxt *ctxt)
3369{
dd856efa
AK		 3370 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3371 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3372 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3373 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3374
3375 return X86EMUL_CONTINUE;
3376}
3377
3378static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3379{
dd856efa 3380 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3381 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3382
3383 return X86EMUL_CONTINUE;
3384}
3385
d7841a4b
TY		 3386static int em_in(struct x86_emulate_ctxt *ctxt)
3387{
3388 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3389 &ctxt->dst.val))
3390 return X86EMUL_IO_NEEDED;
3391
3392 return X86EMUL_CONTINUE;
3393}
3394
3395static int em_out(struct x86_emulate_ctxt *ctxt)
3396{
3397 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3398 &ctxt->src.val, 1);
3399 /* Disable writeback. */
3400 ctxt->dst.type = OP_NONE;
3401 return X86EMUL_CONTINUE;
3402}
3403
f411e6cd
TY		 3404static int em_cli(struct x86_emulate_ctxt *ctxt)
3405{
3406 if (emulator_bad_iopl(ctxt))
3407 return emulate_gp(ctxt, 0);
3408
3409 ctxt->eflags &= ~X86_EFLAGS_IF;
3410 return X86EMUL_CONTINUE;
3411}
3412
3413static int em_sti(struct x86_emulate_ctxt *ctxt)
3414{
3415 if (emulator_bad_iopl(ctxt))
3416 return emulate_gp(ctxt, 0);
3417
3418 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3419 ctxt->eflags |= X86_EFLAGS_IF;
3420 return X86EMUL_CONTINUE;
3421}
3422
ce7faab2
TY		 3423static int em_bt(struct x86_emulate_ctxt *ctxt)
3424{
3425 /* Disable writeback. */
3426 ctxt->dst.type = OP_NONE;
3427 /* only subword offset */
3428 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3429
3430 emulate_2op_SrcV_nobyte(ctxt, "bt");
3431 return X86EMUL_CONTINUE;
3432}
3433
3434static int em_bts(struct x86_emulate_ctxt *ctxt)
3435{
3436 emulate_2op_SrcV_nobyte(ctxt, "bts");
3437 return X86EMUL_CONTINUE;
3438}
3439
3440static int em_btr(struct x86_emulate_ctxt *ctxt)
3441{
3442 emulate_2op_SrcV_nobyte(ctxt, "btr");
3443 return X86EMUL_CONTINUE;
3444}
3445
3446static int em_btc(struct x86_emulate_ctxt *ctxt)
3447{
3448 emulate_2op_SrcV_nobyte(ctxt, "btc");
3449 return X86EMUL_CONTINUE;
3450}
3451
ff227392
TY		 3452static int em_bsf(struct x86_emulate_ctxt *ctxt)
3453{
d54e4237 3454 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3455 return X86EMUL_CONTINUE;
3456}
3457
3458static int em_bsr(struct x86_emulate_ctxt *ctxt)
3459{
d54e4237 3460 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3461 return X86EMUL_CONTINUE;
3462}
3463
6d6eede4
AK		 3464static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3465{
3466 u32 eax, ebx, ecx, edx;
3467
dd856efa
AK		 3468 eax = reg_read(ctxt, VCPU_REGS_RAX);
3469 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3470 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3471 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3472 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3473 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3474 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3475 return X86EMUL_CONTINUE;
3476}
3477
2dd7caa0
AK		 3478static int em_lahf(struct x86_emulate_ctxt *ctxt)
3479{
dd856efa
AK		 3480 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3481 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3482 return X86EMUL_CONTINUE;
3483}
3484
9299836e
AK		 3485static int em_bswap(struct x86_emulate_ctxt *ctxt)
3486{
3487 switch (ctxt->op_bytes) {
3488#ifdef CONFIG_X86_64
3489 case 8:
3490 asm("bswap %0" : "+r"(ctxt->dst.val));
3491 break;
3492#endif
3493 default:
3494 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3495 break;
3496 }
3497 return X86EMUL_CONTINUE;
3498}
3499
cfec82cb
JR		 3500static bool valid_cr(int nr)
3501{
3502 switch (nr) {
3503 case 0:
3504 case 2 ... 4:
3505 case 8:
3506 return true;
3507 default:
3508 return false;
3509 }
3510}
3511
3512static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3513{
9dac77fa 3514 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3515 return emulate_ud(ctxt);
3516
3517 return X86EMUL_CONTINUE;
3518}
3519
3520static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3521{
9dac77fa
AK		 3522 u64 new_val = ctxt->src.val64;
3523 int cr = ctxt->modrm_reg;
c2ad2bb3 3524 u64 efer = 0;
cfec82cb
JR		 3525
3526 static u64 cr_reserved_bits[] = {
3527 0xffffffff00000000ULL,
3528 0, 0, 0, /* CR3 checked later */
3529 CR4_RESERVED_BITS,
3530 0, 0, 0,
3531 CR8_RESERVED_BITS,
3532 };
3533
3534 if (!valid_cr(cr))
3535 return emulate_ud(ctxt);
3536
3537 if (new_val & cr_reserved_bits[cr])
3538 return emulate_gp(ctxt, 0);
3539
3540 switch (cr) {
3541 case 0: {
c2ad2bb3 3542 u64 cr4;
cfec82cb
JR		 3543 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3544 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3545 return emulate_gp(ctxt, 0);
3546
717746e3
AK		 3547 cr4 = ctxt->ops->get_cr(ctxt, 4);
3548 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3549
3550 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3551 !(cr4 & X86_CR4_PAE))
3552 return emulate_gp(ctxt, 0);
3553
3554 break;
3555 }
3556 case 3: {
3557 u64 rsvd = 0;
3558
c2ad2bb3
AK		 3559 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3560 if (efer & EFER_LMA)
cfec82cb 3561 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3562 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3563 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3564 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3565 rsvd = CR3_NONPAE_RESERVED_BITS;
3566
3567 if (new_val & rsvd)
3568 return emulate_gp(ctxt, 0);
3569
3570 break;
3571 }
3572 case 4: {
717746e3 3573 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3574
3575 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3576 return emulate_gp(ctxt, 0);
3577
3578 break;
3579 }
3580 }
3581
3582 return X86EMUL_CONTINUE;
3583}
3584
3b88e41a
JR		 3585static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3586{
3587 unsigned long dr7;
3588
717746e3 3589 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3590
3591 /* Check if DR7.Global_Enable is set */
3592 return dr7 & (1 << 13);
3593}
3594
3595static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3596{
9dac77fa 3597 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3598 u64 cr4;
3599
3600 if (dr > 7)
3601 return emulate_ud(ctxt);
3602
717746e3 3603 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3604 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3605 return emulate_ud(ctxt);
3606
3607 if (check_dr7_gd(ctxt))
3608 return emulate_db(ctxt);
3609
3610 return X86EMUL_CONTINUE;
3611}
3612
3613static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3614{
9dac77fa
AK		 3615 u64 new_val = ctxt->src.val64;
3616 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3617
3618 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3619 return emulate_gp(ctxt, 0);
3620
3621 return check_dr_read(ctxt);
3622}
3623
01de8b09
JR		 3624static int check_svme(struct x86_emulate_ctxt *ctxt)
3625{
3626 u64 efer;
3627
717746e3 3628 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3629
3630 if (!(efer & EFER_SVME))
3631 return emulate_ud(ctxt);
3632
3633 return X86EMUL_CONTINUE;
3634}
3635
3636static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3637{
dd856efa 3638 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3639
3640 /* Valid physical address? */
d4224449 3641 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3642 return emulate_gp(ctxt, 0);
3643
3644 return check_svme(ctxt);
3645}
3646
d7eb8203
JR		 3647static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3648{
717746e3 3649 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3650
717746e3 3651 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3652 return emulate_ud(ctxt);
3653
3654 return X86EMUL_CONTINUE;
3655}
3656
8061252e
JR		 3657static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3658{
717746e3 3659 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3660 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3661
717746e3 3662 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3663 (rcx > 3))
3664 return emulate_gp(ctxt, 0);
3665
3666 return X86EMUL_CONTINUE;
3667}
3668
f6511935
JR		 3669static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3670{
9dac77fa
AK		 3671 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3672 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3673 return emulate_gp(ctxt, 0);
3674
3675 return X86EMUL_CONTINUE;
3676}
3677
3678static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3679{
9dac77fa
AK		 3680 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3681 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3682 return emulate_gp(ctxt, 0);
3683
3684 return X86EMUL_CONTINUE;
3685}
3686
73fba5f4 3687#define D(_y) { .flags = (_y) }
c4f035c6 3688#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3689#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3690 .check_perm = (_p) }
73fba5f4 3691#define N D(0)
01de8b09 3692#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3693#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3694#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3695#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3696#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3697#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3698#define II(_f, _e, _i) \
3699 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3700#define IIP(_f, _e, _i, _p) \
3701 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3702 .check_perm = (_p) }
aa97bb48 3703#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3704
8d8f4e9f 3705#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3706#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3707#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3708#define I2bvIP(_f, _e, _i, _p) \
3709 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3710
d67fc27a
TY		 3711#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3712 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3713 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3714
fd0a0d82 3715static const struct opcode group7_rm1[] = {
1c2545be
TY		 3716 DI(SrcNone | Priv, monitor),
3717 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3718 N, N, N, N, N, N,
3719};
3720
fd0a0d82 3721static const struct opcode group7_rm3[] = {
1c2545be
TY		 3722 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3723 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3724 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3725 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3726 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3727 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3728 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3729 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3730};
6230f7fc 3731
fd0a0d82 3732static const struct opcode group7_rm7[] = {
d7eb8203 3733 N,
1c2545be 3734 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3735 N, N, N, N, N, N,
3736};
d67fc27a 3737
fd0a0d82 3738static const struct opcode group1[] = {
d67fc27a 3739 I(Lock, em_add),
d5ae7ce8 3740 I(Lock | PageTable, em_or),
d67fc27a
TY		 3741 I(Lock, em_adc),
3742 I(Lock, em_sbb),
d5ae7ce8 3743 I(Lock | PageTable, em_and),
d67fc27a
TY		 3744 I(Lock, em_sub),
3745 I(Lock, em_xor),
75f72845 3746 I(NoWrite, em_cmp),
73fba5f4
AK		 3747};
3748
fd0a0d82 3749static const struct opcode group1A[] = {
1c2545be 3750 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3751};
3752
fd0a0d82 3753static const struct opcode group3[] = {
75f72845
AK		 3754 I(DstMem | SrcImm | NoWrite, em_test),
3755 I(DstMem | SrcImm | NoWrite, em_test),
1c2545be
TY		 3756 I(DstMem | SrcNone | Lock, em_not),
3757 I(DstMem | SrcNone | Lock, em_neg),
3758 I(SrcMem, em_mul_ex),
3759 I(SrcMem, em_imul_ex),
3760 I(SrcMem, em_div_ex),
3761 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3762};
3763
fd0a0d82 3764static const struct opcode group4[] = {
1c2545be
TY		 3765 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3766 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3767 N, N, N, N, N, N,
3768};
3769
fd0a0d82 3770static const struct opcode group5[] = {
1c2545be
TY		 3771 I(DstMem | SrcNone | Lock, em_grp45),
3772 I(DstMem | SrcNone | Lock, em_grp45),
3773 I(SrcMem | Stack, em_grp45),
3774 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3775 I(SrcMem | Stack, em_grp45),
3776 I(SrcMemFAddr | ImplicitOps, em_grp45),
3777 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3778};
3779
fd0a0d82 3780static const struct opcode group6[] = {
1c2545be
TY		 3781 DI(Prot, sldt),
3782 DI(Prot, str),
a14e579f 3783 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3784 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3785 N, N, N, N,
3786};
3787
fd0a0d82 3788static const struct group_dual group7 = { {
96051572
AK		 3789 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3790 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3791 II(SrcMem | Priv, em_lgdt, lgdt),
3792 II(SrcMem | Priv, em_lidt, lidt),
3793 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3794 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3795 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3796}, {
1c2545be 3797 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3798 EXT(0, group7_rm1),
01de8b09 3799 N, EXT(0, group7_rm3),
1c2545be
TY		 3800 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3801 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3802 EXT(0, group7_rm7),
73fba5f4
AK		 3803} };
3804
fd0a0d82 3805static const struct opcode group8[] = {
73fba5f4 3806 N, N, N, N,
1c2545be
TY		 3807 I(DstMem | SrcImmByte, em_bt),
3808 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3809 I(DstMem | SrcImmByte | Lock, em_btr),
3810 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3811};
3812
fd0a0d82 3813static const struct group_dual group9 = { {
1c2545be 3814 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3815}, {
3816 N, N, N, N, N, N, N, N,
3817} };
3818
fd0a0d82 3819static const struct opcode group11[] = {
1c2545be 3820 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3821 X7(D(Undefined)),
a4d4a7c1
AK		 3822};
3823
fd0a0d82 3824static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3825 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3826};
3827
fd0a0d82 3828static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3829 I(0, em_mov), N, N, N,
3830};
3831
045a282c
GN		 3832static const struct escape escape_d9 = { {
3833 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3834}, {
3835 /* 0xC0 - 0xC7 */
3836 N, N, N, N, N, N, N, N,
3837 /* 0xC8 - 0xCF */
3838 N, N, N, N, N, N, N, N,
3839 /* 0xD0 - 0xC7 */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xD8 - 0xDF */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xE0 - 0xE7 */
3844 N, N, N, N, N, N, N, N,
3845 /* 0xE8 - 0xEF */
3846 N, N, N, N, N, N, N, N,
3847 /* 0xF0 - 0xF7 */
3848 N, N, N, N, N, N, N, N,
3849 /* 0xF8 - 0xFF */
3850 N, N, N, N, N, N, N, N,
3851} };
3852
3853static const struct escape escape_db = { {
3854 N, N, N, N, N, N, N, N,
3855}, {
3856 /* 0xC0 - 0xC7 */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xC8 - 0xCF */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xD0 - 0xC7 */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xD8 - 0xDF */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xE0 - 0xE7 */
3865 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3866 /* 0xE8 - 0xEF */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xF0 - 0xF7 */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xF8 - 0xFF */
3871 N, N, N, N, N, N, N, N,
3872} };
3873
3874static const struct escape escape_dd = { {
3875 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3876}, {
3877 /* 0xC0 - 0xC7 */
3878 N, N, N, N, N, N, N, N,
3879 /* 0xC8 - 0xCF */
3880 N, N, N, N, N, N, N, N,
3881 /* 0xD0 - 0xC7 */
3882 N, N, N, N, N, N, N, N,
3883 /* 0xD8 - 0xDF */
3884 N, N, N, N, N, N, N, N,
3885 /* 0xE0 - 0xE7 */
3886 N, N, N, N, N, N, N, N,
3887 /* 0xE8 - 0xEF */
3888 N, N, N, N, N, N, N, N,
3889 /* 0xF0 - 0xF7 */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xF8 - 0xFF */
3892 N, N, N, N, N, N, N, N,
3893} };
3894
fd0a0d82 3895static const struct opcode opcode_table[256] = {
73fba5f4 3896 /* 0x00 - 0x07 */
d67fc27a 3897 I6ALU(Lock, em_add),
1cd196ea
AK		 3898 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3899 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3900 /* 0x08 - 0x0F */
d5ae7ce8 3901 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3902 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3903 N,
73fba5f4 3904 /* 0x10 - 0x17 */
d67fc27a 3905 I6ALU(Lock, em_adc),
1cd196ea
AK		 3906 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3907 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3908 /* 0x18 - 0x1F */
d67fc27a 3909 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3910 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3911 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3912 /* 0x20 - 0x27 */
d5ae7ce8 3913 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3914 /* 0x28 - 0x2F */
d67fc27a 3915 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3916 /* 0x30 - 0x37 */
d67fc27a 3917 I6ALU(Lock, em_xor), N, N,
73fba5f4 3918 /* 0x38 - 0x3F */
75f72845 3919 I6ALU(NoWrite, em_cmp), N, N,
73fba5f4
AK		 3920 /* 0x40 - 0x4F */
3921 X16(D(DstReg)),
3922 /* 0x50 - 0x57 */
63540382 3923 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3924 /* 0x58 - 0x5F */
c54fe504 3925 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3926 /* 0x60 - 0x67 */
b96a7fad
TY		 3927 I(ImplicitOps | Stack | No64, em_pusha),
3928 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3929 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3930 N, N, N, N,
3931 /* 0x68 - 0x6F */
d46164db
AK		 3932 I(SrcImm | Mov | Stack, em_push),
3933 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3934 I(SrcImmByte | Mov | Stack, em_push),
3935 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3936 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3937 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3938 /* 0x70 - 0x7F */
3939 X16(D(SrcImmByte)),
3940 /* 0x80 - 0x87 */
1c2545be
TY		 3941 G(ByteOp | DstMem | SrcImm, group1),
3942 G(DstMem | SrcImm, group1),
3943 G(ByteOp | DstMem | SrcImm | No64, group1),
3944 G(DstMem | SrcImmByte, group1),
75f72845 3945 I2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3946 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3947 /* 0x88 - 0x8F */
d5ae7ce8 3948 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3949 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3950 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3951 D(ModRM | SrcMem | NoAccess | DstReg),
3952 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3953 G(0, group1A),
73fba5f4 3954 /* 0x90 - 0x97 */
bf608f88 3955 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3956 /* 0x98 - 0x9F */
61429142 3957 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3958 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3959 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3960 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3961 /* 0xA0 - 0xA7 */
b9eac5f4 3962 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3963 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3964 I2bv(SrcSI | DstDI | Mov | String, em_mov),
75f72845 3965 I2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3966 /* 0xA8 - 0xAF */
75f72845 3967 I2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3968 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3969 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
75f72845 3970 I2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3971 /* 0xB0 - 0xB7 */
b9eac5f4 3972 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3973 /* 0xB8 - 0xBF */
5e2c6883 3974 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3975 /* 0xC0 - 0xC7 */
d2c6c7ad 3976 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3977 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3978 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3979 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3980 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3981 G(ByteOp, group11), G(0, group11),
73fba5f4 3982 /* 0xC8 - 0xCF */
612e89f0
AK		 3983 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3984 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3985 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3986 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3987 /* 0xD0 - 0xD7 */
d2c6c7ad 3988 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3989 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3990 /* 0xD8 - 0xDF */
045a282c 3991 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3992 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3993 X3(I(SrcImmByte, em_loop)),
3994 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3995 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3996 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3997 /* 0xE8 - 0xEF */
d4ddafcd 3998 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3999 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 4000 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4001 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4002 /* 0xF0 - 0xF7 */
bf608f88 4003 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4004 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4005 G(ByteOp, group3), G(0, group3),
73fba5f4 4006 /* 0xF8 - 0xFF */
f411e6cd
TY		 4007 D(ImplicitOps), D(ImplicitOps),
4008 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4009 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4010};
4011
fd0a0d82 4012static const struct opcode twobyte_table[256] = {
73fba5f4 4013 /* 0x00 - 0x0F */
dee6bb70 4014 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 4015 N, I(ImplicitOps | VendorSpecific, em_syscall),
4016 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4017 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 4018 N, D(ImplicitOps | ModRM), N, N,
4019 /* 0x10 - 0x1F */
4020 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
4021 /* 0x20 - 0x2F */
cfec82cb 4022 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 4023 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4024 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4025 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4026 N, N, N, N,
3e114eb4
AK		 4027 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4028 N, N, N, N,
73fba5f4 4029 /* 0x30 - 0x3F */
e1e210b0 4030 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4031 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4032 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4033 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4034 I(ImplicitOps | VendorSpecific, em_sysenter),
4035 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4036 N, N,
73fba5f4
AK		 4037 N, N, N, N, N, N, N, N,
4038 /* 0x40 - 0x4F */
4039 X16(D(DstReg | SrcMem | ModRM | Mov)),
4040 /* 0x50 - 0x5F */
4041 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4042 /* 0x60 - 0x6F */
aa97bb48
AK		 4043 N, N, N, N,
4044 N, N, N, N,
4045 N, N, N, N,
4046 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4047 /* 0x70 - 0x7F */
aa97bb48
AK		 4048 N, N, N, N,
4049 N, N, N, N,
4050 N, N, N, N,
4051 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4052 /* 0x80 - 0x8F */
4053 X16(D(SrcImm)),
4054 /* 0x90 - 0x9F */
ee45b58e 4055 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4056 /* 0xA0 - 0xA7 */
1cd196ea 4057 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 4058 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 4059 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4060 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
4061 /* 0xA8 - 0xAF */
1cd196ea 4062 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4063 DI(ImplicitOps, rsm),
ce7faab2 4064 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 4065 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4066 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 4067 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4068 /* 0xB0 - 0xB7 */
e940b5c2 4069 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4070 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 4071 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4072 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4073 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4074 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4075 /* 0xB8 - 0xBF */
4076 N, N,
ce7faab2
TY		 4077 G(BitOp, group8),
4078 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 4079 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4080 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4081 /* 0xC0 - 0xC7 */
739ae406 4082 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4083 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4084 N, N, N, GD(0, &group9),
9299836e
AK		 4085 /* 0xC8 - 0xCF */
4086 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4087 /* 0xD0 - 0xDF */
4088 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4089 /* 0xE0 - 0xEF */
4090 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4091 /* 0xF0 - 0xFF */
4092 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4093};
4094
4095#undef D
4096#undef N
4097#undef G
4098#undef GD
4099#undef I
aa97bb48 4100#undef GP
01de8b09 4101#undef EXT
73fba5f4 4102
8d8f4e9f 4103#undef D2bv
f6511935 4104#undef D2bvIP
8d8f4e9f 4105#undef I2bv
d7841a4b 4106#undef I2bvIP
d67fc27a 4107#undef I6ALU
8d8f4e9f 4108
9dac77fa 4109static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4110{
4111 unsigned size;
4112
9dac77fa 4113 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4114 if (size == 8)
4115 size = 4;
4116 return size;
4117}
4118
4119static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4120 unsigned size, bool sign_extension)
4121{
39f21ee5
AK		 4122 int rc = X86EMUL_CONTINUE;
4123
4124 op->type = OP_IMM;
4125 op->bytes = size;
9dac77fa 4126 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4127 /* NB. Immediates are sign-extended as necessary. */
4128 switch (op->bytes) {
4129 case 1:
e85a1085 4130 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4131 break;
4132 case 2:
e85a1085 4133 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4134 break;
4135 case 4:
e85a1085 4136 op->val = insn_fetch(s32, ctxt);
39f21ee5 4137 break;
5e2c6883
NA		 4138 case 8:
4139 op->val = insn_fetch(s64, ctxt);
4140 break;
39f21ee5
AK		 4141 }
4142 if (!sign_extension) {
4143 switch (op->bytes) {
4144 case 1:
4145 op->val &= 0xff;
4146 break;
4147 case 2:
4148 op->val &= 0xffff;
4149 break;
4150 case 4:
4151 op->val &= 0xffffffff;
4152 break;
4153 }
4154 }
4155done:
4156 return rc;
4157}
4158
a9945549
AK		 4159static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4160 unsigned d)
4161{
4162 int rc = X86EMUL_CONTINUE;
4163
4164 switch (d) {
4165 case OpReg:
2adb5ad9 4166 decode_register_operand(ctxt, op);
a9945549
AK		 4167 break;
4168 case OpImmUByte:
608aabe3 4169 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4170 break;
4171 case OpMem:
41ddf978 4172 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4173 mem_common:
4174 *op = ctxt->memop;
4175 ctxt->memopp = op;
4176 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4177 fetch_bit_operand(ctxt);
4178 op->orig_val = op->val;
4179 break;
41ddf978
AK		 4180 case OpMem64:
4181 ctxt->memop.bytes = 8;
4182 goto mem_common;
a9945549
AK		 4183 case OpAcc:
4184 op->type = OP_REG;
4185 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4186 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4187 fetch_register_operand(op);
4188 op->orig_val = op->val;
4189 break;
4190 case OpDI:
4191 op->type = OP_MEM;
4192 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4193 op->addr.mem.ea =
dd856efa 4194 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4195 op->addr.mem.seg = VCPU_SREG_ES;
4196 op->val = 0;
b3356bf0 4197 op->count = 1;
a9945549
AK		 4198 break;
4199 case OpDX:
4200 op->type = OP_REG;
4201 op->bytes = 2;
dd856efa 4202 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4203 fetch_register_operand(op);
4204 break;
4dd6a57d
AK		 4205 case OpCL:
4206 op->bytes = 1;
dd856efa 4207 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4208 break;
4209 case OpImmByte:
4210 rc = decode_imm(ctxt, op, 1, true);
4211 break;
4212 case OpOne:
4213 op->bytes = 1;
4214 op->val = 1;
4215 break;
4216 case OpImm:
4217 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4218 break;
5e2c6883
NA		 4219 case OpImm64:
4220 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4221 break;
28867cee
AK		 4222 case OpMem8:
4223 ctxt->memop.bytes = 1;
4224 goto mem_common;
0fe59128
AK		 4225 case OpMem16:
4226 ctxt->memop.bytes = 2;
4227 goto mem_common;
4228 case OpMem32:
4229 ctxt->memop.bytes = 4;
4230 goto mem_common;
4231 case OpImmU16:
4232 rc = decode_imm(ctxt, op, 2, false);
4233 break;
4234 case OpImmU:
4235 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4236 break;
4237 case OpSI:
4238 op->type = OP_MEM;
4239 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4240 op->addr.mem.ea =
dd856efa 4241 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4242 op->addr.mem.seg = seg_override(ctxt);
4243 op->val = 0;
b3356bf0 4244 op->count = 1;
0fe59128
AK		 4245 break;
4246 case OpImmFAddr:
4247 op->type = OP_IMM;
4248 op->addr.mem.ea = ctxt->_eip;
4249 op->bytes = ctxt->op_bytes + 2;
4250 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4251 break;
4252 case OpMemFAddr:
4253 ctxt->memop.bytes = ctxt->op_bytes + 2;
4254 goto mem_common;
c191a7a0
AK		 4255 case OpES:
4256 op->val = VCPU_SREG_ES;
4257 break;
4258 case OpCS:
4259 op->val = VCPU_SREG_CS;
4260 break;
4261 case OpSS:
4262 op->val = VCPU_SREG_SS;
4263 break;
4264 case OpDS:
4265 op->val = VCPU_SREG_DS;
4266 break;
4267 case OpFS:
4268 op->val = VCPU_SREG_FS;
4269 break;
4270 case OpGS:
4271 op->val = VCPU_SREG_GS;
4272 break;
a9945549
AK		 4273 case OpImplicit:
4274 /* Special instructions do their own operand decoding. */
4275 default:
4276 op->type = OP_NONE; /* Disable writeback. */
4277 break;
4278 }
4279
4280done:
4281 return rc;
4282}
4283
ef5d75cc 4284int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4285{
dde7e6d1
AK		 4286 int rc = X86EMUL_CONTINUE;
4287 int mode = ctxt->mode;
46561646 4288 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4289 bool op_prefix = false;
46561646 4290 struct opcode opcode;
dde7e6d1 4291
f09ed83e
AK		 4292 ctxt->memop.type = OP_NONE;
4293 ctxt->memopp = NULL;
9dac77fa
AK		 4294 ctxt->_eip = ctxt->eip;
4295 ctxt->fetch.start = ctxt->_eip;
4296 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4297 if (insn_len > 0)
9dac77fa 4298 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4299
4300 switch (mode) {
4301 case X86EMUL_MODE_REAL:
4302 case X86EMUL_MODE_VM86:
4303 case X86EMUL_MODE_PROT16:
4304 def_op_bytes = def_ad_bytes = 2;
4305 break;
4306 case X86EMUL_MODE_PROT32:
4307 def_op_bytes = def_ad_bytes = 4;
4308 break;
4309#ifdef CONFIG_X86_64
4310 case X86EMUL_MODE_PROT64:
4311 def_op_bytes = 4;
4312 def_ad_bytes = 8;
4313 break;
4314#endif
4315 default:
1d2887e2 4316 return EMULATION_FAILED;
dde7e6d1
AK		 4317 }
4318
9dac77fa
AK		 4319 ctxt->op_bytes = def_op_bytes;
4320 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4321
4322 /* Legacy prefixes. */
4323 for (;;) {
e85a1085 4324 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4325 case 0x66: /* operand-size override */
0d7cdee8 4326 op_prefix = true;
dde7e6d1 4327 /* switch between 2/4 bytes */
9dac77fa 4328 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4329 break;
4330 case 0x67: /* address-size override */
4331 if (mode == X86EMUL_MODE_PROT64)
4332 /* switch between 4/8 bytes */
9dac77fa 4333 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4334 else
4335 /* switch between 2/4 bytes */
9dac77fa 4336 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4337 break;
4338 case 0x26: /* ES override */
4339 case 0x2e: /* CS override */
4340 case 0x36: /* SS override */
4341 case 0x3e: /* DS override */
9dac77fa 4342 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4343 break;
4344 case 0x64: /* FS override */
4345 case 0x65: /* GS override */
9dac77fa 4346 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4347 break;
4348 case 0x40 ... 0x4f: /* REX */
4349 if (mode != X86EMUL_MODE_PROT64)
4350 goto done_prefixes;
9dac77fa 4351 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4352 continue;
4353 case 0xf0: /* LOCK */
9dac77fa 4354 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4355 break;
4356 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4357 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4358 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4359 break;
4360 default:
4361 goto done_prefixes;
4362 }
4363
4364 /* Any legacy prefix after a REX prefix nullifies its effect. */
4365
9dac77fa 4366 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4367 }
4368
4369done_prefixes:
4370
4371 /* REX prefix. */
9dac77fa
AK		 4372 if (ctxt->rex_prefix & 8)
4373 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4374
4375 /* Opcode byte(s). */
9dac77fa 4376 opcode = opcode_table[ctxt->b];
d3ad6243 4377 /* Two-byte opcode? */
9dac77fa
AK		 4378 if (ctxt->b == 0x0f) {
4379 ctxt->twobyte = 1;
e85a1085 4380 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4381 opcode = twobyte_table[ctxt->b];
dde7e6d1 4382 }
9dac77fa 4383 ctxt->d = opcode.flags;
dde7e6d1 4384
9f4260e7
TY		 4385 if (ctxt->d & ModRM)
4386 ctxt->modrm = insn_fetch(u8, ctxt);
4387
9dac77fa
AK		 4388 while (ctxt->d & GroupMask) {
4389 switch (ctxt->d & GroupMask) {
46561646 4390 case Group:
9dac77fa 4391 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4392 opcode = opcode.u.group[goffset];
4393 break;
4394 case GroupDual:
9dac77fa
AK		 4395 goffset = (ctxt->modrm >> 3) & 7;
4396 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4397 opcode = opcode.u.gdual->mod3[goffset];
4398 else
4399 opcode = opcode.u.gdual->mod012[goffset];
4400 break;
4401 case RMExt:
9dac77fa 4402 goffset = ctxt->modrm & 7;
01de8b09 4403 opcode = opcode.u.group[goffset];
46561646
AK		 4404 break;
4405 case Prefix:
9dac77fa 4406 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4407 return EMULATION_FAILED;
9dac77fa 4408 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4409 switch (simd_prefix) {
4410 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4411 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4412 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4413 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4414 }
4415 break;
045a282c
GN		 4416 case Escape:
4417 if (ctxt->modrm > 0xbf)
4418 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4419 else
4420 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4421 break;
46561646 4422 default:
1d2887e2 4423 return EMULATION_FAILED;
0d7cdee8 4424 }
46561646 4425
b1ea50b2 4426 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4427 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4428 }
4429
9dac77fa
AK		 4430 ctxt->execute = opcode.u.execute;
4431 ctxt->check_perm = opcode.check_perm;
4432 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4433
4434 /* Unrecognised? */
9dac77fa 4435 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4436 return EMULATION_FAILED;
dde7e6d1 4437
9dac77fa 4438 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4439 return EMULATION_FAILED;
d867162c 4440
9dac77fa
AK		 4441 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4442 ctxt->op_bytes = 8;
dde7e6d1 4443
9dac77fa 4444 if (ctxt->d & Op3264) {
7f9b4b75 4445 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4446 ctxt->op_bytes = 8;
7f9b4b75 4447 else
9dac77fa 4448 ctxt->op_bytes = 4;
7f9b4b75
AK		 4449 }
4450
9dac77fa
AK		 4451 if (ctxt->d & Sse)
4452 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4453 else if (ctxt->d & Mmx)
4454 ctxt->op_bytes = 8;
1253791d 4455
dde7e6d1 4456 /* ModRM and SIB bytes. */
9dac77fa 4457 if (ctxt->d & ModRM) {
f09ed83e 4458 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4459 if (!ctxt->has_seg_override)
4460 set_seg_override(ctxt, ctxt->modrm_seg);
4461 } else if (ctxt->d & MemAbs)
f09ed83e 4462 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4463 if (rc != X86EMUL_CONTINUE)
4464 goto done;
4465
9dac77fa
AK		 4466 if (!ctxt->has_seg_override)
4467 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4468
f09ed83e 4469 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4470
f09ed83e
AK		 4471 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4472 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4473
dde7e6d1
AK		 4474 /*
4475 * Decode and fetch the source operand: register, memory
4476 * or immediate.
4477 */
0fe59128 4478 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4479 if (rc != X86EMUL_CONTINUE)
4480 goto done;
4481
dde7e6d1
AK		 4482 /*
4483 * Decode and fetch the second source operand: register, memory
4484 * or immediate.
4485 */
4dd6a57d 4486 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4487 if (rc != X86EMUL_CONTINUE)
4488 goto done;
4489
dde7e6d1 4490 /* Decode and fetch the destination operand: register or memory. */
a9945549 4491 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4492
4493done:
f09ed83e
AK		 4494 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4495 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4496
1d2887e2 4497 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4498}
4499
1cb3f3ae
XG		 4500bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4501{
4502 return ctxt->d & PageTable;
4503}
4504
3e2f65d5
GN		 4505static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4506{
3e2f65d5
GN		 4507 /* The second termination condition only applies for REPE
4508 * and REPNE. Test if the repeat string operation prefix is
4509 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4510 * corresponding termination condition according to:
4511 * - if REPE/REPZ and ZF = 0 then done
4512 * - if REPNE/REPNZ and ZF = 1 then done
4513 */
9dac77fa
AK		 4514 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4515 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4516 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4517 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4518 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4519 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4520 return true;
4521
4522 return false;
4523}
4524
cbe2c9d3
AK		 4525static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4526{
4527 bool fault = false;
4528
4529 ctxt->ops->get_fpu(ctxt);
4530 asm volatile("1: fwait \n\t"
4531 "2: \n\t"
4532 ".pushsection .fixup,\"ax\" \n\t"
4533 "3: \n\t"
4534 "movb $1, %[fault] \n\t"
4535 "jmp 2b \n\t"
4536 ".popsection \n\t"
4537 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4538 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4539 ctxt->ops->put_fpu(ctxt);
4540
4541 if (unlikely(fault))
4542 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4543
4544 return X86EMUL_CONTINUE;
4545}
4546
4547static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4548 struct operand *op)
4549{
4550 if (op->type == OP_MM)
4551 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4552}
4553
e28bbd44
AK		 4554static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4555{
4556 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4557 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4558 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4559 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4560 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4561 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4562 return X86EMUL_CONTINUE;
4563}
dd856efa 4564
7b105ca2 4565int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4566{
0225fb50 4567 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4568 int rc = X86EMUL_CONTINUE;
9dac77fa 4569 int saved_dst_type = ctxt->dst.type;
8b4caf66 4570
9dac77fa 4571 ctxt->mem_read.pos = 0;
310b5d30 4572
9dac77fa 4573 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4574 rc = emulate_ud(ctxt);
1161624f
GN		 4575 goto done;
4576 }
4577
d380a5e4 4578 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4579 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4580 rc = emulate_ud(ctxt);
d380a5e4
GN		 4581 goto done;
4582 }
4583
9dac77fa 4584 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4585 rc = emulate_ud(ctxt);
081bca0e
AK		 4586 goto done;
4587 }
4588
cbe2c9d3
AK		 4589 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4590 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4591 rc = emulate_ud(ctxt);
4592 goto done;
4593 }
4594
cbe2c9d3 4595 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4596 rc = emulate_nm(ctxt);
4597 goto done;
4598 }
4599
cbe2c9d3
AK		 4600 if (ctxt->d & Mmx) {
4601 rc = flush_pending_x87_faults(ctxt);
4602 if (rc != X86EMUL_CONTINUE)
4603 goto done;
4604 /*
4605 * Now that we know the fpu is exception safe, we can fetch
4606 * operands from it.
4607 */
4608 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4609 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4610 if (!(ctxt->d & Mov))
4611 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4612 }
4613
9dac77fa
AK		 4614 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4615 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4616 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4617 if (rc != X86EMUL_CONTINUE)
4618 goto done;
4619 }
4620
e92805ac 4621 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4622 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4623 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4624 goto done;
4625 }
4626
8ea7d6ae 4627 /* Instruction can only be executed in protected mode */
9d1b39a9 4628 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4629 rc = emulate_ud(ctxt);
4630 goto done;
4631 }
4632
d09beabd 4633 /* Do instruction specific permission checks */
9dac77fa
AK		 4634 if (ctxt->check_perm) {
4635 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4636 if (rc != X86EMUL_CONTINUE)
4637 goto done;
4638 }
4639
9dac77fa
AK		 4640 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4641 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4642 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4643 if (rc != X86EMUL_CONTINUE)
4644 goto done;
4645 }
4646
9dac77fa 4647 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4648 /* All REP prefixes have the same first termination condition */
dd856efa 4649 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4650 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4651 goto done;
4652 }
b9fa9d6b
AK		 4653 }
4654
9dac77fa
AK		 4655 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4656 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4657 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4658 if (rc != X86EMUL_CONTINUE)
8b4caf66 4659 goto done;
9dac77fa 4660 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4661 }
4662
9dac77fa
AK		 4663 if (ctxt->src2.type == OP_MEM) {
4664 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4665 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4666 if (rc != X86EMUL_CONTINUE)
4667 goto done;
4668 }
4669
9dac77fa 4670 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4671 goto special_insn;
4672
4673
9dac77fa 4674 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4675 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4676 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4677 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4678 if (rc != X86EMUL_CONTINUE)
4679 goto done;
038e51de 4680 }
9dac77fa 4681 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4682
018a98db
AK		 4683special_insn:
4684
9dac77fa
AK		 4685 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4686 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4687 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4688 if (rc != X86EMUL_CONTINUE)
4689 goto done;
4690 }
4691
9dac77fa 4692 if (ctxt->execute) {
e28bbd44
AK		 4693 if (ctxt->d & Fastop) {
4694 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4695 rc = fastop(ctxt, fop);
4696 if (rc != X86EMUL_CONTINUE)
4697 goto done;
4698 goto writeback;
4699 }
9dac77fa 4700 rc = ctxt->execute(ctxt);
ef65c889
AK		 4701 if (rc != X86EMUL_CONTINUE)
4702 goto done;
4703 goto writeback;
4704 }
4705
9dac77fa 4706 if (ctxt->twobyte)
6aa8b732
AK		 4707 goto twobyte_insn;
4708
9dac77fa 4709 switch (ctxt->b) {
33615aa9 4710 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4711 emulate_1op(ctxt, "inc");
33615aa9
AK		 4712 break;
4713 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4714 emulate_1op(ctxt, "dec");
33615aa9 4715 break;
6aa8b732 4716 case 0x63: /* movsxd */
8b4caf66 4717 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4718 goto cannot_emulate;
9dac77fa 4719 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4720 break;
b2833e3c 4721 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4722 if (test_cc(ctxt->b, ctxt->eflags))
4723 jmp_rel(ctxt, ctxt->src.val);
018a98db 4724 break;
7e0b54b1 4725 case 0x8d: /* lea r16/r32, m */
9dac77fa 4726 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4727 break;
3d9e77df 4728 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4729 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4730 break;
e4f973ae
TY		 4731 rc = em_xchg(ctxt);
4732 break;
e8b6fa70 4733 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4734 switch (ctxt->op_bytes) {
4735 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4736 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4737 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4738 }
4739 break;
018a98db 4740 case 0xc0 ... 0xc1:
51187683 4741 rc = em_grp2(ctxt);
018a98db 4742 break;
6e154e56 4743 case 0xcc: /* int3 */
5c5df76b
TY		 4744 rc = emulate_int(ctxt, 3);
4745 break;
6e154e56 4746 case 0xcd: /* int n */
9dac77fa 4747 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4748 break;
4749 case 0xce: /* into */
5c5df76b
TY		 4750 if (ctxt->eflags & EFLG_OF)
4751 rc = emulate_int(ctxt, 4);
6e154e56 4752 break;
018a98db 4753 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4754 rc = em_grp2(ctxt);
018a98db
AK		 4755 break;
4756 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4757 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4758 rc = em_grp2(ctxt);
018a98db 4759 break;
1a52e051 4760 case 0xe9: /* jmp rel */
db5b0762 4761 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4762 jmp_rel(ctxt, ctxt->src.val);
4763 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4764 break;
111de5d6 4765 case 0xf4: /* hlt */
6c3287f7 4766 ctxt->ops->halt(ctxt);
19fdfa0d 4767 break;
111de5d6
AK		 4768 case 0xf5: /* cmc */
4769 /* complement carry flag from eflags reg */
4770 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4771 break;
4772 case 0xf8: /* clc */
4773 ctxt->eflags &= ~EFLG_CF;
111de5d6 4774 break;
8744aa9a
MG		 4775 case 0xf9: /* stc */
4776 ctxt->eflags |= EFLG_CF;
4777 break;
fb4616f4
MG		 4778 case 0xfc: /* cld */
4779 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4780 break;
4781 case 0xfd: /* std */
4782 ctxt->eflags |= EFLG_DF;
fb4616f4 4783 break;
91269b8f
AK		 4784 default:
4785 goto cannot_emulate;
6aa8b732 4786 }
018a98db 4787
7d9ddaed
AK		 4788 if (rc != X86EMUL_CONTINUE)
4789 goto done;
4790
018a98db 4791writeback:
adddcecf 4792 rc = writeback(ctxt);
1b30eaa8 4793 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4794 goto done;
4795
5cd21917
GN		 4796 /*
4797 * restore dst type in case the decoding will be reused
4798 * (happens for string instruction )
4799 */
9dac77fa 4800 ctxt->dst.type = saved_dst_type;
5cd21917 4801
9dac77fa 4802 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4803 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4804
9dac77fa 4805 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4806 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4807
9dac77fa 4808 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4809 unsigned int count;
9dac77fa 4810 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4811 if ((ctxt->d & SrcMask) == SrcSI)
4812 count = ctxt->src.count;
4813 else
4814 count = ctxt->dst.count;
4815 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4816 -count);
3e2f65d5 4817
d2ddd1c4
GN		 4818 if (!string_insn_completed(ctxt)) {
4819 /*
4820 * Re-enter guest when pio read ahead buffer is empty
4821 * or, if it is not used, after each 1024 iteration.
4822 */
dd856efa 4823 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4824 (r->end == 0 || r->end != r->pos)) {
4825 /*
4826 * Reset read cache. Usually happens before
4827 * decode, but since instruction is restarted
4828 * we have to do it here.
4829 */
9dac77fa 4830 ctxt->mem_read.end = 0;
dd856efa 4831 writeback_registers(ctxt);
d2ddd1c4
GN		 4832 return EMULATION_RESTART;
4833 }
4834 goto done; /* skip rip writeback */
0fa6ccbd 4835 }
5cd21917 4836 }
d2ddd1c4 4837
9dac77fa 4838 ctxt->eip = ctxt->_eip;
018a98db
AK		 4839
4840done:
da9cb575
AK		 4841 if (rc == X86EMUL_PROPAGATE_FAULT)
4842 ctxt->have_exception = true;
775fde86
JR		 4843 if (rc == X86EMUL_INTERCEPTED)
4844 return EMULATION_INTERCEPTED;
4845
dd856efa
AK		 4846 if (rc == X86EMUL_CONTINUE)
4847 writeback_registers(ctxt);
4848
d2ddd1c4 4849 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4850
4851twobyte_insn:
9dac77fa 4852 switch (ctxt->b) {
018a98db 4853 case 0x09: /* wbinvd */
cfb22375 4854 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4855 break;
4856 case 0x08: /* invd */
018a98db
AK		 4857 case 0x0d: /* GrpP (prefetch) */
4858 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4859 break;
4860 case 0x20: /* mov cr, reg */
9dac77fa 4861 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4862 break;
6aa8b732 4863 case 0x21: /* mov from dr to reg */
9dac77fa 4864 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4865 break;
6aa8b732 4866 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4867 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4868 if (!test_cc(ctxt->b, ctxt->eflags))
4869 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4870 break;
b2833e3c 4871 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4872 if (test_cc(ctxt->b, ctxt->eflags))
4873 jmp_rel(ctxt, ctxt->src.val);
018a98db 4874 break;
ee45b58e 4875 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4876 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4877 break;
9bf8ea42
GT		 4878 case 0xa4: /* shld imm8, r, r/m */
4879 case 0xa5: /* shld cl, r, r/m */
761441b9 4880 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4881 break;
9bf8ea42
GT		 4882 case 0xac: /* shrd imm8, r, r/m */
4883 case 0xad: /* shrd cl, r, r/m */
761441b9 4884 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4885 break;
2a7c5b8b
GC		 4886 case 0xae: /* clflush */
4887 break;
6aa8b732 4888 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4889 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4890 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4891 : (u16) ctxt->src.val;
6aa8b732 4892 break;
6aa8b732 4893 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4894 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4895 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4896 (s16) ctxt->src.val;
6aa8b732 4897 break;
92f738a5 4898 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4899 emulate_2op_SrcV(ctxt, "add");
92f738a5 4900 /* Write back the register source. */
9dac77fa
AK		 4901 ctxt->src.val = ctxt->dst.orig_val;
4902 write_register_operand(&ctxt->src);
92f738a5 4903 break;
a012e65a 4904 case 0xc3: /* movnti */
9dac77fa
AK		 4905 ctxt->dst.bytes = ctxt->op_bytes;
4906 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4907 (u64) ctxt->src.val;
a012e65a 4908 break;
91269b8f
AK		 4909 default:
4910 goto cannot_emulate;
6aa8b732 4911 }
7d9ddaed
AK		 4912
4913 if (rc != X86EMUL_CONTINUE)
4914 goto done;
4915
6aa8b732
AK		 4916 goto writeback;
4917
4918cannot_emulate:
a0c0ab2f 4919 return EMULATION_FAILED;
6aa8b732 4920}
dd856efa
AK		 4921
4922void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4923{
4924 invalidate_registers(ctxt);
4925}
4926
4927void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4928{
4929 writeback_registers(ctxt);
4930}
Linux kernel - Deliverables
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