Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
221d059d | 12 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
23 | #ifndef __KERNEL__ | |
24 | #include <stdio.h> | |
25 | #include <stdint.h> | |
26 | #include <public/xen.h> | |
d77c26fc | 27 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 28 | #else |
edf88417 | 29 | #include <linux/kvm_host.h> |
5fdbf976 | 30 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
31 | #define DPRINTF(x...) do {} while (0) |
32 | #endif | |
6aa8b732 | 33 | #include <linux/module.h> |
56e82318 | 34 | #include <asm/kvm_emulate.h> |
6aa8b732 | 35 | |
3eeb3288 | 36 | #include "x86.h" |
38ba30ba | 37 | #include "tss.h" |
e99f0507 | 38 | |
6aa8b732 AK |
39 | /* |
40 | * Opcode effective-address decode tables. | |
41 | * Note that we only emulate instructions that have at least one memory | |
42 | * operand (excluding implicit stack references). We assume that stack | |
43 | * references and instruction fetches will never occur in special memory | |
44 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
45 | * not be handled. | |
46 | */ | |
47 | ||
48 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 49 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 50 | /* Destination operand type. */ |
ab85b12b AK |
51 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
52 | #define DstReg (2<<1) /* Register operand. */ | |
53 | #define DstMem (3<<1) /* Memory operand. */ | |
54 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
55 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
56 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 57 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 58 | #define DstMask (7<<1) |
6aa8b732 | 59 | /* Source operand type. */ |
9c9fddd0 GT |
60 | #define SrcNone (0<<4) /* No source operand. */ |
61 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
62 | #define SrcReg (1<<4) /* Register operand. */ | |
63 | #define SrcMem (2<<4) /* Memory operand. */ | |
64 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
65 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
66 | #define SrcImm (5<<4) /* Immediate operand. */ | |
67 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 68 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 69 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 70 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 71 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
72 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
73 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 74 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
341de7e3 | 75 | #define SrcMask (0xf<<4) |
6aa8b732 | 76 | /* Generic ModRM decode. */ |
341de7e3 | 77 | #define ModRM (1<<8) |
6aa8b732 | 78 | /* Destination is only written; never read. */ |
341de7e3 GN |
79 | #define Mov (1<<9) |
80 | #define BitOp (1<<10) | |
81 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
82 | #define String (1<<12) /* String instruction (rep capable) */ |
83 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
84 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
85 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
d8769fed | 86 | /* Misc flags */ |
5a506b12 | 87 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 88 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 89 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 90 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 91 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 92 | #define No64 (1<<28) |
0dc8d10f GT |
93 | /* Source 2 operand type */ |
94 | #define Src2None (0<<29) | |
95 | #define Src2CL (1<<29) | |
96 | #define Src2ImmByte (2<<29) | |
97 | #define Src2One (3<<29) | |
98 | #define Src2Mask (7<<29) | |
6aa8b732 | 99 | |
d0e53325 AK |
100 | #define X2(x...) x, x |
101 | #define X3(x...) X2(x), x | |
102 | #define X4(x...) X2(x), X2(x) | |
103 | #define X5(x...) X4(x), x | |
104 | #define X6(x...) X4(x), X2(x) | |
105 | #define X7(x...) X4(x), X3(x) | |
106 | #define X8(x...) X4(x), X4(x) | |
107 | #define X16(x...) X8(x), X8(x) | |
83babbca | 108 | |
d65b1dee AK |
109 | struct opcode { |
110 | u32 flags; | |
120df890 | 111 | union { |
ef65c889 | 112 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
113 | struct opcode *group; |
114 | struct group_dual *gdual; | |
115 | } u; | |
116 | }; | |
117 | ||
118 | struct group_dual { | |
119 | struct opcode mod012[8]; | |
120 | struct opcode mod3[8]; | |
d65b1dee AK |
121 | }; |
122 | ||
6aa8b732 | 123 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
124 | #define EFLG_ID (1<<21) |
125 | #define EFLG_VIP (1<<20) | |
126 | #define EFLG_VIF (1<<19) | |
127 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
128 | #define EFLG_VM (1<<17) |
129 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
130 | #define EFLG_IOPL (3<<12) |
131 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
132 | #define EFLG_OF (1<<11) |
133 | #define EFLG_DF (1<<10) | |
b1d86143 | 134 | #define EFLG_IF (1<<9) |
d4c6a154 | 135 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
136 | #define EFLG_SF (1<<7) |
137 | #define EFLG_ZF (1<<6) | |
138 | #define EFLG_AF (1<<4) | |
139 | #define EFLG_PF (1<<2) | |
140 | #define EFLG_CF (1<<0) | |
141 | ||
62bd430e MG |
142 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
143 | #define EFLG_RESERVED_ONE_MASK 2 | |
144 | ||
6aa8b732 AK |
145 | /* |
146 | * Instruction emulation: | |
147 | * Most instructions are emulated directly via a fragment of inline assembly | |
148 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
149 | * any modified flags. | |
150 | */ | |
151 | ||
05b3e0c2 | 152 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
153 | #define _LO32 "k" /* force 32-bit operand */ |
154 | #define _STK "%%rsp" /* stack pointer */ | |
155 | #elif defined(__i386__) | |
156 | #define _LO32 "" /* force 32-bit operand */ | |
157 | #define _STK "%%esp" /* stack pointer */ | |
158 | #endif | |
159 | ||
160 | /* | |
161 | * These EFLAGS bits are restored from saved value during emulation, and | |
162 | * any changes are written back to the saved value after emulation. | |
163 | */ | |
164 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
165 | ||
166 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
167 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
168 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
169 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
170 | "push %"_tmp"; " \ | |
171 | "push %"_tmp"; " \ | |
172 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
173 | "andl %"_LO32 _tmp",("_STK"); " \ | |
174 | "pushf; " \ | |
175 | "notl %"_LO32 _tmp"; " \ | |
176 | "andl %"_LO32 _tmp",("_STK"); " \ | |
177 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
178 | "pop %"_tmp"; " \ | |
179 | "orl %"_LO32 _tmp",("_STK"); " \ | |
180 | "popf; " \ | |
181 | "pop %"_sav"; " | |
6aa8b732 AK |
182 | |
183 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
184 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
185 | /* _sav |= EFLAGS & _msk; */ \ | |
186 | "pushf; " \ | |
187 | "pop %"_tmp"; " \ | |
188 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
189 | "orl %"_LO32 _tmp",%"_sav"; " | |
190 | ||
dda96d8f AK |
191 | #ifdef CONFIG_X86_64 |
192 | #define ON64(x) x | |
193 | #else | |
194 | #define ON64(x) | |
195 | #endif | |
196 | ||
b3b3d25a | 197 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
198 | do { \ |
199 | __asm__ __volatile__ ( \ | |
200 | _PRE_EFLAGS("0", "4", "2") \ | |
201 | _op _suffix " %"_x"3,%1; " \ | |
202 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 203 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
204 | "=&r" (_tmp) \ |
205 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 206 | } while (0) |
6b7ad61f AK |
207 | |
208 | ||
6aa8b732 AK |
209 | /* Raw emulation: instruction has two explicit operands. */ |
210 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
211 | do { \ |
212 | unsigned long _tmp; \ | |
213 | \ | |
214 | switch ((_dst).bytes) { \ | |
215 | case 2: \ | |
b3b3d25a | 216 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
217 | break; \ |
218 | case 4: \ | |
b3b3d25a | 219 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
220 | break; \ |
221 | case 8: \ | |
b3b3d25a | 222 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
223 | break; \ |
224 | } \ | |
6aa8b732 AK |
225 | } while (0) |
226 | ||
227 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
228 | do { \ | |
6b7ad61f | 229 | unsigned long _tmp; \ |
d77c26fc | 230 | switch ((_dst).bytes) { \ |
6aa8b732 | 231 | case 1: \ |
b3b3d25a | 232 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
233 | break; \ |
234 | default: \ | |
235 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
236 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
237 | break; \ | |
238 | } \ | |
239 | } while (0) | |
240 | ||
241 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
242 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
243 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
244 | "b", "c", "b", "c", "b", "c", "b", "c") | |
245 | ||
246 | /* Source operand is byte, word, long or quad sized. */ | |
247 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
248 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
249 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
250 | ||
251 | /* Source operand is word, long or quad sized. */ | |
252 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
253 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
254 | "w", "r", _LO32, "r", "", "r") | |
255 | ||
d175226a GT |
256 | /* Instruction has three operands and one operand is stored in ECX register */ |
257 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
258 | do { \ | |
259 | unsigned long _tmp; \ | |
260 | _type _clv = (_cl).val; \ | |
261 | _type _srcv = (_src).val; \ | |
262 | _type _dstv = (_dst).val; \ | |
263 | \ | |
264 | __asm__ __volatile__ ( \ | |
265 | _PRE_EFLAGS("0", "5", "2") \ | |
266 | _op _suffix " %4,%1 \n" \ | |
267 | _POST_EFLAGS("0", "5", "2") \ | |
268 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
269 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
270 | ); \ | |
271 | \ | |
272 | (_cl).val = (unsigned long) _clv; \ | |
273 | (_src).val = (unsigned long) _srcv; \ | |
274 | (_dst).val = (unsigned long) _dstv; \ | |
275 | } while (0) | |
276 | ||
277 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
278 | do { \ | |
279 | switch ((_dst).bytes) { \ | |
280 | case 2: \ | |
281 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
282 | "w", unsigned short); \ | |
283 | break; \ | |
284 | case 4: \ | |
285 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
286 | "l", unsigned int); \ | |
287 | break; \ | |
288 | case 8: \ | |
289 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
290 | "q", unsigned long)); \ | |
291 | break; \ | |
292 | } \ | |
293 | } while (0) | |
294 | ||
dda96d8f | 295 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
296 | do { \ |
297 | unsigned long _tmp; \ | |
298 | \ | |
dda96d8f AK |
299 | __asm__ __volatile__ ( \ |
300 | _PRE_EFLAGS("0", "3", "2") \ | |
301 | _op _suffix " %1; " \ | |
302 | _POST_EFLAGS("0", "3", "2") \ | |
303 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
304 | "=&r" (_tmp) \ | |
305 | : "i" (EFLAGS_MASK)); \ | |
306 | } while (0) | |
307 | ||
308 | /* Instruction has only one explicit operand (no source operand). */ | |
309 | #define emulate_1op(_op, _dst, _eflags) \ | |
310 | do { \ | |
d77c26fc | 311 | switch ((_dst).bytes) { \ |
dda96d8f AK |
312 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
313 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
314 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
315 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
316 | } \ |
317 | } while (0) | |
318 | ||
3f9f53b0 MG |
319 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
320 | do { \ | |
321 | unsigned long _tmp; \ | |
322 | \ | |
323 | __asm__ __volatile__ ( \ | |
324 | _PRE_EFLAGS("0", "4", "1") \ | |
325 | _op _suffix " %5; " \ | |
326 | _POST_EFLAGS("0", "4", "1") \ | |
327 | : "=m" (_eflags), "=&r" (_tmp), \ | |
328 | "+a" (_rax), "+d" (_rdx) \ | |
329 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
330 | "a" (_rax), "d" (_rdx)); \ | |
331 | } while (0) | |
332 | ||
333 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ | |
334 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
335 | do { \ | |
336 | switch((_src).bytes) { \ | |
337 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
338 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
339 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
340 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
341 | } \ | |
342 | } while (0) | |
343 | ||
6aa8b732 AK |
344 | /* Fetch next part of the instruction being emulated. */ |
345 | #define insn_fetch(_type, _size, _eip) \ | |
346 | ({ unsigned long _x; \ | |
62266869 | 347 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 348 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
349 | goto done; \ |
350 | (_eip) += (_size); \ | |
351 | (_type)_x; \ | |
352 | }) | |
353 | ||
414e6277 GN |
354 | #define insn_fetch_arr(_arr, _size, _eip) \ |
355 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
356 | if (rc != X86EMUL_CONTINUE) \ | |
357 | goto done; \ | |
358 | (_eip) += (_size); \ | |
359 | }) | |
360 | ||
ddcb2885 HH |
361 | static inline unsigned long ad_mask(struct decode_cache *c) |
362 | { | |
363 | return (1UL << (c->ad_bytes << 3)) - 1; | |
364 | } | |
365 | ||
6aa8b732 | 366 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
367 | static inline unsigned long |
368 | address_mask(struct decode_cache *c, unsigned long reg) | |
369 | { | |
370 | if (c->ad_bytes == sizeof(unsigned long)) | |
371 | return reg; | |
372 | else | |
373 | return reg & ad_mask(c); | |
374 | } | |
375 | ||
376 | static inline unsigned long | |
377 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
378 | { | |
379 | return base + address_mask(c, reg); | |
380 | } | |
381 | ||
7a957275 HH |
382 | static inline void |
383 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
384 | { | |
385 | if (c->ad_bytes == sizeof(unsigned long)) | |
386 | *reg += inc; | |
387 | else | |
388 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
389 | } | |
6aa8b732 | 390 | |
7a957275 HH |
391 | static inline void jmp_rel(struct decode_cache *c, int rel) |
392 | { | |
393 | register_address_increment(c, &c->eip, rel); | |
394 | } | |
098c937b | 395 | |
7a5b56df AK |
396 | static void set_seg_override(struct decode_cache *c, int seg) |
397 | { | |
398 | c->has_seg_override = true; | |
399 | c->seg_override = seg; | |
400 | } | |
401 | ||
79168fd1 GN |
402 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
403 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
404 | { |
405 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
406 | return 0; | |
407 | ||
79168fd1 | 408 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
409 | } |
410 | ||
411 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 412 | struct x86_emulate_ops *ops, |
7a5b56df AK |
413 | struct decode_cache *c) |
414 | { | |
415 | if (!c->has_seg_override) | |
416 | return 0; | |
417 | ||
79168fd1 | 418 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
419 | } |
420 | ||
79168fd1 GN |
421 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
422 | struct x86_emulate_ops *ops) | |
7a5b56df | 423 | { |
79168fd1 | 424 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
425 | } |
426 | ||
79168fd1 GN |
427 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
428 | struct x86_emulate_ops *ops) | |
7a5b56df | 429 | { |
79168fd1 | 430 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
431 | } |
432 | ||
54b8486f GN |
433 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
434 | u32 error, bool valid) | |
435 | { | |
436 | ctxt->exception = vec; | |
437 | ctxt->error_code = error; | |
438 | ctxt->error_code_valid = valid; | |
439 | ctxt->restart = false; | |
440 | } | |
441 | ||
442 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
443 | { | |
444 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
445 | } | |
446 | ||
447 | static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
448 | int err) | |
449 | { | |
450 | ctxt->cr2 = addr; | |
451 | emulate_exception(ctxt, PF_VECTOR, err, true); | |
452 | } | |
453 | ||
454 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
455 | { | |
456 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
457 | } | |
458 | ||
459 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
460 | { | |
461 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
462 | } | |
463 | ||
62266869 AK |
464 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
465 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 466 | unsigned long eip, u8 *dest) |
62266869 AK |
467 | { |
468 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
469 | int rc; | |
2fb53ad8 | 470 | int size, cur_size; |
62266869 | 471 | |
2fb53ad8 AK |
472 | if (eip == fc->end) { |
473 | cur_size = fc->end - fc->start; | |
474 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
475 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
476 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 477 | if (rc != X86EMUL_CONTINUE) |
62266869 | 478 | return rc; |
2fb53ad8 | 479 | fc->end += size; |
62266869 | 480 | } |
2fb53ad8 | 481 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 482 | return X86EMUL_CONTINUE; |
62266869 AK |
483 | } |
484 | ||
485 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
486 | struct x86_emulate_ops *ops, | |
487 | unsigned long eip, void *dest, unsigned size) | |
488 | { | |
3e2815e9 | 489 | int rc; |
62266869 | 490 | |
eb3c79e6 | 491 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 492 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 493 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
494 | while (size--) { |
495 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 496 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
497 | return rc; |
498 | } | |
3e2815e9 | 499 | return X86EMUL_CONTINUE; |
62266869 AK |
500 | } |
501 | ||
1e3c5cb0 RR |
502 | /* |
503 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
504 | * pointer into the block that addresses the relevant register. | |
505 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
506 | */ | |
507 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
508 | int highbyte_regs) | |
6aa8b732 AK |
509 | { |
510 | void *p; | |
511 | ||
512 | p = ®s[modrm_reg]; | |
513 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
514 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
515 | return p; | |
516 | } | |
517 | ||
518 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
519 | struct x86_emulate_ops *ops, | |
1a6440ae | 520 | ulong addr, |
6aa8b732 AK |
521 | u16 *size, unsigned long *address, int op_bytes) |
522 | { | |
523 | int rc; | |
524 | ||
525 | if (op_bytes == 2) | |
526 | op_bytes = 3; | |
527 | *address = 0; | |
1a6440ae | 528 | rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL); |
1b30eaa8 | 529 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 530 | return rc; |
1a6440ae | 531 | rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL); |
6aa8b732 AK |
532 | return rc; |
533 | } | |
534 | ||
bbe9abbd NK |
535 | static int test_cc(unsigned int condition, unsigned int flags) |
536 | { | |
537 | int rc = 0; | |
538 | ||
539 | switch ((condition & 15) >> 1) { | |
540 | case 0: /* o */ | |
541 | rc |= (flags & EFLG_OF); | |
542 | break; | |
543 | case 1: /* b/c/nae */ | |
544 | rc |= (flags & EFLG_CF); | |
545 | break; | |
546 | case 2: /* z/e */ | |
547 | rc |= (flags & EFLG_ZF); | |
548 | break; | |
549 | case 3: /* be/na */ | |
550 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
551 | break; | |
552 | case 4: /* s */ | |
553 | rc |= (flags & EFLG_SF); | |
554 | break; | |
555 | case 5: /* p/pe */ | |
556 | rc |= (flags & EFLG_PF); | |
557 | break; | |
558 | case 7: /* le/ng */ | |
559 | rc |= (flags & EFLG_ZF); | |
560 | /* fall through */ | |
561 | case 6: /* l/nge */ | |
562 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
563 | break; | |
564 | } | |
565 | ||
566 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
567 | return (!!rc ^ (condition & 1)); | |
568 | } | |
569 | ||
91ff3cb4 AK |
570 | static void fetch_register_operand(struct operand *op) |
571 | { | |
572 | switch (op->bytes) { | |
573 | case 1: | |
574 | op->val = *(u8 *)op->addr.reg; | |
575 | break; | |
576 | case 2: | |
577 | op->val = *(u16 *)op->addr.reg; | |
578 | break; | |
579 | case 4: | |
580 | op->val = *(u32 *)op->addr.reg; | |
581 | break; | |
582 | case 8: | |
583 | op->val = *(u64 *)op->addr.reg; | |
584 | break; | |
585 | } | |
586 | } | |
587 | ||
3c118e24 AK |
588 | static void decode_register_operand(struct operand *op, |
589 | struct decode_cache *c, | |
3c118e24 AK |
590 | int inhibit_bytereg) |
591 | { | |
33615aa9 | 592 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 593 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
594 | |
595 | if (!(c->d & ModRM)) | |
596 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
597 | op->type = OP_REG; |
598 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 599 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
600 | op->bytes = 1; |
601 | } else { | |
1a6440ae | 602 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 603 | op->bytes = c->op_bytes; |
3c118e24 | 604 | } |
91ff3cb4 | 605 | fetch_register_operand(op); |
3c118e24 AK |
606 | op->orig_val = op->val; |
607 | } | |
608 | ||
1c73ef66 | 609 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
610 | struct x86_emulate_ops *ops, |
611 | struct operand *op) | |
1c73ef66 AK |
612 | { |
613 | struct decode_cache *c = &ctxt->decode; | |
614 | u8 sib; | |
f5b4edcd | 615 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 616 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 617 | ulong modrm_ea = 0; |
1c73ef66 AK |
618 | |
619 | if (c->rex_prefix) { | |
620 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
621 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
622 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
623 | } | |
624 | ||
625 | c->modrm = insn_fetch(u8, 1, c->eip); | |
626 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
627 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
628 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 629 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
630 | |
631 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
632 | op->type = OP_REG; |
633 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
634 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 635 | c->regs, c->d & ByteOp); |
2dbd0dd7 | 636 | fetch_register_operand(op); |
1c73ef66 AK |
637 | return rc; |
638 | } | |
639 | ||
2dbd0dd7 AK |
640 | op->type = OP_MEM; |
641 | ||
1c73ef66 AK |
642 | if (c->ad_bytes == 2) { |
643 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
644 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
645 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
646 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
647 | ||
648 | /* 16-bit ModR/M decode. */ | |
649 | switch (c->modrm_mod) { | |
650 | case 0: | |
651 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 652 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
653 | break; |
654 | case 1: | |
2dbd0dd7 | 655 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
656 | break; |
657 | case 2: | |
2dbd0dd7 | 658 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
659 | break; |
660 | } | |
661 | switch (c->modrm_rm) { | |
662 | case 0: | |
2dbd0dd7 | 663 | modrm_ea += bx + si; |
1c73ef66 AK |
664 | break; |
665 | case 1: | |
2dbd0dd7 | 666 | modrm_ea += bx + di; |
1c73ef66 AK |
667 | break; |
668 | case 2: | |
2dbd0dd7 | 669 | modrm_ea += bp + si; |
1c73ef66 AK |
670 | break; |
671 | case 3: | |
2dbd0dd7 | 672 | modrm_ea += bp + di; |
1c73ef66 AK |
673 | break; |
674 | case 4: | |
2dbd0dd7 | 675 | modrm_ea += si; |
1c73ef66 AK |
676 | break; |
677 | case 5: | |
2dbd0dd7 | 678 | modrm_ea += di; |
1c73ef66 AK |
679 | break; |
680 | case 6: | |
681 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 682 | modrm_ea += bp; |
1c73ef66 AK |
683 | break; |
684 | case 7: | |
2dbd0dd7 | 685 | modrm_ea += bx; |
1c73ef66 AK |
686 | break; |
687 | } | |
688 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
689 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 690 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 691 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
692 | } else { |
693 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 694 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
695 | sib = insn_fetch(u8, 1, c->eip); |
696 | index_reg |= (sib >> 3) & 7; | |
697 | base_reg |= sib & 7; | |
698 | scale = sib >> 6; | |
699 | ||
dc71d0f1 | 700 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 701 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 702 | else |
2dbd0dd7 | 703 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 704 | if (index_reg != 4) |
2dbd0dd7 | 705 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
706 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
707 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 708 | c->rip_relative = 1; |
84411d85 | 709 | } else |
2dbd0dd7 | 710 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
711 | switch (c->modrm_mod) { |
712 | case 0: | |
713 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 714 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
715 | break; |
716 | case 1: | |
2dbd0dd7 | 717 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
718 | break; |
719 | case 2: | |
2dbd0dd7 | 720 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
721 | break; |
722 | } | |
723 | } | |
2dbd0dd7 | 724 | op->addr.mem = modrm_ea; |
1c73ef66 AK |
725 | done: |
726 | return rc; | |
727 | } | |
728 | ||
729 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
730 | struct x86_emulate_ops *ops, |
731 | struct operand *op) | |
1c73ef66 AK |
732 | { |
733 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 734 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 735 | |
2dbd0dd7 | 736 | op->type = OP_MEM; |
1c73ef66 AK |
737 | switch (c->ad_bytes) { |
738 | case 2: | |
2dbd0dd7 | 739 | op->addr.mem = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
740 | break; |
741 | case 4: | |
2dbd0dd7 | 742 | op->addr.mem = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
743 | break; |
744 | case 8: | |
2dbd0dd7 | 745 | op->addr.mem = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
746 | break; |
747 | } | |
748 | done: | |
749 | return rc; | |
750 | } | |
751 | ||
35c843c4 WY |
752 | static void fetch_bit_operand(struct decode_cache *c) |
753 | { | |
754 | long sv, mask; | |
755 | ||
3885f18f | 756 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
757 | mask = ~(c->dst.bytes * 8 - 1); |
758 | ||
759 | if (c->src.bytes == 2) | |
760 | sv = (s16)c->src.val & (s16)mask; | |
761 | else if (c->src.bytes == 4) | |
762 | sv = (s32)c->src.val & (s32)mask; | |
763 | ||
764 | c->dst.addr.mem += (sv >> 3); | |
765 | } | |
ba7ff2b7 WY |
766 | |
767 | /* only subword offset */ | |
768 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
769 | } |
770 | ||
dde7e6d1 AK |
771 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
772 | struct x86_emulate_ops *ops, | |
773 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 774 | { |
dde7e6d1 AK |
775 | int rc; |
776 | struct read_cache *mc = &ctxt->decode.mem_read; | |
777 | u32 err; | |
6aa8b732 | 778 | |
dde7e6d1 AK |
779 | while (size) { |
780 | int n = min(size, 8u); | |
781 | size -= n; | |
782 | if (mc->pos < mc->end) | |
783 | goto read_cached; | |
5cd21917 | 784 | |
dde7e6d1 AK |
785 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
786 | ctxt->vcpu); | |
787 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
788 | emulate_pf(ctxt, addr, err); | |
789 | if (rc != X86EMUL_CONTINUE) | |
790 | return rc; | |
791 | mc->end += n; | |
6aa8b732 | 792 | |
dde7e6d1 AK |
793 | read_cached: |
794 | memcpy(dest, mc->data + mc->pos, n); | |
795 | mc->pos += n; | |
796 | dest += n; | |
797 | addr += n; | |
6aa8b732 | 798 | } |
dde7e6d1 AK |
799 | return X86EMUL_CONTINUE; |
800 | } | |
6aa8b732 | 801 | |
dde7e6d1 AK |
802 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
803 | struct x86_emulate_ops *ops, | |
804 | unsigned int size, unsigned short port, | |
805 | void *dest) | |
806 | { | |
807 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 808 | |
dde7e6d1 AK |
809 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
810 | struct decode_cache *c = &ctxt->decode; | |
811 | unsigned int in_page, n; | |
812 | unsigned int count = c->rep_prefix ? | |
813 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
814 | in_page = (ctxt->eflags & EFLG_DF) ? | |
815 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
816 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
817 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
818 | count); | |
819 | if (n == 0) | |
820 | n = 1; | |
821 | rc->pos = rc->end = 0; | |
822 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
823 | return 0; | |
824 | rc->end = n * size; | |
6aa8b732 AK |
825 | } |
826 | ||
dde7e6d1 AK |
827 | memcpy(dest, rc->data + rc->pos, size); |
828 | rc->pos += size; | |
829 | return 1; | |
830 | } | |
6aa8b732 | 831 | |
dde7e6d1 AK |
832 | static u32 desc_limit_scaled(struct desc_struct *desc) |
833 | { | |
834 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 835 | |
dde7e6d1 AK |
836 | return desc->g ? (limit << 12) | 0xfff : limit; |
837 | } | |
6aa8b732 | 838 | |
dde7e6d1 AK |
839 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
840 | struct x86_emulate_ops *ops, | |
841 | u16 selector, struct desc_ptr *dt) | |
842 | { | |
843 | if (selector & 1 << 2) { | |
844 | struct desc_struct desc; | |
845 | memset (dt, 0, sizeof *dt); | |
846 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
847 | return; | |
e09d082c | 848 | |
dde7e6d1 AK |
849 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
850 | dt->address = get_desc_base(&desc); | |
851 | } else | |
852 | ops->get_gdt(dt, ctxt->vcpu); | |
853 | } | |
120df890 | 854 | |
dde7e6d1 AK |
855 | /* allowed just for 8 bytes segments */ |
856 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
857 | struct x86_emulate_ops *ops, | |
858 | u16 selector, struct desc_struct *desc) | |
859 | { | |
860 | struct desc_ptr dt; | |
861 | u16 index = selector >> 3; | |
862 | int ret; | |
863 | u32 err; | |
864 | ulong addr; | |
120df890 | 865 | |
dde7e6d1 | 866 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 867 | |
dde7e6d1 AK |
868 | if (dt.size < index * 8 + 7) { |
869 | emulate_gp(ctxt, selector & 0xfffc); | |
870 | return X86EMUL_PROPAGATE_FAULT; | |
e09d082c | 871 | } |
dde7e6d1 AK |
872 | addr = dt.address + index * 8; |
873 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
874 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
875 | emulate_pf(ctxt, addr, err); | |
e09d082c | 876 | |
dde7e6d1 AK |
877 | return ret; |
878 | } | |
ef65c889 | 879 | |
dde7e6d1 AK |
880 | /* allowed just for 8 bytes segments */ |
881 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
882 | struct x86_emulate_ops *ops, | |
883 | u16 selector, struct desc_struct *desc) | |
884 | { | |
885 | struct desc_ptr dt; | |
886 | u16 index = selector >> 3; | |
887 | u32 err; | |
888 | ulong addr; | |
889 | int ret; | |
6aa8b732 | 890 | |
dde7e6d1 | 891 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 892 | |
dde7e6d1 AK |
893 | if (dt.size < index * 8 + 7) { |
894 | emulate_gp(ctxt, selector & 0xfffc); | |
895 | return X86EMUL_PROPAGATE_FAULT; | |
896 | } | |
6aa8b732 | 897 | |
dde7e6d1 AK |
898 | addr = dt.address + index * 8; |
899 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
900 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
901 | emulate_pf(ctxt, addr, err); | |
c7e75a3d | 902 | |
dde7e6d1 AK |
903 | return ret; |
904 | } | |
c7e75a3d | 905 | |
dde7e6d1 AK |
906 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
907 | struct x86_emulate_ops *ops, | |
908 | u16 selector, int seg) | |
909 | { | |
910 | struct desc_struct seg_desc; | |
911 | u8 dpl, rpl, cpl; | |
912 | unsigned err_vec = GP_VECTOR; | |
913 | u32 err_code = 0; | |
914 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
915 | int ret; | |
69f55cb1 | 916 | |
dde7e6d1 | 917 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 918 | |
dde7e6d1 AK |
919 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
920 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
921 | /* set real mode segment descriptor */ | |
922 | set_desc_base(&seg_desc, selector << 4); | |
923 | set_desc_limit(&seg_desc, 0xffff); | |
924 | seg_desc.type = 3; | |
925 | seg_desc.p = 1; | |
926 | seg_desc.s = 1; | |
927 | goto load; | |
928 | } | |
929 | ||
930 | /* NULL selector is not valid for TR, CS and SS */ | |
931 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
932 | && null_selector) | |
933 | goto exception; | |
934 | ||
935 | /* TR should be in GDT only */ | |
936 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
937 | goto exception; | |
938 | ||
939 | if (null_selector) /* for NULL selector skip all following checks */ | |
940 | goto load; | |
941 | ||
942 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
943 | if (ret != X86EMUL_CONTINUE) | |
944 | return ret; | |
945 | ||
946 | err_code = selector & 0xfffc; | |
947 | err_vec = GP_VECTOR; | |
948 | ||
949 | /* can't load system descriptor into segment selecor */ | |
950 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
951 | goto exception; | |
952 | ||
953 | if (!seg_desc.p) { | |
954 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
955 | goto exception; | |
956 | } | |
957 | ||
958 | rpl = selector & 3; | |
959 | dpl = seg_desc.dpl; | |
960 | cpl = ops->cpl(ctxt->vcpu); | |
961 | ||
962 | switch (seg) { | |
963 | case VCPU_SREG_SS: | |
964 | /* | |
965 | * segment is not a writable data segment or segment | |
966 | * selector's RPL != CPL or segment selector's RPL != CPL | |
967 | */ | |
968 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
969 | goto exception; | |
6aa8b732 | 970 | break; |
dde7e6d1 AK |
971 | case VCPU_SREG_CS: |
972 | if (!(seg_desc.type & 8)) | |
973 | goto exception; | |
974 | ||
975 | if (seg_desc.type & 4) { | |
976 | /* conforming */ | |
977 | if (dpl > cpl) | |
978 | goto exception; | |
979 | } else { | |
980 | /* nonconforming */ | |
981 | if (rpl > cpl || dpl != cpl) | |
982 | goto exception; | |
983 | } | |
984 | /* CS(RPL) <- CPL */ | |
985 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 986 | break; |
dde7e6d1 AK |
987 | case VCPU_SREG_TR: |
988 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
989 | goto exception; | |
990 | break; | |
991 | case VCPU_SREG_LDTR: | |
992 | if (seg_desc.s || seg_desc.type != 2) | |
993 | goto exception; | |
994 | break; | |
995 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 996 | /* |
dde7e6d1 AK |
997 | * segment is not a data or readable code segment or |
998 | * ((segment is a data or nonconforming code segment) | |
999 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1000 | */ |
dde7e6d1 AK |
1001 | if ((seg_desc.type & 0xa) == 0x8 || |
1002 | (((seg_desc.type & 0xc) != 0xc) && | |
1003 | (rpl > dpl && cpl > dpl))) | |
1004 | goto exception; | |
6aa8b732 | 1005 | break; |
dde7e6d1 AK |
1006 | } |
1007 | ||
1008 | if (seg_desc.s) { | |
1009 | /* mark segment as accessed */ | |
1010 | seg_desc.type |= 1; | |
1011 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1012 | if (ret != X86EMUL_CONTINUE) | |
1013 | return ret; | |
1014 | } | |
1015 | load: | |
1016 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1017 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1018 | return X86EMUL_CONTINUE; | |
1019 | exception: | |
1020 | emulate_exception(ctxt, err_vec, err_code, true); | |
1021 | return X86EMUL_PROPAGATE_FAULT; | |
1022 | } | |
1023 | ||
31be40b3 WY |
1024 | static void write_register_operand(struct operand *op) |
1025 | { | |
1026 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1027 | switch (op->bytes) { | |
1028 | case 1: | |
1029 | *(u8 *)op->addr.reg = (u8)op->val; | |
1030 | break; | |
1031 | case 2: | |
1032 | *(u16 *)op->addr.reg = (u16)op->val; | |
1033 | break; | |
1034 | case 4: | |
1035 | *op->addr.reg = (u32)op->val; | |
1036 | break; /* 64b: zero-extend */ | |
1037 | case 8: | |
1038 | *op->addr.reg = op->val; | |
1039 | break; | |
1040 | } | |
1041 | } | |
1042 | ||
dde7e6d1 AK |
1043 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1044 | struct x86_emulate_ops *ops) | |
1045 | { | |
1046 | int rc; | |
1047 | struct decode_cache *c = &ctxt->decode; | |
1048 | u32 err; | |
1049 | ||
1050 | switch (c->dst.type) { | |
1051 | case OP_REG: | |
31be40b3 | 1052 | write_register_operand(&c->dst); |
6aa8b732 | 1053 | break; |
dde7e6d1 AK |
1054 | case OP_MEM: |
1055 | if (c->lock_prefix) | |
1056 | rc = ops->cmpxchg_emulated( | |
1a6440ae | 1057 | c->dst.addr.mem, |
dde7e6d1 AK |
1058 | &c->dst.orig_val, |
1059 | &c->dst.val, | |
1060 | c->dst.bytes, | |
1061 | &err, | |
1062 | ctxt->vcpu); | |
341de7e3 | 1063 | else |
dde7e6d1 | 1064 | rc = ops->write_emulated( |
1a6440ae | 1065 | c->dst.addr.mem, |
dde7e6d1 AK |
1066 | &c->dst.val, |
1067 | c->dst.bytes, | |
1068 | &err, | |
1069 | ctxt->vcpu); | |
1070 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1a6440ae | 1071 | emulate_pf(ctxt, c->dst.addr.mem, err); |
dde7e6d1 AK |
1072 | if (rc != X86EMUL_CONTINUE) |
1073 | return rc; | |
a682e354 | 1074 | break; |
dde7e6d1 AK |
1075 | case OP_NONE: |
1076 | /* no writeback */ | |
414e6277 | 1077 | break; |
dde7e6d1 | 1078 | default: |
414e6277 | 1079 | break; |
6aa8b732 | 1080 | } |
dde7e6d1 AK |
1081 | return X86EMUL_CONTINUE; |
1082 | } | |
6aa8b732 | 1083 | |
dde7e6d1 AK |
1084 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1085 | struct x86_emulate_ops *ops) | |
1086 | { | |
1087 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1088 | |
dde7e6d1 AK |
1089 | c->dst.type = OP_MEM; |
1090 | c->dst.bytes = c->op_bytes; | |
1091 | c->dst.val = c->src.val; | |
1092 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
1a6440ae AK |
1093 | c->dst.addr.mem = register_address(c, ss_base(ctxt, ops), |
1094 | c->regs[VCPU_REGS_RSP]); | |
dde7e6d1 | 1095 | } |
69f55cb1 | 1096 | |
dde7e6d1 AK |
1097 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1098 | struct x86_emulate_ops *ops, | |
1099 | void *dest, int len) | |
1100 | { | |
1101 | struct decode_cache *c = &ctxt->decode; | |
1102 | int rc; | |
8b4caf66 | 1103 | |
dde7e6d1 AK |
1104 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
1105 | c->regs[VCPU_REGS_RSP]), | |
1106 | dest, len); | |
1107 | if (rc != X86EMUL_CONTINUE) | |
1108 | return rc; | |
1109 | ||
1110 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1111 | return rc; | |
8b4caf66 LV |
1112 | } |
1113 | ||
dde7e6d1 AK |
1114 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1115 | struct x86_emulate_ops *ops, | |
1116 | void *dest, int len) | |
9de41573 GN |
1117 | { |
1118 | int rc; | |
dde7e6d1 AK |
1119 | unsigned long val, change_mask; |
1120 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1121 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1122 | |
dde7e6d1 AK |
1123 | rc = emulate_pop(ctxt, ops, &val, len); |
1124 | if (rc != X86EMUL_CONTINUE) | |
1125 | return rc; | |
9de41573 | 1126 | |
dde7e6d1 AK |
1127 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1128 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1129 | |
dde7e6d1 AK |
1130 | switch(ctxt->mode) { |
1131 | case X86EMUL_MODE_PROT64: | |
1132 | case X86EMUL_MODE_PROT32: | |
1133 | case X86EMUL_MODE_PROT16: | |
1134 | if (cpl == 0) | |
1135 | change_mask |= EFLG_IOPL; | |
1136 | if (cpl <= iopl) | |
1137 | change_mask |= EFLG_IF; | |
1138 | break; | |
1139 | case X86EMUL_MODE_VM86: | |
1140 | if (iopl < 3) { | |
1141 | emulate_gp(ctxt, 0); | |
1142 | return X86EMUL_PROPAGATE_FAULT; | |
1143 | } | |
1144 | change_mask |= EFLG_IF; | |
1145 | break; | |
1146 | default: /* real mode */ | |
1147 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1148 | break; | |
9de41573 | 1149 | } |
dde7e6d1 AK |
1150 | |
1151 | *(unsigned long *)dest = | |
1152 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1153 | ||
1154 | return rc; | |
9de41573 GN |
1155 | } |
1156 | ||
dde7e6d1 AK |
1157 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1158 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1159 | { |
dde7e6d1 | 1160 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1161 | |
dde7e6d1 | 1162 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1163 | |
dde7e6d1 | 1164 | emulate_push(ctxt, ops); |
7b262e90 GN |
1165 | } |
1166 | ||
dde7e6d1 AK |
1167 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1168 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1169 | { |
dde7e6d1 AK |
1170 | struct decode_cache *c = &ctxt->decode; |
1171 | unsigned long selector; | |
1172 | int rc; | |
38ba30ba | 1173 | |
dde7e6d1 AK |
1174 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1175 | if (rc != X86EMUL_CONTINUE) | |
1176 | return rc; | |
1177 | ||
1178 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1179 | return rc; | |
38ba30ba GN |
1180 | } |
1181 | ||
dde7e6d1 AK |
1182 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1183 | struct x86_emulate_ops *ops) | |
38ba30ba | 1184 | { |
dde7e6d1 AK |
1185 | struct decode_cache *c = &ctxt->decode; |
1186 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1187 | int rc = X86EMUL_CONTINUE; | |
1188 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1189 | |
dde7e6d1 AK |
1190 | while (reg <= VCPU_REGS_RDI) { |
1191 | (reg == VCPU_REGS_RSP) ? | |
1192 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1193 | |
dde7e6d1 | 1194 | emulate_push(ctxt, ops); |
38ba30ba | 1195 | |
dde7e6d1 AK |
1196 | rc = writeback(ctxt, ops); |
1197 | if (rc != X86EMUL_CONTINUE) | |
1198 | return rc; | |
38ba30ba | 1199 | |
dde7e6d1 | 1200 | ++reg; |
38ba30ba | 1201 | } |
38ba30ba | 1202 | |
dde7e6d1 AK |
1203 | /* Disable writeback. */ |
1204 | c->dst.type = OP_NONE; | |
1205 | ||
1206 | return rc; | |
38ba30ba GN |
1207 | } |
1208 | ||
dde7e6d1 AK |
1209 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1210 | struct x86_emulate_ops *ops) | |
38ba30ba | 1211 | { |
dde7e6d1 AK |
1212 | struct decode_cache *c = &ctxt->decode; |
1213 | int rc = X86EMUL_CONTINUE; | |
1214 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1215 | |
dde7e6d1 AK |
1216 | while (reg >= VCPU_REGS_RAX) { |
1217 | if (reg == VCPU_REGS_RSP) { | |
1218 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1219 | c->op_bytes); | |
1220 | --reg; | |
1221 | } | |
38ba30ba | 1222 | |
dde7e6d1 AK |
1223 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1224 | if (rc != X86EMUL_CONTINUE) | |
1225 | break; | |
1226 | --reg; | |
38ba30ba | 1227 | } |
dde7e6d1 | 1228 | return rc; |
38ba30ba GN |
1229 | } |
1230 | ||
6e154e56 MG |
1231 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1232 | struct x86_emulate_ops *ops, int irq) | |
1233 | { | |
1234 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1235 | int rc; |
6e154e56 MG |
1236 | struct desc_ptr dt; |
1237 | gva_t cs_addr; | |
1238 | gva_t eip_addr; | |
1239 | u16 cs, eip; | |
1240 | u32 err; | |
1241 | ||
1242 | /* TODO: Add limit checks */ | |
1243 | c->src.val = ctxt->eflags; | |
1244 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1245 | rc = writeback(ctxt, ops); |
1246 | if (rc != X86EMUL_CONTINUE) | |
1247 | return rc; | |
6e154e56 MG |
1248 | |
1249 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1250 | ||
1251 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1252 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1253 | rc = writeback(ctxt, ops); |
1254 | if (rc != X86EMUL_CONTINUE) | |
1255 | return rc; | |
6e154e56 MG |
1256 | |
1257 | c->src.val = c->eip; | |
1258 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1259 | rc = writeback(ctxt, ops); |
1260 | if (rc != X86EMUL_CONTINUE) | |
1261 | return rc; | |
1262 | ||
1263 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1264 | |
1265 | ops->get_idt(&dt, ctxt->vcpu); | |
1266 | ||
1267 | eip_addr = dt.address + (irq << 2); | |
1268 | cs_addr = dt.address + (irq << 2) + 2; | |
1269 | ||
1270 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err); | |
1271 | if (rc != X86EMUL_CONTINUE) | |
1272 | return rc; | |
1273 | ||
1274 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err); | |
1275 | if (rc != X86EMUL_CONTINUE) | |
1276 | return rc; | |
1277 | ||
1278 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1279 | if (rc != X86EMUL_CONTINUE) | |
1280 | return rc; | |
1281 | ||
1282 | c->eip = eip; | |
1283 | ||
1284 | return rc; | |
1285 | } | |
1286 | ||
1287 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1288 | struct x86_emulate_ops *ops, int irq) | |
1289 | { | |
1290 | switch(ctxt->mode) { | |
1291 | case X86EMUL_MODE_REAL: | |
1292 | return emulate_int_real(ctxt, ops, irq); | |
1293 | case X86EMUL_MODE_VM86: | |
1294 | case X86EMUL_MODE_PROT16: | |
1295 | case X86EMUL_MODE_PROT32: | |
1296 | case X86EMUL_MODE_PROT64: | |
1297 | default: | |
1298 | /* Protected mode interrupts unimplemented yet */ | |
1299 | return X86EMUL_UNHANDLEABLE; | |
1300 | } | |
1301 | } | |
1302 | ||
dde7e6d1 AK |
1303 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1304 | struct x86_emulate_ops *ops) | |
38ba30ba | 1305 | { |
dde7e6d1 AK |
1306 | struct decode_cache *c = &ctxt->decode; |
1307 | int rc = X86EMUL_CONTINUE; | |
1308 | unsigned long temp_eip = 0; | |
1309 | unsigned long temp_eflags = 0; | |
1310 | unsigned long cs = 0; | |
1311 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1312 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1313 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1314 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1315 | |
dde7e6d1 | 1316 | /* TODO: Add stack limit check */ |
38ba30ba | 1317 | |
dde7e6d1 | 1318 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1319 | |
dde7e6d1 AK |
1320 | if (rc != X86EMUL_CONTINUE) |
1321 | return rc; | |
38ba30ba | 1322 | |
dde7e6d1 AK |
1323 | if (temp_eip & ~0xffff) { |
1324 | emulate_gp(ctxt, 0); | |
1325 | return X86EMUL_PROPAGATE_FAULT; | |
1326 | } | |
38ba30ba | 1327 | |
dde7e6d1 | 1328 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1329 | |
dde7e6d1 AK |
1330 | if (rc != X86EMUL_CONTINUE) |
1331 | return rc; | |
38ba30ba | 1332 | |
dde7e6d1 | 1333 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1334 | |
dde7e6d1 AK |
1335 | if (rc != X86EMUL_CONTINUE) |
1336 | return rc; | |
38ba30ba | 1337 | |
dde7e6d1 | 1338 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1339 | |
dde7e6d1 AK |
1340 | if (rc != X86EMUL_CONTINUE) |
1341 | return rc; | |
38ba30ba | 1342 | |
dde7e6d1 | 1343 | c->eip = temp_eip; |
38ba30ba | 1344 | |
38ba30ba | 1345 | |
dde7e6d1 AK |
1346 | if (c->op_bytes == 4) |
1347 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1348 | else if (c->op_bytes == 2) { | |
1349 | ctxt->eflags &= ~0xffff; | |
1350 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1351 | } |
dde7e6d1 AK |
1352 | |
1353 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1354 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1355 | ||
1356 | return rc; | |
38ba30ba GN |
1357 | } |
1358 | ||
dde7e6d1 AK |
1359 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1360 | struct x86_emulate_ops* ops) | |
c37eda13 | 1361 | { |
dde7e6d1 AK |
1362 | switch(ctxt->mode) { |
1363 | case X86EMUL_MODE_REAL: | |
1364 | return emulate_iret_real(ctxt, ops); | |
1365 | case X86EMUL_MODE_VM86: | |
1366 | case X86EMUL_MODE_PROT16: | |
1367 | case X86EMUL_MODE_PROT32: | |
1368 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1369 | default: |
dde7e6d1 AK |
1370 | /* iret from protected mode unimplemented yet */ |
1371 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1372 | } |
c37eda13 WY |
1373 | } |
1374 | ||
dde7e6d1 | 1375 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1376 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1377 | { |
1378 | struct decode_cache *c = &ctxt->decode; | |
1379 | ||
dde7e6d1 | 1380 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1381 | } |
1382 | ||
dde7e6d1 | 1383 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1384 | { |
05f086f8 | 1385 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1386 | switch (c->modrm_reg) { |
1387 | case 0: /* rol */ | |
05f086f8 | 1388 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1389 | break; |
1390 | case 1: /* ror */ | |
05f086f8 | 1391 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1392 | break; |
1393 | case 2: /* rcl */ | |
05f086f8 | 1394 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1395 | break; |
1396 | case 3: /* rcr */ | |
05f086f8 | 1397 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1398 | break; |
1399 | case 4: /* sal/shl */ | |
1400 | case 6: /* sal/shl */ | |
05f086f8 | 1401 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1402 | break; |
1403 | case 5: /* shr */ | |
05f086f8 | 1404 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1405 | break; |
1406 | case 7: /* sar */ | |
05f086f8 | 1407 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1408 | break; |
1409 | } | |
1410 | } | |
1411 | ||
1412 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1413 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1414 | { |
1415 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1416 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1417 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
8cdbd2c9 LV |
1418 | |
1419 | switch (c->modrm_reg) { | |
1420 | case 0 ... 1: /* test */ | |
05f086f8 | 1421 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1422 | break; |
1423 | case 2: /* not */ | |
1424 | c->dst.val = ~c->dst.val; | |
1425 | break; | |
1426 | case 3: /* neg */ | |
05f086f8 | 1427 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1428 | break; |
3f9f53b0 MG |
1429 | case 4: /* mul */ |
1430 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1431 | break; | |
1432 | case 5: /* imul */ | |
1433 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1434 | break; | |
1435 | case 6: /* div */ | |
1436 | emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags); | |
1437 | break; | |
1438 | case 7: /* idiv */ | |
1439 | emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags); | |
1440 | break; | |
8cdbd2c9 | 1441 | default: |
8c5eee30 | 1442 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1443 | } |
8c5eee30 | 1444 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1445 | } |
1446 | ||
1447 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1448 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1449 | { |
1450 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1451 | |
1452 | switch (c->modrm_reg) { | |
1453 | case 0: /* inc */ | |
05f086f8 | 1454 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1455 | break; |
1456 | case 1: /* dec */ | |
05f086f8 | 1457 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1458 | break; |
d19292e4 MG |
1459 | case 2: /* call near abs */ { |
1460 | long int old_eip; | |
1461 | old_eip = c->eip; | |
1462 | c->eip = c->src.val; | |
1463 | c->src.val = old_eip; | |
79168fd1 | 1464 | emulate_push(ctxt, ops); |
d19292e4 MG |
1465 | break; |
1466 | } | |
8cdbd2c9 | 1467 | case 4: /* jmp abs */ |
fd60754e | 1468 | c->eip = c->src.val; |
8cdbd2c9 LV |
1469 | break; |
1470 | case 6: /* push */ | |
79168fd1 | 1471 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1472 | break; |
8cdbd2c9 | 1473 | } |
1b30eaa8 | 1474 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1475 | } |
1476 | ||
1477 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1478 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1479 | { |
1480 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1481 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1482 | |
1483 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1484 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1485 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1486 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1487 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1488 | } else { |
16518d5a AK |
1489 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1490 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1491 | |
05f086f8 | 1492 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1493 | } |
1b30eaa8 | 1494 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1495 | } |
1496 | ||
a77ab5ea AK |
1497 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1498 | struct x86_emulate_ops *ops) | |
1499 | { | |
1500 | struct decode_cache *c = &ctxt->decode; | |
1501 | int rc; | |
1502 | unsigned long cs; | |
1503 | ||
1504 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1505 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1506 | return rc; |
1507 | if (c->op_bytes == 4) | |
1508 | c->eip = (u32)c->eip; | |
1509 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1510 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1511 | return rc; |
2e873022 | 1512 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1513 | return rc; |
1514 | } | |
1515 | ||
e66bb2cc AP |
1516 | static inline void |
1517 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1518 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1519 | struct desc_struct *ss) | |
e66bb2cc | 1520 | { |
79168fd1 GN |
1521 | memset(cs, 0, sizeof(struct desc_struct)); |
1522 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1523 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1524 | |
1525 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1526 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1527 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1528 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1529 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1530 | cs->s = 1; | |
1531 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1532 | cs->p = 1; |
1533 | cs->d = 1; | |
e66bb2cc | 1534 | |
79168fd1 GN |
1535 | set_desc_base(ss, 0); /* flat segment */ |
1536 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1537 | ss->g = 1; /* 4kb granularity */ |
1538 | ss->s = 1; | |
1539 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1540 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1541 | ss->dpl = 0; |
79168fd1 | 1542 | ss->p = 1; |
e66bb2cc AP |
1543 | } |
1544 | ||
1545 | static int | |
3fb1b5db | 1546 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1547 | { |
1548 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1549 | struct desc_struct cs, ss; |
e66bb2cc | 1550 | u64 msr_data; |
79168fd1 | 1551 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1552 | |
1553 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1554 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1555 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1556 | emulate_ud(ctxt); |
2e901c4c GN |
1557 | return X86EMUL_PROPAGATE_FAULT; |
1558 | } | |
e66bb2cc | 1559 | |
79168fd1 | 1560 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1561 | |
3fb1b5db | 1562 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1563 | msr_data >>= 32; |
79168fd1 GN |
1564 | cs_sel = (u16)(msr_data & 0xfffc); |
1565 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1566 | |
1567 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1568 | cs.d = 0; |
e66bb2cc AP |
1569 | cs.l = 1; |
1570 | } | |
79168fd1 GN |
1571 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1572 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1573 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1574 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1575 | |
1576 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1577 | if (is_long_mode(ctxt->vcpu)) { | |
1578 | #ifdef CONFIG_X86_64 | |
1579 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1580 | ||
3fb1b5db GN |
1581 | ops->get_msr(ctxt->vcpu, |
1582 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1583 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1584 | c->eip = msr_data; |
1585 | ||
3fb1b5db | 1586 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1587 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1588 | #endif | |
1589 | } else { | |
1590 | /* legacy mode */ | |
3fb1b5db | 1591 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1592 | c->eip = (u32)msr_data; |
1593 | ||
1594 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1595 | } | |
1596 | ||
e54cfa97 | 1597 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1598 | } |
1599 | ||
8c604352 | 1600 | static int |
3fb1b5db | 1601 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1602 | { |
1603 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1604 | struct desc_struct cs, ss; |
8c604352 | 1605 | u64 msr_data; |
79168fd1 | 1606 | u16 cs_sel, ss_sel; |
8c604352 | 1607 | |
a0044755 GN |
1608 | /* inject #GP if in real mode */ |
1609 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 1610 | emulate_gp(ctxt, 0); |
2e901c4c | 1611 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1612 | } |
1613 | ||
1614 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1615 | * Therefore, we inject an #UD. | |
1616 | */ | |
2e901c4c | 1617 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 1618 | emulate_ud(ctxt); |
2e901c4c GN |
1619 | return X86EMUL_PROPAGATE_FAULT; |
1620 | } | |
8c604352 | 1621 | |
79168fd1 | 1622 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1623 | |
3fb1b5db | 1624 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1625 | switch (ctxt->mode) { |
1626 | case X86EMUL_MODE_PROT32: | |
1627 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 1628 | emulate_gp(ctxt, 0); |
e54cfa97 | 1629 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1630 | } |
1631 | break; | |
1632 | case X86EMUL_MODE_PROT64: | |
1633 | if (msr_data == 0x0) { | |
54b8486f | 1634 | emulate_gp(ctxt, 0); |
e54cfa97 | 1635 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1636 | } |
1637 | break; | |
1638 | } | |
1639 | ||
1640 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1641 | cs_sel = (u16)msr_data; |
1642 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1643 | ss_sel = cs_sel + 8; | |
1644 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1645 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1646 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1647 | cs.d = 0; |
8c604352 AP |
1648 | cs.l = 1; |
1649 | } | |
1650 | ||
79168fd1 GN |
1651 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1652 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1653 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1654 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 1655 | |
3fb1b5db | 1656 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1657 | c->eip = msr_data; |
1658 | ||
3fb1b5db | 1659 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1660 | c->regs[VCPU_REGS_RSP] = msr_data; |
1661 | ||
e54cfa97 | 1662 | return X86EMUL_CONTINUE; |
8c604352 AP |
1663 | } |
1664 | ||
4668f050 | 1665 | static int |
3fb1b5db | 1666 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1667 | { |
1668 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1669 | struct desc_struct cs, ss; |
4668f050 AP |
1670 | u64 msr_data; |
1671 | int usermode; | |
79168fd1 | 1672 | u16 cs_sel, ss_sel; |
4668f050 | 1673 | |
a0044755 GN |
1674 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1675 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1676 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1677 | emulate_gp(ctxt, 0); |
2e901c4c | 1678 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1679 | } |
1680 | ||
79168fd1 | 1681 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1682 | |
1683 | if ((c->rex_prefix & 0x8) != 0x0) | |
1684 | usermode = X86EMUL_MODE_PROT64; | |
1685 | else | |
1686 | usermode = X86EMUL_MODE_PROT32; | |
1687 | ||
1688 | cs.dpl = 3; | |
1689 | ss.dpl = 3; | |
3fb1b5db | 1690 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1691 | switch (usermode) { |
1692 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1693 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 1694 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 1695 | emulate_gp(ctxt, 0); |
e54cfa97 | 1696 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1697 | } |
79168fd1 | 1698 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1699 | break; |
1700 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1701 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 1702 | if (msr_data == 0x0) { |
54b8486f | 1703 | emulate_gp(ctxt, 0); |
e54cfa97 | 1704 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1705 | } |
79168fd1 GN |
1706 | ss_sel = cs_sel + 8; |
1707 | cs.d = 0; | |
4668f050 AP |
1708 | cs.l = 1; |
1709 | break; | |
1710 | } | |
79168fd1 GN |
1711 | cs_sel |= SELECTOR_RPL_MASK; |
1712 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1713 | |
79168fd1 GN |
1714 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1715 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1716 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1717 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 1718 | |
bdb475a3 GN |
1719 | c->eip = c->regs[VCPU_REGS_RDX]; |
1720 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1721 | |
e54cfa97 | 1722 | return X86EMUL_CONTINUE; |
4668f050 AP |
1723 | } |
1724 | ||
9c537244 GN |
1725 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1726 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1727 | { |
1728 | int iopl; | |
1729 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1730 | return false; | |
1731 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1732 | return true; | |
1733 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1734 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1735 | } |
1736 | ||
1737 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1738 | struct x86_emulate_ops *ops, | |
1739 | u16 port, u16 len) | |
1740 | { | |
79168fd1 | 1741 | struct desc_struct tr_seg; |
f850e2e6 GN |
1742 | int r; |
1743 | u16 io_bitmap_ptr; | |
1744 | u8 perm, bit_idx = port & 0x7; | |
1745 | unsigned mask = (1 << len) - 1; | |
1746 | ||
79168fd1 GN |
1747 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
1748 | if (!tr_seg.p) | |
f850e2e6 | 1749 | return false; |
79168fd1 | 1750 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1751 | return false; |
79168fd1 GN |
1752 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
1753 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
1754 | if (r != X86EMUL_CONTINUE) |
1755 | return false; | |
79168fd1 | 1756 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1757 | return false; |
79168fd1 GN |
1758 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
1759 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1760 | if (r != X86EMUL_CONTINUE) |
1761 | return false; | |
1762 | if ((perm >> bit_idx) & mask) | |
1763 | return false; | |
1764 | return true; | |
1765 | } | |
1766 | ||
1767 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1768 | struct x86_emulate_ops *ops, | |
1769 | u16 port, u16 len) | |
1770 | { | |
4fc40f07 GN |
1771 | if (ctxt->perm_ok) |
1772 | return true; | |
1773 | ||
9c537244 | 1774 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1775 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1776 | return false; | |
4fc40f07 GN |
1777 | |
1778 | ctxt->perm_ok = true; | |
1779 | ||
f850e2e6 GN |
1780 | return true; |
1781 | } | |
1782 | ||
38ba30ba GN |
1783 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1784 | struct x86_emulate_ops *ops, | |
1785 | struct tss_segment_16 *tss) | |
1786 | { | |
1787 | struct decode_cache *c = &ctxt->decode; | |
1788 | ||
1789 | tss->ip = c->eip; | |
1790 | tss->flag = ctxt->eflags; | |
1791 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1792 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1793 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1794 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1795 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1796 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1797 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1798 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1799 | ||
1800 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1801 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1802 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1803 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1804 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1805 | } | |
1806 | ||
1807 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1808 | struct x86_emulate_ops *ops, | |
1809 | struct tss_segment_16 *tss) | |
1810 | { | |
1811 | struct decode_cache *c = &ctxt->decode; | |
1812 | int ret; | |
1813 | ||
1814 | c->eip = tss->ip; | |
1815 | ctxt->eflags = tss->flag | 2; | |
1816 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1817 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1818 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1819 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1820 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1821 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1822 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1823 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1824 | ||
1825 | /* | |
1826 | * SDM says that segment selectors are loaded before segment | |
1827 | * descriptors | |
1828 | */ | |
1829 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1830 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1831 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1832 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1833 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1834 | ||
1835 | /* | |
1836 | * Now load segment descriptors. If fault happenes at this stage | |
1837 | * it is handled in a context of new task | |
1838 | */ | |
1839 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1840 | if (ret != X86EMUL_CONTINUE) | |
1841 | return ret; | |
1842 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1843 | if (ret != X86EMUL_CONTINUE) | |
1844 | return ret; | |
1845 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1846 | if (ret != X86EMUL_CONTINUE) | |
1847 | return ret; | |
1848 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1849 | if (ret != X86EMUL_CONTINUE) | |
1850 | return ret; | |
1851 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1852 | if (ret != X86EMUL_CONTINUE) | |
1853 | return ret; | |
1854 | ||
1855 | return X86EMUL_CONTINUE; | |
1856 | } | |
1857 | ||
1858 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1859 | struct x86_emulate_ops *ops, | |
1860 | u16 tss_selector, u16 old_tss_sel, | |
1861 | ulong old_tss_base, struct desc_struct *new_desc) | |
1862 | { | |
1863 | struct tss_segment_16 tss_seg; | |
1864 | int ret; | |
1865 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1866 | ||
1867 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1868 | &err); | |
1869 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1870 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1871 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1872 | return ret; |
1873 | } | |
1874 | ||
1875 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1876 | ||
1877 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1878 | &err); | |
1879 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1880 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1881 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1882 | return ret; |
1883 | } | |
1884 | ||
1885 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1886 | &err); | |
1887 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1888 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1889 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1890 | return ret; |
1891 | } | |
1892 | ||
1893 | if (old_tss_sel != 0xffff) { | |
1894 | tss_seg.prev_task_link = old_tss_sel; | |
1895 | ||
1896 | ret = ops->write_std(new_tss_base, | |
1897 | &tss_seg.prev_task_link, | |
1898 | sizeof tss_seg.prev_task_link, | |
1899 | ctxt->vcpu, &err); | |
1900 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1901 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1902 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1903 | return ret; |
1904 | } | |
1905 | } | |
1906 | ||
1907 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
1908 | } | |
1909 | ||
1910 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
1911 | struct x86_emulate_ops *ops, | |
1912 | struct tss_segment_32 *tss) | |
1913 | { | |
1914 | struct decode_cache *c = &ctxt->decode; | |
1915 | ||
1916 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
1917 | tss->eip = c->eip; | |
1918 | tss->eflags = ctxt->eflags; | |
1919 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
1920 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
1921 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
1922 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
1923 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
1924 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
1925 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
1926 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
1927 | ||
1928 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1929 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1930 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1931 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1932 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
1933 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
1934 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1935 | } | |
1936 | ||
1937 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
1938 | struct x86_emulate_ops *ops, | |
1939 | struct tss_segment_32 *tss) | |
1940 | { | |
1941 | struct decode_cache *c = &ctxt->decode; | |
1942 | int ret; | |
1943 | ||
0f12244f | 1944 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 1945 | emulate_gp(ctxt, 0); |
0f12244f GN |
1946 | return X86EMUL_PROPAGATE_FAULT; |
1947 | } | |
38ba30ba GN |
1948 | c->eip = tss->eip; |
1949 | ctxt->eflags = tss->eflags | 2; | |
1950 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
1951 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
1952 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
1953 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
1954 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
1955 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
1956 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
1957 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
1958 | ||
1959 | /* | |
1960 | * SDM says that segment selectors are loaded before segment | |
1961 | * descriptors | |
1962 | */ | |
1963 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
1964 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1965 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1966 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1967 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1968 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
1969 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
1970 | ||
1971 | /* | |
1972 | * Now load segment descriptors. If fault happenes at this stage | |
1973 | * it is handled in a context of new task | |
1974 | */ | |
1975 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
1976 | if (ret != X86EMUL_CONTINUE) | |
1977 | return ret; | |
1978 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1979 | if (ret != X86EMUL_CONTINUE) | |
1980 | return ret; | |
1981 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1982 | if (ret != X86EMUL_CONTINUE) | |
1983 | return ret; | |
1984 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1985 | if (ret != X86EMUL_CONTINUE) | |
1986 | return ret; | |
1987 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1988 | if (ret != X86EMUL_CONTINUE) | |
1989 | return ret; | |
1990 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
1991 | if (ret != X86EMUL_CONTINUE) | |
1992 | return ret; | |
1993 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
1994 | if (ret != X86EMUL_CONTINUE) | |
1995 | return ret; | |
1996 | ||
1997 | return X86EMUL_CONTINUE; | |
1998 | } | |
1999 | ||
2000 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2001 | struct x86_emulate_ops *ops, | |
2002 | u16 tss_selector, u16 old_tss_sel, | |
2003 | ulong old_tss_base, struct desc_struct *new_desc) | |
2004 | { | |
2005 | struct tss_segment_32 tss_seg; | |
2006 | int ret; | |
2007 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2008 | ||
2009 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2010 | &err); | |
2011 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2012 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2013 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2014 | return ret; |
2015 | } | |
2016 | ||
2017 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2018 | ||
2019 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2020 | &err); | |
2021 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2022 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2023 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2024 | return ret; |
2025 | } | |
2026 | ||
2027 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2028 | &err); | |
2029 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2030 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2031 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2032 | return ret; |
2033 | } | |
2034 | ||
2035 | if (old_tss_sel != 0xffff) { | |
2036 | tss_seg.prev_task_link = old_tss_sel; | |
2037 | ||
2038 | ret = ops->write_std(new_tss_base, | |
2039 | &tss_seg.prev_task_link, | |
2040 | sizeof tss_seg.prev_task_link, | |
2041 | ctxt->vcpu, &err); | |
2042 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2043 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2044 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2045 | return ret; |
2046 | } | |
2047 | } | |
2048 | ||
2049 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2050 | } | |
2051 | ||
2052 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2053 | struct x86_emulate_ops *ops, |
2054 | u16 tss_selector, int reason, | |
2055 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2056 | { |
2057 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2058 | int ret; | |
2059 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2060 | ulong old_tss_base = | |
5951c442 | 2061 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2062 | u32 desc_limit; |
38ba30ba GN |
2063 | |
2064 | /* FIXME: old_tss_base == ~0 ? */ | |
2065 | ||
2066 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2067 | if (ret != X86EMUL_CONTINUE) | |
2068 | return ret; | |
2069 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2070 | if (ret != X86EMUL_CONTINUE) | |
2071 | return ret; | |
2072 | ||
2073 | /* FIXME: check that next_tss_desc is tss */ | |
2074 | ||
2075 | if (reason != TASK_SWITCH_IRET) { | |
2076 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2077 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2078 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2079 | return X86EMUL_PROPAGATE_FAULT; |
2080 | } | |
2081 | } | |
2082 | ||
ceffb459 GN |
2083 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2084 | if (!next_tss_desc.p || | |
2085 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2086 | desc_limit < 0x2b)) { | |
54b8486f | 2087 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2088 | return X86EMUL_PROPAGATE_FAULT; |
2089 | } | |
2090 | ||
2091 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2092 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2093 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2094 | &curr_tss_desc); | |
2095 | } | |
2096 | ||
2097 | if (reason == TASK_SWITCH_IRET) | |
2098 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2099 | ||
2100 | /* set back link to prev task only if NT bit is set in eflags | |
2101 | note that old_tss_sel is not used afetr this point */ | |
2102 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2103 | old_tss_sel = 0xffff; | |
2104 | ||
2105 | if (next_tss_desc.type & 8) | |
2106 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2107 | old_tss_base, &next_tss_desc); | |
2108 | else | |
2109 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2110 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2111 | if (ret != X86EMUL_CONTINUE) |
2112 | return ret; | |
38ba30ba GN |
2113 | |
2114 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2115 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2116 | ||
2117 | if (reason != TASK_SWITCH_IRET) { | |
2118 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2119 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2120 | &next_tss_desc); | |
2121 | } | |
2122 | ||
2123 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2124 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2125 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2126 | ||
e269fb21 JK |
2127 | if (has_error_code) { |
2128 | struct decode_cache *c = &ctxt->decode; | |
2129 | ||
2130 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2131 | c->lock_prefix = 0; | |
2132 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2133 | emulate_push(ctxt, ops); |
e269fb21 JK |
2134 | } |
2135 | ||
38ba30ba GN |
2136 | return ret; |
2137 | } | |
2138 | ||
2139 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2140 | u16 tss_selector, int reason, |
2141 | bool has_error_code, u32 error_code) | |
38ba30ba | 2142 | { |
9aabc88f | 2143 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2144 | struct decode_cache *c = &ctxt->decode; |
2145 | int rc; | |
2146 | ||
38ba30ba | 2147 | c->eip = ctxt->eip; |
e269fb21 | 2148 | c->dst.type = OP_NONE; |
38ba30ba | 2149 | |
e269fb21 JK |
2150 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2151 | has_error_code, error_code); | |
38ba30ba GN |
2152 | |
2153 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2154 | rc = writeback(ctxt, ops); |
95c55886 GN |
2155 | if (rc == X86EMUL_CONTINUE) |
2156 | ctxt->eip = c->eip; | |
38ba30ba GN |
2157 | } |
2158 | ||
19d04437 | 2159 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2160 | } |
2161 | ||
a682e354 | 2162 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2163 | int reg, struct operand *op) |
a682e354 GN |
2164 | { |
2165 | struct decode_cache *c = &ctxt->decode; | |
2166 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2167 | ||
d9271123 | 2168 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
1a6440ae | 2169 | op->addr.mem = register_address(c, base, c->regs[reg]); |
a682e354 GN |
2170 | } |
2171 | ||
63540382 AK |
2172 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2173 | { | |
2174 | emulate_push(ctxt, ctxt->ops); | |
2175 | return X86EMUL_CONTINUE; | |
2176 | } | |
2177 | ||
7af04fc0 AK |
2178 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2179 | { | |
2180 | struct decode_cache *c = &ctxt->decode; | |
2181 | u8 al, old_al; | |
2182 | bool af, cf, old_cf; | |
2183 | ||
2184 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2185 | al = c->dst.val; | |
2186 | ||
2187 | old_al = al; | |
2188 | old_cf = cf; | |
2189 | cf = false; | |
2190 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2191 | if ((al & 0x0f) > 9 || af) { | |
2192 | al -= 6; | |
2193 | cf = old_cf | (al >= 250); | |
2194 | af = true; | |
2195 | } else { | |
2196 | af = false; | |
2197 | } | |
2198 | if (old_al > 0x99 || old_cf) { | |
2199 | al -= 0x60; | |
2200 | cf = true; | |
2201 | } | |
2202 | ||
2203 | c->dst.val = al; | |
2204 | /* Set PF, ZF, SF */ | |
2205 | c->src.type = OP_IMM; | |
2206 | c->src.val = 0; | |
2207 | c->src.bytes = 1; | |
2208 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2209 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2210 | if (cf) | |
2211 | ctxt->eflags |= X86_EFLAGS_CF; | |
2212 | if (af) | |
2213 | ctxt->eflags |= X86_EFLAGS_AF; | |
2214 | return X86EMUL_CONTINUE; | |
2215 | } | |
2216 | ||
73fba5f4 AK |
2217 | #define D(_y) { .flags = (_y) } |
2218 | #define N D(0) | |
2219 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2220 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2221 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
2222 | ||
2223 | static struct opcode group1[] = { | |
2224 | X7(D(Lock)), N | |
2225 | }; | |
2226 | ||
2227 | static struct opcode group1A[] = { | |
2228 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2229 | }; | |
2230 | ||
2231 | static struct opcode group3[] = { | |
2232 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2233 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2234 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2235 | }; |
2236 | ||
2237 | static struct opcode group4[] = { | |
2238 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2239 | N, N, N, N, N, N, | |
2240 | }; | |
2241 | ||
2242 | static struct opcode group5[] = { | |
2243 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
2244 | D(SrcMem | ModRM | Stack), N, | |
2245 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), | |
2246 | D(SrcMem | ModRM | Stack), N, | |
2247 | }; | |
2248 | ||
2249 | static struct group_dual group7 = { { | |
2250 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2251 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2252 | D(SrcMem16 | ModRM | Mov | Priv), |
2253 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 AK |
2254 | }, { |
2255 | D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv), | |
2256 | D(SrcNone | ModRM | DstMem | Mov), N, | |
2257 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2258 | } }; | |
2259 | ||
2260 | static struct opcode group8[] = { | |
2261 | N, N, N, N, | |
2262 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2263 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2264 | }; | |
2265 | ||
2266 | static struct group_dual group9 = { { | |
2267 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2268 | }, { | |
2269 | N, N, N, N, N, N, N, N, | |
2270 | } }; | |
2271 | ||
2272 | static struct opcode opcode_table[256] = { | |
2273 | /* 0x00 - 0x07 */ | |
2274 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2275 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2276 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2277 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2278 | /* 0x08 - 0x0F */ | |
2279 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2280 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2281 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2282 | D(ImplicitOps | Stack | No64), N, | |
2283 | /* 0x10 - 0x17 */ | |
2284 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2285 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2286 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2287 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2288 | /* 0x18 - 0x1F */ | |
2289 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2290 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2291 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2292 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2293 | /* 0x20 - 0x27 */ | |
2294 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2295 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2296 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2297 | /* 0x28 - 0x2F */ | |
2298 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2299 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
7af04fc0 AK |
2300 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), |
2301 | N, I(ByteOp | DstAcc | No64, em_das), | |
73fba5f4 AK |
2302 | /* 0x30 - 0x37 */ |
2303 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2304 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2305 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2306 | /* 0x38 - 0x3F */ | |
2307 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2308 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2309 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2310 | N, N, | |
2311 | /* 0x40 - 0x4F */ | |
2312 | X16(D(DstReg)), | |
2313 | /* 0x50 - 0x57 */ | |
63540382 | 2314 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2315 | /* 0x58 - 0x5F */ |
2316 | X8(D(DstReg | Stack)), | |
2317 | /* 0x60 - 0x67 */ | |
2318 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2319 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2320 | N, N, N, N, | |
2321 | /* 0x68 - 0x6F */ | |
63540382 AK |
2322 | I(SrcImm | Mov | Stack, em_push), N, |
2323 | I(SrcImmByte | Mov | Stack, em_push), N, | |
73fba5f4 AK |
2324 | D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */ |
2325 | D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
2326 | /* 0x70 - 0x7F */ | |
2327 | X16(D(SrcImmByte)), | |
2328 | /* 0x80 - 0x87 */ | |
2329 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2330 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2331 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2332 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
2333 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2334 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2335 | /* 0x88 - 0x8F */ | |
2336 | D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov), | |
2337 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov), | |
342fc630 | 2338 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2339 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2340 | /* 0x90 - 0x97 */ | |
3d9e77df | 2341 | X8(D(SrcAcc | DstReg)), |
73fba5f4 | 2342 | /* 0x98 - 0x9F */ |
e8b6fa70 | 2343 | D(DstAcc | SrcNone), N, D(SrcImmFAddr | No64), N, |
73fba5f4 AK |
2344 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, |
2345 | /* 0xA0 - 0xA7 */ | |
2346 | D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs), | |
2347 | D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs), | |
2348 | D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String), | |
2349 | D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String), | |
2350 | /* 0xA8 - 0xAF */ | |
06cb7046 WY |
2351 | D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), |
2352 | D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String), | |
73fba5f4 | 2353 | D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String), |
f6b33fc5 | 2354 | D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String), |
73fba5f4 AK |
2355 | /* 0xB0 - 0xB7 */ |
2356 | X8(D(ByteOp | DstReg | SrcImm | Mov)), | |
2357 | /* 0xB8 - 0xBF */ | |
2358 | X8(D(DstReg | SrcImm | Mov)), | |
2359 | /* 0xC0 - 0xC7 */ | |
2360 | D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM), | |
2361 | N, D(ImplicitOps | Stack), N, N, | |
2362 | D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov), | |
2363 | /* 0xC8 - 0xCF */ | |
2364 | N, N, N, D(ImplicitOps | Stack), | |
2365 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2366 | /* 0xD0 - 0xD7 */ | |
c034da8b | 2367 | D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM), |
73fba5f4 AK |
2368 | D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM), |
2369 | N, N, N, N, | |
2370 | /* 0xD8 - 0xDF */ | |
2371 | N, N, N, N, N, N, N, N, | |
2372 | /* 0xE0 - 0xE7 */ | |
f2f31845 | 2373 | X3(D(SrcImmByte)), N, |
73fba5f4 | 2374 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), |
41167be5 | 2375 | D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte), |
73fba5f4 AK |
2376 | /* 0xE8 - 0xEF */ |
2377 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2378 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
2379 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
41167be5 | 2380 | D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps), |
73fba5f4 AK |
2381 | /* 0xF0 - 0xF7 */ |
2382 | N, N, N, N, | |
2383 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2384 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2385 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2386 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2387 | }; | |
2388 | ||
2389 | static struct opcode twobyte_table[256] = { | |
2390 | /* 0x00 - 0x0F */ | |
2391 | N, GD(0, &group7), N, N, | |
2392 | N, D(ImplicitOps), D(ImplicitOps | Priv), N, | |
2393 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, | |
2394 | N, D(ImplicitOps | ModRM), N, N, | |
2395 | /* 0x10 - 0x1F */ | |
2396 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2397 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2398 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2399 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2400 | N, N, N, N, |
2401 | N, N, N, N, N, N, N, N, | |
2402 | /* 0x30 - 0x3F */ | |
2403 | D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N, | |
2404 | D(ImplicitOps), D(ImplicitOps | Priv), N, N, | |
2405 | N, N, N, N, N, N, N, N, | |
2406 | /* 0x40 - 0x4F */ | |
2407 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2408 | /* 0x50 - 0x5F */ | |
2409 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2410 | /* 0x60 - 0x6F */ | |
2411 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2412 | /* 0x70 - 0x7F */ | |
2413 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2414 | /* 0x80 - 0x8F */ | |
2415 | X16(D(SrcImm)), | |
2416 | /* 0x90 - 0x9F */ | |
ee45b58e | 2417 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2418 | /* 0xA0 - 0xA7 */ |
2419 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2420 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2421 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2422 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2423 | /* 0xA8 - 0xAF */ | |
2424 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2425 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2426 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2427 | D(DstMem | SrcReg | Src2CL | ModRM), | |
2428 | D(ModRM), N, | |
2429 | /* 0xB0 - 0xB7 */ | |
2430 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2431 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2432 | N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov), | |
2433 | D(DstReg | SrcMem16 | ModRM | Mov), | |
2434 | /* 0xB8 - 0xBF */ | |
2435 | N, N, | |
ba7ff2b7 | 2436 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2437 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2438 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2439 | /* 0xC0 - 0xCF */ |
92f738a5 WY |
2440 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), |
2441 | N, D(DstMem | SrcReg | ModRM | Mov), | |
73fba5f4 AK |
2442 | N, N, N, GD(0, &group9), |
2443 | N, N, N, N, N, N, N, N, | |
2444 | /* 0xD0 - 0xDF */ | |
2445 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2446 | /* 0xE0 - 0xEF */ | |
2447 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2448 | /* 0xF0 - 0xFF */ | |
2449 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2450 | }; | |
2451 | ||
2452 | #undef D | |
2453 | #undef N | |
2454 | #undef G | |
2455 | #undef GD | |
2456 | #undef I | |
2457 | ||
dde7e6d1 AK |
2458 | int |
2459 | x86_decode_insn(struct x86_emulate_ctxt *ctxt) | |
2460 | { | |
2461 | struct x86_emulate_ops *ops = ctxt->ops; | |
2462 | struct decode_cache *c = &ctxt->decode; | |
2463 | int rc = X86EMUL_CONTINUE; | |
2464 | int mode = ctxt->mode; | |
2465 | int def_op_bytes, def_ad_bytes, dual, goffset; | |
2466 | struct opcode opcode, *g_mod012, *g_mod3; | |
2dbd0dd7 | 2467 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 AK |
2468 | |
2469 | /* we cannot decode insn before we complete previous rep insn */ | |
2470 | WARN_ON(ctxt->restart); | |
2471 | ||
2472 | c->eip = ctxt->eip; | |
2473 | c->fetch.start = c->fetch.end = c->eip; | |
2474 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); | |
2475 | ||
2476 | switch (mode) { | |
2477 | case X86EMUL_MODE_REAL: | |
2478 | case X86EMUL_MODE_VM86: | |
2479 | case X86EMUL_MODE_PROT16: | |
2480 | def_op_bytes = def_ad_bytes = 2; | |
2481 | break; | |
2482 | case X86EMUL_MODE_PROT32: | |
2483 | def_op_bytes = def_ad_bytes = 4; | |
2484 | break; | |
2485 | #ifdef CONFIG_X86_64 | |
2486 | case X86EMUL_MODE_PROT64: | |
2487 | def_op_bytes = 4; | |
2488 | def_ad_bytes = 8; | |
2489 | break; | |
2490 | #endif | |
2491 | default: | |
2492 | return -1; | |
2493 | } | |
2494 | ||
2495 | c->op_bytes = def_op_bytes; | |
2496 | c->ad_bytes = def_ad_bytes; | |
2497 | ||
2498 | /* Legacy prefixes. */ | |
2499 | for (;;) { | |
2500 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2501 | case 0x66: /* operand-size override */ | |
2502 | /* switch between 2/4 bytes */ | |
2503 | c->op_bytes = def_op_bytes ^ 6; | |
2504 | break; | |
2505 | case 0x67: /* address-size override */ | |
2506 | if (mode == X86EMUL_MODE_PROT64) | |
2507 | /* switch between 4/8 bytes */ | |
2508 | c->ad_bytes = def_ad_bytes ^ 12; | |
2509 | else | |
2510 | /* switch between 2/4 bytes */ | |
2511 | c->ad_bytes = def_ad_bytes ^ 6; | |
2512 | break; | |
2513 | case 0x26: /* ES override */ | |
2514 | case 0x2e: /* CS override */ | |
2515 | case 0x36: /* SS override */ | |
2516 | case 0x3e: /* DS override */ | |
2517 | set_seg_override(c, (c->b >> 3) & 3); | |
2518 | break; | |
2519 | case 0x64: /* FS override */ | |
2520 | case 0x65: /* GS override */ | |
2521 | set_seg_override(c, c->b & 7); | |
2522 | break; | |
2523 | case 0x40 ... 0x4f: /* REX */ | |
2524 | if (mode != X86EMUL_MODE_PROT64) | |
2525 | goto done_prefixes; | |
2526 | c->rex_prefix = c->b; | |
2527 | continue; | |
2528 | case 0xf0: /* LOCK */ | |
2529 | c->lock_prefix = 1; | |
2530 | break; | |
2531 | case 0xf2: /* REPNE/REPNZ */ | |
2532 | c->rep_prefix = REPNE_PREFIX; | |
2533 | break; | |
2534 | case 0xf3: /* REP/REPE/REPZ */ | |
2535 | c->rep_prefix = REPE_PREFIX; | |
2536 | break; | |
2537 | default: | |
2538 | goto done_prefixes; | |
2539 | } | |
2540 | ||
2541 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2542 | ||
2543 | c->rex_prefix = 0; | |
2544 | } | |
2545 | ||
2546 | done_prefixes: | |
2547 | ||
2548 | /* REX prefix. */ | |
1e87e3ef AK |
2549 | if (c->rex_prefix & 8) |
2550 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2551 | |
2552 | /* Opcode byte(s). */ | |
2553 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2554 | /* Two-byte opcode? */ |
2555 | if (c->b == 0x0f) { | |
2556 | c->twobyte = 1; | |
2557 | c->b = insn_fetch(u8, 1, c->eip); | |
2558 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2559 | } |
2560 | c->d = opcode.flags; | |
2561 | ||
2562 | if (c->d & Group) { | |
2563 | dual = c->d & GroupDual; | |
2564 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2565 | --c->eip; | |
2566 | ||
2567 | if (c->d & GroupDual) { | |
2568 | g_mod012 = opcode.u.gdual->mod012; | |
2569 | g_mod3 = opcode.u.gdual->mod3; | |
2570 | } else | |
2571 | g_mod012 = g_mod3 = opcode.u.group; | |
2572 | ||
2573 | c->d &= ~(Group | GroupDual); | |
2574 | ||
2575 | goffset = (c->modrm >> 3) & 7; | |
2576 | ||
2577 | if ((c->modrm >> 6) == 3) | |
2578 | opcode = g_mod3[goffset]; | |
2579 | else | |
2580 | opcode = g_mod012[goffset]; | |
2581 | c->d |= opcode.flags; | |
2582 | } | |
2583 | ||
2584 | c->execute = opcode.u.execute; | |
2585 | ||
2586 | /* Unrecognised? */ | |
2587 | if (c->d == 0 || (c->d & Undefined)) { | |
2588 | DPRINTF("Cannot emulate %02x\n", c->b); | |
2589 | return -1; | |
2590 | } | |
2591 | ||
2592 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) | |
2593 | c->op_bytes = 8; | |
2594 | ||
7f9b4b75 AK |
2595 | if (c->d & Op3264) { |
2596 | if (mode == X86EMUL_MODE_PROT64) | |
2597 | c->op_bytes = 8; | |
2598 | else | |
2599 | c->op_bytes = 4; | |
2600 | } | |
2601 | ||
dde7e6d1 | 2602 | /* ModRM and SIB bytes. */ |
09ee57cd | 2603 | if (c->d & ModRM) { |
2dbd0dd7 | 2604 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2605 | if (!c->has_seg_override) |
2606 | set_seg_override(c, c->modrm_seg); | |
2607 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2608 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2609 | if (rc != X86EMUL_CONTINUE) |
2610 | goto done; | |
2611 | ||
2612 | if (!c->has_seg_override) | |
2613 | set_seg_override(c, VCPU_SREG_DS); | |
2614 | ||
2dbd0dd7 AK |
2615 | if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d)) |
2616 | memop.addr.mem += seg_override_base(ctxt, ops, c); | |
dde7e6d1 | 2617 | |
2dbd0dd7 AK |
2618 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
2619 | memop.addr.mem = (u32)memop.addr.mem; | |
dde7e6d1 | 2620 | |
2dbd0dd7 AK |
2621 | if (memop.type == OP_MEM && c->rip_relative) |
2622 | memop.addr.mem += c->eip; | |
dde7e6d1 AK |
2623 | |
2624 | /* | |
2625 | * Decode and fetch the source operand: register, memory | |
2626 | * or immediate. | |
2627 | */ | |
2628 | switch (c->d & SrcMask) { | |
2629 | case SrcNone: | |
2630 | break; | |
2631 | case SrcReg: | |
2632 | decode_register_operand(&c->src, c, 0); | |
2633 | break; | |
2634 | case SrcMem16: | |
2dbd0dd7 | 2635 | memop.bytes = 2; |
dde7e6d1 AK |
2636 | goto srcmem_common; |
2637 | case SrcMem32: | |
2dbd0dd7 | 2638 | memop.bytes = 4; |
dde7e6d1 AK |
2639 | goto srcmem_common; |
2640 | case SrcMem: | |
2dbd0dd7 | 2641 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2642 | c->op_bytes; |
dde7e6d1 | 2643 | srcmem_common: |
2dbd0dd7 | 2644 | c->src = memop; |
dde7e6d1 AK |
2645 | break; |
2646 | case SrcImm: | |
2647 | case SrcImmU: | |
2648 | c->src.type = OP_IMM; | |
1a6440ae | 2649 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2650 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
2651 | if (c->src.bytes == 8) | |
2652 | c->src.bytes = 4; | |
2653 | /* NB. Immediates are sign-extended as necessary. */ | |
2654 | switch (c->src.bytes) { | |
2655 | case 1: | |
2656 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2657 | break; | |
2658 | case 2: | |
2659 | c->src.val = insn_fetch(s16, 2, c->eip); | |
2660 | break; | |
2661 | case 4: | |
2662 | c->src.val = insn_fetch(s32, 4, c->eip); | |
2663 | break; | |
2664 | } | |
2665 | if ((c->d & SrcMask) == SrcImmU) { | |
2666 | switch (c->src.bytes) { | |
2667 | case 1: | |
2668 | c->src.val &= 0xff; | |
2669 | break; | |
2670 | case 2: | |
2671 | c->src.val &= 0xffff; | |
2672 | break; | |
2673 | case 4: | |
2674 | c->src.val &= 0xffffffff; | |
2675 | break; | |
2676 | } | |
2677 | } | |
2678 | break; | |
2679 | case SrcImmByte: | |
2680 | case SrcImmUByte: | |
2681 | c->src.type = OP_IMM; | |
1a6440ae | 2682 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2683 | c->src.bytes = 1; |
2684 | if ((c->d & SrcMask) == SrcImmByte) | |
2685 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2686 | else | |
2687 | c->src.val = insn_fetch(u8, 1, c->eip); | |
2688 | break; | |
2689 | case SrcAcc: | |
2690 | c->src.type = OP_REG; | |
2691 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2692 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2693 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2694 | break; |
2695 | case SrcOne: | |
2696 | c->src.bytes = 1; | |
2697 | c->src.val = 1; | |
2698 | break; | |
2699 | case SrcSI: | |
2700 | c->src.type = OP_MEM; | |
2701 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2702 | c->src.addr.mem = |
dde7e6d1 AK |
2703 | register_address(c, seg_override_base(ctxt, ops, c), |
2704 | c->regs[VCPU_REGS_RSI]); | |
2705 | c->src.val = 0; | |
2706 | break; | |
2707 | case SrcImmFAddr: | |
2708 | c->src.type = OP_IMM; | |
1a6440ae | 2709 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2710 | c->src.bytes = c->op_bytes + 2; |
2711 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2712 | break; | |
2713 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2714 | memop.bytes = c->op_bytes + 2; |
2715 | goto srcmem_common; | |
dde7e6d1 AK |
2716 | break; |
2717 | } | |
2718 | ||
2719 | /* | |
2720 | * Decode and fetch the second source operand: register, memory | |
2721 | * or immediate. | |
2722 | */ | |
2723 | switch (c->d & Src2Mask) { | |
2724 | case Src2None: | |
2725 | break; | |
2726 | case Src2CL: | |
2727 | c->src2.bytes = 1; | |
2728 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2729 | break; | |
2730 | case Src2ImmByte: | |
2731 | c->src2.type = OP_IMM; | |
1a6440ae | 2732 | c->src2.addr.mem = c->eip; |
dde7e6d1 AK |
2733 | c->src2.bytes = 1; |
2734 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
2735 | break; | |
2736 | case Src2One: | |
2737 | c->src2.bytes = 1; | |
2738 | c->src2.val = 1; | |
2739 | break; | |
2740 | } | |
2741 | ||
2742 | /* Decode and fetch the destination operand: register or memory. */ | |
2743 | switch (c->d & DstMask) { | |
dde7e6d1 AK |
2744 | case DstReg: |
2745 | decode_register_operand(&c->dst, c, | |
2746 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); | |
2747 | break; | |
943858e2 WY |
2748 | case DstImmUByte: |
2749 | c->dst.type = OP_IMM; | |
2750 | c->dst.addr.mem = c->eip; | |
2751 | c->dst.bytes = 1; | |
2752 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
2753 | break; | |
dde7e6d1 AK |
2754 | case DstMem: |
2755 | case DstMem64: | |
2dbd0dd7 | 2756 | c->dst = memop; |
dde7e6d1 AK |
2757 | if ((c->d & DstMask) == DstMem64) |
2758 | c->dst.bytes = 8; | |
2759 | else | |
2760 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
2761 | if (c->d & BitOp) |
2762 | fetch_bit_operand(c); | |
2dbd0dd7 | 2763 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
2764 | break; |
2765 | case DstAcc: | |
2766 | c->dst.type = OP_REG; | |
2767 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2768 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2769 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
2770 | c->dst.orig_val = c->dst.val; |
2771 | break; | |
2772 | case DstDI: | |
2773 | c->dst.type = OP_MEM; | |
2774 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2775 | c->dst.addr.mem = |
dde7e6d1 AK |
2776 | register_address(c, es_base(ctxt, ops), |
2777 | c->regs[VCPU_REGS_RDI]); | |
2778 | c->dst.val = 0; | |
2779 | break; | |
36089fed WY |
2780 | case ImplicitOps: |
2781 | /* Special instructions do their own operand decoding. */ | |
2782 | default: | |
2783 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2784 | return 0; | |
dde7e6d1 AK |
2785 | } |
2786 | ||
2787 | done: | |
2788 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
2789 | } | |
2790 | ||
8b4caf66 | 2791 | int |
9aabc88f | 2792 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 2793 | { |
9aabc88f | 2794 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 2795 | u64 msr_data; |
8b4caf66 | 2796 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2797 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2798 | int saved_dst_type = c->dst.type; |
6e154e56 | 2799 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 2800 | |
9de41573 | 2801 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2802 | |
1161624f | 2803 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2804 | emulate_ud(ctxt); |
1161624f GN |
2805 | goto done; |
2806 | } | |
2807 | ||
d380a5e4 | 2808 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2809 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2810 | emulate_ud(ctxt); |
d380a5e4 GN |
2811 | goto done; |
2812 | } | |
2813 | ||
e92805ac | 2814 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2815 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 2816 | emulate_gp(ctxt, 0); |
e92805ac GN |
2817 | goto done; |
2818 | } | |
2819 | ||
b9fa9d6b | 2820 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2821 | ctxt->restart = true; |
b9fa9d6b | 2822 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2823 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 | 2824 | ctxt->restart = false; |
95c55886 | 2825 | ctxt->eip = c->eip; |
b9fa9d6b AK |
2826 | goto done; |
2827 | } | |
b9fa9d6b AK |
2828 | } |
2829 | ||
c483c02a | 2830 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
1a6440ae | 2831 | rc = read_emulated(ctxt, ops, c->src.addr.mem, |
414e6277 | 2832 | c->src.valptr, c->src.bytes); |
b60d513c | 2833 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 2834 | goto done; |
16518d5a | 2835 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
2836 | } |
2837 | ||
e35b7b9c | 2838 | if (c->src2.type == OP_MEM) { |
1a6440ae | 2839 | rc = read_emulated(ctxt, ops, c->src2.addr.mem, |
9de41573 | 2840 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
2841 | if (rc != X86EMUL_CONTINUE) |
2842 | goto done; | |
2843 | } | |
2844 | ||
8b4caf66 LV |
2845 | if ((c->d & DstMask) == ImplicitOps) |
2846 | goto special_insn; | |
2847 | ||
2848 | ||
69f55cb1 GN |
2849 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2850 | /* optimisation - avoid slow emulated read if Mov */ | |
1a6440ae | 2851 | rc = read_emulated(ctxt, ops, c->dst.addr.mem, |
9de41573 | 2852 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
2853 | if (rc != X86EMUL_CONTINUE) |
2854 | goto done; | |
038e51de | 2855 | } |
e4e03ded | 2856 | c->dst.orig_val = c->dst.val; |
038e51de | 2857 | |
018a98db AK |
2858 | special_insn: |
2859 | ||
ef65c889 AK |
2860 | if (c->execute) { |
2861 | rc = c->execute(ctxt); | |
2862 | if (rc != X86EMUL_CONTINUE) | |
2863 | goto done; | |
2864 | goto writeback; | |
2865 | } | |
2866 | ||
e4e03ded | 2867 | if (c->twobyte) |
6aa8b732 AK |
2868 | goto twobyte_insn; |
2869 | ||
e4e03ded | 2870 | switch (c->b) { |
6aa8b732 AK |
2871 | case 0x00 ... 0x05: |
2872 | add: /* add */ | |
05f086f8 | 2873 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2874 | break; |
0934ac9d | 2875 | case 0x06: /* push es */ |
79168fd1 | 2876 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
2877 | break; |
2878 | case 0x07: /* pop es */ | |
0934ac9d | 2879 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2880 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2881 | goto done; |
2882 | break; | |
6aa8b732 AK |
2883 | case 0x08 ... 0x0d: |
2884 | or: /* or */ | |
05f086f8 | 2885 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2886 | break; |
0934ac9d | 2887 | case 0x0e: /* push cs */ |
79168fd1 | 2888 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 2889 | break; |
6aa8b732 AK |
2890 | case 0x10 ... 0x15: |
2891 | adc: /* adc */ | |
05f086f8 | 2892 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2893 | break; |
0934ac9d | 2894 | case 0x16: /* push ss */ |
79168fd1 | 2895 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
2896 | break; |
2897 | case 0x17: /* pop ss */ | |
0934ac9d | 2898 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2899 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2900 | goto done; |
2901 | break; | |
6aa8b732 AK |
2902 | case 0x18 ... 0x1d: |
2903 | sbb: /* sbb */ | |
05f086f8 | 2904 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2905 | break; |
0934ac9d | 2906 | case 0x1e: /* push ds */ |
79168fd1 | 2907 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
2908 | break; |
2909 | case 0x1f: /* pop ds */ | |
0934ac9d | 2910 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2911 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2912 | goto done; |
2913 | break; | |
aa3a816b | 2914 | case 0x20 ... 0x25: |
6aa8b732 | 2915 | and: /* and */ |
05f086f8 | 2916 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2917 | break; |
2918 | case 0x28 ... 0x2d: | |
2919 | sub: /* sub */ | |
05f086f8 | 2920 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2921 | break; |
2922 | case 0x30 ... 0x35: | |
2923 | xor: /* xor */ | |
05f086f8 | 2924 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2925 | break; |
2926 | case 0x38 ... 0x3d: | |
2927 | cmp: /* cmp */ | |
05f086f8 | 2928 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2929 | break; |
33615aa9 AK |
2930 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2931 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2932 | break; | |
2933 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2934 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2935 | break; | |
33615aa9 AK |
2936 | case 0x58 ... 0x5f: /* pop reg */ |
2937 | pop_instruction: | |
350f69dc | 2938 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2939 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2940 | goto done; |
33615aa9 | 2941 | break; |
abcf14b5 | 2942 | case 0x60: /* pusha */ |
c37eda13 WY |
2943 | rc = emulate_pusha(ctxt, ops); |
2944 | if (rc != X86EMUL_CONTINUE) | |
2945 | goto done; | |
abcf14b5 MG |
2946 | break; |
2947 | case 0x61: /* popa */ | |
2948 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2949 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2950 | goto done; |
2951 | break; | |
6aa8b732 | 2952 | case 0x63: /* movsxd */ |
8b4caf66 | 2953 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2954 | goto cannot_emulate; |
e4e03ded | 2955 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2956 | break; |
018a98db AK |
2957 | case 0x6c: /* insb */ |
2958 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
2959 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2960 | goto do_io_in; | |
018a98db AK |
2961 | case 0x6e: /* outsb */ |
2962 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
2963 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
2964 | goto do_io_out; | |
7972995b | 2965 | break; |
b2833e3c | 2966 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2967 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2968 | jmp_rel(c, c->src.val); |
018a98db | 2969 | break; |
6aa8b732 | 2970 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2971 | switch (c->modrm_reg) { |
6aa8b732 AK |
2972 | case 0: |
2973 | goto add; | |
2974 | case 1: | |
2975 | goto or; | |
2976 | case 2: | |
2977 | goto adc; | |
2978 | case 3: | |
2979 | goto sbb; | |
2980 | case 4: | |
2981 | goto and; | |
2982 | case 5: | |
2983 | goto sub; | |
2984 | case 6: | |
2985 | goto xor; | |
2986 | case 7: | |
2987 | goto cmp; | |
2988 | } | |
2989 | break; | |
2990 | case 0x84 ... 0x85: | |
dfb507c4 | 2991 | test: |
05f086f8 | 2992 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2993 | break; |
2994 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2995 | xchg: |
6aa8b732 | 2996 | /* Write back the register source. */ |
31be40b3 WY |
2997 | c->src.val = c->dst.val; |
2998 | write_register_operand(&c->src); | |
6aa8b732 AK |
2999 | /* |
3000 | * Write back the memory destination with implicit LOCK | |
3001 | * prefix. | |
3002 | */ | |
31be40b3 | 3003 | c->dst.val = c->src.orig_val; |
e4e03ded | 3004 | c->lock_prefix = 1; |
6aa8b732 | 3005 | break; |
6aa8b732 | 3006 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 3007 | goto mov; |
79168fd1 GN |
3008 | case 0x8c: /* mov r/m, sreg */ |
3009 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3010 | emulate_ud(ctxt); |
5e3ae6c5 | 3011 | goto done; |
38d5bc6d | 3012 | } |
79168fd1 | 3013 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3014 | break; |
7e0b54b1 | 3015 | case 0x8d: /* lea r16/r32, m */ |
342fc630 | 3016 | c->dst.val = c->src.addr.mem; |
7e0b54b1 | 3017 | break; |
4257198a GT |
3018 | case 0x8e: { /* mov seg, r/m16 */ |
3019 | uint16_t sel; | |
4257198a GT |
3020 | |
3021 | sel = c->src.val; | |
8b9f4414 | 3022 | |
c697518a GN |
3023 | if (c->modrm_reg == VCPU_SREG_CS || |
3024 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3025 | emulate_ud(ctxt); |
8b9f4414 GN |
3026 | goto done; |
3027 | } | |
3028 | ||
310b5d30 | 3029 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3030 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3031 | |
2e873022 | 3032 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3033 | |
3034 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3035 | break; | |
3036 | } | |
6aa8b732 | 3037 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3038 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 3039 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 3040 | goto done; |
6aa8b732 | 3041 | break; |
3d9e77df AK |
3042 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3043 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3044 | break; |
b13354f8 | 3045 | goto xchg; |
e8b6fa70 WY |
3046 | case 0x98: /* cbw/cwde/cdqe */ |
3047 | switch (c->op_bytes) { | |
3048 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3049 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3050 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3051 | } | |
3052 | break; | |
fd2a7608 | 3053 | case 0x9c: /* pushf */ |
05f086f8 | 3054 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3055 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3056 | break; |
535eabcf | 3057 | case 0x9d: /* popf */ |
2b48cc75 | 3058 | c->dst.type = OP_REG; |
1a6440ae | 3059 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3060 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
3061 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
3062 | if (rc != X86EMUL_CONTINUE) | |
3063 | goto done; | |
3064 | break; | |
5d55f299 | 3065 | case 0xa0 ... 0xa3: /* mov */ |
6aa8b732 | 3066 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 3067 | goto mov; |
6aa8b732 | 3068 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3069 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a6440ae | 3070 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem); |
a682e354 | 3071 | goto cmp; |
dfb507c4 MG |
3072 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3073 | goto test; | |
6aa8b732 | 3074 | case 0xaa ... 0xab: /* stos */ |
6aa8b732 | 3075 | case 0xac ... 0xad: /* lods */ |
a682e354 | 3076 | goto mov; |
6aa8b732 | 3077 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3078 | goto cmp; |
a5e2e82b | 3079 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 3080 | goto mov; |
018a98db AK |
3081 | case 0xc0 ... 0xc1: |
3082 | emulate_grp2(ctxt); | |
3083 | break; | |
111de5d6 | 3084 | case 0xc3: /* ret */ |
cf5de4f8 | 3085 | c->dst.type = OP_REG; |
1a6440ae | 3086 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3087 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3088 | goto pop_instruction; |
018a98db AK |
3089 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
3090 | mov: | |
3091 | c->dst.val = c->src.val; | |
3092 | break; | |
a77ab5ea AK |
3093 | case 0xcb: /* ret far */ |
3094 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e MG |
3095 | if (rc != X86EMUL_CONTINUE) |
3096 | goto done; | |
3097 | break; | |
6e154e56 MG |
3098 | case 0xcc: /* int3 */ |
3099 | irq = 3; | |
3100 | goto do_interrupt; | |
3101 | case 0xcd: /* int n */ | |
3102 | irq = c->src.val; | |
3103 | do_interrupt: | |
3104 | rc = emulate_int(ctxt, ops, irq); | |
3105 | if (rc != X86EMUL_CONTINUE) | |
3106 | goto done; | |
3107 | break; | |
3108 | case 0xce: /* into */ | |
3109 | if (ctxt->eflags & EFLG_OF) { | |
3110 | irq = 4; | |
3111 | goto do_interrupt; | |
3112 | } | |
3113 | break; | |
62bd430e MG |
3114 | case 0xcf: /* iret */ |
3115 | rc = emulate_iret(ctxt, ops); | |
3116 | ||
1b30eaa8 | 3117 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
3118 | goto done; |
3119 | break; | |
018a98db | 3120 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3121 | emulate_grp2(ctxt); |
3122 | break; | |
3123 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3124 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3125 | emulate_grp2(ctxt); | |
3126 | break; | |
f2f31845 WY |
3127 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3128 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3129 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3130 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3131 | jmp_rel(c, c->src.val); | |
3132 | break; | |
a6a3034c MG |
3133 | case 0xe4: /* inb */ |
3134 | case 0xe5: /* in */ | |
cf8f70bf | 3135 | goto do_io_in; |
a6a3034c MG |
3136 | case 0xe6: /* outb */ |
3137 | case 0xe7: /* out */ | |
cf8f70bf | 3138 | goto do_io_out; |
1a52e051 | 3139 | case 0xe8: /* call (near) */ { |
d53c4777 | 3140 | long int rel = c->src.val; |
e4e03ded | 3141 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3142 | jmp_rel(c, rel); |
79168fd1 | 3143 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3144 | break; |
1a52e051 NK |
3145 | } |
3146 | case 0xe9: /* jmp rel */ | |
954cd36f | 3147 | goto jmp; |
414e6277 GN |
3148 | case 0xea: { /* jmp far */ |
3149 | unsigned short sel; | |
ea79849d | 3150 | jump_far: |
414e6277 GN |
3151 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3152 | ||
3153 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3154 | goto done; |
954cd36f | 3155 | |
414e6277 GN |
3156 | c->eip = 0; |
3157 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3158 | break; |
414e6277 | 3159 | } |
954cd36f GT |
3160 | case 0xeb: |
3161 | jmp: /* jmp rel short */ | |
7a957275 | 3162 | jmp_rel(c, c->src.val); |
a01af5ec | 3163 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3164 | break; |
a6a3034c MG |
3165 | case 0xec: /* in al,dx */ |
3166 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3167 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3168 | do_io_in: | |
3169 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3170 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3171 | emulate_gp(ctxt, 0); |
cf8f70bf GN |
3172 | goto done; |
3173 | } | |
7b262e90 GN |
3174 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3175 | &c->dst.val)) | |
cf8f70bf GN |
3176 | goto done; /* IO is needed */ |
3177 | break; | |
ce7a0ad3 WY |
3178 | case 0xee: /* out dx,al */ |
3179 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3180 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3181 | do_io_out: |
41167be5 WY |
3182 | c->src.bytes = min(c->src.bytes, 4u); |
3183 | if (!emulator_io_permited(ctxt, ops, c->dst.val, | |
3184 | c->src.bytes)) { | |
54b8486f | 3185 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
3186 | goto done; |
3187 | } | |
41167be5 WY |
3188 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3189 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3190 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3191 | break; |
111de5d6 | 3192 | case 0xf4: /* hlt */ |
ad312c7c | 3193 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3194 | break; |
111de5d6 AK |
3195 | case 0xf5: /* cmc */ |
3196 | /* complement carry flag from eflags reg */ | |
3197 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3198 | break; |
018a98db | 3199 | case 0xf6 ... 0xf7: /* Grp3 */ |
8c5eee30 | 3200 | if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE) |
aca06a83 | 3201 | goto cannot_emulate; |
018a98db | 3202 | break; |
111de5d6 AK |
3203 | case 0xf8: /* clc */ |
3204 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3205 | break; |
8744aa9a MG |
3206 | case 0xf9: /* stc */ |
3207 | ctxt->eflags |= EFLG_CF; | |
3208 | break; | |
111de5d6 | 3209 | case 0xfa: /* cli */ |
07cbc6c1 | 3210 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3211 | emulate_gp(ctxt, 0); |
07cbc6c1 | 3212 | goto done; |
36089fed | 3213 | } else |
f850e2e6 | 3214 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3215 | break; |
3216 | case 0xfb: /* sti */ | |
07cbc6c1 | 3217 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3218 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3219 | goto done; |
3220 | } else { | |
95cb2295 | 3221 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3222 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3223 | } |
111de5d6 | 3224 | break; |
fb4616f4 MG |
3225 | case 0xfc: /* cld */ |
3226 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3227 | break; |
3228 | case 0xfd: /* std */ | |
3229 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3230 | break; |
ea79849d GN |
3231 | case 0xfe: /* Grp4 */ |
3232 | grp45: | |
018a98db | 3233 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 3234 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3235 | goto done; |
3236 | break; | |
ea79849d GN |
3237 | case 0xff: /* Grp5 */ |
3238 | if (c->modrm_reg == 5) | |
3239 | goto jump_far; | |
3240 | goto grp45; | |
91269b8f AK |
3241 | default: |
3242 | goto cannot_emulate; | |
6aa8b732 | 3243 | } |
018a98db AK |
3244 | |
3245 | writeback: | |
3246 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3247 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3248 | goto done; |
3249 | ||
5cd21917 GN |
3250 | /* |
3251 | * restore dst type in case the decoding will be reused | |
3252 | * (happens for string instruction ) | |
3253 | */ | |
3254 | c->dst.type = saved_dst_type; | |
3255 | ||
a682e354 | 3256 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3257 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3258 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3259 | |
3260 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3261 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3262 | &c->dst); | |
d9271123 | 3263 | |
5cd21917 | 3264 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3265 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3266 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
0fa6ccbd AK |
3267 | /* The second termination condition only applies for REPE |
3268 | * and REPNE. Test if the repeat string operation prefix is | |
3269 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3270 | * corresponding termination condition according to: | |
3271 | * - if REPE/REPZ and ZF = 0 then done | |
3272 | * - if REPNE/REPNZ and ZF = 1 then done | |
3273 | */ | |
3274 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
3275 | (c->b == 0xae) || (c->b == 0xaf)) | |
3276 | && (((c->rep_prefix == REPE_PREFIX) && | |
3277 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
3278 | || ((c->rep_prefix == REPNE_PREFIX) && | |
3279 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
3280 | ctxt->restart = false; | |
7b262e90 GN |
3281 | /* |
3282 | * Re-enter guest when pio read ahead buffer is empty or, | |
3283 | * if it is not used, after each 1024 iteration. | |
3284 | */ | |
0fa6ccbd AK |
3285 | else if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || |
3286 | (rc->end != 0 && rc->end == rc->pos)) { | |
5cd21917 | 3287 | ctxt->restart = false; |
0fa6ccbd AK |
3288 | c->eip = ctxt->eip; |
3289 | } | |
5cd21917 | 3290 | } |
9de41573 GN |
3291 | /* |
3292 | * reset read cache here in case string instruction is restared | |
3293 | * without decoding | |
3294 | */ | |
3295 | ctxt->decode.mem_read.end = 0; | |
0fa6ccbd AK |
3296 | if (!ctxt->restart) |
3297 | ctxt->eip = c->eip; | |
018a98db AK |
3298 | |
3299 | done: | |
cb404fe0 | 3300 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3301 | |
3302 | twobyte_insn: | |
e4e03ded | 3303 | switch (c->b) { |
6aa8b732 | 3304 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3305 | switch (c->modrm_reg) { |
6aa8b732 AK |
3306 | u16 size; |
3307 | unsigned long address; | |
3308 | ||
aca7f966 | 3309 | case 0: /* vmcall */ |
e4e03ded | 3310 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3311 | goto cannot_emulate; |
3312 | ||
7aa81cc0 | 3313 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3314 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3315 | goto done; |
3316 | ||
33e3885d | 3317 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3318 | c->eip = ctxt->eip; |
16286d08 AK |
3319 | /* Disable writeback. */ |
3320 | c->dst.type = OP_NONE; | |
aca7f966 | 3321 | break; |
6aa8b732 | 3322 | case 2: /* lgdt */ |
1a6440ae | 3323 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3324 | &size, &address, c->op_bytes); |
1b30eaa8 | 3325 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3326 | goto done; |
3327 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3328 | /* Disable writeback. */ |
3329 | c->dst.type = OP_NONE; | |
6aa8b732 | 3330 | break; |
aca7f966 | 3331 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3332 | if (c->modrm_mod == 3) { |
3333 | switch (c->modrm_rm) { | |
3334 | case 1: | |
3335 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3336 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3337 | goto done; |
3338 | break; | |
3339 | default: | |
3340 | goto cannot_emulate; | |
3341 | } | |
aca7f966 | 3342 | } else { |
1a6440ae | 3343 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3344 | &size, &address, |
e4e03ded | 3345 | c->op_bytes); |
1b30eaa8 | 3346 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3347 | goto done; |
3348 | realmode_lidt(ctxt->vcpu, size, address); | |
3349 | } | |
16286d08 AK |
3350 | /* Disable writeback. */ |
3351 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3352 | break; |
3353 | case 4: /* smsw */ | |
16286d08 | 3354 | c->dst.bytes = 2; |
52a46617 | 3355 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3356 | break; |
3357 | case 6: /* lmsw */ | |
9928ff60 | 3358 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3359 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3360 | c->dst.type = OP_NONE; |
6aa8b732 | 3361 | break; |
6e1e5ffe | 3362 | case 5: /* not defined */ |
54b8486f | 3363 | emulate_ud(ctxt); |
6e1e5ffe | 3364 | goto done; |
6aa8b732 | 3365 | case 7: /* invlpg*/ |
1f6f0580 | 3366 | emulate_invlpg(ctxt->vcpu, c->src.addr.mem); |
16286d08 AK |
3367 | /* Disable writeback. */ |
3368 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3369 | break; |
3370 | default: | |
3371 | goto cannot_emulate; | |
3372 | } | |
3373 | break; | |
e99f0507 | 3374 | case 0x05: /* syscall */ |
3fb1b5db | 3375 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3376 | if (rc != X86EMUL_CONTINUE) |
3377 | goto done; | |
e66bb2cc AP |
3378 | else |
3379 | goto writeback; | |
e99f0507 | 3380 | break; |
018a98db AK |
3381 | case 0x06: |
3382 | emulate_clts(ctxt->vcpu); | |
018a98db | 3383 | break; |
018a98db | 3384 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3385 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3386 | break; |
3387 | case 0x08: /* invd */ | |
018a98db AK |
3388 | case 0x0d: /* GrpP (prefetch) */ |
3389 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3390 | break; |
3391 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3392 | switch (c->modrm_reg) { |
3393 | case 1: | |
3394 | case 5 ... 7: | |
3395 | case 9 ... 15: | |
54b8486f | 3396 | emulate_ud(ctxt); |
6aebfa6e GN |
3397 | goto done; |
3398 | } | |
1a0c7d44 | 3399 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3400 | break; |
6aa8b732 | 3401 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3402 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3403 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3404 | emulate_ud(ctxt); |
1e470be5 GN |
3405 | goto done; |
3406 | } | |
b27f3856 | 3407 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3408 | break; |
018a98db | 3409 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3410 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3411 | emulate_gp(ctxt, 0); |
0f12244f GN |
3412 | goto done; |
3413 | } | |
018a98db AK |
3414 | c->dst.type = OP_NONE; |
3415 | break; | |
6aa8b732 | 3416 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3417 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3418 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3419 | emulate_ud(ctxt); |
1e470be5 GN |
3420 | goto done; |
3421 | } | |
35aa5375 | 3422 | |
b27f3856 | 3423 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3424 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3425 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3426 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3427 | emulate_gp(ctxt, 0); |
338dbc97 GN |
3428 | goto done; |
3429 | } | |
3430 | ||
a01af5ec | 3431 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3432 | break; |
018a98db AK |
3433 | case 0x30: |
3434 | /* wrmsr */ | |
3435 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3436 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3437 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3438 | emulate_gp(ctxt, 0); |
fd525365 | 3439 | goto done; |
018a98db AK |
3440 | } |
3441 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3442 | break; |
3443 | case 0x32: | |
3444 | /* rdmsr */ | |
3fb1b5db | 3445 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3446 | emulate_gp(ctxt, 0); |
fd525365 | 3447 | goto done; |
018a98db AK |
3448 | } else { |
3449 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3450 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3451 | } | |
3452 | rc = X86EMUL_CONTINUE; | |
018a98db | 3453 | break; |
e99f0507 | 3454 | case 0x34: /* sysenter */ |
3fb1b5db | 3455 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3456 | if (rc != X86EMUL_CONTINUE) |
3457 | goto done; | |
8c604352 AP |
3458 | else |
3459 | goto writeback; | |
e99f0507 AP |
3460 | break; |
3461 | case 0x35: /* sysexit */ | |
3fb1b5db | 3462 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3463 | if (rc != X86EMUL_CONTINUE) |
3464 | goto done; | |
4668f050 AP |
3465 | else |
3466 | goto writeback; | |
e99f0507 | 3467 | break; |
6aa8b732 | 3468 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3469 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3470 | if (!test_cc(c->b, ctxt->eflags)) |
3471 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3472 | break; |
b2833e3c | 3473 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3474 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3475 | jmp_rel(c, c->src.val); |
018a98db | 3476 | break; |
ee45b58e WY |
3477 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
3478 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
3479 | break; | |
0934ac9d | 3480 | case 0xa0: /* push fs */ |
79168fd1 | 3481 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3482 | break; |
3483 | case 0xa1: /* pop fs */ | |
3484 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3485 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3486 | goto done; |
3487 | break; | |
7de75248 NK |
3488 | case 0xa3: |
3489 | bt: /* bt */ | |
e4f8e039 | 3490 | c->dst.type = OP_NONE; |
e4e03ded LV |
3491 | /* only subword offset */ |
3492 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3493 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3494 | break; |
9bf8ea42 GT |
3495 | case 0xa4: /* shld imm8, r, r/m */ |
3496 | case 0xa5: /* shld cl, r, r/m */ | |
3497 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3498 | break; | |
0934ac9d | 3499 | case 0xa8: /* push gs */ |
79168fd1 | 3500 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3501 | break; |
3502 | case 0xa9: /* pop gs */ | |
3503 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3504 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3505 | goto done; |
3506 | break; | |
7de75248 NK |
3507 | case 0xab: |
3508 | bts: /* bts */ | |
05f086f8 | 3509 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3510 | break; |
9bf8ea42 GT |
3511 | case 0xac: /* shrd imm8, r, r/m */ |
3512 | case 0xad: /* shrd cl, r, r/m */ | |
3513 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3514 | break; | |
2a7c5b8b GC |
3515 | case 0xae: /* clflush */ |
3516 | break; | |
6aa8b732 AK |
3517 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3518 | /* | |
3519 | * Save real source value, then compare EAX against | |
3520 | * destination. | |
3521 | */ | |
e4e03ded LV |
3522 | c->src.orig_val = c->src.val; |
3523 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3524 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3525 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3526 | /* Success: write back to memory. */ |
e4e03ded | 3527 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3528 | } else { |
3529 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3530 | c->dst.type = OP_REG; |
1a6440ae | 3531 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3532 | } |
3533 | break; | |
6aa8b732 AK |
3534 | case 0xb3: |
3535 | btr: /* btr */ | |
05f086f8 | 3536 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3537 | break; |
6aa8b732 | 3538 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3539 | c->dst.bytes = c->op_bytes; |
3540 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3541 | : (u16) c->src.val; | |
6aa8b732 | 3542 | break; |
6aa8b732 | 3543 | case 0xba: /* Grp8 */ |
e4e03ded | 3544 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3545 | case 0: |
3546 | goto bt; | |
3547 | case 1: | |
3548 | goto bts; | |
3549 | case 2: | |
3550 | goto btr; | |
3551 | case 3: | |
3552 | goto btc; | |
3553 | } | |
3554 | break; | |
7de75248 NK |
3555 | case 0xbb: |
3556 | btc: /* btc */ | |
05f086f8 | 3557 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3558 | break; |
d9574a25 WY |
3559 | case 0xbc: { /* bsf */ |
3560 | u8 zf; | |
3561 | __asm__ ("bsf %2, %0; setz %1" | |
3562 | : "=r"(c->dst.val), "=q"(zf) | |
3563 | : "r"(c->src.val)); | |
3564 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3565 | if (zf) { | |
3566 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3567 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3568 | } | |
3569 | break; | |
3570 | } | |
3571 | case 0xbd: { /* bsr */ | |
3572 | u8 zf; | |
3573 | __asm__ ("bsr %2, %0; setz %1" | |
3574 | : "=r"(c->dst.val), "=q"(zf) | |
3575 | : "r"(c->src.val)); | |
3576 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3577 | if (zf) { | |
3578 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3579 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3580 | } | |
3581 | break; | |
3582 | } | |
6aa8b732 | 3583 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3584 | c->dst.bytes = c->op_bytes; |
3585 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3586 | (s16) c->src.val; | |
6aa8b732 | 3587 | break; |
92f738a5 WY |
3588 | case 0xc0 ... 0xc1: /* xadd */ |
3589 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
3590 | /* Write back the register source. */ | |
3591 | c->src.val = c->dst.orig_val; | |
3592 | write_register_operand(&c->src); | |
3593 | break; | |
a012e65a | 3594 | case 0xc3: /* movnti */ |
e4e03ded LV |
3595 | c->dst.bytes = c->op_bytes; |
3596 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3597 | (u64) c->src.val; | |
a012e65a | 3598 | break; |
6aa8b732 | 3599 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3600 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3601 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3602 | goto done; |
3603 | break; | |
91269b8f AK |
3604 | default: |
3605 | goto cannot_emulate; | |
6aa8b732 AK |
3606 | } |
3607 | goto writeback; | |
3608 | ||
3609 | cannot_emulate: | |
e4e03ded | 3610 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3611 | return -1; |
3612 | } |