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KVM: emulator: implement AAD instruction
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 164 const struct opcode *group;
165 const struct group_dual *gdual;
166 const struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
dd856efa
AK		 205static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
206{
207 if (!(ctxt->regs_valid & (1 << nr))) {
208 ctxt->regs_valid |= 1 << nr;
209 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
210 }
211 return ctxt->_regs[nr];
212}
213
214static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
215{
216 ctxt->regs_valid |= 1 << nr;
217 ctxt->regs_dirty |= 1 << nr;
218 return &ctxt->_regs[nr];
219}
220
221static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
222{
223 reg_read(ctxt, nr);
224 return reg_write(ctxt, nr);
225}
226
227static void writeback_registers(struct x86_emulate_ctxt *ctxt)
228{
229 unsigned reg;
230
231 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
232 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
233}
234
235static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
236{
237 ctxt->regs_dirty = 0;
238 ctxt->regs_valid = 0;
239}
240
6aa8b732
AK		 241/*
242 * Instruction emulation:
243 * Most instructions are emulated directly via a fragment of inline assembly
244 * code. This allows us to save/restore EFLAGS and thus very easily pick up
245 * any modified flags.
246 */
247
05b3e0c2 248#if defined(CONFIG_X86_64)
6aa8b732
AK		 249#define _LO32 "k" /* force 32-bit operand */
250#define _STK "%%rsp" /* stack pointer */
251#elif defined(__i386__)
252#define _LO32 "" /* force 32-bit operand */
253#define _STK "%%esp" /* stack pointer */
254#endif
255
256/*
257 * These EFLAGS bits are restored from saved value during emulation, and
258 * any changes are written back to the saved value after emulation.
259 */
260#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
261
262/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 263#define _PRE_EFLAGS(_sav, _msk, _tmp) \
264 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
265 "movl %"_sav",%"_LO32 _tmp"; " \
266 "push %"_tmp"; " \
267 "push %"_tmp"; " \
268 "movl %"_msk",%"_LO32 _tmp"; " \
269 "andl %"_LO32 _tmp",("_STK"); " \
270 "pushf; " \
271 "notl %"_LO32 _tmp"; " \
272 "andl %"_LO32 _tmp",("_STK"); " \
273 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
274 "pop %"_tmp"; " \
275 "orl %"_LO32 _tmp",("_STK"); " \
276 "popf; " \
277 "pop %"_sav"; "
6aa8b732
AK		 278
279/* After executing instruction: write-back necessary bits in EFLAGS. */
280#define _POST_EFLAGS(_sav, _msk, _tmp) \
281 /* _sav |= EFLAGS & _msk; */ \
282 "pushf; " \
283 "pop %"_tmp"; " \
284 "andl %"_msk",%"_LO32 _tmp"; " \
285 "orl %"_LO32 _tmp",%"_sav"; "
286
dda96d8f
AK		 287#ifdef CONFIG_X86_64
288#define ON64(x) x
289#else
290#define ON64(x)
291#endif
292
a31b9cea 293#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 294 do { \
295 __asm__ __volatile__ ( \
296 _PRE_EFLAGS("0", "4", "2") \
297 _op _suffix " %"_x"3,%1; " \
298 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 299 : "=m" ((ctxt)->eflags), \
300 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 301 "=&r" (_tmp) \
a31b9cea 302 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 303 } while (0)
6b7ad61f
AK		 304
305
6aa8b732 306/* Raw emulation: instruction has two explicit operands. */
a31b9cea 307#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 308 do { \
309 unsigned long _tmp; \
310 \
a31b9cea 311 switch ((ctxt)->dst.bytes) { \
6b7ad61f 312 case 2: \
a31b9cea 313 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 314 break; \
315 case 4: \
a31b9cea 316 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 317 break; \
318 case 8: \
a31b9cea 319 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 320 break; \
321 } \
6aa8b732
AK		 322 } while (0)
323
a31b9cea 324#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 325 do { \
6b7ad61f 326 unsigned long _tmp; \
a31b9cea 327 switch ((ctxt)->dst.bytes) { \
6aa8b732 328 case 1: \
a31b9cea 329 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 330 break; \
331 default: \
a31b9cea 332 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 333 _wx, _wy, _lx, _ly, _qx, _qy); \
334 break; \
335 } \
336 } while (0)
337
338/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 339#define emulate_2op_SrcB(ctxt, _op) \
340 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 341
342/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 343#define emulate_2op_SrcV(ctxt, _op) \
344 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 345
346/* Source operand is word, long or quad sized. */
a31b9cea
AK		 347#define emulate_2op_SrcV_nobyte(ctxt, _op) \
348 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 349
d175226a 350/* Instruction has three operands and one operand is stored in ECX register */
29053a60 351#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 352 do { \
353 unsigned long _tmp; \
761441b9
AK		 354 _type _clv = (ctxt)->src2.val; \
355 _type _srcv = (ctxt)->src.val; \
356 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 357 \
358 __asm__ __volatile__ ( \
359 _PRE_EFLAGS("0", "5", "2") \
360 _op _suffix " %4,%1 \n" \
361 _POST_EFLAGS("0", "5", "2") \
761441b9 362 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 363 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
364 ); \
365 \
761441b9
AK		 366 (ctxt)->src2.val = (unsigned long) _clv; \
367 (ctxt)->src2.val = (unsigned long) _srcv; \
368 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 369 } while (0)
370
761441b9 371#define emulate_2op_cl(ctxt, _op) \
7295261c 372 do { \
761441b9 373 switch ((ctxt)->dst.bytes) { \
7295261c 374 case 2: \
29053a60 375 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 376 break; \
377 case 4: \
29053a60 378 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 379 break; \
380 case 8: \
29053a60 381 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 382 break; \
383 } \
d175226a
GT		 384 } while (0)
385
d1eef45d 386#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 387 do { \
388 unsigned long _tmp; \
389 \
dda96d8f
AK		 390 __asm__ __volatile__ ( \
391 _PRE_EFLAGS("0", "3", "2") \
392 _op _suffix " %1; " \
393 _POST_EFLAGS("0", "3", "2") \
d1eef45d 394 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 395 "=&r" (_tmp) \
396 : "i" (EFLAGS_MASK)); \
397 } while (0)
398
399/* Instruction has only one explicit operand (no source operand). */
d1eef45d 400#define emulate_1op(ctxt, _op) \
dda96d8f 401 do { \
d1eef45d
AK		 402 switch ((ctxt)->dst.bytes) { \
403 case 1: __emulate_1op(ctxt, _op, "b"); break; \
404 case 2: __emulate_1op(ctxt, _op, "w"); break; \
405 case 4: __emulate_1op(ctxt, _op, "l"); break; \
406 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 407 } \
408 } while (0)
409
e8f2b1d6 410#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 411 do { \
412 unsigned long _tmp; \
dd856efa
AK		 413 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
414 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 415 \
416 __asm__ __volatile__ ( \
417 _PRE_EFLAGS("0", "5", "1") \
418 "1: \n\t" \
419 _op _suffix " %6; " \
420 "2: \n\t" \
421 _POST_EFLAGS("0", "5", "1") \
422 ".pushsection .fixup,\"ax\" \n\t" \
423 "3: movb $1, %4 \n\t" \
424 "jmp 2b \n\t" \
425 ".popsection \n\t" \
426 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 427 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
428 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 429 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 430 } while (0)
431
3f9f53b0 432/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 433#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 434 do { \
e8f2b1d6 435 switch((ctxt)->src.bytes) { \
7295261c 436 case 1: \
e8f2b1d6 437 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 438 break; \
439 case 2: \
e8f2b1d6 440 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 441 break; \
442 case 4: \
e8f2b1d6 443 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 444 break; \
445 case 8: ON64( \
e8f2b1d6 446 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 447 break; \
448 } \
449 } while (0)
450
8a76d7f2
JR		 451static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
452 enum x86_intercept intercept,
453 enum x86_intercept_stage stage)
454{
455 struct x86_instruction_info info = {
456 .intercept = intercept,
9dac77fa
AK		 457 .rep_prefix = ctxt->rep_prefix,
458 .modrm_mod = ctxt->modrm_mod,
459 .modrm_reg = ctxt->modrm_reg,
460 .modrm_rm = ctxt->modrm_rm,
461 .src_val = ctxt->src.val64,
462 .src_bytes = ctxt->src.bytes,
463 .dst_bytes = ctxt->dst.bytes,
464 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 465 .next_rip = ctxt->eip,
466 };
467
2953538e 468 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 469}
470
f47cfa31
AK		 471static void assign_masked(ulong *dest, ulong src, ulong mask)
472{
473 *dest = (*dest & ~mask) | (src & mask);
474}
475
9dac77fa 476static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 477{
9dac77fa 478 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 479}
480
f47cfa31
AK		 481static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
482{
483 u16 sel;
484 struct desc_struct ss;
485
486 if (ctxt->mode == X86EMUL_MODE_PROT64)
487 return ~0UL;
488 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
489 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
490}
491
612e89f0
AK		 492static int stack_size(struct x86_emulate_ctxt *ctxt)
493{
494 return (__fls(stack_mask(ctxt)) + 1) >> 3;
495}
496
6aa8b732 497/* Access/update address held in a register, based on addressing mode. */
e4706772 498static inline unsigned long
9dac77fa 499address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 500{
9dac77fa 501 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 502 return reg;
503 else
9dac77fa 504 return reg & ad_mask(ctxt);
e4706772
HH		 505}
506
507static inline unsigned long
9dac77fa 508register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 509{
9dac77fa 510 return address_mask(ctxt, reg);
e4706772
HH		 511}
512
5ad105e5
AK		 513static void masked_increment(ulong *reg, ulong mask, int inc)
514{
515 assign_masked(reg, *reg + inc, mask);
516}
517
7a957275 518static inline void
9dac77fa 519register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 520{
5ad105e5
AK		 521 ulong mask;
522
9dac77fa 523 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 524 mask = ~0UL;
7a957275 525 else
5ad105e5
AK		 526 mask = ad_mask(ctxt);
527 masked_increment(reg, mask, inc);
528}
529
530static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
531{
dd856efa 532 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 533}
6aa8b732 534
9dac77fa 535static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 536{
9dac77fa 537 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 538}
098c937b 539
56697687
AK		 540static u32 desc_limit_scaled(struct desc_struct *desc)
541{
542 u32 limit = get_desc_limit(desc);
543
544 return desc->g ? (limit << 12) | 0xfff : limit;
545}
546
9dac77fa 547static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 548{
9dac77fa
AK		 549 ctxt->has_seg_override = true;
550 ctxt->seg_override = seg;
7a5b56df
AK		 551}
552
7b105ca2 553static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 554{
555 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
556 return 0;
557
7b105ca2 558 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 559}
560
9dac77fa 561static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 562{
9dac77fa 563 if (!ctxt->has_seg_override)
7a5b56df
AK		 564 return 0;
565
9dac77fa 566 return ctxt->seg_override;
7a5b56df
AK		 567}
568
35d3d4a1
AK		 569static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
570 u32 error, bool valid)
54b8486f 571{
da9cb575
AK		 572 ctxt->exception.vector = vec;
573 ctxt->exception.error_code = error;
574 ctxt->exception.error_code_valid = valid;
35d3d4a1 575 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 576}
577
3b88e41a
JR		 578static int emulate_db(struct x86_emulate_ctxt *ctxt)
579{
580 return emulate_exception(ctxt, DB_VECTOR, 0, false);
581}
582
35d3d4a1 583static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 584{
35d3d4a1 585 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 586}
587
618ff15d
AK		 588static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
589{
590 return emulate_exception(ctxt, SS_VECTOR, err, true);
591}
592
35d3d4a1 593static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 594{
35d3d4a1 595 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 596}
597
35d3d4a1 598static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 599{
35d3d4a1 600 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 601}
602
34d1f490
AK		 603static int emulate_de(struct x86_emulate_ctxt *ctxt)
604{
35d3d4a1 605 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 606}
607
1253791d
AK		 608static int emulate_nm(struct x86_emulate_ctxt *ctxt)
609{
610 return emulate_exception(ctxt, NM_VECTOR, 0, false);
611}
612
1aa36616
AK		 613static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
614{
615 u16 selector;
616 struct desc_struct desc;
617
618 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
619 return selector;
620}
621
622static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
623 unsigned seg)
624{
625 u16 dummy;
626 u32 base3;
627 struct desc_struct desc;
628
629 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
630 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
631}
632
1c11b376
AK		 633/*
634 * x86 defines three classes of vector instructions: explicitly
635 * aligned, explicitly unaligned, and the rest, which change behaviour
636 * depending on whether they're AVX encoded or not.
637 *
638 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
639 * subject to the same check.
640 */
641static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
642{
643 if (likely(size < 16))
644 return false;
645
646 if (ctxt->d & Aligned)
647 return true;
648 else if (ctxt->d & Unaligned)
649 return false;
650 else if (ctxt->d & Avx)
651 return false;
652 else
653 return true;
654}
655
3d9b938e 656static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 657 struct segmented_address addr,
3d9b938e 658 unsigned size, bool write, bool fetch,
52fd8b44
AK		 659 ulong *linear)
660{
618ff15d
AK		 661 struct desc_struct desc;
662 bool usable;
52fd8b44 663 ulong la;
618ff15d 664 u32 lim;
1aa36616 665 u16 sel;
618ff15d 666 unsigned cpl, rpl;
52fd8b44 667
7b105ca2 668 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 669 switch (ctxt->mode) {
618ff15d
AK		 670 case X86EMUL_MODE_PROT64:
671 if (((signed long)la << 16) >> 16 != la)
672 return emulate_gp(ctxt, 0);
673 break;
674 default:
1aa36616
AK		 675 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
676 addr.seg);
618ff15d
AK		 677 if (!usable)
678 goto bad;
58b7825b
GN		 679 /* code segment in protected mode or read-only data segment */
680 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
681 || !(desc.type & 2)) && write)
618ff15d
AK		 682 goto bad;
683 /* unreadable code segment */
3d9b938e 684 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 685 goto bad;
686 lim = desc_limit_scaled(&desc);
687 if ((desc.type & 8) || !(desc.type & 4)) {
688 /* expand-up segment */
689 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
690 goto bad;
691 } else {
fc058680 692 /* expand-down segment */
618ff15d
AK		 693 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
694 goto bad;
695 lim = desc.d ? 0xffffffff : 0xffff;
696 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
697 goto bad;
698 }
717746e3 699 cpl = ctxt->ops->cpl(ctxt);
a5625189
AK		 700 if (ctxt->mode == X86EMUL_MODE_REAL)
701 rpl = 0;
702 else
703 rpl = sel & 3;
618ff15d
AK		 704 cpl = max(cpl, rpl);
705 if (!(desc.type & 8)) {
706 /* data segment */
707 if (cpl > desc.dpl)
708 goto bad;
709 } else if ((desc.type & 8) && !(desc.type & 4)) {
710 /* nonconforming code segment */
711 if (cpl != desc.dpl)
712 goto bad;
713 } else if ((desc.type & 8) && (desc.type & 4)) {
714 /* conforming code segment */
715 if (cpl < desc.dpl)
716 goto bad;
717 }
718 break;
719 }
9dac77fa 720 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 721 la &= (u32)-1;
1c11b376
AK		 722 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
723 return emulate_gp(ctxt, 0);
52fd8b44
AK		 724 *linear = la;
725 return X86EMUL_CONTINUE;
618ff15d
AK		 726bad:
727 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 728 return emulate_ss(ctxt, sel);
618ff15d 729 else
0afbe2f8 730 return emulate_gp(ctxt, sel);
52fd8b44
AK		 731}
732
3d9b938e
NE		 733static int linearize(struct x86_emulate_ctxt *ctxt,
734 struct segmented_address addr,
735 unsigned size, bool write,
736 ulong *linear)
737{
738 return __linearize(ctxt, addr, size, write, false, linear);
739}
740
741
3ca3ac4d
AK		 742static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
743 struct segmented_address addr,
744 void *data,
745 unsigned size)
746{
9fa088f4
AK		 747 int rc;
748 ulong linear;
749
83b8795a 750 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 751 if (rc != X86EMUL_CONTINUE)
752 return rc;
0f65dd70 753 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 754}
755
807941b1
TY		 756/*
757 * Fetch the next byte of the instruction being emulated which is pointed to
758 * by ctxt->_eip, then increment ctxt->_eip.
759 *
760 * Also prefetch the remaining bytes of the instruction without crossing page
761 * boundary if they are not in fetch_cache yet.
762 */
763static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 764{
9dac77fa 765 struct fetch_cache *fc = &ctxt->fetch;
62266869 766 int rc;
2fb53ad8 767 int size, cur_size;
62266869 768
807941b1 769 if (ctxt->_eip == fc->end) {
3d9b938e 770 unsigned long linear;
807941b1
TY		 771 struct segmented_address addr = { .seg = VCPU_SREG_CS,
772 .ea = ctxt->_eip };
2fb53ad8 773 cur_size = fc->end - fc->start;
807941b1
TY		 774 size = min(15UL - cur_size,
775 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 776 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 777 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 778 return rc;
ef5d75cc
TY		 779 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
780 size, &ctxt->exception);
7d88bb48 781 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 782 return rc;
2fb53ad8 783 fc->end += size;
62266869 784 }
807941b1
TY		 785 *dest = fc->data[ctxt->_eip - fc->start];
786 ctxt->_eip++;
3e2815e9 787 return X86EMUL_CONTINUE;
62266869
AK		 788}
789
790static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 791 void *dest, unsigned size)
62266869 792{
3e2815e9 793 int rc;
62266869 794
eb3c79e6 795 /* x86 instructions are limited to 15 bytes. */
7d88bb48 796 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 797 return X86EMUL_UNHANDLEABLE;
62266869 798 while (size--) {
807941b1 799 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 800 if (rc != X86EMUL_CONTINUE)
62266869
AK		 801 return rc;
802 }
3e2815e9 803 return X86EMUL_CONTINUE;
62266869
AK		 804}
805
67cbc90d 806/* Fetch next part of the instruction being emulated. */
e85a1085 807#define insn_fetch(_type, _ctxt) \
67cbc90d 808({ unsigned long _x; \
e85a1085 809 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 810 if (rc != X86EMUL_CONTINUE) \
811 goto done; \
67cbc90d
TY		 812 (_type)_x; \
813})
814
807941b1
TY		 815#define insn_fetch_arr(_arr, _size, _ctxt) \
816({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 817 if (rc != X86EMUL_CONTINUE) \
818 goto done; \
67cbc90d
TY		 819})
820
1e3c5cb0
RR		 821/*
822 * Given the 'reg' portion of a ModRM byte, and a register block, return a
823 * pointer into the block that addresses the relevant register.
824 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
825 */
dd856efa 826static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 827 int highbyte_regs)
6aa8b732
AK		 828{
829 void *p;
830
6aa8b732 831 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 832 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
833 else
834 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 835 return p;
836}
837
838static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 839 struct segmented_address addr,
6aa8b732
AK		 840 u16 *size, unsigned long *address, int op_bytes)
841{
842 int rc;
843
844 if (op_bytes == 2)
845 op_bytes = 3;
846 *address = 0;
3ca3ac4d 847 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 848 if (rc != X86EMUL_CONTINUE)
6aa8b732 849 return rc;
30b31ab6 850 addr.ea += 2;
3ca3ac4d 851 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 852 return rc;
853}
854
bbe9abbd
NK		 855static int test_cc(unsigned int condition, unsigned int flags)
856{
857 int rc = 0;
858
859 switch ((condition & 15) >> 1) {
860 case 0: /* o */
861 rc |= (flags & EFLG_OF);
862 break;
863 case 1: /* b/c/nae */
864 rc |= (flags & EFLG_CF);
865 break;
866 case 2: /* z/e */
867 rc |= (flags & EFLG_ZF);
868 break;
869 case 3: /* be/na */
870 rc |= (flags & (EFLG_CF|EFLG_ZF));
871 break;
872 case 4: /* s */
873 rc |= (flags & EFLG_SF);
874 break;
875 case 5: /* p/pe */
876 rc |= (flags & EFLG_PF);
877 break;
878 case 7: /* le/ng */
879 rc |= (flags & EFLG_ZF);
880 /* fall through */
881 case 6: /* l/nge */
882 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
883 break;
884 }
885
886 /* Odd condition identifiers (lsb == 1) have inverted sense. */
887 return (!!rc ^ (condition & 1));
888}
889
91ff3cb4
AK		 890static void fetch_register_operand(struct operand *op)
891{
892 switch (op->bytes) {
893 case 1:
894 op->val = *(u8 *)op->addr.reg;
895 break;
896 case 2:
897 op->val = *(u16 *)op->addr.reg;
898 break;
899 case 4:
900 op->val = *(u32 *)op->addr.reg;
901 break;
902 case 8:
903 op->val = *(u64 *)op->addr.reg;
904 break;
905 }
906}
907
1253791d
AK		 908static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
909{
910 ctxt->ops->get_fpu(ctxt);
911 switch (reg) {
89a87c67
MK		 912 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
913 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
914 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
915 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
916 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
917 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
918 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
919 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 920#ifdef CONFIG_X86_64
89a87c67
MK		 921 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
922 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
923 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
924 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
925 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
926 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
927 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
928 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 929#endif
930 default: BUG();
931 }
932 ctxt->ops->put_fpu(ctxt);
933}
934
935static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
936 int reg)
937{
938 ctxt->ops->get_fpu(ctxt);
939 switch (reg) {
89a87c67
MK		 940 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
941 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
942 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
943 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
944 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
945 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
946 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
947 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 948#ifdef CONFIG_X86_64
89a87c67
MK		 949 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
950 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
951 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
952 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
953 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
954 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
955 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
956 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 957#endif
958 default: BUG();
959 }
960 ctxt->ops->put_fpu(ctxt);
961}
962
cbe2c9d3
AK		 963static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
964{
965 ctxt->ops->get_fpu(ctxt);
966 switch (reg) {
967 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
968 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
969 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
970 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
971 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
972 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
973 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
974 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
975 default: BUG();
976 }
977 ctxt->ops->put_fpu(ctxt);
978}
979
980static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
981{
982 ctxt->ops->get_fpu(ctxt);
983 switch (reg) {
984 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
985 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
986 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
987 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
988 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
989 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
990 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
991 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
992 default: BUG();
993 }
994 ctxt->ops->put_fpu(ctxt);
995}
996
1253791d 997static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 998 struct operand *op)
3c118e24 999{
9dac77fa
AK		 1000 unsigned reg = ctxt->modrm_reg;
1001 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1002
9dac77fa
AK		 1003 if (!(ctxt->d & ModRM))
1004 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1005
9dac77fa 1006 if (ctxt->d & Sse) {
1253791d
AK		 1007 op->type = OP_XMM;
1008 op->bytes = 16;
1009 op->addr.xmm = reg;
1010 read_sse_reg(ctxt, &op->vec_val, reg);
1011 return;
1012 }
cbe2c9d3
AK		 1013 if (ctxt->d & Mmx) {
1014 reg &= 7;
1015 op->type = OP_MM;
1016 op->bytes = 8;
1017 op->addr.mm = reg;
1018 return;
1019 }
1253791d 1020
3c118e24 1021 op->type = OP_REG;
2adb5ad9 1022 if (ctxt->d & ByteOp) {
dd856efa 1023 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1024 op->bytes = 1;
1025 } else {
dd856efa 1026 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1027 op->bytes = ctxt->op_bytes;
3c118e24 1028 }
91ff3cb4 1029 fetch_register_operand(op);
3c118e24
AK		 1030 op->orig_val = op->val;
1031}
1032
a6e3407b
AK		 1033static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1034{
1035 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1036 ctxt->modrm_seg = VCPU_SREG_SS;
1037}
1038
1c73ef66 1039static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1040 struct operand *op)
1c73ef66 1041{
1c73ef66 1042 u8 sib;
f5b4edcd 1043 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1044 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1045 ulong modrm_ea = 0;
1c73ef66 1046
9dac77fa
AK		 1047 if (ctxt->rex_prefix) {
1048 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1049 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1050 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1051 }
1052
9dac77fa
AK		 1053 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1054 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1055 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1056 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1057
9dac77fa 1058 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1059 op->type = OP_REG;
9dac77fa 1060 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1061 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1062 if (ctxt->d & Sse) {
1253791d
AK		 1063 op->type = OP_XMM;
1064 op->bytes = 16;
9dac77fa
AK		 1065 op->addr.xmm = ctxt->modrm_rm;
1066 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1067 return rc;
1068 }
cbe2c9d3
AK		 1069 if (ctxt->d & Mmx) {
1070 op->type = OP_MM;
1071 op->bytes = 8;
1072 op->addr.xmm = ctxt->modrm_rm & 7;
1073 return rc;
1074 }
2dbd0dd7 1075 fetch_register_operand(op);
1c73ef66
AK		 1076 return rc;
1077 }
1078
2dbd0dd7
AK		 1079 op->type = OP_MEM;
1080
9dac77fa 1081 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1082 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1083 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1084 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1085 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1086
1087 /* 16-bit ModR/M decode. */
9dac77fa 1088 switch (ctxt->modrm_mod) {
1c73ef66 1089 case 0:
9dac77fa 1090 if (ctxt->modrm_rm == 6)
e85a1085 1091 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1092 break;
1093 case 1:
e85a1085 1094 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1095 break;
1096 case 2:
e85a1085 1097 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1098 break;
1099 }
9dac77fa 1100 switch (ctxt->modrm_rm) {
1c73ef66 1101 case 0:
2dbd0dd7 1102 modrm_ea += bx + si;
1c73ef66
AK		 1103 break;
1104 case 1:
2dbd0dd7 1105 modrm_ea += bx + di;
1c73ef66
AK		 1106 break;
1107 case 2:
2dbd0dd7 1108 modrm_ea += bp + si;
1c73ef66
AK		 1109 break;
1110 case 3:
2dbd0dd7 1111 modrm_ea += bp + di;
1c73ef66
AK		 1112 break;
1113 case 4:
2dbd0dd7 1114 modrm_ea += si;
1c73ef66
AK		 1115 break;
1116 case 5:
2dbd0dd7 1117 modrm_ea += di;
1c73ef66
AK		 1118 break;
1119 case 6:
9dac77fa 1120 if (ctxt->modrm_mod != 0)
2dbd0dd7 1121 modrm_ea += bp;
1c73ef66
AK		 1122 break;
1123 case 7:
2dbd0dd7 1124 modrm_ea += bx;
1c73ef66
AK		 1125 break;
1126 }
9dac77fa
AK		 1127 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1128 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1129 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1130 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1131 } else {
1132 /* 32/64-bit ModR/M decode. */
9dac77fa 1133 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1134 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1135 index_reg |= (sib >> 3) & 7;
1136 base_reg |= sib & 7;
1137 scale = sib >> 6;
1138
9dac77fa 1139 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1140 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1141 else {
dd856efa 1142 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1143 adjust_modrm_seg(ctxt, base_reg);
1144 }
dc71d0f1 1145 if (index_reg != 4)
dd856efa 1146 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1147 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1148 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1149 ctxt->rip_relative = 1;
a6e3407b
AK		 1150 } else {
1151 base_reg = ctxt->modrm_rm;
dd856efa 1152 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1153 adjust_modrm_seg(ctxt, base_reg);
1154 }
9dac77fa 1155 switch (ctxt->modrm_mod) {
1c73ef66 1156 case 0:
9dac77fa 1157 if (ctxt->modrm_rm == 5)
e85a1085 1158 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1159 break;
1160 case 1:
e85a1085 1161 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1162 break;
1163 case 2:
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1165 break;
1166 }
1167 }
90de84f5 1168 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1169done:
1170 return rc;
1171}
1172
1173static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1174 struct operand *op)
1c73ef66 1175{
3e2815e9 1176 int rc = X86EMUL_CONTINUE;
1c73ef66 1177
2dbd0dd7 1178 op->type = OP_MEM;
9dac77fa 1179 switch (ctxt->ad_bytes) {
1c73ef66 1180 case 2:
e85a1085 1181 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1182 break;
1183 case 4:
e85a1085 1184 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1185 break;
1186 case 8:
e85a1085 1187 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1188 break;
1189 }
1190done:
1191 return rc;
1192}
1193
9dac77fa 1194static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1195{
7129eeca 1196 long sv = 0, mask;
35c843c4 1197
9dac77fa
AK		 1198 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1199 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1200
9dac77fa
AK		 1201 if (ctxt->src.bytes == 2)
1202 sv = (s16)ctxt->src.val & (s16)mask;
1203 else if (ctxt->src.bytes == 4)
1204 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1205
9dac77fa 1206 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1207 }
ba7ff2b7
WY		 1208
1209 /* only subword offset */
9dac77fa 1210 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1211}
1212
dde7e6d1 1213static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1214 unsigned long addr, void *dest, unsigned size)
6aa8b732 1215{
dde7e6d1 1216 int rc;
9dac77fa 1217 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1218
f23b070e
XG		 1219 if (mc->pos < mc->end)
1220 goto read_cached;
6aa8b732 1221
f23b070e
XG		 1222 WARN_ON((mc->end + size) >= sizeof(mc->data));
1223
1224 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1225 &ctxt->exception);
1226 if (rc != X86EMUL_CONTINUE)
1227 return rc;
1228
1229 mc->end += size;
1230
1231read_cached:
1232 memcpy(dest, mc->data + mc->pos, size);
1233 mc->pos += size;
dde7e6d1
AK		 1234 return X86EMUL_CONTINUE;
1235}
6aa8b732 1236
3ca3ac4d
AK		 1237static int segmented_read(struct x86_emulate_ctxt *ctxt,
1238 struct segmented_address addr,
1239 void *data,
1240 unsigned size)
1241{
9fa088f4
AK		 1242 int rc;
1243 ulong linear;
1244
83b8795a 1245 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1246 if (rc != X86EMUL_CONTINUE)
1247 return rc;
7b105ca2 1248 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1249}
1250
1251static int segmented_write(struct x86_emulate_ctxt *ctxt,
1252 struct segmented_address addr,
1253 const void *data,
1254 unsigned size)
1255{
9fa088f4
AK		 1256 int rc;
1257 ulong linear;
1258
83b8795a 1259 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1260 if (rc != X86EMUL_CONTINUE)
1261 return rc;
0f65dd70
AK		 1262 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1263 &ctxt->exception);
3ca3ac4d
AK		 1264}
1265
1266static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1267 struct segmented_address addr,
1268 const void *orig_data, const void *data,
1269 unsigned size)
1270{
9fa088f4
AK		 1271 int rc;
1272 ulong linear;
1273
83b8795a 1274 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
0f65dd70
AK		 1277 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1278 size, &ctxt->exception);
3ca3ac4d
AK		 1279}
1280
dde7e6d1 1281static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1282 unsigned int size, unsigned short port,
1283 void *dest)
1284{
9dac77fa 1285 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1286
dde7e6d1 1287 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1288 unsigned int in_page, n;
9dac77fa 1289 unsigned int count = ctxt->rep_prefix ?
dd856efa 1290 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1291 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1292 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1293 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1294 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1295 count);
1296 if (n == 0)
1297 n = 1;
1298 rc->pos = rc->end = 0;
7b105ca2 1299 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1300 return 0;
1301 rc->end = n * size;
6aa8b732
AK		 1302 }
1303
b3356bf0
GN		 1304 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1305 ctxt->dst.data = rc->data + rc->pos;
1306 ctxt->dst.type = OP_MEM_STR;
1307 ctxt->dst.count = (rc->end - rc->pos) / size;
1308 rc->pos = rc->end;
1309 } else {
1310 memcpy(dest, rc->data + rc->pos, size);
1311 rc->pos += size;
1312 }
dde7e6d1
AK		 1313 return 1;
1314}
6aa8b732 1315
7f3d35fd
KW		 1316static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1317 u16 index, struct desc_struct *desc)
1318{
1319 struct desc_ptr dt;
1320 ulong addr;
1321
1322 ctxt->ops->get_idt(ctxt, &dt);
1323
1324 if (dt.size < index * 8 + 7)
1325 return emulate_gp(ctxt, index << 3 | 0x2);
1326
1327 addr = dt.address + index * 8;
1328 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1329 &ctxt->exception);
1330}
1331
dde7e6d1 1332static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1333 u16 selector, struct desc_ptr *dt)
1334{
0225fb50 1335 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1336
dde7e6d1
AK		 1337 if (selector & 1 << 2) {
1338 struct desc_struct desc;
1aa36616
AK		 1339 u16 sel;
1340
dde7e6d1 1341 memset (dt, 0, sizeof *dt);
1aa36616 1342 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1343 return;
e09d082c 1344
dde7e6d1
AK		 1345 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1346 dt->address = get_desc_base(&desc);
1347 } else
4bff1e86 1348 ops->get_gdt(ctxt, dt);
dde7e6d1 1349}
120df890 1350
dde7e6d1
AK		 1351/* allowed just for 8 bytes segments */
1352static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1353 u16 selector, struct desc_struct *desc,
1354 ulong *desc_addr_p)
dde7e6d1
AK		 1355{
1356 struct desc_ptr dt;
1357 u16 index = selector >> 3;
dde7e6d1 1358 ulong addr;
120df890 1359
7b105ca2 1360 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1361
35d3d4a1
AK		 1362 if (dt.size < index * 8 + 7)
1363 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1364
e919464b 1365 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1366 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1367 &ctxt->exception);
dde7e6d1 1368}
ef65c889 1369
dde7e6d1
AK		 1370/* allowed just for 8 bytes segments */
1371static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1372 u16 selector, struct desc_struct *desc)
1373{
1374 struct desc_ptr dt;
1375 u16 index = selector >> 3;
dde7e6d1 1376 ulong addr;
6aa8b732 1377
7b105ca2 1378 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1379
35d3d4a1
AK		 1380 if (dt.size < index * 8 + 7)
1381 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1382
dde7e6d1 1383 addr = dt.address + index * 8;
7b105ca2
TY		 1384 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1385 &ctxt->exception);
dde7e6d1 1386}
c7e75a3d 1387
5601d05b 1388/* Does not support long mode */
dde7e6d1 1389static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1390 u16 selector, int seg)
1391{
869be99c 1392 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1393 u8 dpl, rpl, cpl;
1394 unsigned err_vec = GP_VECTOR;
1395 u32 err_code = 0;
1396 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1397 ulong desc_addr;
dde7e6d1 1398 int ret;
03ebebeb 1399 u16 dummy;
69f55cb1 1400
dde7e6d1 1401 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1402
dde7e6d1
AK		 1403 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1404 || ctxt->mode == X86EMUL_MODE_REAL) {
1405 /* set real mode segment descriptor */
03ebebeb 1406 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1407 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1408 goto load;
1409 }
1410
79d5b4c3
AK		 1411 rpl = selector & 3;
1412 cpl = ctxt->ops->cpl(ctxt);
1413
1414 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1415 if ((seg == VCPU_SREG_CS
1416 || (seg == VCPU_SREG_SS
1417 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1418 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1419 && null_selector)
1420 goto exception;
1421
1422 /* TR should be in GDT only */
1423 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1424 goto exception;
1425
1426 if (null_selector) /* for NULL selector skip all following checks */
1427 goto load;
1428
e919464b 1429 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1430 if (ret != X86EMUL_CONTINUE)
1431 return ret;
1432
1433 err_code = selector & 0xfffc;
1434 err_vec = GP_VECTOR;
1435
fc058680 1436 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1437 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1438 goto exception;
1439
1440 if (!seg_desc.p) {
1441 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1442 goto exception;
1443 }
1444
dde7e6d1 1445 dpl = seg_desc.dpl;
dde7e6d1
AK		 1446
1447 switch (seg) {
1448 case VCPU_SREG_SS:
1449 /*
1450 * segment is not a writable data segment or segment
1451 * selector's RPL != CPL or segment selector's RPL != CPL
1452 */
1453 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1454 goto exception;
6aa8b732 1455 break;
dde7e6d1
AK		 1456 case VCPU_SREG_CS:
1457 if (!(seg_desc.type & 8))
1458 goto exception;
1459
1460 if (seg_desc.type & 4) {
1461 /* conforming */
1462 if (dpl > cpl)
1463 goto exception;
1464 } else {
1465 /* nonconforming */
1466 if (rpl > cpl || dpl != cpl)
1467 goto exception;
1468 }
1469 /* CS(RPL) <- CPL */
1470 selector = (selector & 0xfffc) | cpl;
6aa8b732 1471 break;
dde7e6d1
AK		 1472 case VCPU_SREG_TR:
1473 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1474 goto exception;
869be99c
AK		 1475 old_desc = seg_desc;
1476 seg_desc.type |= 2; /* busy */
1477 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1478 sizeof(seg_desc), &ctxt->exception);
1479 if (ret != X86EMUL_CONTINUE)
1480 return ret;
dde7e6d1
AK		 1481 break;
1482 case VCPU_SREG_LDTR:
1483 if (seg_desc.s || seg_desc.type != 2)
1484 goto exception;
1485 break;
1486 default: /* DS, ES, FS, or GS */
4e62417b 1487 /*
dde7e6d1
AK		 1488 * segment is not a data or readable code segment or
1489 * ((segment is a data or nonconforming code segment)
1490 * and (both RPL and CPL > DPL))
4e62417b 1491 */
dde7e6d1
AK		 1492 if ((seg_desc.type & 0xa) == 0x8 ||
1493 (((seg_desc.type & 0xc) != 0xc) &&
1494 (rpl > dpl && cpl > dpl)))
1495 goto exception;
6aa8b732 1496 break;
dde7e6d1
AK		 1497 }
1498
1499 if (seg_desc.s) {
1500 /* mark segment as accessed */
1501 seg_desc.type |= 1;
7b105ca2 1502 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1503 if (ret != X86EMUL_CONTINUE)
1504 return ret;
1505 }
1506load:
7b105ca2 1507 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1508 return X86EMUL_CONTINUE;
1509exception:
1510 emulate_exception(ctxt, err_vec, err_code, true);
1511 return X86EMUL_PROPAGATE_FAULT;
1512}
1513
31be40b3
WY		 1514static void write_register_operand(struct operand *op)
1515{
1516 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1517 switch (op->bytes) {
1518 case 1:
1519 *(u8 *)op->addr.reg = (u8)op->val;
1520 break;
1521 case 2:
1522 *(u16 *)op->addr.reg = (u16)op->val;
1523 break;
1524 case 4:
1525 *op->addr.reg = (u32)op->val;
1526 break; /* 64b: zero-extend */
1527 case 8:
1528 *op->addr.reg = op->val;
1529 break;
1530 }
1531}
1532
adddcecf 1533static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1534{
1535 int rc;
dde7e6d1 1536
9dac77fa 1537 switch (ctxt->dst.type) {
dde7e6d1 1538 case OP_REG:
9dac77fa 1539 write_register_operand(&ctxt->dst);
6aa8b732 1540 break;
dde7e6d1 1541 case OP_MEM:
9dac77fa 1542 if (ctxt->lock_prefix)
3ca3ac4d 1543 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1544 ctxt->dst.addr.mem,
1545 &ctxt->dst.orig_val,
1546 &ctxt->dst.val,
1547 ctxt->dst.bytes);
341de7e3 1548 else
3ca3ac4d 1549 rc = segmented_write(ctxt,
9dac77fa
AK		 1550 ctxt->dst.addr.mem,
1551 &ctxt->dst.val,
1552 ctxt->dst.bytes);
dde7e6d1
AK		 1553 if (rc != X86EMUL_CONTINUE)
1554 return rc;
a682e354 1555 break;
b3356bf0
GN		 1556 case OP_MEM_STR:
1557 rc = segmented_write(ctxt,
1558 ctxt->dst.addr.mem,
1559 ctxt->dst.data,
1560 ctxt->dst.bytes * ctxt->dst.count);
1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
1563 break;
1253791d 1564 case OP_XMM:
9dac77fa 1565 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1566 break;
cbe2c9d3
AK		 1567 case OP_MM:
1568 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1569 break;
dde7e6d1
AK		 1570 case OP_NONE:
1571 /* no writeback */
414e6277 1572 break;
dde7e6d1 1573 default:
414e6277 1574 break;
6aa8b732 1575 }
dde7e6d1
AK		 1576 return X86EMUL_CONTINUE;
1577}
6aa8b732 1578
51ddff50 1579static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1580{
4179bb02 1581 struct segmented_address addr;
0dc8d10f 1582
5ad105e5 1583 rsp_increment(ctxt, -bytes);
dd856efa 1584 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1585 addr.seg = VCPU_SREG_SS;
1586
51ddff50
AK		 1587 return segmented_write(ctxt, addr, data, bytes);
1588}
1589
1590static int em_push(struct x86_emulate_ctxt *ctxt)
1591{
4179bb02 1592 /* Disable writeback. */
9dac77fa 1593 ctxt->dst.type = OP_NONE;
51ddff50 1594 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1595}
69f55cb1 1596
dde7e6d1 1597static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1598 void *dest, int len)
1599{
dde7e6d1 1600 int rc;
90de84f5 1601 struct segmented_address addr;
8b4caf66 1602
dd856efa 1603 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1604 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1605 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1606 if (rc != X86EMUL_CONTINUE)
1607 return rc;
1608
5ad105e5 1609 rsp_increment(ctxt, len);
dde7e6d1 1610 return rc;
8b4caf66
LV		 1611}
1612
c54fe504
TY		 1613static int em_pop(struct x86_emulate_ctxt *ctxt)
1614{
9dac77fa 1615 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1616}
1617
dde7e6d1 1618static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1619 void *dest, int len)
9de41573
GN		 1620{
1621 int rc;
dde7e6d1
AK		 1622 unsigned long val, change_mask;
1623 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1624 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1625
3b9be3bf 1626 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1627 if (rc != X86EMUL_CONTINUE)
1628 return rc;
9de41573 1629
dde7e6d1
AK		 1630 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1631 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1632
dde7e6d1
AK		 1633 switch(ctxt->mode) {
1634 case X86EMUL_MODE_PROT64:
1635 case X86EMUL_MODE_PROT32:
1636 case X86EMUL_MODE_PROT16:
1637 if (cpl == 0)
1638 change_mask |= EFLG_IOPL;
1639 if (cpl <= iopl)
1640 change_mask |= EFLG_IF;
1641 break;
1642 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1643 if (iopl < 3)
1644 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1645 change_mask |= EFLG_IF;
1646 break;
1647 default: /* real mode */
1648 change_mask |= (EFLG_IOPL | EFLG_IF);
1649 break;
9de41573 1650 }
dde7e6d1
AK		 1651
1652 *(unsigned long *)dest =
1653 (ctxt->eflags & ~change_mask) | (val & change_mask);
1654
1655 return rc;
9de41573
GN		 1656}
1657
62aaa2f0
TY		 1658static int em_popf(struct x86_emulate_ctxt *ctxt)
1659{
9dac77fa
AK		 1660 ctxt->dst.type = OP_REG;
1661 ctxt->dst.addr.reg = &ctxt->eflags;
1662 ctxt->dst.bytes = ctxt->op_bytes;
1663 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1664}
1665
612e89f0
AK		 1666static int em_enter(struct x86_emulate_ctxt *ctxt)
1667{
1668 int rc;
1669 unsigned frame_size = ctxt->src.val;
1670 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1671 ulong rbp;
612e89f0
AK		 1672
1673 if (nesting_level)
1674 return X86EMUL_UNHANDLEABLE;
1675
dd856efa
AK		 1676 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1677 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1678 if (rc != X86EMUL_CONTINUE)
1679 return rc;
dd856efa 1680 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1681 stack_mask(ctxt));
dd856efa
AK		 1682 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1683 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1684 stack_mask(ctxt));
1685 return X86EMUL_CONTINUE;
1686}
1687
f47cfa31
AK		 1688static int em_leave(struct x86_emulate_ctxt *ctxt)
1689{
dd856efa 1690 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1691 stack_mask(ctxt));
dd856efa 1692 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1693}
1694
1cd196ea 1695static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1696{
1cd196ea
AK		 1697 int seg = ctxt->src2.val;
1698
9dac77fa 1699 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1700
4487b3b4 1701 return em_push(ctxt);
7b262e90
GN		 1702}
1703
1cd196ea 1704static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1705{
1cd196ea 1706 int seg = ctxt->src2.val;
dde7e6d1
AK		 1707 unsigned long selector;
1708 int rc;
38ba30ba 1709
9dac77fa 1710 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1711 if (rc != X86EMUL_CONTINUE)
1712 return rc;
1713
7b105ca2 1714 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1715 return rc;
38ba30ba
GN		 1716}
1717
b96a7fad 1718static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1719{
dd856efa 1720 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1721 int rc = X86EMUL_CONTINUE;
1722 int reg = VCPU_REGS_RAX;
38ba30ba 1723
dde7e6d1
AK		 1724 while (reg <= VCPU_REGS_RDI) {
1725 (reg == VCPU_REGS_RSP) ?
dd856efa 1726 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1727
4487b3b4 1728 rc = em_push(ctxt);
dde7e6d1
AK		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
38ba30ba 1731
dde7e6d1 1732 ++reg;
38ba30ba 1733 }
38ba30ba 1734
dde7e6d1 1735 return rc;
38ba30ba
GN		 1736}
1737
62aaa2f0
TY		 1738static int em_pushf(struct x86_emulate_ctxt *ctxt)
1739{
9dac77fa 1740 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1741 return em_push(ctxt);
1742}
1743
b96a7fad 1744static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1745{
dde7e6d1
AK		 1746 int rc = X86EMUL_CONTINUE;
1747 int reg = VCPU_REGS_RDI;
38ba30ba 1748
dde7e6d1
AK		 1749 while (reg >= VCPU_REGS_RAX) {
1750 if (reg == VCPU_REGS_RSP) {
5ad105e5 1751 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1752 --reg;
1753 }
38ba30ba 1754
dd856efa 1755 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1756 if (rc != X86EMUL_CONTINUE)
1757 break;
1758 --reg;
38ba30ba 1759 }
dde7e6d1 1760 return rc;
38ba30ba
GN		 1761}
1762
dd856efa 1763static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1764{
0225fb50 1765 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1766 int rc;
6e154e56
MG		 1767 struct desc_ptr dt;
1768 gva_t cs_addr;
1769 gva_t eip_addr;
1770 u16 cs, eip;
6e154e56
MG		 1771
1772 /* TODO: Add limit checks */
9dac77fa 1773 ctxt->src.val = ctxt->eflags;
4487b3b4 1774 rc = em_push(ctxt);
5c56e1cf
AK		 1775 if (rc != X86EMUL_CONTINUE)
1776 return rc;
6e154e56
MG		 1777
1778 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1779
9dac77fa 1780 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1781 rc = em_push(ctxt);
5c56e1cf
AK		 1782 if (rc != X86EMUL_CONTINUE)
1783 return rc;
6e154e56 1784
9dac77fa 1785 ctxt->src.val = ctxt->_eip;
4487b3b4 1786 rc = em_push(ctxt);
5c56e1cf
AK		 1787 if (rc != X86EMUL_CONTINUE)
1788 return rc;
1789
4bff1e86 1790 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1791
1792 eip_addr = dt.address + (irq << 2);
1793 cs_addr = dt.address + (irq << 2) + 2;
1794
0f65dd70 1795 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1796 if (rc != X86EMUL_CONTINUE)
1797 return rc;
1798
0f65dd70 1799 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1800 if (rc != X86EMUL_CONTINUE)
1801 return rc;
1802
7b105ca2 1803 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1804 if (rc != X86EMUL_CONTINUE)
1805 return rc;
1806
9dac77fa 1807 ctxt->_eip = eip;
6e154e56
MG		 1808
1809 return rc;
1810}
1811
dd856efa
AK		 1812int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1813{
1814 int rc;
1815
1816 invalidate_registers(ctxt);
1817 rc = __emulate_int_real(ctxt, irq);
1818 if (rc == X86EMUL_CONTINUE)
1819 writeback_registers(ctxt);
1820 return rc;
1821}
1822
7b105ca2 1823static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1824{
1825 switch(ctxt->mode) {
1826 case X86EMUL_MODE_REAL:
dd856efa 1827 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1828 case X86EMUL_MODE_VM86:
1829 case X86EMUL_MODE_PROT16:
1830 case X86EMUL_MODE_PROT32:
1831 case X86EMUL_MODE_PROT64:
1832 default:
1833 /* Protected mode interrupts unimplemented yet */
1834 return X86EMUL_UNHANDLEABLE;
1835 }
1836}
1837
7b105ca2 1838static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1839{
dde7e6d1
AK		 1840 int rc = X86EMUL_CONTINUE;
1841 unsigned long temp_eip = 0;
1842 unsigned long temp_eflags = 0;
1843 unsigned long cs = 0;
1844 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1845 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1846 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1847 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1848
dde7e6d1 1849 /* TODO: Add stack limit check */
38ba30ba 1850
9dac77fa 1851 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1852
dde7e6d1
AK		 1853 if (rc != X86EMUL_CONTINUE)
1854 return rc;
38ba30ba 1855
35d3d4a1
AK		 1856 if (temp_eip & ~0xffff)
1857 return emulate_gp(ctxt, 0);
38ba30ba 1858
9dac77fa 1859 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1860
dde7e6d1
AK		 1861 if (rc != X86EMUL_CONTINUE)
1862 return rc;
38ba30ba 1863
9dac77fa 1864 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1865
dde7e6d1
AK		 1866 if (rc != X86EMUL_CONTINUE)
1867 return rc;
38ba30ba 1868
7b105ca2 1869 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1870
dde7e6d1
AK		 1871 if (rc != X86EMUL_CONTINUE)
1872 return rc;
38ba30ba 1873
9dac77fa 1874 ctxt->_eip = temp_eip;
38ba30ba 1875
38ba30ba 1876
9dac77fa 1877 if (ctxt->op_bytes == 4)
dde7e6d1 1878 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1879 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1880 ctxt->eflags &= ~0xffff;
1881 ctxt->eflags |= temp_eflags;
38ba30ba 1882 }
dde7e6d1
AK		 1883
1884 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1885 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1886
1887 return rc;
38ba30ba
GN		 1888}
1889
e01991e7 1890static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1891{
dde7e6d1
AK		 1892 switch(ctxt->mode) {
1893 case X86EMUL_MODE_REAL:
7b105ca2 1894 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1895 case X86EMUL_MODE_VM86:
1896 case X86EMUL_MODE_PROT16:
1897 case X86EMUL_MODE_PROT32:
1898 case X86EMUL_MODE_PROT64:
c37eda13 1899 default:
dde7e6d1
AK		 1900 /* iret from protected mode unimplemented yet */
1901 return X86EMUL_UNHANDLEABLE;
c37eda13 1902 }
c37eda13
WY		 1903}
1904
d2f62766
TY		 1905static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1906{
d2f62766
TY		 1907 int rc;
1908 unsigned short sel;
1909
9dac77fa 1910 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1911
7b105ca2 1912 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1913 if (rc != X86EMUL_CONTINUE)
1914 return rc;
1915
9dac77fa
AK		 1916 ctxt->_eip = 0;
1917 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1918 return X86EMUL_CONTINUE;
1919}
1920
51187683 1921static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1922{
9dac77fa 1923 switch (ctxt->modrm_reg) {
8cdbd2c9 1924 case 0: /* rol */
a31b9cea 1925 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1926 break;
1927 case 1: /* ror */
a31b9cea 1928 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1929 break;
1930 case 2: /* rcl */
a31b9cea 1931 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1932 break;
1933 case 3: /* rcr */
a31b9cea 1934 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1935 break;
1936 case 4: /* sal/shl */
1937 case 6: /* sal/shl */
a31b9cea 1938 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1939 break;
1940 case 5: /* shr */
a31b9cea 1941 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1942 break;
1943 case 7: /* sar */
a31b9cea 1944 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1945 break;
1946 }
51187683 1947 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1948}
1949
3329ece1
AK		 1950static int em_not(struct x86_emulate_ctxt *ctxt)
1951{
1952 ctxt->dst.val = ~ctxt->dst.val;
1953 return X86EMUL_CONTINUE;
1954}
1955
1956static int em_neg(struct x86_emulate_ctxt *ctxt)
1957{
1958 emulate_1op(ctxt, "neg");
1959 return X86EMUL_CONTINUE;
1960}
1961
1962static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1963{
1964 u8 ex = 0;
1965
1966 emulate_1op_rax_rdx(ctxt, "mul", ex);
1967 return X86EMUL_CONTINUE;
1968}
1969
1970static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1971{
1972 u8 ex = 0;
1973
1974 emulate_1op_rax_rdx(ctxt, "imul", ex);
1975 return X86EMUL_CONTINUE;
1976}
1977
1978static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1979{
34d1f490 1980 u8 de = 0;
8cdbd2c9 1981
3329ece1
AK		 1982 emulate_1op_rax_rdx(ctxt, "div", de);
1983 if (de)
1984 return emulate_de(ctxt);
1985 return X86EMUL_CONTINUE;
1986}
1987
1988static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1989{
1990 u8 de = 0;
1991
1992 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1993 if (de)
1994 return emulate_de(ctxt);
8c5eee30 1995 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1996}
1997
51187683 1998static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1999{
4179bb02 2000 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2001
9dac77fa 2002 switch (ctxt->modrm_reg) {
8cdbd2c9 2003 case 0: /* inc */
d1eef45d 2004 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2005 break;
2006 case 1: /* dec */
d1eef45d 2007 emulate_1op(ctxt, "dec");
8cdbd2c9 2008 break;
d19292e4
MG		 2009 case 2: /* call near abs */ {
2010 long int old_eip;
9dac77fa
AK		 2011 old_eip = ctxt->_eip;
2012 ctxt->_eip = ctxt->src.val;
2013 ctxt->src.val = old_eip;
4487b3b4 2014 rc = em_push(ctxt);
d19292e4
MG		 2015 break;
2016 }
8cdbd2c9 2017 case 4: /* jmp abs */
9dac77fa 2018 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2019 break;
d2f62766
TY		 2020 case 5: /* jmp far */
2021 rc = em_jmp_far(ctxt);
2022 break;
8cdbd2c9 2023 case 6: /* push */
4487b3b4 2024 rc = em_push(ctxt);
8cdbd2c9 2025 break;
8cdbd2c9 2026 }
4179bb02 2027 return rc;
8cdbd2c9
LV		 2028}
2029
e0dac408 2030static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2031{
9dac77fa 2032 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2033
dd856efa
AK		 2034 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2035 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2036 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2037 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2038 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2039 } else {
dd856efa
AK		 2040 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2041 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2042
05f086f8 2043 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2044 }
1b30eaa8 2045 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2046}
2047
ebda02c2
TY		 2048static int em_ret(struct x86_emulate_ctxt *ctxt)
2049{
9dac77fa
AK		 2050 ctxt->dst.type = OP_REG;
2051 ctxt->dst.addr.reg = &ctxt->_eip;
2052 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2053 return em_pop(ctxt);
2054}
2055
e01991e7 2056static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2057{
a77ab5ea
AK		 2058 int rc;
2059 unsigned long cs;
2060
9dac77fa 2061 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2062 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2063 return rc;
9dac77fa
AK		 2064 if (ctxt->op_bytes == 4)
2065 ctxt->_eip = (u32)ctxt->_eip;
2066 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2067 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2068 return rc;
7b105ca2 2069 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2070 return rc;
2071}
2072
e940b5c2
TY		 2073static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2074{
2075 /* Save real source value, then compare EAX against destination. */
2076 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2077 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2078 emulate_2op_SrcV(ctxt, "cmp");
2079
2080 if (ctxt->eflags & EFLG_ZF) {
2081 /* Success: write back to memory. */
2082 ctxt->dst.val = ctxt->src.orig_val;
2083 } else {
2084 /* Failure: write the value we saw to EAX. */
2085 ctxt->dst.type = OP_REG;
dd856efa 2086 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2087 }
2088 return X86EMUL_CONTINUE;
2089}
2090
d4b4325f 2091static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2092{
d4b4325f 2093 int seg = ctxt->src2.val;
09b5f4d3
WY		 2094 unsigned short sel;
2095 int rc;
2096
9dac77fa 2097 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2098
7b105ca2 2099 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2100 if (rc != X86EMUL_CONTINUE)
2101 return rc;
2102
9dac77fa 2103 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2104 return rc;
2105}
2106
7b105ca2 2107static void
e66bb2cc 2108setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2109 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2110{
e66bb2cc 2111 cs->l = 0; /* will be adjusted later */
79168fd1 2112 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2113 cs->g = 1; /* 4kb granularity */
79168fd1 2114 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2115 cs->type = 0x0b; /* Read, Execute, Accessed */
2116 cs->s = 1;
2117 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2118 cs->p = 1;
2119 cs->d = 1;
99245b50 2120 cs->avl = 0;
e66bb2cc 2121
79168fd1
GN		 2122 set_desc_base(ss, 0); /* flat segment */
2123 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2124 ss->g = 1; /* 4kb granularity */
2125 ss->s = 1;
2126 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2127 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2128 ss->dpl = 0;
79168fd1 2129 ss->p = 1;
99245b50
GN		 2130 ss->l = 0;
2131 ss->avl = 0;
e66bb2cc
AP		 2132}
2133
1a18a69b
AK		 2134static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2135{
2136 u32 eax, ebx, ecx, edx;
2137
2138 eax = ecx = 0;
0017f93a
AK		 2139 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2140 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2141 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2142 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2143}
2144
c2226fc9
SB		 2145static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2146{
0225fb50 2147 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2148 u32 eax, ebx, ecx, edx;
2149
2150 /*
2151 * syscall should always be enabled in longmode - so only become
2152 * vendor specific (cpuid) if other modes are active...
2153 */
2154 if (ctxt->mode == X86EMUL_MODE_PROT64)
2155 return true;
2156
2157 eax = 0x00000000;
2158 ecx = 0x00000000;
0017f93a
AK		 2159 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2160 /*
2161 * Intel ("GenuineIntel")
2162 * remark: Intel CPUs only support "syscall" in 64bit
2163 * longmode. Also an 64bit guest with a
2164 * 32bit compat-app running will #UD !! While this
2165 * behaviour can be fixed (by emulating) into AMD
2166 * response - CPUs of AMD can't behave like Intel.
2167 */
2168 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2169 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2170 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2171 return false;
2172
2173 /* AMD ("AuthenticAMD") */
2174 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2175 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2176 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2177 return true;
2178
2179 /* AMD ("AMDisbetter!") */
2180 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2181 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2182 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2183 return true;
c2226fc9
SB		 2184
2185 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2186 return false;
2187}
2188
e01991e7 2189static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2190{
0225fb50 2191 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2192 struct desc_struct cs, ss;
e66bb2cc 2193 u64 msr_data;
79168fd1 2194 u16 cs_sel, ss_sel;
c2ad2bb3 2195 u64 efer = 0;
e66bb2cc
AP		 2196
2197 /* syscall is not available in real mode */
2e901c4c 2198 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2199 ctxt->mode == X86EMUL_MODE_VM86)
2200 return emulate_ud(ctxt);
e66bb2cc 2201
c2226fc9
SB		 2202 if (!(em_syscall_is_enabled(ctxt)))
2203 return emulate_ud(ctxt);
2204
c2ad2bb3 2205 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2206 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2207
c2226fc9
SB		 2208 if (!(efer & EFER_SCE))
2209 return emulate_ud(ctxt);
2210
717746e3 2211 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2212 msr_data >>= 32;
79168fd1
GN		 2213 cs_sel = (u16)(msr_data & 0xfffc);
2214 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2215
c2ad2bb3 2216 if (efer & EFER_LMA) {
79168fd1 2217 cs.d = 0;
e66bb2cc
AP		 2218 cs.l = 1;
2219 }
1aa36616
AK		 2220 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2221 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2222
dd856efa 2223 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2224 if (efer & EFER_LMA) {
e66bb2cc 2225#ifdef CONFIG_X86_64
dd856efa 2226 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2227
717746e3 2228 ops->get_msr(ctxt,
3fb1b5db
GN		 2229 ctxt->mode == X86EMUL_MODE_PROT64 ?
2230 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2231 ctxt->_eip = msr_data;
e66bb2cc 2232
717746e3 2233 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2234 ctxt->eflags &= ~(msr_data | EFLG_RF);
2235#endif
2236 } else {
2237 /* legacy mode */
717746e3 2238 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2239 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2240
2241 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2242 }
2243
e54cfa97 2244 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2245}
2246
e01991e7 2247static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2248{
0225fb50 2249 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2250 struct desc_struct cs, ss;
8c604352 2251 u64 msr_data;
79168fd1 2252 u16 cs_sel, ss_sel;
c2ad2bb3 2253 u64 efer = 0;
8c604352 2254
7b105ca2 2255 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2256 /* inject #GP if in real mode */
35d3d4a1
AK		 2257 if (ctxt->mode == X86EMUL_MODE_REAL)
2258 return emulate_gp(ctxt, 0);
8c604352 2259
1a18a69b
AK		 2260 /*
2261 * Not recognized on AMD in compat mode (but is recognized in legacy
2262 * mode).
2263 */
2264 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2265 && !vendor_intel(ctxt))
2266 return emulate_ud(ctxt);
2267
8c604352
AP		 2268 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2269 * Therefore, we inject an #UD.
2270 */
35d3d4a1
AK		 2271 if (ctxt->mode == X86EMUL_MODE_PROT64)
2272 return emulate_ud(ctxt);
8c604352 2273
7b105ca2 2274 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2275
717746e3 2276 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2277 switch (ctxt->mode) {
2278 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2279 if ((msr_data & 0xfffc) == 0x0)
2280 return emulate_gp(ctxt, 0);
8c604352
AP		 2281 break;
2282 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2283 if (msr_data == 0x0)
2284 return emulate_gp(ctxt, 0);
8c604352 2285 break;
9d1b39a9
GN		 2286 default:
2287 break;
8c604352
AP		 2288 }
2289
2290 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2291 cs_sel = (u16)msr_data;
2292 cs_sel &= ~SELECTOR_RPL_MASK;
2293 ss_sel = cs_sel + 8;
2294 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2295 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2296 cs.d = 0;
8c604352
AP		 2297 cs.l = 1;
2298 }
2299
1aa36616
AK		 2300 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2301 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2302
717746e3 2303 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2304 ctxt->_eip = msr_data;
8c604352 2305
717746e3 2306 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2307 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2308
e54cfa97 2309 return X86EMUL_CONTINUE;
8c604352
AP		 2310}
2311
e01991e7 2312static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2313{
0225fb50 2314 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2315 struct desc_struct cs, ss;
4668f050
AP		 2316 u64 msr_data;
2317 int usermode;
1249b96e 2318 u16 cs_sel = 0, ss_sel = 0;
4668f050 2319
a0044755
GN		 2320 /* inject #GP if in real mode or Virtual 8086 mode */
2321 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2322 ctxt->mode == X86EMUL_MODE_VM86)
2323 return emulate_gp(ctxt, 0);
4668f050 2324
7b105ca2 2325 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2326
9dac77fa 2327 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2328 usermode = X86EMUL_MODE_PROT64;
2329 else
2330 usermode = X86EMUL_MODE_PROT32;
2331
2332 cs.dpl = 3;
2333 ss.dpl = 3;
717746e3 2334 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2335 switch (usermode) {
2336 case X86EMUL_MODE_PROT32:
79168fd1 2337 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2338 if ((msr_data & 0xfffc) == 0x0)
2339 return emulate_gp(ctxt, 0);
79168fd1 2340 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2341 break;
2342 case X86EMUL_MODE_PROT64:
79168fd1 2343 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2344 if (msr_data == 0x0)
2345 return emulate_gp(ctxt, 0);
79168fd1
GN		 2346 ss_sel = cs_sel + 8;
2347 cs.d = 0;
4668f050
AP		 2348 cs.l = 1;
2349 break;
2350 }
79168fd1
GN		 2351 cs_sel |= SELECTOR_RPL_MASK;
2352 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2353
1aa36616
AK		 2354 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2355 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2356
dd856efa
AK		 2357 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2358 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2359
e54cfa97 2360 return X86EMUL_CONTINUE;
4668f050
AP		 2361}
2362
7b105ca2 2363static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2364{
2365 int iopl;
2366 if (ctxt->mode == X86EMUL_MODE_REAL)
2367 return false;
2368 if (ctxt->mode == X86EMUL_MODE_VM86)
2369 return true;
2370 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2371 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2372}
2373
2374static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2375 u16 port, u16 len)
2376{
0225fb50 2377 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2378 struct desc_struct tr_seg;
5601d05b 2379 u32 base3;
f850e2e6 2380 int r;
1aa36616 2381 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2382 unsigned mask = (1 << len) - 1;
5601d05b 2383 unsigned long base;
f850e2e6 2384
1aa36616 2385 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2386 if (!tr_seg.p)
f850e2e6 2387 return false;
79168fd1 2388 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2389 return false;
5601d05b
GN		 2390 base = get_desc_base(&tr_seg);
2391#ifdef CONFIG_X86_64
2392 base |= ((u64)base3) << 32;
2393#endif
0f65dd70 2394 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2395 if (r != X86EMUL_CONTINUE)
2396 return false;
79168fd1 2397 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2398 return false;
0f65dd70 2399 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2400 if (r != X86EMUL_CONTINUE)
2401 return false;
2402 if ((perm >> bit_idx) & mask)
2403 return false;
2404 return true;
2405}
2406
2407static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2408 u16 port, u16 len)
2409{
4fc40f07
GN		 2410 if (ctxt->perm_ok)
2411 return true;
2412
7b105ca2
TY		 2413 if (emulator_bad_iopl(ctxt))
2414 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2415 return false;
4fc40f07
GN		 2416
2417 ctxt->perm_ok = true;
2418
f850e2e6
GN		 2419 return true;
2420}
2421
38ba30ba 2422static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2423 struct tss_segment_16 *tss)
2424{
9dac77fa 2425 tss->ip = ctxt->_eip;
38ba30ba 2426 tss->flag = ctxt->eflags;
dd856efa
AK		 2427 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2428 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2429 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2430 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2431 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2432 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2433 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2434 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2435
1aa36616
AK		 2436 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2437 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2438 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2439 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2440 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2441}
2442
2443static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2444 struct tss_segment_16 *tss)
2445{
38ba30ba
GN		 2446 int ret;
2447
9dac77fa 2448 ctxt->_eip = tss->ip;
38ba30ba 2449 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2450 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2451 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2452 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2453 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2454 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2455 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2456 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2457 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2458
2459 /*
2460 * SDM says that segment selectors are loaded before segment
2461 * descriptors
2462 */
1aa36616
AK		 2463 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2464 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2465 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2466 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2467 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2468
2469 /*
fc058680 2470 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2471 * it is handled in a context of new task
2472 */
7b105ca2 2473 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
7b105ca2 2476 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
7b105ca2 2479 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2480 if (ret != X86EMUL_CONTINUE)
2481 return ret;
7b105ca2 2482 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2483 if (ret != X86EMUL_CONTINUE)
2484 return ret;
7b105ca2 2485 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2486 if (ret != X86EMUL_CONTINUE)
2487 return ret;
2488
2489 return X86EMUL_CONTINUE;
2490}
2491
2492static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2493 u16 tss_selector, u16 old_tss_sel,
2494 ulong old_tss_base, struct desc_struct *new_desc)
2495{
0225fb50 2496 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2497 struct tss_segment_16 tss_seg;
2498 int ret;
bcc55cba 2499 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2500
0f65dd70 2501 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2502 &ctxt->exception);
db297e3d 2503 if (ret != X86EMUL_CONTINUE)
38ba30ba 2504 /* FIXME: need to provide precise fault address */
38ba30ba 2505 return ret;
38ba30ba 2506
7b105ca2 2507 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2508
0f65dd70 2509 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2510 &ctxt->exception);
db297e3d 2511 if (ret != X86EMUL_CONTINUE)
38ba30ba 2512 /* FIXME: need to provide precise fault address */
38ba30ba 2513 return ret;
38ba30ba 2514
0f65dd70 2515 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2516 &ctxt->exception);
db297e3d 2517 if (ret != X86EMUL_CONTINUE)
38ba30ba 2518 /* FIXME: need to provide precise fault address */
38ba30ba 2519 return ret;
38ba30ba
GN		 2520
2521 if (old_tss_sel != 0xffff) {
2522 tss_seg.prev_task_link = old_tss_sel;
2523
0f65dd70 2524 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2525 &tss_seg.prev_task_link,
2526 sizeof tss_seg.prev_task_link,
0f65dd70 2527 &ctxt->exception);
db297e3d 2528 if (ret != X86EMUL_CONTINUE)
38ba30ba 2529 /* FIXME: need to provide precise fault address */
38ba30ba 2530 return ret;
38ba30ba
GN		 2531 }
2532
7b105ca2 2533 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2534}
2535
2536static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2537 struct tss_segment_32 *tss)
2538{
7b105ca2 2539 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2540 tss->eip = ctxt->_eip;
38ba30ba 2541 tss->eflags = ctxt->eflags;
dd856efa
AK		 2542 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2543 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2544 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2545 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2546 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2547 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2548 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2549 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2550
1aa36616
AK		 2551 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2552 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2553 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2554 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2555 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2556 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2557 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2558}
2559
2560static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2561 struct tss_segment_32 *tss)
2562{
38ba30ba
GN		 2563 int ret;
2564
7b105ca2 2565 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2566 return emulate_gp(ctxt, 0);
9dac77fa 2567 ctxt->_eip = tss->eip;
38ba30ba 2568 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2569
2570 /* General purpose registers */
dd856efa
AK		 2571 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2572 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2573 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2574 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2575 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2576 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2577 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2578 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2579
2580 /*
2581 * SDM says that segment selectors are loaded before segment
2582 * descriptors
2583 */
1aa36616
AK		 2584 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2585 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2586 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2587 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2588 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2589 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2590 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2591
4cee4798
KW		 2592 /*
2593 * If we're switching between Protected Mode and VM86, we need to make
2594 * sure to update the mode before loading the segment descriptors so
2595 * that the selectors are interpreted correctly.
2596 *
2597 * Need to get rflags to the vcpu struct immediately because it
2598 * influences the CPL which is checked at least when loading the segment
2599 * descriptors and when pushing an error code to the new kernel stack.
2600 *
2601 * TODO Introduce a separate ctxt->ops->set_cpl callback
2602 */
2603 if (ctxt->eflags & X86_EFLAGS_VM)
2604 ctxt->mode = X86EMUL_MODE_VM86;
2605 else
2606 ctxt->mode = X86EMUL_MODE_PROT32;
2607
2608 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2609
38ba30ba
GN		 2610 /*
2611 * Now load segment descriptors. If fault happenes at this stage
2612 * it is handled in a context of new task
2613 */
7b105ca2 2614 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2615 if (ret != X86EMUL_CONTINUE)
2616 return ret;
7b105ca2 2617 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2618 if (ret != X86EMUL_CONTINUE)
2619 return ret;
7b105ca2 2620 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
7b105ca2 2623 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
7b105ca2 2626 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
7b105ca2 2629 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
7b105ca2 2632 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2633 if (ret != X86EMUL_CONTINUE)
2634 return ret;
2635
2636 return X86EMUL_CONTINUE;
2637}
2638
2639static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2640 u16 tss_selector, u16 old_tss_sel,
2641 ulong old_tss_base, struct desc_struct *new_desc)
2642{
0225fb50 2643 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2644 struct tss_segment_32 tss_seg;
2645 int ret;
bcc55cba 2646 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2647
0f65dd70 2648 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2649 &ctxt->exception);
db297e3d 2650 if (ret != X86EMUL_CONTINUE)
38ba30ba 2651 /* FIXME: need to provide precise fault address */
38ba30ba 2652 return ret;
38ba30ba 2653
7b105ca2 2654 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2655
0f65dd70 2656 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2657 &ctxt->exception);
db297e3d 2658 if (ret != X86EMUL_CONTINUE)
38ba30ba 2659 /* FIXME: need to provide precise fault address */
38ba30ba 2660 return ret;
38ba30ba 2661
0f65dd70 2662 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2663 &ctxt->exception);
db297e3d 2664 if (ret != X86EMUL_CONTINUE)
38ba30ba 2665 /* FIXME: need to provide precise fault address */
38ba30ba 2666 return ret;
38ba30ba
GN		 2667
2668 if (old_tss_sel != 0xffff) {
2669 tss_seg.prev_task_link = old_tss_sel;
2670
0f65dd70 2671 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2672 &tss_seg.prev_task_link,
2673 sizeof tss_seg.prev_task_link,
0f65dd70 2674 &ctxt->exception);
db297e3d 2675 if (ret != X86EMUL_CONTINUE)
38ba30ba 2676 /* FIXME: need to provide precise fault address */
38ba30ba 2677 return ret;
38ba30ba
GN		 2678 }
2679
7b105ca2 2680 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2681}
2682
2683static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2684 u16 tss_selector, int idt_index, int reason,
e269fb21 2685 bool has_error_code, u32 error_code)
38ba30ba 2686{
0225fb50 2687 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2688 struct desc_struct curr_tss_desc, next_tss_desc;
2689 int ret;
1aa36616 2690 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2691 ulong old_tss_base =
4bff1e86 2692 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2693 u32 desc_limit;
e919464b 2694 ulong desc_addr;
38ba30ba
GN		 2695
2696 /* FIXME: old_tss_base == ~0 ? */
2697
e919464b 2698 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2699 if (ret != X86EMUL_CONTINUE)
2700 return ret;
e919464b 2701 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2702 if (ret != X86EMUL_CONTINUE)
2703 return ret;
2704
2705 /* FIXME: check that next_tss_desc is tss */
2706
7f3d35fd
KW		 2707 /*
2708 * Check privileges. The three cases are task switch caused by...
2709 *
2710 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2711 * 2. Exception/IRQ/iret: No check is performed
fc058680 2712 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2713 */
2714 if (reason == TASK_SWITCH_GATE) {
2715 if (idt_index != -1) {
2716 /* Software interrupts */
2717 struct desc_struct task_gate_desc;
2718 int dpl;
2719
2720 ret = read_interrupt_descriptor(ctxt, idt_index,
2721 &task_gate_desc);
2722 if (ret != X86EMUL_CONTINUE)
2723 return ret;
2724
2725 dpl = task_gate_desc.dpl;
2726 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2727 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2728 }
2729 } else if (reason != TASK_SWITCH_IRET) {
2730 int dpl = next_tss_desc.dpl;
2731 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2732 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2733 }
2734
7f3d35fd 2735
ceffb459
GN		 2736 desc_limit = desc_limit_scaled(&next_tss_desc);
2737 if (!next_tss_desc.p ||
2738 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2739 desc_limit < 0x2b)) {
54b8486f 2740 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2741 return X86EMUL_PROPAGATE_FAULT;
2742 }
2743
2744 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2745 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2746 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2747 }
2748
2749 if (reason == TASK_SWITCH_IRET)
2750 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2751
2752 /* set back link to prev task only if NT bit is set in eflags
fc058680 2753 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2754 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2755 old_tss_sel = 0xffff;
2756
2757 if (next_tss_desc.type & 8)
7b105ca2 2758 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2759 old_tss_base, &next_tss_desc);
2760 else
7b105ca2 2761 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2762 old_tss_base, &next_tss_desc);
0760d448
JK		 2763 if (ret != X86EMUL_CONTINUE)
2764 return ret;
38ba30ba
GN		 2765
2766 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2767 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2768
2769 if (reason != TASK_SWITCH_IRET) {
2770 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2771 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2772 }
2773
717746e3 2774 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2775 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2776
e269fb21 2777 if (has_error_code) {
9dac77fa
AK		 2778 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2779 ctxt->lock_prefix = 0;
2780 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2781 ret = em_push(ctxt);
e269fb21
JK		 2782 }
2783
38ba30ba
GN		 2784 return ret;
2785}
2786
2787int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2788 u16 tss_selector, int idt_index, int reason,
e269fb21 2789 bool has_error_code, u32 error_code)
38ba30ba 2790{
38ba30ba
GN		 2791 int rc;
2792
dd856efa 2793 invalidate_registers(ctxt);
9dac77fa
AK		 2794 ctxt->_eip = ctxt->eip;
2795 ctxt->dst.type = OP_NONE;
38ba30ba 2796
7f3d35fd 2797 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2798 has_error_code, error_code);
38ba30ba 2799
dd856efa 2800 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2801 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2802 writeback_registers(ctxt);
2803 }
38ba30ba 2804
a0c0ab2f 2805 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2806}
2807
f3bd64c6
GN		 2808static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2809 struct operand *op)
a682e354 2810{
b3356bf0 2811 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2812
dd856efa
AK		 2813 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2814 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2815}
2816
7af04fc0
AK		 2817static int em_das(struct x86_emulate_ctxt *ctxt)
2818{
7af04fc0
AK		 2819 u8 al, old_al;
2820 bool af, cf, old_cf;
2821
2822 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2823 al = ctxt->dst.val;
7af04fc0
AK		 2824
2825 old_al = al;
2826 old_cf = cf;
2827 cf = false;
2828 af = ctxt->eflags & X86_EFLAGS_AF;
2829 if ((al & 0x0f) > 9 || af) {
2830 al -= 6;
2831 cf = old_cf | (al >= 250);
2832 af = true;
2833 } else {
2834 af = false;
2835 }
2836 if (old_al > 0x99 || old_cf) {
2837 al -= 0x60;
2838 cf = true;
2839 }
2840
9dac77fa 2841 ctxt->dst.val = al;
7af04fc0 2842 /* Set PF, ZF, SF */
9dac77fa
AK		 2843 ctxt->src.type = OP_IMM;
2844 ctxt->src.val = 0;
2845 ctxt->src.bytes = 1;
a31b9cea 2846 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2847 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2848 if (cf)
2849 ctxt->eflags |= X86_EFLAGS_CF;
2850 if (af)
2851 ctxt->eflags |= X86_EFLAGS_AF;
2852 return X86EMUL_CONTINUE;
2853}
2854
7f662273
GN		 2855static int em_aad(struct x86_emulate_ctxt *ctxt)
2856{
2857 u8 al = ctxt->dst.val & 0xff;
2858 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2859
2860 al = (al + (ah * ctxt->src.val)) & 0xff;
2861
2862 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2863
2864 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2865
2866 if (!al)
2867 ctxt->eflags |= X86_EFLAGS_ZF;
2868 if (!(al & 1))
2869 ctxt->eflags |= X86_EFLAGS_PF;
2870 if (al & 0x80)
2871 ctxt->eflags |= X86_EFLAGS_SF;
2872
2873 return X86EMUL_CONTINUE;
2874}
2875
d4ddafcd
TY		 2876static int em_call(struct x86_emulate_ctxt *ctxt)
2877{
2878 long rel = ctxt->src.val;
2879
2880 ctxt->src.val = (unsigned long)ctxt->_eip;
2881 jmp_rel(ctxt, rel);
2882 return em_push(ctxt);
2883}
2884
0ef753b8
AK		 2885static int em_call_far(struct x86_emulate_ctxt *ctxt)
2886{
0ef753b8
AK		 2887 u16 sel, old_cs;
2888 ulong old_eip;
2889 int rc;
2890
1aa36616 2891 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2892 old_eip = ctxt->_eip;
0ef753b8 2893
9dac77fa 2894 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2895 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2896 return X86EMUL_CONTINUE;
2897
9dac77fa
AK		 2898 ctxt->_eip = 0;
2899 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2900
9dac77fa 2901 ctxt->src.val = old_cs;
4487b3b4 2902 rc = em_push(ctxt);
0ef753b8
AK		 2903 if (rc != X86EMUL_CONTINUE)
2904 return rc;
2905
9dac77fa 2906 ctxt->src.val = old_eip;
4487b3b4 2907 return em_push(ctxt);
0ef753b8
AK		 2908}
2909
40ece7c7
AK		 2910static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2911{
40ece7c7
AK		 2912 int rc;
2913
9dac77fa
AK		 2914 ctxt->dst.type = OP_REG;
2915 ctxt->dst.addr.reg = &ctxt->_eip;
2916 ctxt->dst.bytes = ctxt->op_bytes;
2917 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2918 if (rc != X86EMUL_CONTINUE)
2919 return rc;
5ad105e5 2920 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2921 return X86EMUL_CONTINUE;
2922}
2923
d67fc27a
TY		 2924static int em_add(struct x86_emulate_ctxt *ctxt)
2925{
a31b9cea 2926 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2927 return X86EMUL_CONTINUE;
2928}
2929
2930static int em_or(struct x86_emulate_ctxt *ctxt)
2931{
a31b9cea 2932 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2933 return X86EMUL_CONTINUE;
2934}
2935
2936static int em_adc(struct x86_emulate_ctxt *ctxt)
2937{
a31b9cea 2938 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2939 return X86EMUL_CONTINUE;
2940}
2941
2942static int em_sbb(struct x86_emulate_ctxt *ctxt)
2943{
a31b9cea 2944 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2945 return X86EMUL_CONTINUE;
2946}
2947
2948static int em_and(struct x86_emulate_ctxt *ctxt)
2949{
a31b9cea 2950 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2951 return X86EMUL_CONTINUE;
2952}
2953
2954static int em_sub(struct x86_emulate_ctxt *ctxt)
2955{
a31b9cea 2956 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2957 return X86EMUL_CONTINUE;
2958}
2959
2960static int em_xor(struct x86_emulate_ctxt *ctxt)
2961{
a31b9cea 2962 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2963 return X86EMUL_CONTINUE;
2964}
2965
2966static int em_cmp(struct x86_emulate_ctxt *ctxt)
2967{
a31b9cea 2968 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2969 /* Disable writeback. */
9dac77fa 2970 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2971 return X86EMUL_CONTINUE;
2972}
2973
9f21ca59
TY		 2974static int em_test(struct x86_emulate_ctxt *ctxt)
2975{
a31b9cea 2976 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2977 /* Disable writeback. */
2978 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2979 return X86EMUL_CONTINUE;
2980}
2981
e4f973ae
TY		 2982static int em_xchg(struct x86_emulate_ctxt *ctxt)
2983{
e4f973ae 2984 /* Write back the register source. */
9dac77fa
AK		 2985 ctxt->src.val = ctxt->dst.val;
2986 write_register_operand(&ctxt->src);
e4f973ae
TY		 2987
2988 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2989 ctxt->dst.val = ctxt->src.orig_val;
2990 ctxt->lock_prefix = 1;
e4f973ae
TY		 2991 return X86EMUL_CONTINUE;
2992}
2993
5c82aa29 2994static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2995{
a31b9cea 2996 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2997 return X86EMUL_CONTINUE;
2998}
2999
5c82aa29
AK		 3000static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3001{
9dac77fa 3002 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3003 return em_imul(ctxt);
3004}
3005
61429142
AK		 3006static int em_cwd(struct x86_emulate_ctxt *ctxt)
3007{
9dac77fa
AK		 3008 ctxt->dst.type = OP_REG;
3009 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3010 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3011 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3012
3013 return X86EMUL_CONTINUE;
3014}
3015
48bb5d3c
AK		 3016static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3017{
48bb5d3c
AK		 3018 u64 tsc = 0;
3019
717746e3 3020 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3021 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3022 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3023 return X86EMUL_CONTINUE;
3024}
3025
222d21aa
AK		 3026static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3027{
3028 u64 pmc;
3029
dd856efa 3030 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3031 return emulate_gp(ctxt, 0);
dd856efa
AK		 3032 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3033 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3034 return X86EMUL_CONTINUE;
3035}
3036
b9eac5f4
AK		 3037static int em_mov(struct x86_emulate_ctxt *ctxt)
3038{
49597d81 3039 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3040 return X86EMUL_CONTINUE;
3041}
3042
bc00f8d2
TY		 3043static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3044{
3045 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3046 return emulate_gp(ctxt, 0);
3047
3048 /* Disable writeback. */
3049 ctxt->dst.type = OP_NONE;
3050 return X86EMUL_CONTINUE;
3051}
3052
3053static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3054{
3055 unsigned long val;
3056
3057 if (ctxt->mode == X86EMUL_MODE_PROT64)
3058 val = ctxt->src.val & ~0ULL;
3059 else
3060 val = ctxt->src.val & ~0U;
3061
3062 /* #UD condition is already handled. */
3063 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3064 return emulate_gp(ctxt, 0);
3065
3066 /* Disable writeback. */
3067 ctxt->dst.type = OP_NONE;
3068 return X86EMUL_CONTINUE;
3069}
3070
e1e210b0
TY		 3071static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3072{
3073 u64 msr_data;
3074
dd856efa
AK		 3075 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3076 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3077 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3078 return emulate_gp(ctxt, 0);
3079
3080 return X86EMUL_CONTINUE;
3081}
3082
3083static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3084{
3085 u64 msr_data;
3086
dd856efa 3087 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3088 return emulate_gp(ctxt, 0);
3089
dd856efa
AK		 3090 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3091 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3092 return X86EMUL_CONTINUE;
3093}
3094
1bd5f469
TY		 3095static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3096{
9dac77fa 3097 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3098 return emulate_ud(ctxt);
3099
9dac77fa 3100 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3101 return X86EMUL_CONTINUE;
3102}
3103
3104static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3105{
9dac77fa 3106 u16 sel = ctxt->src.val;
1bd5f469 3107
9dac77fa 3108 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3109 return emulate_ud(ctxt);
3110
9dac77fa 3111 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3112 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3113
3114 /* Disable writeback. */
9dac77fa
AK		 3115 ctxt->dst.type = OP_NONE;
3116 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3117}
3118
a14e579f
AK		 3119static int em_lldt(struct x86_emulate_ctxt *ctxt)
3120{
3121 u16 sel = ctxt->src.val;
3122
3123 /* Disable writeback. */
3124 ctxt->dst.type = OP_NONE;
3125 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3126}
3127
80890006
AK		 3128static int em_ltr(struct x86_emulate_ctxt *ctxt)
3129{
3130 u16 sel = ctxt->src.val;
3131
3132 /* Disable writeback. */
3133 ctxt->dst.type = OP_NONE;
3134 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3135}
3136
38503911
AK		 3137static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3138{
9fa088f4
AK		 3139 int rc;
3140 ulong linear;
3141
9dac77fa 3142 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3143 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3144 ctxt->ops->invlpg(ctxt, linear);
38503911 3145 /* Disable writeback. */
9dac77fa 3146 ctxt->dst.type = OP_NONE;
38503911
AK		 3147 return X86EMUL_CONTINUE;
3148}
3149
2d04a05b
AK		 3150static int em_clts(struct x86_emulate_ctxt *ctxt)
3151{
3152 ulong cr0;
3153
3154 cr0 = ctxt->ops->get_cr(ctxt, 0);
3155 cr0 &= ~X86_CR0_TS;
3156 ctxt->ops->set_cr(ctxt, 0, cr0);
3157 return X86EMUL_CONTINUE;
3158}
3159
26d05cc7
AK		 3160static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3161{
26d05cc7
AK		 3162 int rc;
3163
9dac77fa 3164 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3165 return X86EMUL_UNHANDLEABLE;
3166
3167 rc = ctxt->ops->fix_hypercall(ctxt);
3168 if (rc != X86EMUL_CONTINUE)
3169 return rc;
3170
3171 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3172 ctxt->_eip = ctxt->eip;
26d05cc7 3173 /* Disable writeback. */
9dac77fa 3174 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3175 return X86EMUL_CONTINUE;
3176}
3177
96051572
AK		 3178static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3179 void (*get)(struct x86_emulate_ctxt *ctxt,
3180 struct desc_ptr *ptr))
3181{
3182 struct desc_ptr desc_ptr;
3183
3184 if (ctxt->mode == X86EMUL_MODE_PROT64)
3185 ctxt->op_bytes = 8;
3186 get(ctxt, &desc_ptr);
3187 if (ctxt->op_bytes == 2) {
3188 ctxt->op_bytes = 4;
3189 desc_ptr.address &= 0x00ffffff;
3190 }
3191 /* Disable writeback. */
3192 ctxt->dst.type = OP_NONE;
3193 return segmented_write(ctxt, ctxt->dst.addr.mem,
3194 &desc_ptr, 2 + ctxt->op_bytes);
3195}
3196
3197static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3198{
3199 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3200}
3201
3202static int em_sidt(struct x86_emulate_ctxt *ctxt)
3203{
3204 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3205}
3206
26d05cc7
AK		 3207static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3208{
26d05cc7
AK		 3209 struct desc_ptr desc_ptr;
3210 int rc;
3211
510425ff
AK		 3212 if (ctxt->mode == X86EMUL_MODE_PROT64)
3213 ctxt->op_bytes = 8;
9dac77fa 3214 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3215 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3216 ctxt->op_bytes);
26d05cc7
AK		 3217 if (rc != X86EMUL_CONTINUE)
3218 return rc;
3219 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3220 /* Disable writeback. */
9dac77fa 3221 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3222 return X86EMUL_CONTINUE;
3223}
3224
5ef39c71 3225static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3226{
26d05cc7
AK		 3227 int rc;
3228
5ef39c71
AK		 3229 rc = ctxt->ops->fix_hypercall(ctxt);
3230
26d05cc7 3231 /* Disable writeback. */
9dac77fa 3232 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3233 return rc;
3234}
3235
3236static int em_lidt(struct x86_emulate_ctxt *ctxt)
3237{
26d05cc7
AK		 3238 struct desc_ptr desc_ptr;
3239 int rc;
3240
510425ff
AK		 3241 if (ctxt->mode == X86EMUL_MODE_PROT64)
3242 ctxt->op_bytes = 8;
9dac77fa 3243 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3244 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3245 ctxt->op_bytes);
26d05cc7
AK		 3246 if (rc != X86EMUL_CONTINUE)
3247 return rc;
3248 ctxt->ops->set_idt(ctxt, &desc_ptr);
3249 /* Disable writeback. */
9dac77fa 3250 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3251 return X86EMUL_CONTINUE;
3252}
3253
3254static int em_smsw(struct x86_emulate_ctxt *ctxt)
3255{
9dac77fa
AK		 3256 ctxt->dst.bytes = 2;
3257 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3258 return X86EMUL_CONTINUE;
3259}
3260
3261static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3262{
26d05cc7 3263 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3264 | (ctxt->src.val & 0x0f));
3265 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3266 return X86EMUL_CONTINUE;
3267}
3268
d06e03ad
TY		 3269static int em_loop(struct x86_emulate_ctxt *ctxt)
3270{
dd856efa
AK		 3271 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3272 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3273 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3274 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3275
3276 return X86EMUL_CONTINUE;
3277}
3278
3279static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3280{
dd856efa 3281 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3282 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3283
3284 return X86EMUL_CONTINUE;
3285}
3286
d7841a4b
TY		 3287static int em_in(struct x86_emulate_ctxt *ctxt)
3288{
3289 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3290 &ctxt->dst.val))
3291 return X86EMUL_IO_NEEDED;
3292
3293 return X86EMUL_CONTINUE;
3294}
3295
3296static int em_out(struct x86_emulate_ctxt *ctxt)
3297{
3298 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3299 &ctxt->src.val, 1);
3300 /* Disable writeback. */
3301 ctxt->dst.type = OP_NONE;
3302 return X86EMUL_CONTINUE;
3303}
3304
f411e6cd
TY		 3305static int em_cli(struct x86_emulate_ctxt *ctxt)
3306{
3307 if (emulator_bad_iopl(ctxt))
3308 return emulate_gp(ctxt, 0);
3309
3310 ctxt->eflags &= ~X86_EFLAGS_IF;
3311 return X86EMUL_CONTINUE;
3312}
3313
3314static int em_sti(struct x86_emulate_ctxt *ctxt)
3315{
3316 if (emulator_bad_iopl(ctxt))
3317 return emulate_gp(ctxt, 0);
3318
3319 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3320 ctxt->eflags |= X86_EFLAGS_IF;
3321 return X86EMUL_CONTINUE;
3322}
3323
ce7faab2
TY		 3324static int em_bt(struct x86_emulate_ctxt *ctxt)
3325{
3326 /* Disable writeback. */
3327 ctxt->dst.type = OP_NONE;
3328 /* only subword offset */
3329 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3330
3331 emulate_2op_SrcV_nobyte(ctxt, "bt");
3332 return X86EMUL_CONTINUE;
3333}
3334
3335static int em_bts(struct x86_emulate_ctxt *ctxt)
3336{
3337 emulate_2op_SrcV_nobyte(ctxt, "bts");
3338 return X86EMUL_CONTINUE;
3339}
3340
3341static int em_btr(struct x86_emulate_ctxt *ctxt)
3342{
3343 emulate_2op_SrcV_nobyte(ctxt, "btr");
3344 return X86EMUL_CONTINUE;
3345}
3346
3347static int em_btc(struct x86_emulate_ctxt *ctxt)
3348{
3349 emulate_2op_SrcV_nobyte(ctxt, "btc");
3350 return X86EMUL_CONTINUE;
3351}
3352
ff227392
TY		 3353static int em_bsf(struct x86_emulate_ctxt *ctxt)
3354{
d54e4237 3355 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3356 return X86EMUL_CONTINUE;
3357}
3358
3359static int em_bsr(struct x86_emulate_ctxt *ctxt)
3360{
d54e4237 3361 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3362 return X86EMUL_CONTINUE;
3363}
3364
6d6eede4
AK		 3365static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3366{
3367 u32 eax, ebx, ecx, edx;
3368
dd856efa
AK		 3369 eax = reg_read(ctxt, VCPU_REGS_RAX);
3370 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3371 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3372 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3373 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3374 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3375 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3376 return X86EMUL_CONTINUE;
3377}
3378
2dd7caa0
AK		 3379static int em_lahf(struct x86_emulate_ctxt *ctxt)
3380{
dd856efa
AK		 3381 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3382 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3383 return X86EMUL_CONTINUE;
3384}
3385
9299836e
AK		 3386static int em_bswap(struct x86_emulate_ctxt *ctxt)
3387{
3388 switch (ctxt->op_bytes) {
3389#ifdef CONFIG_X86_64
3390 case 8:
3391 asm("bswap %0" : "+r"(ctxt->dst.val));
3392 break;
3393#endif
3394 default:
3395 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3396 break;
3397 }
3398 return X86EMUL_CONTINUE;
3399}
3400
cfec82cb
JR		 3401static bool valid_cr(int nr)
3402{
3403 switch (nr) {
3404 case 0:
3405 case 2 ... 4:
3406 case 8:
3407 return true;
3408 default:
3409 return false;
3410 }
3411}
3412
3413static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3414{
9dac77fa 3415 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3416 return emulate_ud(ctxt);
3417
3418 return X86EMUL_CONTINUE;
3419}
3420
3421static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3422{
9dac77fa
AK		 3423 u64 new_val = ctxt->src.val64;
3424 int cr = ctxt->modrm_reg;
c2ad2bb3 3425 u64 efer = 0;
cfec82cb
JR		 3426
3427 static u64 cr_reserved_bits[] = {
3428 0xffffffff00000000ULL,
3429 0, 0, 0, /* CR3 checked later */
3430 CR4_RESERVED_BITS,
3431 0, 0, 0,
3432 CR8_RESERVED_BITS,
3433 };
3434
3435 if (!valid_cr(cr))
3436 return emulate_ud(ctxt);
3437
3438 if (new_val & cr_reserved_bits[cr])
3439 return emulate_gp(ctxt, 0);
3440
3441 switch (cr) {
3442 case 0: {
c2ad2bb3 3443 u64 cr4;
cfec82cb
JR		 3444 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3445 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3446 return emulate_gp(ctxt, 0);
3447
717746e3
AK		 3448 cr4 = ctxt->ops->get_cr(ctxt, 4);
3449 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3450
3451 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3452 !(cr4 & X86_CR4_PAE))
3453 return emulate_gp(ctxt, 0);
3454
3455 break;
3456 }
3457 case 3: {
3458 u64 rsvd = 0;
3459
c2ad2bb3
AK		 3460 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3461 if (efer & EFER_LMA)
cfec82cb 3462 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3463 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3464 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3465 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3466 rsvd = CR3_NONPAE_RESERVED_BITS;
3467
3468 if (new_val & rsvd)
3469 return emulate_gp(ctxt, 0);
3470
3471 break;
3472 }
3473 case 4: {
717746e3 3474 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3475
3476 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3477 return emulate_gp(ctxt, 0);
3478
3479 break;
3480 }
3481 }
3482
3483 return X86EMUL_CONTINUE;
3484}
3485
3b88e41a
JR		 3486static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3487{
3488 unsigned long dr7;
3489
717746e3 3490 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3491
3492 /* Check if DR7.Global_Enable is set */
3493 return dr7 & (1 << 13);
3494}
3495
3496static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3497{
9dac77fa 3498 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3499 u64 cr4;
3500
3501 if (dr > 7)
3502 return emulate_ud(ctxt);
3503
717746e3 3504 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3505 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3506 return emulate_ud(ctxt);
3507
3508 if (check_dr7_gd(ctxt))
3509 return emulate_db(ctxt);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
3514static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3515{
9dac77fa
AK		 3516 u64 new_val = ctxt->src.val64;
3517 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3518
3519 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3520 return emulate_gp(ctxt, 0);
3521
3522 return check_dr_read(ctxt);
3523}
3524
01de8b09
JR		 3525static int check_svme(struct x86_emulate_ctxt *ctxt)
3526{
3527 u64 efer;
3528
717746e3 3529 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3530
3531 if (!(efer & EFER_SVME))
3532 return emulate_ud(ctxt);
3533
3534 return X86EMUL_CONTINUE;
3535}
3536
3537static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3538{
dd856efa 3539 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3540
3541 /* Valid physical address? */
d4224449 3542 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3543 return emulate_gp(ctxt, 0);
3544
3545 return check_svme(ctxt);
3546}
3547
d7eb8203
JR		 3548static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3549{
717746e3 3550 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3551
717746e3 3552 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3553 return emulate_ud(ctxt);
3554
3555 return X86EMUL_CONTINUE;
3556}
3557
8061252e
JR		 3558static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3559{
717746e3 3560 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3561 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3562
717746e3 3563 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3564 (rcx > 3))
3565 return emulate_gp(ctxt, 0);
3566
3567 return X86EMUL_CONTINUE;
3568}
3569
f6511935
JR		 3570static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3571{
9dac77fa
AK		 3572 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3573 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3574 return emulate_gp(ctxt, 0);
3575
3576 return X86EMUL_CONTINUE;
3577}
3578
3579static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3580{
9dac77fa
AK		 3581 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3582 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3583 return emulate_gp(ctxt, 0);
3584
3585 return X86EMUL_CONTINUE;
3586}
3587
73fba5f4 3588#define D(_y) { .flags = (_y) }
c4f035c6 3589#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3590#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3591 .check_perm = (_p) }
73fba5f4 3592#define N D(0)
01de8b09 3593#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3594#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3595#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3596#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3597#define II(_f, _e, _i) \
3598 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3599#define IIP(_f, _e, _i, _p) \
3600 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3601 .check_perm = (_p) }
aa97bb48 3602#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3603
8d8f4e9f 3604#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3605#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3606#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3607#define I2bvIP(_f, _e, _i, _p) \
3608 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3609
d67fc27a
TY		 3610#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3611 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3612 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3613
fd0a0d82 3614static const struct opcode group7_rm1[] = {
1c2545be
TY		 3615 DI(SrcNone | Priv, monitor),
3616 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3617 N, N, N, N, N, N,
3618};
3619
fd0a0d82 3620static const struct opcode group7_rm3[] = {
1c2545be
TY		 3621 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3622 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3623 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3624 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3625 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3626 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3627 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3628 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3629};
6230f7fc 3630
fd0a0d82 3631static const struct opcode group7_rm7[] = {
d7eb8203 3632 N,
1c2545be 3633 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3634 N, N, N, N, N, N,
3635};
d67fc27a 3636
fd0a0d82 3637static const struct opcode group1[] = {
d67fc27a 3638 I(Lock, em_add),
d5ae7ce8 3639 I(Lock | PageTable, em_or),
d67fc27a
TY		 3640 I(Lock, em_adc),
3641 I(Lock, em_sbb),
d5ae7ce8 3642 I(Lock | PageTable, em_and),
d67fc27a
TY		 3643 I(Lock, em_sub),
3644 I(Lock, em_xor),
3645 I(0, em_cmp),
73fba5f4
AK		 3646};
3647
fd0a0d82 3648static const struct opcode group1A[] = {
1c2545be 3649 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3650};
3651
fd0a0d82 3652static const struct opcode group3[] = {
1c2545be
TY		 3653 I(DstMem | SrcImm, em_test),
3654 I(DstMem | SrcImm, em_test),
3655 I(DstMem | SrcNone | Lock, em_not),
3656 I(DstMem | SrcNone | Lock, em_neg),
3657 I(SrcMem, em_mul_ex),
3658 I(SrcMem, em_imul_ex),
3659 I(SrcMem, em_div_ex),
3660 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3661};
3662
fd0a0d82 3663static const struct opcode group4[] = {
1c2545be
TY		 3664 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3665 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3666 N, N, N, N, N, N,
3667};
3668
fd0a0d82 3669static const struct opcode group5[] = {
1c2545be
TY		 3670 I(DstMem | SrcNone | Lock, em_grp45),
3671 I(DstMem | SrcNone | Lock, em_grp45),
3672 I(SrcMem | Stack, em_grp45),
3673 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3674 I(SrcMem | Stack, em_grp45),
3675 I(SrcMemFAddr | ImplicitOps, em_grp45),
3676 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3677};
3678
fd0a0d82 3679static const struct opcode group6[] = {
1c2545be
TY		 3680 DI(Prot, sldt),
3681 DI(Prot, str),
a14e579f 3682 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3683 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3684 N, N, N, N,
3685};
3686
fd0a0d82 3687static const struct group_dual group7 = { {
96051572
AK		 3688 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3689 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3690 II(SrcMem | Priv, em_lgdt, lgdt),
3691 II(SrcMem | Priv, em_lidt, lidt),
3692 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3693 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3694 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3695}, {
1c2545be 3696 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3697 EXT(0, group7_rm1),
01de8b09 3698 N, EXT(0, group7_rm3),
1c2545be
TY		 3699 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3700 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3701 EXT(0, group7_rm7),
73fba5f4
AK		 3702} };
3703
fd0a0d82 3704static const struct opcode group8[] = {
73fba5f4 3705 N, N, N, N,
1c2545be
TY		 3706 I(DstMem | SrcImmByte, em_bt),
3707 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3708 I(DstMem | SrcImmByte | Lock, em_btr),
3709 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3710};
3711
fd0a0d82 3712static const struct group_dual group9 = { {
1c2545be 3713 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3714}, {
3715 N, N, N, N, N, N, N, N,
3716} };
3717
fd0a0d82 3718static const struct opcode group11[] = {
1c2545be 3719 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3720 X7(D(Undefined)),
a4d4a7c1
AK		 3721};
3722
fd0a0d82 3723static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3724 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3725};
3726
fd0a0d82 3727static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3728 I(0, em_mov), N, N, N,
3729};
3730
fd0a0d82 3731static const struct opcode opcode_table[256] = {
73fba5f4 3732 /* 0x00 - 0x07 */
d67fc27a 3733 I6ALU(Lock, em_add),
1cd196ea
AK		 3734 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3735 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3736 /* 0x08 - 0x0F */
d5ae7ce8 3737 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3738 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3739 N,
73fba5f4 3740 /* 0x10 - 0x17 */
d67fc27a 3741 I6ALU(Lock, em_adc),
1cd196ea
AK		 3742 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3743 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3744 /* 0x18 - 0x1F */
d67fc27a 3745 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3746 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3747 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3748 /* 0x20 - 0x27 */
d5ae7ce8 3749 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3750 /* 0x28 - 0x2F */
d67fc27a 3751 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3752 /* 0x30 - 0x37 */
d67fc27a 3753 I6ALU(Lock, em_xor), N, N,
73fba5f4 3754 /* 0x38 - 0x3F */
d67fc27a 3755 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3756 /* 0x40 - 0x4F */
3757 X16(D(DstReg)),
3758 /* 0x50 - 0x57 */
63540382 3759 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3760 /* 0x58 - 0x5F */
c54fe504 3761 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3762 /* 0x60 - 0x67 */
b96a7fad
TY		 3763 I(ImplicitOps | Stack | No64, em_pusha),
3764 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3765 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3766 N, N, N, N,
3767 /* 0x68 - 0x6F */
d46164db
AK		 3768 I(SrcImm | Mov | Stack, em_push),
3769 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3770 I(SrcImmByte | Mov | Stack, em_push),
3771 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3772 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3773 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3774 /* 0x70 - 0x7F */
3775 X16(D(SrcImmByte)),
3776 /* 0x80 - 0x87 */
1c2545be
TY		 3777 G(ByteOp | DstMem | SrcImm, group1),
3778 G(DstMem | SrcImm, group1),
3779 G(ByteOp | DstMem | SrcImm | No64, group1),
3780 G(DstMem | SrcImmByte, group1),
9f21ca59 3781 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3782 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3783 /* 0x88 - 0x8F */
d5ae7ce8 3784 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3785 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3786 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3787 D(ModRM | SrcMem | NoAccess | DstReg),
3788 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3789 G(0, group1A),
73fba5f4 3790 /* 0x90 - 0x97 */
bf608f88 3791 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3792 /* 0x98 - 0x9F */
61429142 3793 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3794 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3795 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3796 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3797 /* 0xA0 - 0xA7 */
b9eac5f4 3798 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3799 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3800 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3801 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3802 /* 0xA8 - 0xAF */
9f21ca59 3803 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3804 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3805 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3806 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3807 /* 0xB0 - 0xB7 */
b9eac5f4 3808 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3809 /* 0xB8 - 0xBF */
b9eac5f4 3810 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3811 /* 0xC0 - 0xC7 */
d2c6c7ad 3812 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3813 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3814 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3815 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3816 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3817 G(ByteOp, group11), G(0, group11),
73fba5f4 3818 /* 0xC8 - 0xCF */
612e89f0
AK		 3819 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3820 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3821 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3822 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3823 /* 0xD0 - 0xD7 */
d2c6c7ad 3824 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3825 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4
AK		 3826 /* 0xD8 - 0xDF */
3827 N, N, N, N, N, N, N, N,
3828 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3829 X3(I(SrcImmByte, em_loop)),
3830 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3831 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3832 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3833 /* 0xE8 - 0xEF */
d4ddafcd 3834 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3835 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3836 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3837 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3838 /* 0xF0 - 0xF7 */
bf608f88 3839 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3840 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3841 G(ByteOp, group3), G(0, group3),
73fba5f4 3842 /* 0xF8 - 0xFF */
f411e6cd
TY		 3843 D(ImplicitOps), D(ImplicitOps),
3844 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3845 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3846};
3847
fd0a0d82 3848static const struct opcode twobyte_table[256] = {
73fba5f4 3849 /* 0x00 - 0x0F */
dee6bb70 3850 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3851 N, I(ImplicitOps | VendorSpecific, em_syscall),
3852 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3853 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3854 N, D(ImplicitOps | ModRM), N, N,
3855 /* 0x10 - 0x1F */
3856 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3857 /* 0x20 - 0x2F */
cfec82cb 3858 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3859 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3860 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3861 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3862 N, N, N, N,
3e114eb4
AK		 3863 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3864 N, N, N, N,
73fba5f4 3865 /* 0x30 - 0x3F */
e1e210b0 3866 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3867 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3868 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3869 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3870 I(ImplicitOps | VendorSpecific, em_sysenter),
3871 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3872 N, N,
73fba5f4
AK		 3873 N, N, N, N, N, N, N, N,
3874 /* 0x40 - 0x4F */
3875 X16(D(DstReg | SrcMem | ModRM | Mov)),
3876 /* 0x50 - 0x5F */
3877 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3878 /* 0x60 - 0x6F */
aa97bb48
AK		 3879 N, N, N, N,
3880 N, N, N, N,
3881 N, N, N, N,
3882 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3883 /* 0x70 - 0x7F */
aa97bb48
AK		 3884 N, N, N, N,
3885 N, N, N, N,
3886 N, N, N, N,
3887 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3888 /* 0x80 - 0x8F */
3889 X16(D(SrcImm)),
3890 /* 0x90 - 0x9F */
ee45b58e 3891 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3892 /* 0xA0 - 0xA7 */
1cd196ea 3893 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3894 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3895 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3896 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3897 /* 0xA8 - 0xAF */
1cd196ea 3898 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3899 DI(ImplicitOps, rsm),
ce7faab2 3900 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3901 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3902 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3903 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3904 /* 0xB0 - 0xB7 */
e940b5c2 3905 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3906 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3907 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3908 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3909 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3910 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3911 /* 0xB8 - 0xBF */
3912 N, N,
ce7faab2
TY		 3913 G(BitOp, group8),
3914 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3915 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3916 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3917 /* 0xC0 - 0xC7 */
739ae406 3918 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3919 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3920 N, N, N, GD(0, &group9),
9299836e
AK		 3921 /* 0xC8 - 0xCF */
3922 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3923 /* 0xD0 - 0xDF */
3924 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3925 /* 0xE0 - 0xEF */
3926 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3927 /* 0xF0 - 0xFF */
3928 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3929};
3930
3931#undef D
3932#undef N
3933#undef G
3934#undef GD
3935#undef I
aa97bb48 3936#undef GP
01de8b09 3937#undef EXT
73fba5f4 3938
8d8f4e9f 3939#undef D2bv
f6511935 3940#undef D2bvIP
8d8f4e9f 3941#undef I2bv
d7841a4b 3942#undef I2bvIP
d67fc27a 3943#undef I6ALU
8d8f4e9f 3944
9dac77fa 3945static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3946{
3947 unsigned size;
3948
9dac77fa 3949 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3950 if (size == 8)
3951 size = 4;
3952 return size;
3953}
3954
3955static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3956 unsigned size, bool sign_extension)
3957{
39f21ee5
AK		 3958 int rc = X86EMUL_CONTINUE;
3959
3960 op->type = OP_IMM;
3961 op->bytes = size;
9dac77fa 3962 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3963 /* NB. Immediates are sign-extended as necessary. */
3964 switch (op->bytes) {
3965 case 1:
e85a1085 3966 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3967 break;
3968 case 2:
e85a1085 3969 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3970 break;
3971 case 4:
e85a1085 3972 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3973 break;
3974 }
3975 if (!sign_extension) {
3976 switch (op->bytes) {
3977 case 1:
3978 op->val &= 0xff;
3979 break;
3980 case 2:
3981 op->val &= 0xffff;
3982 break;
3983 case 4:
3984 op->val &= 0xffffffff;
3985 break;
3986 }
3987 }
3988done:
3989 return rc;
3990}
3991
a9945549
AK		 3992static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3993 unsigned d)
3994{
3995 int rc = X86EMUL_CONTINUE;
3996
3997 switch (d) {
3998 case OpReg:
2adb5ad9 3999 decode_register_operand(ctxt, op);
a9945549
AK		 4000 break;
4001 case OpImmUByte:
608aabe3 4002 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4003 break;
4004 case OpMem:
41ddf978 4005 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4006 mem_common:
4007 *op = ctxt->memop;
4008 ctxt->memopp = op;
4009 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4010 fetch_bit_operand(ctxt);
4011 op->orig_val = op->val;
4012 break;
41ddf978
AK		 4013 case OpMem64:
4014 ctxt->memop.bytes = 8;
4015 goto mem_common;
a9945549
AK		 4016 case OpAcc:
4017 op->type = OP_REG;
4018 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4019 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4020 fetch_register_operand(op);
4021 op->orig_val = op->val;
4022 break;
4023 case OpDI:
4024 op->type = OP_MEM;
4025 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4026 op->addr.mem.ea =
dd856efa 4027 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4028 op->addr.mem.seg = VCPU_SREG_ES;
4029 op->val = 0;
b3356bf0 4030 op->count = 1;
a9945549
AK		 4031 break;
4032 case OpDX:
4033 op->type = OP_REG;
4034 op->bytes = 2;
dd856efa 4035 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4036 fetch_register_operand(op);
4037 break;
4dd6a57d
AK		 4038 case OpCL:
4039 op->bytes = 1;
dd856efa 4040 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4041 break;
4042 case OpImmByte:
4043 rc = decode_imm(ctxt, op, 1, true);
4044 break;
4045 case OpOne:
4046 op->bytes = 1;
4047 op->val = 1;
4048 break;
4049 case OpImm:
4050 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4051 break;
28867cee
AK		 4052 case OpMem8:
4053 ctxt->memop.bytes = 1;
4054 goto mem_common;
0fe59128
AK		 4055 case OpMem16:
4056 ctxt->memop.bytes = 2;
4057 goto mem_common;
4058 case OpMem32:
4059 ctxt->memop.bytes = 4;
4060 goto mem_common;
4061 case OpImmU16:
4062 rc = decode_imm(ctxt, op, 2, false);
4063 break;
4064 case OpImmU:
4065 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4066 break;
4067 case OpSI:
4068 op->type = OP_MEM;
4069 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4070 op->addr.mem.ea =
dd856efa 4071 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4072 op->addr.mem.seg = seg_override(ctxt);
4073 op->val = 0;
b3356bf0 4074 op->count = 1;
0fe59128
AK		 4075 break;
4076 case OpImmFAddr:
4077 op->type = OP_IMM;
4078 op->addr.mem.ea = ctxt->_eip;
4079 op->bytes = ctxt->op_bytes + 2;
4080 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4081 break;
4082 case OpMemFAddr:
4083 ctxt->memop.bytes = ctxt->op_bytes + 2;
4084 goto mem_common;
c191a7a0
AK		 4085 case OpES:
4086 op->val = VCPU_SREG_ES;
4087 break;
4088 case OpCS:
4089 op->val = VCPU_SREG_CS;
4090 break;
4091 case OpSS:
4092 op->val = VCPU_SREG_SS;
4093 break;
4094 case OpDS:
4095 op->val = VCPU_SREG_DS;
4096 break;
4097 case OpFS:
4098 op->val = VCPU_SREG_FS;
4099 break;
4100 case OpGS:
4101 op->val = VCPU_SREG_GS;
4102 break;
a9945549
AK		 4103 case OpImplicit:
4104 /* Special instructions do their own operand decoding. */
4105 default:
4106 op->type = OP_NONE; /* Disable writeback. */
4107 break;
4108 }
4109
4110done:
4111 return rc;
4112}
4113
ef5d75cc 4114int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4115{
dde7e6d1
AK		 4116 int rc = X86EMUL_CONTINUE;
4117 int mode = ctxt->mode;
46561646 4118 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4119 bool op_prefix = false;
46561646 4120 struct opcode opcode;
dde7e6d1 4121
f09ed83e
AK		 4122 ctxt->memop.type = OP_NONE;
4123 ctxt->memopp = NULL;
9dac77fa
AK		 4124 ctxt->_eip = ctxt->eip;
4125 ctxt->fetch.start = ctxt->_eip;
4126 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4127 if (insn_len > 0)
9dac77fa 4128 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4129
4130 switch (mode) {
4131 case X86EMUL_MODE_REAL:
4132 case X86EMUL_MODE_VM86:
4133 case X86EMUL_MODE_PROT16:
4134 def_op_bytes = def_ad_bytes = 2;
4135 break;
4136 case X86EMUL_MODE_PROT32:
4137 def_op_bytes = def_ad_bytes = 4;
4138 break;
4139#ifdef CONFIG_X86_64
4140 case X86EMUL_MODE_PROT64:
4141 def_op_bytes = 4;
4142 def_ad_bytes = 8;
4143 break;
4144#endif
4145 default:
1d2887e2 4146 return EMULATION_FAILED;
dde7e6d1
AK		 4147 }
4148
9dac77fa
AK		 4149 ctxt->op_bytes = def_op_bytes;
4150 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4151
4152 /* Legacy prefixes. */
4153 for (;;) {
e85a1085 4154 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4155 case 0x66: /* operand-size override */
0d7cdee8 4156 op_prefix = true;
dde7e6d1 4157 /* switch between 2/4 bytes */
9dac77fa 4158 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4159 break;
4160 case 0x67: /* address-size override */
4161 if (mode == X86EMUL_MODE_PROT64)
4162 /* switch between 4/8 bytes */
9dac77fa 4163 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4164 else
4165 /* switch between 2/4 bytes */
9dac77fa 4166 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4167 break;
4168 case 0x26: /* ES override */
4169 case 0x2e: /* CS override */
4170 case 0x36: /* SS override */
4171 case 0x3e: /* DS override */
9dac77fa 4172 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4173 break;
4174 case 0x64: /* FS override */
4175 case 0x65: /* GS override */
9dac77fa 4176 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4177 break;
4178 case 0x40 ... 0x4f: /* REX */
4179 if (mode != X86EMUL_MODE_PROT64)
4180 goto done_prefixes;
9dac77fa 4181 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4182 continue;
4183 case 0xf0: /* LOCK */
9dac77fa 4184 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4185 break;
4186 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4187 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4188 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4189 break;
4190 default:
4191 goto done_prefixes;
4192 }
4193
4194 /* Any legacy prefix after a REX prefix nullifies its effect. */
4195
9dac77fa 4196 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4197 }
4198
4199done_prefixes:
4200
4201 /* REX prefix. */
9dac77fa
AK		 4202 if (ctxt->rex_prefix & 8)
4203 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4204
4205 /* Opcode byte(s). */
9dac77fa 4206 opcode = opcode_table[ctxt->b];
d3ad6243 4207 /* Two-byte opcode? */
9dac77fa
AK		 4208 if (ctxt->b == 0x0f) {
4209 ctxt->twobyte = 1;
e85a1085 4210 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4211 opcode = twobyte_table[ctxt->b];
dde7e6d1 4212 }
9dac77fa 4213 ctxt->d = opcode.flags;
dde7e6d1 4214
9f4260e7
TY		 4215 if (ctxt->d & ModRM)
4216 ctxt->modrm = insn_fetch(u8, ctxt);
4217
9dac77fa
AK		 4218 while (ctxt->d & GroupMask) {
4219 switch (ctxt->d & GroupMask) {
46561646 4220 case Group:
9dac77fa 4221 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4222 opcode = opcode.u.group[goffset];
4223 break;
4224 case GroupDual:
9dac77fa
AK		 4225 goffset = (ctxt->modrm >> 3) & 7;
4226 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4227 opcode = opcode.u.gdual->mod3[goffset];
4228 else
4229 opcode = opcode.u.gdual->mod012[goffset];
4230 break;
4231 case RMExt:
9dac77fa 4232 goffset = ctxt->modrm & 7;
01de8b09 4233 opcode = opcode.u.group[goffset];
46561646
AK		 4234 break;
4235 case Prefix:
9dac77fa 4236 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4237 return EMULATION_FAILED;
9dac77fa 4238 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4239 switch (simd_prefix) {
4240 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4241 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4242 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4243 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4244 }
4245 break;
4246 default:
1d2887e2 4247 return EMULATION_FAILED;
0d7cdee8 4248 }
46561646 4249
b1ea50b2 4250 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4251 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4252 }
4253
9dac77fa
AK		 4254 ctxt->execute = opcode.u.execute;
4255 ctxt->check_perm = opcode.check_perm;
4256 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4257
4258 /* Unrecognised? */
9dac77fa 4259 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4260 return EMULATION_FAILED;
dde7e6d1 4261
9dac77fa 4262 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4263 return EMULATION_FAILED;
d867162c 4264
9dac77fa
AK		 4265 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4266 ctxt->op_bytes = 8;
dde7e6d1 4267
9dac77fa 4268 if (ctxt->d & Op3264) {
7f9b4b75 4269 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4270 ctxt->op_bytes = 8;
7f9b4b75 4271 else
9dac77fa 4272 ctxt->op_bytes = 4;
7f9b4b75
AK		 4273 }
4274
9dac77fa
AK		 4275 if (ctxt->d & Sse)
4276 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4277 else if (ctxt->d & Mmx)
4278 ctxt->op_bytes = 8;
1253791d 4279
dde7e6d1 4280 /* ModRM and SIB bytes. */
9dac77fa 4281 if (ctxt->d & ModRM) {
f09ed83e 4282 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4283 if (!ctxt->has_seg_override)
4284 set_seg_override(ctxt, ctxt->modrm_seg);
4285 } else if (ctxt->d & MemAbs)
f09ed83e 4286 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4287 if (rc != X86EMUL_CONTINUE)
4288 goto done;
4289
9dac77fa
AK		 4290 if (!ctxt->has_seg_override)
4291 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4292
f09ed83e 4293 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4294
f09ed83e
AK		 4295 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4296 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4297
dde7e6d1
AK		 4298 /*
4299 * Decode and fetch the source operand: register, memory
4300 * or immediate.
4301 */
0fe59128 4302 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4303 if (rc != X86EMUL_CONTINUE)
4304 goto done;
4305
dde7e6d1
AK		 4306 /*
4307 * Decode and fetch the second source operand: register, memory
4308 * or immediate.
4309 */
4dd6a57d 4310 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4311 if (rc != X86EMUL_CONTINUE)
4312 goto done;
4313
dde7e6d1 4314 /* Decode and fetch the destination operand: register or memory. */
a9945549 4315 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4316
4317done:
f09ed83e
AK		 4318 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4319 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4320
1d2887e2 4321 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4322}
4323
1cb3f3ae
XG		 4324bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4325{
4326 return ctxt->d & PageTable;
4327}
4328
3e2f65d5
GN		 4329static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4330{
3e2f65d5
GN		 4331 /* The second termination condition only applies for REPE
4332 * and REPNE. Test if the repeat string operation prefix is
4333 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4334 * corresponding termination condition according to:
4335 * - if REPE/REPZ and ZF = 0 then done
4336 * - if REPNE/REPNZ and ZF = 1 then done
4337 */
9dac77fa
AK		 4338 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4339 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4340 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4341 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4342 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4343 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4344 return true;
4345
4346 return false;
4347}
4348
cbe2c9d3
AK		 4349static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4350{
4351 bool fault = false;
4352
4353 ctxt->ops->get_fpu(ctxt);
4354 asm volatile("1: fwait \n\t"
4355 "2: \n\t"
4356 ".pushsection .fixup,\"ax\" \n\t"
4357 "3: \n\t"
4358 "movb $1, %[fault] \n\t"
4359 "jmp 2b \n\t"
4360 ".popsection \n\t"
4361 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4362 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4363 ctxt->ops->put_fpu(ctxt);
4364
4365 if (unlikely(fault))
4366 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4367
4368 return X86EMUL_CONTINUE;
4369}
4370
4371static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4372 struct operand *op)
4373{
4374 if (op->type == OP_MM)
4375 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4376}
4377
dd856efa 4378
7b105ca2 4379int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4380{
0225fb50 4381 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4382 int rc = X86EMUL_CONTINUE;
9dac77fa 4383 int saved_dst_type = ctxt->dst.type;
8b4caf66 4384
9dac77fa 4385 ctxt->mem_read.pos = 0;
310b5d30 4386
9dac77fa 4387 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4388 rc = emulate_ud(ctxt);
1161624f
GN		 4389 goto done;
4390 }
4391
d380a5e4 4392 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4393 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4394 rc = emulate_ud(ctxt);
d380a5e4
GN		 4395 goto done;
4396 }
4397
9dac77fa 4398 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4399 rc = emulate_ud(ctxt);
081bca0e
AK		 4400 goto done;
4401 }
4402
cbe2c9d3
AK		 4403 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4404 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4405 rc = emulate_ud(ctxt);
4406 goto done;
4407 }
4408
cbe2c9d3 4409 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4410 rc = emulate_nm(ctxt);
4411 goto done;
4412 }
4413
cbe2c9d3
AK		 4414 if (ctxt->d & Mmx) {
4415 rc = flush_pending_x87_faults(ctxt);
4416 if (rc != X86EMUL_CONTINUE)
4417 goto done;
4418 /*
4419 * Now that we know the fpu is exception safe, we can fetch
4420 * operands from it.
4421 */
4422 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4423 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4424 if (!(ctxt->d & Mov))
4425 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4426 }
4427
9dac77fa
AK		 4428 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4429 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4430 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433 }
4434
e92805ac 4435 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4436 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4437 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4438 goto done;
4439 }
4440
8ea7d6ae 4441 /* Instruction can only be executed in protected mode */
9d1b39a9 4442 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4443 rc = emulate_ud(ctxt);
4444 goto done;
4445 }
4446
d09beabd 4447 /* Do instruction specific permission checks */
9dac77fa
AK		 4448 if (ctxt->check_perm) {
4449 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4450 if (rc != X86EMUL_CONTINUE)
4451 goto done;
4452 }
4453
9dac77fa
AK		 4454 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4455 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4456 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4457 if (rc != X86EMUL_CONTINUE)
4458 goto done;
4459 }
4460
9dac77fa 4461 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4462 /* All REP prefixes have the same first termination condition */
dd856efa 4463 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4464 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4465 goto done;
4466 }
b9fa9d6b
AK		 4467 }
4468
9dac77fa
AK		 4469 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4470 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4471 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4472 if (rc != X86EMUL_CONTINUE)
8b4caf66 4473 goto done;
9dac77fa 4474 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4475 }
4476
9dac77fa
AK		 4477 if (ctxt->src2.type == OP_MEM) {
4478 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4479 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4480 if (rc != X86EMUL_CONTINUE)
4481 goto done;
4482 }
4483
9dac77fa 4484 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4485 goto special_insn;
4486
4487
9dac77fa 4488 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4489 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4490 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4491 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4492 if (rc != X86EMUL_CONTINUE)
4493 goto done;
038e51de 4494 }
9dac77fa 4495 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4496
018a98db
AK		 4497special_insn:
4498
9dac77fa
AK		 4499 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4500 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4501 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4502 if (rc != X86EMUL_CONTINUE)
4503 goto done;
4504 }
4505
9dac77fa
AK		 4506 if (ctxt->execute) {
4507 rc = ctxt->execute(ctxt);
ef65c889
AK		 4508 if (rc != X86EMUL_CONTINUE)
4509 goto done;
4510 goto writeback;
4511 }
4512
9dac77fa 4513 if (ctxt->twobyte)
6aa8b732
AK		 4514 goto twobyte_insn;
4515
9dac77fa 4516 switch (ctxt->b) {
33615aa9 4517 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4518 emulate_1op(ctxt, "inc");
33615aa9
AK		 4519 break;
4520 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4521 emulate_1op(ctxt, "dec");
33615aa9 4522 break;
6aa8b732 4523 case 0x63: /* movsxd */
8b4caf66 4524 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4525 goto cannot_emulate;
9dac77fa 4526 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4527 break;
b2833e3c 4528 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4529 if (test_cc(ctxt->b, ctxt->eflags))
4530 jmp_rel(ctxt, ctxt->src.val);
018a98db 4531 break;
7e0b54b1 4532 case 0x8d: /* lea r16/r32, m */
9dac77fa 4533 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4534 break;
3d9e77df 4535 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4536 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4537 break;
e4f973ae
TY		 4538 rc = em_xchg(ctxt);
4539 break;
e8b6fa70 4540 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4541 switch (ctxt->op_bytes) {
4542 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4543 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4544 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4545 }
4546 break;
018a98db 4547 case 0xc0 ... 0xc1:
51187683 4548 rc = em_grp2(ctxt);
018a98db 4549 break;
6e154e56 4550 case 0xcc: /* int3 */
5c5df76b
TY		 4551 rc = emulate_int(ctxt, 3);
4552 break;
6e154e56 4553 case 0xcd: /* int n */
9dac77fa 4554 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4555 break;
4556 case 0xce: /* into */
5c5df76b
TY		 4557 if (ctxt->eflags & EFLG_OF)
4558 rc = emulate_int(ctxt, 4);
6e154e56 4559 break;
018a98db 4560 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4561 rc = em_grp2(ctxt);
018a98db
AK		 4562 break;
4563 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4564 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4565 rc = em_grp2(ctxt);
018a98db 4566 break;
1a52e051 4567 case 0xe9: /* jmp rel */
db5b0762 4568 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4569 jmp_rel(ctxt, ctxt->src.val);
4570 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4571 break;
111de5d6 4572 case 0xf4: /* hlt */
6c3287f7 4573 ctxt->ops->halt(ctxt);
19fdfa0d 4574 break;
111de5d6
AK		 4575 case 0xf5: /* cmc */
4576 /* complement carry flag from eflags reg */
4577 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4578 break;
4579 case 0xf8: /* clc */
4580 ctxt->eflags &= ~EFLG_CF;
111de5d6 4581 break;
8744aa9a
MG		 4582 case 0xf9: /* stc */
4583 ctxt->eflags |= EFLG_CF;
4584 break;
fb4616f4
MG		 4585 case 0xfc: /* cld */
4586 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4587 break;
4588 case 0xfd: /* std */
4589 ctxt->eflags |= EFLG_DF;
fb4616f4 4590 break;
91269b8f
AK		 4591 default:
4592 goto cannot_emulate;
6aa8b732 4593 }
018a98db 4594
7d9ddaed
AK		 4595 if (rc != X86EMUL_CONTINUE)
4596 goto done;
4597
018a98db 4598writeback:
adddcecf 4599 rc = writeback(ctxt);
1b30eaa8 4600 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4601 goto done;
4602
5cd21917
GN		 4603 /*
4604 * restore dst type in case the decoding will be reused
4605 * (happens for string instruction )
4606 */
9dac77fa 4607 ctxt->dst.type = saved_dst_type;
5cd21917 4608
9dac77fa 4609 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4610 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4611
9dac77fa 4612 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4613 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4614
9dac77fa 4615 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4616 unsigned int count;
9dac77fa 4617 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4618 if ((ctxt->d & SrcMask) == SrcSI)
4619 count = ctxt->src.count;
4620 else
4621 count = ctxt->dst.count;
4622 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4623 -count);
3e2f65d5 4624
d2ddd1c4
GN		 4625 if (!string_insn_completed(ctxt)) {
4626 /*
4627 * Re-enter guest when pio read ahead buffer is empty
4628 * or, if it is not used, after each 1024 iteration.
4629 */
dd856efa 4630 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4631 (r->end == 0 || r->end != r->pos)) {
4632 /*
4633 * Reset read cache. Usually happens before
4634 * decode, but since instruction is restarted
4635 * we have to do it here.
4636 */
9dac77fa 4637 ctxt->mem_read.end = 0;
dd856efa 4638 writeback_registers(ctxt);
d2ddd1c4
GN		 4639 return EMULATION_RESTART;
4640 }
4641 goto done; /* skip rip writeback */
0fa6ccbd 4642 }
5cd21917 4643 }
d2ddd1c4 4644
9dac77fa 4645 ctxt->eip = ctxt->_eip;
018a98db
AK		 4646
4647done:
da9cb575
AK		 4648 if (rc == X86EMUL_PROPAGATE_FAULT)
4649 ctxt->have_exception = true;
775fde86
JR		 4650 if (rc == X86EMUL_INTERCEPTED)
4651 return EMULATION_INTERCEPTED;
4652
dd856efa
AK		 4653 if (rc == X86EMUL_CONTINUE)
4654 writeback_registers(ctxt);
4655
d2ddd1c4 4656 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4657
4658twobyte_insn:
9dac77fa 4659 switch (ctxt->b) {
018a98db 4660 case 0x09: /* wbinvd */
cfb22375 4661 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4662 break;
4663 case 0x08: /* invd */
018a98db
AK		 4664 case 0x0d: /* GrpP (prefetch) */
4665 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4666 break;
4667 case 0x20: /* mov cr, reg */
9dac77fa 4668 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4669 break;
6aa8b732 4670 case 0x21: /* mov from dr to reg */
9dac77fa 4671 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4672 break;
6aa8b732 4673 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4674 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4675 if (!test_cc(ctxt->b, ctxt->eflags))
4676 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4677 break;
b2833e3c 4678 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4679 if (test_cc(ctxt->b, ctxt->eflags))
4680 jmp_rel(ctxt, ctxt->src.val);
018a98db 4681 break;
ee45b58e 4682 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4683 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4684 break;
9bf8ea42
GT		 4685 case 0xa4: /* shld imm8, r, r/m */
4686 case 0xa5: /* shld cl, r, r/m */
761441b9 4687 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4688 break;
9bf8ea42
GT		 4689 case 0xac: /* shrd imm8, r, r/m */
4690 case 0xad: /* shrd cl, r, r/m */
761441b9 4691 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4692 break;
2a7c5b8b
GC		 4693 case 0xae: /* clflush */
4694 break;
6aa8b732 4695 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4696 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4697 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4698 : (u16) ctxt->src.val;
6aa8b732 4699 break;
6aa8b732 4700 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4701 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4702 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4703 (s16) ctxt->src.val;
6aa8b732 4704 break;
92f738a5 4705 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4706 emulate_2op_SrcV(ctxt, "add");
92f738a5 4707 /* Write back the register source. */
9dac77fa
AK		 4708 ctxt->src.val = ctxt->dst.orig_val;
4709 write_register_operand(&ctxt->src);
92f738a5 4710 break;
a012e65a 4711 case 0xc3: /* movnti */
9dac77fa
AK		 4712 ctxt->dst.bytes = ctxt->op_bytes;
4713 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4714 (u64) ctxt->src.val;
a012e65a 4715 break;
91269b8f
AK		 4716 default:
4717 goto cannot_emulate;
6aa8b732 4718 }
7d9ddaed
AK		 4719
4720 if (rc != X86EMUL_CONTINUE)
4721 goto done;
4722
6aa8b732
AK		 4723 goto writeback;
4724
4725cannot_emulate:
a0c0ab2f 4726 return EMULATION_FAILED;
6aa8b732 4727}
dd856efa
AK		 4728
4729void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4730{
4731 invalidate_registers(ctxt);
4732}
4733
4734void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4735{
4736 writeback_registers(ctxt);
4737}
Linux kernel - Deliverables
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