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KVM: emulator: emulate XLAT
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
0fe59128
AK		 64
65#define OpBits 5 /* Width of operand field */
b1ea50b2 66#define OpMask ((1ull << OpBits) - 1)
a9945549 67
6aa8b732
AK		 68/*
69 * Opcode effective-address decode tables.
70 * Note that we only emulate instructions that have at least one memory
71 * operand (excluding implicit stack references). We assume that stack
72 * references and instruction fetches will never occur in special memory
73 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
74 * not be handled.
75 */
76
77/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 78#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 79/* Destination operand type. */
a9945549
AK		 80#define DstShift 1
81#define ImplicitOps (OpImplicit << DstShift)
82#define DstReg (OpReg << DstShift)
83#define DstMem (OpMem << DstShift)
84#define DstAcc (OpAcc << DstShift)
85#define DstDI (OpDI << DstShift)
86#define DstMem64 (OpMem64 << DstShift)
87#define DstImmUByte (OpImmUByte << DstShift)
88#define DstDX (OpDX << DstShift)
89#define DstMask (OpMask << DstShift)
6aa8b732 90/* Source operand type. */
0fe59128
AK		 91#define SrcShift 6
92#define SrcNone (OpNone << SrcShift)
93#define SrcReg (OpReg << SrcShift)
94#define SrcMem (OpMem << SrcShift)
95#define SrcMem16 (OpMem16 << SrcShift)
96#define SrcMem32 (OpMem32 << SrcShift)
97#define SrcImm (OpImm << SrcShift)
98#define SrcImmByte (OpImmByte << SrcShift)
99#define SrcOne (OpOne << SrcShift)
100#define SrcImmUByte (OpImmUByte << SrcShift)
101#define SrcImmU (OpImmU << SrcShift)
102#define SrcSI (OpSI << SrcShift)
7fa57952 103#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 104#define SrcImmFAddr (OpImmFAddr << SrcShift)
105#define SrcMemFAddr (OpMemFAddr << SrcShift)
106#define SrcAcc (OpAcc << SrcShift)
107#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 108#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 109#define SrcDX (OpDX << SrcShift)
28867cee 110#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 111#define SrcMask (OpMask << SrcShift)
221192bd
MT		 112#define BitOp (1<<11)
113#define MemAbs (1<<12) /* Memory operand is absolute displacement */
114#define String (1<<13) /* String instruction (rep capable) */
115#define Stack (1<<14) /* Stack instruction (push/pop) */
116#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
117#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
118#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
119#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
120#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 121#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 122#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 123/* Generic ModRM decode. */
124#define ModRM (1<<19)
125/* Destination is only written; never read. */
126#define Mov (1<<20)
d8769fed 127/* Misc flags */
8ea7d6ae 128#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 129#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 130#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 131#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 132#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 133#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 134#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 135#define No64 (1<<28)
d5ae7ce8 136#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 137#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 138/* Source 2 operand type */
0b789eee 139#define Src2Shift (31)
4dd6a57d
AK		 140#define Src2None (OpNone << Src2Shift)
141#define Src2CL (OpCL << Src2Shift)
142#define Src2ImmByte (OpImmByte << Src2Shift)
143#define Src2One (OpOne << Src2Shift)
144#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 145#define Src2ES (OpES << Src2Shift)
146#define Src2CS (OpCS << Src2Shift)
147#define Src2SS (OpSS << Src2Shift)
148#define Src2DS (OpDS << Src2Shift)
149#define Src2FS (OpFS << Src2Shift)
150#define Src2GS (OpGS << Src2Shift)
4dd6a57d 151#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 152#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 153#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
154#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
155#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 156#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 157#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 158
d0e53325
AK		 159#define X2(x...) x, x
160#define X3(x...) X2(x), x
161#define X4(x...) X2(x), X2(x)
162#define X5(x...) X4(x), x
163#define X6(x...) X4(x), X2(x)
164#define X7(x...) X4(x), X3(x)
165#define X8(x...) X4(x), X4(x)
166#define X16(x...) X8(x), X8(x)
83babbca 167
e28bbd44
AK		 168#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
169#define FASTOP_SIZE 8
170
171/*
172 * fastop functions have a special calling convention:
173 *
174 * dst: [rdx]:rax (in/out)
175 * src: rbx (in/out)
176 * src2: rcx (in)
177 * flags: rflags (in/out)
178 *
179 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
180 * different operand sizes can be reached by calculation, rather than a jump
181 * table (which would be bigger than the code).
182 *
183 * fastop functions are declared as taking a never-defined fastop parameter,
184 * so they can't be called from C directly.
185 */
186
187struct fastop;
188
d65b1dee 189struct opcode {
b1ea50b2
AK		 190 u64 flags : 56;
191 u64 intercept : 8;
120df890 192 union {
ef65c889 193 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 194 const struct opcode *group;
195 const struct group_dual *gdual;
196 const struct gprefix *gprefix;
045a282c 197 const struct escape *esc;
e28bbd44 198 void (*fastop)(struct fastop *fake);
120df890 199 } u;
d09beabd 200 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 201};
202
203struct group_dual {
204 struct opcode mod012[8];
205 struct opcode mod3[8];
d65b1dee
AK		 206};
207
0d7cdee8
AK		 208struct gprefix {
209 struct opcode pfx_no;
210 struct opcode pfx_66;
211 struct opcode pfx_f2;
212 struct opcode pfx_f3;
213};
214
045a282c
GN		 215struct escape {
216 struct opcode op[8];
217 struct opcode high[64];
218};
219
6aa8b732 220/* EFLAGS bit definitions. */
d4c6a154
GN		 221#define EFLG_ID (1<<21)
222#define EFLG_VIP (1<<20)
223#define EFLG_VIF (1<<19)
224#define EFLG_AC (1<<18)
b1d86143
AP		 225#define EFLG_VM (1<<17)
226#define EFLG_RF (1<<16)
d4c6a154
GN		 227#define EFLG_IOPL (3<<12)
228#define EFLG_NT (1<<14)
6aa8b732
AK		 229#define EFLG_OF (1<<11)
230#define EFLG_DF (1<<10)
b1d86143 231#define EFLG_IF (1<<9)
d4c6a154 232#define EFLG_TF (1<<8)
6aa8b732
AK		 233#define EFLG_SF (1<<7)
234#define EFLG_ZF (1<<6)
235#define EFLG_AF (1<<4)
236#define EFLG_PF (1<<2)
237#define EFLG_CF (1<<0)
238
62bd430e
MG		 239#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
240#define EFLG_RESERVED_ONE_MASK 2
241
dd856efa
AK		 242static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
243{
244 if (!(ctxt->regs_valid & (1 << nr))) {
245 ctxt->regs_valid |= 1 << nr;
246 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
247 }
248 return ctxt->_regs[nr];
249}
250
251static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
252{
253 ctxt->regs_valid |= 1 << nr;
254 ctxt->regs_dirty |= 1 << nr;
255 return &ctxt->_regs[nr];
256}
257
258static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
259{
260 reg_read(ctxt, nr);
261 return reg_write(ctxt, nr);
262}
263
264static void writeback_registers(struct x86_emulate_ctxt *ctxt)
265{
266 unsigned reg;
267
268 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
269 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
270}
271
272static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
273{
274 ctxt->regs_dirty = 0;
275 ctxt->regs_valid = 0;
276}
277
6aa8b732
AK		 278/*
279 * Instruction emulation:
280 * Most instructions are emulated directly via a fragment of inline assembly
281 * code. This allows us to save/restore EFLAGS and thus very easily pick up
282 * any modified flags.
283 */
284
05b3e0c2 285#if defined(CONFIG_X86_64)
6aa8b732
AK		 286#define _LO32 "k" /* force 32-bit operand */
287#define _STK "%%rsp" /* stack pointer */
288#elif defined(__i386__)
289#define _LO32 "" /* force 32-bit operand */
290#define _STK "%%esp" /* stack pointer */
291#endif
292
293/*
294 * These EFLAGS bits are restored from saved value during emulation, and
295 * any changes are written back to the saved value after emulation.
296 */
297#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
298
299/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 300#define _PRE_EFLAGS(_sav, _msk, _tmp) \
301 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
302 "movl %"_sav",%"_LO32 _tmp"; " \
303 "push %"_tmp"; " \
304 "push %"_tmp"; " \
305 "movl %"_msk",%"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "pushf; " \
308 "notl %"_LO32 _tmp"; " \
309 "andl %"_LO32 _tmp",("_STK"); " \
310 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
311 "pop %"_tmp"; " \
312 "orl %"_LO32 _tmp",("_STK"); " \
313 "popf; " \
314 "pop %"_sav"; "
6aa8b732
AK		 315
316/* After executing instruction: write-back necessary bits in EFLAGS. */
317#define _POST_EFLAGS(_sav, _msk, _tmp) \
318 /* _sav |= EFLAGS & _msk; */ \
319 "pushf; " \
320 "pop %"_tmp"; " \
321 "andl %"_msk",%"_LO32 _tmp"; " \
322 "orl %"_LO32 _tmp",%"_sav"; "
323
dda96d8f
AK		 324#ifdef CONFIG_X86_64
325#define ON64(x) x
326#else
327#define ON64(x)
328#endif
329
a31b9cea 330#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 331 do { \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "2") \
334 _op _suffix " %"_x"3,%1; " \
335 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 336 : "=m" ((ctxt)->eflags), \
337 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 338 "=&r" (_tmp) \
a31b9cea 339 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 340 } while (0)
6b7ad61f
AK		 341
342
6aa8b732 343/* Raw emulation: instruction has two explicit operands. */
a31b9cea 344#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 345 do { \
346 unsigned long _tmp; \
347 \
a31b9cea 348 switch ((ctxt)->dst.bytes) { \
6b7ad61f 349 case 2: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 351 break; \
352 case 4: \
a31b9cea 353 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 354 break; \
355 case 8: \
a31b9cea 356 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 357 break; \
358 } \
6aa8b732
AK		 359 } while (0)
360
a31b9cea 361#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 362 do { \
6b7ad61f 363 unsigned long _tmp; \
a31b9cea 364 switch ((ctxt)->dst.bytes) { \
6aa8b732 365 case 1: \
a31b9cea 366 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 367 break; \
368 default: \
a31b9cea 369 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 370 _wx, _wy, _lx, _ly, _qx, _qy); \
371 break; \
372 } \
373 } while (0)
374
375/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 376#define emulate_2op_SrcB(ctxt, _op) \
377 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 378
379/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 380#define emulate_2op_SrcV(ctxt, _op) \
381 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 382
383/* Source operand is word, long or quad sized. */
a31b9cea
AK		 384#define emulate_2op_SrcV_nobyte(ctxt, _op) \
385 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 386
d175226a 387/* Instruction has three operands and one operand is stored in ECX register */
29053a60 388#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 389 do { \
390 unsigned long _tmp; \
761441b9
AK		 391 _type _clv = (ctxt)->src2.val; \
392 _type _srcv = (ctxt)->src.val; \
393 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 394 \
395 __asm__ __volatile__ ( \
396 _PRE_EFLAGS("0", "5", "2") \
397 _op _suffix " %4,%1 \n" \
398 _POST_EFLAGS("0", "5", "2") \
761441b9 399 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 400 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
401 ); \
402 \
761441b9
AK		 403 (ctxt)->src2.val = (unsigned long) _clv; \
404 (ctxt)->src2.val = (unsigned long) _srcv; \
405 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 406 } while (0)
407
761441b9 408#define emulate_2op_cl(ctxt, _op) \
7295261c 409 do { \
761441b9 410 switch ((ctxt)->dst.bytes) { \
7295261c 411 case 2: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 413 break; \
414 case 4: \
29053a60 415 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 416 break; \
417 case 8: \
29053a60 418 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 419 break; \
420 } \
d175226a
GT		 421 } while (0)
422
d1eef45d 423#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 424 do { \
425 unsigned long _tmp; \
426 \
dda96d8f
AK		 427 __asm__ __volatile__ ( \
428 _PRE_EFLAGS("0", "3", "2") \
429 _op _suffix " %1; " \
430 _POST_EFLAGS("0", "3", "2") \
d1eef45d 431 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 432 "=&r" (_tmp) \
433 : "i" (EFLAGS_MASK)); \
434 } while (0)
435
436/* Instruction has only one explicit operand (no source operand). */
d1eef45d 437#define emulate_1op(ctxt, _op) \
dda96d8f 438 do { \
d1eef45d
AK		 439 switch ((ctxt)->dst.bytes) { \
440 case 1: __emulate_1op(ctxt, _op, "b"); break; \
441 case 2: __emulate_1op(ctxt, _op, "w"); break; \
442 case 4: __emulate_1op(ctxt, _op, "l"); break; \
443 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 444 } \
445 } while (0)
446
4d758349
AK		 447static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
448
b7d491e7
AK		 449#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
450#define FOP_RET "ret \n\t"
451
452#define FOP_START(op) \
453 extern void em_##op(struct fastop *fake); \
454 asm(".pushsection .text, \"ax\" \n\t" \
455 ".global em_" #op " \n\t" \
456 FOP_ALIGN \
457 "em_" #op ": \n\t"
458
459#define FOP_END \
460 ".popsection")
461
0bdea068
AK		 462#define FOPNOP() FOP_ALIGN FOP_RET
463
b7d491e7
AK		 464#define FOP1E(op, dst) \
465 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
466
467#define FASTOP1(op) \
468 FOP_START(op) \
469 FOP1E(op##b, al) \
470 FOP1E(op##w, ax) \
471 FOP1E(op##l, eax) \
472 ON64(FOP1E(op##q, rax)) \
473 FOP_END
474
f7857f35
AK		 475#define FOP2E(op, dst, src) \
476 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
477
478#define FASTOP2(op) \
479 FOP_START(op) \
480 FOP2E(op##b, al, bl) \
481 FOP2E(op##w, ax, bx) \
482 FOP2E(op##l, eax, ebx) \
483 ON64(FOP2E(op##q, rax, rbx)) \
484 FOP_END
485
11c363ba
AK		 486/* 2 operand, word only */
487#define FASTOP2W(op) \
488 FOP_START(op) \
489 FOPNOP() \
490 FOP2E(op##w, ax, bx) \
491 FOP2E(op##l, eax, ebx) \
492 ON64(FOP2E(op##q, rax, rbx)) \
493 FOP_END
494
007a3b54
AK		 495/* 2 operand, src is CL */
496#define FASTOP2CL(op) \
497 FOP_START(op) \
498 FOP2E(op##b, al, cl) \
499 FOP2E(op##w, ax, cl) \
500 FOP2E(op##l, eax, cl) \
501 ON64(FOP2E(op##q, rax, cl)) \
502 FOP_END
503
0bdea068
AK		 504#define FOP3E(op, dst, src, src2) \
505 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
506
507/* 3-operand, word-only, src2=cl */
508#define FASTOP3WCL(op) \
509 FOP_START(op) \
510 FOPNOP() \
511 FOP3E(op##w, ax, bx, cl) \
512 FOP3E(op##l, eax, ebx, cl) \
513 ON64(FOP3E(op##q, rax, rbx, cl)) \
514 FOP_END
515
9ae9feba
AK		 516/* Special case for SETcc - 1 instruction per cc */
517#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
518
519FOP_START(setcc)
520FOP_SETCC(seto)
521FOP_SETCC(setno)
522FOP_SETCC(setc)
523FOP_SETCC(setnc)
524FOP_SETCC(setz)
525FOP_SETCC(setnz)
526FOP_SETCC(setbe)
527FOP_SETCC(setnbe)
528FOP_SETCC(sets)
529FOP_SETCC(setns)
530FOP_SETCC(setp)
531FOP_SETCC(setnp)
532FOP_SETCC(setl)
533FOP_SETCC(setnl)
534FOP_SETCC(setle)
535FOP_SETCC(setnle)
536FOP_END;
537
e8f2b1d6 538#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 539 do { \
540 unsigned long _tmp; \
dd856efa
AK		 541 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
542 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 543 \
544 __asm__ __volatile__ ( \
545 _PRE_EFLAGS("0", "5", "1") \
546 "1: \n\t" \
547 _op _suffix " %6; " \
548 "2: \n\t" \
549 _POST_EFLAGS("0", "5", "1") \
550 ".pushsection .fixup,\"ax\" \n\t" \
551 "3: movb $1, %4 \n\t" \
552 "jmp 2b \n\t" \
553 ".popsection \n\t" \
554 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 555 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
556 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 557 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 558 } while (0)
559
3f9f53b0 560/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 561#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 562 do { \
e8f2b1d6 563 switch((ctxt)->src.bytes) { \
7295261c 564 case 1: \
e8f2b1d6 565 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 566 break; \
567 case 2: \
e8f2b1d6 568 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 569 break; \
570 case 4: \
e8f2b1d6 571 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 572 break; \
573 case 8: ON64( \
e8f2b1d6 574 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 575 break; \
576 } \
577 } while (0)
578
8a76d7f2
JR		 579static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
580 enum x86_intercept intercept,
581 enum x86_intercept_stage stage)
582{
583 struct x86_instruction_info info = {
584 .intercept = intercept,
9dac77fa
AK		 585 .rep_prefix = ctxt->rep_prefix,
586 .modrm_mod = ctxt->modrm_mod,
587 .modrm_reg = ctxt->modrm_reg,
588 .modrm_rm = ctxt->modrm_rm,
589 .src_val = ctxt->src.val64,
590 .src_bytes = ctxt->src.bytes,
591 .dst_bytes = ctxt->dst.bytes,
592 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 593 .next_rip = ctxt->eip,
594 };
595
2953538e 596 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 597}
598
f47cfa31
AK		 599static void assign_masked(ulong *dest, ulong src, ulong mask)
600{
601 *dest = (*dest & ~mask) | (src & mask);
602}
603
9dac77fa 604static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 605{
9dac77fa 606 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 607}
608
f47cfa31
AK		 609static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
610{
611 u16 sel;
612 struct desc_struct ss;
613
614 if (ctxt->mode == X86EMUL_MODE_PROT64)
615 return ~0UL;
616 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
617 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
618}
619
612e89f0
AK		 620static int stack_size(struct x86_emulate_ctxt *ctxt)
621{
622 return (__fls(stack_mask(ctxt)) + 1) >> 3;
623}
624
6aa8b732 625/* Access/update address held in a register, based on addressing mode. */
e4706772 626static inline unsigned long
9dac77fa 627address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 628{
9dac77fa 629 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 630 return reg;
631 else
9dac77fa 632 return reg & ad_mask(ctxt);
e4706772
HH		 633}
634
635static inline unsigned long
9dac77fa 636register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 637{
9dac77fa 638 return address_mask(ctxt, reg);
e4706772
HH		 639}
640
5ad105e5
AK		 641static void masked_increment(ulong *reg, ulong mask, int inc)
642{
643 assign_masked(reg, *reg + inc, mask);
644}
645
7a957275 646static inline void
9dac77fa 647register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 648{
5ad105e5
AK		 649 ulong mask;
650
9dac77fa 651 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 652 mask = ~0UL;
7a957275 653 else
5ad105e5
AK		 654 mask = ad_mask(ctxt);
655 masked_increment(reg, mask, inc);
656}
657
658static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
659{
dd856efa 660 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 661}
6aa8b732 662
9dac77fa 663static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 664{
9dac77fa 665 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 666}
098c937b 667
56697687
AK		 668static u32 desc_limit_scaled(struct desc_struct *desc)
669{
670 u32 limit = get_desc_limit(desc);
671
672 return desc->g ? (limit << 12) | 0xfff : limit;
673}
674
9dac77fa 675static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 676{
9dac77fa
AK		 677 ctxt->has_seg_override = true;
678 ctxt->seg_override = seg;
7a5b56df
AK		 679}
680
7b105ca2 681static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 682{
683 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
684 return 0;
685
7b105ca2 686 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 687}
688
9dac77fa 689static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 690{
9dac77fa 691 if (!ctxt->has_seg_override)
7a5b56df
AK		 692 return 0;
693
9dac77fa 694 return ctxt->seg_override;
7a5b56df
AK		 695}
696
35d3d4a1
AK		 697static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
698 u32 error, bool valid)
54b8486f 699{
da9cb575
AK		 700 ctxt->exception.vector = vec;
701 ctxt->exception.error_code = error;
702 ctxt->exception.error_code_valid = valid;
35d3d4a1 703 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 704}
705
3b88e41a
JR		 706static int emulate_db(struct x86_emulate_ctxt *ctxt)
707{
708 return emulate_exception(ctxt, DB_VECTOR, 0, false);
709}
710
35d3d4a1 711static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 712{
35d3d4a1 713 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 714}
715
618ff15d
AK		 716static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
717{
718 return emulate_exception(ctxt, SS_VECTOR, err, true);
719}
720
35d3d4a1 721static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 722{
35d3d4a1 723 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 724}
725
35d3d4a1 726static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 727{
35d3d4a1 728 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 729}
730
34d1f490
AK		 731static int emulate_de(struct x86_emulate_ctxt *ctxt)
732{
35d3d4a1 733 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 734}
735
1253791d
AK		 736static int emulate_nm(struct x86_emulate_ctxt *ctxt)
737{
738 return emulate_exception(ctxt, NM_VECTOR, 0, false);
739}
740
1aa36616
AK		 741static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
742{
743 u16 selector;
744 struct desc_struct desc;
745
746 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
747 return selector;
748}
749
750static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
751 unsigned seg)
752{
753 u16 dummy;
754 u32 base3;
755 struct desc_struct desc;
756
757 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
758 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
759}
760
1c11b376
AK		 761/*
762 * x86 defines three classes of vector instructions: explicitly
763 * aligned, explicitly unaligned, and the rest, which change behaviour
764 * depending on whether they're AVX encoded or not.
765 *
766 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
767 * subject to the same check.
768 */
769static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
770{
771 if (likely(size < 16))
772 return false;
773
774 if (ctxt->d & Aligned)
775 return true;
776 else if (ctxt->d & Unaligned)
777 return false;
778 else if (ctxt->d & Avx)
779 return false;
780 else
781 return true;
782}
783
3d9b938e 784static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 785 struct segmented_address addr,
3d9b938e 786 unsigned size, bool write, bool fetch,
52fd8b44
AK		 787 ulong *linear)
788{
618ff15d
AK		 789 struct desc_struct desc;
790 bool usable;
52fd8b44 791 ulong la;
618ff15d 792 u32 lim;
1aa36616 793 u16 sel;
3a78a4f4 794 unsigned cpl;
52fd8b44 795
7b105ca2 796 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 797 switch (ctxt->mode) {
618ff15d
AK		 798 case X86EMUL_MODE_PROT64:
799 if (((signed long)la << 16) >> 16 != la)
800 return emulate_gp(ctxt, 0);
801 break;
802 default:
1aa36616
AK		 803 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
804 addr.seg);
618ff15d
AK		 805 if (!usable)
806 goto bad;
58b7825b
GN		 807 /* code segment in protected mode or read-only data segment */
808 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
809 || !(desc.type & 2)) && write)
618ff15d
AK		 810 goto bad;
811 /* unreadable code segment */
3d9b938e 812 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 813 goto bad;
814 lim = desc_limit_scaled(&desc);
815 if ((desc.type & 8) || !(desc.type & 4)) {
816 /* expand-up segment */
817 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
818 goto bad;
819 } else {
fc058680 820 /* expand-down segment */
618ff15d
AK		 821 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
822 goto bad;
823 lim = desc.d ? 0xffffffff : 0xffff;
824 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
825 goto bad;
826 }
717746e3 827 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 828 if (!(desc.type & 8)) {
829 /* data segment */
830 if (cpl > desc.dpl)
831 goto bad;
832 } else if ((desc.type & 8) && !(desc.type & 4)) {
833 /* nonconforming code segment */
834 if (cpl != desc.dpl)
835 goto bad;
836 } else if ((desc.type & 8) && (desc.type & 4)) {
837 /* conforming code segment */
838 if (cpl < desc.dpl)
839 goto bad;
840 }
841 break;
842 }
9dac77fa 843 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 844 la &= (u32)-1;
1c11b376
AK		 845 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
846 return emulate_gp(ctxt, 0);
52fd8b44
AK		 847 *linear = la;
848 return X86EMUL_CONTINUE;
618ff15d
AK		 849bad:
850 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 851 return emulate_ss(ctxt, sel);
618ff15d 852 else
0afbe2f8 853 return emulate_gp(ctxt, sel);
52fd8b44
AK		 854}
855
3d9b938e
NE		 856static int linearize(struct x86_emulate_ctxt *ctxt,
857 struct segmented_address addr,
858 unsigned size, bool write,
859 ulong *linear)
860{
861 return __linearize(ctxt, addr, size, write, false, linear);
862}
863
864
3ca3ac4d
AK		 865static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
866 struct segmented_address addr,
867 void *data,
868 unsigned size)
869{
9fa088f4
AK		 870 int rc;
871 ulong linear;
872
83b8795a 873 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 874 if (rc != X86EMUL_CONTINUE)
875 return rc;
0f65dd70 876 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 877}
878
807941b1
TY		 879/*
880 * Fetch the next byte of the instruction being emulated which is pointed to
881 * by ctxt->_eip, then increment ctxt->_eip.
882 *
883 * Also prefetch the remaining bytes of the instruction without crossing page
884 * boundary if they are not in fetch_cache yet.
885 */
886static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 887{
9dac77fa 888 struct fetch_cache *fc = &ctxt->fetch;
62266869 889 int rc;
2fb53ad8 890 int size, cur_size;
62266869 891
807941b1 892 if (ctxt->_eip == fc->end) {
3d9b938e 893 unsigned long linear;
807941b1
TY		 894 struct segmented_address addr = { .seg = VCPU_SREG_CS,
895 .ea = ctxt->_eip };
2fb53ad8 896 cur_size = fc->end - fc->start;
807941b1
TY		 897 size = min(15UL - cur_size,
898 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 899 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 900 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 901 return rc;
ef5d75cc
TY		 902 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
903 size, &ctxt->exception);
7d88bb48 904 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 905 return rc;
2fb53ad8 906 fc->end += size;
62266869 907 }
807941b1
TY		 908 *dest = fc->data[ctxt->_eip - fc->start];
909 ctxt->_eip++;
3e2815e9 910 return X86EMUL_CONTINUE;
62266869
AK		 911}
912
913static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 914 void *dest, unsigned size)
62266869 915{
3e2815e9 916 int rc;
62266869 917
eb3c79e6 918 /* x86 instructions are limited to 15 bytes. */
7d88bb48 919 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 920 return X86EMUL_UNHANDLEABLE;
62266869 921 while (size--) {
807941b1 922 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 923 if (rc != X86EMUL_CONTINUE)
62266869
AK		 924 return rc;
925 }
3e2815e9 926 return X86EMUL_CONTINUE;
62266869
AK		 927}
928
67cbc90d 929/* Fetch next part of the instruction being emulated. */
e85a1085 930#define insn_fetch(_type, _ctxt) \
67cbc90d 931({ unsigned long _x; \
e85a1085 932 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 933 if (rc != X86EMUL_CONTINUE) \
934 goto done; \
67cbc90d
TY		 935 (_type)_x; \
936})
937
807941b1
TY		 938#define insn_fetch_arr(_arr, _size, _ctxt) \
939({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 940 if (rc != X86EMUL_CONTINUE) \
941 goto done; \
67cbc90d
TY		 942})
943
1e3c5cb0
RR		 944/*
945 * Given the 'reg' portion of a ModRM byte, and a register block, return a
946 * pointer into the block that addresses the relevant register.
947 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
948 */
dd856efa 949static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 950 int highbyte_regs)
6aa8b732
AK		 951{
952 void *p;
953
6aa8b732 954 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 955 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
956 else
957 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 958 return p;
959}
960
961static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 962 struct segmented_address addr,
6aa8b732
AK		 963 u16 *size, unsigned long *address, int op_bytes)
964{
965 int rc;
966
967 if (op_bytes == 2)
968 op_bytes = 3;
969 *address = 0;
3ca3ac4d 970 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 971 if (rc != X86EMUL_CONTINUE)
6aa8b732 972 return rc;
30b31ab6 973 addr.ea += 2;
3ca3ac4d 974 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 975 return rc;
976}
977
34b77652
AK		 978FASTOP2(add);
979FASTOP2(or);
980FASTOP2(adc);
981FASTOP2(sbb);
982FASTOP2(and);
983FASTOP2(sub);
984FASTOP2(xor);
985FASTOP2(cmp);
986FASTOP2(test);
987
988FASTOP3WCL(shld);
989FASTOP3WCL(shrd);
990
991FASTOP2W(imul);
992
993FASTOP1(not);
994FASTOP1(neg);
995FASTOP1(inc);
996FASTOP1(dec);
997
998FASTOP2CL(rol);
999FASTOP2CL(ror);
1000FASTOP2CL(rcl);
1001FASTOP2CL(rcr);
1002FASTOP2CL(shl);
1003FASTOP2CL(shr);
1004FASTOP2CL(sar);
1005
1006FASTOP2W(bsf);
1007FASTOP2W(bsr);
1008FASTOP2W(bt);
1009FASTOP2W(bts);
1010FASTOP2W(btr);
1011FASTOP2W(btc);
1012
9ae9feba 1013static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1014{
9ae9feba
AK		 1015 u8 rc;
1016 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1017
9ae9feba 1018 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1019 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1020 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1021 return rc;
bbe9abbd
NK		 1022}
1023
91ff3cb4
AK		 1024static void fetch_register_operand(struct operand *op)
1025{
1026 switch (op->bytes) {
1027 case 1:
1028 op->val = *(u8 *)op->addr.reg;
1029 break;
1030 case 2:
1031 op->val = *(u16 *)op->addr.reg;
1032 break;
1033 case 4:
1034 op->val = *(u32 *)op->addr.reg;
1035 break;
1036 case 8:
1037 op->val = *(u64 *)op->addr.reg;
1038 break;
1039 }
1040}
1041
1253791d
AK		 1042static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1043{
1044 ctxt->ops->get_fpu(ctxt);
1045 switch (reg) {
89a87c67
MK		 1046 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1047 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1048 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1049 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1050 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1051 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1052 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1053 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1054#ifdef CONFIG_X86_64
89a87c67
MK		 1055 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1056 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1057 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1058 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1059 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1060 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1061 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1062 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1063#endif
1064 default: BUG();
1065 }
1066 ctxt->ops->put_fpu(ctxt);
1067}
1068
1069static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1070 int reg)
1071{
1072 ctxt->ops->get_fpu(ctxt);
1073 switch (reg) {
89a87c67
MK		 1074 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1075 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1076 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1077 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1078 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1079 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1080 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1081 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1082#ifdef CONFIG_X86_64
89a87c67
MK		 1083 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1084 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1085 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1086 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1087 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1088 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1089 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1090 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1091#endif
1092 default: BUG();
1093 }
1094 ctxt->ops->put_fpu(ctxt);
1095}
1096
cbe2c9d3
AK		 1097static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1098{
1099 ctxt->ops->get_fpu(ctxt);
1100 switch (reg) {
1101 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1102 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1103 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1104 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1105 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1106 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1107 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1108 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1109 default: BUG();
1110 }
1111 ctxt->ops->put_fpu(ctxt);
1112}
1113
1114static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1115{
1116 ctxt->ops->get_fpu(ctxt);
1117 switch (reg) {
1118 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1119 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1120 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1121 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1122 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1123 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1124 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1125 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1126 default: BUG();
1127 }
1128 ctxt->ops->put_fpu(ctxt);
1129}
1130
045a282c
GN		 1131static int em_fninit(struct x86_emulate_ctxt *ctxt)
1132{
1133 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1134 return emulate_nm(ctxt);
1135
1136 ctxt->ops->get_fpu(ctxt);
1137 asm volatile("fninit");
1138 ctxt->ops->put_fpu(ctxt);
1139 return X86EMUL_CONTINUE;
1140}
1141
1142static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1143{
1144 u16 fcw;
1145
1146 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1147 return emulate_nm(ctxt);
1148
1149 ctxt->ops->get_fpu(ctxt);
1150 asm volatile("fnstcw %0": "+m"(fcw));
1151 ctxt->ops->put_fpu(ctxt);
1152
1153 /* force 2 byte destination */
1154 ctxt->dst.bytes = 2;
1155 ctxt->dst.val = fcw;
1156
1157 return X86EMUL_CONTINUE;
1158}
1159
1160static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1161{
1162 u16 fsw;
1163
1164 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1165 return emulate_nm(ctxt);
1166
1167 ctxt->ops->get_fpu(ctxt);
1168 asm volatile("fnstsw %0": "+m"(fsw));
1169 ctxt->ops->put_fpu(ctxt);
1170
1171 /* force 2 byte destination */
1172 ctxt->dst.bytes = 2;
1173 ctxt->dst.val = fsw;
1174
1175 return X86EMUL_CONTINUE;
1176}
1177
1253791d 1178static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1179 struct operand *op)
3c118e24 1180{
9dac77fa
AK		 1181 unsigned reg = ctxt->modrm_reg;
1182 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1183
9dac77fa
AK		 1184 if (!(ctxt->d & ModRM))
1185 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1186
9dac77fa 1187 if (ctxt->d & Sse) {
1253791d
AK		 1188 op->type = OP_XMM;
1189 op->bytes = 16;
1190 op->addr.xmm = reg;
1191 read_sse_reg(ctxt, &op->vec_val, reg);
1192 return;
1193 }
cbe2c9d3
AK		 1194 if (ctxt->d & Mmx) {
1195 reg &= 7;
1196 op->type = OP_MM;
1197 op->bytes = 8;
1198 op->addr.mm = reg;
1199 return;
1200 }
1253791d 1201
3c118e24 1202 op->type = OP_REG;
2adb5ad9 1203 if (ctxt->d & ByteOp) {
dd856efa 1204 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1205 op->bytes = 1;
1206 } else {
dd856efa 1207 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1208 op->bytes = ctxt->op_bytes;
3c118e24 1209 }
91ff3cb4 1210 fetch_register_operand(op);
3c118e24
AK		 1211 op->orig_val = op->val;
1212}
1213
a6e3407b
AK		 1214static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1215{
1216 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1217 ctxt->modrm_seg = VCPU_SREG_SS;
1218}
1219
1c73ef66 1220static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1221 struct operand *op)
1c73ef66 1222{
1c73ef66 1223 u8 sib;
f5b4edcd 1224 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1225 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1226 ulong modrm_ea = 0;
1c73ef66 1227
9dac77fa
AK		 1228 if (ctxt->rex_prefix) {
1229 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1230 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1231 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1232 }
1233
9dac77fa
AK		 1234 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1235 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1236 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1237 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1238
9dac77fa 1239 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1240 op->type = OP_REG;
9dac77fa 1241 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1242 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1243 if (ctxt->d & Sse) {
1253791d
AK		 1244 op->type = OP_XMM;
1245 op->bytes = 16;
9dac77fa
AK		 1246 op->addr.xmm = ctxt->modrm_rm;
1247 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1248 return rc;
1249 }
cbe2c9d3
AK		 1250 if (ctxt->d & Mmx) {
1251 op->type = OP_MM;
1252 op->bytes = 8;
1253 op->addr.xmm = ctxt->modrm_rm & 7;
1254 return rc;
1255 }
2dbd0dd7 1256 fetch_register_operand(op);
1c73ef66
AK		 1257 return rc;
1258 }
1259
2dbd0dd7
AK		 1260 op->type = OP_MEM;
1261
9dac77fa 1262 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1263 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1264 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1265 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1266 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1267
1268 /* 16-bit ModR/M decode. */
9dac77fa 1269 switch (ctxt->modrm_mod) {
1c73ef66 1270 case 0:
9dac77fa 1271 if (ctxt->modrm_rm == 6)
e85a1085 1272 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1273 break;
1274 case 1:
e85a1085 1275 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1276 break;
1277 case 2:
e85a1085 1278 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1279 break;
1280 }
9dac77fa 1281 switch (ctxt->modrm_rm) {
1c73ef66 1282 case 0:
2dbd0dd7 1283 modrm_ea += bx + si;
1c73ef66
AK		 1284 break;
1285 case 1:
2dbd0dd7 1286 modrm_ea += bx + di;
1c73ef66
AK		 1287 break;
1288 case 2:
2dbd0dd7 1289 modrm_ea += bp + si;
1c73ef66
AK		 1290 break;
1291 case 3:
2dbd0dd7 1292 modrm_ea += bp + di;
1c73ef66
AK		 1293 break;
1294 case 4:
2dbd0dd7 1295 modrm_ea += si;
1c73ef66
AK		 1296 break;
1297 case 5:
2dbd0dd7 1298 modrm_ea += di;
1c73ef66
AK		 1299 break;
1300 case 6:
9dac77fa 1301 if (ctxt->modrm_mod != 0)
2dbd0dd7 1302 modrm_ea += bp;
1c73ef66
AK		 1303 break;
1304 case 7:
2dbd0dd7 1305 modrm_ea += bx;
1c73ef66
AK		 1306 break;
1307 }
9dac77fa
AK		 1308 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1309 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1310 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1311 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1312 } else {
1313 /* 32/64-bit ModR/M decode. */
9dac77fa 1314 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1315 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1316 index_reg |= (sib >> 3) & 7;
1317 base_reg |= sib & 7;
1318 scale = sib >> 6;
1319
9dac77fa 1320 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1321 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1322 else {
dd856efa 1323 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1324 adjust_modrm_seg(ctxt, base_reg);
1325 }
dc71d0f1 1326 if (index_reg != 4)
dd856efa 1327 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1328 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1329 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1330 ctxt->rip_relative = 1;
a6e3407b
AK		 1331 } else {
1332 base_reg = ctxt->modrm_rm;
dd856efa 1333 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1334 adjust_modrm_seg(ctxt, base_reg);
1335 }
9dac77fa 1336 switch (ctxt->modrm_mod) {
1c73ef66 1337 case 0:
9dac77fa 1338 if (ctxt->modrm_rm == 5)
e85a1085 1339 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1340 break;
1341 case 1:
e85a1085 1342 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1343 break;
1344 case 2:
e85a1085 1345 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1346 break;
1347 }
1348 }
90de84f5 1349 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1350done:
1351 return rc;
1352}
1353
1354static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1355 struct operand *op)
1c73ef66 1356{
3e2815e9 1357 int rc = X86EMUL_CONTINUE;
1c73ef66 1358
2dbd0dd7 1359 op->type = OP_MEM;
9dac77fa 1360 switch (ctxt->ad_bytes) {
1c73ef66 1361 case 2:
e85a1085 1362 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1363 break;
1364 case 4:
e85a1085 1365 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1366 break;
1367 case 8:
e85a1085 1368 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1369 break;
1370 }
1371done:
1372 return rc;
1373}
1374
9dac77fa 1375static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1376{
7129eeca 1377 long sv = 0, mask;
35c843c4 1378
9dac77fa
AK		 1379 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1380 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1381
9dac77fa
AK		 1382 if (ctxt->src.bytes == 2)
1383 sv = (s16)ctxt->src.val & (s16)mask;
1384 else if (ctxt->src.bytes == 4)
1385 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1386
9dac77fa 1387 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1388 }
ba7ff2b7
WY		 1389
1390 /* only subword offset */
9dac77fa 1391 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1392}
1393
dde7e6d1 1394static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1395 unsigned long addr, void *dest, unsigned size)
6aa8b732 1396{
dde7e6d1 1397 int rc;
9dac77fa 1398 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1399
f23b070e
XG		 1400 if (mc->pos < mc->end)
1401 goto read_cached;
6aa8b732 1402
f23b070e
XG		 1403 WARN_ON((mc->end + size) >= sizeof(mc->data));
1404
1405 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1406 &ctxt->exception);
1407 if (rc != X86EMUL_CONTINUE)
1408 return rc;
1409
1410 mc->end += size;
1411
1412read_cached:
1413 memcpy(dest, mc->data + mc->pos, size);
1414 mc->pos += size;
dde7e6d1
AK		 1415 return X86EMUL_CONTINUE;
1416}
6aa8b732 1417
3ca3ac4d
AK		 1418static int segmented_read(struct x86_emulate_ctxt *ctxt,
1419 struct segmented_address addr,
1420 void *data,
1421 unsigned size)
1422{
9fa088f4
AK		 1423 int rc;
1424 ulong linear;
1425
83b8795a 1426 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1427 if (rc != X86EMUL_CONTINUE)
1428 return rc;
7b105ca2 1429 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1430}
1431
1432static int segmented_write(struct x86_emulate_ctxt *ctxt,
1433 struct segmented_address addr,
1434 const void *data,
1435 unsigned size)
1436{
9fa088f4
AK		 1437 int rc;
1438 ulong linear;
1439
83b8795a 1440 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1441 if (rc != X86EMUL_CONTINUE)
1442 return rc;
0f65dd70
AK		 1443 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1444 &ctxt->exception);
3ca3ac4d
AK		 1445}
1446
1447static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1448 struct segmented_address addr,
1449 const void *orig_data, const void *data,
1450 unsigned size)
1451{
9fa088f4
AK		 1452 int rc;
1453 ulong linear;
1454
83b8795a 1455 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1456 if (rc != X86EMUL_CONTINUE)
1457 return rc;
0f65dd70
AK		 1458 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1459 size, &ctxt->exception);
3ca3ac4d
AK		 1460}
1461
dde7e6d1 1462static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1463 unsigned int size, unsigned short port,
1464 void *dest)
1465{
9dac77fa 1466 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1467
dde7e6d1 1468 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1469 unsigned int in_page, n;
9dac77fa 1470 unsigned int count = ctxt->rep_prefix ?
dd856efa 1471 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1472 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1473 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1474 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1475 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1476 count);
1477 if (n == 0)
1478 n = 1;
1479 rc->pos = rc->end = 0;
7b105ca2 1480 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1481 return 0;
1482 rc->end = n * size;
6aa8b732
AK		 1483 }
1484
b3356bf0
GN		 1485 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1486 ctxt->dst.data = rc->data + rc->pos;
1487 ctxt->dst.type = OP_MEM_STR;
1488 ctxt->dst.count = (rc->end - rc->pos) / size;
1489 rc->pos = rc->end;
1490 } else {
1491 memcpy(dest, rc->data + rc->pos, size);
1492 rc->pos += size;
1493 }
dde7e6d1
AK		 1494 return 1;
1495}
6aa8b732 1496
7f3d35fd
KW		 1497static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1498 u16 index, struct desc_struct *desc)
1499{
1500 struct desc_ptr dt;
1501 ulong addr;
1502
1503 ctxt->ops->get_idt(ctxt, &dt);
1504
1505 if (dt.size < index * 8 + 7)
1506 return emulate_gp(ctxt, index << 3 | 0x2);
1507
1508 addr = dt.address + index * 8;
1509 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1510 &ctxt->exception);
1511}
1512
dde7e6d1 1513static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1514 u16 selector, struct desc_ptr *dt)
1515{
0225fb50 1516 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1517
dde7e6d1
AK		 1518 if (selector & 1 << 2) {
1519 struct desc_struct desc;
1aa36616
AK		 1520 u16 sel;
1521
dde7e6d1 1522 memset (dt, 0, sizeof *dt);
1aa36616 1523 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1524 return;
e09d082c 1525
dde7e6d1
AK		 1526 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1527 dt->address = get_desc_base(&desc);
1528 } else
4bff1e86 1529 ops->get_gdt(ctxt, dt);
dde7e6d1 1530}
120df890 1531
dde7e6d1
AK		 1532/* allowed just for 8 bytes segments */
1533static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1534 u16 selector, struct desc_struct *desc,
1535 ulong *desc_addr_p)
dde7e6d1
AK		 1536{
1537 struct desc_ptr dt;
1538 u16 index = selector >> 3;
dde7e6d1 1539 ulong addr;
120df890 1540
7b105ca2 1541 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1542
35d3d4a1
AK		 1543 if (dt.size < index * 8 + 7)
1544 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1545
e919464b 1546 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1547 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1548 &ctxt->exception);
dde7e6d1 1549}
ef65c889 1550
dde7e6d1
AK		 1551/* allowed just for 8 bytes segments */
1552static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1553 u16 selector, struct desc_struct *desc)
1554{
1555 struct desc_ptr dt;
1556 u16 index = selector >> 3;
dde7e6d1 1557 ulong addr;
6aa8b732 1558
7b105ca2 1559 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1560
35d3d4a1
AK		 1561 if (dt.size < index * 8 + 7)
1562 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1563
dde7e6d1 1564 addr = dt.address + index * 8;
7b105ca2
TY		 1565 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1566 &ctxt->exception);
dde7e6d1 1567}
c7e75a3d 1568
5601d05b 1569/* Does not support long mode */
dde7e6d1 1570static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1571 u16 selector, int seg)
1572{
869be99c 1573 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1574 u8 dpl, rpl, cpl;
1575 unsigned err_vec = GP_VECTOR;
1576 u32 err_code = 0;
1577 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1578 ulong desc_addr;
dde7e6d1 1579 int ret;
03ebebeb 1580 u16 dummy;
69f55cb1 1581
dde7e6d1 1582 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1583
f8da94e9
KW		 1584 if (ctxt->mode == X86EMUL_MODE_REAL) {
1585 /* set real mode segment descriptor (keep limit etc. for
1586 * unreal mode) */
03ebebeb 1587 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1588 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1589 goto load;
f8da94e9
KW		 1590 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1591 /* VM86 needs a clean new segment descriptor */
1592 set_desc_base(&seg_desc, selector << 4);
1593 set_desc_limit(&seg_desc, 0xffff);
1594 seg_desc.type = 3;
1595 seg_desc.p = 1;
1596 seg_desc.s = 1;
1597 seg_desc.dpl = 3;
1598 goto load;
dde7e6d1
AK		 1599 }
1600
79d5b4c3
AK		 1601 rpl = selector & 3;
1602 cpl = ctxt->ops->cpl(ctxt);
1603
1604 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1605 if ((seg == VCPU_SREG_CS
1606 || (seg == VCPU_SREG_SS
1607 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1608 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1609 && null_selector)
1610 goto exception;
1611
1612 /* TR should be in GDT only */
1613 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1614 goto exception;
1615
1616 if (null_selector) /* for NULL selector skip all following checks */
1617 goto load;
1618
e919464b 1619 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1620 if (ret != X86EMUL_CONTINUE)
1621 return ret;
1622
1623 err_code = selector & 0xfffc;
1624 err_vec = GP_VECTOR;
1625
fc058680 1626 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1627 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1628 goto exception;
1629
1630 if (!seg_desc.p) {
1631 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1632 goto exception;
1633 }
1634
dde7e6d1 1635 dpl = seg_desc.dpl;
dde7e6d1
AK		 1636
1637 switch (seg) {
1638 case VCPU_SREG_SS:
1639 /*
1640 * segment is not a writable data segment or segment
1641 * selector's RPL != CPL or segment selector's RPL != CPL
1642 */
1643 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1644 goto exception;
6aa8b732 1645 break;
dde7e6d1
AK		 1646 case VCPU_SREG_CS:
1647 if (!(seg_desc.type & 8))
1648 goto exception;
1649
1650 if (seg_desc.type & 4) {
1651 /* conforming */
1652 if (dpl > cpl)
1653 goto exception;
1654 } else {
1655 /* nonconforming */
1656 if (rpl > cpl || dpl != cpl)
1657 goto exception;
1658 }
1659 /* CS(RPL) <- CPL */
1660 selector = (selector & 0xfffc) | cpl;
6aa8b732 1661 break;
dde7e6d1
AK		 1662 case VCPU_SREG_TR:
1663 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1664 goto exception;
869be99c
AK		 1665 old_desc = seg_desc;
1666 seg_desc.type |= 2; /* busy */
1667 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1668 sizeof(seg_desc), &ctxt->exception);
1669 if (ret != X86EMUL_CONTINUE)
1670 return ret;
dde7e6d1
AK		 1671 break;
1672 case VCPU_SREG_LDTR:
1673 if (seg_desc.s || seg_desc.type != 2)
1674 goto exception;
1675 break;
1676 default: /* DS, ES, FS, or GS */
4e62417b 1677 /*
dde7e6d1
AK		 1678 * segment is not a data or readable code segment or
1679 * ((segment is a data or nonconforming code segment)
1680 * and (both RPL and CPL > DPL))
4e62417b 1681 */
dde7e6d1
AK		 1682 if ((seg_desc.type & 0xa) == 0x8 ||
1683 (((seg_desc.type & 0xc) != 0xc) &&
1684 (rpl > dpl && cpl > dpl)))
1685 goto exception;
6aa8b732 1686 break;
dde7e6d1
AK		 1687 }
1688
1689 if (seg_desc.s) {
1690 /* mark segment as accessed */
1691 seg_desc.type |= 1;
7b105ca2 1692 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1693 if (ret != X86EMUL_CONTINUE)
1694 return ret;
1695 }
1696load:
7b105ca2 1697 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1698 return X86EMUL_CONTINUE;
1699exception:
1700 emulate_exception(ctxt, err_vec, err_code, true);
1701 return X86EMUL_PROPAGATE_FAULT;
1702}
1703
31be40b3
WY		 1704static void write_register_operand(struct operand *op)
1705{
1706 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1707 switch (op->bytes) {
1708 case 1:
1709 *(u8 *)op->addr.reg = (u8)op->val;
1710 break;
1711 case 2:
1712 *(u16 *)op->addr.reg = (u16)op->val;
1713 break;
1714 case 4:
1715 *op->addr.reg = (u32)op->val;
1716 break; /* 64b: zero-extend */
1717 case 8:
1718 *op->addr.reg = op->val;
1719 break;
1720 }
1721}
1722
adddcecf 1723static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1724{
1725 int rc;
dde7e6d1 1726
b6744dc3
AK		 1727 if (ctxt->d & NoWrite)
1728 return X86EMUL_CONTINUE;
1729
9dac77fa 1730 switch (ctxt->dst.type) {
dde7e6d1 1731 case OP_REG:
9dac77fa 1732 write_register_operand(&ctxt->dst);
6aa8b732 1733 break;
dde7e6d1 1734 case OP_MEM:
9dac77fa 1735 if (ctxt->lock_prefix)
3ca3ac4d 1736 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1737 ctxt->dst.addr.mem,
1738 &ctxt->dst.orig_val,
1739 &ctxt->dst.val,
1740 ctxt->dst.bytes);
341de7e3 1741 else
3ca3ac4d 1742 rc = segmented_write(ctxt,
9dac77fa
AK		 1743 ctxt->dst.addr.mem,
1744 &ctxt->dst.val,
1745 ctxt->dst.bytes);
dde7e6d1
AK		 1746 if (rc != X86EMUL_CONTINUE)
1747 return rc;
a682e354 1748 break;
b3356bf0
GN		 1749 case OP_MEM_STR:
1750 rc = segmented_write(ctxt,
1751 ctxt->dst.addr.mem,
1752 ctxt->dst.data,
1753 ctxt->dst.bytes * ctxt->dst.count);
1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
1756 break;
1253791d 1757 case OP_XMM:
9dac77fa 1758 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1759 break;
cbe2c9d3
AK		 1760 case OP_MM:
1761 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1762 break;
dde7e6d1
AK		 1763 case OP_NONE:
1764 /* no writeback */
414e6277 1765 break;
dde7e6d1 1766 default:
414e6277 1767 break;
6aa8b732 1768 }
dde7e6d1
AK		 1769 return X86EMUL_CONTINUE;
1770}
6aa8b732 1771
51ddff50 1772static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1773{
4179bb02 1774 struct segmented_address addr;
0dc8d10f 1775
5ad105e5 1776 rsp_increment(ctxt, -bytes);
dd856efa 1777 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1778 addr.seg = VCPU_SREG_SS;
1779
51ddff50
AK		 1780 return segmented_write(ctxt, addr, data, bytes);
1781}
1782
1783static int em_push(struct x86_emulate_ctxt *ctxt)
1784{
4179bb02 1785 /* Disable writeback. */
9dac77fa 1786 ctxt->dst.type = OP_NONE;
51ddff50 1787 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1788}
69f55cb1 1789
dde7e6d1 1790static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1791 void *dest, int len)
1792{
dde7e6d1 1793 int rc;
90de84f5 1794 struct segmented_address addr;
8b4caf66 1795
dd856efa 1796 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1797 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1798 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1799 if (rc != X86EMUL_CONTINUE)
1800 return rc;
1801
5ad105e5 1802 rsp_increment(ctxt, len);
dde7e6d1 1803 return rc;
8b4caf66
LV		 1804}
1805
c54fe504
TY		 1806static int em_pop(struct x86_emulate_ctxt *ctxt)
1807{
9dac77fa 1808 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1809}
1810
dde7e6d1 1811static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1812 void *dest, int len)
9de41573
GN		 1813{
1814 int rc;
dde7e6d1
AK		 1815 unsigned long val, change_mask;
1816 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1817 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1818
3b9be3bf 1819 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1820 if (rc != X86EMUL_CONTINUE)
1821 return rc;
9de41573 1822
dde7e6d1
AK		 1823 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1824 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1825
dde7e6d1
AK		 1826 switch(ctxt->mode) {
1827 case X86EMUL_MODE_PROT64:
1828 case X86EMUL_MODE_PROT32:
1829 case X86EMUL_MODE_PROT16:
1830 if (cpl == 0)
1831 change_mask |= EFLG_IOPL;
1832 if (cpl <= iopl)
1833 change_mask |= EFLG_IF;
1834 break;
1835 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1836 if (iopl < 3)
1837 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1838 change_mask |= EFLG_IF;
1839 break;
1840 default: /* real mode */
1841 change_mask |= (EFLG_IOPL | EFLG_IF);
1842 break;
9de41573 1843 }
dde7e6d1
AK		 1844
1845 *(unsigned long *)dest =
1846 (ctxt->eflags & ~change_mask) | (val & change_mask);
1847
1848 return rc;
9de41573
GN		 1849}
1850
62aaa2f0
TY		 1851static int em_popf(struct x86_emulate_ctxt *ctxt)
1852{
9dac77fa
AK		 1853 ctxt->dst.type = OP_REG;
1854 ctxt->dst.addr.reg = &ctxt->eflags;
1855 ctxt->dst.bytes = ctxt->op_bytes;
1856 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1857}
1858
612e89f0
AK		 1859static int em_enter(struct x86_emulate_ctxt *ctxt)
1860{
1861 int rc;
1862 unsigned frame_size = ctxt->src.val;
1863 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1864 ulong rbp;
612e89f0
AK		 1865
1866 if (nesting_level)
1867 return X86EMUL_UNHANDLEABLE;
1868
dd856efa
AK		 1869 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1870 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1871 if (rc != X86EMUL_CONTINUE)
1872 return rc;
dd856efa 1873 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1874 stack_mask(ctxt));
dd856efa
AK		 1875 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1876 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1877 stack_mask(ctxt));
1878 return X86EMUL_CONTINUE;
1879}
1880
f47cfa31
AK		 1881static int em_leave(struct x86_emulate_ctxt *ctxt)
1882{
dd856efa 1883 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1884 stack_mask(ctxt));
dd856efa 1885 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1886}
1887
1cd196ea 1888static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1889{
1cd196ea
AK		 1890 int seg = ctxt->src2.val;
1891
9dac77fa 1892 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1893
4487b3b4 1894 return em_push(ctxt);
7b262e90
GN		 1895}
1896
1cd196ea 1897static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1898{
1cd196ea 1899 int seg = ctxt->src2.val;
dde7e6d1
AK		 1900 unsigned long selector;
1901 int rc;
38ba30ba 1902
9dac77fa 1903 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
1906
7b105ca2 1907 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1908 return rc;
38ba30ba
GN		 1909}
1910
b96a7fad 1911static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1912{
dd856efa 1913 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1914 int rc = X86EMUL_CONTINUE;
1915 int reg = VCPU_REGS_RAX;
38ba30ba 1916
dde7e6d1
AK		 1917 while (reg <= VCPU_REGS_RDI) {
1918 (reg == VCPU_REGS_RSP) ?
dd856efa 1919 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1920
4487b3b4 1921 rc = em_push(ctxt);
dde7e6d1
AK		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
38ba30ba 1924
dde7e6d1 1925 ++reg;
38ba30ba 1926 }
38ba30ba 1927
dde7e6d1 1928 return rc;
38ba30ba
GN		 1929}
1930
62aaa2f0
TY		 1931static int em_pushf(struct x86_emulate_ctxt *ctxt)
1932{
9dac77fa 1933 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1934 return em_push(ctxt);
1935}
1936
b96a7fad 1937static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1938{
dde7e6d1
AK		 1939 int rc = X86EMUL_CONTINUE;
1940 int reg = VCPU_REGS_RDI;
38ba30ba 1941
dde7e6d1
AK		 1942 while (reg >= VCPU_REGS_RAX) {
1943 if (reg == VCPU_REGS_RSP) {
5ad105e5 1944 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1945 --reg;
1946 }
38ba30ba 1947
dd856efa 1948 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1949 if (rc != X86EMUL_CONTINUE)
1950 break;
1951 --reg;
38ba30ba 1952 }
dde7e6d1 1953 return rc;
38ba30ba
GN		 1954}
1955
dd856efa 1956static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1957{
0225fb50 1958 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1959 int rc;
6e154e56
MG		 1960 struct desc_ptr dt;
1961 gva_t cs_addr;
1962 gva_t eip_addr;
1963 u16 cs, eip;
6e154e56
MG		 1964
1965 /* TODO: Add limit checks */
9dac77fa 1966 ctxt->src.val = ctxt->eflags;
4487b3b4 1967 rc = em_push(ctxt);
5c56e1cf
AK		 1968 if (rc != X86EMUL_CONTINUE)
1969 return rc;
6e154e56
MG		 1970
1971 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1972
9dac77fa 1973 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1974 rc = em_push(ctxt);
5c56e1cf
AK		 1975 if (rc != X86EMUL_CONTINUE)
1976 return rc;
6e154e56 1977
9dac77fa 1978 ctxt->src.val = ctxt->_eip;
4487b3b4 1979 rc = em_push(ctxt);
5c56e1cf
AK		 1980 if (rc != X86EMUL_CONTINUE)
1981 return rc;
1982
4bff1e86 1983 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1984
1985 eip_addr = dt.address + (irq << 2);
1986 cs_addr = dt.address + (irq << 2) + 2;
1987
0f65dd70 1988 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1989 if (rc != X86EMUL_CONTINUE)
1990 return rc;
1991
0f65dd70 1992 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1993 if (rc != X86EMUL_CONTINUE)
1994 return rc;
1995
7b105ca2 1996 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1997 if (rc != X86EMUL_CONTINUE)
1998 return rc;
1999
9dac77fa 2000 ctxt->_eip = eip;
6e154e56
MG		 2001
2002 return rc;
2003}
2004
dd856efa
AK		 2005int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2006{
2007 int rc;
2008
2009 invalidate_registers(ctxt);
2010 rc = __emulate_int_real(ctxt, irq);
2011 if (rc == X86EMUL_CONTINUE)
2012 writeback_registers(ctxt);
2013 return rc;
2014}
2015
7b105ca2 2016static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2017{
2018 switch(ctxt->mode) {
2019 case X86EMUL_MODE_REAL:
dd856efa 2020 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2021 case X86EMUL_MODE_VM86:
2022 case X86EMUL_MODE_PROT16:
2023 case X86EMUL_MODE_PROT32:
2024 case X86EMUL_MODE_PROT64:
2025 default:
2026 /* Protected mode interrupts unimplemented yet */
2027 return X86EMUL_UNHANDLEABLE;
2028 }
2029}
2030
7b105ca2 2031static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2032{
dde7e6d1
AK		 2033 int rc = X86EMUL_CONTINUE;
2034 unsigned long temp_eip = 0;
2035 unsigned long temp_eflags = 0;
2036 unsigned long cs = 0;
2037 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2038 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2039 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2040 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2041
dde7e6d1 2042 /* TODO: Add stack limit check */
38ba30ba 2043
9dac77fa 2044 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2045
dde7e6d1
AK		 2046 if (rc != X86EMUL_CONTINUE)
2047 return rc;
38ba30ba 2048
35d3d4a1
AK		 2049 if (temp_eip & ~0xffff)
2050 return emulate_gp(ctxt, 0);
38ba30ba 2051
9dac77fa 2052 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2053
dde7e6d1
AK		 2054 if (rc != X86EMUL_CONTINUE)
2055 return rc;
38ba30ba 2056
9dac77fa 2057 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2058
dde7e6d1
AK		 2059 if (rc != X86EMUL_CONTINUE)
2060 return rc;
38ba30ba 2061
7b105ca2 2062 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2063
dde7e6d1
AK		 2064 if (rc != X86EMUL_CONTINUE)
2065 return rc;
38ba30ba 2066
9dac77fa 2067 ctxt->_eip = temp_eip;
38ba30ba 2068
38ba30ba 2069
9dac77fa 2070 if (ctxt->op_bytes == 4)
dde7e6d1 2071 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2072 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2073 ctxt->eflags &= ~0xffff;
2074 ctxt->eflags |= temp_eflags;
38ba30ba 2075 }
dde7e6d1
AK		 2076
2077 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2078 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2079
2080 return rc;
38ba30ba
GN		 2081}
2082
e01991e7 2083static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2084{
dde7e6d1
AK		 2085 switch(ctxt->mode) {
2086 case X86EMUL_MODE_REAL:
7b105ca2 2087 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2088 case X86EMUL_MODE_VM86:
2089 case X86EMUL_MODE_PROT16:
2090 case X86EMUL_MODE_PROT32:
2091 case X86EMUL_MODE_PROT64:
c37eda13 2092 default:
dde7e6d1
AK		 2093 /* iret from protected mode unimplemented yet */
2094 return X86EMUL_UNHANDLEABLE;
c37eda13 2095 }
c37eda13
WY		 2096}
2097
d2f62766
TY		 2098static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2099{
d2f62766
TY		 2100 int rc;
2101 unsigned short sel;
2102
9dac77fa 2103 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2104
7b105ca2 2105 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2106 if (rc != X86EMUL_CONTINUE)
2107 return rc;
2108
9dac77fa
AK		 2109 ctxt->_eip = 0;
2110 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2111 return X86EMUL_CONTINUE;
2112}
2113
3329ece1
AK		 2114static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2115{
2116 u8 ex = 0;
2117
2118 emulate_1op_rax_rdx(ctxt, "mul", ex);
2119 return X86EMUL_CONTINUE;
2120}
2121
2122static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2123{
2124 u8 ex = 0;
2125
2126 emulate_1op_rax_rdx(ctxt, "imul", ex);
2127 return X86EMUL_CONTINUE;
2128}
2129
2130static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2131{
34d1f490 2132 u8 de = 0;
8cdbd2c9 2133
3329ece1
AK		 2134 emulate_1op_rax_rdx(ctxt, "div", de);
2135 if (de)
2136 return emulate_de(ctxt);
2137 return X86EMUL_CONTINUE;
2138}
2139
2140static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2141{
2142 u8 de = 0;
2143
2144 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2145 if (de)
2146 return emulate_de(ctxt);
8c5eee30 2147 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2148}
2149
51187683 2150static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2151{
4179bb02 2152 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2153
9dac77fa 2154 switch (ctxt->modrm_reg) {
d19292e4
MG		 2155 case 2: /* call near abs */ {
2156 long int old_eip;
9dac77fa
AK		 2157 old_eip = ctxt->_eip;
2158 ctxt->_eip = ctxt->src.val;
2159 ctxt->src.val = old_eip;
4487b3b4 2160 rc = em_push(ctxt);
d19292e4
MG		 2161 break;
2162 }
8cdbd2c9 2163 case 4: /* jmp abs */
9dac77fa 2164 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2165 break;
d2f62766
TY		 2166 case 5: /* jmp far */
2167 rc = em_jmp_far(ctxt);
2168 break;
8cdbd2c9 2169 case 6: /* push */
4487b3b4 2170 rc = em_push(ctxt);
8cdbd2c9 2171 break;
8cdbd2c9 2172 }
4179bb02 2173 return rc;
8cdbd2c9
LV		 2174}
2175
e0dac408 2176static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2177{
9dac77fa 2178 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2179
dd856efa
AK		 2180 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2181 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2182 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2183 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2184 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2185 } else {
dd856efa
AK		 2186 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2187 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2188
05f086f8 2189 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2190 }
1b30eaa8 2191 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2192}
2193
ebda02c2
TY		 2194static int em_ret(struct x86_emulate_ctxt *ctxt)
2195{
9dac77fa
AK		 2196 ctxt->dst.type = OP_REG;
2197 ctxt->dst.addr.reg = &ctxt->_eip;
2198 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2199 return em_pop(ctxt);
2200}
2201
e01991e7 2202static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2203{
a77ab5ea
AK		 2204 int rc;
2205 unsigned long cs;
2206
9dac77fa 2207 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2208 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2209 return rc;
9dac77fa
AK		 2210 if (ctxt->op_bytes == 4)
2211 ctxt->_eip = (u32)ctxt->_eip;
2212 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2213 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2214 return rc;
7b105ca2 2215 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2216 return rc;
2217}
2218
e940b5c2
TY		 2219static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2220{
2221 /* Save real source value, then compare EAX against destination. */
2222 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2223 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2224 fastop(ctxt, em_cmp);
e940b5c2
TY		 2225
2226 if (ctxt->eflags & EFLG_ZF) {
2227 /* Success: write back to memory. */
2228 ctxt->dst.val = ctxt->src.orig_val;
2229 } else {
2230 /* Failure: write the value we saw to EAX. */
2231 ctxt->dst.type = OP_REG;
dd856efa 2232 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2233 }
2234 return X86EMUL_CONTINUE;
2235}
2236
d4b4325f 2237static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2238{
d4b4325f 2239 int seg = ctxt->src2.val;
09b5f4d3
WY		 2240 unsigned short sel;
2241 int rc;
2242
9dac77fa 2243 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2244
7b105ca2 2245 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2246 if (rc != X86EMUL_CONTINUE)
2247 return rc;
2248
9dac77fa 2249 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2250 return rc;
2251}
2252
7b105ca2 2253static void
e66bb2cc 2254setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2255 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2256{
e66bb2cc 2257 cs->l = 0; /* will be adjusted later */
79168fd1 2258 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2259 cs->g = 1; /* 4kb granularity */
79168fd1 2260 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2261 cs->type = 0x0b; /* Read, Execute, Accessed */
2262 cs->s = 1;
2263 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2264 cs->p = 1;
2265 cs->d = 1;
99245b50 2266 cs->avl = 0;
e66bb2cc 2267
79168fd1
GN		 2268 set_desc_base(ss, 0); /* flat segment */
2269 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2270 ss->g = 1; /* 4kb granularity */
2271 ss->s = 1;
2272 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2273 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2274 ss->dpl = 0;
79168fd1 2275 ss->p = 1;
99245b50
GN		 2276 ss->l = 0;
2277 ss->avl = 0;
e66bb2cc
AP		 2278}
2279
1a18a69b
AK		 2280static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2281{
2282 u32 eax, ebx, ecx, edx;
2283
2284 eax = ecx = 0;
0017f93a
AK		 2285 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2286 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2287 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2288 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2289}
2290
c2226fc9
SB		 2291static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2292{
0225fb50 2293 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2294 u32 eax, ebx, ecx, edx;
2295
2296 /*
2297 * syscall should always be enabled in longmode - so only become
2298 * vendor specific (cpuid) if other modes are active...
2299 */
2300 if (ctxt->mode == X86EMUL_MODE_PROT64)
2301 return true;
2302
2303 eax = 0x00000000;
2304 ecx = 0x00000000;
0017f93a
AK		 2305 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2306 /*
2307 * Intel ("GenuineIntel")
2308 * remark: Intel CPUs only support "syscall" in 64bit
2309 * longmode. Also an 64bit guest with a
2310 * 32bit compat-app running will #UD !! While this
2311 * behaviour can be fixed (by emulating) into AMD
2312 * response - CPUs of AMD can't behave like Intel.
2313 */
2314 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2315 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2316 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2317 return false;
2318
2319 /* AMD ("AuthenticAMD") */
2320 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2321 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2322 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2323 return true;
2324
2325 /* AMD ("AMDisbetter!") */
2326 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2327 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2328 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2329 return true;
c2226fc9
SB		 2330
2331 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2332 return false;
2333}
2334
e01991e7 2335static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2336{
0225fb50 2337 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2338 struct desc_struct cs, ss;
e66bb2cc 2339 u64 msr_data;
79168fd1 2340 u16 cs_sel, ss_sel;
c2ad2bb3 2341 u64 efer = 0;
e66bb2cc
AP		 2342
2343 /* syscall is not available in real mode */
2e901c4c 2344 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2345 ctxt->mode == X86EMUL_MODE_VM86)
2346 return emulate_ud(ctxt);
e66bb2cc 2347
c2226fc9
SB		 2348 if (!(em_syscall_is_enabled(ctxt)))
2349 return emulate_ud(ctxt);
2350
c2ad2bb3 2351 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2352 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2353
c2226fc9
SB		 2354 if (!(efer & EFER_SCE))
2355 return emulate_ud(ctxt);
2356
717746e3 2357 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2358 msr_data >>= 32;
79168fd1
GN		 2359 cs_sel = (u16)(msr_data & 0xfffc);
2360 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2361
c2ad2bb3 2362 if (efer & EFER_LMA) {
79168fd1 2363 cs.d = 0;
e66bb2cc
AP		 2364 cs.l = 1;
2365 }
1aa36616
AK		 2366 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2367 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2368
dd856efa 2369 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2370 if (efer & EFER_LMA) {
e66bb2cc 2371#ifdef CONFIG_X86_64
dd856efa 2372 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2373
717746e3 2374 ops->get_msr(ctxt,
3fb1b5db
GN		 2375 ctxt->mode == X86EMUL_MODE_PROT64 ?
2376 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2377 ctxt->_eip = msr_data;
e66bb2cc 2378
717746e3 2379 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2380 ctxt->eflags &= ~(msr_data | EFLG_RF);
2381#endif
2382 } else {
2383 /* legacy mode */
717746e3 2384 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2385 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2386
2387 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2388 }
2389
e54cfa97 2390 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2391}
2392
e01991e7 2393static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2394{
0225fb50 2395 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2396 struct desc_struct cs, ss;
8c604352 2397 u64 msr_data;
79168fd1 2398 u16 cs_sel, ss_sel;
c2ad2bb3 2399 u64 efer = 0;
8c604352 2400
7b105ca2 2401 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2402 /* inject #GP if in real mode */
35d3d4a1
AK		 2403 if (ctxt->mode == X86EMUL_MODE_REAL)
2404 return emulate_gp(ctxt, 0);
8c604352 2405
1a18a69b
AK		 2406 /*
2407 * Not recognized on AMD in compat mode (but is recognized in legacy
2408 * mode).
2409 */
2410 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2411 && !vendor_intel(ctxt))
2412 return emulate_ud(ctxt);
2413
8c604352
AP		 2414 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2415 * Therefore, we inject an #UD.
2416 */
35d3d4a1
AK		 2417 if (ctxt->mode == X86EMUL_MODE_PROT64)
2418 return emulate_ud(ctxt);
8c604352 2419
7b105ca2 2420 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2421
717746e3 2422 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2423 switch (ctxt->mode) {
2424 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2425 if ((msr_data & 0xfffc) == 0x0)
2426 return emulate_gp(ctxt, 0);
8c604352
AP		 2427 break;
2428 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2429 if (msr_data == 0x0)
2430 return emulate_gp(ctxt, 0);
8c604352 2431 break;
9d1b39a9
GN		 2432 default:
2433 break;
8c604352
AP		 2434 }
2435
2436 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2437 cs_sel = (u16)msr_data;
2438 cs_sel &= ~SELECTOR_RPL_MASK;
2439 ss_sel = cs_sel + 8;
2440 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2441 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2442 cs.d = 0;
8c604352
AP		 2443 cs.l = 1;
2444 }
2445
1aa36616
AK		 2446 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2447 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2448
717746e3 2449 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2450 ctxt->_eip = msr_data;
8c604352 2451
717746e3 2452 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2453 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2454
e54cfa97 2455 return X86EMUL_CONTINUE;
8c604352
AP		 2456}
2457
e01991e7 2458static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2459{
0225fb50 2460 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2461 struct desc_struct cs, ss;
4668f050
AP		 2462 u64 msr_data;
2463 int usermode;
1249b96e 2464 u16 cs_sel = 0, ss_sel = 0;
4668f050 2465
a0044755
GN		 2466 /* inject #GP if in real mode or Virtual 8086 mode */
2467 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2468 ctxt->mode == X86EMUL_MODE_VM86)
2469 return emulate_gp(ctxt, 0);
4668f050 2470
7b105ca2 2471 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2472
9dac77fa 2473 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2474 usermode = X86EMUL_MODE_PROT64;
2475 else
2476 usermode = X86EMUL_MODE_PROT32;
2477
2478 cs.dpl = 3;
2479 ss.dpl = 3;
717746e3 2480 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2481 switch (usermode) {
2482 case X86EMUL_MODE_PROT32:
79168fd1 2483 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2484 if ((msr_data & 0xfffc) == 0x0)
2485 return emulate_gp(ctxt, 0);
79168fd1 2486 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2487 break;
2488 case X86EMUL_MODE_PROT64:
79168fd1 2489 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2490 if (msr_data == 0x0)
2491 return emulate_gp(ctxt, 0);
79168fd1
GN		 2492 ss_sel = cs_sel + 8;
2493 cs.d = 0;
4668f050
AP		 2494 cs.l = 1;
2495 break;
2496 }
79168fd1
GN		 2497 cs_sel |= SELECTOR_RPL_MASK;
2498 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2499
1aa36616
AK		 2500 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2501 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2502
dd856efa
AK		 2503 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2504 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2505
e54cfa97 2506 return X86EMUL_CONTINUE;
4668f050
AP		 2507}
2508
7b105ca2 2509static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2510{
2511 int iopl;
2512 if (ctxt->mode == X86EMUL_MODE_REAL)
2513 return false;
2514 if (ctxt->mode == X86EMUL_MODE_VM86)
2515 return true;
2516 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2517 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2518}
2519
2520static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2521 u16 port, u16 len)
2522{
0225fb50 2523 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2524 struct desc_struct tr_seg;
5601d05b 2525 u32 base3;
f850e2e6 2526 int r;
1aa36616 2527 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2528 unsigned mask = (1 << len) - 1;
5601d05b 2529 unsigned long base;
f850e2e6 2530
1aa36616 2531 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2532 if (!tr_seg.p)
f850e2e6 2533 return false;
79168fd1 2534 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2535 return false;
5601d05b
GN		 2536 base = get_desc_base(&tr_seg);
2537#ifdef CONFIG_X86_64
2538 base |= ((u64)base3) << 32;
2539#endif
0f65dd70 2540 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2541 if (r != X86EMUL_CONTINUE)
2542 return false;
79168fd1 2543 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2544 return false;
0f65dd70 2545 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2546 if (r != X86EMUL_CONTINUE)
2547 return false;
2548 if ((perm >> bit_idx) & mask)
2549 return false;
2550 return true;
2551}
2552
2553static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2554 u16 port, u16 len)
2555{
4fc40f07
GN		 2556 if (ctxt->perm_ok)
2557 return true;
2558
7b105ca2
TY		 2559 if (emulator_bad_iopl(ctxt))
2560 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2561 return false;
4fc40f07
GN		 2562
2563 ctxt->perm_ok = true;
2564
f850e2e6
GN		 2565 return true;
2566}
2567
38ba30ba 2568static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2569 struct tss_segment_16 *tss)
2570{
9dac77fa 2571 tss->ip = ctxt->_eip;
38ba30ba 2572 tss->flag = ctxt->eflags;
dd856efa
AK		 2573 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2574 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2575 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2576 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2577 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2578 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2579 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2580 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2581
1aa36616
AK		 2582 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2583 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2584 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2585 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2586 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2587}
2588
2589static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2590 struct tss_segment_16 *tss)
2591{
38ba30ba
GN		 2592 int ret;
2593
9dac77fa 2594 ctxt->_eip = tss->ip;
38ba30ba 2595 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2596 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2597 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2598 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2599 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2600 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2601 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2602 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2603 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2604
2605 /*
2606 * SDM says that segment selectors are loaded before segment
2607 * descriptors
2608 */
1aa36616
AK		 2609 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2610 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2611 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2612 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2613 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2614
2615 /*
fc058680 2616 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2617 * it is handled in a context of new task
2618 */
7b105ca2 2619 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2620 if (ret != X86EMUL_CONTINUE)
2621 return ret;
7b105ca2 2622 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2623 if (ret != X86EMUL_CONTINUE)
2624 return ret;
7b105ca2 2625 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2626 if (ret != X86EMUL_CONTINUE)
2627 return ret;
7b105ca2 2628 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2629 if (ret != X86EMUL_CONTINUE)
2630 return ret;
7b105ca2 2631 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2632 if (ret != X86EMUL_CONTINUE)
2633 return ret;
2634
2635 return X86EMUL_CONTINUE;
2636}
2637
2638static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2639 u16 tss_selector, u16 old_tss_sel,
2640 ulong old_tss_base, struct desc_struct *new_desc)
2641{
0225fb50 2642 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2643 struct tss_segment_16 tss_seg;
2644 int ret;
bcc55cba 2645 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2646
0f65dd70 2647 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2648 &ctxt->exception);
db297e3d 2649 if (ret != X86EMUL_CONTINUE)
38ba30ba 2650 /* FIXME: need to provide precise fault address */
38ba30ba 2651 return ret;
38ba30ba 2652
7b105ca2 2653 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2654
0f65dd70 2655 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2656 &ctxt->exception);
db297e3d 2657 if (ret != X86EMUL_CONTINUE)
38ba30ba 2658 /* FIXME: need to provide precise fault address */
38ba30ba 2659 return ret;
38ba30ba 2660
0f65dd70 2661 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2662 &ctxt->exception);
db297e3d 2663 if (ret != X86EMUL_CONTINUE)
38ba30ba 2664 /* FIXME: need to provide precise fault address */
38ba30ba 2665 return ret;
38ba30ba
GN		 2666
2667 if (old_tss_sel != 0xffff) {
2668 tss_seg.prev_task_link = old_tss_sel;
2669
0f65dd70 2670 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2671 &tss_seg.prev_task_link,
2672 sizeof tss_seg.prev_task_link,
0f65dd70 2673 &ctxt->exception);
db297e3d 2674 if (ret != X86EMUL_CONTINUE)
38ba30ba 2675 /* FIXME: need to provide precise fault address */
38ba30ba 2676 return ret;
38ba30ba
GN		 2677 }
2678
7b105ca2 2679 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2680}
2681
2682static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2683 struct tss_segment_32 *tss)
2684{
7b105ca2 2685 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2686 tss->eip = ctxt->_eip;
38ba30ba 2687 tss->eflags = ctxt->eflags;
dd856efa
AK		 2688 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2689 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2690 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2691 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2692 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2693 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2694 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2695 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2696
1aa36616
AK		 2697 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2698 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2699 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2700 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2701 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2702 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2703 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2704}
2705
2706static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2707 struct tss_segment_32 *tss)
2708{
38ba30ba
GN		 2709 int ret;
2710
7b105ca2 2711 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2712 return emulate_gp(ctxt, 0);
9dac77fa 2713 ctxt->_eip = tss->eip;
38ba30ba 2714 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2715
2716 /* General purpose registers */
dd856efa
AK		 2717 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2718 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2719 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2720 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2721 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2722 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2723 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2724 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2725
2726 /*
2727 * SDM says that segment selectors are loaded before segment
2728 * descriptors
2729 */
1aa36616
AK		 2730 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2731 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2732 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2733 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2734 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2735 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2736 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2737
4cee4798
KW		 2738 /*
2739 * If we're switching between Protected Mode and VM86, we need to make
2740 * sure to update the mode before loading the segment descriptors so
2741 * that the selectors are interpreted correctly.
2742 *
2743 * Need to get rflags to the vcpu struct immediately because it
2744 * influences the CPL which is checked at least when loading the segment
2745 * descriptors and when pushing an error code to the new kernel stack.
2746 *
2747 * TODO Introduce a separate ctxt->ops->set_cpl callback
2748 */
2749 if (ctxt->eflags & X86_EFLAGS_VM)
2750 ctxt->mode = X86EMUL_MODE_VM86;
2751 else
2752 ctxt->mode = X86EMUL_MODE_PROT32;
2753
2754 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2755
38ba30ba
GN		 2756 /*
2757 * Now load segment descriptors. If fault happenes at this stage
2758 * it is handled in a context of new task
2759 */
7b105ca2 2760 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2761 if (ret != X86EMUL_CONTINUE)
2762 return ret;
7b105ca2 2763 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2764 if (ret != X86EMUL_CONTINUE)
2765 return ret;
7b105ca2 2766 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2767 if (ret != X86EMUL_CONTINUE)
2768 return ret;
7b105ca2 2769 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2770 if (ret != X86EMUL_CONTINUE)
2771 return ret;
7b105ca2 2772 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2773 if (ret != X86EMUL_CONTINUE)
2774 return ret;
7b105ca2 2775 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2776 if (ret != X86EMUL_CONTINUE)
2777 return ret;
7b105ca2 2778 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2779 if (ret != X86EMUL_CONTINUE)
2780 return ret;
2781
2782 return X86EMUL_CONTINUE;
2783}
2784
2785static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2786 u16 tss_selector, u16 old_tss_sel,
2787 ulong old_tss_base, struct desc_struct *new_desc)
2788{
0225fb50 2789 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2790 struct tss_segment_32 tss_seg;
2791 int ret;
bcc55cba 2792 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2793
0f65dd70 2794 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2795 &ctxt->exception);
db297e3d 2796 if (ret != X86EMUL_CONTINUE)
38ba30ba 2797 /* FIXME: need to provide precise fault address */
38ba30ba 2798 return ret;
38ba30ba 2799
7b105ca2 2800 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2801
0f65dd70 2802 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2803 &ctxt->exception);
db297e3d 2804 if (ret != X86EMUL_CONTINUE)
38ba30ba 2805 /* FIXME: need to provide precise fault address */
38ba30ba 2806 return ret;
38ba30ba 2807
0f65dd70 2808 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2809 &ctxt->exception);
db297e3d 2810 if (ret != X86EMUL_CONTINUE)
38ba30ba 2811 /* FIXME: need to provide precise fault address */
38ba30ba 2812 return ret;
38ba30ba
GN		 2813
2814 if (old_tss_sel != 0xffff) {
2815 tss_seg.prev_task_link = old_tss_sel;
2816
0f65dd70 2817 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2818 &tss_seg.prev_task_link,
2819 sizeof tss_seg.prev_task_link,
0f65dd70 2820 &ctxt->exception);
db297e3d 2821 if (ret != X86EMUL_CONTINUE)
38ba30ba 2822 /* FIXME: need to provide precise fault address */
38ba30ba 2823 return ret;
38ba30ba
GN		 2824 }
2825
7b105ca2 2826 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2827}
2828
2829static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2830 u16 tss_selector, int idt_index, int reason,
e269fb21 2831 bool has_error_code, u32 error_code)
38ba30ba 2832{
0225fb50 2833 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2834 struct desc_struct curr_tss_desc, next_tss_desc;
2835 int ret;
1aa36616 2836 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2837 ulong old_tss_base =
4bff1e86 2838 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2839 u32 desc_limit;
e919464b 2840 ulong desc_addr;
38ba30ba
GN		 2841
2842 /* FIXME: old_tss_base == ~0 ? */
2843
e919464b 2844 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2845 if (ret != X86EMUL_CONTINUE)
2846 return ret;
e919464b 2847 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2848 if (ret != X86EMUL_CONTINUE)
2849 return ret;
2850
2851 /* FIXME: check that next_tss_desc is tss */
2852
7f3d35fd
KW		 2853 /*
2854 * Check privileges. The three cases are task switch caused by...
2855 *
2856 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2857 * 2. Exception/IRQ/iret: No check is performed
fc058680 2858 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2859 */
2860 if (reason == TASK_SWITCH_GATE) {
2861 if (idt_index != -1) {
2862 /* Software interrupts */
2863 struct desc_struct task_gate_desc;
2864 int dpl;
2865
2866 ret = read_interrupt_descriptor(ctxt, idt_index,
2867 &task_gate_desc);
2868 if (ret != X86EMUL_CONTINUE)
2869 return ret;
2870
2871 dpl = task_gate_desc.dpl;
2872 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2873 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2874 }
2875 } else if (reason != TASK_SWITCH_IRET) {
2876 int dpl = next_tss_desc.dpl;
2877 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2878 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2879 }
2880
7f3d35fd 2881
ceffb459
GN		 2882 desc_limit = desc_limit_scaled(&next_tss_desc);
2883 if (!next_tss_desc.p ||
2884 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2885 desc_limit < 0x2b)) {
54b8486f 2886 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2887 return X86EMUL_PROPAGATE_FAULT;
2888 }
2889
2890 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2891 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2892 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2893 }
2894
2895 if (reason == TASK_SWITCH_IRET)
2896 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2897
2898 /* set back link to prev task only if NT bit is set in eflags
fc058680 2899 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2900 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2901 old_tss_sel = 0xffff;
2902
2903 if (next_tss_desc.type & 8)
7b105ca2 2904 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2905 old_tss_base, &next_tss_desc);
2906 else
7b105ca2 2907 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2908 old_tss_base, &next_tss_desc);
0760d448
JK		 2909 if (ret != X86EMUL_CONTINUE)
2910 return ret;
38ba30ba
GN		 2911
2912 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2913 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2914
2915 if (reason != TASK_SWITCH_IRET) {
2916 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2917 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2918 }
2919
717746e3 2920 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2921 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2922
e269fb21 2923 if (has_error_code) {
9dac77fa
AK		 2924 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2925 ctxt->lock_prefix = 0;
2926 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2927 ret = em_push(ctxt);
e269fb21
JK		 2928 }
2929
38ba30ba
GN		 2930 return ret;
2931}
2932
2933int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2934 u16 tss_selector, int idt_index, int reason,
e269fb21 2935 bool has_error_code, u32 error_code)
38ba30ba 2936{
38ba30ba
GN		 2937 int rc;
2938
dd856efa 2939 invalidate_registers(ctxt);
9dac77fa
AK		 2940 ctxt->_eip = ctxt->eip;
2941 ctxt->dst.type = OP_NONE;
38ba30ba 2942
7f3d35fd 2943 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2944 has_error_code, error_code);
38ba30ba 2945
dd856efa 2946 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2947 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2948 writeback_registers(ctxt);
2949 }
38ba30ba 2950
a0c0ab2f 2951 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2952}
2953
f3bd64c6
GN		 2954static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2955 struct operand *op)
a682e354 2956{
b3356bf0 2957 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2958
dd856efa
AK		 2959 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2960 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2961}
2962
7af04fc0
AK		 2963static int em_das(struct x86_emulate_ctxt *ctxt)
2964{
7af04fc0
AK		 2965 u8 al, old_al;
2966 bool af, cf, old_cf;
2967
2968 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2969 al = ctxt->dst.val;
7af04fc0
AK		 2970
2971 old_al = al;
2972 old_cf = cf;
2973 cf = false;
2974 af = ctxt->eflags & X86_EFLAGS_AF;
2975 if ((al & 0x0f) > 9 || af) {
2976 al -= 6;
2977 cf = old_cf | (al >= 250);
2978 af = true;
2979 } else {
2980 af = false;
2981 }
2982 if (old_al > 0x99 || old_cf) {
2983 al -= 0x60;
2984 cf = true;
2985 }
2986
9dac77fa 2987 ctxt->dst.val = al;
7af04fc0 2988 /* Set PF, ZF, SF */
9dac77fa
AK		 2989 ctxt->src.type = OP_IMM;
2990 ctxt->src.val = 0;
2991 ctxt->src.bytes = 1;
158de57f 2992 fastop(ctxt, em_or);
7af04fc0
AK		 2993 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2994 if (cf)
2995 ctxt->eflags |= X86_EFLAGS_CF;
2996 if (af)
2997 ctxt->eflags |= X86_EFLAGS_AF;
2998 return X86EMUL_CONTINUE;
2999}
3000
a035d5c6
PB		 3001static int em_aam(struct x86_emulate_ctxt *ctxt)
3002{
3003 u8 al, ah;
3004
3005 if (ctxt->src.val == 0)
3006 return emulate_de(ctxt);
3007
3008 al = ctxt->dst.val & 0xff;
3009 ah = al / ctxt->src.val;
3010 al %= ctxt->src.val;
3011
3012 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3013
3014 /* Set PF, ZF, SF */
3015 ctxt->src.type = OP_IMM;
3016 ctxt->src.val = 0;
3017 ctxt->src.bytes = 1;
3018 fastop(ctxt, em_or);
3019
3020 return X86EMUL_CONTINUE;
3021}
3022
7f662273
GN		 3023static int em_aad(struct x86_emulate_ctxt *ctxt)
3024{
3025 u8 al = ctxt->dst.val & 0xff;
3026 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3027
3028 al = (al + (ah * ctxt->src.val)) & 0xff;
3029
3030 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3031
f583c29b
GN		 3032 /* Set PF, ZF, SF */
3033 ctxt->src.type = OP_IMM;
3034 ctxt->src.val = 0;
3035 ctxt->src.bytes = 1;
3036 fastop(ctxt, em_or);
7f662273
GN		 3037
3038 return X86EMUL_CONTINUE;
3039}
3040
d4ddafcd
TY		 3041static int em_call(struct x86_emulate_ctxt *ctxt)
3042{
3043 long rel = ctxt->src.val;
3044
3045 ctxt->src.val = (unsigned long)ctxt->_eip;
3046 jmp_rel(ctxt, rel);
3047 return em_push(ctxt);
3048}
3049
0ef753b8
AK		 3050static int em_call_far(struct x86_emulate_ctxt *ctxt)
3051{
0ef753b8
AK		 3052 u16 sel, old_cs;
3053 ulong old_eip;
3054 int rc;
3055
1aa36616 3056 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3057 old_eip = ctxt->_eip;
0ef753b8 3058
9dac77fa 3059 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3060 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3061 return X86EMUL_CONTINUE;
3062
9dac77fa
AK		 3063 ctxt->_eip = 0;
3064 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3065
9dac77fa 3066 ctxt->src.val = old_cs;
4487b3b4 3067 rc = em_push(ctxt);
0ef753b8
AK		 3068 if (rc != X86EMUL_CONTINUE)
3069 return rc;
3070
9dac77fa 3071 ctxt->src.val = old_eip;
4487b3b4 3072 return em_push(ctxt);
0ef753b8
AK		 3073}
3074
40ece7c7
AK		 3075static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3076{
40ece7c7
AK		 3077 int rc;
3078
9dac77fa
AK		 3079 ctxt->dst.type = OP_REG;
3080 ctxt->dst.addr.reg = &ctxt->_eip;
3081 ctxt->dst.bytes = ctxt->op_bytes;
3082 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3083 if (rc != X86EMUL_CONTINUE)
3084 return rc;
5ad105e5 3085 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3086 return X86EMUL_CONTINUE;
3087}
3088
e4f973ae
TY		 3089static int em_xchg(struct x86_emulate_ctxt *ctxt)
3090{
e4f973ae 3091 /* Write back the register source. */
9dac77fa
AK		 3092 ctxt->src.val = ctxt->dst.val;
3093 write_register_operand(&ctxt->src);
e4f973ae
TY		 3094
3095 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3096 ctxt->dst.val = ctxt->src.orig_val;
3097 ctxt->lock_prefix = 1;
e4f973ae
TY		 3098 return X86EMUL_CONTINUE;
3099}
3100
5c82aa29
AK		 3101static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3102{
9dac77fa 3103 ctxt->dst.val = ctxt->src2.val;
4d758349 3104 return fastop(ctxt, em_imul);
5c82aa29
AK		 3105}
3106
61429142
AK		 3107static int em_cwd(struct x86_emulate_ctxt *ctxt)
3108{
9dac77fa
AK		 3109 ctxt->dst.type = OP_REG;
3110 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3111 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3112 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3113
3114 return X86EMUL_CONTINUE;
3115}
3116
48bb5d3c
AK		 3117static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3118{
48bb5d3c
AK		 3119 u64 tsc = 0;
3120
717746e3 3121 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3122 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3123 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3124 return X86EMUL_CONTINUE;
3125}
3126
222d21aa
AK		 3127static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3128{
3129 u64 pmc;
3130
dd856efa 3131 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3132 return emulate_gp(ctxt, 0);
dd856efa
AK		 3133 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3134 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3135 return X86EMUL_CONTINUE;
3136}
3137
b9eac5f4
AK		 3138static int em_mov(struct x86_emulate_ctxt *ctxt)
3139{
49597d81 3140 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3141 return X86EMUL_CONTINUE;
3142}
3143
bc00f8d2
TY		 3144static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3145{
3146 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3147 return emulate_gp(ctxt, 0);
3148
3149 /* Disable writeback. */
3150 ctxt->dst.type = OP_NONE;
3151 return X86EMUL_CONTINUE;
3152}
3153
3154static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3155{
3156 unsigned long val;
3157
3158 if (ctxt->mode == X86EMUL_MODE_PROT64)
3159 val = ctxt->src.val & ~0ULL;
3160 else
3161 val = ctxt->src.val & ~0U;
3162
3163 /* #UD condition is already handled. */
3164 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3165 return emulate_gp(ctxt, 0);
3166
3167 /* Disable writeback. */
3168 ctxt->dst.type = OP_NONE;
3169 return X86EMUL_CONTINUE;
3170}
3171
e1e210b0
TY		 3172static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3173{
3174 u64 msr_data;
3175
dd856efa
AK		 3176 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3177 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3178 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3179 return emulate_gp(ctxt, 0);
3180
3181 return X86EMUL_CONTINUE;
3182}
3183
3184static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3185{
3186 u64 msr_data;
3187
dd856efa 3188 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3189 return emulate_gp(ctxt, 0);
3190
dd856efa
AK		 3191 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3192 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3193 return X86EMUL_CONTINUE;
3194}
3195
1bd5f469
TY		 3196static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3197{
9dac77fa 3198 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3199 return emulate_ud(ctxt);
3200
9dac77fa 3201 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3202 return X86EMUL_CONTINUE;
3203}
3204
3205static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3206{
9dac77fa 3207 u16 sel = ctxt->src.val;
1bd5f469 3208
9dac77fa 3209 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3210 return emulate_ud(ctxt);
3211
9dac77fa 3212 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3213 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3214
3215 /* Disable writeback. */
9dac77fa
AK		 3216 ctxt->dst.type = OP_NONE;
3217 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3218}
3219
a14e579f
AK		 3220static int em_lldt(struct x86_emulate_ctxt *ctxt)
3221{
3222 u16 sel = ctxt->src.val;
3223
3224 /* Disable writeback. */
3225 ctxt->dst.type = OP_NONE;
3226 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3227}
3228
80890006
AK		 3229static int em_ltr(struct x86_emulate_ctxt *ctxt)
3230{
3231 u16 sel = ctxt->src.val;
3232
3233 /* Disable writeback. */
3234 ctxt->dst.type = OP_NONE;
3235 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3236}
3237
38503911
AK		 3238static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3239{
9fa088f4
AK		 3240 int rc;
3241 ulong linear;
3242
9dac77fa 3243 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3244 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3245 ctxt->ops->invlpg(ctxt, linear);
38503911 3246 /* Disable writeback. */
9dac77fa 3247 ctxt->dst.type = OP_NONE;
38503911
AK		 3248 return X86EMUL_CONTINUE;
3249}
3250
2d04a05b
AK		 3251static int em_clts(struct x86_emulate_ctxt *ctxt)
3252{
3253 ulong cr0;
3254
3255 cr0 = ctxt->ops->get_cr(ctxt, 0);
3256 cr0 &= ~X86_CR0_TS;
3257 ctxt->ops->set_cr(ctxt, 0, cr0);
3258 return X86EMUL_CONTINUE;
3259}
3260
26d05cc7
AK		 3261static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3262{
26d05cc7
AK		 3263 int rc;
3264
9dac77fa 3265 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3266 return X86EMUL_UNHANDLEABLE;
3267
3268 rc = ctxt->ops->fix_hypercall(ctxt);
3269 if (rc != X86EMUL_CONTINUE)
3270 return rc;
3271
3272 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3273 ctxt->_eip = ctxt->eip;
26d05cc7 3274 /* Disable writeback. */
9dac77fa 3275 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3276 return X86EMUL_CONTINUE;
3277}
3278
96051572
AK		 3279static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3280 void (*get)(struct x86_emulate_ctxt *ctxt,
3281 struct desc_ptr *ptr))
3282{
3283 struct desc_ptr desc_ptr;
3284
3285 if (ctxt->mode == X86EMUL_MODE_PROT64)
3286 ctxt->op_bytes = 8;
3287 get(ctxt, &desc_ptr);
3288 if (ctxt->op_bytes == 2) {
3289 ctxt->op_bytes = 4;
3290 desc_ptr.address &= 0x00ffffff;
3291 }
3292 /* Disable writeback. */
3293 ctxt->dst.type = OP_NONE;
3294 return segmented_write(ctxt, ctxt->dst.addr.mem,
3295 &desc_ptr, 2 + ctxt->op_bytes);
3296}
3297
3298static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3299{
3300 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3301}
3302
3303static int em_sidt(struct x86_emulate_ctxt *ctxt)
3304{
3305 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3306}
3307
26d05cc7
AK		 3308static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3309{
26d05cc7
AK		 3310 struct desc_ptr desc_ptr;
3311 int rc;
3312
510425ff
AK		 3313 if (ctxt->mode == X86EMUL_MODE_PROT64)
3314 ctxt->op_bytes = 8;
9dac77fa 3315 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3316 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3317 ctxt->op_bytes);
26d05cc7
AK		 3318 if (rc != X86EMUL_CONTINUE)
3319 return rc;
3320 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3321 /* Disable writeback. */
9dac77fa 3322 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3323 return X86EMUL_CONTINUE;
3324}
3325
5ef39c71 3326static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3327{
26d05cc7
AK		 3328 int rc;
3329
5ef39c71
AK		 3330 rc = ctxt->ops->fix_hypercall(ctxt);
3331
26d05cc7 3332 /* Disable writeback. */
9dac77fa 3333 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3334 return rc;
3335}
3336
3337static int em_lidt(struct x86_emulate_ctxt *ctxt)
3338{
26d05cc7
AK		 3339 struct desc_ptr desc_ptr;
3340 int rc;
3341
510425ff
AK		 3342 if (ctxt->mode == X86EMUL_MODE_PROT64)
3343 ctxt->op_bytes = 8;
9dac77fa 3344 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3345 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3346 ctxt->op_bytes);
26d05cc7
AK		 3347 if (rc != X86EMUL_CONTINUE)
3348 return rc;
3349 ctxt->ops->set_idt(ctxt, &desc_ptr);
3350 /* Disable writeback. */
9dac77fa 3351 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3352 return X86EMUL_CONTINUE;
3353}
3354
3355static int em_smsw(struct x86_emulate_ctxt *ctxt)
3356{
9dac77fa
AK		 3357 ctxt->dst.bytes = 2;
3358 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3359 return X86EMUL_CONTINUE;
3360}
3361
3362static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3363{
26d05cc7 3364 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3365 | (ctxt->src.val & 0x0f));
3366 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3367 return X86EMUL_CONTINUE;
3368}
3369
d06e03ad
TY		 3370static int em_loop(struct x86_emulate_ctxt *ctxt)
3371{
dd856efa
AK		 3372 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3373 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3374 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3375 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3376
3377 return X86EMUL_CONTINUE;
3378}
3379
3380static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3381{
dd856efa 3382 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3383 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3384
3385 return X86EMUL_CONTINUE;
3386}
3387
d7841a4b
TY		 3388static int em_in(struct x86_emulate_ctxt *ctxt)
3389{
3390 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3391 &ctxt->dst.val))
3392 return X86EMUL_IO_NEEDED;
3393
3394 return X86EMUL_CONTINUE;
3395}
3396
3397static int em_out(struct x86_emulate_ctxt *ctxt)
3398{
3399 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3400 &ctxt->src.val, 1);
3401 /* Disable writeback. */
3402 ctxt->dst.type = OP_NONE;
3403 return X86EMUL_CONTINUE;
3404}
3405
f411e6cd
TY		 3406static int em_cli(struct x86_emulate_ctxt *ctxt)
3407{
3408 if (emulator_bad_iopl(ctxt))
3409 return emulate_gp(ctxt, 0);
3410
3411 ctxt->eflags &= ~X86_EFLAGS_IF;
3412 return X86EMUL_CONTINUE;
3413}
3414
3415static int em_sti(struct x86_emulate_ctxt *ctxt)
3416{
3417 if (emulator_bad_iopl(ctxt))
3418 return emulate_gp(ctxt, 0);
3419
3420 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3421 ctxt->eflags |= X86_EFLAGS_IF;
3422 return X86EMUL_CONTINUE;
3423}
3424
6d6eede4
AK		 3425static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3426{
3427 u32 eax, ebx, ecx, edx;
3428
dd856efa
AK		 3429 eax = reg_read(ctxt, VCPU_REGS_RAX);
3430 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3431 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3432 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3433 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3434 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3435 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3436 return X86EMUL_CONTINUE;
3437}
3438
2dd7caa0
AK		 3439static int em_lahf(struct x86_emulate_ctxt *ctxt)
3440{
dd856efa
AK		 3441 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3442 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3443 return X86EMUL_CONTINUE;
3444}
3445
9299836e
AK		 3446static int em_bswap(struct x86_emulate_ctxt *ctxt)
3447{
3448 switch (ctxt->op_bytes) {
3449#ifdef CONFIG_X86_64
3450 case 8:
3451 asm("bswap %0" : "+r"(ctxt->dst.val));
3452 break;
3453#endif
3454 default:
3455 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3456 break;
3457 }
3458 return X86EMUL_CONTINUE;
3459}
3460
cfec82cb
JR		 3461static bool valid_cr(int nr)
3462{
3463 switch (nr) {
3464 case 0:
3465 case 2 ... 4:
3466 case 8:
3467 return true;
3468 default:
3469 return false;
3470 }
3471}
3472
3473static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3474{
9dac77fa 3475 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3476 return emulate_ud(ctxt);
3477
3478 return X86EMUL_CONTINUE;
3479}
3480
3481static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3482{
9dac77fa
AK		 3483 u64 new_val = ctxt->src.val64;
3484 int cr = ctxt->modrm_reg;
c2ad2bb3 3485 u64 efer = 0;
cfec82cb
JR		 3486
3487 static u64 cr_reserved_bits[] = {
3488 0xffffffff00000000ULL,
3489 0, 0, 0, /* CR3 checked later */
3490 CR4_RESERVED_BITS,
3491 0, 0, 0,
3492 CR8_RESERVED_BITS,
3493 };
3494
3495 if (!valid_cr(cr))
3496 return emulate_ud(ctxt);
3497
3498 if (new_val & cr_reserved_bits[cr])
3499 return emulate_gp(ctxt, 0);
3500
3501 switch (cr) {
3502 case 0: {
c2ad2bb3 3503 u64 cr4;
cfec82cb
JR		 3504 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3505 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3506 return emulate_gp(ctxt, 0);
3507
717746e3
AK		 3508 cr4 = ctxt->ops->get_cr(ctxt, 4);
3509 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3510
3511 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3512 !(cr4 & X86_CR4_PAE))
3513 return emulate_gp(ctxt, 0);
3514
3515 break;
3516 }
3517 case 3: {
3518 u64 rsvd = 0;
3519
c2ad2bb3
AK		 3520 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3521 if (efer & EFER_LMA)
cfec82cb 3522 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3523 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3524 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3525 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3526 rsvd = CR3_NONPAE_RESERVED_BITS;
3527
3528 if (new_val & rsvd)
3529 return emulate_gp(ctxt, 0);
3530
3531 break;
3532 }
3533 case 4: {
717746e3 3534 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3535
3536 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3537 return emulate_gp(ctxt, 0);
3538
3539 break;
3540 }
3541 }
3542
3543 return X86EMUL_CONTINUE;
3544}
3545
3b88e41a
JR		 3546static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3547{
3548 unsigned long dr7;
3549
717746e3 3550 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3551
3552 /* Check if DR7.Global_Enable is set */
3553 return dr7 & (1 << 13);
3554}
3555
3556static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3557{
9dac77fa 3558 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3559 u64 cr4;
3560
3561 if (dr > 7)
3562 return emulate_ud(ctxt);
3563
717746e3 3564 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3565 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3566 return emulate_ud(ctxt);
3567
3568 if (check_dr7_gd(ctxt))
3569 return emulate_db(ctxt);
3570
3571 return X86EMUL_CONTINUE;
3572}
3573
3574static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3575{
9dac77fa
AK		 3576 u64 new_val = ctxt->src.val64;
3577 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3578
3579 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3580 return emulate_gp(ctxt, 0);
3581
3582 return check_dr_read(ctxt);
3583}
3584
01de8b09
JR		 3585static int check_svme(struct x86_emulate_ctxt *ctxt)
3586{
3587 u64 efer;
3588
717746e3 3589 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3590
3591 if (!(efer & EFER_SVME))
3592 return emulate_ud(ctxt);
3593
3594 return X86EMUL_CONTINUE;
3595}
3596
3597static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3598{
dd856efa 3599 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3600
3601 /* Valid physical address? */
d4224449 3602 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3603 return emulate_gp(ctxt, 0);
3604
3605 return check_svme(ctxt);
3606}
3607
d7eb8203
JR		 3608static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3609{
717746e3 3610 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3611
717746e3 3612 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3613 return emulate_ud(ctxt);
3614
3615 return X86EMUL_CONTINUE;
3616}
3617
8061252e
JR		 3618static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3619{
717746e3 3620 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3621 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3622
717746e3 3623 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3624 (rcx > 3))
3625 return emulate_gp(ctxt, 0);
3626
3627 return X86EMUL_CONTINUE;
3628}
3629
f6511935
JR		 3630static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3631{
9dac77fa
AK		 3632 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3633 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3634 return emulate_gp(ctxt, 0);
3635
3636 return X86EMUL_CONTINUE;
3637}
3638
3639static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3640{
9dac77fa
AK		 3641 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3642 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3643 return emulate_gp(ctxt, 0);
3644
3645 return X86EMUL_CONTINUE;
3646}
3647
73fba5f4 3648#define D(_y) { .flags = (_y) }
c4f035c6 3649#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3650#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3651 .check_perm = (_p) }
0b789eee 3652#define N D(NotImpl)
01de8b09 3653#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3654#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3655#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3656#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3657#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3658#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3659#define II(_f, _e, _i) \
3660 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3661#define IIP(_f, _e, _i, _p) \
3662 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3663 .check_perm = (_p) }
aa97bb48 3664#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3665
8d8f4e9f 3666#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3667#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3668#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3669#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3670#define I2bvIP(_f, _e, _i, _p) \
3671 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3672
fb864fbc
AK		 3673#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3674 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3675 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3676
fd0a0d82 3677static const struct opcode group7_rm1[] = {
1c2545be
TY		 3678 DI(SrcNone | Priv, monitor),
3679 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3680 N, N, N, N, N, N,
3681};
3682
fd0a0d82 3683static const struct opcode group7_rm3[] = {
1c2545be
TY		 3684 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3685 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3686 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3687 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3688 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3689 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3690 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3691 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3692};
6230f7fc 3693
fd0a0d82 3694static const struct opcode group7_rm7[] = {
d7eb8203 3695 N,
1c2545be 3696 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3697 N, N, N, N, N, N,
3698};
d67fc27a 3699
fd0a0d82 3700static const struct opcode group1[] = {
fb864fbc
AK		 3701 F(Lock, em_add),
3702 F(Lock | PageTable, em_or),
3703 F(Lock, em_adc),
3704 F(Lock, em_sbb),
3705 F(Lock | PageTable, em_and),
3706 F(Lock, em_sub),
3707 F(Lock, em_xor),
3708 F(NoWrite, em_cmp),
73fba5f4
AK		 3709};
3710
fd0a0d82 3711static const struct opcode group1A[] = {
1c2545be 3712 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3713};
3714
007a3b54
AK		 3715static const struct opcode group2[] = {
3716 F(DstMem | ModRM, em_rol),
3717 F(DstMem | ModRM, em_ror),
3718 F(DstMem | ModRM, em_rcl),
3719 F(DstMem | ModRM, em_rcr),
3720 F(DstMem | ModRM, em_shl),
3721 F(DstMem | ModRM, em_shr),
3722 F(DstMem | ModRM, em_shl),
3723 F(DstMem | ModRM, em_sar),
3724};
3725
fd0a0d82 3726static const struct opcode group3[] = {
fb864fbc
AK		 3727 F(DstMem | SrcImm | NoWrite, em_test),
3728 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3729 F(DstMem | SrcNone | Lock, em_not),
3730 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3731 I(SrcMem, em_mul_ex),
3732 I(SrcMem, em_imul_ex),
3733 I(SrcMem, em_div_ex),
3734 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3735};
3736
fd0a0d82 3737static const struct opcode group4[] = {
95413dc4
AK		 3738 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3739 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3740 N, N, N, N, N, N,
3741};
3742
fd0a0d82 3743static const struct opcode group5[] = {
95413dc4
AK		 3744 F(DstMem | SrcNone | Lock, em_inc),
3745 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3746 I(SrcMem | Stack, em_grp45),
3747 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3748 I(SrcMem | Stack, em_grp45),
3749 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3750 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3751};
3752
fd0a0d82 3753static const struct opcode group6[] = {
1c2545be
TY		 3754 DI(Prot, sldt),
3755 DI(Prot, str),
a14e579f 3756 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3757 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3758 N, N, N, N,
3759};
3760
fd0a0d82 3761static const struct group_dual group7 = { {
96051572
AK		 3762 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3763 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3764 II(SrcMem | Priv, em_lgdt, lgdt),
3765 II(SrcMem | Priv, em_lidt, lidt),
3766 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3767 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3768 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3769}, {
1c2545be 3770 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3771 EXT(0, group7_rm1),
01de8b09 3772 N, EXT(0, group7_rm3),
1c2545be
TY		 3773 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3774 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3775 EXT(0, group7_rm7),
73fba5f4
AK		 3776} };
3777
fd0a0d82 3778static const struct opcode group8[] = {
73fba5f4 3779 N, N, N, N,
11c363ba
AK		 3780 F(DstMem | SrcImmByte | NoWrite, em_bt),
3781 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3782 F(DstMem | SrcImmByte | Lock, em_btr),
3783 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3784};
3785
fd0a0d82 3786static const struct group_dual group9 = { {
1c2545be 3787 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3788}, {
3789 N, N, N, N, N, N, N, N,
3790} };
3791
fd0a0d82 3792static const struct opcode group11[] = {
1c2545be 3793 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3794 X7(D(Undefined)),
a4d4a7c1
AK		 3795};
3796
fd0a0d82 3797static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3798 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3799};
3800
fd0a0d82 3801static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3802 I(0, em_mov), N, N, N,
3803};
3804
045a282c
GN		 3805static const struct escape escape_d9 = { {
3806 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3807}, {
3808 /* 0xC0 - 0xC7 */
3809 N, N, N, N, N, N, N, N,
3810 /* 0xC8 - 0xCF */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xD0 - 0xC7 */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xD8 - 0xDF */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xE0 - 0xE7 */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xE8 - 0xEF */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xF0 - 0xF7 */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xF8 - 0xFF */
3823 N, N, N, N, N, N, N, N,
3824} };
3825
3826static const struct escape escape_db = { {
3827 N, N, N, N, N, N, N, N,
3828}, {
3829 /* 0xC0 - 0xC7 */
3830 N, N, N, N, N, N, N, N,
3831 /* 0xC8 - 0xCF */
3832 N, N, N, N, N, N, N, N,
3833 /* 0xD0 - 0xC7 */
3834 N, N, N, N, N, N, N, N,
3835 /* 0xD8 - 0xDF */
3836 N, N, N, N, N, N, N, N,
3837 /* 0xE0 - 0xE7 */
3838 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3839 /* 0xE8 - 0xEF */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xF0 - 0xF7 */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xF8 - 0xFF */
3844 N, N, N, N, N, N, N, N,
3845} };
3846
3847static const struct escape escape_dd = { {
3848 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3849}, {
3850 /* 0xC0 - 0xC7 */
3851 N, N, N, N, N, N, N, N,
3852 /* 0xC8 - 0xCF */
3853 N, N, N, N, N, N, N, N,
3854 /* 0xD0 - 0xC7 */
3855 N, N, N, N, N, N, N, N,
3856 /* 0xD8 - 0xDF */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xE0 - 0xE7 */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xE8 - 0xEF */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xF0 - 0xF7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xF8 - 0xFF */
3865 N, N, N, N, N, N, N, N,
3866} };
3867
fd0a0d82 3868static const struct opcode opcode_table[256] = {
73fba5f4 3869 /* 0x00 - 0x07 */
fb864fbc 3870 F6ALU(Lock, em_add),
1cd196ea
AK		 3871 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3872 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3873 /* 0x08 - 0x0F */
fb864fbc 3874 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3875 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3876 N,
73fba5f4 3877 /* 0x10 - 0x17 */
fb864fbc 3878 F6ALU(Lock, em_adc),
1cd196ea
AK		 3879 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3880 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3881 /* 0x18 - 0x1F */
fb864fbc 3882 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3883 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3884 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3885 /* 0x20 - 0x27 */
fb864fbc 3886 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3887 /* 0x28 - 0x2F */
fb864fbc 3888 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3889 /* 0x30 - 0x37 */
fb864fbc 3890 F6ALU(Lock, em_xor), N, N,
73fba5f4 3891 /* 0x38 - 0x3F */
fb864fbc 3892 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3893 /* 0x40 - 0x4F */
95413dc4 3894 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3895 /* 0x50 - 0x57 */
63540382 3896 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3897 /* 0x58 - 0x5F */
c54fe504 3898 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3899 /* 0x60 - 0x67 */
b96a7fad
TY		 3900 I(ImplicitOps | Stack | No64, em_pusha),
3901 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3902 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3903 N, N, N, N,
3904 /* 0x68 - 0x6F */
d46164db
AK		 3905 I(SrcImm | Mov | Stack, em_push),
3906 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3907 I(SrcImmByte | Mov | Stack, em_push),
3908 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3909 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3910 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3911 /* 0x70 - 0x7F */
3912 X16(D(SrcImmByte)),
3913 /* 0x80 - 0x87 */
1c2545be
TY		 3914 G(ByteOp | DstMem | SrcImm, group1),
3915 G(DstMem | SrcImm, group1),
3916 G(ByteOp | DstMem | SrcImm | No64, group1),
3917 G(DstMem | SrcImmByte, group1),
fb864fbc 3918 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3919 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3920 /* 0x88 - 0x8F */
d5ae7ce8 3921 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3922 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3923 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3924 D(ModRM | SrcMem | NoAccess | DstReg),
3925 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3926 G(0, group1A),
73fba5f4 3927 /* 0x90 - 0x97 */
bf608f88 3928 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3929 /* 0x98 - 0x9F */
61429142 3930 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3931 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3932 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3933 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3934 /* 0xA0 - 0xA7 */
b9eac5f4 3935 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3936 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3937 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3938 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3939 /* 0xA8 - 0xAF */
fb864fbc 3940 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3941 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3942 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3943 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3944 /* 0xB0 - 0xB7 */
b9eac5f4 3945 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3946 /* 0xB8 - 0xBF */
5e2c6883 3947 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3948 /* 0xC0 - 0xC7 */
007a3b54 3949 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3950 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3951 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3952 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3953 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3954 G(ByteOp, group11), G(0, group11),
73fba5f4 3955 /* 0xC8 - 0xCF */
612e89f0
AK		 3956 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3957 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3958 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3959 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3960 /* 0xD0 - 0xD7 */
007a3b54
AK		 3961 G(Src2One | ByteOp, group2), G(Src2One, group2),
3962 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3963 I(DstAcc | SrcImmUByte | No64, em_aam),
7fa57952
PB		 3964 I(DstAcc | SrcImmUByte | No64, em_aad), N,
3965 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3966 /* 0xD8 - 0xDF */
045a282c 3967 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3968 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3969 X3(I(SrcImmByte, em_loop)),
3970 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3971 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3972 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3973 /* 0xE8 - 0xEF */
d4ddafcd 3974 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3975 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3976 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3977 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3978 /* 0xF0 - 0xF7 */
bf608f88 3979 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3980 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3981 G(ByteOp, group3), G(0, group3),
73fba5f4 3982 /* 0xF8 - 0xFF */
f411e6cd
TY		 3983 D(ImplicitOps), D(ImplicitOps),
3984 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3985 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3986};
3987
fd0a0d82 3988static const struct opcode twobyte_table[256] = {
73fba5f4 3989 /* 0x00 - 0x0F */
dee6bb70 3990 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3991 N, I(ImplicitOps | VendorSpecific, em_syscall),
3992 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3993 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3994 N, D(ImplicitOps | ModRM), N, N,
3995 /* 0x10 - 0x1F */
3996 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3997 /* 0x20 - 0x2F */
cfec82cb 3998 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3999 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4000 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4001 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4002 N, N, N, N,
3e114eb4
AK		 4003 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4004 N, N, N, N,
73fba5f4 4005 /* 0x30 - 0x3F */
e1e210b0 4006 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4007 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4008 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4009 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4010 I(ImplicitOps | VendorSpecific, em_sysenter),
4011 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4012 N, N,
73fba5f4
AK		 4013 N, N, N, N, N, N, N, N,
4014 /* 0x40 - 0x4F */
4015 X16(D(DstReg | SrcMem | ModRM | Mov)),
4016 /* 0x50 - 0x5F */
4017 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4018 /* 0x60 - 0x6F */
aa97bb48
AK		 4019 N, N, N, N,
4020 N, N, N, N,
4021 N, N, N, N,
4022 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4023 /* 0x70 - 0x7F */
aa97bb48
AK		 4024 N, N, N, N,
4025 N, N, N, N,
4026 N, N, N, N,
4027 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4028 /* 0x80 - 0x8F */
4029 X16(D(SrcImm)),
4030 /* 0x90 - 0x9F */
ee45b58e 4031 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4032 /* 0xA0 - 0xA7 */
1cd196ea 4033 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4034 II(ImplicitOps, em_cpuid, cpuid),
4035 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4036 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4037 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4038 /* 0xA8 - 0xAF */
1cd196ea 4039 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4040 DI(ImplicitOps, rsm),
11c363ba 4041 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4042 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4043 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4044 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4045 /* 0xB0 - 0xB7 */
e940b5c2 4046 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4047 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4048 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4049 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4050 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4051 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4052 /* 0xB8 - 0xBF */
4053 N, N,
ce7faab2 4054 G(BitOp, group8),
11c363ba
AK		 4055 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4056 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4057 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4058 /* 0xC0 - 0xC7 */
739ae406 4059 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4060 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4061 N, N, N, GD(0, &group9),
9299836e
AK		 4062 /* 0xC8 - 0xCF */
4063 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4064 /* 0xD0 - 0xDF */
4065 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4066 /* 0xE0 - 0xEF */
4067 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4068 /* 0xF0 - 0xFF */
4069 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4070};
4071
4072#undef D
4073#undef N
4074#undef G
4075#undef GD
4076#undef I
aa97bb48 4077#undef GP
01de8b09 4078#undef EXT
73fba5f4 4079
8d8f4e9f 4080#undef D2bv
f6511935 4081#undef D2bvIP
8d8f4e9f 4082#undef I2bv
d7841a4b 4083#undef I2bvIP
d67fc27a 4084#undef I6ALU
8d8f4e9f 4085
9dac77fa 4086static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4087{
4088 unsigned size;
4089
9dac77fa 4090 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4091 if (size == 8)
4092 size = 4;
4093 return size;
4094}
4095
4096static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4097 unsigned size, bool sign_extension)
4098{
39f21ee5
AK		 4099 int rc = X86EMUL_CONTINUE;
4100
4101 op->type = OP_IMM;
4102 op->bytes = size;
9dac77fa 4103 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4104 /* NB. Immediates are sign-extended as necessary. */
4105 switch (op->bytes) {
4106 case 1:
e85a1085 4107 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4108 break;
4109 case 2:
e85a1085 4110 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4111 break;
4112 case 4:
e85a1085 4113 op->val = insn_fetch(s32, ctxt);
39f21ee5 4114 break;
5e2c6883
NA		 4115 case 8:
4116 op->val = insn_fetch(s64, ctxt);
4117 break;
39f21ee5
AK		 4118 }
4119 if (!sign_extension) {
4120 switch (op->bytes) {
4121 case 1:
4122 op->val &= 0xff;
4123 break;
4124 case 2:
4125 op->val &= 0xffff;
4126 break;
4127 case 4:
4128 op->val &= 0xffffffff;
4129 break;
4130 }
4131 }
4132done:
4133 return rc;
4134}
4135
a9945549
AK		 4136static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4137 unsigned d)
4138{
4139 int rc = X86EMUL_CONTINUE;
4140
4141 switch (d) {
4142 case OpReg:
2adb5ad9 4143 decode_register_operand(ctxt, op);
a9945549
AK		 4144 break;
4145 case OpImmUByte:
608aabe3 4146 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4147 break;
4148 case OpMem:
41ddf978 4149 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4150 mem_common:
4151 *op = ctxt->memop;
4152 ctxt->memopp = op;
4153 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4154 fetch_bit_operand(ctxt);
4155 op->orig_val = op->val;
4156 break;
41ddf978
AK		 4157 case OpMem64:
4158 ctxt->memop.bytes = 8;
4159 goto mem_common;
a9945549
AK		 4160 case OpAcc:
4161 op->type = OP_REG;
4162 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4163 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4164 fetch_register_operand(op);
4165 op->orig_val = op->val;
4166 break;
4167 case OpDI:
4168 op->type = OP_MEM;
4169 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4170 op->addr.mem.ea =
dd856efa 4171 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4172 op->addr.mem.seg = VCPU_SREG_ES;
4173 op->val = 0;
b3356bf0 4174 op->count = 1;
a9945549
AK		 4175 break;
4176 case OpDX:
4177 op->type = OP_REG;
4178 op->bytes = 2;
dd856efa 4179 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4180 fetch_register_operand(op);
4181 break;
4dd6a57d
AK		 4182 case OpCL:
4183 op->bytes = 1;
dd856efa 4184 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4185 break;
4186 case OpImmByte:
4187 rc = decode_imm(ctxt, op, 1, true);
4188 break;
4189 case OpOne:
4190 op->bytes = 1;
4191 op->val = 1;
4192 break;
4193 case OpImm:
4194 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4195 break;
5e2c6883
NA		 4196 case OpImm64:
4197 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4198 break;
28867cee
AK		 4199 case OpMem8:
4200 ctxt->memop.bytes = 1;
660696d1
GN		 4201 if (ctxt->memop.type == OP_REG) {
4202 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4203 fetch_register_operand(&ctxt->memop);
4204 }
28867cee 4205 goto mem_common;
0fe59128
AK		 4206 case OpMem16:
4207 ctxt->memop.bytes = 2;
4208 goto mem_common;
4209 case OpMem32:
4210 ctxt->memop.bytes = 4;
4211 goto mem_common;
4212 case OpImmU16:
4213 rc = decode_imm(ctxt, op, 2, false);
4214 break;
4215 case OpImmU:
4216 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4217 break;
4218 case OpSI:
4219 op->type = OP_MEM;
4220 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4221 op->addr.mem.ea =
dd856efa 4222 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4223 op->addr.mem.seg = seg_override(ctxt);
4224 op->val = 0;
b3356bf0 4225 op->count = 1;
0fe59128 4226 break;
7fa57952
PB		 4227 case OpXLat:
4228 op->type = OP_MEM;
4229 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4230 op->addr.mem.ea =
4231 register_address(ctxt,
4232 reg_read(ctxt, VCPU_REGS_RBX) +
4233 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4234 op->addr.mem.seg = seg_override(ctxt);
4235 op->val = 0;
4236 break;
0fe59128
AK		 4237 case OpImmFAddr:
4238 op->type = OP_IMM;
4239 op->addr.mem.ea = ctxt->_eip;
4240 op->bytes = ctxt->op_bytes + 2;
4241 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4242 break;
4243 case OpMemFAddr:
4244 ctxt->memop.bytes = ctxt->op_bytes + 2;
4245 goto mem_common;
c191a7a0
AK		 4246 case OpES:
4247 op->val = VCPU_SREG_ES;
4248 break;
4249 case OpCS:
4250 op->val = VCPU_SREG_CS;
4251 break;
4252 case OpSS:
4253 op->val = VCPU_SREG_SS;
4254 break;
4255 case OpDS:
4256 op->val = VCPU_SREG_DS;
4257 break;
4258 case OpFS:
4259 op->val = VCPU_SREG_FS;
4260 break;
4261 case OpGS:
4262 op->val = VCPU_SREG_GS;
4263 break;
a9945549
AK		 4264 case OpImplicit:
4265 /* Special instructions do their own operand decoding. */
4266 default:
4267 op->type = OP_NONE; /* Disable writeback. */
4268 break;
4269 }
4270
4271done:
4272 return rc;
4273}
4274
ef5d75cc 4275int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4276{
dde7e6d1
AK		 4277 int rc = X86EMUL_CONTINUE;
4278 int mode = ctxt->mode;
46561646 4279 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4280 bool op_prefix = false;
46561646 4281 struct opcode opcode;
dde7e6d1 4282
f09ed83e
AK		 4283 ctxt->memop.type = OP_NONE;
4284 ctxt->memopp = NULL;
9dac77fa
AK		 4285 ctxt->_eip = ctxt->eip;
4286 ctxt->fetch.start = ctxt->_eip;
4287 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4288 if (insn_len > 0)
9dac77fa 4289 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4290
4291 switch (mode) {
4292 case X86EMUL_MODE_REAL:
4293 case X86EMUL_MODE_VM86:
4294 case X86EMUL_MODE_PROT16:
4295 def_op_bytes = def_ad_bytes = 2;
4296 break;
4297 case X86EMUL_MODE_PROT32:
4298 def_op_bytes = def_ad_bytes = 4;
4299 break;
4300#ifdef CONFIG_X86_64
4301 case X86EMUL_MODE_PROT64:
4302 def_op_bytes = 4;
4303 def_ad_bytes = 8;
4304 break;
4305#endif
4306 default:
1d2887e2 4307 return EMULATION_FAILED;
dde7e6d1
AK		 4308 }
4309
9dac77fa
AK		 4310 ctxt->op_bytes = def_op_bytes;
4311 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4312
4313 /* Legacy prefixes. */
4314 for (;;) {
e85a1085 4315 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4316 case 0x66: /* operand-size override */
0d7cdee8 4317 op_prefix = true;
dde7e6d1 4318 /* switch between 2/4 bytes */
9dac77fa 4319 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4320 break;
4321 case 0x67: /* address-size override */
4322 if (mode == X86EMUL_MODE_PROT64)
4323 /* switch between 4/8 bytes */
9dac77fa 4324 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4325 else
4326 /* switch between 2/4 bytes */
9dac77fa 4327 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4328 break;
4329 case 0x26: /* ES override */
4330 case 0x2e: /* CS override */
4331 case 0x36: /* SS override */
4332 case 0x3e: /* DS override */
9dac77fa 4333 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4334 break;
4335 case 0x64: /* FS override */
4336 case 0x65: /* GS override */
9dac77fa 4337 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4338 break;
4339 case 0x40 ... 0x4f: /* REX */
4340 if (mode != X86EMUL_MODE_PROT64)
4341 goto done_prefixes;
9dac77fa 4342 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4343 continue;
4344 case 0xf0: /* LOCK */
9dac77fa 4345 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4346 break;
4347 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4348 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4349 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4350 break;
4351 default:
4352 goto done_prefixes;
4353 }
4354
4355 /* Any legacy prefix after a REX prefix nullifies its effect. */
4356
9dac77fa 4357 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4358 }
4359
4360done_prefixes:
4361
4362 /* REX prefix. */
9dac77fa
AK		 4363 if (ctxt->rex_prefix & 8)
4364 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4365
4366 /* Opcode byte(s). */
9dac77fa 4367 opcode = opcode_table[ctxt->b];
d3ad6243 4368 /* Two-byte opcode? */
9dac77fa
AK		 4369 if (ctxt->b == 0x0f) {
4370 ctxt->twobyte = 1;
e85a1085 4371 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4372 opcode = twobyte_table[ctxt->b];
dde7e6d1 4373 }
9dac77fa 4374 ctxt->d = opcode.flags;
dde7e6d1 4375
9f4260e7
TY		 4376 if (ctxt->d & ModRM)
4377 ctxt->modrm = insn_fetch(u8, ctxt);
4378
9dac77fa
AK		 4379 while (ctxt->d & GroupMask) {
4380 switch (ctxt->d & GroupMask) {
46561646 4381 case Group:
9dac77fa 4382 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4383 opcode = opcode.u.group[goffset];
4384 break;
4385 case GroupDual:
9dac77fa
AK		 4386 goffset = (ctxt->modrm >> 3) & 7;
4387 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4388 opcode = opcode.u.gdual->mod3[goffset];
4389 else
4390 opcode = opcode.u.gdual->mod012[goffset];
4391 break;
4392 case RMExt:
9dac77fa 4393 goffset = ctxt->modrm & 7;
01de8b09 4394 opcode = opcode.u.group[goffset];
46561646
AK		 4395 break;
4396 case Prefix:
9dac77fa 4397 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4398 return EMULATION_FAILED;
9dac77fa 4399 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4400 switch (simd_prefix) {
4401 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4402 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4403 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4404 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4405 }
4406 break;
045a282c
GN		 4407 case Escape:
4408 if (ctxt->modrm > 0xbf)
4409 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4410 else
4411 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4412 break;
46561646 4413 default:
1d2887e2 4414 return EMULATION_FAILED;
0d7cdee8 4415 }
46561646 4416
b1ea50b2 4417 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4418 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4419 }
4420
9dac77fa
AK		 4421 ctxt->execute = opcode.u.execute;
4422 ctxt->check_perm = opcode.check_perm;
4423 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4424
4425 /* Unrecognised? */
1146a78b 4426 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4427 return EMULATION_FAILED;
dde7e6d1 4428
9dac77fa 4429 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4430 return EMULATION_FAILED;
d867162c 4431
9dac77fa
AK		 4432 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4433 ctxt->op_bytes = 8;
dde7e6d1 4434
9dac77fa 4435 if (ctxt->d & Op3264) {
7f9b4b75 4436 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4437 ctxt->op_bytes = 8;
7f9b4b75 4438 else
9dac77fa 4439 ctxt->op_bytes = 4;
7f9b4b75
AK		 4440 }
4441
9dac77fa
AK		 4442 if (ctxt->d & Sse)
4443 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4444 else if (ctxt->d & Mmx)
4445 ctxt->op_bytes = 8;
1253791d 4446
dde7e6d1 4447 /* ModRM and SIB bytes. */
9dac77fa 4448 if (ctxt->d & ModRM) {
f09ed83e 4449 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4450 if (!ctxt->has_seg_override)
4451 set_seg_override(ctxt, ctxt->modrm_seg);
4452 } else if (ctxt->d & MemAbs)
f09ed83e 4453 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4454 if (rc != X86EMUL_CONTINUE)
4455 goto done;
4456
9dac77fa
AK		 4457 if (!ctxt->has_seg_override)
4458 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4459
f09ed83e 4460 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4461
f09ed83e
AK		 4462 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4463 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4464
dde7e6d1
AK		 4465 /*
4466 * Decode and fetch the source operand: register, memory
4467 * or immediate.
4468 */
0fe59128 4469 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4470 if (rc != X86EMUL_CONTINUE)
4471 goto done;
4472
dde7e6d1
AK		 4473 /*
4474 * Decode and fetch the second source operand: register, memory
4475 * or immediate.
4476 */
4dd6a57d 4477 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4478 if (rc != X86EMUL_CONTINUE)
4479 goto done;
4480
dde7e6d1 4481 /* Decode and fetch the destination operand: register or memory. */
a9945549 4482 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4483
4484done:
f09ed83e
AK		 4485 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4486 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4487
1d2887e2 4488 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4489}
4490
1cb3f3ae
XG		 4491bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4492{
4493 return ctxt->d & PageTable;
4494}
4495
3e2f65d5
GN		 4496static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4497{
3e2f65d5
GN		 4498 /* The second termination condition only applies for REPE
4499 * and REPNE. Test if the repeat string operation prefix is
4500 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4501 * corresponding termination condition according to:
4502 * - if REPE/REPZ and ZF = 0 then done
4503 * - if REPNE/REPNZ and ZF = 1 then done
4504 */
9dac77fa
AK		 4505 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4506 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4507 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4508 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4509 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4510 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4511 return true;
4512
4513 return false;
4514}
4515
cbe2c9d3
AK		 4516static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4517{
4518 bool fault = false;
4519
4520 ctxt->ops->get_fpu(ctxt);
4521 asm volatile("1: fwait \n\t"
4522 "2: \n\t"
4523 ".pushsection .fixup,\"ax\" \n\t"
4524 "3: \n\t"
4525 "movb $1, %[fault] \n\t"
4526 "jmp 2b \n\t"
4527 ".popsection \n\t"
4528 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4529 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4530 ctxt->ops->put_fpu(ctxt);
4531
4532 if (unlikely(fault))
4533 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4534
4535 return X86EMUL_CONTINUE;
4536}
4537
4538static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4539 struct operand *op)
4540{
4541 if (op->type == OP_MM)
4542 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4543}
4544
e28bbd44
AK		 4545static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4546{
4547 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4549 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4550 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4551 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4552 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4553 return X86EMUL_CONTINUE;
4554}
dd856efa 4555
7b105ca2 4556int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4557{
0225fb50 4558 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4559 int rc = X86EMUL_CONTINUE;
9dac77fa 4560 int saved_dst_type = ctxt->dst.type;
8b4caf66 4561
9dac77fa 4562 ctxt->mem_read.pos = 0;
310b5d30 4563
1146a78b
GN		 4564 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4565 (ctxt->d & Undefined)) {
35d3d4a1 4566 rc = emulate_ud(ctxt);
1161624f
GN		 4567 goto done;
4568 }
4569
d380a5e4 4570 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4571 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4572 rc = emulate_ud(ctxt);
d380a5e4
GN		 4573 goto done;
4574 }
4575
9dac77fa 4576 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4577 rc = emulate_ud(ctxt);
081bca0e
AK		 4578 goto done;
4579 }
4580
cbe2c9d3
AK		 4581 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4582 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4583 rc = emulate_ud(ctxt);
4584 goto done;
4585 }
4586
cbe2c9d3 4587 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4588 rc = emulate_nm(ctxt);
4589 goto done;
4590 }
4591
cbe2c9d3
AK		 4592 if (ctxt->d & Mmx) {
4593 rc = flush_pending_x87_faults(ctxt);
4594 if (rc != X86EMUL_CONTINUE)
4595 goto done;
4596 /*
4597 * Now that we know the fpu is exception safe, we can fetch
4598 * operands from it.
4599 */
4600 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4601 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4602 if (!(ctxt->d & Mov))
4603 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4604 }
4605
9dac77fa
AK		 4606 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4607 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4608 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4609 if (rc != X86EMUL_CONTINUE)
4610 goto done;
4611 }
4612
e92805ac 4613 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4614 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4615 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4616 goto done;
4617 }
4618
8ea7d6ae 4619 /* Instruction can only be executed in protected mode */
9d1b39a9 4620 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4621 rc = emulate_ud(ctxt);
4622 goto done;
4623 }
4624
d09beabd 4625 /* Do instruction specific permission checks */
9dac77fa
AK		 4626 if (ctxt->check_perm) {
4627 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4628 if (rc != X86EMUL_CONTINUE)
4629 goto done;
4630 }
4631
9dac77fa
AK		 4632 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4633 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4634 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637 }
4638
9dac77fa 4639 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4640 /* All REP prefixes have the same first termination condition */
dd856efa 4641 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4642 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4643 goto done;
4644 }
b9fa9d6b
AK		 4645 }
4646
9dac77fa
AK		 4647 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4648 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4649 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4650 if (rc != X86EMUL_CONTINUE)
8b4caf66 4651 goto done;
9dac77fa 4652 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4653 }
4654
9dac77fa
AK		 4655 if (ctxt->src2.type == OP_MEM) {
4656 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4657 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4658 if (rc != X86EMUL_CONTINUE)
4659 goto done;
4660 }
4661
9dac77fa 4662 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4663 goto special_insn;
4664
4665
9dac77fa 4666 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4667 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4668 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4669 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4670 if (rc != X86EMUL_CONTINUE)
4671 goto done;
038e51de 4672 }
9dac77fa 4673 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4674
018a98db
AK		 4675special_insn:
4676
9dac77fa
AK		 4677 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4678 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4679 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4680 if (rc != X86EMUL_CONTINUE)
4681 goto done;
4682 }
4683
9dac77fa 4684 if (ctxt->execute) {
e28bbd44
AK		 4685 if (ctxt->d & Fastop) {
4686 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4687 rc = fastop(ctxt, fop);
4688 if (rc != X86EMUL_CONTINUE)
4689 goto done;
4690 goto writeback;
4691 }
9dac77fa 4692 rc = ctxt->execute(ctxt);
ef65c889
AK		 4693 if (rc != X86EMUL_CONTINUE)
4694 goto done;
4695 goto writeback;
4696 }
4697
9dac77fa 4698 if (ctxt->twobyte)
6aa8b732
AK		 4699 goto twobyte_insn;
4700
9dac77fa 4701 switch (ctxt->b) {
6aa8b732 4702 case 0x63: /* movsxd */
8b4caf66 4703 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4704 goto cannot_emulate;
9dac77fa 4705 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4706 break;
b2833e3c 4707 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4708 if (test_cc(ctxt->b, ctxt->eflags))
4709 jmp_rel(ctxt, ctxt->src.val);
018a98db 4710 break;
7e0b54b1 4711 case 0x8d: /* lea r16/r32, m */
9dac77fa 4712 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4713 break;
3d9e77df 4714 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4715 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4716 break;
e4f973ae
TY		 4717 rc = em_xchg(ctxt);
4718 break;
e8b6fa70 4719 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4720 switch (ctxt->op_bytes) {
4721 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4722 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4723 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4724 }
4725 break;
6e154e56 4726 case 0xcc: /* int3 */
5c5df76b
TY		 4727 rc = emulate_int(ctxt, 3);
4728 break;
6e154e56 4729 case 0xcd: /* int n */
9dac77fa 4730 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4731 break;
4732 case 0xce: /* into */
5c5df76b
TY		 4733 if (ctxt->eflags & EFLG_OF)
4734 rc = emulate_int(ctxt, 4);
6e154e56 4735 break;
1a52e051 4736 case 0xe9: /* jmp rel */
db5b0762 4737 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4738 jmp_rel(ctxt, ctxt->src.val);
4739 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4740 break;
111de5d6 4741 case 0xf4: /* hlt */
6c3287f7 4742 ctxt->ops->halt(ctxt);
19fdfa0d 4743 break;
111de5d6
AK		 4744 case 0xf5: /* cmc */
4745 /* complement carry flag from eflags reg */
4746 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4747 break;
4748 case 0xf8: /* clc */
4749 ctxt->eflags &= ~EFLG_CF;
111de5d6 4750 break;
8744aa9a
MG		 4751 case 0xf9: /* stc */
4752 ctxt->eflags |= EFLG_CF;
4753 break;
fb4616f4
MG		 4754 case 0xfc: /* cld */
4755 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4756 break;
4757 case 0xfd: /* std */
4758 ctxt->eflags |= EFLG_DF;
fb4616f4 4759 break;
91269b8f
AK		 4760 default:
4761 goto cannot_emulate;
6aa8b732 4762 }
018a98db 4763
7d9ddaed
AK		 4764 if (rc != X86EMUL_CONTINUE)
4765 goto done;
4766
018a98db 4767writeback:
adddcecf 4768 rc = writeback(ctxt);
1b30eaa8 4769 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4770 goto done;
4771
5cd21917
GN		 4772 /*
4773 * restore dst type in case the decoding will be reused
4774 * (happens for string instruction )
4775 */
9dac77fa 4776 ctxt->dst.type = saved_dst_type;
5cd21917 4777
9dac77fa 4778 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4779 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4780
9dac77fa 4781 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4782 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4783
9dac77fa 4784 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4785 unsigned int count;
9dac77fa 4786 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4787 if ((ctxt->d & SrcMask) == SrcSI)
4788 count = ctxt->src.count;
4789 else
4790 count = ctxt->dst.count;
4791 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4792 -count);
3e2f65d5 4793
d2ddd1c4
GN		 4794 if (!string_insn_completed(ctxt)) {
4795 /*
4796 * Re-enter guest when pio read ahead buffer is empty
4797 * or, if it is not used, after each 1024 iteration.
4798 */
dd856efa 4799 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4800 (r->end == 0 || r->end != r->pos)) {
4801 /*
4802 * Reset read cache. Usually happens before
4803 * decode, but since instruction is restarted
4804 * we have to do it here.
4805 */
9dac77fa 4806 ctxt->mem_read.end = 0;
dd856efa 4807 writeback_registers(ctxt);
d2ddd1c4
GN		 4808 return EMULATION_RESTART;
4809 }
4810 goto done; /* skip rip writeback */
0fa6ccbd 4811 }
5cd21917 4812 }
d2ddd1c4 4813
9dac77fa 4814 ctxt->eip = ctxt->_eip;
018a98db
AK		 4815
4816done:
da9cb575
AK		 4817 if (rc == X86EMUL_PROPAGATE_FAULT)
4818 ctxt->have_exception = true;
775fde86
JR		 4819 if (rc == X86EMUL_INTERCEPTED)
4820 return EMULATION_INTERCEPTED;
4821
dd856efa
AK		 4822 if (rc == X86EMUL_CONTINUE)
4823 writeback_registers(ctxt);
4824
d2ddd1c4 4825 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4826
4827twobyte_insn:
9dac77fa 4828 switch (ctxt->b) {
018a98db 4829 case 0x09: /* wbinvd */
cfb22375 4830 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4831 break;
4832 case 0x08: /* invd */
018a98db
AK		 4833 case 0x0d: /* GrpP (prefetch) */
4834 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4835 break;
4836 case 0x20: /* mov cr, reg */
9dac77fa 4837 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4838 break;
6aa8b732 4839 case 0x21: /* mov from dr to reg */
9dac77fa 4840 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4841 break;
6aa8b732 4842 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4843 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4844 if (!test_cc(ctxt->b, ctxt->eflags))
4845 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4846 break;
b2833e3c 4847 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4848 if (test_cc(ctxt->b, ctxt->eflags))
4849 jmp_rel(ctxt, ctxt->src.val);
018a98db 4850 break;
ee45b58e 4851 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4852 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4853 break;
2a7c5b8b
GC		 4854 case 0xae: /* clflush */
4855 break;
6aa8b732 4856 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4857 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4858 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4859 : (u16) ctxt->src.val;
6aa8b732 4860 break;
6aa8b732 4861 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4862 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4863 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4864 (s16) ctxt->src.val;
6aa8b732 4865 break;
92f738a5 4866 case 0xc0 ... 0xc1: /* xadd */
158de57f 4867 fastop(ctxt, em_add);
92f738a5 4868 /* Write back the register source. */
9dac77fa
AK		 4869 ctxt->src.val = ctxt->dst.orig_val;
4870 write_register_operand(&ctxt->src);
92f738a5 4871 break;
a012e65a 4872 case 0xc3: /* movnti */
9dac77fa
AK		 4873 ctxt->dst.bytes = ctxt->op_bytes;
4874 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4875 (u64) ctxt->src.val;
a012e65a 4876 break;
91269b8f
AK		 4877 default:
4878 goto cannot_emulate;
6aa8b732 4879 }
7d9ddaed
AK		 4880
4881 if (rc != X86EMUL_CONTINUE)
4882 goto done;
4883
6aa8b732
AK		 4884 goto writeback;
4885
4886cannot_emulate:
a0c0ab2f 4887 return EMULATION_FAILED;
6aa8b732 4888}
dd856efa
AK		 4889
4890void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4891{
4892 invalidate_registers(ctxt);
4893}
4894
4895void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4896{
4897 writeback_registers(ctxt);
4898}
Linux kernel - Deliverables
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