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KVM: x86: Breakpoints do not consider CS.base
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 169#define NearBranch ((u64)1 << 52) /* Near branches */
6aa8b732 170
820207c8 171#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 172
d0e53325
AK		 173#define X2(x...) x, x
174#define X3(x...) X2(x), x
175#define X4(x...) X2(x), X2(x)
176#define X5(x...) X4(x), x
177#define X6(x...) X4(x), X2(x)
178#define X7(x...) X4(x), X3(x)
179#define X8(x...) X4(x), X4(x)
180#define X16(x...) X8(x), X8(x)
83babbca 181
e28bbd44
AK		 182#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
183#define FASTOP_SIZE 8
184
185/*
186 * fastop functions have a special calling convention:
187 *
017da7b6
AK		 188 * dst: rax (in/out)
189 * src: rdx (in/out)
e28bbd44
AK		 190 * src2: rcx (in)
191 * flags: rflags (in/out)
b8c0b6ae 192 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 193 *
194 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
195 * different operand sizes can be reached by calculation, rather than a jump
196 * table (which would be bigger than the code).
197 *
198 * fastop functions are declared as taking a never-defined fastop parameter,
199 * so they can't be called from C directly.
200 */
201
202struct fastop;
203
d65b1dee 204struct opcode {
b1ea50b2
AK		 205 u64 flags : 56;
206 u64 intercept : 8;
120df890 207 union {
ef65c889 208 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 209 const struct opcode *group;
210 const struct group_dual *gdual;
211 const struct gprefix *gprefix;
045a282c 212 const struct escape *esc;
e28bbd44 213 void (*fastop)(struct fastop *fake);
120df890 214 } u;
d09beabd 215 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 216};
217
218struct group_dual {
219 struct opcode mod012[8];
220 struct opcode mod3[8];
d65b1dee
AK		 221};
222
0d7cdee8
AK		 223struct gprefix {
224 struct opcode pfx_no;
225 struct opcode pfx_66;
226 struct opcode pfx_f2;
227 struct opcode pfx_f3;
228};
229
045a282c
GN		 230struct escape {
231 struct opcode op[8];
232 struct opcode high[64];
233};
234
6aa8b732 235/* EFLAGS bit definitions. */
d4c6a154
GN		 236#define EFLG_ID (1<<21)
237#define EFLG_VIP (1<<20)
238#define EFLG_VIF (1<<19)
239#define EFLG_AC (1<<18)
b1d86143
AP		 240#define EFLG_VM (1<<17)
241#define EFLG_RF (1<<16)
d4c6a154
GN		 242#define EFLG_IOPL (3<<12)
243#define EFLG_NT (1<<14)
6aa8b732
AK		 244#define EFLG_OF (1<<11)
245#define EFLG_DF (1<<10)
b1d86143 246#define EFLG_IF (1<<9)
d4c6a154 247#define EFLG_TF (1<<8)
6aa8b732
AK		 248#define EFLG_SF (1<<7)
249#define EFLG_ZF (1<<6)
250#define EFLG_AF (1<<4)
251#define EFLG_PF (1<<2)
252#define EFLG_CF (1<<0)
253
62bd430e
MG		 254#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
255#define EFLG_RESERVED_ONE_MASK 2
256
dd856efa
AK		 257static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
258{
259 if (!(ctxt->regs_valid & (1 << nr))) {
260 ctxt->regs_valid |= 1 << nr;
261 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
262 }
263 return ctxt->_regs[nr];
264}
265
266static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 ctxt->regs_valid |= 1 << nr;
269 ctxt->regs_dirty |= 1 << nr;
270 return &ctxt->_regs[nr];
271}
272
273static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
274{
275 reg_read(ctxt, nr);
276 return reg_write(ctxt, nr);
277}
278
279static void writeback_registers(struct x86_emulate_ctxt *ctxt)
280{
281 unsigned reg;
282
283 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
284 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
285}
286
287static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
288{
289 ctxt->regs_dirty = 0;
290 ctxt->regs_valid = 0;
291}
292
6aa8b732
AK		 293/*
294 * These EFLAGS bits are restored from saved value during emulation, and
295 * any changes are written back to the saved value after emulation.
296 */
297#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
298
dda96d8f
AK		 299#ifdef CONFIG_X86_64
300#define ON64(x) x
301#else
302#define ON64(x)
303#endif
304
4d758349
AK		 305static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
306
b7d491e7
AK		 307#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
308#define FOP_RET "ret \n\t"
309
310#define FOP_START(op) \
311 extern void em_##op(struct fastop *fake); \
312 asm(".pushsection .text, \"ax\" \n\t" \
313 ".global em_" #op " \n\t" \
314 FOP_ALIGN \
315 "em_" #op ": \n\t"
316
317#define FOP_END \
318 ".popsection")
319
0bdea068
AK		 320#define FOPNOP() FOP_ALIGN FOP_RET
321
b7d491e7 322#define FOP1E(op, dst) \
b8c0b6ae
AK		 323 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
324
325#define FOP1EEX(op, dst) \
326 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 327
328#define FASTOP1(op) \
329 FOP_START(op) \
330 FOP1E(op##b, al) \
331 FOP1E(op##w, ax) \
332 FOP1E(op##l, eax) \
333 ON64(FOP1E(op##q, rax)) \
334 FOP_END
335
b9fa409b
AK		 336/* 1-operand, using src2 (for MUL/DIV r/m) */
337#define FASTOP1SRC2(op, name) \
338 FOP_START(name) \
339 FOP1E(op, cl) \
340 FOP1E(op, cx) \
341 FOP1E(op, ecx) \
342 ON64(FOP1E(op, rcx)) \
343 FOP_END
344
b8c0b6ae
AK		 345/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
346#define FASTOP1SRC2EX(op, name) \
347 FOP_START(name) \
348 FOP1EEX(op, cl) \
349 FOP1EEX(op, cx) \
350 FOP1EEX(op, ecx) \
351 ON64(FOP1EEX(op, rcx)) \
352 FOP_END
353
f7857f35
AK		 354#define FOP2E(op, dst, src) \
355 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
356
357#define FASTOP2(op) \
358 FOP_START(op) \
017da7b6
AK		 359 FOP2E(op##b, al, dl) \
360 FOP2E(op##w, ax, dx) \
361 FOP2E(op##l, eax, edx) \
362 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 363 FOP_END
364
11c363ba
AK		 365/* 2 operand, word only */
366#define FASTOP2W(op) \
367 FOP_START(op) \
368 FOPNOP() \
017da7b6
AK		 369 FOP2E(op##w, ax, dx) \
370 FOP2E(op##l, eax, edx) \
371 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 372 FOP_END
373
007a3b54
AK		 374/* 2 operand, src is CL */
375#define FASTOP2CL(op) \
376 FOP_START(op) \
377 FOP2E(op##b, al, cl) \
378 FOP2E(op##w, ax, cl) \
379 FOP2E(op##l, eax, cl) \
380 ON64(FOP2E(op##q, rax, cl)) \
381 FOP_END
382
0bdea068
AK		 383#define FOP3E(op, dst, src, src2) \
384 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
385
386/* 3-operand, word-only, src2=cl */
387#define FASTOP3WCL(op) \
388 FOP_START(op) \
389 FOPNOP() \
017da7b6
AK		 390 FOP3E(op##w, ax, dx, cl) \
391 FOP3E(op##l, eax, edx, cl) \
392 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 393 FOP_END
394
9ae9feba
AK		 395/* Special case for SETcc - 1 instruction per cc */
396#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
397
b8c0b6ae
AK		 398asm(".global kvm_fastop_exception \n"
399 "kvm_fastop_exception: xor %esi, %esi; ret");
400
9ae9feba
AK		 401FOP_START(setcc)
402FOP_SETCC(seto)
403FOP_SETCC(setno)
404FOP_SETCC(setc)
405FOP_SETCC(setnc)
406FOP_SETCC(setz)
407FOP_SETCC(setnz)
408FOP_SETCC(setbe)
409FOP_SETCC(setnbe)
410FOP_SETCC(sets)
411FOP_SETCC(setns)
412FOP_SETCC(setp)
413FOP_SETCC(setnp)
414FOP_SETCC(setl)
415FOP_SETCC(setnl)
416FOP_SETCC(setle)
417FOP_SETCC(setnle)
418FOP_END;
419
326f578f
PB		 420FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
421FOP_END;
422
8a76d7f2
JR		 423static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
424 enum x86_intercept intercept,
425 enum x86_intercept_stage stage)
426{
427 struct x86_instruction_info info = {
428 .intercept = intercept,
9dac77fa
AK		 429 .rep_prefix = ctxt->rep_prefix,
430 .modrm_mod = ctxt->modrm_mod,
431 .modrm_reg = ctxt->modrm_reg,
432 .modrm_rm = ctxt->modrm_rm,
433 .src_val = ctxt->src.val64,
6cbc5f5a 434 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 435 .src_bytes = ctxt->src.bytes,
436 .dst_bytes = ctxt->dst.bytes,
437 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 438 .next_rip = ctxt->eip,
439 };
440
2953538e 441 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 442}
443
f47cfa31
AK		 444static void assign_masked(ulong *dest, ulong src, ulong mask)
445{
446 *dest = (*dest & ~mask) | (src & mask);
447}
448
9dac77fa 449static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 450{
9dac77fa 451 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 452}
453
f47cfa31
AK		 454static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
455{
456 u16 sel;
457 struct desc_struct ss;
458
459 if (ctxt->mode == X86EMUL_MODE_PROT64)
460 return ~0UL;
461 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
462 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
463}
464
612e89f0
AK		 465static int stack_size(struct x86_emulate_ctxt *ctxt)
466{
467 return (__fls(stack_mask(ctxt)) + 1) >> 3;
468}
469
6aa8b732 470/* Access/update address held in a register, based on addressing mode. */
e4706772 471static inline unsigned long
9dac77fa 472address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 473{
9dac77fa 474 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 475 return reg;
476 else
9dac77fa 477 return reg & ad_mask(ctxt);
e4706772
HH		 478}
479
480static inline unsigned long
9dac77fa 481register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 482{
9dac77fa 483 return address_mask(ctxt, reg);
e4706772
HH		 484}
485
5ad105e5
AK		 486static void masked_increment(ulong *reg, ulong mask, int inc)
487{
488 assign_masked(reg, *reg + inc, mask);
489}
490
7a957275 491static inline void
9dac77fa 492register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 493{
5ad105e5
AK		 494 ulong mask;
495
9dac77fa 496 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 497 mask = ~0UL;
7a957275 498 else
5ad105e5
AK		 499 mask = ad_mask(ctxt);
500 masked_increment(reg, mask, inc);
501}
502
503static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
504{
dd856efa 505 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 506}
6aa8b732 507
56697687
AK		 508static u32 desc_limit_scaled(struct desc_struct *desc)
509{
510 u32 limit = get_desc_limit(desc);
511
512 return desc->g ? (limit << 12) | 0xfff : limit;
513}
514
7b105ca2 515static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 516{
517 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
518 return 0;
519
7b105ca2 520 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 521}
522
35d3d4a1
AK		 523static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
524 u32 error, bool valid)
54b8486f 525{
e0ad0b47 526 WARN_ON(vec > 0x1f);
da9cb575
AK		 527 ctxt->exception.vector = vec;
528 ctxt->exception.error_code = error;
529 ctxt->exception.error_code_valid = valid;
35d3d4a1 530 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 531}
532
3b88e41a
JR		 533static int emulate_db(struct x86_emulate_ctxt *ctxt)
534{
535 return emulate_exception(ctxt, DB_VECTOR, 0, false);
536}
537
35d3d4a1 538static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 539{
35d3d4a1 540 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 541}
542
618ff15d
AK		 543static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
544{
545 return emulate_exception(ctxt, SS_VECTOR, err, true);
546}
547
35d3d4a1 548static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 549{
35d3d4a1 550 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 551}
552
35d3d4a1 553static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 554{
35d3d4a1 555 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 556}
557
34d1f490
AK		 558static int emulate_de(struct x86_emulate_ctxt *ctxt)
559{
35d3d4a1 560 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 561}
562
1253791d
AK		 563static int emulate_nm(struct x86_emulate_ctxt *ctxt)
564{
565 return emulate_exception(ctxt, NM_VECTOR, 0, false);
566}
567
234f3ce4
NA		 568static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
569 int cs_l)
05c83ec9
NA		 570{
571 switch (ctxt->op_bytes) {
572 case 2:
573 ctxt->_eip = (u16)dst;
574 break;
575 case 4:
576 ctxt->_eip = (u32)dst;
577 break;
cd9b8e2c 578#ifdef CONFIG_X86_64
05c83ec9 579 case 8:
234f3ce4 580 if ((cs_l && is_noncanonical_address(dst)) ||
cd9b8e2c 581 (!cs_l && (dst >> 32) != 0))
234f3ce4 582 return emulate_gp(ctxt, 0);
05c83ec9
NA		 583 ctxt->_eip = dst;
584 break;
cd9b8e2c 585#endif
05c83ec9
NA		 586 default:
587 WARN(1, "unsupported eip assignment size\n");
588 }
234f3ce4
NA		 589 return X86EMUL_CONTINUE;
590}
591
592static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
593{
594 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
05c83ec9
NA		 595}
596
234f3ce4 597static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
05c83ec9 598{
234f3ce4 599 return assign_eip_near(ctxt, ctxt->_eip + rel);
05c83ec9
NA		 600}
601
1aa36616
AK		 602static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
603{
604 u16 selector;
605 struct desc_struct desc;
606
607 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
608 return selector;
609}
610
611static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
612 unsigned seg)
613{
614 u16 dummy;
615 u32 base3;
616 struct desc_struct desc;
617
618 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
619 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
620}
621
1c11b376
AK		 622/*
623 * x86 defines three classes of vector instructions: explicitly
624 * aligned, explicitly unaligned, and the rest, which change behaviour
625 * depending on whether they're AVX encoded or not.
626 *
627 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
628 * subject to the same check.
629 */
630static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
631{
632 if (likely(size < 16))
633 return false;
634
635 if (ctxt->d & Aligned)
636 return true;
637 else if (ctxt->d & Unaligned)
638 return false;
639 else if (ctxt->d & Avx)
640 return false;
641 else
642 return true;
643}
644
d09155d2
PB		 645static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
646 struct segmented_address addr,
647 unsigned *max_size, unsigned size,
648 bool write, bool fetch,
649 ulong *linear)
52fd8b44 650{
618ff15d
AK		 651 struct desc_struct desc;
652 bool usable;
52fd8b44 653 ulong la;
618ff15d 654 u32 lim;
1aa36616 655 u16 sel;
3a78a4f4 656 unsigned cpl;
52fd8b44 657
518547b3
NA		 658 la = seg_base(ctxt, addr.seg) +
659 (fetch || ctxt->ad_bytes == 8 ? addr.ea : (u32)addr.ea);
fd56e154 660 *max_size = 0;
618ff15d 661 switch (ctxt->mode) {
618ff15d 662 case X86EMUL_MODE_PROT64:
4be4de7e 663 if (is_noncanonical_address(la))
618ff15d 664 return emulate_gp(ctxt, 0);
fd56e154
PB		 665
666 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
667 if (size > *max_size)
668 goto bad;
618ff15d
AK		 669 break;
670 default:
1aa36616
AK		 671 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
672 addr.seg);
618ff15d
AK		 673 if (!usable)
674 goto bad;
58b7825b
GN		 675 /* code segment in protected mode or read-only data segment */
676 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
677 || !(desc.type & 2)) && write)
618ff15d
AK		 678 goto bad;
679 /* unreadable code segment */
3d9b938e 680 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 681 goto bad;
682 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 683 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
684 (ctxt->d & NoBigReal)) {
685 /* la is between zero and 0xffff */
fd56e154 686 if (la > 0xffff)
10e38fc7 687 goto bad;
fd56e154 688 *max_size = 0x10000 - la;
10e38fc7 689 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d 690 /* expand-up segment */
fd56e154 691 if (addr.ea > lim)
618ff15d 692 goto bad;
fd56e154 693 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 694 } else {
fc058680 695 /* expand-down segment */
fd56e154 696 if (addr.ea <= lim)
618ff15d
AK		 697 goto bad;
698 lim = desc.d ? 0xffffffff : 0xffff;
fd56e154 699 if (addr.ea > lim)
618ff15d 700 goto bad;
fd56e154 701 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 702 }
fd56e154
PB		 703 if (size > *max_size)
704 goto bad;
717746e3 705 cpl = ctxt->ops->cpl(ctxt);
c49c759f
NA		 706 if (!fetch) {
707 /* data segment or readable code segment */
618ff15d
AK		 708 if (cpl > desc.dpl)
709 goto bad;
710 } else if ((desc.type & 8) && !(desc.type & 4)) {
711 /* nonconforming code segment */
712 if (cpl != desc.dpl)
713 goto bad;
714 } else if ((desc.type & 8) && (desc.type & 4)) {
715 /* conforming code segment */
716 if (cpl < desc.dpl)
717 goto bad;
718 }
719 break;
720 }
518547b3 721 if (ctxt->mode != X86EMUL_MODE_PROT64)
52fd8b44 722 la &= (u32)-1;
1c11b376
AK		 723 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
724 return emulate_gp(ctxt, 0);
52fd8b44
AK		 725 *linear = la;
726 return X86EMUL_CONTINUE;
618ff15d
AK		 727bad:
728 if (addr.seg == VCPU_SREG_SS)
3606189f 729 return emulate_ss(ctxt, 0);
618ff15d 730 else
3606189f 731 return emulate_gp(ctxt, 0);
52fd8b44
AK		 732}
733
3d9b938e
NE		 734static int linearize(struct x86_emulate_ctxt *ctxt,
735 struct segmented_address addr,
736 unsigned size, bool write,
737 ulong *linear)
738{
fd56e154
PB		 739 unsigned max_size;
740 return __linearize(ctxt, addr, &max_size, size, write, false, linear);
3d9b938e
NE		 741}
742
743
3ca3ac4d
AK		 744static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
745 struct segmented_address addr,
746 void *data,
747 unsigned size)
748{
9fa088f4
AK		 749 int rc;
750 ulong linear;
751
83b8795a 752 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 753 if (rc != X86EMUL_CONTINUE)
754 return rc;
0f65dd70 755 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 756}
757
807941b1 758/*
285ca9e9 759 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 760 * boundary if they are not in fetch_cache yet.
761 */
9506d57d 762static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 763{
62266869 764 int rc;
fd56e154 765 unsigned size, max_size;
285ca9e9 766 unsigned long linear;
17052f16 767 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 768 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 769 .ea = ctxt->eip + cur_size };
770
fd56e154
PB		 771 /*
772 * We do not know exactly how many bytes will be needed, and
773 * __linearize is expensive, so fetch as much as possible. We
774 * just have to avoid going beyond the 15 byte limit, the end
775 * of the segment, or the end of the page.
776 *
777 * __linearize is called with size 0 so that it does not do any
778 * boundary check itself. Instead, we use max_size to check
779 * against op_size.
780 */
781 rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
719d5a9b
PB		 782 if (unlikely(rc != X86EMUL_CONTINUE))
783 return rc;
784
fd56e154 785 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 786 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 787
788 /*
789 * One instruction can only straddle two pages,
790 * and one has been loaded at the beginning of
791 * x86_decode_insn. So, if not enough bytes
792 * still, we must have hit the 15-byte boundary.
793 */
794 if (unlikely(size < op_size))
fd56e154
PB		 795 return emulate_gp(ctxt, 0);
796
17052f16 797 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 798 size, &ctxt->exception);
799 if (unlikely(rc != X86EMUL_CONTINUE))
800 return rc;
17052f16 801 ctxt->fetch.end += size;
3e2815e9 802 return X86EMUL_CONTINUE;
62266869
AK		 803}
804
9506d57d
PB		 805static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
806 unsigned size)
62266869 807{
08da44ae
NA		 808 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
809
810 if (unlikely(done_size < size))
811 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 812 else
813 return X86EMUL_CONTINUE;
62266869
AK		 814}
815
67cbc90d 816/* Fetch next part of the instruction being emulated. */
e85a1085 817#define insn_fetch(_type, _ctxt) \
9506d57d 818({ _type _x; \
9506d57d
PB		 819 \
820 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 821 if (rc != X86EMUL_CONTINUE) \
822 goto done; \
9506d57d 823 ctxt->_eip += sizeof(_type); \
17052f16
PB		 824 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
825 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 826 _x; \
67cbc90d
TY		 827})
828
807941b1 829#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 830({ \
9506d57d 831 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 832 if (rc != X86EMUL_CONTINUE) \
833 goto done; \
9506d57d 834 ctxt->_eip += (_size); \
17052f16
PB		 835 memcpy(_arr, ctxt->fetch.ptr, _size); \
836 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 837})
838
1e3c5cb0
RR		 839/*
840 * Given the 'reg' portion of a ModRM byte, and a register block, return a
841 * pointer into the block that addresses the relevant register.
842 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
843 */
dd856efa 844static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 845 int byteop)
6aa8b732
AK		 846{
847 void *p;
aa9ac1a6 848 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 849
6aa8b732 850 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 851 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
852 else
853 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 854 return p;
855}
856
857static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 858 struct segmented_address addr,
6aa8b732
AK		 859 u16 *size, unsigned long *address, int op_bytes)
860{
861 int rc;
862
863 if (op_bytes == 2)
864 op_bytes = 3;
865 *address = 0;
3ca3ac4d 866 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 867 if (rc != X86EMUL_CONTINUE)
6aa8b732 868 return rc;
30b31ab6 869 addr.ea += 2;
3ca3ac4d 870 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 871 return rc;
872}
873
34b77652
AK		 874FASTOP2(add);
875FASTOP2(or);
876FASTOP2(adc);
877FASTOP2(sbb);
878FASTOP2(and);
879FASTOP2(sub);
880FASTOP2(xor);
881FASTOP2(cmp);
882FASTOP2(test);
883
b9fa409b
AK		 884FASTOP1SRC2(mul, mul_ex);
885FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 886FASTOP1SRC2EX(div, div_ex);
887FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 888
34b77652
AK		 889FASTOP3WCL(shld);
890FASTOP3WCL(shrd);
891
892FASTOP2W(imul);
893
894FASTOP1(not);
895FASTOP1(neg);
896FASTOP1(inc);
897FASTOP1(dec);
898
899FASTOP2CL(rol);
900FASTOP2CL(ror);
901FASTOP2CL(rcl);
902FASTOP2CL(rcr);
903FASTOP2CL(shl);
904FASTOP2CL(shr);
905FASTOP2CL(sar);
906
907FASTOP2W(bsf);
908FASTOP2W(bsr);
909FASTOP2W(bt);
910FASTOP2W(bts);
911FASTOP2W(btr);
912FASTOP2W(btc);
913
e47a5f5f
AK		 914FASTOP2(xadd);
915
9ae9feba 916static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 917{
9ae9feba
AK		 918 u8 rc;
919 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 920
9ae9feba 921 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 922 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 923 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
924 return rc;
bbe9abbd
NK		 925}
926
91ff3cb4
AK		 927static void fetch_register_operand(struct operand *op)
928{
929 switch (op->bytes) {
930 case 1:
931 op->val = *(u8 *)op->addr.reg;
932 break;
933 case 2:
934 op->val = *(u16 *)op->addr.reg;
935 break;
936 case 4:
937 op->val = *(u32 *)op->addr.reg;
938 break;
939 case 8:
940 op->val = *(u64 *)op->addr.reg;
941 break;
942 }
943}
944
1253791d
AK		 945static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
946{
947 ctxt->ops->get_fpu(ctxt);
948 switch (reg) {
89a87c67
MK		 949 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
950 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
951 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
952 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
953 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
954 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
955 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
956 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 957#ifdef CONFIG_X86_64
89a87c67
MK		 958 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
959 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
960 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
961 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
962 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
963 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
964 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
965 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 966#endif
967 default: BUG();
968 }
969 ctxt->ops->put_fpu(ctxt);
970}
971
972static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
973 int reg)
974{
975 ctxt->ops->get_fpu(ctxt);
976 switch (reg) {
89a87c67
MK		 977 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
978 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
979 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
980 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
981 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
982 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
983 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
984 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 985#ifdef CONFIG_X86_64
89a87c67
MK		 986 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
987 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
988 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
989 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
990 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
991 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
992 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
993 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 994#endif
995 default: BUG();
996 }
997 ctxt->ops->put_fpu(ctxt);
998}
999
cbe2c9d3
AK		 1000static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1001{
1002 ctxt->ops->get_fpu(ctxt);
1003 switch (reg) {
1004 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1005 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1006 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1007 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1008 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1009 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1010 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1011 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1012 default: BUG();
1013 }
1014 ctxt->ops->put_fpu(ctxt);
1015}
1016
1017static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1018{
1019 ctxt->ops->get_fpu(ctxt);
1020 switch (reg) {
1021 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1022 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1023 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1024 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1025 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1026 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1027 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1028 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1029 default: BUG();
1030 }
1031 ctxt->ops->put_fpu(ctxt);
1032}
1033
045a282c
GN		 1034static int em_fninit(struct x86_emulate_ctxt *ctxt)
1035{
1036 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1037 return emulate_nm(ctxt);
1038
1039 ctxt->ops->get_fpu(ctxt);
1040 asm volatile("fninit");
1041 ctxt->ops->put_fpu(ctxt);
1042 return X86EMUL_CONTINUE;
1043}
1044
1045static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1046{
1047 u16 fcw;
1048
1049 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1050 return emulate_nm(ctxt);
1051
1052 ctxt->ops->get_fpu(ctxt);
1053 asm volatile("fnstcw %0": "+m"(fcw));
1054 ctxt->ops->put_fpu(ctxt);
1055
1056 /* force 2 byte destination */
1057 ctxt->dst.bytes = 2;
1058 ctxt->dst.val = fcw;
1059
1060 return X86EMUL_CONTINUE;
1061}
1062
1063static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1064{
1065 u16 fsw;
1066
1067 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1068 return emulate_nm(ctxt);
1069
1070 ctxt->ops->get_fpu(ctxt);
1071 asm volatile("fnstsw %0": "+m"(fsw));
1072 ctxt->ops->put_fpu(ctxt);
1073
1074 /* force 2 byte destination */
1075 ctxt->dst.bytes = 2;
1076 ctxt->dst.val = fsw;
1077
1078 return X86EMUL_CONTINUE;
1079}
1080
1253791d 1081static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1082 struct operand *op)
3c118e24 1083{
9dac77fa 1084 unsigned reg = ctxt->modrm_reg;
33615aa9 1085
9dac77fa
AK		 1086 if (!(ctxt->d & ModRM))
1087 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1088
9dac77fa 1089 if (ctxt->d & Sse) {
1253791d
AK		 1090 op->type = OP_XMM;
1091 op->bytes = 16;
1092 op->addr.xmm = reg;
1093 read_sse_reg(ctxt, &op->vec_val, reg);
1094 return;
1095 }
cbe2c9d3
AK		 1096 if (ctxt->d & Mmx) {
1097 reg &= 7;
1098 op->type = OP_MM;
1099 op->bytes = 8;
1100 op->addr.mm = reg;
1101 return;
1102 }
1253791d 1103
3c118e24 1104 op->type = OP_REG;
6d4d85ec
GN		 1105 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1106 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1107
91ff3cb4 1108 fetch_register_operand(op);
3c118e24
AK		 1109 op->orig_val = op->val;
1110}
1111
a6e3407b
AK		 1112static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1113{
1114 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1115 ctxt->modrm_seg = VCPU_SREG_SS;
1116}
1117
1c73ef66 1118static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1119 struct operand *op)
1c73ef66 1120{
1c73ef66 1121 u8 sib;
02357bdc 1122 int index_reg, base_reg, scale;
3e2815e9 1123 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1124 ulong modrm_ea = 0;
1c73ef66 1125
02357bdc
BD		 1126 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1127 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1128 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1129
02357bdc 1130 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1131 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1132 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1133 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1134
9b88ae99 1135 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1136 op->type = OP_REG;
9dac77fa 1137 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1138 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1139 ctxt->d & ByteOp);
9dac77fa 1140 if (ctxt->d & Sse) {
1253791d
AK		 1141 op->type = OP_XMM;
1142 op->bytes = 16;
9dac77fa
AK		 1143 op->addr.xmm = ctxt->modrm_rm;
1144 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1145 return rc;
1146 }
cbe2c9d3
AK		 1147 if (ctxt->d & Mmx) {
1148 op->type = OP_MM;
1149 op->bytes = 8;
bdc90722 1150 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1151 return rc;
1152 }
2dbd0dd7 1153 fetch_register_operand(op);
1c73ef66
AK		 1154 return rc;
1155 }
1156
2dbd0dd7
AK		 1157 op->type = OP_MEM;
1158
9dac77fa 1159 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1160 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1161 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1162 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1163 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1164
1165 /* 16-bit ModR/M decode. */
9dac77fa 1166 switch (ctxt->modrm_mod) {
1c73ef66 1167 case 0:
9dac77fa 1168 if (ctxt->modrm_rm == 6)
e85a1085 1169 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1170 break;
1171 case 1:
e85a1085 1172 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1173 break;
1174 case 2:
e85a1085 1175 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1176 break;
1177 }
9dac77fa 1178 switch (ctxt->modrm_rm) {
1c73ef66 1179 case 0:
2dbd0dd7 1180 modrm_ea += bx + si;
1c73ef66
AK		 1181 break;
1182 case 1:
2dbd0dd7 1183 modrm_ea += bx + di;
1c73ef66
AK		 1184 break;
1185 case 2:
2dbd0dd7 1186 modrm_ea += bp + si;
1c73ef66
AK		 1187 break;
1188 case 3:
2dbd0dd7 1189 modrm_ea += bp + di;
1c73ef66
AK		 1190 break;
1191 case 4:
2dbd0dd7 1192 modrm_ea += si;
1c73ef66
AK		 1193 break;
1194 case 5:
2dbd0dd7 1195 modrm_ea += di;
1c73ef66
AK		 1196 break;
1197 case 6:
9dac77fa 1198 if (ctxt->modrm_mod != 0)
2dbd0dd7 1199 modrm_ea += bp;
1c73ef66
AK		 1200 break;
1201 case 7:
2dbd0dd7 1202 modrm_ea += bx;
1c73ef66
AK		 1203 break;
1204 }
9dac77fa
AK		 1205 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1206 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1207 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1208 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1209 } else {
1210 /* 32/64-bit ModR/M decode. */
9dac77fa 1211 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1212 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1213 index_reg |= (sib >> 3) & 7;
1214 base_reg |= sib & 7;
1215 scale = sib >> 6;
1216
9dac77fa 1217 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1218 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1219 else {
dd856efa 1220 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1221 adjust_modrm_seg(ctxt, base_reg);
1222 }
dc71d0f1 1223 if (index_reg != 4)
dd856efa 1224 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1225 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1226 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1227 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1228 ctxt->rip_relative = 1;
a6e3407b
AK		 1229 } else {
1230 base_reg = ctxt->modrm_rm;
dd856efa 1231 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1232 adjust_modrm_seg(ctxt, base_reg);
1233 }
9dac77fa 1234 switch (ctxt->modrm_mod) {
1c73ef66 1235 case 1:
e85a1085 1236 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1237 break;
1238 case 2:
e85a1085 1239 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1240 break;
1241 }
1242 }
90de84f5 1243 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1244 if (ctxt->ad_bytes != 8)
1245 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1246
1c73ef66
AK		 1247done:
1248 return rc;
1249}
1250
1251static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1252 struct operand *op)
1c73ef66 1253{
3e2815e9 1254 int rc = X86EMUL_CONTINUE;
1c73ef66 1255
2dbd0dd7 1256 op->type = OP_MEM;
9dac77fa 1257 switch (ctxt->ad_bytes) {
1c73ef66 1258 case 2:
e85a1085 1259 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1260 break;
1261 case 4:
e85a1085 1262 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1263 break;
1264 case 8:
e85a1085 1265 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1266 break;
1267 }
1268done:
1269 return rc;
1270}
1271
9dac77fa 1272static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1273{
7129eeca 1274 long sv = 0, mask;
35c843c4 1275
9dac77fa 1276 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1277 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1278
9dac77fa
AK		 1279 if (ctxt->src.bytes == 2)
1280 sv = (s16)ctxt->src.val & (s16)mask;
1281 else if (ctxt->src.bytes == 4)
1282 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1283 else
1284 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1285
9dac77fa 1286 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1287 }
ba7ff2b7
WY		 1288
1289 /* only subword offset */
9dac77fa 1290 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1291}
1292
dde7e6d1 1293static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1294 unsigned long addr, void *dest, unsigned size)
6aa8b732 1295{
dde7e6d1 1296 int rc;
9dac77fa 1297 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1298
f23b070e
XG		 1299 if (mc->pos < mc->end)
1300 goto read_cached;
6aa8b732 1301
f23b070e
XG		 1302 WARN_ON((mc->end + size) >= sizeof(mc->data));
1303
1304 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1305 &ctxt->exception);
1306 if (rc != X86EMUL_CONTINUE)
1307 return rc;
1308
1309 mc->end += size;
1310
1311read_cached:
1312 memcpy(dest, mc->data + mc->pos, size);
1313 mc->pos += size;
dde7e6d1
AK		 1314 return X86EMUL_CONTINUE;
1315}
6aa8b732 1316
3ca3ac4d
AK		 1317static int segmented_read(struct x86_emulate_ctxt *ctxt,
1318 struct segmented_address addr,
1319 void *data,
1320 unsigned size)
1321{
9fa088f4
AK		 1322 int rc;
1323 ulong linear;
1324
83b8795a 1325 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1326 if (rc != X86EMUL_CONTINUE)
1327 return rc;
7b105ca2 1328 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1329}
1330
1331static int segmented_write(struct x86_emulate_ctxt *ctxt,
1332 struct segmented_address addr,
1333 const void *data,
1334 unsigned size)
1335{
9fa088f4
AK		 1336 int rc;
1337 ulong linear;
1338
83b8795a 1339 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
0f65dd70
AK		 1342 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1343 &ctxt->exception);
3ca3ac4d
AK		 1344}
1345
1346static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1347 struct segmented_address addr,
1348 const void *orig_data, const void *data,
1349 unsigned size)
1350{
9fa088f4
AK		 1351 int rc;
1352 ulong linear;
1353
83b8795a 1354 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1355 if (rc != X86EMUL_CONTINUE)
1356 return rc;
0f65dd70
AK		 1357 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1358 size, &ctxt->exception);
3ca3ac4d
AK		 1359}
1360
dde7e6d1 1361static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1362 unsigned int size, unsigned short port,
1363 void *dest)
1364{
9dac77fa 1365 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1366
dde7e6d1 1367 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1368 unsigned int in_page, n;
9dac77fa 1369 unsigned int count = ctxt->rep_prefix ?
dd856efa 1370 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1371 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1372 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1373 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1374 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1375 if (n == 0)
1376 n = 1;
1377 rc->pos = rc->end = 0;
7b105ca2 1378 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1379 return 0;
1380 rc->end = n * size;
6aa8b732
AK		 1381 }
1382
e6e39f04
NA		 1383 if (ctxt->rep_prefix && (ctxt->d & String) &&
1384 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1385 ctxt->dst.data = rc->data + rc->pos;
1386 ctxt->dst.type = OP_MEM_STR;
1387 ctxt->dst.count = (rc->end - rc->pos) / size;
1388 rc->pos = rc->end;
1389 } else {
1390 memcpy(dest, rc->data + rc->pos, size);
1391 rc->pos += size;
1392 }
dde7e6d1
AK		 1393 return 1;
1394}
6aa8b732 1395
7f3d35fd
KW		 1396static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1397 u16 index, struct desc_struct *desc)
1398{
1399 struct desc_ptr dt;
1400 ulong addr;
1401
1402 ctxt->ops->get_idt(ctxt, &dt);
1403
1404 if (dt.size < index * 8 + 7)
1405 return emulate_gp(ctxt, index << 3 | 0x2);
1406
1407 addr = dt.address + index * 8;
1408 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1409 &ctxt->exception);
1410}
1411
dde7e6d1 1412static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1413 u16 selector, struct desc_ptr *dt)
1414{
0225fb50 1415 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1416 u32 base3 = 0;
7b105ca2 1417
dde7e6d1
AK		 1418 if (selector & 1 << 2) {
1419 struct desc_struct desc;
1aa36616
AK		 1420 u16 sel;
1421
dde7e6d1 1422 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1423 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1424 VCPU_SREG_LDTR))
dde7e6d1 1425 return;
e09d082c 1426
dde7e6d1 1427 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1428 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1429 } else
4bff1e86 1430 ops->get_gdt(ctxt, dt);
dde7e6d1 1431}
120df890 1432
dde7e6d1
AK		 1433/* allowed just for 8 bytes segments */
1434static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1435 u16 selector, struct desc_struct *desc,
1436 ulong *desc_addr_p)
dde7e6d1
AK		 1437{
1438 struct desc_ptr dt;
1439 u16 index = selector >> 3;
dde7e6d1 1440 ulong addr;
120df890 1441
7b105ca2 1442 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1443
35d3d4a1
AK		 1444 if (dt.size < index * 8 + 7)
1445 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1446
e919464b 1447 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1448 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1449 &ctxt->exception);
dde7e6d1 1450}
ef65c889 1451
dde7e6d1
AK		 1452/* allowed just for 8 bytes segments */
1453static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1454 u16 selector, struct desc_struct *desc)
1455{
1456 struct desc_ptr dt;
1457 u16 index = selector >> 3;
dde7e6d1 1458 ulong addr;
6aa8b732 1459
7b105ca2 1460 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1461
35d3d4a1
AK		 1462 if (dt.size < index * 8 + 7)
1463 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1464
dde7e6d1 1465 addr = dt.address + index * 8;
7b105ca2
TY		 1466 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1467 &ctxt->exception);
dde7e6d1 1468}
c7e75a3d 1469
5601d05b 1470/* Does not support long mode */
2356aaeb 1471static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1472 u16 selector, int seg, u8 cpl,
1473 bool in_task_switch,
1474 struct desc_struct *desc)
dde7e6d1 1475{
869be99c 1476 struct desc_struct seg_desc, old_desc;
2356aaeb 1477 u8 dpl, rpl;
dde7e6d1
AK		 1478 unsigned err_vec = GP_VECTOR;
1479 u32 err_code = 0;
1480 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1481 ulong desc_addr;
dde7e6d1 1482 int ret;
03ebebeb 1483 u16 dummy;
e37a75a1 1484 u32 base3 = 0;
69f55cb1 1485
dde7e6d1 1486 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1487
f8da94e9
KW		 1488 if (ctxt->mode == X86EMUL_MODE_REAL) {
1489 /* set real mode segment descriptor (keep limit etc. for
1490 * unreal mode) */
03ebebeb 1491 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1492 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1493 goto load;
f8da94e9
KW		 1494 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1495 /* VM86 needs a clean new segment descriptor */
1496 set_desc_base(&seg_desc, selector << 4);
1497 set_desc_limit(&seg_desc, 0xffff);
1498 seg_desc.type = 3;
1499 seg_desc.p = 1;
1500 seg_desc.s = 1;
1501 seg_desc.dpl = 3;
1502 goto load;
dde7e6d1
AK		 1503 }
1504
79d5b4c3 1505 rpl = selector & 3;
79d5b4c3
AK		 1506
1507 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1508 if ((seg == VCPU_SREG_CS
1509 || (seg == VCPU_SREG_SS
1510 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1511 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1512 && null_selector)
1513 goto exception;
1514
1515 /* TR should be in GDT only */
1516 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1517 goto exception;
1518
1519 if (null_selector) /* for NULL selector skip all following checks */
1520 goto load;
1521
e919464b 1522 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1523 if (ret != X86EMUL_CONTINUE)
1524 return ret;
1525
1526 err_code = selector & 0xfffc;
15fc0752 1527 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1528
fc058680 1529 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1530 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1531 goto exception;
1532
1533 if (!seg_desc.p) {
1534 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1535 goto exception;
1536 }
1537
dde7e6d1 1538 dpl = seg_desc.dpl;
dde7e6d1
AK		 1539
1540 switch (seg) {
1541 case VCPU_SREG_SS:
1542 /*
1543 * segment is not a writable data segment or segment
1544 * selector's RPL != CPL or segment selector's RPL != CPL
1545 */
1546 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1547 goto exception;
6aa8b732 1548 break;
dde7e6d1
AK		 1549 case VCPU_SREG_CS:
1550 if (!(seg_desc.type & 8))
1551 goto exception;
1552
1553 if (seg_desc.type & 4) {
1554 /* conforming */
1555 if (dpl > cpl)
1556 goto exception;
1557 } else {
1558 /* nonconforming */
1559 if (rpl > cpl || dpl != cpl)
1560 goto exception;
1561 }
040c8dc8
NA		 1562 /* in long-mode d/b must be clear if l is set */
1563 if (seg_desc.d && seg_desc.l) {
1564 u64 efer = 0;
1565
1566 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1567 if (efer & EFER_LMA)
1568 goto exception;
1569 }
1570
dde7e6d1
AK		 1571 /* CS(RPL) <- CPL */
1572 selector = (selector & 0xfffc) | cpl;
6aa8b732 1573 break;
dde7e6d1
AK		 1574 case VCPU_SREG_TR:
1575 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1576 goto exception;
869be99c
AK		 1577 old_desc = seg_desc;
1578 seg_desc.type |= 2; /* busy */
1579 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1580 sizeof(seg_desc), &ctxt->exception);
1581 if (ret != X86EMUL_CONTINUE)
1582 return ret;
dde7e6d1
AK		 1583 break;
1584 case VCPU_SREG_LDTR:
1585 if (seg_desc.s || seg_desc.type != 2)
1586 goto exception;
1587 break;
1588 default: /* DS, ES, FS, or GS */
4e62417b 1589 /*
dde7e6d1
AK		 1590 * segment is not a data or readable code segment or
1591 * ((segment is a data or nonconforming code segment)
1592 * and (both RPL and CPL > DPL))
4e62417b 1593 */
dde7e6d1
AK		 1594 if ((seg_desc.type & 0xa) == 0x8 ||
1595 (((seg_desc.type & 0xc) != 0xc) &&
1596 (rpl > dpl && cpl > dpl)))
1597 goto exception;
6aa8b732 1598 break;
dde7e6d1
AK		 1599 }
1600
1601 if (seg_desc.s) {
1602 /* mark segment as accessed */
1603 seg_desc.type |= 1;
7b105ca2 1604 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1605 if (ret != X86EMUL_CONTINUE)
1606 return ret;
e37a75a1
NA		 1607 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1608 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1609 sizeof(base3), &ctxt->exception);
1610 if (ret != X86EMUL_CONTINUE)
1611 return ret;
dde7e6d1
AK		 1612 }
1613load:
e37a75a1 1614 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1615 if (desc)
1616 *desc = seg_desc;
dde7e6d1
AK		 1617 return X86EMUL_CONTINUE;
1618exception:
592f0858 1619 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1620}
1621
2356aaeb
PB		 1622static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1623 u16 selector, int seg)
1624{
1625 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1626 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1627}
1628
31be40b3
WY		 1629static void write_register_operand(struct operand *op)
1630{
1631 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1632 switch (op->bytes) {
1633 case 1:
1634 *(u8 *)op->addr.reg = (u8)op->val;
1635 break;
1636 case 2:
1637 *(u16 *)op->addr.reg = (u16)op->val;
1638 break;
1639 case 4:
1640 *op->addr.reg = (u32)op->val;
1641 break; /* 64b: zero-extend */
1642 case 8:
1643 *op->addr.reg = op->val;
1644 break;
1645 }
1646}
1647
fb32b1ed 1648static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1649{
fb32b1ed 1650 switch (op->type) {
dde7e6d1 1651 case OP_REG:
fb32b1ed 1652 write_register_operand(op);
6aa8b732 1653 break;
dde7e6d1 1654 case OP_MEM:
9dac77fa 1655 if (ctxt->lock_prefix)
f5f87dfb
PB		 1656 return segmented_cmpxchg(ctxt,
1657 op->addr.mem,
1658 &op->orig_val,
1659 &op->val,
1660 op->bytes);
1661 else
1662 return segmented_write(ctxt,
fb32b1ed 1663 op->addr.mem,
fb32b1ed
AK		 1664 &op->val,
1665 op->bytes);
a682e354 1666 break;
b3356bf0 1667 case OP_MEM_STR:
f5f87dfb
PB		 1668 return segmented_write(ctxt,
1669 op->addr.mem,
1670 op->data,
1671 op->bytes * op->count);
b3356bf0 1672 break;
1253791d 1673 case OP_XMM:
fb32b1ed 1674 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1675 break;
cbe2c9d3 1676 case OP_MM:
fb32b1ed 1677 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1678 break;
dde7e6d1
AK		 1679 case OP_NONE:
1680 /* no writeback */
414e6277 1681 break;
dde7e6d1 1682 default:
414e6277 1683 break;
6aa8b732 1684 }
dde7e6d1
AK		 1685 return X86EMUL_CONTINUE;
1686}
6aa8b732 1687
51ddff50 1688static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1689{
4179bb02 1690 struct segmented_address addr;
0dc8d10f 1691
5ad105e5 1692 rsp_increment(ctxt, -bytes);
dd856efa 1693 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1694 addr.seg = VCPU_SREG_SS;
1695
51ddff50
AK		 1696 return segmented_write(ctxt, addr, data, bytes);
1697}
1698
1699static int em_push(struct x86_emulate_ctxt *ctxt)
1700{
4179bb02 1701 /* Disable writeback. */
9dac77fa 1702 ctxt->dst.type = OP_NONE;
51ddff50 1703 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1704}
69f55cb1 1705
dde7e6d1 1706static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1707 void *dest, int len)
1708{
dde7e6d1 1709 int rc;
90de84f5 1710 struct segmented_address addr;
8b4caf66 1711
dd856efa 1712 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1713 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1714 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1715 if (rc != X86EMUL_CONTINUE)
1716 return rc;
1717
5ad105e5 1718 rsp_increment(ctxt, len);
dde7e6d1 1719 return rc;
8b4caf66
LV		 1720}
1721
c54fe504
TY		 1722static int em_pop(struct x86_emulate_ctxt *ctxt)
1723{
9dac77fa 1724 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1725}
1726
dde7e6d1 1727static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1728 void *dest, int len)
9de41573
GN		 1729{
1730 int rc;
dde7e6d1
AK		 1731 unsigned long val, change_mask;
1732 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1733 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1734
3b9be3bf 1735 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1736 if (rc != X86EMUL_CONTINUE)
1737 return rc;
9de41573 1738
dde7e6d1 1739 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1740 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1741
dde7e6d1
AK		 1742 switch(ctxt->mode) {
1743 case X86EMUL_MODE_PROT64:
1744 case X86EMUL_MODE_PROT32:
1745 case X86EMUL_MODE_PROT16:
1746 if (cpl == 0)
1747 change_mask |= EFLG_IOPL;
1748 if (cpl <= iopl)
1749 change_mask |= EFLG_IF;
1750 break;
1751 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1752 if (iopl < 3)
1753 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1754 change_mask |= EFLG_IF;
1755 break;
1756 default: /* real mode */
1757 change_mask |= (EFLG_IOPL | EFLG_IF);
1758 break;
9de41573 1759 }
dde7e6d1
AK		 1760
1761 *(unsigned long *)dest =
1762 (ctxt->eflags & ~change_mask) | (val & change_mask);
1763
1764 return rc;
9de41573
GN		 1765}
1766
62aaa2f0
TY		 1767static int em_popf(struct x86_emulate_ctxt *ctxt)
1768{
9dac77fa
AK		 1769 ctxt->dst.type = OP_REG;
1770 ctxt->dst.addr.reg = &ctxt->eflags;
1771 ctxt->dst.bytes = ctxt->op_bytes;
1772 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1773}
1774
612e89f0
AK		 1775static int em_enter(struct x86_emulate_ctxt *ctxt)
1776{
1777 int rc;
1778 unsigned frame_size = ctxt->src.val;
1779 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1780 ulong rbp;
612e89f0
AK		 1781
1782 if (nesting_level)
1783 return X86EMUL_UNHANDLEABLE;
1784
dd856efa
AK		 1785 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1786 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1787 if (rc != X86EMUL_CONTINUE)
1788 return rc;
dd856efa 1789 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1790 stack_mask(ctxt));
dd856efa
AK		 1791 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1792 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1793 stack_mask(ctxt));
1794 return X86EMUL_CONTINUE;
1795}
1796
f47cfa31
AK		 1797static int em_leave(struct x86_emulate_ctxt *ctxt)
1798{
dd856efa 1799 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1800 stack_mask(ctxt));
dd856efa 1801 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1802}
1803
1cd196ea 1804static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1805{
1cd196ea
AK		 1806 int seg = ctxt->src2.val;
1807
9dac77fa 1808 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1809
4487b3b4 1810 return em_push(ctxt);
7b262e90
GN		 1811}
1812
1cd196ea 1813static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1814{
1cd196ea 1815 int seg = ctxt->src2.val;
dde7e6d1
AK		 1816 unsigned long selector;
1817 int rc;
38ba30ba 1818
9dac77fa 1819 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1820 if (rc != X86EMUL_CONTINUE)
1821 return rc;
1822
a5457e7b
PB		 1823 if (ctxt->modrm_reg == VCPU_SREG_SS)
1824 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1825
7b105ca2 1826 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1827 return rc;
38ba30ba
GN		 1828}
1829
b96a7fad 1830static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1831{
dd856efa 1832 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1833 int rc = X86EMUL_CONTINUE;
1834 int reg = VCPU_REGS_RAX;
38ba30ba 1835
dde7e6d1
AK		 1836 while (reg <= VCPU_REGS_RDI) {
1837 (reg == VCPU_REGS_RSP) ?
dd856efa 1838 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1839
4487b3b4 1840 rc = em_push(ctxt);
dde7e6d1
AK		 1841 if (rc != X86EMUL_CONTINUE)
1842 return rc;
38ba30ba 1843
dde7e6d1 1844 ++reg;
38ba30ba 1845 }
38ba30ba 1846
dde7e6d1 1847 return rc;
38ba30ba
GN		 1848}
1849
62aaa2f0
TY		 1850static int em_pushf(struct x86_emulate_ctxt *ctxt)
1851{
9dac77fa 1852 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1853 return em_push(ctxt);
1854}
1855
b96a7fad 1856static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1857{
dde7e6d1
AK		 1858 int rc = X86EMUL_CONTINUE;
1859 int reg = VCPU_REGS_RDI;
38ba30ba 1860
dde7e6d1
AK		 1861 while (reg >= VCPU_REGS_RAX) {
1862 if (reg == VCPU_REGS_RSP) {
5ad105e5 1863 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1864 --reg;
1865 }
38ba30ba 1866
dd856efa 1867 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1868 if (rc != X86EMUL_CONTINUE)
1869 break;
1870 --reg;
38ba30ba 1871 }
dde7e6d1 1872 return rc;
38ba30ba
GN		 1873}
1874
dd856efa 1875static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1876{
0225fb50 1877 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1878 int rc;
6e154e56
MG		 1879 struct desc_ptr dt;
1880 gva_t cs_addr;
1881 gva_t eip_addr;
1882 u16 cs, eip;
6e154e56
MG		 1883
1884 /* TODO: Add limit checks */
9dac77fa 1885 ctxt->src.val = ctxt->eflags;
4487b3b4 1886 rc = em_push(ctxt);
5c56e1cf
AK		 1887 if (rc != X86EMUL_CONTINUE)
1888 return rc;
6e154e56
MG		 1889
1890 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1891
9dac77fa 1892 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1893 rc = em_push(ctxt);
5c56e1cf
AK		 1894 if (rc != X86EMUL_CONTINUE)
1895 return rc;
6e154e56 1896
9dac77fa 1897 ctxt->src.val = ctxt->_eip;
4487b3b4 1898 rc = em_push(ctxt);
5c56e1cf
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
1901
4bff1e86 1902 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1903
1904 eip_addr = dt.address + (irq << 2);
1905 cs_addr = dt.address + (irq << 2) + 2;
1906
0f65dd70 1907 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1908 if (rc != X86EMUL_CONTINUE)
1909 return rc;
1910
0f65dd70 1911 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
1914
7b105ca2 1915 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1916 if (rc != X86EMUL_CONTINUE)
1917 return rc;
1918
9dac77fa 1919 ctxt->_eip = eip;
6e154e56
MG		 1920
1921 return rc;
1922}
1923
dd856efa
AK		 1924int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1925{
1926 int rc;
1927
1928 invalidate_registers(ctxt);
1929 rc = __emulate_int_real(ctxt, irq);
1930 if (rc == X86EMUL_CONTINUE)
1931 writeback_registers(ctxt);
1932 return rc;
1933}
1934
7b105ca2 1935static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1936{
1937 switch(ctxt->mode) {
1938 case X86EMUL_MODE_REAL:
dd856efa 1939 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1940 case X86EMUL_MODE_VM86:
1941 case X86EMUL_MODE_PROT16:
1942 case X86EMUL_MODE_PROT32:
1943 case X86EMUL_MODE_PROT64:
1944 default:
1945 /* Protected mode interrupts unimplemented yet */
1946 return X86EMUL_UNHANDLEABLE;
1947 }
1948}
1949
7b105ca2 1950static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1951{
dde7e6d1
AK		 1952 int rc = X86EMUL_CONTINUE;
1953 unsigned long temp_eip = 0;
1954 unsigned long temp_eflags = 0;
1955 unsigned long cs = 0;
1956 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1957 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1958 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1959 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1960
dde7e6d1 1961 /* TODO: Add stack limit check */
38ba30ba 1962
9dac77fa 1963 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1964
dde7e6d1
AK		 1965 if (rc != X86EMUL_CONTINUE)
1966 return rc;
38ba30ba 1967
35d3d4a1
AK		 1968 if (temp_eip & ~0xffff)
1969 return emulate_gp(ctxt, 0);
38ba30ba 1970
9dac77fa 1971 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1972
dde7e6d1
AK		 1973 if (rc != X86EMUL_CONTINUE)
1974 return rc;
38ba30ba 1975
9dac77fa 1976 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1977
dde7e6d1
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 return rc;
38ba30ba 1980
7b105ca2 1981 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1982
dde7e6d1
AK		 1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
38ba30ba 1985
9dac77fa 1986 ctxt->_eip = temp_eip;
38ba30ba 1987
38ba30ba 1988
9dac77fa 1989 if (ctxt->op_bytes == 4)
dde7e6d1 1990 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1991 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1992 ctxt->eflags &= ~0xffff;
1993 ctxt->eflags |= temp_eflags;
38ba30ba 1994 }
dde7e6d1
AK		 1995
1996 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1997 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1998
1999 return rc;
38ba30ba
GN		 2000}
2001
e01991e7 2002static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2003{
dde7e6d1
AK		 2004 switch(ctxt->mode) {
2005 case X86EMUL_MODE_REAL:
7b105ca2 2006 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2007 case X86EMUL_MODE_VM86:
2008 case X86EMUL_MODE_PROT16:
2009 case X86EMUL_MODE_PROT32:
2010 case X86EMUL_MODE_PROT64:
c37eda13 2011 default:
dde7e6d1
AK		 2012 /* iret from protected mode unimplemented yet */
2013 return X86EMUL_UNHANDLEABLE;
c37eda13 2014 }
c37eda13
WY		 2015}
2016
d2f62766
TY		 2017static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2018{
d2f62766 2019 int rc;
d1442d85
NA		 2020 unsigned short sel, old_sel;
2021 struct desc_struct old_desc, new_desc;
2022 const struct x86_emulate_ops *ops = ctxt->ops;
2023 u8 cpl = ctxt->ops->cpl(ctxt);
2024
2025 /* Assignment of RIP may only fail in 64-bit mode */
2026 if (ctxt->mode == X86EMUL_MODE_PROT64)
2027 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2028 VCPU_SREG_CS);
d2f62766 2029
9dac77fa 2030 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2031
d1442d85
NA		 2032 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2033 &new_desc);
d2f62766
TY		 2034 if (rc != X86EMUL_CONTINUE)
2035 return rc;
2036
d1442d85
NA		 2037 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2038 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2039 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2040 /* assigning eip failed; restore the old cs */
2041 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2042 return rc;
2043 }
2044 return rc;
d2f62766
TY		 2045}
2046
f7784046 2047static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2048{
f7784046
NA		 2049 return assign_eip_near(ctxt, ctxt->src.val);
2050}
8cdbd2c9 2051
f7784046
NA		 2052static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2053{
2054 int rc;
2055 long int old_eip;
2056
2057 old_eip = ctxt->_eip;
2058 rc = assign_eip_near(ctxt, ctxt->src.val);
2059 if (rc != X86EMUL_CONTINUE)
2060 return rc;
2061 ctxt->src.val = old_eip;
2062 rc = em_push(ctxt);
4179bb02 2063 return rc;
8cdbd2c9
LV		 2064}
2065
e0dac408 2066static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2067{
9dac77fa 2068 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2069
aaa05f24
NA		 2070 if (ctxt->dst.bytes == 16)
2071 return X86EMUL_UNHANDLEABLE;
2072
dd856efa
AK		 2073 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2074 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2075 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2076 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2077 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2078 } else {
dd856efa
AK		 2079 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2080 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2081
05f086f8 2082 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2083 }
1b30eaa8 2084 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2085}
2086
ebda02c2
TY		 2087static int em_ret(struct x86_emulate_ctxt *ctxt)
2088{
234f3ce4
NA		 2089 int rc;
2090 unsigned long eip;
2091
2092 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2093 if (rc != X86EMUL_CONTINUE)
2094 return rc;
2095
2096 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2097}
2098
e01991e7 2099static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2100{
a77ab5ea 2101 int rc;
d1442d85
NA		 2102 unsigned long eip, cs;
2103 u16 old_cs;
9e8919ae 2104 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2105 struct desc_struct old_desc, new_desc;
2106 const struct x86_emulate_ops *ops = ctxt->ops;
2107
2108 if (ctxt->mode == X86EMUL_MODE_PROT64)
2109 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2110 VCPU_SREG_CS);
a77ab5ea 2111
d1442d85 2112 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2113 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2114 return rc;
9dac77fa 2115 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2116 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2117 return rc;
9e8919ae
NA		 2118 /* Outer-privilege level return is not implemented */
2119 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2120 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2121 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2122 &new_desc);
2123 if (rc != X86EMUL_CONTINUE)
2124 return rc;
2125 rc = assign_eip_far(ctxt, eip, new_desc.l);
2126 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2127 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2128 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2129 }
a77ab5ea
AK		 2130 return rc;
2131}
2132
3261107e
BR		 2133static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2134{
2135 int rc;
2136
2137 rc = em_ret_far(ctxt);
2138 if (rc != X86EMUL_CONTINUE)
2139 return rc;
2140 rsp_increment(ctxt, ctxt->src.val);
2141 return X86EMUL_CONTINUE;
2142}
2143
e940b5c2
TY		 2144static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2145{
2146 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2147 ctxt->dst.orig_val = ctxt->dst.val;
2148 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2149 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2150 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2151 fastop(ctxt, em_cmp);
e940b5c2
TY		 2152
2153 if (ctxt->eflags & EFLG_ZF) {
2154 /* Success: write back to memory. */
2155 ctxt->dst.val = ctxt->src.orig_val;
2156 } else {
2157 /* Failure: write the value we saw to EAX. */
2158 ctxt->dst.type = OP_REG;
dd856efa 2159 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2160 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2161 }
2162 return X86EMUL_CONTINUE;
2163}
2164
d4b4325f 2165static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2166{
d4b4325f 2167 int seg = ctxt->src2.val;
09b5f4d3
WY		 2168 unsigned short sel;
2169 int rc;
2170
9dac77fa 2171 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2172
7b105ca2 2173 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2174 if (rc != X86EMUL_CONTINUE)
2175 return rc;
2176
9dac77fa 2177 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2178 return rc;
2179}
2180
7b105ca2 2181static void
e66bb2cc 2182setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2183 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2184{
e66bb2cc 2185 cs->l = 0; /* will be adjusted later */
79168fd1 2186 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2187 cs->g = 1; /* 4kb granularity */
79168fd1 2188 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2189 cs->type = 0x0b; /* Read, Execute, Accessed */
2190 cs->s = 1;
2191 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2192 cs->p = 1;
2193 cs->d = 1;
99245b50 2194 cs->avl = 0;
e66bb2cc 2195
79168fd1
GN		 2196 set_desc_base(ss, 0); /* flat segment */
2197 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2198 ss->g = 1; /* 4kb granularity */
2199 ss->s = 1;
2200 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2201 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2202 ss->dpl = 0;
79168fd1 2203 ss->p = 1;
99245b50
GN		 2204 ss->l = 0;
2205 ss->avl = 0;
e66bb2cc
AP		 2206}
2207
1a18a69b
AK		 2208static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2209{
2210 u32 eax, ebx, ecx, edx;
2211
2212 eax = ecx = 0;
0017f93a
AK		 2213 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2214 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2215 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2216 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2217}
2218
c2226fc9
SB		 2219static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2220{
0225fb50 2221 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2222 u32 eax, ebx, ecx, edx;
2223
2224 /*
2225 * syscall should always be enabled in longmode - so only become
2226 * vendor specific (cpuid) if other modes are active...
2227 */
2228 if (ctxt->mode == X86EMUL_MODE_PROT64)
2229 return true;
2230
2231 eax = 0x00000000;
2232 ecx = 0x00000000;
0017f93a
AK		 2233 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2234 /*
2235 * Intel ("GenuineIntel")
2236 * remark: Intel CPUs only support "syscall" in 64bit
2237 * longmode. Also an 64bit guest with a
2238 * 32bit compat-app running will #UD !! While this
2239 * behaviour can be fixed (by emulating) into AMD
2240 * response - CPUs of AMD can't behave like Intel.
2241 */
2242 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2243 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2244 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2245 return false;
2246
2247 /* AMD ("AuthenticAMD") */
2248 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2249 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2250 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2251 return true;
2252
2253 /* AMD ("AMDisbetter!") */
2254 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2255 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2256 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2257 return true;
c2226fc9
SB		 2258
2259 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2260 return false;
2261}
2262
e01991e7 2263static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2264{
0225fb50 2265 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2266 struct desc_struct cs, ss;
e66bb2cc 2267 u64 msr_data;
79168fd1 2268 u16 cs_sel, ss_sel;
c2ad2bb3 2269 u64 efer = 0;
e66bb2cc
AP		 2270
2271 /* syscall is not available in real mode */
2e901c4c 2272 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2273 ctxt->mode == X86EMUL_MODE_VM86)
2274 return emulate_ud(ctxt);
e66bb2cc 2275
c2226fc9
SB		 2276 if (!(em_syscall_is_enabled(ctxt)))
2277 return emulate_ud(ctxt);
2278
c2ad2bb3 2279 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2280 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2281
c2226fc9
SB		 2282 if (!(efer & EFER_SCE))
2283 return emulate_ud(ctxt);
2284
717746e3 2285 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2286 msr_data >>= 32;
79168fd1
GN		 2287 cs_sel = (u16)(msr_data & 0xfffc);
2288 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2289
c2ad2bb3 2290 if (efer & EFER_LMA) {
79168fd1 2291 cs.d = 0;
e66bb2cc
AP		 2292 cs.l = 1;
2293 }
1aa36616
AK		 2294 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2295 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2296
dd856efa 2297 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2298 if (efer & EFER_LMA) {
e66bb2cc 2299#ifdef CONFIG_X86_64
6c6cb69b 2300 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2301
717746e3 2302 ops->get_msr(ctxt,
3fb1b5db
GN		 2303 ctxt->mode == X86EMUL_MODE_PROT64 ?
2304 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2305 ctxt->_eip = msr_data;
e66bb2cc 2306
717746e3 2307 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2308 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2309#endif
2310 } else {
2311 /* legacy mode */
717746e3 2312 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2313 ctxt->_eip = (u32)msr_data;
e66bb2cc 2314
6c6cb69b 2315 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2316 }
2317
e54cfa97 2318 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2319}
2320
e01991e7 2321static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2322{
0225fb50 2323 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2324 struct desc_struct cs, ss;
8c604352 2325 u64 msr_data;
79168fd1 2326 u16 cs_sel, ss_sel;
c2ad2bb3 2327 u64 efer = 0;
8c604352 2328
7b105ca2 2329 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2330 /* inject #GP if in real mode */
35d3d4a1
AK		 2331 if (ctxt->mode == X86EMUL_MODE_REAL)
2332 return emulate_gp(ctxt, 0);
8c604352 2333
1a18a69b
AK		 2334 /*
2335 * Not recognized on AMD in compat mode (but is recognized in legacy
2336 * mode).
2337 */
2338 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2339 && !vendor_intel(ctxt))
2340 return emulate_ud(ctxt);
2341
8c604352
AP		 2342 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2343 * Therefore, we inject an #UD.
2344 */
35d3d4a1
AK		 2345 if (ctxt->mode == X86EMUL_MODE_PROT64)
2346 return emulate_ud(ctxt);
8c604352 2347
7b105ca2 2348 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2349
717746e3 2350 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2351 switch (ctxt->mode) {
2352 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2353 if ((msr_data & 0xfffc) == 0x0)
2354 return emulate_gp(ctxt, 0);
8c604352
AP		 2355 break;
2356 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2357 if (msr_data == 0x0)
2358 return emulate_gp(ctxt, 0);
8c604352 2359 break;
9d1b39a9
GN		 2360 default:
2361 break;
8c604352
AP		 2362 }
2363
6c6cb69b 2364 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2365 cs_sel = (u16)msr_data;
2366 cs_sel &= ~SELECTOR_RPL_MASK;
2367 ss_sel = cs_sel + 8;
2368 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2369 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2370 cs.d = 0;
8c604352
AP		 2371 cs.l = 1;
2372 }
2373
1aa36616
AK		 2374 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2375 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2376
717746e3 2377 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2378 ctxt->_eip = msr_data;
8c604352 2379
717746e3 2380 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2381 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2382
e54cfa97 2383 return X86EMUL_CONTINUE;
8c604352
AP		 2384}
2385
e01991e7 2386static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2387{
0225fb50 2388 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2389 struct desc_struct cs, ss;
234f3ce4 2390 u64 msr_data, rcx, rdx;
4668f050 2391 int usermode;
1249b96e 2392 u16 cs_sel = 0, ss_sel = 0;
4668f050 2393
a0044755
GN		 2394 /* inject #GP if in real mode or Virtual 8086 mode */
2395 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2396 ctxt->mode == X86EMUL_MODE_VM86)
2397 return emulate_gp(ctxt, 0);
4668f050 2398
7b105ca2 2399 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2400
9dac77fa 2401 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2402 usermode = X86EMUL_MODE_PROT64;
2403 else
2404 usermode = X86EMUL_MODE_PROT32;
2405
234f3ce4
NA		 2406 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2407 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2408
4668f050
AP		 2409 cs.dpl = 3;
2410 ss.dpl = 3;
717746e3 2411 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2412 switch (usermode) {
2413 case X86EMUL_MODE_PROT32:
79168fd1 2414 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2415 if ((msr_data & 0xfffc) == 0x0)
2416 return emulate_gp(ctxt, 0);
79168fd1 2417 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2418 rcx = (u32)rcx;
2419 rdx = (u32)rdx;
4668f050
AP		 2420 break;
2421 case X86EMUL_MODE_PROT64:
79168fd1 2422 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2423 if (msr_data == 0x0)
2424 return emulate_gp(ctxt, 0);
79168fd1
GN		 2425 ss_sel = cs_sel + 8;
2426 cs.d = 0;
4668f050 2427 cs.l = 1;
234f3ce4
NA		 2428 if (is_noncanonical_address(rcx) ||
2429 is_noncanonical_address(rdx))
2430 return emulate_gp(ctxt, 0);
4668f050
AP		 2431 break;
2432 }
79168fd1
GN		 2433 cs_sel |= SELECTOR_RPL_MASK;
2434 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2435
1aa36616
AK		 2436 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2437 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2438
234f3ce4
NA		 2439 ctxt->_eip = rdx;
2440 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2441
e54cfa97 2442 return X86EMUL_CONTINUE;
4668f050
AP		 2443}
2444
7b105ca2 2445static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2446{
2447 int iopl;
2448 if (ctxt->mode == X86EMUL_MODE_REAL)
2449 return false;
2450 if (ctxt->mode == X86EMUL_MODE_VM86)
2451 return true;
2452 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2453 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2454}
2455
2456static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2457 u16 port, u16 len)
2458{
0225fb50 2459 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2460 struct desc_struct tr_seg;
5601d05b 2461 u32 base3;
f850e2e6 2462 int r;
1aa36616 2463 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2464 unsigned mask = (1 << len) - 1;
5601d05b 2465 unsigned long base;
f850e2e6 2466
1aa36616 2467 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2468 if (!tr_seg.p)
f850e2e6 2469 return false;
79168fd1 2470 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2471 return false;
5601d05b
GN		 2472 base = get_desc_base(&tr_seg);
2473#ifdef CONFIG_X86_64
2474 base |= ((u64)base3) << 32;
2475#endif
0f65dd70 2476 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2477 if (r != X86EMUL_CONTINUE)
2478 return false;
79168fd1 2479 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2480 return false;
0f65dd70 2481 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2482 if (r != X86EMUL_CONTINUE)
2483 return false;
2484 if ((perm >> bit_idx) & mask)
2485 return false;
2486 return true;
2487}
2488
2489static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2490 u16 port, u16 len)
2491{
4fc40f07
GN		 2492 if (ctxt->perm_ok)
2493 return true;
2494
7b105ca2
TY		 2495 if (emulator_bad_iopl(ctxt))
2496 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2497 return false;
4fc40f07
GN		 2498
2499 ctxt->perm_ok = true;
2500
f850e2e6
GN		 2501 return true;
2502}
2503
38ba30ba 2504static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2505 struct tss_segment_16 *tss)
2506{
9dac77fa 2507 tss->ip = ctxt->_eip;
38ba30ba 2508 tss->flag = ctxt->eflags;
dd856efa
AK		 2509 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2510 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2511 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2512 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2513 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2514 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2515 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2516 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2517
1aa36616
AK		 2518 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2519 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2520 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2521 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2522 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2523}
2524
2525static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2526 struct tss_segment_16 *tss)
2527{
38ba30ba 2528 int ret;
2356aaeb 2529 u8 cpl;
38ba30ba 2530
9dac77fa 2531 ctxt->_eip = tss->ip;
38ba30ba 2532 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2533 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2534 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2535 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2536 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2537 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2538 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2539 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2540 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2541
2542 /*
2543 * SDM says that segment selectors are loaded before segment
2544 * descriptors
2545 */
1aa36616
AK		 2546 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2547 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2548 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2549 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2550 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2551
2356aaeb
PB		 2552 cpl = tss->cs & 3;
2553
38ba30ba 2554 /*
fc058680 2555 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2556 * it is handled in a context of new task
2557 */
d1442d85
NA		 2558 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2559 true, NULL);
38ba30ba
GN		 2560 if (ret != X86EMUL_CONTINUE)
2561 return ret;
d1442d85
NA		 2562 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2563 true, NULL);
38ba30ba
GN		 2564 if (ret != X86EMUL_CONTINUE)
2565 return ret;
d1442d85
NA		 2566 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2567 true, NULL);
38ba30ba
GN		 2568 if (ret != X86EMUL_CONTINUE)
2569 return ret;
d1442d85
NA		 2570 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2571 true, NULL);
38ba30ba
GN		 2572 if (ret != X86EMUL_CONTINUE)
2573 return ret;
d1442d85
NA		 2574 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2575 true, NULL);
38ba30ba
GN		 2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
2578
2579 return X86EMUL_CONTINUE;
2580}
2581
2582static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2583 u16 tss_selector, u16 old_tss_sel,
2584 ulong old_tss_base, struct desc_struct *new_desc)
2585{
0225fb50 2586 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2587 struct tss_segment_16 tss_seg;
2588 int ret;
bcc55cba 2589 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2590
0f65dd70 2591 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2592 &ctxt->exception);
db297e3d 2593 if (ret != X86EMUL_CONTINUE)
38ba30ba 2594 /* FIXME: need to provide precise fault address */
38ba30ba 2595 return ret;
38ba30ba 2596
7b105ca2 2597 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2598
0f65dd70 2599 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2600 &ctxt->exception);
db297e3d 2601 if (ret != X86EMUL_CONTINUE)
38ba30ba 2602 /* FIXME: need to provide precise fault address */
38ba30ba 2603 return ret;
38ba30ba 2604
0f65dd70 2605 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2606 &ctxt->exception);
db297e3d 2607 if (ret != X86EMUL_CONTINUE)
38ba30ba 2608 /* FIXME: need to provide precise fault address */
38ba30ba 2609 return ret;
38ba30ba
GN		 2610
2611 if (old_tss_sel != 0xffff) {
2612 tss_seg.prev_task_link = old_tss_sel;
2613
0f65dd70 2614 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2615 &tss_seg.prev_task_link,
2616 sizeof tss_seg.prev_task_link,
0f65dd70 2617 &ctxt->exception);
db297e3d 2618 if (ret != X86EMUL_CONTINUE)
38ba30ba 2619 /* FIXME: need to provide precise fault address */
38ba30ba 2620 return ret;
38ba30ba
GN		 2621 }
2622
7b105ca2 2623 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2624}
2625
2626static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2627 struct tss_segment_32 *tss)
2628{
5c7411e2 2629 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2630 tss->eip = ctxt->_eip;
38ba30ba 2631 tss->eflags = ctxt->eflags;
dd856efa
AK		 2632 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2633 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2634 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2635 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2636 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2637 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2638 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2639 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2640
1aa36616
AK		 2641 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2642 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2643 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2644 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2645 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2646 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2647}
2648
2649static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2650 struct tss_segment_32 *tss)
2651{
38ba30ba 2652 int ret;
2356aaeb 2653 u8 cpl;
38ba30ba 2654
7b105ca2 2655 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2656 return emulate_gp(ctxt, 0);
9dac77fa 2657 ctxt->_eip = tss->eip;
38ba30ba 2658 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2659
2660 /* General purpose registers */
dd856efa
AK		 2661 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2662 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2663 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2664 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2665 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2666 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2667 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2668 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2669
2670 /*
2671 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2672 * descriptors. This is important because CPL checks will
2673 * use CS.RPL.
38ba30ba 2674 */
1aa36616
AK		 2675 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2676 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2677 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2678 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2679 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2680 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2681 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2682
4cee4798
KW		 2683 /*
2684 * If we're switching between Protected Mode and VM86, we need to make
2685 * sure to update the mode before loading the segment descriptors so
2686 * that the selectors are interpreted correctly.
4cee4798 2687 */
2356aaeb 2688 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2689 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2690 cpl = 3;
2691 } else {
4cee4798 2692 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2693 cpl = tss->cs & 3;
2694 }
4cee4798 2695
38ba30ba
GN		 2696 /*
2697 * Now load segment descriptors. If fault happenes at this stage
2698 * it is handled in a context of new task
2699 */
d1442d85
NA		 2700 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2701 cpl, true, NULL);
38ba30ba
GN		 2702 if (ret != X86EMUL_CONTINUE)
2703 return ret;
d1442d85
NA		 2704 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2705 true, NULL);
38ba30ba
GN		 2706 if (ret != X86EMUL_CONTINUE)
2707 return ret;
d1442d85
NA		 2708 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2709 true, NULL);
38ba30ba
GN		 2710 if (ret != X86EMUL_CONTINUE)
2711 return ret;
d1442d85
NA		 2712 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2713 true, NULL);
38ba30ba
GN		 2714 if (ret != X86EMUL_CONTINUE)
2715 return ret;
d1442d85
NA		 2716 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2717 true, NULL);
38ba30ba
GN		 2718 if (ret != X86EMUL_CONTINUE)
2719 return ret;
d1442d85
NA		 2720 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2721 true, NULL);
38ba30ba
GN		 2722 if (ret != X86EMUL_CONTINUE)
2723 return ret;
d1442d85
NA		 2724 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2725 true, NULL);
38ba30ba
GN		 2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
2728
2729 return X86EMUL_CONTINUE;
2730}
2731
2732static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2733 u16 tss_selector, u16 old_tss_sel,
2734 ulong old_tss_base, struct desc_struct *new_desc)
2735{
0225fb50 2736 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2737 struct tss_segment_32 tss_seg;
2738 int ret;
bcc55cba 2739 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2740 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2741 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2742
0f65dd70 2743 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2744 &ctxt->exception);
db297e3d 2745 if (ret != X86EMUL_CONTINUE)
38ba30ba 2746 /* FIXME: need to provide precise fault address */
38ba30ba 2747 return ret;
38ba30ba 2748
7b105ca2 2749 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2750
5c7411e2
NA		 2751 /* Only GP registers and segment selectors are saved */
2752 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2753 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2754 if (ret != X86EMUL_CONTINUE)
38ba30ba 2755 /* FIXME: need to provide precise fault address */
38ba30ba 2756 return ret;
38ba30ba 2757
0f65dd70 2758 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2759 &ctxt->exception);
db297e3d 2760 if (ret != X86EMUL_CONTINUE)
38ba30ba 2761 /* FIXME: need to provide precise fault address */
38ba30ba 2762 return ret;
38ba30ba
GN		 2763
2764 if (old_tss_sel != 0xffff) {
2765 tss_seg.prev_task_link = old_tss_sel;
2766
0f65dd70 2767 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2768 &tss_seg.prev_task_link,
2769 sizeof tss_seg.prev_task_link,
0f65dd70 2770 &ctxt->exception);
db297e3d 2771 if (ret != X86EMUL_CONTINUE)
38ba30ba 2772 /* FIXME: need to provide precise fault address */
38ba30ba 2773 return ret;
38ba30ba
GN		 2774 }
2775
7b105ca2 2776 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2777}
2778
2779static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2780 u16 tss_selector, int idt_index, int reason,
e269fb21 2781 bool has_error_code, u32 error_code)
38ba30ba 2782{
0225fb50 2783 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2784 struct desc_struct curr_tss_desc, next_tss_desc;
2785 int ret;
1aa36616 2786 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2787 ulong old_tss_base =
4bff1e86 2788 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2789 u32 desc_limit;
e919464b 2790 ulong desc_addr;
38ba30ba
GN		 2791
2792 /* FIXME: old_tss_base == ~0 ? */
2793
e919464b 2794 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2795 if (ret != X86EMUL_CONTINUE)
2796 return ret;
e919464b 2797 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2798 if (ret != X86EMUL_CONTINUE)
2799 return ret;
2800
2801 /* FIXME: check that next_tss_desc is tss */
2802
7f3d35fd
KW		 2803 /*
2804 * Check privileges. The three cases are task switch caused by...
2805 *
2806 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2807 * 2. Exception/IRQ/iret: No check is performed
fc058680 2808 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2809 */
2810 if (reason == TASK_SWITCH_GATE) {
2811 if (idt_index != -1) {
2812 /* Software interrupts */
2813 struct desc_struct task_gate_desc;
2814 int dpl;
2815
2816 ret = read_interrupt_descriptor(ctxt, idt_index,
2817 &task_gate_desc);
2818 if (ret != X86EMUL_CONTINUE)
2819 return ret;
2820
2821 dpl = task_gate_desc.dpl;
2822 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2823 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2824 }
2825 } else if (reason != TASK_SWITCH_IRET) {
2826 int dpl = next_tss_desc.dpl;
2827 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2828 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2829 }
2830
7f3d35fd 2831
ceffb459
GN		 2832 desc_limit = desc_limit_scaled(&next_tss_desc);
2833 if (!next_tss_desc.p ||
2834 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2835 desc_limit < 0x2b)) {
592f0858 2836 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2837 }
2838
2839 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2840 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2841 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2842 }
2843
2844 if (reason == TASK_SWITCH_IRET)
2845 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2846
2847 /* set back link to prev task only if NT bit is set in eflags
fc058680 2848 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2849 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2850 old_tss_sel = 0xffff;
2851
2852 if (next_tss_desc.type & 8)
7b105ca2 2853 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2854 old_tss_base, &next_tss_desc);
2855 else
7b105ca2 2856 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2857 old_tss_base, &next_tss_desc);
0760d448
JK		 2858 if (ret != X86EMUL_CONTINUE)
2859 return ret;
38ba30ba
GN		 2860
2861 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2862 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2863
2864 if (reason != TASK_SWITCH_IRET) {
2865 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2866 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2867 }
2868
717746e3 2869 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2870 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2871
e269fb21 2872 if (has_error_code) {
9dac77fa
AK		 2873 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2874 ctxt->lock_prefix = 0;
2875 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2876 ret = em_push(ctxt);
e269fb21
JK		 2877 }
2878
38ba30ba
GN		 2879 return ret;
2880}
2881
2882int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2883 u16 tss_selector, int idt_index, int reason,
e269fb21 2884 bool has_error_code, u32 error_code)
38ba30ba 2885{
38ba30ba
GN		 2886 int rc;
2887
dd856efa 2888 invalidate_registers(ctxt);
9dac77fa
AK		 2889 ctxt->_eip = ctxt->eip;
2890 ctxt->dst.type = OP_NONE;
38ba30ba 2891
7f3d35fd 2892 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2893 has_error_code, error_code);
38ba30ba 2894
dd856efa 2895 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2896 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2897 writeback_registers(ctxt);
2898 }
38ba30ba 2899
a0c0ab2f 2900 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2901}
2902
f3bd64c6
GN		 2903static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2904 struct operand *op)
a682e354 2905{
b3356bf0 2906 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2907
dd856efa
AK		 2908 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2909 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2910}
2911
7af04fc0
AK		 2912static int em_das(struct x86_emulate_ctxt *ctxt)
2913{
7af04fc0
AK		 2914 u8 al, old_al;
2915 bool af, cf, old_cf;
2916
2917 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2918 al = ctxt->dst.val;
7af04fc0
AK		 2919
2920 old_al = al;
2921 old_cf = cf;
2922 cf = false;
2923 af = ctxt->eflags & X86_EFLAGS_AF;
2924 if ((al & 0x0f) > 9 || af) {
2925 al -= 6;
2926 cf = old_cf | (al >= 250);
2927 af = true;
2928 } else {
2929 af = false;
2930 }
2931 if (old_al > 0x99 || old_cf) {
2932 al -= 0x60;
2933 cf = true;
2934 }
2935
9dac77fa 2936 ctxt->dst.val = al;
7af04fc0 2937 /* Set PF, ZF, SF */
9dac77fa
AK		 2938 ctxt->src.type = OP_IMM;
2939 ctxt->src.val = 0;
2940 ctxt->src.bytes = 1;
158de57f 2941 fastop(ctxt, em_or);
7af04fc0
AK		 2942 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2943 if (cf)
2944 ctxt->eflags |= X86_EFLAGS_CF;
2945 if (af)
2946 ctxt->eflags |= X86_EFLAGS_AF;
2947 return X86EMUL_CONTINUE;
2948}
2949
a035d5c6
PB		 2950static int em_aam(struct x86_emulate_ctxt *ctxt)
2951{
2952 u8 al, ah;
2953
2954 if (ctxt->src.val == 0)
2955 return emulate_de(ctxt);
2956
2957 al = ctxt->dst.val & 0xff;
2958 ah = al / ctxt->src.val;
2959 al %= ctxt->src.val;
2960
2961 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2962
2963 /* Set PF, ZF, SF */
2964 ctxt->src.type = OP_IMM;
2965 ctxt->src.val = 0;
2966 ctxt->src.bytes = 1;
2967 fastop(ctxt, em_or);
2968
2969 return X86EMUL_CONTINUE;
2970}
2971
7f662273
GN		 2972static int em_aad(struct x86_emulate_ctxt *ctxt)
2973{
2974 u8 al = ctxt->dst.val & 0xff;
2975 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2976
2977 al = (al + (ah * ctxt->src.val)) & 0xff;
2978
2979 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2980
f583c29b
GN		 2981 /* Set PF, ZF, SF */
2982 ctxt->src.type = OP_IMM;
2983 ctxt->src.val = 0;
2984 ctxt->src.bytes = 1;
2985 fastop(ctxt, em_or);
7f662273
GN		 2986
2987 return X86EMUL_CONTINUE;
2988}
2989
d4ddafcd
TY		 2990static int em_call(struct x86_emulate_ctxt *ctxt)
2991{
234f3ce4 2992 int rc;
d4ddafcd
TY		 2993 long rel = ctxt->src.val;
2994
2995 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2996 rc = jmp_rel(ctxt, rel);
2997 if (rc != X86EMUL_CONTINUE)
2998 return rc;
d4ddafcd
TY		 2999 return em_push(ctxt);
3000}
3001
0ef753b8
AK		 3002static int em_call_far(struct x86_emulate_ctxt *ctxt)
3003{
0ef753b8
AK		 3004 u16 sel, old_cs;
3005 ulong old_eip;
3006 int rc;
d1442d85
NA		 3007 struct desc_struct old_desc, new_desc;
3008 const struct x86_emulate_ops *ops = ctxt->ops;
3009 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3010
9dac77fa 3011 old_eip = ctxt->_eip;
d1442d85 3012 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3013
9dac77fa 3014 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3015 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3016 &new_desc);
3017 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3018 return X86EMUL_CONTINUE;
3019
d1442d85
NA		 3020 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
3021 if (rc != X86EMUL_CONTINUE)
3022 goto fail;
0ef753b8 3023
9dac77fa 3024 ctxt->src.val = old_cs;
4487b3b4 3025 rc = em_push(ctxt);
0ef753b8 3026 if (rc != X86EMUL_CONTINUE)
d1442d85 3027 goto fail;
0ef753b8 3028
9dac77fa 3029 ctxt->src.val = old_eip;
d1442d85
NA		 3030 rc = em_push(ctxt);
3031 /* If we failed, we tainted the memory, but the very least we should
3032 restore cs */
3033 if (rc != X86EMUL_CONTINUE)
3034 goto fail;
3035 return rc;
3036fail:
3037 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3038 return rc;
3039
0ef753b8
AK		 3040}
3041
40ece7c7
AK		 3042static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3043{
40ece7c7 3044 int rc;
234f3ce4 3045 unsigned long eip;
40ece7c7 3046
234f3ce4
NA		 3047 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3048 if (rc != X86EMUL_CONTINUE)
3049 return rc;
3050 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3051 if (rc != X86EMUL_CONTINUE)
3052 return rc;
5ad105e5 3053 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3054 return X86EMUL_CONTINUE;
3055}
3056
e4f973ae
TY		 3057static int em_xchg(struct x86_emulate_ctxt *ctxt)
3058{
e4f973ae 3059 /* Write back the register source. */
9dac77fa
AK		 3060 ctxt->src.val = ctxt->dst.val;
3061 write_register_operand(&ctxt->src);
e4f973ae
TY		 3062
3063 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3064 ctxt->dst.val = ctxt->src.orig_val;
3065 ctxt->lock_prefix = 1;
e4f973ae
TY		 3066 return X86EMUL_CONTINUE;
3067}
3068
5c82aa29
AK		 3069static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3070{
9dac77fa 3071 ctxt->dst.val = ctxt->src2.val;
4d758349 3072 return fastop(ctxt, em_imul);
5c82aa29
AK		 3073}
3074
61429142
AK		 3075static int em_cwd(struct x86_emulate_ctxt *ctxt)
3076{
9dac77fa
AK		 3077 ctxt->dst.type = OP_REG;
3078 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3079 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3080 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3081
3082 return X86EMUL_CONTINUE;
3083}
3084
48bb5d3c
AK		 3085static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3086{
48bb5d3c
AK		 3087 u64 tsc = 0;
3088
717746e3 3089 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3090 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3091 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3092 return X86EMUL_CONTINUE;
3093}
3094
222d21aa
AK		 3095static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3096{
3097 u64 pmc;
3098
dd856efa 3099 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3100 return emulate_gp(ctxt, 0);
dd856efa
AK		 3101 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3102 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3103 return X86EMUL_CONTINUE;
3104}
3105
b9eac5f4
AK		 3106static int em_mov(struct x86_emulate_ctxt *ctxt)
3107{
54cfdb3e 3108 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3109 return X86EMUL_CONTINUE;
3110}
3111
84cffe49
BP		 3112#define FFL(x) bit(X86_FEATURE_##x)
3113
3114static int em_movbe(struct x86_emulate_ctxt *ctxt)
3115{
3116 u32 ebx, ecx, edx, eax = 1;
3117 u16 tmp;
3118
3119 /*
3120 * Check MOVBE is set in the guest-visible CPUID leaf.
3121 */
3122 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3123 if (!(ecx & FFL(MOVBE)))
3124 return emulate_ud(ctxt);
3125
3126 switch (ctxt->op_bytes) {
3127 case 2:
3128 /*
3129 * From MOVBE definition: "...When the operand size is 16 bits,
3130 * the upper word of the destination register remains unchanged
3131 * ..."
3132 *
3133 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3134 * rules so we have to do the operation almost per hand.
3135 */
3136 tmp = (u16)ctxt->src.val;
3137 ctxt->dst.val &= ~0xffffUL;
3138 ctxt->dst.val |= (unsigned long)swab16(tmp);
3139 break;
3140 case 4:
3141 ctxt->dst.val = swab32((u32)ctxt->src.val);
3142 break;
3143 case 8:
3144 ctxt->dst.val = swab64(ctxt->src.val);
3145 break;
3146 default:
592f0858 3147 BUG();
84cffe49
BP		 3148 }
3149 return X86EMUL_CONTINUE;
3150}
3151
bc00f8d2
TY		 3152static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3153{
3154 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3155 return emulate_gp(ctxt, 0);
3156
3157 /* Disable writeback. */
3158 ctxt->dst.type = OP_NONE;
3159 return X86EMUL_CONTINUE;
3160}
3161
3162static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3163{
3164 unsigned long val;
3165
3166 if (ctxt->mode == X86EMUL_MODE_PROT64)
3167 val = ctxt->src.val & ~0ULL;
3168 else
3169 val = ctxt->src.val & ~0U;
3170
3171 /* #UD condition is already handled. */
3172 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3173 return emulate_gp(ctxt, 0);
3174
3175 /* Disable writeback. */
3176 ctxt->dst.type = OP_NONE;
3177 return X86EMUL_CONTINUE;
3178}
3179
e1e210b0
TY		 3180static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3181{
3182 u64 msr_data;
3183
dd856efa
AK		 3184 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3185 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3186 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3187 return emulate_gp(ctxt, 0);
3188
3189 return X86EMUL_CONTINUE;
3190}
3191
3192static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3193{
3194 u64 msr_data;
3195
dd856efa 3196 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3197 return emulate_gp(ctxt, 0);
3198
dd856efa
AK		 3199 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3200 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3201 return X86EMUL_CONTINUE;
3202}
3203
1bd5f469
TY		 3204static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3205{
9dac77fa 3206 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3207 return emulate_ud(ctxt);
3208
9dac77fa 3209 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3210 return X86EMUL_CONTINUE;
3211}
3212
3213static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3214{
9dac77fa 3215 u16 sel = ctxt->src.val;
1bd5f469 3216
9dac77fa 3217 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3218 return emulate_ud(ctxt);
3219
9dac77fa 3220 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3221 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3222
3223 /* Disable writeback. */
9dac77fa
AK		 3224 ctxt->dst.type = OP_NONE;
3225 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3226}
3227
a14e579f
AK		 3228static int em_lldt(struct x86_emulate_ctxt *ctxt)
3229{
3230 u16 sel = ctxt->src.val;
3231
3232 /* Disable writeback. */
3233 ctxt->dst.type = OP_NONE;
3234 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3235}
3236
80890006
AK		 3237static int em_ltr(struct x86_emulate_ctxt *ctxt)
3238{
3239 u16 sel = ctxt->src.val;
3240
3241 /* Disable writeback. */
3242 ctxt->dst.type = OP_NONE;
3243 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3244}
3245
38503911
AK		 3246static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3247{
9fa088f4
AK		 3248 int rc;
3249 ulong linear;
3250
9dac77fa 3251 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3252 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3253 ctxt->ops->invlpg(ctxt, linear);
38503911 3254 /* Disable writeback. */
9dac77fa 3255 ctxt->dst.type = OP_NONE;
38503911
AK		 3256 return X86EMUL_CONTINUE;
3257}
3258
2d04a05b
AK		 3259static int em_clts(struct x86_emulate_ctxt *ctxt)
3260{
3261 ulong cr0;
3262
3263 cr0 = ctxt->ops->get_cr(ctxt, 0);
3264 cr0 &= ~X86_CR0_TS;
3265 ctxt->ops->set_cr(ctxt, 0, cr0);
3266 return X86EMUL_CONTINUE;
3267}
3268
26d05cc7
AK		 3269static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3270{
0f54a321 3271 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3272
26d05cc7
AK		 3273 if (rc != X86EMUL_CONTINUE)
3274 return rc;
3275
3276 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3277 ctxt->_eip = ctxt->eip;
26d05cc7 3278 /* Disable writeback. */
9dac77fa 3279 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3280 return X86EMUL_CONTINUE;
3281}
3282
96051572
AK		 3283static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3284 void (*get)(struct x86_emulate_ctxt *ctxt,
3285 struct desc_ptr *ptr))
3286{
3287 struct desc_ptr desc_ptr;
3288
3289 if (ctxt->mode == X86EMUL_MODE_PROT64)
3290 ctxt->op_bytes = 8;
3291 get(ctxt, &desc_ptr);
3292 if (ctxt->op_bytes == 2) {
3293 ctxt->op_bytes = 4;
3294 desc_ptr.address &= 0x00ffffff;
3295 }
3296 /* Disable writeback. */
3297 ctxt->dst.type = OP_NONE;
3298 return segmented_write(ctxt, ctxt->dst.addr.mem,
3299 &desc_ptr, 2 + ctxt->op_bytes);
3300}
3301
3302static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3303{
3304 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3305}
3306
3307static int em_sidt(struct x86_emulate_ctxt *ctxt)
3308{
3309 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3310}
3311
26d05cc7
AK		 3312static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3313{
26d05cc7
AK		 3314 struct desc_ptr desc_ptr;
3315 int rc;
3316
510425ff
AK		 3317 if (ctxt->mode == X86EMUL_MODE_PROT64)
3318 ctxt->op_bytes = 8;
9dac77fa 3319 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3320 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3321 ctxt->op_bytes);
26d05cc7
AK		 3322 if (rc != X86EMUL_CONTINUE)
3323 return rc;
3324 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3325 /* Disable writeback. */
9dac77fa 3326 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3327 return X86EMUL_CONTINUE;
3328}
3329
5ef39c71 3330static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3331{
26d05cc7
AK		 3332 int rc;
3333
5ef39c71
AK		 3334 rc = ctxt->ops->fix_hypercall(ctxt);
3335
26d05cc7 3336 /* Disable writeback. */
9dac77fa 3337 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3338 return rc;
3339}
3340
3341static int em_lidt(struct x86_emulate_ctxt *ctxt)
3342{
26d05cc7
AK		 3343 struct desc_ptr desc_ptr;
3344 int rc;
3345
510425ff
AK		 3346 if (ctxt->mode == X86EMUL_MODE_PROT64)
3347 ctxt->op_bytes = 8;
9dac77fa 3348 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3349 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3350 ctxt->op_bytes);
26d05cc7
AK		 3351 if (rc != X86EMUL_CONTINUE)
3352 return rc;
3353 ctxt->ops->set_idt(ctxt, &desc_ptr);
3354 /* Disable writeback. */
9dac77fa 3355 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3356 return X86EMUL_CONTINUE;
3357}
3358
3359static int em_smsw(struct x86_emulate_ctxt *ctxt)
3360{
32e94d06
NA		 3361 if (ctxt->dst.type == OP_MEM)
3362 ctxt->dst.bytes = 2;
9dac77fa 3363 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3364 return X86EMUL_CONTINUE;
3365}
3366
3367static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3368{
26d05cc7 3369 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3370 | (ctxt->src.val & 0x0f));
3371 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3372 return X86EMUL_CONTINUE;
3373}
3374
d06e03ad
TY		 3375static int em_loop(struct x86_emulate_ctxt *ctxt)
3376{
234f3ce4
NA		 3377 int rc = X86EMUL_CONTINUE;
3378
dd856efa
AK		 3379 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3380 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3381 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3382 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3383
234f3ce4 3384 return rc;
d06e03ad
TY		 3385}
3386
3387static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3388{
234f3ce4
NA		 3389 int rc = X86EMUL_CONTINUE;
3390
dd856efa 3391 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3392 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3393
234f3ce4 3394 return rc;
d06e03ad
TY		 3395}
3396
d7841a4b
TY		 3397static int em_in(struct x86_emulate_ctxt *ctxt)
3398{
3399 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3400 &ctxt->dst.val))
3401 return X86EMUL_IO_NEEDED;
3402
3403 return X86EMUL_CONTINUE;
3404}
3405
3406static int em_out(struct x86_emulate_ctxt *ctxt)
3407{
3408 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3409 &ctxt->src.val, 1);
3410 /* Disable writeback. */
3411 ctxt->dst.type = OP_NONE;
3412 return X86EMUL_CONTINUE;
3413}
3414
f411e6cd
TY		 3415static int em_cli(struct x86_emulate_ctxt *ctxt)
3416{
3417 if (emulator_bad_iopl(ctxt))
3418 return emulate_gp(ctxt, 0);
3419
3420 ctxt->eflags &= ~X86_EFLAGS_IF;
3421 return X86EMUL_CONTINUE;
3422}
3423
3424static int em_sti(struct x86_emulate_ctxt *ctxt)
3425{
3426 if (emulator_bad_iopl(ctxt))
3427 return emulate_gp(ctxt, 0);
3428
3429 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3430 ctxt->eflags |= X86_EFLAGS_IF;
3431 return X86EMUL_CONTINUE;
3432}
3433
6d6eede4
AK		 3434static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3435{
3436 u32 eax, ebx, ecx, edx;
3437
dd856efa
AK		 3438 eax = reg_read(ctxt, VCPU_REGS_RAX);
3439 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3440 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3441 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3442 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3443 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3444 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3445 return X86EMUL_CONTINUE;
3446}
3447
98f73630
PB		 3448static int em_sahf(struct x86_emulate_ctxt *ctxt)
3449{
3450 u32 flags;
3451
3452 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3453 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3454
3455 ctxt->eflags &= ~0xffUL;
3456 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3457 return X86EMUL_CONTINUE;
3458}
3459
2dd7caa0
AK		 3460static int em_lahf(struct x86_emulate_ctxt *ctxt)
3461{
dd856efa
AK		 3462 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3463 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3464 return X86EMUL_CONTINUE;
3465}
3466
9299836e
AK		 3467static int em_bswap(struct x86_emulate_ctxt *ctxt)
3468{
3469 switch (ctxt->op_bytes) {
3470#ifdef CONFIG_X86_64
3471 case 8:
3472 asm("bswap %0" : "+r"(ctxt->dst.val));
3473 break;
3474#endif
3475 default:
3476 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3477 break;
3478 }
3479 return X86EMUL_CONTINUE;
3480}
3481
13e457e0
NA		 3482static int em_clflush(struct x86_emulate_ctxt *ctxt)
3483{
3484 /* emulating clflush regardless of cpuid */
3485 return X86EMUL_CONTINUE;
3486}
3487
cfec82cb
JR		 3488static bool valid_cr(int nr)
3489{
3490 switch (nr) {
3491 case 0:
3492 case 2 ... 4:
3493 case 8:
3494 return true;
3495 default:
3496 return false;
3497 }
3498}
3499
3500static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3501{
9dac77fa 3502 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3503 return emulate_ud(ctxt);
3504
3505 return X86EMUL_CONTINUE;
3506}
3507
3508static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3509{
9dac77fa
AK		 3510 u64 new_val = ctxt->src.val64;
3511 int cr = ctxt->modrm_reg;
c2ad2bb3 3512 u64 efer = 0;
cfec82cb
JR		 3513
3514 static u64 cr_reserved_bits[] = {
3515 0xffffffff00000000ULL,
3516 0, 0, 0, /* CR3 checked later */
3517 CR4_RESERVED_BITS,
3518 0, 0, 0,
3519 CR8_RESERVED_BITS,
3520 };
3521
3522 if (!valid_cr(cr))
3523 return emulate_ud(ctxt);
3524
3525 if (new_val & cr_reserved_bits[cr])
3526 return emulate_gp(ctxt, 0);
3527
3528 switch (cr) {
3529 case 0: {
c2ad2bb3 3530 u64 cr4;
cfec82cb
JR		 3531 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3532 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3533 return emulate_gp(ctxt, 0);
3534
717746e3
AK		 3535 cr4 = ctxt->ops->get_cr(ctxt, 4);
3536 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3537
3538 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3539 !(cr4 & X86_CR4_PAE))
3540 return emulate_gp(ctxt, 0);
3541
3542 break;
3543 }
3544 case 3: {
3545 u64 rsvd = 0;
3546
c2ad2bb3
AK		 3547 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3548 if (efer & EFER_LMA)
cfec82cb 3549 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3550
3551 if (new_val & rsvd)
3552 return emulate_gp(ctxt, 0);
3553
3554 break;
3555 }
3556 case 4: {
717746e3 3557 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3558
3559 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3560 return emulate_gp(ctxt, 0);
3561
3562 break;
3563 }
3564 }
3565
3566 return X86EMUL_CONTINUE;
3567}
3568
3b88e41a
JR		 3569static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3570{
3571 unsigned long dr7;
3572
717746e3 3573 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3574
3575 /* Check if DR7.Global_Enable is set */
3576 return dr7 & (1 << 13);
3577}
3578
3579static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3580{
9dac77fa 3581 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3582 u64 cr4;
3583
3584 if (dr > 7)
3585 return emulate_ud(ctxt);
3586
717746e3 3587 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3588 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3589 return emulate_ud(ctxt);
3590
6d2a0526
NA		 3591 if (check_dr7_gd(ctxt)) {
3592 ulong dr6;
3593
3594 ctxt->ops->get_dr(ctxt, 6, &dr6);
3595 dr6 &= ~15;
3596 dr6 |= DR6_BD | DR6_RTM;
3597 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3598 return emulate_db(ctxt);
6d2a0526 3599 }
3b88e41a
JR		 3600
3601 return X86EMUL_CONTINUE;
3602}
3603
3604static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3605{
9dac77fa
AK		 3606 u64 new_val = ctxt->src.val64;
3607 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3608
3609 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3610 return emulate_gp(ctxt, 0);
3611
3612 return check_dr_read(ctxt);
3613}
3614
01de8b09
JR		 3615static int check_svme(struct x86_emulate_ctxt *ctxt)
3616{
3617 u64 efer;
3618
717746e3 3619 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3620
3621 if (!(efer & EFER_SVME))
3622 return emulate_ud(ctxt);
3623
3624 return X86EMUL_CONTINUE;
3625}
3626
3627static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3628{
dd856efa 3629 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3630
3631 /* Valid physical address? */
d4224449 3632 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3633 return emulate_gp(ctxt, 0);
3634
3635 return check_svme(ctxt);
3636}
3637
d7eb8203
JR		 3638static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3639{
717746e3 3640 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3641
717746e3 3642 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3643 return emulate_ud(ctxt);
3644
3645 return X86EMUL_CONTINUE;
3646}
3647
8061252e
JR		 3648static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3649{
717746e3 3650 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3651 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3652
717746e3 3653 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3654 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3655 return emulate_gp(ctxt, 0);
3656
3657 return X86EMUL_CONTINUE;
3658}
3659
f6511935
JR		 3660static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3661{
9dac77fa
AK		 3662 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3663 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3664 return emulate_gp(ctxt, 0);
3665
3666 return X86EMUL_CONTINUE;
3667}
3668
3669static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3670{
9dac77fa
AK		 3671 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3672 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3673 return emulate_gp(ctxt, 0);
3674
3675 return X86EMUL_CONTINUE;
3676}
3677
73fba5f4 3678#define D(_y) { .flags = (_y) }
d40a6898
PB		 3679#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3680#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3681 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3682#define N D(NotImpl)
01de8b09 3683#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3684#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3685#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3686#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3687#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3688#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3689#define II(_f, _e, _i) \
d40a6898 3690 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3691#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3692 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3693 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3694#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3695
8d8f4e9f 3696#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3697#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3698#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3699#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3700#define I2bvIP(_f, _e, _i, _p) \
3701 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3702
fb864fbc
AK		 3703#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3704 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3705 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3706
0f54a321
NA		 3707static const struct opcode group7_rm0[] = {
3708 N,
3709 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3710 N, N, N, N, N, N,
3711};
3712
fd0a0d82 3713static const struct opcode group7_rm1[] = {
1c2545be
TY		 3714 DI(SrcNone | Priv, monitor),
3715 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3716 N, N, N, N, N, N,
3717};
3718
fd0a0d82 3719static const struct opcode group7_rm3[] = {
1c2545be 3720 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3721 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3722 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3723 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3724 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3725 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3726 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3727 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3728};
6230f7fc 3729
fd0a0d82 3730static const struct opcode group7_rm7[] = {
d7eb8203 3731 N,
1c2545be 3732 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3733 N, N, N, N, N, N,
3734};
d67fc27a 3735
fd0a0d82 3736static const struct opcode group1[] = {
fb864fbc
AK		 3737 F(Lock, em_add),
3738 F(Lock | PageTable, em_or),
3739 F(Lock, em_adc),
3740 F(Lock, em_sbb),
3741 F(Lock | PageTable, em_and),
3742 F(Lock, em_sub),
3743 F(Lock, em_xor),
3744 F(NoWrite, em_cmp),
73fba5f4
AK		 3745};
3746
fd0a0d82 3747static const struct opcode group1A[] = {
1c2545be 3748 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3749};
3750
007a3b54
AK		 3751static const struct opcode group2[] = {
3752 F(DstMem | ModRM, em_rol),
3753 F(DstMem | ModRM, em_ror),
3754 F(DstMem | ModRM, em_rcl),
3755 F(DstMem | ModRM, em_rcr),
3756 F(DstMem | ModRM, em_shl),
3757 F(DstMem | ModRM, em_shr),
3758 F(DstMem | ModRM, em_shl),
3759 F(DstMem | ModRM, em_sar),
3760};
3761
fd0a0d82 3762static const struct opcode group3[] = {
fb864fbc
AK		 3763 F(DstMem | SrcImm | NoWrite, em_test),
3764 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3765 F(DstMem | SrcNone | Lock, em_not),
3766 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3767 F(DstXacc | Src2Mem, em_mul_ex),
3768 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3769 F(DstXacc | Src2Mem, em_div_ex),
3770 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3771};
3772
fd0a0d82 3773static const struct opcode group4[] = {
95413dc4
AK		 3774 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3775 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3776 N, N, N, N, N, N,
3777};
3778
fd0a0d82 3779static const struct opcode group5[] = {
95413dc4
AK		 3780 F(DstMem | SrcNone | Lock, em_inc),
3781 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3782 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3783 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3784 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3785 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3786 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3787};
3788
fd0a0d82 3789static const struct opcode group6[] = {
1c2545be
TY		 3790 DI(Prot, sldt),
3791 DI(Prot, str),
a14e579f 3792 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3793 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3794 N, N, N, N,
3795};
3796
fd0a0d82 3797static const struct group_dual group7 = { {
606b1c3e
NA		 3798 II(Mov | DstMem, em_sgdt, sgdt),
3799 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3800 II(SrcMem | Priv, em_lgdt, lgdt),
3801 II(SrcMem | Priv, em_lidt, lidt),
3802 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3803 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3804 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3805}, {
0f54a321 3806 EXT(0, group7_rm0),
5ef39c71 3807 EXT(0, group7_rm1),
01de8b09 3808 N, EXT(0, group7_rm3),
1c2545be
TY		 3809 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3810 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3811 EXT(0, group7_rm7),
73fba5f4
AK		 3812} };
3813
fd0a0d82 3814static const struct opcode group8[] = {
73fba5f4 3815 N, N, N, N,
11c363ba
AK		 3816 F(DstMem | SrcImmByte | NoWrite, em_bt),
3817 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3818 F(DstMem | SrcImmByte | Lock, em_btr),
3819 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3820};
3821
fd0a0d82 3822static const struct group_dual group9 = { {
1c2545be 3823 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3824}, {
3825 N, N, N, N, N, N, N, N,
3826} };
3827
fd0a0d82 3828static const struct opcode group11[] = {
1c2545be 3829 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3830 X7(D(Undefined)),
a4d4a7c1
AK		 3831};
3832
13e457e0 3833static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3834 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3835};
3836
3837static const struct group_dual group15 = { {
3838 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3839}, {
3840 N, N, N, N, N, N, N, N,
3841} };
3842
fd0a0d82 3843static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3844 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3845};
3846
d5b77069
PB		 3847static const struct gprefix pfx_0f_2b = {
3848 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3849};
3850
27ce8258 3851static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3852 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3853};
3854
0a37027e
AW		 3855static const struct gprefix pfx_0f_e7 = {
3856 N, I(Sse, em_mov), N, N,
3857};
3858
045a282c
GN		 3859static const struct escape escape_d9 = { {
3860 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3861}, {
3862 /* 0xC0 - 0xC7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xC8 - 0xCF */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xD0 - 0xC7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xD8 - 0xDF */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xE0 - 0xE7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xE8 - 0xEF */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xF0 - 0xF7 */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xF8 - 0xFF */
3877 N, N, N, N, N, N, N, N,
3878} };
3879
3880static const struct escape escape_db = { {
3881 N, N, N, N, N, N, N, N,
3882}, {
3883 /* 0xC0 - 0xC7 */
3884 N, N, N, N, N, N, N, N,
3885 /* 0xC8 - 0xCF */
3886 N, N, N, N, N, N, N, N,
3887 /* 0xD0 - 0xC7 */
3888 N, N, N, N, N, N, N, N,
3889 /* 0xD8 - 0xDF */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xE0 - 0xE7 */
3892 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3893 /* 0xE8 - 0xEF */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xF0 - 0xF7 */
3896 N, N, N, N, N, N, N, N,
3897 /* 0xF8 - 0xFF */
3898 N, N, N, N, N, N, N, N,
3899} };
3900
3901static const struct escape escape_dd = { {
3902 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3903}, {
3904 /* 0xC0 - 0xC7 */
3905 N, N, N, N, N, N, N, N,
3906 /* 0xC8 - 0xCF */
3907 N, N, N, N, N, N, N, N,
3908 /* 0xD0 - 0xC7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xD8 - 0xDF */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xE0 - 0xE7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xE8 - 0xEF */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xF0 - 0xF7 */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xF8 - 0xFF */
3919 N, N, N, N, N, N, N, N,
3920} };
3921
fd0a0d82 3922static const struct opcode opcode_table[256] = {
73fba5f4 3923 /* 0x00 - 0x07 */
fb864fbc 3924 F6ALU(Lock, em_add),
1cd196ea
AK		 3925 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3926 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3927 /* 0x08 - 0x0F */
fb864fbc 3928 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3929 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3930 N,
73fba5f4 3931 /* 0x10 - 0x17 */
fb864fbc 3932 F6ALU(Lock, em_adc),
1cd196ea
AK		 3933 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3934 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3935 /* 0x18 - 0x1F */
fb864fbc 3936 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3937 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3938 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3939 /* 0x20 - 0x27 */
fb864fbc 3940 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3941 /* 0x28 - 0x2F */
fb864fbc 3942 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3943 /* 0x30 - 0x37 */
fb864fbc 3944 F6ALU(Lock, em_xor), N, N,
73fba5f4 3945 /* 0x38 - 0x3F */
fb864fbc 3946 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3947 /* 0x40 - 0x4F */
95413dc4 3948 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3949 /* 0x50 - 0x57 */
63540382 3950 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3951 /* 0x58 - 0x5F */
c54fe504 3952 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3953 /* 0x60 - 0x67 */
b96a7fad
TY		 3954 I(ImplicitOps | Stack | No64, em_pusha),
3955 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3956 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3957 N, N, N, N,
3958 /* 0x68 - 0x6F */
d46164db
AK		 3959 I(SrcImm | Mov | Stack, em_push),
3960 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3961 I(SrcImmByte | Mov | Stack, em_push),
3962 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3963 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3964 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3965 /* 0x70 - 0x7F */
58b7075d 3966 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3967 /* 0x80 - 0x87 */
1c2545be
TY		 3968 G(ByteOp | DstMem | SrcImm, group1),
3969 G(DstMem | SrcImm, group1),
3970 G(ByteOp | DstMem | SrcImm | No64, group1),
3971 G(DstMem | SrcImmByte, group1),
fb864fbc 3972 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3973 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3974 /* 0x88 - 0x8F */
d5ae7ce8 3975 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3976 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3977 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3978 D(ModRM | SrcMem | NoAccess | DstReg),
3979 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3980 G(0, group1A),
73fba5f4 3981 /* 0x90 - 0x97 */
bf608f88 3982 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3983 /* 0x98 - 0x9F */
61429142 3984 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3985 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3986 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3987 II(ImplicitOps | Stack, em_popf, popf),
3988 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3989 /* 0xA0 - 0xA7 */
b9eac5f4 3990 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3991 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3992 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3993 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3994 /* 0xA8 - 0xAF */
fb864fbc 3995 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3996 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3997 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3998 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3999 /* 0xB0 - 0xB7 */
b9eac5f4 4000 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4001 /* 0xB8 - 0xBF */
5e2c6883 4002 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4003 /* 0xC0 - 0xC7 */
007a3b54 4004 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4005 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4006 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4007 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4008 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4009 G(ByteOp, group11), G(0, group11),
73fba5f4 4010 /* 0xC8 - 0xCF */
612e89f0 4011 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4012 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4013 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4014 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4015 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4016 /* 0xD0 - 0xD7 */
007a3b54
AK		 4017 G(Src2One | ByteOp, group2), G(Src2One, group2),
4018 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4019 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4020 I(DstAcc | SrcImmUByte | No64, em_aad),
4021 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4022 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4023 /* 0xD8 - 0xDF */
045a282c 4024 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4025 /* 0xE0 - 0xE7 */
58b7075d
NA		 4026 X3(I(SrcImmByte | NearBranch, em_loop)),
4027 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4028 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4029 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4030 /* 0xE8 - 0xEF */
58b7075d
NA		 4031 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4032 I(SrcImmFAddr | No64, em_jmp_far),
4033 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4034 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4035 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4036 /* 0xF0 - 0xF7 */
bf608f88 4037 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4038 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4039 G(ByteOp, group3), G(0, group3),
73fba5f4 4040 /* 0xF8 - 0xFF */
f411e6cd
TY		 4041 D(ImplicitOps), D(ImplicitOps),
4042 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4043 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4044};
4045
fd0a0d82 4046static const struct opcode twobyte_table[256] = {
73fba5f4 4047 /* 0x00 - 0x0F */
dee6bb70 4048 G(0, group6), GD(0, &group7), N, N,
b51e974f 4049 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4050 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4051 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4052 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4053 /* 0x10 - 0x1F */
103f98ea 4054 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4055 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4056 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4057 /* 0x20 - 0x2F */
9b88ae99
NA		 4058 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4059 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4060 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4061 check_cr_write),
4062 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4063 check_dr_write),
73fba5f4 4064 N, N, N, N,
27ce8258
IM		 4065 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4066 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4067 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4068 N, N, N, N,
73fba5f4 4069 /* 0x30 - 0x3F */
e1e210b0 4070 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4071 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4072 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4073 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4074 I(ImplicitOps | EmulateOnUD, em_sysenter),
4075 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4076 N, N,
73fba5f4
AK		 4077 N, N, N, N, N, N, N, N,
4078 /* 0x40 - 0x4F */
140bad89 4079 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4080 /* 0x50 - 0x5F */
4081 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4082 /* 0x60 - 0x6F */
aa97bb48
AK		 4083 N, N, N, N,
4084 N, N, N, N,
4085 N, N, N, N,
4086 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4087 /* 0x70 - 0x7F */
aa97bb48
AK		 4088 N, N, N, N,
4089 N, N, N, N,
4090 N, N, N, N,
4091 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4092 /* 0x80 - 0x8F */
58b7075d 4093 X16(D(SrcImm | NearBranch)),
73fba5f4 4094 /* 0x90 - 0x9F */
ee45b58e 4095 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4096 /* 0xA0 - 0xA7 */
1cd196ea 4097 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4098 II(ImplicitOps, em_cpuid, cpuid),
4099 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4100 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4101 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4102 /* 0xA8 - 0xAF */
1cd196ea 4103 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4104 DI(ImplicitOps, rsm),
11c363ba 4105 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4106 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4107 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4108 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4109 /* 0xB0 - 0xB7 */
e940b5c2 4110 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4111 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4112 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4113 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4114 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4115 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4116 /* 0xB8 - 0xBF */
4117 N, N,
ce7faab2 4118 G(BitOp, group8),
11c363ba
AK		 4119 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4120 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4121 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4122 /* 0xC0 - 0xC7 */
e47a5f5f 4123 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 4124 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4125 N, N, N, GD(0, &group9),
9299836e
AK		 4126 /* 0xC8 - 0xCF */
4127 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4128 /* 0xD0 - 0xDF */
4129 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4130 /* 0xE0 - 0xEF */
0a37027e
AW		 4131 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4132 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4133 /* 0xF0 - 0xFF */
4134 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4135};
4136
0bc5eedb 4137static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4138 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4139};
4140
4141static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4142 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4143};
4144
4145/*
4146 * Insns below are selected by the prefix which indexed by the third opcode
4147 * byte.
4148 */
4149static const struct opcode opcode_map_0f_38[256] = {
4150 /* 0x00 - 0x7f */
4151 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4152 /* 0x80 - 0xef */
4153 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4154 /* 0xf0 - 0xf1 */
4155 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4156 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4157 /* 0xf2 - 0xff */
4158 N, N, X4(N), X8(N)
0bc5eedb
BP		 4159};
4160
73fba5f4
AK		 4161#undef D
4162#undef N
4163#undef G
4164#undef GD
4165#undef I
aa97bb48 4166#undef GP
01de8b09 4167#undef EXT
73fba5f4 4168
8d8f4e9f 4169#undef D2bv
f6511935 4170#undef D2bvIP
8d8f4e9f 4171#undef I2bv
d7841a4b 4172#undef I2bvIP
d67fc27a 4173#undef I6ALU
8d8f4e9f 4174
9dac77fa 4175static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4176{
4177 unsigned size;
4178
9dac77fa 4179 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4180 if (size == 8)
4181 size = 4;
4182 return size;
4183}
4184
4185static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4186 unsigned size, bool sign_extension)
4187{
39f21ee5
AK		 4188 int rc = X86EMUL_CONTINUE;
4189
4190 op->type = OP_IMM;
4191 op->bytes = size;
9dac77fa 4192 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4193 /* NB. Immediates are sign-extended as necessary. */
4194 switch (op->bytes) {
4195 case 1:
e85a1085 4196 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4197 break;
4198 case 2:
e85a1085 4199 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4200 break;
4201 case 4:
e85a1085 4202 op->val = insn_fetch(s32, ctxt);
39f21ee5 4203 break;
5e2c6883
NA		 4204 case 8:
4205 op->val = insn_fetch(s64, ctxt);
4206 break;
39f21ee5
AK		 4207 }
4208 if (!sign_extension) {
4209 switch (op->bytes) {
4210 case 1:
4211 op->val &= 0xff;
4212 break;
4213 case 2:
4214 op->val &= 0xffff;
4215 break;
4216 case 4:
4217 op->val &= 0xffffffff;
4218 break;
4219 }
4220 }
4221done:
4222 return rc;
4223}
4224
a9945549
AK		 4225static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4226 unsigned d)
4227{
4228 int rc = X86EMUL_CONTINUE;
4229
4230 switch (d) {
4231 case OpReg:
2adb5ad9 4232 decode_register_operand(ctxt, op);
a9945549
AK		 4233 break;
4234 case OpImmUByte:
608aabe3 4235 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4236 break;
4237 case OpMem:
41ddf978 4238 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4239 mem_common:
4240 *op = ctxt->memop;
4241 ctxt->memopp = op;
96888977 4242 if (ctxt->d & BitOp)
a9945549
AK		 4243 fetch_bit_operand(ctxt);
4244 op->orig_val = op->val;
4245 break;
41ddf978 4246 case OpMem64:
aaa05f24 4247 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4248 goto mem_common;
a9945549
AK		 4249 case OpAcc:
4250 op->type = OP_REG;
4251 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4252 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4253 fetch_register_operand(op);
4254 op->orig_val = op->val;
4255 break;
820207c8
AK		 4256 case OpAccLo:
4257 op->type = OP_REG;
4258 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4259 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4260 fetch_register_operand(op);
4261 op->orig_val = op->val;
4262 break;
4263 case OpAccHi:
4264 if (ctxt->d & ByteOp) {
4265 op->type = OP_NONE;
4266 break;
4267 }
4268 op->type = OP_REG;
4269 op->bytes = ctxt->op_bytes;
4270 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4271 fetch_register_operand(op);
4272 op->orig_val = op->val;
4273 break;
a9945549
AK		 4274 case OpDI:
4275 op->type = OP_MEM;
4276 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4277 op->addr.mem.ea =
dd856efa 4278 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4279 op->addr.mem.seg = VCPU_SREG_ES;
4280 op->val = 0;
b3356bf0 4281 op->count = 1;
a9945549
AK		 4282 break;
4283 case OpDX:
4284 op->type = OP_REG;
4285 op->bytes = 2;
dd856efa 4286 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4287 fetch_register_operand(op);
4288 break;
4dd6a57d
AK		 4289 case OpCL:
4290 op->bytes = 1;
dd856efa 4291 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4292 break;
4293 case OpImmByte:
4294 rc = decode_imm(ctxt, op, 1, true);
4295 break;
4296 case OpOne:
4297 op->bytes = 1;
4298 op->val = 1;
4299 break;
4300 case OpImm:
4301 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4302 break;
5e2c6883
NA		 4303 case OpImm64:
4304 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4305 break;
28867cee
AK		 4306 case OpMem8:
4307 ctxt->memop.bytes = 1;
660696d1 4308 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4309 ctxt->memop.addr.reg = decode_register(ctxt,
4310 ctxt->modrm_rm, true);
660696d1
GN		 4311 fetch_register_operand(&ctxt->memop);
4312 }
28867cee 4313 goto mem_common;
0fe59128
AK		 4314 case OpMem16:
4315 ctxt->memop.bytes = 2;
4316 goto mem_common;
4317 case OpMem32:
4318 ctxt->memop.bytes = 4;
4319 goto mem_common;
4320 case OpImmU16:
4321 rc = decode_imm(ctxt, op, 2, false);
4322 break;
4323 case OpImmU:
4324 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4325 break;
4326 case OpSI:
4327 op->type = OP_MEM;
4328 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4329 op->addr.mem.ea =
dd856efa 4330 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4331 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4332 op->val = 0;
b3356bf0 4333 op->count = 1;
0fe59128 4334 break;
7fa57952
PB		 4335 case OpXLat:
4336 op->type = OP_MEM;
4337 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4338 op->addr.mem.ea =
4339 register_address(ctxt,
4340 reg_read(ctxt, VCPU_REGS_RBX) +
4341 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4342 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4343 op->val = 0;
4344 break;
0fe59128
AK		 4345 case OpImmFAddr:
4346 op->type = OP_IMM;
4347 op->addr.mem.ea = ctxt->_eip;
4348 op->bytes = ctxt->op_bytes + 2;
4349 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4350 break;
4351 case OpMemFAddr:
4352 ctxt->memop.bytes = ctxt->op_bytes + 2;
4353 goto mem_common;
c191a7a0
AK		 4354 case OpES:
4355 op->val = VCPU_SREG_ES;
4356 break;
4357 case OpCS:
4358 op->val = VCPU_SREG_CS;
4359 break;
4360 case OpSS:
4361 op->val = VCPU_SREG_SS;
4362 break;
4363 case OpDS:
4364 op->val = VCPU_SREG_DS;
4365 break;
4366 case OpFS:
4367 op->val = VCPU_SREG_FS;
4368 break;
4369 case OpGS:
4370 op->val = VCPU_SREG_GS;
4371 break;
a9945549
AK		 4372 case OpImplicit:
4373 /* Special instructions do their own operand decoding. */
4374 default:
4375 op->type = OP_NONE; /* Disable writeback. */
4376 break;
4377 }
4378
4379done:
4380 return rc;
4381}
4382
ef5d75cc 4383int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4384{
dde7e6d1
AK		 4385 int rc = X86EMUL_CONTINUE;
4386 int mode = ctxt->mode;
46561646 4387 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4388 bool op_prefix = false;
573e80fe 4389 bool has_seg_override = false;
46561646 4390 struct opcode opcode;
dde7e6d1 4391
f09ed83e
AK		 4392 ctxt->memop.type = OP_NONE;
4393 ctxt->memopp = NULL;
9dac77fa 4394 ctxt->_eip = ctxt->eip;
17052f16
PB		 4395 ctxt->fetch.ptr = ctxt->fetch.data;
4396 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4397 ctxt->opcode_len = 1;
dc25e89e 4398 if (insn_len > 0)
9dac77fa 4399 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4400 else {
9506d57d 4401 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4402 if (rc != X86EMUL_CONTINUE)
4403 return rc;
4404 }
dde7e6d1
AK		 4405
4406 switch (mode) {
4407 case X86EMUL_MODE_REAL:
4408 case X86EMUL_MODE_VM86:
4409 case X86EMUL_MODE_PROT16:
4410 def_op_bytes = def_ad_bytes = 2;
4411 break;
4412 case X86EMUL_MODE_PROT32:
4413 def_op_bytes = def_ad_bytes = 4;
4414 break;
4415#ifdef CONFIG_X86_64
4416 case X86EMUL_MODE_PROT64:
4417 def_op_bytes = 4;
4418 def_ad_bytes = 8;
4419 break;
4420#endif
4421 default:
1d2887e2 4422 return EMULATION_FAILED;
dde7e6d1
AK		 4423 }
4424
9dac77fa
AK		 4425 ctxt->op_bytes = def_op_bytes;
4426 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4427
4428 /* Legacy prefixes. */
4429 for (;;) {
e85a1085 4430 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4431 case 0x66: /* operand-size override */
0d7cdee8 4432 op_prefix = true;
dde7e6d1 4433 /* switch between 2/4 bytes */
9dac77fa 4434 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4435 break;
4436 case 0x67: /* address-size override */
4437 if (mode == X86EMUL_MODE_PROT64)
4438 /* switch between 4/8 bytes */
9dac77fa 4439 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4440 else
4441 /* switch between 2/4 bytes */
9dac77fa 4442 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4443 break;
4444 case 0x26: /* ES override */
4445 case 0x2e: /* CS override */
4446 case 0x36: /* SS override */
4447 case 0x3e: /* DS override */
573e80fe
BD		 4448 has_seg_override = true;
4449 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4450 break;
4451 case 0x64: /* FS override */
4452 case 0x65: /* GS override */
573e80fe
BD		 4453 has_seg_override = true;
4454 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4455 break;
4456 case 0x40 ... 0x4f: /* REX */
4457 if (mode != X86EMUL_MODE_PROT64)
4458 goto done_prefixes;
9dac77fa 4459 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4460 continue;
4461 case 0xf0: /* LOCK */
9dac77fa 4462 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4463 break;
4464 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4465 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4466 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4467 break;
4468 default:
4469 goto done_prefixes;
4470 }
4471
4472 /* Any legacy prefix after a REX prefix nullifies its effect. */
4473
9dac77fa 4474 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4475 }
4476
4477done_prefixes:
4478
4479 /* REX prefix. */
9dac77fa
AK		 4480 if (ctxt->rex_prefix & 8)
4481 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4482
4483 /* Opcode byte(s). */
9dac77fa 4484 opcode = opcode_table[ctxt->b];
d3ad6243 4485 /* Two-byte opcode? */
9dac77fa 4486 if (ctxt->b == 0x0f) {
1ce19dc1 4487 ctxt->opcode_len = 2;
e85a1085 4488 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4489 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4490
4491 /* 0F_38 opcode map */
4492 if (ctxt->b == 0x38) {
4493 ctxt->opcode_len = 3;
4494 ctxt->b = insn_fetch(u8, ctxt);
4495 opcode = opcode_map_0f_38[ctxt->b];
4496 }
dde7e6d1 4497 }
9dac77fa 4498 ctxt->d = opcode.flags;
dde7e6d1 4499
9f4260e7
TY		 4500 if (ctxt->d & ModRM)
4501 ctxt->modrm = insn_fetch(u8, ctxt);
4502
7fe864dc
NA		 4503 /* vex-prefix instructions are not implemented */
4504 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4505 (mode == X86EMUL_MODE_PROT64 ||
4506 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4507 ctxt->d = NotImpl;
4508 }
4509
9dac77fa
AK		 4510 while (ctxt->d & GroupMask) {
4511 switch (ctxt->d & GroupMask) {
46561646 4512 case Group:
9dac77fa 4513 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4514 opcode = opcode.u.group[goffset];
4515 break;
4516 case GroupDual:
9dac77fa
AK		 4517 goffset = (ctxt->modrm >> 3) & 7;
4518 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4519 opcode = opcode.u.gdual->mod3[goffset];
4520 else
4521 opcode = opcode.u.gdual->mod012[goffset];
4522 break;
4523 case RMExt:
9dac77fa 4524 goffset = ctxt->modrm & 7;
01de8b09 4525 opcode = opcode.u.group[goffset];
46561646
AK		 4526 break;
4527 case Prefix:
9dac77fa 4528 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4529 return EMULATION_FAILED;
9dac77fa 4530 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4531 switch (simd_prefix) {
4532 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4533 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4534 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4535 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4536 }
4537 break;
045a282c
GN		 4538 case Escape:
4539 if (ctxt->modrm > 0xbf)
4540 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4541 else
4542 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4543 break;
46561646 4544 default:
1d2887e2 4545 return EMULATION_FAILED;
0d7cdee8 4546 }
46561646 4547
b1ea50b2 4548 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4549 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4550 }
4551
e24186e0
PB		 4552 /* Unrecognised? */
4553 if (ctxt->d == 0)
4554 return EMULATION_FAILED;
4555
9dac77fa 4556 ctxt->execute = opcode.u.execute;
dde7e6d1 4557
3a6095a0
NA		 4558 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4559 return EMULATION_FAILED;
4560
d40a6898 4561 if (unlikely(ctxt->d &
58b7075d 4562 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch))) {
d40a6898
PB		 4563 /*
4564 * These are copied unconditionally here, and checked unconditionally
4565 * in x86_emulate_insn.
4566 */
4567 ctxt->check_perm = opcode.check_perm;
4568 ctxt->intercept = opcode.intercept;
dde7e6d1 4569
d40a6898
PB		 4570 if (ctxt->d & NotImpl)
4571 return EMULATION_FAILED;
d867162c 4572
58b7075d
NA		 4573 if (mode == X86EMUL_MODE_PROT64) {
4574 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4575 ctxt->op_bytes = 8;
4576 else if (ctxt->d & NearBranch)
4577 ctxt->op_bytes = 8;
4578 }
7f9b4b75 4579
d40a6898
PB		 4580 if (ctxt->d & Op3264) {
4581 if (mode == X86EMUL_MODE_PROT64)
4582 ctxt->op_bytes = 8;
4583 else
4584 ctxt->op_bytes = 4;
4585 }
4586
4587 if (ctxt->d & Sse)
4588 ctxt->op_bytes = 16;
4589 else if (ctxt->d & Mmx)
4590 ctxt->op_bytes = 8;
4591 }
1253791d 4592
dde7e6d1 4593 /* ModRM and SIB bytes. */
9dac77fa 4594 if (ctxt->d & ModRM) {
f09ed83e 4595 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4596 if (!has_seg_override) {
4597 has_seg_override = true;
4598 ctxt->seg_override = ctxt->modrm_seg;
4599 }
9dac77fa 4600 } else if (ctxt->d & MemAbs)
f09ed83e 4601 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4602 if (rc != X86EMUL_CONTINUE)
4603 goto done;
4604
573e80fe
BD		 4605 if (!has_seg_override)
4606 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4607
573e80fe 4608 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4609
dde7e6d1
AK		 4610 /*
4611 * Decode and fetch the source operand: register, memory
4612 * or immediate.
4613 */
0fe59128 4614 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4615 if (rc != X86EMUL_CONTINUE)
4616 goto done;
4617
dde7e6d1
AK		 4618 /*
4619 * Decode and fetch the second source operand: register, memory
4620 * or immediate.
4621 */
4dd6a57d 4622 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4623 if (rc != X86EMUL_CONTINUE)
4624 goto done;
4625
dde7e6d1 4626 /* Decode and fetch the destination operand: register or memory. */
a9945549 4627 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4628
41061cdb 4629 if (ctxt->rip_relative)
f09ed83e 4630 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4631
a430c916 4632done:
1d2887e2 4633 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4634}
4635
1cb3f3ae
XG		 4636bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4637{
4638 return ctxt->d & PageTable;
4639}
4640
3e2f65d5
GN		 4641static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4642{
3e2f65d5
GN		 4643 /* The second termination condition only applies for REPE
4644 * and REPNE. Test if the repeat string operation prefix is
4645 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4646 * corresponding termination condition according to:
4647 * - if REPE/REPZ and ZF = 0 then done
4648 * - if REPNE/REPNZ and ZF = 1 then done
4649 */
9dac77fa
AK		 4650 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4651 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4652 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4653 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4654 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4655 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4656 return true;
4657
4658 return false;
4659}
4660
cbe2c9d3
AK		 4661static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4662{
4663 bool fault = false;
4664
4665 ctxt->ops->get_fpu(ctxt);
4666 asm volatile("1: fwait \n\t"
4667 "2: \n\t"
4668 ".pushsection .fixup,\"ax\" \n\t"
4669 "3: \n\t"
4670 "movb $1, %[fault] \n\t"
4671 "jmp 2b \n\t"
4672 ".popsection \n\t"
4673 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4674 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4675 ctxt->ops->put_fpu(ctxt);
4676
4677 if (unlikely(fault))
4678 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4679
4680 return X86EMUL_CONTINUE;
4681}
4682
4683static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4684 struct operand *op)
4685{
4686 if (op->type == OP_MM)
4687 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4688}
4689
e28bbd44
AK		 4690static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4691{
4692 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4693 if (!(ctxt->d & ByteOp))
4694 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4695 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4696 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4697 [fastop]"+S"(fop)
4698 : "c"(ctxt->src2.val));
e28bbd44 4699 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4700 if (!fop) /* exception is returned in fop variable */
4701 return emulate_de(ctxt);
e28bbd44
AK		 4702 return X86EMUL_CONTINUE;
4703}
dd856efa 4704
1498507a
BD		 4705void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4706{
573e80fe
BD		 4707 memset(&ctxt->rip_relative, 0,
4708 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4709
1498507a
BD		 4710 ctxt->io_read.pos = 0;
4711 ctxt->io_read.end = 0;
1498507a
BD		 4712 ctxt->mem_read.end = 0;
4713}
4714
7b105ca2 4715int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4716{
0225fb50 4717 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4718 int rc = X86EMUL_CONTINUE;
9dac77fa 4719 int saved_dst_type = ctxt->dst.type;
8b4caf66 4720
9dac77fa 4721 ctxt->mem_read.pos = 0;
310b5d30 4722
e24186e0
PB		 4723 /* LOCK prefix is allowed only with some instructions */
4724 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4725 rc = emulate_ud(ctxt);
1161624f
GN		 4726 goto done;
4727 }
4728
e24186e0 4729 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4730 rc = emulate_ud(ctxt);
d380a5e4
GN		 4731 goto done;
4732 }
4733
d40a6898
PB		 4734 if (unlikely(ctxt->d &
4735 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4736 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4737 (ctxt->d & Undefined)) {
4738 rc = emulate_ud(ctxt);
4739 goto done;
4740 }
1253791d 4741
d40a6898
PB		 4742 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4743 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4744 rc = emulate_ud(ctxt);
cbe2c9d3 4745 goto done;
d40a6898 4746 }
cbe2c9d3 4747
d40a6898
PB		 4748 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4749 rc = emulate_nm(ctxt);
c4f035c6 4750 goto done;
d40a6898 4751 }
c4f035c6 4752
d40a6898
PB		 4753 if (ctxt->d & Mmx) {
4754 rc = flush_pending_x87_faults(ctxt);
4755 if (rc != X86EMUL_CONTINUE)
4756 goto done;
4757 /*
4758 * Now that we know the fpu is exception safe, we can fetch
4759 * operands from it.
4760 */
4761 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4762 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4763 if (!(ctxt->d & Mov))
4764 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4765 }
e92805ac 4766
685bbf4a 4767 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4768 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4769 X86_ICPT_PRE_EXCEPT);
4770 if (rc != X86EMUL_CONTINUE)
4771 goto done;
4772 }
8ea7d6ae 4773
d40a6898
PB		 4774 /* Privileged instruction can be executed only in CPL=0 */
4775 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4776 if (ctxt->d & PrivUD)
4777 rc = emulate_ud(ctxt);
4778 else
4779 rc = emulate_gp(ctxt, 0);
d09beabd 4780 goto done;
d40a6898 4781 }
d09beabd 4782
d40a6898
PB		 4783 /* Instruction can only be executed in protected mode */
4784 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4785 rc = emulate_ud(ctxt);
c4f035c6 4786 goto done;
d40a6898 4787 }
c4f035c6 4788
d40a6898 4789 /* Do instruction specific permission checks */
685bbf4a 4790 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4791 rc = ctxt->check_perm(ctxt);
4792 if (rc != X86EMUL_CONTINUE)
4793 goto done;
4794 }
4795
685bbf4a 4796 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4797 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4798 X86_ICPT_POST_EXCEPT);
4799 if (rc != X86EMUL_CONTINUE)
4800 goto done;
4801 }
4802
4803 if (ctxt->rep_prefix && (ctxt->d & String)) {
4804 /* All REP prefixes have the same first termination condition */
4805 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4806 ctxt->eip = ctxt->_eip;
4467c3f1 4807 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4808 goto done;
4809 }
b9fa9d6b 4810 }
b9fa9d6b
AK		 4811 }
4812
9dac77fa
AK		 4813 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4814 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4815 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4816 if (rc != X86EMUL_CONTINUE)
8b4caf66 4817 goto done;
9dac77fa 4818 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4819 }
4820
9dac77fa
AK		 4821 if (ctxt->src2.type == OP_MEM) {
4822 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4823 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4824 if (rc != X86EMUL_CONTINUE)
4825 goto done;
4826 }
4827
9dac77fa 4828 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4829 goto special_insn;
4830
4831
9dac77fa 4832 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4833 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4834 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4835 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4836 if (rc != X86EMUL_CONTINUE)
4837 goto done;
038e51de 4838 }
9dac77fa 4839 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4840
018a98db
AK		 4841special_insn:
4842
685bbf4a 4843 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4844 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4845 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4846 if (rc != X86EMUL_CONTINUE)
4847 goto done;
4848 }
4849
b9a1ecb9
NA		 4850 if (ctxt->rep_prefix && (ctxt->d & String))
4851 ctxt->eflags |= EFLG_RF;
4852 else
4853 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4854
9dac77fa 4855 if (ctxt->execute) {
e28bbd44
AK		 4856 if (ctxt->d & Fastop) {
4857 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4858 rc = fastop(ctxt, fop);
4859 if (rc != X86EMUL_CONTINUE)
4860 goto done;
4861 goto writeback;
4862 }
9dac77fa 4863 rc = ctxt->execute(ctxt);
ef65c889
AK		 4864 if (rc != X86EMUL_CONTINUE)
4865 goto done;
4866 goto writeback;
4867 }
4868
1ce19dc1 4869 if (ctxt->opcode_len == 2)
6aa8b732 4870 goto twobyte_insn;
0bc5eedb
BP		 4871 else if (ctxt->opcode_len == 3)
4872 goto threebyte_insn;
6aa8b732 4873
9dac77fa 4874 switch (ctxt->b) {
6aa8b732 4875 case 0x63: /* movsxd */
8b4caf66 4876 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4877 goto cannot_emulate;
9dac77fa 4878 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4879 break;
b2833e3c 4880 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4881 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4882 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4883 break;
7e0b54b1 4884 case 0x8d: /* lea r16/r32, m */
9dac77fa 4885 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4886 break;
3d9e77df 4887 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4888 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4889 ctxt->dst.type = OP_NONE;
4890 else
4891 rc = em_xchg(ctxt);
e4f973ae 4892 break;
e8b6fa70 4893 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4894 switch (ctxt->op_bytes) {
4895 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4896 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4897 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4898 }
4899 break;
6e154e56 4900 case 0xcc: /* int3 */
5c5df76b
TY		 4901 rc = emulate_int(ctxt, 3);
4902 break;
6e154e56 4903 case 0xcd: /* int n */
9dac77fa 4904 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4905 break;
4906 case 0xce: /* into */
5c5df76b
TY		 4907 if (ctxt->eflags & EFLG_OF)
4908 rc = emulate_int(ctxt, 4);
6e154e56 4909 break;
1a52e051 4910 case 0xe9: /* jmp rel */
db5b0762 4911 case 0xeb: /* jmp rel short */
234f3ce4 4912 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4913 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4914 break;
111de5d6 4915 case 0xf4: /* hlt */
6c3287f7 4916 ctxt->ops->halt(ctxt);
19fdfa0d 4917 break;
111de5d6
AK		 4918 case 0xf5: /* cmc */
4919 /* complement carry flag from eflags reg */
4920 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4921 break;
4922 case 0xf8: /* clc */
4923 ctxt->eflags &= ~EFLG_CF;
111de5d6 4924 break;
8744aa9a
MG		 4925 case 0xf9: /* stc */
4926 ctxt->eflags |= EFLG_CF;
4927 break;
fb4616f4
MG		 4928 case 0xfc: /* cld */
4929 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4930 break;
4931 case 0xfd: /* std */
4932 ctxt->eflags |= EFLG_DF;
fb4616f4 4933 break;
91269b8f
AK		 4934 default:
4935 goto cannot_emulate;
6aa8b732 4936 }
018a98db 4937
7d9ddaed
AK		 4938 if (rc != X86EMUL_CONTINUE)
4939 goto done;
4940
018a98db 4941writeback:
fb32b1ed
AK		 4942 if (ctxt->d & SrcWrite) {
4943 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4944 rc = writeback(ctxt, &ctxt->src);
4945 if (rc != X86EMUL_CONTINUE)
4946 goto done;
4947 }
ee212297
NA		 4948 if (!(ctxt->d & NoWrite)) {
4949 rc = writeback(ctxt, &ctxt->dst);
4950 if (rc != X86EMUL_CONTINUE)
4951 goto done;
4952 }
018a98db 4953
5cd21917
GN		 4954 /*
4955 * restore dst type in case the decoding will be reused
4956 * (happens for string instruction )
4957 */
9dac77fa 4958 ctxt->dst.type = saved_dst_type;
5cd21917 4959
9dac77fa 4960 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4961 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4962
9dac77fa 4963 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4964 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4965
9dac77fa 4966 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4967 unsigned int count;
9dac77fa 4968 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4969 if ((ctxt->d & SrcMask) == SrcSI)
4970 count = ctxt->src.count;
4971 else
4972 count = ctxt->dst.count;
4973 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4974 -count);
3e2f65d5 4975
d2ddd1c4
GN		 4976 if (!string_insn_completed(ctxt)) {
4977 /*
4978 * Re-enter guest when pio read ahead buffer is empty
4979 * or, if it is not used, after each 1024 iteration.
4980 */
dd856efa 4981 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4982 (r->end == 0 || r->end != r->pos)) {
4983 /*
4984 * Reset read cache. Usually happens before
4985 * decode, but since instruction is restarted
4986 * we have to do it here.
4987 */
9dac77fa 4988 ctxt->mem_read.end = 0;
dd856efa 4989 writeback_registers(ctxt);
d2ddd1c4
GN		 4990 return EMULATION_RESTART;
4991 }
4992 goto done; /* skip rip writeback */
0fa6ccbd 4993 }
b9a1ecb9 4994 ctxt->eflags &= ~EFLG_RF;
5cd21917 4995 }
d2ddd1c4 4996
9dac77fa 4997 ctxt->eip = ctxt->_eip;
018a98db
AK		 4998
4999done:
e0ad0b47
PB		 5000 if (rc == X86EMUL_PROPAGATE_FAULT) {
5001 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5002 ctxt->have_exception = true;
e0ad0b47 5003 }
775fde86
JR		 5004 if (rc == X86EMUL_INTERCEPTED)
5005 return EMULATION_INTERCEPTED;
5006
dd856efa
AK		 5007 if (rc == X86EMUL_CONTINUE)
5008 writeback_registers(ctxt);
5009
d2ddd1c4 5010 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5011
5012twobyte_insn:
9dac77fa 5013 switch (ctxt->b) {
018a98db 5014 case 0x09: /* wbinvd */
cfb22375 5015 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5016 break;
5017 case 0x08: /* invd */
018a98db
AK		 5018 case 0x0d: /* GrpP (prefetch) */
5019 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5020 case 0x1f: /* nop */
018a98db
AK		 5021 break;
5022 case 0x20: /* mov cr, reg */
9dac77fa 5023 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5024 break;
6aa8b732 5025 case 0x21: /* mov from dr to reg */
9dac77fa 5026 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5027 break;
6aa8b732 5028 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5029 if (test_cc(ctxt->b, ctxt->eflags))
5030 ctxt->dst.val = ctxt->src.val;
5031 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5032 ctxt->op_bytes != 4)
9dac77fa 5033 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5034 break;
b2833e3c 5035 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5036 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5037 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5038 break;
ee45b58e 5039 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5040 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5041 break;
6aa8b732 5042 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5043 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5044 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5045 : (u16) ctxt->src.val;
6aa8b732 5046 break;
6aa8b732 5047 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5048 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5049 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5050 (s16) ctxt->src.val;
6aa8b732 5051 break;
a012e65a 5052 case 0xc3: /* movnti */
9dac77fa 5053 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 5054 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
5055 (u32) ctxt->src.val;
a012e65a 5056 break;
91269b8f
AK		 5057 default:
5058 goto cannot_emulate;
6aa8b732 5059 }
7d9ddaed 5060
0bc5eedb
BP		 5061threebyte_insn:
5062
7d9ddaed
AK		 5063 if (rc != X86EMUL_CONTINUE)
5064 goto done;
5065
6aa8b732
AK		 5066 goto writeback;
5067
5068cannot_emulate:
a0c0ab2f 5069 return EMULATION_FAILED;
6aa8b732 5070}
dd856efa
AK		 5071
5072void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5073{
5074 invalidate_registers(ctxt);
5075}
5076
5077void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5078{
5079 writeback_registers(ctxt);
5080}
Linux kernel - Deliverables
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