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KVM: x86: Remove FIXMEs in emulate.c
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 169#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 170#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 171
820207c8 172#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 173
d0e53325
AK		 174#define X2(x...) x, x
175#define X3(x...) X2(x), x
176#define X4(x...) X2(x), X2(x)
177#define X5(x...) X4(x), x
178#define X6(x...) X4(x), X2(x)
179#define X7(x...) X4(x), X3(x)
180#define X8(x...) X4(x), X4(x)
181#define X16(x...) X8(x), X8(x)
83babbca 182
e28bbd44
AK		 183#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
184#define FASTOP_SIZE 8
185
186/*
187 * fastop functions have a special calling convention:
188 *
017da7b6
AK		 189 * dst: rax (in/out)
190 * src: rdx (in/out)
e28bbd44
AK		 191 * src2: rcx (in)
192 * flags: rflags (in/out)
b8c0b6ae 193 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 194 *
195 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
196 * different operand sizes can be reached by calculation, rather than a jump
197 * table (which would be bigger than the code).
198 *
199 * fastop functions are declared as taking a never-defined fastop parameter,
200 * so they can't be called from C directly.
201 */
202
203struct fastop;
204
d65b1dee 205struct opcode {
b1ea50b2
AK		 206 u64 flags : 56;
207 u64 intercept : 8;
120df890 208 union {
ef65c889 209 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 210 const struct opcode *group;
211 const struct group_dual *gdual;
212 const struct gprefix *gprefix;
045a282c 213 const struct escape *esc;
e28bbd44 214 void (*fastop)(struct fastop *fake);
120df890 215 } u;
d09beabd 216 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 217};
218
219struct group_dual {
220 struct opcode mod012[8];
221 struct opcode mod3[8];
d65b1dee
AK		 222};
223
0d7cdee8
AK		 224struct gprefix {
225 struct opcode pfx_no;
226 struct opcode pfx_66;
227 struct opcode pfx_f2;
228 struct opcode pfx_f3;
229};
230
045a282c
GN		 231struct escape {
232 struct opcode op[8];
233 struct opcode high[64];
234};
235
6aa8b732 236/* EFLAGS bit definitions. */
d4c6a154
GN		 237#define EFLG_ID (1<<21)
238#define EFLG_VIP (1<<20)
239#define EFLG_VIF (1<<19)
240#define EFLG_AC (1<<18)
b1d86143
AP		 241#define EFLG_VM (1<<17)
242#define EFLG_RF (1<<16)
d4c6a154
GN		 243#define EFLG_IOPL (3<<12)
244#define EFLG_NT (1<<14)
6aa8b732
AK		 245#define EFLG_OF (1<<11)
246#define EFLG_DF (1<<10)
b1d86143 247#define EFLG_IF (1<<9)
d4c6a154 248#define EFLG_TF (1<<8)
6aa8b732
AK		 249#define EFLG_SF (1<<7)
250#define EFLG_ZF (1<<6)
251#define EFLG_AF (1<<4)
252#define EFLG_PF (1<<2)
253#define EFLG_CF (1<<0)
254
62bd430e
MG		 255#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
256#define EFLG_RESERVED_ONE_MASK 2
257
dd856efa
AK		 258static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
259{
260 if (!(ctxt->regs_valid & (1 << nr))) {
261 ctxt->regs_valid |= 1 << nr;
262 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
263 }
264 return ctxt->_regs[nr];
265}
266
267static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
268{
269 ctxt->regs_valid |= 1 << nr;
270 ctxt->regs_dirty |= 1 << nr;
271 return &ctxt->_regs[nr];
272}
273
274static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 reg_read(ctxt, nr);
277 return reg_write(ctxt, nr);
278}
279
280static void writeback_registers(struct x86_emulate_ctxt *ctxt)
281{
282 unsigned reg;
283
284 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
285 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
286}
287
288static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
289{
290 ctxt->regs_dirty = 0;
291 ctxt->regs_valid = 0;
292}
293
6aa8b732
AK		 294/*
295 * These EFLAGS bits are restored from saved value during emulation, and
296 * any changes are written back to the saved value after emulation.
297 */
298#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
299
dda96d8f
AK		 300#ifdef CONFIG_X86_64
301#define ON64(x) x
302#else
303#define ON64(x)
304#endif
305
4d758349
AK		 306static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
307
b7d491e7
AK		 308#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
309#define FOP_RET "ret \n\t"
310
311#define FOP_START(op) \
312 extern void em_##op(struct fastop *fake); \
313 asm(".pushsection .text, \"ax\" \n\t" \
314 ".global em_" #op " \n\t" \
315 FOP_ALIGN \
316 "em_" #op ": \n\t"
317
318#define FOP_END \
319 ".popsection")
320
0bdea068
AK		 321#define FOPNOP() FOP_ALIGN FOP_RET
322
b7d491e7 323#define FOP1E(op, dst) \
b8c0b6ae
AK		 324 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
325
326#define FOP1EEX(op, dst) \
327 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 328
329#define FASTOP1(op) \
330 FOP_START(op) \
331 FOP1E(op##b, al) \
332 FOP1E(op##w, ax) \
333 FOP1E(op##l, eax) \
334 ON64(FOP1E(op##q, rax)) \
335 FOP_END
336
b9fa409b
AK		 337/* 1-operand, using src2 (for MUL/DIV r/m) */
338#define FASTOP1SRC2(op, name) \
339 FOP_START(name) \
340 FOP1E(op, cl) \
341 FOP1E(op, cx) \
342 FOP1E(op, ecx) \
343 ON64(FOP1E(op, rcx)) \
344 FOP_END
345
b8c0b6ae
AK		 346/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
347#define FASTOP1SRC2EX(op, name) \
348 FOP_START(name) \
349 FOP1EEX(op, cl) \
350 FOP1EEX(op, cx) \
351 FOP1EEX(op, ecx) \
352 ON64(FOP1EEX(op, rcx)) \
353 FOP_END
354
f7857f35
AK		 355#define FOP2E(op, dst, src) \
356 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
357
358#define FASTOP2(op) \
359 FOP_START(op) \
017da7b6
AK		 360 FOP2E(op##b, al, dl) \
361 FOP2E(op##w, ax, dx) \
362 FOP2E(op##l, eax, edx) \
363 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 364 FOP_END
365
11c363ba
AK		 366/* 2 operand, word only */
367#define FASTOP2W(op) \
368 FOP_START(op) \
369 FOPNOP() \
017da7b6
AK		 370 FOP2E(op##w, ax, dx) \
371 FOP2E(op##l, eax, edx) \
372 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 373 FOP_END
374
007a3b54
AK		 375/* 2 operand, src is CL */
376#define FASTOP2CL(op) \
377 FOP_START(op) \
378 FOP2E(op##b, al, cl) \
379 FOP2E(op##w, ax, cl) \
380 FOP2E(op##l, eax, cl) \
381 ON64(FOP2E(op##q, rax, cl)) \
382 FOP_END
383
5aca3722
NA		 384/* 2 operand, src and dest are reversed */
385#define FASTOP2R(op, name) \
386 FOP_START(name) \
387 FOP2E(op##b, dl, al) \
388 FOP2E(op##w, dx, ax) \
389 FOP2E(op##l, edx, eax) \
390 ON64(FOP2E(op##q, rdx, rax)) \
391 FOP_END
392
0bdea068
AK		 393#define FOP3E(op, dst, src, src2) \
394 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
395
396/* 3-operand, word-only, src2=cl */
397#define FASTOP3WCL(op) \
398 FOP_START(op) \
399 FOPNOP() \
017da7b6
AK		 400 FOP3E(op##w, ax, dx, cl) \
401 FOP3E(op##l, eax, edx, cl) \
402 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 403 FOP_END
404
9ae9feba
AK		 405/* Special case for SETcc - 1 instruction per cc */
406#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
407
b8c0b6ae
AK		 408asm(".global kvm_fastop_exception \n"
409 "kvm_fastop_exception: xor %esi, %esi; ret");
410
9ae9feba
AK		 411FOP_START(setcc)
412FOP_SETCC(seto)
413FOP_SETCC(setno)
414FOP_SETCC(setc)
415FOP_SETCC(setnc)
416FOP_SETCC(setz)
417FOP_SETCC(setnz)
418FOP_SETCC(setbe)
419FOP_SETCC(setnbe)
420FOP_SETCC(sets)
421FOP_SETCC(setns)
422FOP_SETCC(setp)
423FOP_SETCC(setnp)
424FOP_SETCC(setl)
425FOP_SETCC(setnl)
426FOP_SETCC(setle)
427FOP_SETCC(setnle)
428FOP_END;
429
326f578f
PB		 430FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
431FOP_END;
432
8a76d7f2
JR		 433static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
434 enum x86_intercept intercept,
435 enum x86_intercept_stage stage)
436{
437 struct x86_instruction_info info = {
438 .intercept = intercept,
9dac77fa
AK		 439 .rep_prefix = ctxt->rep_prefix,
440 .modrm_mod = ctxt->modrm_mod,
441 .modrm_reg = ctxt->modrm_reg,
442 .modrm_rm = ctxt->modrm_rm,
443 .src_val = ctxt->src.val64,
6cbc5f5a 444 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 445 .src_bytes = ctxt->src.bytes,
446 .dst_bytes = ctxt->dst.bytes,
447 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 448 .next_rip = ctxt->eip,
449 };
450
2953538e 451 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 452}
453
f47cfa31
AK		 454static void assign_masked(ulong *dest, ulong src, ulong mask)
455{
456 *dest = (*dest & ~mask) | (src & mask);
457}
458
9dac77fa 459static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 460{
9dac77fa 461 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 462}
463
f47cfa31
AK		 464static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
465{
466 u16 sel;
467 struct desc_struct ss;
468
469 if (ctxt->mode == X86EMUL_MODE_PROT64)
470 return ~0UL;
471 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
472 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
473}
474
612e89f0
AK		 475static int stack_size(struct x86_emulate_ctxt *ctxt)
476{
477 return (__fls(stack_mask(ctxt)) + 1) >> 3;
478}
479
6aa8b732 480/* Access/update address held in a register, based on addressing mode. */
e4706772 481static inline unsigned long
9dac77fa 482address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 483{
9dac77fa 484 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 485 return reg;
486 else
9dac77fa 487 return reg & ad_mask(ctxt);
e4706772
HH		 488}
489
490static inline unsigned long
01485a22 491register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 492{
01485a22 493 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 494}
495
5ad105e5
AK		 496static void masked_increment(ulong *reg, ulong mask, int inc)
497{
498 assign_masked(reg, *reg + inc, mask);
499}
500
7a957275 501static inline void
01485a22 502register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 503{
5ad105e5
AK		 504 ulong mask;
505
9dac77fa 506 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 507 mask = ~0UL;
7a957275 508 else
5ad105e5 509 mask = ad_mask(ctxt);
01485a22 510 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 511}
512
513static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
514{
dd856efa 515 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 516}
6aa8b732 517
56697687
AK		 518static u32 desc_limit_scaled(struct desc_struct *desc)
519{
520 u32 limit = get_desc_limit(desc);
521
522 return desc->g ? (limit << 12) | 0xfff : limit;
523}
524
7b105ca2 525static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 526{
527 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
528 return 0;
529
7b105ca2 530 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 531}
532
35d3d4a1
AK		 533static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
534 u32 error, bool valid)
54b8486f 535{
e0ad0b47 536 WARN_ON(vec > 0x1f);
da9cb575
AK		 537 ctxt->exception.vector = vec;
538 ctxt->exception.error_code = error;
539 ctxt->exception.error_code_valid = valid;
35d3d4a1 540 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 541}
542
3b88e41a
JR		 543static int emulate_db(struct x86_emulate_ctxt *ctxt)
544{
545 return emulate_exception(ctxt, DB_VECTOR, 0, false);
546}
547
35d3d4a1 548static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 549{
35d3d4a1 550 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 551}
552
618ff15d
AK		 553static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
554{
555 return emulate_exception(ctxt, SS_VECTOR, err, true);
556}
557
35d3d4a1 558static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 559{
35d3d4a1 560 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 561}
562
35d3d4a1 563static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 566}
567
34d1f490
AK		 568static int emulate_de(struct x86_emulate_ctxt *ctxt)
569{
35d3d4a1 570 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 571}
572
1253791d
AK		 573static int emulate_nm(struct x86_emulate_ctxt *ctxt)
574{
575 return emulate_exception(ctxt, NM_VECTOR, 0, false);
576}
577
1aa36616
AK		 578static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
579{
580 u16 selector;
581 struct desc_struct desc;
582
583 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
584 return selector;
585}
586
587static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
588 unsigned seg)
589{
590 u16 dummy;
591 u32 base3;
592 struct desc_struct desc;
593
594 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
595 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
596}
597
1c11b376
AK		 598/*
599 * x86 defines three classes of vector instructions: explicitly
600 * aligned, explicitly unaligned, and the rest, which change behaviour
601 * depending on whether they're AVX encoded or not.
602 *
603 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
604 * subject to the same check.
605 */
606static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
607{
608 if (likely(size < 16))
609 return false;
610
611 if (ctxt->d & Aligned)
612 return true;
613 else if (ctxt->d & Unaligned)
614 return false;
615 else if (ctxt->d & Avx)
616 return false;
617 else
618 return true;
619}
620
d09155d2
PB		 621static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
622 struct segmented_address addr,
623 unsigned *max_size, unsigned size,
624 bool write, bool fetch,
d50eaa18 625 enum x86emul_mode mode, ulong *linear)
52fd8b44 626{
618ff15d
AK		 627 struct desc_struct desc;
628 bool usable;
52fd8b44 629 ulong la;
618ff15d 630 u32 lim;
1aa36616 631 u16 sel;
52fd8b44 632
1c1c35ae 633 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 634 *max_size = 0;
d50eaa18 635 switch (mode) {
618ff15d 636 case X86EMUL_MODE_PROT64:
4be4de7e 637 if (is_noncanonical_address(la))
abc7d8a4 638 goto bad;
fd56e154
PB		 639
640 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
641 if (size > *max_size)
642 goto bad;
618ff15d
AK		 643 break;
644 default:
1aa36616
AK		 645 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
646 addr.seg);
618ff15d
AK		 647 if (!usable)
648 goto bad;
58b7825b
GN		 649 /* code segment in protected mode or read-only data segment */
650 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
651 || !(desc.type & 2)) && write)
618ff15d
AK		 652 goto bad;
653 /* unreadable code segment */
3d9b938e 654 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 655 goto bad;
656 lim = desc_limit_scaled(&desc);
997b0412 657 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 658 /* expand-down segment */
fd56e154 659 if (addr.ea <= lim)
618ff15d
AK		 660 goto bad;
661 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 662 }
997b0412
PB		 663 if (addr.ea > lim)
664 goto bad;
665 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 666 if (size > *max_size)
667 goto bad;
31ff6488 668 la &= (u32)-1;
618ff15d
AK		 669 break;
670 }
1c11b376
AK		 671 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
672 return emulate_gp(ctxt, 0);
52fd8b44
AK		 673 *linear = la;
674 return X86EMUL_CONTINUE;
618ff15d
AK		 675bad:
676 if (addr.seg == VCPU_SREG_SS)
3606189f 677 return emulate_ss(ctxt, 0);
618ff15d 678 else
3606189f 679 return emulate_gp(ctxt, 0);
52fd8b44
AK		 680}
681
3d9b938e
NE		 682static int linearize(struct x86_emulate_ctxt *ctxt,
683 struct segmented_address addr,
684 unsigned size, bool write,
685 ulong *linear)
686{
fd56e154 687 unsigned max_size;
d50eaa18
NA		 688 return __linearize(ctxt, addr, &max_size, size, write, false,
689 ctxt->mode, linear);
3d9b938e
NE		 690}
691
d50eaa18
NA		 692static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
693 enum x86emul_mode mode)
694{
695 ulong linear;
696 int rc;
697 unsigned max_size;
698 struct segmented_address addr = { .seg = VCPU_SREG_CS,
699 .ea = dst };
700
701 if (ctxt->op_bytes != sizeof(unsigned long))
702 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
703 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
704 if (rc == X86EMUL_CONTINUE)
705 ctxt->_eip = addr.ea;
706 return rc;
707}
708
709static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
710{
711 return assign_eip(ctxt, dst, ctxt->mode);
712}
713
714static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
715 const struct desc_struct *cs_desc)
716{
717 enum x86emul_mode mode = ctxt->mode;
718
719#ifdef CONFIG_X86_64
720 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
721 u64 efer = 0;
722
723 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
724 if (efer & EFER_LMA)
725 mode = X86EMUL_MODE_PROT64;
726 }
727#endif
728 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
729 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
730 return assign_eip(ctxt, dst, mode);
731}
732
733static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
734{
735 return assign_eip_near(ctxt, ctxt->_eip + rel);
736}
3d9b938e 737
3ca3ac4d
AK		 738static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
739 struct segmented_address addr,
740 void *data,
741 unsigned size)
742{
9fa088f4
AK		 743 int rc;
744 ulong linear;
745
83b8795a 746 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 747 if (rc != X86EMUL_CONTINUE)
748 return rc;
0f65dd70 749 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 750}
751
807941b1 752/*
285ca9e9 753 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 754 * boundary if they are not in fetch_cache yet.
755 */
9506d57d 756static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 757{
62266869 758 int rc;
fd56e154 759 unsigned size, max_size;
285ca9e9 760 unsigned long linear;
17052f16 761 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 762 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 763 .ea = ctxt->eip + cur_size };
764
fd56e154
PB		 765 /*
766 * We do not know exactly how many bytes will be needed, and
767 * __linearize is expensive, so fetch as much as possible. We
768 * just have to avoid going beyond the 15 byte limit, the end
769 * of the segment, or the end of the page.
770 *
771 * __linearize is called with size 0 so that it does not do any
772 * boundary check itself. Instead, we use max_size to check
773 * against op_size.
774 */
d50eaa18
NA		 775 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
776 &linear);
719d5a9b
PB		 777 if (unlikely(rc != X86EMUL_CONTINUE))
778 return rc;
779
fd56e154 780 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 781 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 782
783 /*
784 * One instruction can only straddle two pages,
785 * and one has been loaded at the beginning of
786 * x86_decode_insn. So, if not enough bytes
787 * still, we must have hit the 15-byte boundary.
788 */
789 if (unlikely(size < op_size))
fd56e154
PB		 790 return emulate_gp(ctxt, 0);
791
17052f16 792 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 793 size, &ctxt->exception);
794 if (unlikely(rc != X86EMUL_CONTINUE))
795 return rc;
17052f16 796 ctxt->fetch.end += size;
3e2815e9 797 return X86EMUL_CONTINUE;
62266869
AK		 798}
799
9506d57d
PB		 800static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
801 unsigned size)
62266869 802{
08da44ae
NA		 803 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
804
805 if (unlikely(done_size < size))
806 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 807 else
808 return X86EMUL_CONTINUE;
62266869
AK		 809}
810
67cbc90d 811/* Fetch next part of the instruction being emulated. */
e85a1085 812#define insn_fetch(_type, _ctxt) \
9506d57d 813({ _type _x; \
9506d57d
PB		 814 \
815 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 816 if (rc != X86EMUL_CONTINUE) \
817 goto done; \
9506d57d 818 ctxt->_eip += sizeof(_type); \
17052f16
PB		 819 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
820 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 821 _x; \
67cbc90d
TY		 822})
823
807941b1 824#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 825({ \
9506d57d 826 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 827 if (rc != X86EMUL_CONTINUE) \
828 goto done; \
9506d57d 829 ctxt->_eip += (_size); \
17052f16
PB		 830 memcpy(_arr, ctxt->fetch.ptr, _size); \
831 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 832})
833
1e3c5cb0
RR		 834/*
835 * Given the 'reg' portion of a ModRM byte, and a register block, return a
836 * pointer into the block that addresses the relevant register.
837 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
838 */
dd856efa 839static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 840 int byteop)
6aa8b732
AK		 841{
842 void *p;
aa9ac1a6 843 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 844
6aa8b732 845 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 846 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
847 else
848 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 849 return p;
850}
851
852static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 853 struct segmented_address addr,
6aa8b732
AK		 854 u16 *size, unsigned long *address, int op_bytes)
855{
856 int rc;
857
858 if (op_bytes == 2)
859 op_bytes = 3;
860 *address = 0;
3ca3ac4d 861 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 862 if (rc != X86EMUL_CONTINUE)
6aa8b732 863 return rc;
30b31ab6 864 addr.ea += 2;
3ca3ac4d 865 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 866 return rc;
867}
868
34b77652
AK		 869FASTOP2(add);
870FASTOP2(or);
871FASTOP2(adc);
872FASTOP2(sbb);
873FASTOP2(and);
874FASTOP2(sub);
875FASTOP2(xor);
876FASTOP2(cmp);
877FASTOP2(test);
878
b9fa409b
AK		 879FASTOP1SRC2(mul, mul_ex);
880FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 881FASTOP1SRC2EX(div, div_ex);
882FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 883
34b77652
AK		 884FASTOP3WCL(shld);
885FASTOP3WCL(shrd);
886
887FASTOP2W(imul);
888
889FASTOP1(not);
890FASTOP1(neg);
891FASTOP1(inc);
892FASTOP1(dec);
893
894FASTOP2CL(rol);
895FASTOP2CL(ror);
896FASTOP2CL(rcl);
897FASTOP2CL(rcr);
898FASTOP2CL(shl);
899FASTOP2CL(shr);
900FASTOP2CL(sar);
901
902FASTOP2W(bsf);
903FASTOP2W(bsr);
904FASTOP2W(bt);
905FASTOP2W(bts);
906FASTOP2W(btr);
907FASTOP2W(btc);
908
e47a5f5f
AK		 909FASTOP2(xadd);
910
5aca3722
NA		 911FASTOP2R(cmp, cmp_r);
912
9ae9feba 913static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 914{
9ae9feba
AK		 915 u8 rc;
916 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 917
9ae9feba 918 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 919 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 920 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
921 return rc;
bbe9abbd
NK		 922}
923
91ff3cb4
AK		 924static void fetch_register_operand(struct operand *op)
925{
926 switch (op->bytes) {
927 case 1:
928 op->val = *(u8 *)op->addr.reg;
929 break;
930 case 2:
931 op->val = *(u16 *)op->addr.reg;
932 break;
933 case 4:
934 op->val = *(u32 *)op->addr.reg;
935 break;
936 case 8:
937 op->val = *(u64 *)op->addr.reg;
938 break;
939 }
940}
941
1253791d
AK		 942static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
943{
944 ctxt->ops->get_fpu(ctxt);
945 switch (reg) {
89a87c67
MK		 946 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
947 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
948 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
949 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
950 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
951 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
952 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
953 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 954#ifdef CONFIG_X86_64
89a87c67
MK		 955 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
956 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
957 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
958 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
959 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
960 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
961 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
962 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 963#endif
964 default: BUG();
965 }
966 ctxt->ops->put_fpu(ctxt);
967}
968
969static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
970 int reg)
971{
972 ctxt->ops->get_fpu(ctxt);
973 switch (reg) {
89a87c67
MK		 974 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
975 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
976 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
977 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
978 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
979 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
980 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
981 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 982#ifdef CONFIG_X86_64
89a87c67
MK		 983 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
984 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
985 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
986 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
987 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
988 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
989 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
990 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 991#endif
992 default: BUG();
993 }
994 ctxt->ops->put_fpu(ctxt);
995}
996
cbe2c9d3
AK		 997static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
998{
999 ctxt->ops->get_fpu(ctxt);
1000 switch (reg) {
1001 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1002 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1003 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1004 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1005 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1006 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1007 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1008 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1009 default: BUG();
1010 }
1011 ctxt->ops->put_fpu(ctxt);
1012}
1013
1014static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1015{
1016 ctxt->ops->get_fpu(ctxt);
1017 switch (reg) {
1018 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1019 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1020 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1021 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1022 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1023 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1024 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1025 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1026 default: BUG();
1027 }
1028 ctxt->ops->put_fpu(ctxt);
1029}
1030
045a282c
GN		 1031static int em_fninit(struct x86_emulate_ctxt *ctxt)
1032{
1033 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1034 return emulate_nm(ctxt);
1035
1036 ctxt->ops->get_fpu(ctxt);
1037 asm volatile("fninit");
1038 ctxt->ops->put_fpu(ctxt);
1039 return X86EMUL_CONTINUE;
1040}
1041
1042static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1043{
1044 u16 fcw;
1045
1046 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1047 return emulate_nm(ctxt);
1048
1049 ctxt->ops->get_fpu(ctxt);
1050 asm volatile("fnstcw %0": "+m"(fcw));
1051 ctxt->ops->put_fpu(ctxt);
1052
1053 /* force 2 byte destination */
1054 ctxt->dst.bytes = 2;
1055 ctxt->dst.val = fcw;
1056
1057 return X86EMUL_CONTINUE;
1058}
1059
1060static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1061{
1062 u16 fsw;
1063
1064 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1065 return emulate_nm(ctxt);
1066
1067 ctxt->ops->get_fpu(ctxt);
1068 asm volatile("fnstsw %0": "+m"(fsw));
1069 ctxt->ops->put_fpu(ctxt);
1070
1071 /* force 2 byte destination */
1072 ctxt->dst.bytes = 2;
1073 ctxt->dst.val = fsw;
1074
1075 return X86EMUL_CONTINUE;
1076}
1077
1253791d 1078static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1079 struct operand *op)
3c118e24 1080{
9dac77fa 1081 unsigned reg = ctxt->modrm_reg;
33615aa9 1082
9dac77fa
AK		 1083 if (!(ctxt->d & ModRM))
1084 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1085
9dac77fa 1086 if (ctxt->d & Sse) {
1253791d
AK		 1087 op->type = OP_XMM;
1088 op->bytes = 16;
1089 op->addr.xmm = reg;
1090 read_sse_reg(ctxt, &op->vec_val, reg);
1091 return;
1092 }
cbe2c9d3
AK		 1093 if (ctxt->d & Mmx) {
1094 reg &= 7;
1095 op->type = OP_MM;
1096 op->bytes = 8;
1097 op->addr.mm = reg;
1098 return;
1099 }
1253791d 1100
3c118e24 1101 op->type = OP_REG;
6d4d85ec
GN		 1102 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1103 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1104
91ff3cb4 1105 fetch_register_operand(op);
3c118e24
AK		 1106 op->orig_val = op->val;
1107}
1108
a6e3407b
AK		 1109static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1110{
1111 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1112 ctxt->modrm_seg = VCPU_SREG_SS;
1113}
1114
1c73ef66 1115static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1116 struct operand *op)
1c73ef66 1117{
1c73ef66 1118 u8 sib;
02357bdc 1119 int index_reg, base_reg, scale;
3e2815e9 1120 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1121 ulong modrm_ea = 0;
1c73ef66 1122
02357bdc
BD		 1123 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1124 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1125 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1126
02357bdc 1127 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1128 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1129 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1130 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1131
9b88ae99 1132 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1133 op->type = OP_REG;
9dac77fa 1134 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1135 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1136 ctxt->d & ByteOp);
9dac77fa 1137 if (ctxt->d & Sse) {
1253791d
AK		 1138 op->type = OP_XMM;
1139 op->bytes = 16;
9dac77fa
AK		 1140 op->addr.xmm = ctxt->modrm_rm;
1141 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1142 return rc;
1143 }
cbe2c9d3
AK		 1144 if (ctxt->d & Mmx) {
1145 op->type = OP_MM;
1146 op->bytes = 8;
bdc90722 1147 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1148 return rc;
1149 }
2dbd0dd7 1150 fetch_register_operand(op);
1c73ef66
AK		 1151 return rc;
1152 }
1153
2dbd0dd7
AK		 1154 op->type = OP_MEM;
1155
9dac77fa 1156 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1157 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1158 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1159 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1160 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1161
1162 /* 16-bit ModR/M decode. */
9dac77fa 1163 switch (ctxt->modrm_mod) {
1c73ef66 1164 case 0:
9dac77fa 1165 if (ctxt->modrm_rm == 6)
e85a1085 1166 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1167 break;
1168 case 1:
e85a1085 1169 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1170 break;
1171 case 2:
e85a1085 1172 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1173 break;
1174 }
9dac77fa 1175 switch (ctxt->modrm_rm) {
1c73ef66 1176 case 0:
2dbd0dd7 1177 modrm_ea += bx + si;
1c73ef66
AK		 1178 break;
1179 case 1:
2dbd0dd7 1180 modrm_ea += bx + di;
1c73ef66
AK		 1181 break;
1182 case 2:
2dbd0dd7 1183 modrm_ea += bp + si;
1c73ef66
AK		 1184 break;
1185 case 3:
2dbd0dd7 1186 modrm_ea += bp + di;
1c73ef66
AK		 1187 break;
1188 case 4:
2dbd0dd7 1189 modrm_ea += si;
1c73ef66
AK		 1190 break;
1191 case 5:
2dbd0dd7 1192 modrm_ea += di;
1c73ef66
AK		 1193 break;
1194 case 6:
9dac77fa 1195 if (ctxt->modrm_mod != 0)
2dbd0dd7 1196 modrm_ea += bp;
1c73ef66
AK		 1197 break;
1198 case 7:
2dbd0dd7 1199 modrm_ea += bx;
1c73ef66
AK		 1200 break;
1201 }
9dac77fa
AK		 1202 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1203 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1204 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1205 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1206 } else {
1207 /* 32/64-bit ModR/M decode. */
9dac77fa 1208 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1209 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1210 index_reg |= (sib >> 3) & 7;
1211 base_reg |= sib & 7;
1212 scale = sib >> 6;
1213
9dac77fa 1214 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1215 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1216 else {
dd856efa 1217 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1218 adjust_modrm_seg(ctxt, base_reg);
1219 }
dc71d0f1 1220 if (index_reg != 4)
dd856efa 1221 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1222 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1223 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1224 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1225 ctxt->rip_relative = 1;
a6e3407b
AK		 1226 } else {
1227 base_reg = ctxt->modrm_rm;
dd856efa 1228 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1229 adjust_modrm_seg(ctxt, base_reg);
1230 }
9dac77fa 1231 switch (ctxt->modrm_mod) {
1c73ef66 1232 case 1:
e85a1085 1233 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1234 break;
1235 case 2:
e85a1085 1236 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1237 break;
1238 }
1239 }
90de84f5 1240 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1241 if (ctxt->ad_bytes != 8)
1242 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1243
1c73ef66
AK		 1244done:
1245 return rc;
1246}
1247
1248static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1249 struct operand *op)
1c73ef66 1250{
3e2815e9 1251 int rc = X86EMUL_CONTINUE;
1c73ef66 1252
2dbd0dd7 1253 op->type = OP_MEM;
9dac77fa 1254 switch (ctxt->ad_bytes) {
1c73ef66 1255 case 2:
e85a1085 1256 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1257 break;
1258 case 4:
e85a1085 1259 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1260 break;
1261 case 8:
e85a1085 1262 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1263 break;
1264 }
1265done:
1266 return rc;
1267}
1268
9dac77fa 1269static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1270{
7129eeca 1271 long sv = 0, mask;
35c843c4 1272
9dac77fa 1273 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1274 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1275
9dac77fa
AK		 1276 if (ctxt->src.bytes == 2)
1277 sv = (s16)ctxt->src.val & (s16)mask;
1278 else if (ctxt->src.bytes == 4)
1279 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1280 else
1281 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1282
1c1c35ae
NA		 1283 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1284 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1285 }
ba7ff2b7
WY		 1286
1287 /* only subword offset */
9dac77fa 1288 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1289}
1290
dde7e6d1 1291static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1292 unsigned long addr, void *dest, unsigned size)
6aa8b732 1293{
dde7e6d1 1294 int rc;
9dac77fa 1295 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1296
f23b070e
XG		 1297 if (mc->pos < mc->end)
1298 goto read_cached;
6aa8b732 1299
f23b070e
XG		 1300 WARN_ON((mc->end + size) >= sizeof(mc->data));
1301
1302 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1303 &ctxt->exception);
1304 if (rc != X86EMUL_CONTINUE)
1305 return rc;
1306
1307 mc->end += size;
1308
1309read_cached:
1310 memcpy(dest, mc->data + mc->pos, size);
1311 mc->pos += size;
dde7e6d1
AK		 1312 return X86EMUL_CONTINUE;
1313}
6aa8b732 1314
3ca3ac4d
AK		 1315static int segmented_read(struct x86_emulate_ctxt *ctxt,
1316 struct segmented_address addr,
1317 void *data,
1318 unsigned size)
1319{
9fa088f4
AK		 1320 int rc;
1321 ulong linear;
1322
83b8795a 1323 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1324 if (rc != X86EMUL_CONTINUE)
1325 return rc;
7b105ca2 1326 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1327}
1328
1329static int segmented_write(struct x86_emulate_ctxt *ctxt,
1330 struct segmented_address addr,
1331 const void *data,
1332 unsigned size)
1333{
9fa088f4
AK		 1334 int rc;
1335 ulong linear;
1336
83b8795a 1337 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1338 if (rc != X86EMUL_CONTINUE)
1339 return rc;
0f65dd70
AK		 1340 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1341 &ctxt->exception);
3ca3ac4d
AK		 1342}
1343
1344static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1345 struct segmented_address addr,
1346 const void *orig_data, const void *data,
1347 unsigned size)
1348{
9fa088f4
AK		 1349 int rc;
1350 ulong linear;
1351
83b8795a 1352 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1353 if (rc != X86EMUL_CONTINUE)
1354 return rc;
0f65dd70
AK		 1355 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1356 size, &ctxt->exception);
3ca3ac4d
AK		 1357}
1358
dde7e6d1 1359static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1360 unsigned int size, unsigned short port,
1361 void *dest)
1362{
9dac77fa 1363 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1364
dde7e6d1 1365 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1366 unsigned int in_page, n;
9dac77fa 1367 unsigned int count = ctxt->rep_prefix ?
dd856efa 1368 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1369 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1370 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1371 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1372 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1373 if (n == 0)
1374 n = 1;
1375 rc->pos = rc->end = 0;
7b105ca2 1376 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1377 return 0;
1378 rc->end = n * size;
6aa8b732
AK		 1379 }
1380
e6e39f04
NA		 1381 if (ctxt->rep_prefix && (ctxt->d & String) &&
1382 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1383 ctxt->dst.data = rc->data + rc->pos;
1384 ctxt->dst.type = OP_MEM_STR;
1385 ctxt->dst.count = (rc->end - rc->pos) / size;
1386 rc->pos = rc->end;
1387 } else {
1388 memcpy(dest, rc->data + rc->pos, size);
1389 rc->pos += size;
1390 }
dde7e6d1
AK		 1391 return 1;
1392}
6aa8b732 1393
7f3d35fd
KW		 1394static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1395 u16 index, struct desc_struct *desc)
1396{
1397 struct desc_ptr dt;
1398 ulong addr;
1399
1400 ctxt->ops->get_idt(ctxt, &dt);
1401
1402 if (dt.size < index * 8 + 7)
1403 return emulate_gp(ctxt, index << 3 | 0x2);
1404
1405 addr = dt.address + index * 8;
1406 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1407 &ctxt->exception);
1408}
1409
dde7e6d1 1410static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1411 u16 selector, struct desc_ptr *dt)
1412{
0225fb50 1413 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1414 u32 base3 = 0;
7b105ca2 1415
dde7e6d1
AK		 1416 if (selector & 1 << 2) {
1417 struct desc_struct desc;
1aa36616
AK		 1418 u16 sel;
1419
dde7e6d1 1420 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1421 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1422 VCPU_SREG_LDTR))
dde7e6d1 1423 return;
e09d082c 1424
dde7e6d1 1425 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1426 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1427 } else
4bff1e86 1428 ops->get_gdt(ctxt, dt);
dde7e6d1 1429}
120df890 1430
dde7e6d1
AK		 1431/* allowed just for 8 bytes segments */
1432static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1433 u16 selector, struct desc_struct *desc,
1434 ulong *desc_addr_p)
dde7e6d1
AK		 1435{
1436 struct desc_ptr dt;
1437 u16 index = selector >> 3;
dde7e6d1 1438 ulong addr;
120df890 1439
7b105ca2 1440 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1441
35d3d4a1
AK		 1442 if (dt.size < index * 8 + 7)
1443 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1444
e919464b 1445 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1446 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1447 &ctxt->exception);
dde7e6d1 1448}
ef65c889 1449
dde7e6d1
AK		 1450/* allowed just for 8 bytes segments */
1451static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1452 u16 selector, struct desc_struct *desc)
1453{
1454 struct desc_ptr dt;
1455 u16 index = selector >> 3;
dde7e6d1 1456 ulong addr;
6aa8b732 1457
7b105ca2 1458 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1459
35d3d4a1
AK		 1460 if (dt.size < index * 8 + 7)
1461 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1462
dde7e6d1 1463 addr = dt.address + index * 8;
7b105ca2
TY		 1464 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1465 &ctxt->exception);
dde7e6d1 1466}
c7e75a3d 1467
5601d05b 1468/* Does not support long mode */
2356aaeb 1469static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1470 u16 selector, int seg, u8 cpl,
1471 bool in_task_switch,
1472 struct desc_struct *desc)
dde7e6d1 1473{
869be99c 1474 struct desc_struct seg_desc, old_desc;
2356aaeb 1475 u8 dpl, rpl;
dde7e6d1
AK		 1476 unsigned err_vec = GP_VECTOR;
1477 u32 err_code = 0;
1478 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1479 ulong desc_addr;
dde7e6d1 1480 int ret;
03ebebeb 1481 u16 dummy;
e37a75a1 1482 u32 base3 = 0;
69f55cb1 1483
dde7e6d1 1484 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1485
f8da94e9
KW		 1486 if (ctxt->mode == X86EMUL_MODE_REAL) {
1487 /* set real mode segment descriptor (keep limit etc. for
1488 * unreal mode) */
03ebebeb 1489 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1490 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1491 goto load;
f8da94e9
KW		 1492 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1493 /* VM86 needs a clean new segment descriptor */
1494 set_desc_base(&seg_desc, selector << 4);
1495 set_desc_limit(&seg_desc, 0xffff);
1496 seg_desc.type = 3;
1497 seg_desc.p = 1;
1498 seg_desc.s = 1;
1499 seg_desc.dpl = 3;
1500 goto load;
dde7e6d1
AK		 1501 }
1502
79d5b4c3 1503 rpl = selector & 3;
79d5b4c3
AK		 1504
1505 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1506 if ((seg == VCPU_SREG_CS
1507 || (seg == VCPU_SREG_SS
1508 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1509 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1510 && null_selector)
1511 goto exception;
1512
1513 /* TR should be in GDT only */
1514 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1515 goto exception;
1516
1517 if (null_selector) /* for NULL selector skip all following checks */
1518 goto load;
1519
e919464b 1520 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1521 if (ret != X86EMUL_CONTINUE)
1522 return ret;
1523
1524 err_code = selector & 0xfffc;
15fc0752 1525 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1526
fc058680 1527 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1528 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1529 goto exception;
1530
1531 if (!seg_desc.p) {
1532 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1533 goto exception;
1534 }
1535
dde7e6d1 1536 dpl = seg_desc.dpl;
dde7e6d1
AK		 1537
1538 switch (seg) {
1539 case VCPU_SREG_SS:
1540 /*
1541 * segment is not a writable data segment or segment
1542 * selector's RPL != CPL or segment selector's RPL != CPL
1543 */
1544 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1545 goto exception;
6aa8b732 1546 break;
dde7e6d1
AK		 1547 case VCPU_SREG_CS:
1548 if (!(seg_desc.type & 8))
1549 goto exception;
1550
1551 if (seg_desc.type & 4) {
1552 /* conforming */
1553 if (dpl > cpl)
1554 goto exception;
1555 } else {
1556 /* nonconforming */
1557 if (rpl > cpl || dpl != cpl)
1558 goto exception;
1559 }
040c8dc8
NA		 1560 /* in long-mode d/b must be clear if l is set */
1561 if (seg_desc.d && seg_desc.l) {
1562 u64 efer = 0;
1563
1564 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1565 if (efer & EFER_LMA)
1566 goto exception;
1567 }
1568
dde7e6d1
AK		 1569 /* CS(RPL) <- CPL */
1570 selector = (selector & 0xfffc) | cpl;
6aa8b732 1571 break;
dde7e6d1
AK		 1572 case VCPU_SREG_TR:
1573 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1574 goto exception;
869be99c
AK		 1575 old_desc = seg_desc;
1576 seg_desc.type |= 2; /* busy */
1577 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1578 sizeof(seg_desc), &ctxt->exception);
1579 if (ret != X86EMUL_CONTINUE)
1580 return ret;
dde7e6d1
AK		 1581 break;
1582 case VCPU_SREG_LDTR:
1583 if (seg_desc.s || seg_desc.type != 2)
1584 goto exception;
1585 break;
1586 default: /* DS, ES, FS, or GS */
4e62417b 1587 /*
dde7e6d1
AK		 1588 * segment is not a data or readable code segment or
1589 * ((segment is a data or nonconforming code segment)
1590 * and (both RPL and CPL > DPL))
4e62417b 1591 */
dde7e6d1
AK		 1592 if ((seg_desc.type & 0xa) == 0x8 ||
1593 (((seg_desc.type & 0xc) != 0xc) &&
1594 (rpl > dpl && cpl > dpl)))
1595 goto exception;
6aa8b732 1596 break;
dde7e6d1
AK		 1597 }
1598
1599 if (seg_desc.s) {
1600 /* mark segment as accessed */
1601 seg_desc.type |= 1;
7b105ca2 1602 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1603 if (ret != X86EMUL_CONTINUE)
1604 return ret;
e37a75a1
NA		 1605 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1606 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1607 sizeof(base3), &ctxt->exception);
1608 if (ret != X86EMUL_CONTINUE)
1609 return ret;
9a9abf6b
NA		 1610 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1611 ((u64)base3 << 32)))
1612 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1613 }
1614load:
e37a75a1 1615 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1616 if (desc)
1617 *desc = seg_desc;
dde7e6d1
AK		 1618 return X86EMUL_CONTINUE;
1619exception:
592f0858 1620 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1621}
1622
2356aaeb
PB		 1623static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1624 u16 selector, int seg)
1625{
1626 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1627 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1628}
1629
31be40b3
WY		 1630static void write_register_operand(struct operand *op)
1631{
1632 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1633 switch (op->bytes) {
1634 case 1:
1635 *(u8 *)op->addr.reg = (u8)op->val;
1636 break;
1637 case 2:
1638 *(u16 *)op->addr.reg = (u16)op->val;
1639 break;
1640 case 4:
1641 *op->addr.reg = (u32)op->val;
1642 break; /* 64b: zero-extend */
1643 case 8:
1644 *op->addr.reg = op->val;
1645 break;
1646 }
1647}
1648
fb32b1ed 1649static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1650{
fb32b1ed 1651 switch (op->type) {
dde7e6d1 1652 case OP_REG:
fb32b1ed 1653 write_register_operand(op);
6aa8b732 1654 break;
dde7e6d1 1655 case OP_MEM:
9dac77fa 1656 if (ctxt->lock_prefix)
f5f87dfb
PB		 1657 return segmented_cmpxchg(ctxt,
1658 op->addr.mem,
1659 &op->orig_val,
1660 &op->val,
1661 op->bytes);
1662 else
1663 return segmented_write(ctxt,
fb32b1ed 1664 op->addr.mem,
fb32b1ed
AK		 1665 &op->val,
1666 op->bytes);
a682e354 1667 break;
b3356bf0 1668 case OP_MEM_STR:
f5f87dfb
PB		 1669 return segmented_write(ctxt,
1670 op->addr.mem,
1671 op->data,
1672 op->bytes * op->count);
b3356bf0 1673 break;
1253791d 1674 case OP_XMM:
fb32b1ed 1675 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1676 break;
cbe2c9d3 1677 case OP_MM:
fb32b1ed 1678 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1679 break;
dde7e6d1
AK		 1680 case OP_NONE:
1681 /* no writeback */
414e6277 1682 break;
dde7e6d1 1683 default:
414e6277 1684 break;
6aa8b732 1685 }
dde7e6d1
AK		 1686 return X86EMUL_CONTINUE;
1687}
6aa8b732 1688
51ddff50 1689static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1690{
4179bb02 1691 struct segmented_address addr;
0dc8d10f 1692
5ad105e5 1693 rsp_increment(ctxt, -bytes);
dd856efa 1694 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1695 addr.seg = VCPU_SREG_SS;
1696
51ddff50
AK		 1697 return segmented_write(ctxt, addr, data, bytes);
1698}
1699
1700static int em_push(struct x86_emulate_ctxt *ctxt)
1701{
4179bb02 1702 /* Disable writeback. */
9dac77fa 1703 ctxt->dst.type = OP_NONE;
51ddff50 1704 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1705}
69f55cb1 1706
dde7e6d1 1707static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1708 void *dest, int len)
1709{
dde7e6d1 1710 int rc;
90de84f5 1711 struct segmented_address addr;
8b4caf66 1712
dd856efa 1713 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1714 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1715 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1716 if (rc != X86EMUL_CONTINUE)
1717 return rc;
1718
5ad105e5 1719 rsp_increment(ctxt, len);
dde7e6d1 1720 return rc;
8b4caf66
LV		 1721}
1722
c54fe504
TY		 1723static int em_pop(struct x86_emulate_ctxt *ctxt)
1724{
9dac77fa 1725 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1726}
1727
dde7e6d1 1728static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1729 void *dest, int len)
9de41573
GN		 1730{
1731 int rc;
dde7e6d1
AK		 1732 unsigned long val, change_mask;
1733 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1734 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1735
3b9be3bf 1736 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1737 if (rc != X86EMUL_CONTINUE)
1738 return rc;
9de41573 1739
dde7e6d1 1740 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1741 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1742
dde7e6d1
AK		 1743 switch(ctxt->mode) {
1744 case X86EMUL_MODE_PROT64:
1745 case X86EMUL_MODE_PROT32:
1746 case X86EMUL_MODE_PROT16:
1747 if (cpl == 0)
1748 change_mask |= EFLG_IOPL;
1749 if (cpl <= iopl)
1750 change_mask |= EFLG_IF;
1751 break;
1752 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1753 if (iopl < 3)
1754 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1755 change_mask |= EFLG_IF;
1756 break;
1757 default: /* real mode */
1758 change_mask |= (EFLG_IOPL | EFLG_IF);
1759 break;
9de41573 1760 }
dde7e6d1
AK		 1761
1762 *(unsigned long *)dest =
1763 (ctxt->eflags & ~change_mask) | (val & change_mask);
1764
1765 return rc;
9de41573
GN		 1766}
1767
62aaa2f0
TY		 1768static int em_popf(struct x86_emulate_ctxt *ctxt)
1769{
9dac77fa
AK		 1770 ctxt->dst.type = OP_REG;
1771 ctxt->dst.addr.reg = &ctxt->eflags;
1772 ctxt->dst.bytes = ctxt->op_bytes;
1773 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1774}
1775
612e89f0
AK		 1776static int em_enter(struct x86_emulate_ctxt *ctxt)
1777{
1778 int rc;
1779 unsigned frame_size = ctxt->src.val;
1780 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1781 ulong rbp;
612e89f0
AK		 1782
1783 if (nesting_level)
1784 return X86EMUL_UNHANDLEABLE;
1785
dd856efa
AK		 1786 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1787 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1788 if (rc != X86EMUL_CONTINUE)
1789 return rc;
dd856efa 1790 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1791 stack_mask(ctxt));
dd856efa
AK		 1792 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1793 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1794 stack_mask(ctxt));
1795 return X86EMUL_CONTINUE;
1796}
1797
f47cfa31
AK		 1798static int em_leave(struct x86_emulate_ctxt *ctxt)
1799{
dd856efa 1800 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1801 stack_mask(ctxt));
dd856efa 1802 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1803}
1804
1cd196ea 1805static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1806{
1cd196ea
AK		 1807 int seg = ctxt->src2.val;
1808
9dac77fa 1809 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1810 if (ctxt->op_bytes == 4) {
1811 rsp_increment(ctxt, -2);
1812 ctxt->op_bytes = 2;
1813 }
7b262e90 1814
4487b3b4 1815 return em_push(ctxt);
7b262e90
GN		 1816}
1817
1cd196ea 1818static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1819{
1cd196ea 1820 int seg = ctxt->src2.val;
dde7e6d1
AK		 1821 unsigned long selector;
1822 int rc;
38ba30ba 1823
9dac77fa 1824 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
1827
a5457e7b
PB		 1828 if (ctxt->modrm_reg == VCPU_SREG_SS)
1829 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1830
7b105ca2 1831 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1832 return rc;
38ba30ba
GN		 1833}
1834
b96a7fad 1835static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1836{
dd856efa 1837 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1838 int rc = X86EMUL_CONTINUE;
1839 int reg = VCPU_REGS_RAX;
38ba30ba 1840
dde7e6d1
AK		 1841 while (reg <= VCPU_REGS_RDI) {
1842 (reg == VCPU_REGS_RSP) ?
dd856efa 1843 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1844
4487b3b4 1845 rc = em_push(ctxt);
dde7e6d1
AK		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
38ba30ba 1848
dde7e6d1 1849 ++reg;
38ba30ba 1850 }
38ba30ba 1851
dde7e6d1 1852 return rc;
38ba30ba
GN		 1853}
1854
62aaa2f0
TY		 1855static int em_pushf(struct x86_emulate_ctxt *ctxt)
1856{
9dac77fa 1857 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1858 return em_push(ctxt);
1859}
1860
b96a7fad 1861static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1862{
dde7e6d1
AK		 1863 int rc = X86EMUL_CONTINUE;
1864 int reg = VCPU_REGS_RDI;
38ba30ba 1865
dde7e6d1
AK		 1866 while (reg >= VCPU_REGS_RAX) {
1867 if (reg == VCPU_REGS_RSP) {
5ad105e5 1868 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1869 --reg;
1870 }
38ba30ba 1871
dd856efa 1872 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1873 if (rc != X86EMUL_CONTINUE)
1874 break;
1875 --reg;
38ba30ba 1876 }
dde7e6d1 1877 return rc;
38ba30ba
GN		 1878}
1879
dd856efa 1880static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1881{
0225fb50 1882 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1883 int rc;
6e154e56
MG		 1884 struct desc_ptr dt;
1885 gva_t cs_addr;
1886 gva_t eip_addr;
1887 u16 cs, eip;
6e154e56
MG		 1888
1889 /* TODO: Add limit checks */
9dac77fa 1890 ctxt->src.val = ctxt->eflags;
4487b3b4 1891 rc = em_push(ctxt);
5c56e1cf
AK		 1892 if (rc != X86EMUL_CONTINUE)
1893 return rc;
6e154e56
MG		 1894
1895 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1896
9dac77fa 1897 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1898 rc = em_push(ctxt);
5c56e1cf
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
6e154e56 1901
9dac77fa 1902 ctxt->src.val = ctxt->_eip;
4487b3b4 1903 rc = em_push(ctxt);
5c56e1cf
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
1906
4bff1e86 1907 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1908
1909 eip_addr = dt.address + (irq << 2);
1910 cs_addr = dt.address + (irq << 2) + 2;
1911
0f65dd70 1912 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1913 if (rc != X86EMUL_CONTINUE)
1914 return rc;
1915
0f65dd70 1916 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
1919
7b105ca2 1920 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1921 if (rc != X86EMUL_CONTINUE)
1922 return rc;
1923
9dac77fa 1924 ctxt->_eip = eip;
6e154e56
MG		 1925
1926 return rc;
1927}
1928
dd856efa
AK		 1929int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1930{
1931 int rc;
1932
1933 invalidate_registers(ctxt);
1934 rc = __emulate_int_real(ctxt, irq);
1935 if (rc == X86EMUL_CONTINUE)
1936 writeback_registers(ctxt);
1937 return rc;
1938}
1939
7b105ca2 1940static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1941{
1942 switch(ctxt->mode) {
1943 case X86EMUL_MODE_REAL:
dd856efa 1944 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1945 case X86EMUL_MODE_VM86:
1946 case X86EMUL_MODE_PROT16:
1947 case X86EMUL_MODE_PROT32:
1948 case X86EMUL_MODE_PROT64:
1949 default:
1950 /* Protected mode interrupts unimplemented yet */
1951 return X86EMUL_UNHANDLEABLE;
1952 }
1953}
1954
7b105ca2 1955static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1956{
dde7e6d1
AK		 1957 int rc = X86EMUL_CONTINUE;
1958 unsigned long temp_eip = 0;
1959 unsigned long temp_eflags = 0;
1960 unsigned long cs = 0;
1961 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1962 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1963 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1964 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1965
dde7e6d1 1966 /* TODO: Add stack limit check */
38ba30ba 1967
9dac77fa 1968 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1969
dde7e6d1
AK		 1970 if (rc != X86EMUL_CONTINUE)
1971 return rc;
38ba30ba 1972
35d3d4a1
AK		 1973 if (temp_eip & ~0xffff)
1974 return emulate_gp(ctxt, 0);
38ba30ba 1975
9dac77fa 1976 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1977
dde7e6d1
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 return rc;
38ba30ba 1980
9dac77fa 1981 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1982
dde7e6d1
AK		 1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
38ba30ba 1985
7b105ca2 1986 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1987
dde7e6d1
AK		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
38ba30ba 1990
9dac77fa 1991 ctxt->_eip = temp_eip;
38ba30ba 1992
38ba30ba 1993
9dac77fa 1994 if (ctxt->op_bytes == 4)
dde7e6d1 1995 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1996 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1997 ctxt->eflags &= ~0xffff;
1998 ctxt->eflags |= temp_eflags;
38ba30ba 1999 }
dde7e6d1
AK		 2000
2001 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2002 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2003
2004 return rc;
38ba30ba
GN		 2005}
2006
e01991e7 2007static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2008{
dde7e6d1
AK		 2009 switch(ctxt->mode) {
2010 case X86EMUL_MODE_REAL:
7b105ca2 2011 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2012 case X86EMUL_MODE_VM86:
2013 case X86EMUL_MODE_PROT16:
2014 case X86EMUL_MODE_PROT32:
2015 case X86EMUL_MODE_PROT64:
c37eda13 2016 default:
dde7e6d1
AK		 2017 /* iret from protected mode unimplemented yet */
2018 return X86EMUL_UNHANDLEABLE;
c37eda13 2019 }
c37eda13
WY		 2020}
2021
d2f62766
TY		 2022static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2023{
d2f62766 2024 int rc;
d1442d85
NA		 2025 unsigned short sel, old_sel;
2026 struct desc_struct old_desc, new_desc;
2027 const struct x86_emulate_ops *ops = ctxt->ops;
2028 u8 cpl = ctxt->ops->cpl(ctxt);
2029
2030 /* Assignment of RIP may only fail in 64-bit mode */
2031 if (ctxt->mode == X86EMUL_MODE_PROT64)
2032 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2033 VCPU_SREG_CS);
d2f62766 2034
9dac77fa 2035 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2036
d1442d85
NA		 2037 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2038 &new_desc);
d2f62766
TY		 2039 if (rc != X86EMUL_CONTINUE)
2040 return rc;
2041
d50eaa18 2042 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2043 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2044 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2045 /* assigning eip failed; restore the old cs */
2046 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2047 return rc;
2048 }
2049 return rc;
d2f62766
TY		 2050}
2051
f7784046 2052static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2053{
f7784046
NA		 2054 return assign_eip_near(ctxt, ctxt->src.val);
2055}
8cdbd2c9 2056
f7784046
NA		 2057static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2058{
2059 int rc;
2060 long int old_eip;
2061
2062 old_eip = ctxt->_eip;
2063 rc = assign_eip_near(ctxt, ctxt->src.val);
2064 if (rc != X86EMUL_CONTINUE)
2065 return rc;
2066 ctxt->src.val = old_eip;
2067 rc = em_push(ctxt);
4179bb02 2068 return rc;
8cdbd2c9
LV		 2069}
2070
e0dac408 2071static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2072{
9dac77fa 2073 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2074
aaa05f24
NA		 2075 if (ctxt->dst.bytes == 16)
2076 return X86EMUL_UNHANDLEABLE;
2077
dd856efa
AK		 2078 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2079 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2080 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2081 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2082 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2083 } else {
dd856efa
AK		 2084 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2085 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2086
05f086f8 2087 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2088 }
1b30eaa8 2089 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2090}
2091
ebda02c2
TY		 2092static int em_ret(struct x86_emulate_ctxt *ctxt)
2093{
234f3ce4
NA		 2094 int rc;
2095 unsigned long eip;
2096
2097 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2098 if (rc != X86EMUL_CONTINUE)
2099 return rc;
2100
2101 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2102}
2103
e01991e7 2104static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2105{
a77ab5ea 2106 int rc;
d1442d85
NA		 2107 unsigned long eip, cs;
2108 u16 old_cs;
9e8919ae 2109 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2110 struct desc_struct old_desc, new_desc;
2111 const struct x86_emulate_ops *ops = ctxt->ops;
2112
2113 if (ctxt->mode == X86EMUL_MODE_PROT64)
2114 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2115 VCPU_SREG_CS);
a77ab5ea 2116
d1442d85 2117 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2118 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2119 return rc;
9dac77fa 2120 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2121 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2122 return rc;
9e8919ae
NA		 2123 /* Outer-privilege level return is not implemented */
2124 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2125 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2126 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2127 &new_desc);
2128 if (rc != X86EMUL_CONTINUE)
2129 return rc;
d50eaa18 2130 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2131 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2132 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2133 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2134 }
a77ab5ea
AK		 2135 return rc;
2136}
2137
3261107e
BR		 2138static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2139{
2140 int rc;
2141
2142 rc = em_ret_far(ctxt);
2143 if (rc != X86EMUL_CONTINUE)
2144 return rc;
2145 rsp_increment(ctxt, ctxt->src.val);
2146 return X86EMUL_CONTINUE;
2147}
2148
e940b5c2
TY		 2149static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2150{
2151 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2152 ctxt->dst.orig_val = ctxt->dst.val;
2153 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2154 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2155 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2156 fastop(ctxt, em_cmp);
e940b5c2
TY		 2157
2158 if (ctxt->eflags & EFLG_ZF) {
2159 /* Success: write back to memory. */
2160 ctxt->dst.val = ctxt->src.orig_val;
2161 } else {
2162 /* Failure: write the value we saw to EAX. */
2163 ctxt->dst.type = OP_REG;
dd856efa 2164 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2165 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2166 }
2167 return X86EMUL_CONTINUE;
2168}
2169
d4b4325f 2170static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2171{
d4b4325f 2172 int seg = ctxt->src2.val;
09b5f4d3
WY		 2173 unsigned short sel;
2174 int rc;
2175
9dac77fa 2176 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2177
7b105ca2 2178 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2179 if (rc != X86EMUL_CONTINUE)
2180 return rc;
2181
9dac77fa 2182 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2183 return rc;
2184}
2185
7b105ca2 2186static void
e66bb2cc 2187setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2188 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2189{
e66bb2cc 2190 cs->l = 0; /* will be adjusted later */
79168fd1 2191 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2192 cs->g = 1; /* 4kb granularity */
79168fd1 2193 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2194 cs->type = 0x0b; /* Read, Execute, Accessed */
2195 cs->s = 1;
2196 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2197 cs->p = 1;
2198 cs->d = 1;
99245b50 2199 cs->avl = 0;
e66bb2cc 2200
79168fd1
GN		 2201 set_desc_base(ss, 0); /* flat segment */
2202 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2203 ss->g = 1; /* 4kb granularity */
2204 ss->s = 1;
2205 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2206 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2207 ss->dpl = 0;
79168fd1 2208 ss->p = 1;
99245b50
GN		 2209 ss->l = 0;
2210 ss->avl = 0;
e66bb2cc
AP		 2211}
2212
1a18a69b
AK		 2213static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2214{
2215 u32 eax, ebx, ecx, edx;
2216
2217 eax = ecx = 0;
0017f93a
AK		 2218 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2219 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2220 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2221 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2222}
2223
c2226fc9
SB		 2224static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2225{
0225fb50 2226 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2227 u32 eax, ebx, ecx, edx;
2228
2229 /*
2230 * syscall should always be enabled in longmode - so only become
2231 * vendor specific (cpuid) if other modes are active...
2232 */
2233 if (ctxt->mode == X86EMUL_MODE_PROT64)
2234 return true;
2235
2236 eax = 0x00000000;
2237 ecx = 0x00000000;
0017f93a
AK		 2238 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2239 /*
2240 * Intel ("GenuineIntel")
2241 * remark: Intel CPUs only support "syscall" in 64bit
2242 * longmode. Also an 64bit guest with a
2243 * 32bit compat-app running will #UD !! While this
2244 * behaviour can be fixed (by emulating) into AMD
2245 * response - CPUs of AMD can't behave like Intel.
2246 */
2247 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2248 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2249 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2250 return false;
2251
2252 /* AMD ("AuthenticAMD") */
2253 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2254 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2255 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2256 return true;
2257
2258 /* AMD ("AMDisbetter!") */
2259 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2260 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2261 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2262 return true;
c2226fc9
SB		 2263
2264 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2265 return false;
2266}
2267
e01991e7 2268static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2269{
0225fb50 2270 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2271 struct desc_struct cs, ss;
e66bb2cc 2272 u64 msr_data;
79168fd1 2273 u16 cs_sel, ss_sel;
c2ad2bb3 2274 u64 efer = 0;
e66bb2cc
AP		 2275
2276 /* syscall is not available in real mode */
2e901c4c 2277 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2278 ctxt->mode == X86EMUL_MODE_VM86)
2279 return emulate_ud(ctxt);
e66bb2cc 2280
c2226fc9
SB		 2281 if (!(em_syscall_is_enabled(ctxt)))
2282 return emulate_ud(ctxt);
2283
c2ad2bb3 2284 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2285 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2286
c2226fc9
SB		 2287 if (!(efer & EFER_SCE))
2288 return emulate_ud(ctxt);
2289
717746e3 2290 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2291 msr_data >>= 32;
79168fd1
GN		 2292 cs_sel = (u16)(msr_data & 0xfffc);
2293 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2294
c2ad2bb3 2295 if (efer & EFER_LMA) {
79168fd1 2296 cs.d = 0;
e66bb2cc
AP		 2297 cs.l = 1;
2298 }
1aa36616
AK		 2299 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2300 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2301
dd856efa 2302 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2303 if (efer & EFER_LMA) {
e66bb2cc 2304#ifdef CONFIG_X86_64
6c6cb69b 2305 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2306
717746e3 2307 ops->get_msr(ctxt,
3fb1b5db
GN		 2308 ctxt->mode == X86EMUL_MODE_PROT64 ?
2309 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2310 ctxt->_eip = msr_data;
e66bb2cc 2311
717746e3 2312 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2313 ctxt->eflags &= ~msr_data;
807c1425 2314 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2315#endif
2316 } else {
2317 /* legacy mode */
717746e3 2318 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2319 ctxt->_eip = (u32)msr_data;
e66bb2cc 2320
6c6cb69b 2321 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2322 }
2323
e54cfa97 2324 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2325}
2326
e01991e7 2327static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2328{
0225fb50 2329 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2330 struct desc_struct cs, ss;
8c604352 2331 u64 msr_data;
79168fd1 2332 u16 cs_sel, ss_sel;
c2ad2bb3 2333 u64 efer = 0;
8c604352 2334
7b105ca2 2335 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2336 /* inject #GP if in real mode */
35d3d4a1
AK		 2337 if (ctxt->mode == X86EMUL_MODE_REAL)
2338 return emulate_gp(ctxt, 0);
8c604352 2339
1a18a69b
AK		 2340 /*
2341 * Not recognized on AMD in compat mode (but is recognized in legacy
2342 * mode).
2343 */
2344 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2345 && !vendor_intel(ctxt))
2346 return emulate_ud(ctxt);
2347
b2c9d43e 2348 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2349 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2350 return X86EMUL_UNHANDLEABLE;
8c604352 2351
7b105ca2 2352 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2353
717746e3 2354 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2355 switch (ctxt->mode) {
2356 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2357 if ((msr_data & 0xfffc) == 0x0)
2358 return emulate_gp(ctxt, 0);
8c604352
AP		 2359 break;
2360 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2361 if (msr_data == 0x0)
2362 return emulate_gp(ctxt, 0);
8c604352 2363 break;
9d1b39a9
GN		 2364 default:
2365 break;
8c604352
AP		 2366 }
2367
6c6cb69b 2368 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2369 cs_sel = (u16)msr_data;
2370 cs_sel &= ~SELECTOR_RPL_MASK;
2371 ss_sel = cs_sel + 8;
2372 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2373 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2374 cs.d = 0;
8c604352
AP		 2375 cs.l = 1;
2376 }
2377
1aa36616
AK		 2378 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2379 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2380
717746e3 2381 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2382 ctxt->_eip = msr_data;
8c604352 2383
717746e3 2384 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2385 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2386
e54cfa97 2387 return X86EMUL_CONTINUE;
8c604352
AP		 2388}
2389
e01991e7 2390static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2391{
0225fb50 2392 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2393 struct desc_struct cs, ss;
234f3ce4 2394 u64 msr_data, rcx, rdx;
4668f050 2395 int usermode;
1249b96e 2396 u16 cs_sel = 0, ss_sel = 0;
4668f050 2397
a0044755
GN		 2398 /* inject #GP if in real mode or Virtual 8086 mode */
2399 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2400 ctxt->mode == X86EMUL_MODE_VM86)
2401 return emulate_gp(ctxt, 0);
4668f050 2402
7b105ca2 2403 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2404
9dac77fa 2405 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2406 usermode = X86EMUL_MODE_PROT64;
2407 else
2408 usermode = X86EMUL_MODE_PROT32;
2409
234f3ce4
NA		 2410 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2411 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2412
4668f050
AP		 2413 cs.dpl = 3;
2414 ss.dpl = 3;
717746e3 2415 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2416 switch (usermode) {
2417 case X86EMUL_MODE_PROT32:
79168fd1 2418 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2419 if ((msr_data & 0xfffc) == 0x0)
2420 return emulate_gp(ctxt, 0);
79168fd1 2421 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2422 rcx = (u32)rcx;
2423 rdx = (u32)rdx;
4668f050
AP		 2424 break;
2425 case X86EMUL_MODE_PROT64:
79168fd1 2426 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2427 if (msr_data == 0x0)
2428 return emulate_gp(ctxt, 0);
79168fd1
GN		 2429 ss_sel = cs_sel + 8;
2430 cs.d = 0;
4668f050 2431 cs.l = 1;
234f3ce4
NA		 2432 if (is_noncanonical_address(rcx) ||
2433 is_noncanonical_address(rdx))
2434 return emulate_gp(ctxt, 0);
4668f050
AP		 2435 break;
2436 }
79168fd1
GN		 2437 cs_sel |= SELECTOR_RPL_MASK;
2438 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2439
1aa36616
AK		 2440 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2441 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2442
234f3ce4
NA		 2443 ctxt->_eip = rdx;
2444 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2445
e54cfa97 2446 return X86EMUL_CONTINUE;
4668f050
AP		 2447}
2448
7b105ca2 2449static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2450{
2451 int iopl;
2452 if (ctxt->mode == X86EMUL_MODE_REAL)
2453 return false;
2454 if (ctxt->mode == X86EMUL_MODE_VM86)
2455 return true;
2456 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2457 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2458}
2459
2460static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2461 u16 port, u16 len)
2462{
0225fb50 2463 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2464 struct desc_struct tr_seg;
5601d05b 2465 u32 base3;
f850e2e6 2466 int r;
1aa36616 2467 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2468 unsigned mask = (1 << len) - 1;
5601d05b 2469 unsigned long base;
f850e2e6 2470
1aa36616 2471 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2472 if (!tr_seg.p)
f850e2e6 2473 return false;
79168fd1 2474 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2475 return false;
5601d05b
GN		 2476 base = get_desc_base(&tr_seg);
2477#ifdef CONFIG_X86_64
2478 base |= ((u64)base3) << 32;
2479#endif
0f65dd70 2480 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2481 if (r != X86EMUL_CONTINUE)
2482 return false;
79168fd1 2483 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2484 return false;
0f65dd70 2485 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2486 if (r != X86EMUL_CONTINUE)
2487 return false;
2488 if ((perm >> bit_idx) & mask)
2489 return false;
2490 return true;
2491}
2492
2493static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2494 u16 port, u16 len)
2495{
4fc40f07
GN		 2496 if (ctxt->perm_ok)
2497 return true;
2498
7b105ca2
TY		 2499 if (emulator_bad_iopl(ctxt))
2500 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2501 return false;
4fc40f07
GN		 2502
2503 ctxt->perm_ok = true;
2504
f850e2e6
GN		 2505 return true;
2506}
2507
38ba30ba 2508static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2509 struct tss_segment_16 *tss)
2510{
9dac77fa 2511 tss->ip = ctxt->_eip;
38ba30ba 2512 tss->flag = ctxt->eflags;
dd856efa
AK		 2513 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2514 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2515 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2516 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2517 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2518 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2519 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2520 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2521
1aa36616
AK		 2522 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2523 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2524 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2525 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2526 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2527}
2528
2529static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2530 struct tss_segment_16 *tss)
2531{
38ba30ba 2532 int ret;
2356aaeb 2533 u8 cpl;
38ba30ba 2534
9dac77fa 2535 ctxt->_eip = tss->ip;
38ba30ba 2536 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2537 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2538 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2539 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2540 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2541 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2542 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2543 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2544 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2545
2546 /*
2547 * SDM says that segment selectors are loaded before segment
2548 * descriptors
2549 */
1aa36616
AK		 2550 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2551 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2552 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2553 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2554 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2555
2356aaeb
PB		 2556 cpl = tss->cs & 3;
2557
38ba30ba 2558 /*
fc058680 2559 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2560 * it is handled in a context of new task
2561 */
d1442d85
NA		 2562 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2563 true, NULL);
38ba30ba
GN		 2564 if (ret != X86EMUL_CONTINUE)
2565 return ret;
d1442d85
NA		 2566 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2567 true, NULL);
38ba30ba
GN		 2568 if (ret != X86EMUL_CONTINUE)
2569 return ret;
d1442d85
NA		 2570 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2571 true, NULL);
38ba30ba
GN		 2572 if (ret != X86EMUL_CONTINUE)
2573 return ret;
d1442d85
NA		 2574 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2575 true, NULL);
38ba30ba
GN		 2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
d1442d85
NA		 2578 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2579 true, NULL);
38ba30ba
GN		 2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
2582
2583 return X86EMUL_CONTINUE;
2584}
2585
2586static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2587 u16 tss_selector, u16 old_tss_sel,
2588 ulong old_tss_base, struct desc_struct *new_desc)
2589{
0225fb50 2590 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2591 struct tss_segment_16 tss_seg;
2592 int ret;
bcc55cba 2593 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2594
0f65dd70 2595 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2596 &ctxt->exception);
db297e3d 2597 if (ret != X86EMUL_CONTINUE)
38ba30ba 2598 return ret;
38ba30ba 2599
7b105ca2 2600 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2601
0f65dd70 2602 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2603 &ctxt->exception);
db297e3d 2604 if (ret != X86EMUL_CONTINUE)
38ba30ba 2605 return ret;
38ba30ba 2606
0f65dd70 2607 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2608 &ctxt->exception);
db297e3d 2609 if (ret != X86EMUL_CONTINUE)
38ba30ba 2610 return ret;
38ba30ba
GN		 2611
2612 if (old_tss_sel != 0xffff) {
2613 tss_seg.prev_task_link = old_tss_sel;
2614
0f65dd70 2615 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2616 &tss_seg.prev_task_link,
2617 sizeof tss_seg.prev_task_link,
0f65dd70 2618 &ctxt->exception);
db297e3d 2619 if (ret != X86EMUL_CONTINUE)
38ba30ba 2620 return ret;
38ba30ba
GN		 2621 }
2622
7b105ca2 2623 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2624}
2625
2626static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2627 struct tss_segment_32 *tss)
2628{
5c7411e2 2629 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2630 tss->eip = ctxt->_eip;
38ba30ba 2631 tss->eflags = ctxt->eflags;
dd856efa
AK		 2632 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2633 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2634 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2635 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2636 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2637 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2638 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2639 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2640
1aa36616
AK		 2641 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2642 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2643 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2644 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2645 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2646 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2647}
2648
2649static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2650 struct tss_segment_32 *tss)
2651{
38ba30ba 2652 int ret;
2356aaeb 2653 u8 cpl;
38ba30ba 2654
7b105ca2 2655 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2656 return emulate_gp(ctxt, 0);
9dac77fa 2657 ctxt->_eip = tss->eip;
38ba30ba 2658 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2659
2660 /* General purpose registers */
dd856efa
AK		 2661 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2662 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2663 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2664 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2665 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2666 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2667 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2668 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2669
2670 /*
2671 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2672 * descriptors. This is important because CPL checks will
2673 * use CS.RPL.
38ba30ba 2674 */
1aa36616
AK		 2675 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2676 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2677 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2678 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2679 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2680 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2681 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2682
4cee4798
KW		 2683 /*
2684 * If we're switching between Protected Mode and VM86, we need to make
2685 * sure to update the mode before loading the segment descriptors so
2686 * that the selectors are interpreted correctly.
4cee4798 2687 */
2356aaeb 2688 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2689 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2690 cpl = 3;
2691 } else {
4cee4798 2692 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2693 cpl = tss->cs & 3;
2694 }
4cee4798 2695
38ba30ba
GN		 2696 /*
2697 * Now load segment descriptors. If fault happenes at this stage
2698 * it is handled in a context of new task
2699 */
d1442d85
NA		 2700 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2701 cpl, true, NULL);
38ba30ba
GN		 2702 if (ret != X86EMUL_CONTINUE)
2703 return ret;
d1442d85
NA		 2704 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2705 true, NULL);
38ba30ba
GN		 2706 if (ret != X86EMUL_CONTINUE)
2707 return ret;
d1442d85
NA		 2708 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2709 true, NULL);
38ba30ba
GN		 2710 if (ret != X86EMUL_CONTINUE)
2711 return ret;
d1442d85
NA		 2712 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2713 true, NULL);
38ba30ba
GN		 2714 if (ret != X86EMUL_CONTINUE)
2715 return ret;
d1442d85
NA		 2716 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2717 true, NULL);
38ba30ba
GN		 2718 if (ret != X86EMUL_CONTINUE)
2719 return ret;
d1442d85
NA		 2720 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2721 true, NULL);
38ba30ba
GN		 2722 if (ret != X86EMUL_CONTINUE)
2723 return ret;
d1442d85
NA		 2724 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2725 true, NULL);
38ba30ba
GN		 2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
2728
2729 return X86EMUL_CONTINUE;
2730}
2731
2732static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2733 u16 tss_selector, u16 old_tss_sel,
2734 ulong old_tss_base, struct desc_struct *new_desc)
2735{
0225fb50 2736 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2737 struct tss_segment_32 tss_seg;
2738 int ret;
bcc55cba 2739 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2740 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2741 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2742
0f65dd70 2743 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2744 &ctxt->exception);
db297e3d 2745 if (ret != X86EMUL_CONTINUE)
38ba30ba 2746 /* FIXME: need to provide precise fault address */
38ba30ba 2747 return ret;
38ba30ba 2748
7b105ca2 2749 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2750
5c7411e2
NA		 2751 /* Only GP registers and segment selectors are saved */
2752 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2753 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2754 if (ret != X86EMUL_CONTINUE)
38ba30ba 2755 /* FIXME: need to provide precise fault address */
38ba30ba 2756 return ret;
38ba30ba 2757
0f65dd70 2758 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2759 &ctxt->exception);
db297e3d 2760 if (ret != X86EMUL_CONTINUE)
38ba30ba 2761 /* FIXME: need to provide precise fault address */
38ba30ba 2762 return ret;
38ba30ba
GN		 2763
2764 if (old_tss_sel != 0xffff) {
2765 tss_seg.prev_task_link = old_tss_sel;
2766
0f65dd70 2767 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2768 &tss_seg.prev_task_link,
2769 sizeof tss_seg.prev_task_link,
0f65dd70 2770 &ctxt->exception);
db297e3d 2771 if (ret != X86EMUL_CONTINUE)
38ba30ba 2772 /* FIXME: need to provide precise fault address */
38ba30ba 2773 return ret;
38ba30ba
GN		 2774 }
2775
7b105ca2 2776 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2777}
2778
2779static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2780 u16 tss_selector, int idt_index, int reason,
e269fb21 2781 bool has_error_code, u32 error_code)
38ba30ba 2782{
0225fb50 2783 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2784 struct desc_struct curr_tss_desc, next_tss_desc;
2785 int ret;
1aa36616 2786 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2787 ulong old_tss_base =
4bff1e86 2788 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2789 u32 desc_limit;
e919464b 2790 ulong desc_addr;
38ba30ba
GN		 2791
2792 /* FIXME: old_tss_base == ~0 ? */
2793
e919464b 2794 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2795 if (ret != X86EMUL_CONTINUE)
2796 return ret;
e919464b 2797 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2798 if (ret != X86EMUL_CONTINUE)
2799 return ret;
2800
2801 /* FIXME: check that next_tss_desc is tss */
2802
7f3d35fd
KW		 2803 /*
2804 * Check privileges. The three cases are task switch caused by...
2805 *
2806 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2807 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2808 * 3. jmp/call to TSS/task-gate: No check is performed since the
2809 * hardware checks it before exiting.
7f3d35fd
KW		 2810 */
2811 if (reason == TASK_SWITCH_GATE) {
2812 if (idt_index != -1) {
2813 /* Software interrupts */
2814 struct desc_struct task_gate_desc;
2815 int dpl;
2816
2817 ret = read_interrupt_descriptor(ctxt, idt_index,
2818 &task_gate_desc);
2819 if (ret != X86EMUL_CONTINUE)
2820 return ret;
2821
2822 dpl = task_gate_desc.dpl;
2823 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2824 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2825 }
38ba30ba
GN		 2826 }
2827
ceffb459
GN		 2828 desc_limit = desc_limit_scaled(&next_tss_desc);
2829 if (!next_tss_desc.p ||
2830 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2831 desc_limit < 0x2b)) {
592f0858 2832 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2833 }
2834
2835 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2836 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2837 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2838 }
2839
2840 if (reason == TASK_SWITCH_IRET)
2841 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2842
2843 /* set back link to prev task only if NT bit is set in eflags
fc058680 2844 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2845 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2846 old_tss_sel = 0xffff;
2847
2848 if (next_tss_desc.type & 8)
7b105ca2 2849 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2850 old_tss_base, &next_tss_desc);
2851 else
7b105ca2 2852 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2853 old_tss_base, &next_tss_desc);
0760d448
JK		 2854 if (ret != X86EMUL_CONTINUE)
2855 return ret;
38ba30ba
GN		 2856
2857 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2858 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2859
2860 if (reason != TASK_SWITCH_IRET) {
2861 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2862 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2863 }
2864
717746e3 2865 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2866 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2867
e269fb21 2868 if (has_error_code) {
9dac77fa
AK		 2869 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2870 ctxt->lock_prefix = 0;
2871 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2872 ret = em_push(ctxt);
e269fb21
JK		 2873 }
2874
38ba30ba
GN		 2875 return ret;
2876}
2877
2878int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2879 u16 tss_selector, int idt_index, int reason,
e269fb21 2880 bool has_error_code, u32 error_code)
38ba30ba 2881{
38ba30ba
GN		 2882 int rc;
2883
dd856efa 2884 invalidate_registers(ctxt);
9dac77fa
AK		 2885 ctxt->_eip = ctxt->eip;
2886 ctxt->dst.type = OP_NONE;
38ba30ba 2887
7f3d35fd 2888 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2889 has_error_code, error_code);
38ba30ba 2890
dd856efa 2891 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2892 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2893 writeback_registers(ctxt);
2894 }
38ba30ba 2895
a0c0ab2f 2896 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2897}
2898
f3bd64c6
GN		 2899static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2900 struct operand *op)
a682e354 2901{
b3356bf0 2902 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2903
01485a22
PB		 2904 register_address_increment(ctxt, reg, df * op->bytes);
2905 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2906}
2907
7af04fc0
AK		 2908static int em_das(struct x86_emulate_ctxt *ctxt)
2909{
7af04fc0
AK		 2910 u8 al, old_al;
2911 bool af, cf, old_cf;
2912
2913 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2914 al = ctxt->dst.val;
7af04fc0
AK		 2915
2916 old_al = al;
2917 old_cf = cf;
2918 cf = false;
2919 af = ctxt->eflags & X86_EFLAGS_AF;
2920 if ((al & 0x0f) > 9 || af) {
2921 al -= 6;
2922 cf = old_cf | (al >= 250);
2923 af = true;
2924 } else {
2925 af = false;
2926 }
2927 if (old_al > 0x99 || old_cf) {
2928 al -= 0x60;
2929 cf = true;
2930 }
2931
9dac77fa 2932 ctxt->dst.val = al;
7af04fc0 2933 /* Set PF, ZF, SF */
9dac77fa
AK		 2934 ctxt->src.type = OP_IMM;
2935 ctxt->src.val = 0;
2936 ctxt->src.bytes = 1;
158de57f 2937 fastop(ctxt, em_or);
7af04fc0
AK		 2938 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2939 if (cf)
2940 ctxt->eflags |= X86_EFLAGS_CF;
2941 if (af)
2942 ctxt->eflags |= X86_EFLAGS_AF;
2943 return X86EMUL_CONTINUE;
2944}
2945
a035d5c6
PB		 2946static int em_aam(struct x86_emulate_ctxt *ctxt)
2947{
2948 u8 al, ah;
2949
2950 if (ctxt->src.val == 0)
2951 return emulate_de(ctxt);
2952
2953 al = ctxt->dst.val & 0xff;
2954 ah = al / ctxt->src.val;
2955 al %= ctxt->src.val;
2956
2957 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2958
2959 /* Set PF, ZF, SF */
2960 ctxt->src.type = OP_IMM;
2961 ctxt->src.val = 0;
2962 ctxt->src.bytes = 1;
2963 fastop(ctxt, em_or);
2964
2965 return X86EMUL_CONTINUE;
2966}
2967
7f662273
GN		 2968static int em_aad(struct x86_emulate_ctxt *ctxt)
2969{
2970 u8 al = ctxt->dst.val & 0xff;
2971 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2972
2973 al = (al + (ah * ctxt->src.val)) & 0xff;
2974
2975 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2976
f583c29b
GN		 2977 /* Set PF, ZF, SF */
2978 ctxt->src.type = OP_IMM;
2979 ctxt->src.val = 0;
2980 ctxt->src.bytes = 1;
2981 fastop(ctxt, em_or);
7f662273
GN		 2982
2983 return X86EMUL_CONTINUE;
2984}
2985
d4ddafcd
TY		 2986static int em_call(struct x86_emulate_ctxt *ctxt)
2987{
234f3ce4 2988 int rc;
d4ddafcd
TY		 2989 long rel = ctxt->src.val;
2990
2991 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2992 rc = jmp_rel(ctxt, rel);
2993 if (rc != X86EMUL_CONTINUE)
2994 return rc;
d4ddafcd
TY		 2995 return em_push(ctxt);
2996}
2997
0ef753b8
AK		 2998static int em_call_far(struct x86_emulate_ctxt *ctxt)
2999{
0ef753b8
AK		 3000 u16 sel, old_cs;
3001 ulong old_eip;
3002 int rc;
d1442d85
NA		 3003 struct desc_struct old_desc, new_desc;
3004 const struct x86_emulate_ops *ops = ctxt->ops;
3005 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3006
9dac77fa 3007 old_eip = ctxt->_eip;
d1442d85 3008 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3009
9dac77fa 3010 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3011 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3012 &new_desc);
3013 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3014 return X86EMUL_CONTINUE;
3015
d50eaa18 3016 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3017 if (rc != X86EMUL_CONTINUE)
3018 goto fail;
0ef753b8 3019
9dac77fa 3020 ctxt->src.val = old_cs;
4487b3b4 3021 rc = em_push(ctxt);
0ef753b8 3022 if (rc != X86EMUL_CONTINUE)
d1442d85 3023 goto fail;
0ef753b8 3024
9dac77fa 3025 ctxt->src.val = old_eip;
d1442d85
NA		 3026 rc = em_push(ctxt);
3027 /* If we failed, we tainted the memory, but the very least we should
3028 restore cs */
3029 if (rc != X86EMUL_CONTINUE)
3030 goto fail;
3031 return rc;
3032fail:
3033 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3034 return rc;
3035
0ef753b8
AK		 3036}
3037
40ece7c7
AK		 3038static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3039{
40ece7c7 3040 int rc;
234f3ce4 3041 unsigned long eip;
40ece7c7 3042
234f3ce4
NA		 3043 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3044 if (rc != X86EMUL_CONTINUE)
3045 return rc;
3046 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3047 if (rc != X86EMUL_CONTINUE)
3048 return rc;
5ad105e5 3049 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3050 return X86EMUL_CONTINUE;
3051}
3052
e4f973ae
TY		 3053static int em_xchg(struct x86_emulate_ctxt *ctxt)
3054{
e4f973ae 3055 /* Write back the register source. */
9dac77fa
AK		 3056 ctxt->src.val = ctxt->dst.val;
3057 write_register_operand(&ctxt->src);
e4f973ae
TY		 3058
3059 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3060 ctxt->dst.val = ctxt->src.orig_val;
3061 ctxt->lock_prefix = 1;
e4f973ae
TY		 3062 return X86EMUL_CONTINUE;
3063}
3064
5c82aa29
AK		 3065static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3066{
9dac77fa 3067 ctxt->dst.val = ctxt->src2.val;
4d758349 3068 return fastop(ctxt, em_imul);
5c82aa29
AK		 3069}
3070
61429142
AK		 3071static int em_cwd(struct x86_emulate_ctxt *ctxt)
3072{
9dac77fa
AK		 3073 ctxt->dst.type = OP_REG;
3074 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3075 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3076 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3077
3078 return X86EMUL_CONTINUE;
3079}
3080
48bb5d3c
AK		 3081static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3082{
48bb5d3c
AK		 3083 u64 tsc = 0;
3084
717746e3 3085 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3086 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3087 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3088 return X86EMUL_CONTINUE;
3089}
3090
222d21aa
AK		 3091static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3092{
3093 u64 pmc;
3094
dd856efa 3095 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3096 return emulate_gp(ctxt, 0);
dd856efa
AK		 3097 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3098 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3099 return X86EMUL_CONTINUE;
3100}
3101
b9eac5f4
AK		 3102static int em_mov(struct x86_emulate_ctxt *ctxt)
3103{
54cfdb3e 3104 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3105 return X86EMUL_CONTINUE;
3106}
3107
84cffe49
BP		 3108#define FFL(x) bit(X86_FEATURE_##x)
3109
3110static int em_movbe(struct x86_emulate_ctxt *ctxt)
3111{
3112 u32 ebx, ecx, edx, eax = 1;
3113 u16 tmp;
3114
3115 /*
3116 * Check MOVBE is set in the guest-visible CPUID leaf.
3117 */
3118 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3119 if (!(ecx & FFL(MOVBE)))
3120 return emulate_ud(ctxt);
3121
3122 switch (ctxt->op_bytes) {
3123 case 2:
3124 /*
3125 * From MOVBE definition: "...When the operand size is 16 bits,
3126 * the upper word of the destination register remains unchanged
3127 * ..."
3128 *
3129 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3130 * rules so we have to do the operation almost per hand.
3131 */
3132 tmp = (u16)ctxt->src.val;
3133 ctxt->dst.val &= ~0xffffUL;
3134 ctxt->dst.val |= (unsigned long)swab16(tmp);
3135 break;
3136 case 4:
3137 ctxt->dst.val = swab32((u32)ctxt->src.val);
3138 break;
3139 case 8:
3140 ctxt->dst.val = swab64(ctxt->src.val);
3141 break;
3142 default:
592f0858 3143 BUG();
84cffe49
BP		 3144 }
3145 return X86EMUL_CONTINUE;
3146}
3147
bc00f8d2
TY		 3148static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3149{
3150 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3151 return emulate_gp(ctxt, 0);
3152
3153 /* Disable writeback. */
3154 ctxt->dst.type = OP_NONE;
3155 return X86EMUL_CONTINUE;
3156}
3157
3158static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3159{
3160 unsigned long val;
3161
3162 if (ctxt->mode == X86EMUL_MODE_PROT64)
3163 val = ctxt->src.val & ~0ULL;
3164 else
3165 val = ctxt->src.val & ~0U;
3166
3167 /* #UD condition is already handled. */
3168 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3169 return emulate_gp(ctxt, 0);
3170
3171 /* Disable writeback. */
3172 ctxt->dst.type = OP_NONE;
3173 return X86EMUL_CONTINUE;
3174}
3175
e1e210b0
TY		 3176static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3177{
3178 u64 msr_data;
3179
dd856efa
AK		 3180 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3181 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3182 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3183 return emulate_gp(ctxt, 0);
3184
3185 return X86EMUL_CONTINUE;
3186}
3187
3188static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3189{
3190 u64 msr_data;
3191
dd856efa 3192 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3193 return emulate_gp(ctxt, 0);
3194
dd856efa
AK		 3195 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3196 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3197 return X86EMUL_CONTINUE;
3198}
3199
1bd5f469
TY		 3200static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3201{
9dac77fa 3202 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3203 return emulate_ud(ctxt);
3204
9dac77fa 3205 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3206 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3207 ctxt->dst.bytes = 2;
1bd5f469
TY		 3208 return X86EMUL_CONTINUE;
3209}
3210
3211static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3212{
9dac77fa 3213 u16 sel = ctxt->src.val;
1bd5f469 3214
9dac77fa 3215 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3216 return emulate_ud(ctxt);
3217
9dac77fa 3218 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3219 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3220
3221 /* Disable writeback. */
9dac77fa
AK		 3222 ctxt->dst.type = OP_NONE;
3223 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3224}
3225
a14e579f
AK		 3226static int em_lldt(struct x86_emulate_ctxt *ctxt)
3227{
3228 u16 sel = ctxt->src.val;
3229
3230 /* Disable writeback. */
3231 ctxt->dst.type = OP_NONE;
3232 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3233}
3234
80890006
AK		 3235static int em_ltr(struct x86_emulate_ctxt *ctxt)
3236{
3237 u16 sel = ctxt->src.val;
3238
3239 /* Disable writeback. */
3240 ctxt->dst.type = OP_NONE;
3241 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3242}
3243
38503911
AK		 3244static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3245{
9fa088f4
AK		 3246 int rc;
3247 ulong linear;
3248
9dac77fa 3249 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3250 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3251 ctxt->ops->invlpg(ctxt, linear);
38503911 3252 /* Disable writeback. */
9dac77fa 3253 ctxt->dst.type = OP_NONE;
38503911
AK		 3254 return X86EMUL_CONTINUE;
3255}
3256
2d04a05b
AK		 3257static int em_clts(struct x86_emulate_ctxt *ctxt)
3258{
3259 ulong cr0;
3260
3261 cr0 = ctxt->ops->get_cr(ctxt, 0);
3262 cr0 &= ~X86_CR0_TS;
3263 ctxt->ops->set_cr(ctxt, 0, cr0);
3264 return X86EMUL_CONTINUE;
3265}
3266
26d05cc7
AK		 3267static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3268{
0f54a321 3269 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3270
26d05cc7
AK		 3271 if (rc != X86EMUL_CONTINUE)
3272 return rc;
3273
3274 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3275 ctxt->_eip = ctxt->eip;
26d05cc7 3276 /* Disable writeback. */
9dac77fa 3277 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3278 return X86EMUL_CONTINUE;
3279}
3280
96051572
AK		 3281static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3282 void (*get)(struct x86_emulate_ctxt *ctxt,
3283 struct desc_ptr *ptr))
3284{
3285 struct desc_ptr desc_ptr;
3286
3287 if (ctxt->mode == X86EMUL_MODE_PROT64)
3288 ctxt->op_bytes = 8;
3289 get(ctxt, &desc_ptr);
3290 if (ctxt->op_bytes == 2) {
3291 ctxt->op_bytes = 4;
3292 desc_ptr.address &= 0x00ffffff;
3293 }
3294 /* Disable writeback. */
3295 ctxt->dst.type = OP_NONE;
3296 return segmented_write(ctxt, ctxt->dst.addr.mem,
3297 &desc_ptr, 2 + ctxt->op_bytes);
3298}
3299
3300static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3301{
3302 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3303}
3304
3305static int em_sidt(struct x86_emulate_ctxt *ctxt)
3306{
3307 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3308}
3309
5b7f6a1e 3310static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3311{
26d05cc7
AK		 3312 struct desc_ptr desc_ptr;
3313 int rc;
3314
510425ff
AK		 3315 if (ctxt->mode == X86EMUL_MODE_PROT64)
3316 ctxt->op_bytes = 8;
9dac77fa 3317 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3318 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3319 ctxt->op_bytes);
26d05cc7
AK		 3320 if (rc != X86EMUL_CONTINUE)
3321 return rc;
9a9abf6b
NA		 3322 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3323 is_noncanonical_address(desc_ptr.address))
3324 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3325 if (lgdt)
3326 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3327 else
3328 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3329 /* Disable writeback. */
9dac77fa 3330 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3331 return X86EMUL_CONTINUE;
3332}
3333
5b7f6a1e
NA		 3334static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3335{
3336 return em_lgdt_lidt(ctxt, true);
3337}
3338
5ef39c71 3339static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3340{
26d05cc7
AK		 3341 int rc;
3342
5ef39c71
AK		 3343 rc = ctxt->ops->fix_hypercall(ctxt);
3344
26d05cc7 3345 /* Disable writeback. */
9dac77fa 3346 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3347 return rc;
3348}
3349
3350static int em_lidt(struct x86_emulate_ctxt *ctxt)
3351{
5b7f6a1e 3352 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3353}
3354
3355static int em_smsw(struct x86_emulate_ctxt *ctxt)
3356{
32e94d06
NA		 3357 if (ctxt->dst.type == OP_MEM)
3358 ctxt->dst.bytes = 2;
9dac77fa 3359 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3360 return X86EMUL_CONTINUE;
3361}
3362
3363static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3364{
26d05cc7 3365 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3366 | (ctxt->src.val & 0x0f));
3367 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3368 return X86EMUL_CONTINUE;
3369}
3370
d06e03ad
TY		 3371static int em_loop(struct x86_emulate_ctxt *ctxt)
3372{
234f3ce4
NA		 3373 int rc = X86EMUL_CONTINUE;
3374
01485a22 3375 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3376 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3377 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3378 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3379
234f3ce4 3380 return rc;
d06e03ad
TY		 3381}
3382
3383static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3384{
234f3ce4
NA		 3385 int rc = X86EMUL_CONTINUE;
3386
dd856efa 3387 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3388 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3389
234f3ce4 3390 return rc;
d06e03ad
TY		 3391}
3392
d7841a4b
TY		 3393static int em_in(struct x86_emulate_ctxt *ctxt)
3394{
3395 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3396 &ctxt->dst.val))
3397 return X86EMUL_IO_NEEDED;
3398
3399 return X86EMUL_CONTINUE;
3400}
3401
3402static int em_out(struct x86_emulate_ctxt *ctxt)
3403{
3404 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3405 &ctxt->src.val, 1);
3406 /* Disable writeback. */
3407 ctxt->dst.type = OP_NONE;
3408 return X86EMUL_CONTINUE;
3409}
3410
f411e6cd
TY		 3411static int em_cli(struct x86_emulate_ctxt *ctxt)
3412{
3413 if (emulator_bad_iopl(ctxt))
3414 return emulate_gp(ctxt, 0);
3415
3416 ctxt->eflags &= ~X86_EFLAGS_IF;
3417 return X86EMUL_CONTINUE;
3418}
3419
3420static int em_sti(struct x86_emulate_ctxt *ctxt)
3421{
3422 if (emulator_bad_iopl(ctxt))
3423 return emulate_gp(ctxt, 0);
3424
3425 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3426 ctxt->eflags |= X86_EFLAGS_IF;
3427 return X86EMUL_CONTINUE;
3428}
3429
6d6eede4
AK		 3430static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3431{
3432 u32 eax, ebx, ecx, edx;
3433
dd856efa
AK		 3434 eax = reg_read(ctxt, VCPU_REGS_RAX);
3435 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3436 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3437 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3438 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3439 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3440 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3441 return X86EMUL_CONTINUE;
3442}
3443
98f73630
PB		 3444static int em_sahf(struct x86_emulate_ctxt *ctxt)
3445{
3446 u32 flags;
3447
3448 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3449 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3450
3451 ctxt->eflags &= ~0xffUL;
3452 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3453 return X86EMUL_CONTINUE;
3454}
3455
2dd7caa0
AK		 3456static int em_lahf(struct x86_emulate_ctxt *ctxt)
3457{
dd856efa
AK		 3458 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3459 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3460 return X86EMUL_CONTINUE;
3461}
3462
9299836e
AK		 3463static int em_bswap(struct x86_emulate_ctxt *ctxt)
3464{
3465 switch (ctxt->op_bytes) {
3466#ifdef CONFIG_X86_64
3467 case 8:
3468 asm("bswap %0" : "+r"(ctxt->dst.val));
3469 break;
3470#endif
3471 default:
3472 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3473 break;
3474 }
3475 return X86EMUL_CONTINUE;
3476}
3477
13e457e0
NA		 3478static int em_clflush(struct x86_emulate_ctxt *ctxt)
3479{
3480 /* emulating clflush regardless of cpuid */
3481 return X86EMUL_CONTINUE;
3482}
3483
cfec82cb
JR		 3484static bool valid_cr(int nr)
3485{
3486 switch (nr) {
3487 case 0:
3488 case 2 ... 4:
3489 case 8:
3490 return true;
3491 default:
3492 return false;
3493 }
3494}
3495
3496static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3497{
9dac77fa 3498 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3499 return emulate_ud(ctxt);
3500
3501 return X86EMUL_CONTINUE;
3502}
3503
3504static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3505{
9dac77fa
AK		 3506 u64 new_val = ctxt->src.val64;
3507 int cr = ctxt->modrm_reg;
c2ad2bb3 3508 u64 efer = 0;
cfec82cb
JR		 3509
3510 static u64 cr_reserved_bits[] = {
3511 0xffffffff00000000ULL,
3512 0, 0, 0, /* CR3 checked later */
3513 CR4_RESERVED_BITS,
3514 0, 0, 0,
3515 CR8_RESERVED_BITS,
3516 };
3517
3518 if (!valid_cr(cr))
3519 return emulate_ud(ctxt);
3520
3521 if (new_val & cr_reserved_bits[cr])
3522 return emulate_gp(ctxt, 0);
3523
3524 switch (cr) {
3525 case 0: {
c2ad2bb3 3526 u64 cr4;
cfec82cb
JR		 3527 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3528 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3529 return emulate_gp(ctxt, 0);
3530
717746e3
AK		 3531 cr4 = ctxt->ops->get_cr(ctxt, 4);
3532 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3533
3534 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3535 !(cr4 & X86_CR4_PAE))
3536 return emulate_gp(ctxt, 0);
3537
3538 break;
3539 }
3540 case 3: {
3541 u64 rsvd = 0;
3542
c2ad2bb3
AK		 3543 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3544 if (efer & EFER_LMA)
9d88fca7 3545 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3546
3547 if (new_val & rsvd)
3548 return emulate_gp(ctxt, 0);
3549
3550 break;
3551 }
3552 case 4: {
717746e3 3553 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3554
3555 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3556 return emulate_gp(ctxt, 0);
3557
3558 break;
3559 }
3560 }
3561
3562 return X86EMUL_CONTINUE;
3563}
3564
3b88e41a
JR		 3565static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3566{
3567 unsigned long dr7;
3568
717746e3 3569 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3570
3571 /* Check if DR7.Global_Enable is set */
3572 return dr7 & (1 << 13);
3573}
3574
3575static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3576{
9dac77fa 3577 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3578 u64 cr4;
3579
3580 if (dr > 7)
3581 return emulate_ud(ctxt);
3582
717746e3 3583 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3584 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3585 return emulate_ud(ctxt);
3586
6d2a0526
NA		 3587 if (check_dr7_gd(ctxt)) {
3588 ulong dr6;
3589
3590 ctxt->ops->get_dr(ctxt, 6, &dr6);
3591 dr6 &= ~15;
3592 dr6 |= DR6_BD | DR6_RTM;
3593 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3594 return emulate_db(ctxt);
6d2a0526 3595 }
3b88e41a
JR		 3596
3597 return X86EMUL_CONTINUE;
3598}
3599
3600static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3601{
9dac77fa
AK		 3602 u64 new_val = ctxt->src.val64;
3603 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3604
3605 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3606 return emulate_gp(ctxt, 0);
3607
3608 return check_dr_read(ctxt);
3609}
3610
01de8b09
JR		 3611static int check_svme(struct x86_emulate_ctxt *ctxt)
3612{
3613 u64 efer;
3614
717746e3 3615 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3616
3617 if (!(efer & EFER_SVME))
3618 return emulate_ud(ctxt);
3619
3620 return X86EMUL_CONTINUE;
3621}
3622
3623static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3624{
dd856efa 3625 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3626
3627 /* Valid physical address? */
d4224449 3628 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3629 return emulate_gp(ctxt, 0);
3630
3631 return check_svme(ctxt);
3632}
3633
d7eb8203
JR		 3634static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3635{
717746e3 3636 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3637
717746e3 3638 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3639 return emulate_ud(ctxt);
3640
3641 return X86EMUL_CONTINUE;
3642}
3643
8061252e
JR		 3644static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3645{
717746e3 3646 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3647 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3648
717746e3 3649 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3650 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3651 return emulate_gp(ctxt, 0);
3652
3653 return X86EMUL_CONTINUE;
3654}
3655
f6511935
JR		 3656static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3657{
9dac77fa
AK		 3658 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3659 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3660 return emulate_gp(ctxt, 0);
3661
3662 return X86EMUL_CONTINUE;
3663}
3664
3665static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3666{
9dac77fa
AK		 3667 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3668 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3669 return emulate_gp(ctxt, 0);
3670
3671 return X86EMUL_CONTINUE;
3672}
3673
73fba5f4 3674#define D(_y) { .flags = (_y) }
d40a6898
PB		 3675#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3676#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3677 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3678#define N D(NotImpl)
01de8b09 3679#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3680#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3681#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3682#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3683#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3684#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3685#define II(_f, _e, _i) \
d40a6898 3686 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3687#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3688 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3689 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3690#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3691
8d8f4e9f 3692#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3693#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3694#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3695#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3696#define I2bvIP(_f, _e, _i, _p) \
3697 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3698
fb864fbc
AK		 3699#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3700 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3701 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3702
0f54a321
NA		 3703static const struct opcode group7_rm0[] = {
3704 N,
3705 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3706 N, N, N, N, N, N,
3707};
3708
fd0a0d82 3709static const struct opcode group7_rm1[] = {
1c2545be
TY		 3710 DI(SrcNone | Priv, monitor),
3711 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3712 N, N, N, N, N, N,
3713};
3714
fd0a0d82 3715static const struct opcode group7_rm3[] = {
1c2545be 3716 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3717 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3718 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3719 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3720 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3721 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3722 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3723 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3724};
6230f7fc 3725
fd0a0d82 3726static const struct opcode group7_rm7[] = {
d7eb8203 3727 N,
1c2545be 3728 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3729 N, N, N, N, N, N,
3730};
d67fc27a 3731
fd0a0d82 3732static const struct opcode group1[] = {
fb864fbc
AK		 3733 F(Lock, em_add),
3734 F(Lock | PageTable, em_or),
3735 F(Lock, em_adc),
3736 F(Lock, em_sbb),
3737 F(Lock | PageTable, em_and),
3738 F(Lock, em_sub),
3739 F(Lock, em_xor),
3740 F(NoWrite, em_cmp),
73fba5f4
AK		 3741};
3742
fd0a0d82 3743static const struct opcode group1A[] = {
1c2545be 3744 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3745};
3746
007a3b54
AK		 3747static const struct opcode group2[] = {
3748 F(DstMem | ModRM, em_rol),
3749 F(DstMem | ModRM, em_ror),
3750 F(DstMem | ModRM, em_rcl),
3751 F(DstMem | ModRM, em_rcr),
3752 F(DstMem | ModRM, em_shl),
3753 F(DstMem | ModRM, em_shr),
3754 F(DstMem | ModRM, em_shl),
3755 F(DstMem | ModRM, em_sar),
3756};
3757
fd0a0d82 3758static const struct opcode group3[] = {
fb864fbc
AK		 3759 F(DstMem | SrcImm | NoWrite, em_test),
3760 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3761 F(DstMem | SrcNone | Lock, em_not),
3762 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3763 F(DstXacc | Src2Mem, em_mul_ex),
3764 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3765 F(DstXacc | Src2Mem, em_div_ex),
3766 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3767};
3768
fd0a0d82 3769static const struct opcode group4[] = {
95413dc4
AK		 3770 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3771 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3772 N, N, N, N, N, N,
3773};
3774
fd0a0d82 3775static const struct opcode group5[] = {
95413dc4
AK		 3776 F(DstMem | SrcNone | Lock, em_inc),
3777 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3778 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3779 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3780 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3781 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3782 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3783};
3784
fd0a0d82 3785static const struct opcode group6[] = {
1c2545be
TY		 3786 DI(Prot, sldt),
3787 DI(Prot, str),
a14e579f 3788 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3789 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3790 N, N, N, N,
3791};
3792
fd0a0d82 3793static const struct group_dual group7 = { {
606b1c3e
NA		 3794 II(Mov | DstMem, em_sgdt, sgdt),
3795 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3796 II(SrcMem | Priv, em_lgdt, lgdt),
3797 II(SrcMem | Priv, em_lidt, lidt),
3798 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3799 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3800 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3801}, {
0f54a321 3802 EXT(0, group7_rm0),
5ef39c71 3803 EXT(0, group7_rm1),
01de8b09 3804 N, EXT(0, group7_rm3),
1c2545be
TY		 3805 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3806 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3807 EXT(0, group7_rm7),
73fba5f4
AK		 3808} };
3809
fd0a0d82 3810static const struct opcode group8[] = {
73fba5f4 3811 N, N, N, N,
11c363ba
AK		 3812 F(DstMem | SrcImmByte | NoWrite, em_bt),
3813 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3814 F(DstMem | SrcImmByte | Lock, em_btr),
3815 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3816};
3817
fd0a0d82 3818static const struct group_dual group9 = { {
1c2545be 3819 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3820}, {
3821 N, N, N, N, N, N, N, N,
3822} };
3823
fd0a0d82 3824static const struct opcode group11[] = {
1c2545be 3825 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3826 X7(D(Undefined)),
a4d4a7c1
AK		 3827};
3828
13e457e0 3829static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3830 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3831};
3832
3833static const struct group_dual group15 = { {
3834 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3835}, {
3836 N, N, N, N, N, N, N, N,
3837} };
3838
fd0a0d82 3839static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3840 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3841};
3842
d5b77069
PB		 3843static const struct gprefix pfx_0f_2b = {
3844 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3845};
3846
27ce8258 3847static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3848 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3849};
3850
0a37027e
AW		 3851static const struct gprefix pfx_0f_e7 = {
3852 N, I(Sse, em_mov), N, N,
3853};
3854
045a282c
GN		 3855static const struct escape escape_d9 = { {
3856 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3857}, {
3858 /* 0xC0 - 0xC7 */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xC8 - 0xCF */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xD0 - 0xC7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xD8 - 0xDF */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xE0 - 0xE7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xE8 - 0xEF */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xF0 - 0xF7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xF8 - 0xFF */
3873 N, N, N, N, N, N, N, N,
3874} };
3875
3876static const struct escape escape_db = { {
3877 N, N, N, N, N, N, N, N,
3878}, {
3879 /* 0xC0 - 0xC7 */
3880 N, N, N, N, N, N, N, N,
3881 /* 0xC8 - 0xCF */
3882 N, N, N, N, N, N, N, N,
3883 /* 0xD0 - 0xC7 */
3884 N, N, N, N, N, N, N, N,
3885 /* 0xD8 - 0xDF */
3886 N, N, N, N, N, N, N, N,
3887 /* 0xE0 - 0xE7 */
3888 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3889 /* 0xE8 - 0xEF */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xF0 - 0xF7 */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xF8 - 0xFF */
3894 N, N, N, N, N, N, N, N,
3895} };
3896
3897static const struct escape escape_dd = { {
3898 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3899}, {
3900 /* 0xC0 - 0xC7 */
3901 N, N, N, N, N, N, N, N,
3902 /* 0xC8 - 0xCF */
3903 N, N, N, N, N, N, N, N,
3904 /* 0xD0 - 0xC7 */
3905 N, N, N, N, N, N, N, N,
3906 /* 0xD8 - 0xDF */
3907 N, N, N, N, N, N, N, N,
3908 /* 0xE0 - 0xE7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xE8 - 0xEF */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xF0 - 0xF7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xF8 - 0xFF */
3915 N, N, N, N, N, N, N, N,
3916} };
3917
fd0a0d82 3918static const struct opcode opcode_table[256] = {
73fba5f4 3919 /* 0x00 - 0x07 */
fb864fbc 3920 F6ALU(Lock, em_add),
1cd196ea
AK		 3921 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3922 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3923 /* 0x08 - 0x0F */
fb864fbc 3924 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3925 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3926 N,
73fba5f4 3927 /* 0x10 - 0x17 */
fb864fbc 3928 F6ALU(Lock, em_adc),
1cd196ea
AK		 3929 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3930 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3931 /* 0x18 - 0x1F */
fb864fbc 3932 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3933 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3934 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3935 /* 0x20 - 0x27 */
fb864fbc 3936 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3937 /* 0x28 - 0x2F */
fb864fbc 3938 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3939 /* 0x30 - 0x37 */
fb864fbc 3940 F6ALU(Lock, em_xor), N, N,
73fba5f4 3941 /* 0x38 - 0x3F */
fb864fbc 3942 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3943 /* 0x40 - 0x4F */
95413dc4 3944 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3945 /* 0x50 - 0x57 */
63540382 3946 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3947 /* 0x58 - 0x5F */
c54fe504 3948 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3949 /* 0x60 - 0x67 */
b96a7fad
TY		 3950 I(ImplicitOps | Stack | No64, em_pusha),
3951 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3952 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3953 N, N, N, N,
3954 /* 0x68 - 0x6F */
d46164db
AK		 3955 I(SrcImm | Mov | Stack, em_push),
3956 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3957 I(SrcImmByte | Mov | Stack, em_push),
3958 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3959 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3960 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3961 /* 0x70 - 0x7F */
58b7075d 3962 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3963 /* 0x80 - 0x87 */
1c2545be
TY		 3964 G(ByteOp | DstMem | SrcImm, group1),
3965 G(DstMem | SrcImm, group1),
3966 G(ByteOp | DstMem | SrcImm | No64, group1),
3967 G(DstMem | SrcImmByte, group1),
fb864fbc 3968 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3969 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3970 /* 0x88 - 0x8F */
d5ae7ce8 3971 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3972 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3973 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3974 D(ModRM | SrcMem | NoAccess | DstReg),
3975 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3976 G(0, group1A),
73fba5f4 3977 /* 0x90 - 0x97 */
bf608f88 3978 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3979 /* 0x98 - 0x9F */
61429142 3980 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3981 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3982 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3983 II(ImplicitOps | Stack, em_popf, popf),
3984 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3985 /* 0xA0 - 0xA7 */
b9eac5f4 3986 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3987 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3988 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 3989 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 3990 /* 0xA8 - 0xAF */
fb864fbc 3991 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3992 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3993 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 3994 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 3995 /* 0xB0 - 0xB7 */
b9eac5f4 3996 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3997 /* 0xB8 - 0xBF */
5e2c6883 3998 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3999 /* 0xC0 - 0xC7 */
007a3b54 4000 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4001 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4002 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4003 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4004 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4005 G(ByteOp, group11), G(0, group11),
73fba5f4 4006 /* 0xC8 - 0xCF */
612e89f0 4007 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4008 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4009 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4010 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4011 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4012 /* 0xD0 - 0xD7 */
007a3b54
AK		 4013 G(Src2One | ByteOp, group2), G(Src2One, group2),
4014 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4015 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4016 I(DstAcc | SrcImmUByte | No64, em_aad),
4017 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4018 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4019 /* 0xD8 - 0xDF */
045a282c 4020 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4021 /* 0xE0 - 0xE7 */
58b7075d
NA		 4022 X3(I(SrcImmByte | NearBranch, em_loop)),
4023 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4024 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4025 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4026 /* 0xE8 - 0xEF */
58b7075d
NA		 4027 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4028 I(SrcImmFAddr | No64, em_jmp_far),
4029 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4030 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4031 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4032 /* 0xF0 - 0xF7 */
bf608f88 4033 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4034 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4035 G(ByteOp, group3), G(0, group3),
73fba5f4 4036 /* 0xF8 - 0xFF */
f411e6cd
TY		 4037 D(ImplicitOps), D(ImplicitOps),
4038 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4039 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4040};
4041
fd0a0d82 4042static const struct opcode twobyte_table[256] = {
73fba5f4 4043 /* 0x00 - 0x0F */
dee6bb70 4044 G(0, group6), GD(0, &group7), N, N,
b51e974f 4045 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4046 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4047 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4048 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4049 /* 0x10 - 0x1F */
103f98ea 4050 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4051 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4052 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4053 /* 0x20 - 0x2F */
9b88ae99
NA		 4054 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4055 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4056 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4057 check_cr_write),
4058 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4059 check_dr_write),
73fba5f4 4060 N, N, N, N,
27ce8258
IM		 4061 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4062 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4063 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4064 N, N, N, N,
73fba5f4 4065 /* 0x30 - 0x3F */
e1e210b0 4066 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4067 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4068 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4069 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4070 I(ImplicitOps | EmulateOnUD, em_sysenter),
4071 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4072 N, N,
73fba5f4
AK		 4073 N, N, N, N, N, N, N, N,
4074 /* 0x40 - 0x4F */
140bad89 4075 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4076 /* 0x50 - 0x5F */
4077 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4078 /* 0x60 - 0x6F */
aa97bb48
AK		 4079 N, N, N, N,
4080 N, N, N, N,
4081 N, N, N, N,
4082 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4083 /* 0x70 - 0x7F */
aa97bb48
AK		 4084 N, N, N, N,
4085 N, N, N, N,
4086 N, N, N, N,
4087 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4088 /* 0x80 - 0x8F */
58b7075d 4089 X16(D(SrcImm | NearBranch)),
73fba5f4 4090 /* 0x90 - 0x9F */
ee45b58e 4091 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4092 /* 0xA0 - 0xA7 */
1cd196ea 4093 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4094 II(ImplicitOps, em_cpuid, cpuid),
4095 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4096 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4097 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4098 /* 0xA8 - 0xAF */
1cd196ea 4099 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4100 DI(ImplicitOps, rsm),
11c363ba 4101 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4102 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4103 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4104 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4105 /* 0xB0 - 0xB7 */
e940b5c2 4106 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4107 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4108 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4109 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4110 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4111 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4112 /* 0xB8 - 0xBF */
4113 N, N,
ce7faab2 4114 G(BitOp, group8),
11c363ba
AK		 4115 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4116 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4117 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4118 /* 0xC0 - 0xC7 */
e47a5f5f 4119 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
ed9aad21 4120 N, I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov),
73fba5f4 4121 N, N, N, GD(0, &group9),
9299836e
AK		 4122 /* 0xC8 - 0xCF */
4123 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4124 /* 0xD0 - 0xDF */
4125 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4126 /* 0xE0 - 0xEF */
0a37027e
AW		 4127 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4128 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4129 /* 0xF0 - 0xFF */
4130 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4131};
4132
0bc5eedb 4133static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4134 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4135};
4136
4137static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4138 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4139};
4140
4141/*
4142 * Insns below are selected by the prefix which indexed by the third opcode
4143 * byte.
4144 */
4145static const struct opcode opcode_map_0f_38[256] = {
4146 /* 0x00 - 0x7f */
4147 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4148 /* 0x80 - 0xef */
4149 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4150 /* 0xf0 - 0xf1 */
4151 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4152 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4153 /* 0xf2 - 0xff */
4154 N, N, X4(N), X8(N)
0bc5eedb
BP		 4155};
4156
73fba5f4
AK		 4157#undef D
4158#undef N
4159#undef G
4160#undef GD
4161#undef I
aa97bb48 4162#undef GP
01de8b09 4163#undef EXT
73fba5f4 4164
8d8f4e9f 4165#undef D2bv
f6511935 4166#undef D2bvIP
8d8f4e9f 4167#undef I2bv
d7841a4b 4168#undef I2bvIP
d67fc27a 4169#undef I6ALU
8d8f4e9f 4170
9dac77fa 4171static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4172{
4173 unsigned size;
4174
9dac77fa 4175 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4176 if (size == 8)
4177 size = 4;
4178 return size;
4179}
4180
4181static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4182 unsigned size, bool sign_extension)
4183{
39f21ee5
AK		 4184 int rc = X86EMUL_CONTINUE;
4185
4186 op->type = OP_IMM;
4187 op->bytes = size;
9dac77fa 4188 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4189 /* NB. Immediates are sign-extended as necessary. */
4190 switch (op->bytes) {
4191 case 1:
e85a1085 4192 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4193 break;
4194 case 2:
e85a1085 4195 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4196 break;
4197 case 4:
e85a1085 4198 op->val = insn_fetch(s32, ctxt);
39f21ee5 4199 break;
5e2c6883
NA		 4200 case 8:
4201 op->val = insn_fetch(s64, ctxt);
4202 break;
39f21ee5
AK		 4203 }
4204 if (!sign_extension) {
4205 switch (op->bytes) {
4206 case 1:
4207 op->val &= 0xff;
4208 break;
4209 case 2:
4210 op->val &= 0xffff;
4211 break;
4212 case 4:
4213 op->val &= 0xffffffff;
4214 break;
4215 }
4216 }
4217done:
4218 return rc;
4219}
4220
a9945549
AK		 4221static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4222 unsigned d)
4223{
4224 int rc = X86EMUL_CONTINUE;
4225
4226 switch (d) {
4227 case OpReg:
2adb5ad9 4228 decode_register_operand(ctxt, op);
a9945549
AK		 4229 break;
4230 case OpImmUByte:
608aabe3 4231 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4232 break;
4233 case OpMem:
41ddf978 4234 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4235 mem_common:
4236 *op = ctxt->memop;
4237 ctxt->memopp = op;
96888977 4238 if (ctxt->d & BitOp)
a9945549
AK		 4239 fetch_bit_operand(ctxt);
4240 op->orig_val = op->val;
4241 break;
41ddf978 4242 case OpMem64:
aaa05f24 4243 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4244 goto mem_common;
a9945549
AK		 4245 case OpAcc:
4246 op->type = OP_REG;
4247 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4248 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4249 fetch_register_operand(op);
4250 op->orig_val = op->val;
4251 break;
820207c8
AK		 4252 case OpAccLo:
4253 op->type = OP_REG;
4254 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4255 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4256 fetch_register_operand(op);
4257 op->orig_val = op->val;
4258 break;
4259 case OpAccHi:
4260 if (ctxt->d & ByteOp) {
4261 op->type = OP_NONE;
4262 break;
4263 }
4264 op->type = OP_REG;
4265 op->bytes = ctxt->op_bytes;
4266 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4267 fetch_register_operand(op);
4268 op->orig_val = op->val;
4269 break;
a9945549
AK		 4270 case OpDI:
4271 op->type = OP_MEM;
4272 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4273 op->addr.mem.ea =
01485a22 4274 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4275 op->addr.mem.seg = VCPU_SREG_ES;
4276 op->val = 0;
b3356bf0 4277 op->count = 1;
a9945549
AK		 4278 break;
4279 case OpDX:
4280 op->type = OP_REG;
4281 op->bytes = 2;
dd856efa 4282 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4283 fetch_register_operand(op);
4284 break;
4dd6a57d
AK		 4285 case OpCL:
4286 op->bytes = 1;
dd856efa 4287 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4288 break;
4289 case OpImmByte:
4290 rc = decode_imm(ctxt, op, 1, true);
4291 break;
4292 case OpOne:
4293 op->bytes = 1;
4294 op->val = 1;
4295 break;
4296 case OpImm:
4297 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4298 break;
5e2c6883
NA		 4299 case OpImm64:
4300 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4301 break;
28867cee
AK		 4302 case OpMem8:
4303 ctxt->memop.bytes = 1;
660696d1 4304 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4305 ctxt->memop.addr.reg = decode_register(ctxt,
4306 ctxt->modrm_rm, true);
660696d1
GN		 4307 fetch_register_operand(&ctxt->memop);
4308 }
28867cee 4309 goto mem_common;
0fe59128
AK		 4310 case OpMem16:
4311 ctxt->memop.bytes = 2;
4312 goto mem_common;
4313 case OpMem32:
4314 ctxt->memop.bytes = 4;
4315 goto mem_common;
4316 case OpImmU16:
4317 rc = decode_imm(ctxt, op, 2, false);
4318 break;
4319 case OpImmU:
4320 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4321 break;
4322 case OpSI:
4323 op->type = OP_MEM;
4324 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4325 op->addr.mem.ea =
01485a22 4326 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4327 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4328 op->val = 0;
b3356bf0 4329 op->count = 1;
0fe59128 4330 break;
7fa57952
PB		 4331 case OpXLat:
4332 op->type = OP_MEM;
4333 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4334 op->addr.mem.ea =
01485a22 4335 address_mask(ctxt,
7fa57952
PB		 4336 reg_read(ctxt, VCPU_REGS_RBX) +
4337 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4338 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4339 op->val = 0;
4340 break;
0fe59128
AK		 4341 case OpImmFAddr:
4342 op->type = OP_IMM;
4343 op->addr.mem.ea = ctxt->_eip;
4344 op->bytes = ctxt->op_bytes + 2;
4345 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4346 break;
4347 case OpMemFAddr:
4348 ctxt->memop.bytes = ctxt->op_bytes + 2;
4349 goto mem_common;
c191a7a0
AK		 4350 case OpES:
4351 op->val = VCPU_SREG_ES;
4352 break;
4353 case OpCS:
4354 op->val = VCPU_SREG_CS;
4355 break;
4356 case OpSS:
4357 op->val = VCPU_SREG_SS;
4358 break;
4359 case OpDS:
4360 op->val = VCPU_SREG_DS;
4361 break;
4362 case OpFS:
4363 op->val = VCPU_SREG_FS;
4364 break;
4365 case OpGS:
4366 op->val = VCPU_SREG_GS;
4367 break;
a9945549
AK		 4368 case OpImplicit:
4369 /* Special instructions do their own operand decoding. */
4370 default:
4371 op->type = OP_NONE; /* Disable writeback. */
4372 break;
4373 }
4374
4375done:
4376 return rc;
4377}
4378
ef5d75cc 4379int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4380{
dde7e6d1
AK		 4381 int rc = X86EMUL_CONTINUE;
4382 int mode = ctxt->mode;
46561646 4383 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4384 bool op_prefix = false;
573e80fe 4385 bool has_seg_override = false;
46561646 4386 struct opcode opcode;
dde7e6d1 4387
f09ed83e
AK		 4388 ctxt->memop.type = OP_NONE;
4389 ctxt->memopp = NULL;
9dac77fa 4390 ctxt->_eip = ctxt->eip;
17052f16
PB		 4391 ctxt->fetch.ptr = ctxt->fetch.data;
4392 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4393 ctxt->opcode_len = 1;
dc25e89e 4394 if (insn_len > 0)
9dac77fa 4395 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4396 else {
9506d57d 4397 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4398 if (rc != X86EMUL_CONTINUE)
4399 return rc;
4400 }
dde7e6d1
AK		 4401
4402 switch (mode) {
4403 case X86EMUL_MODE_REAL:
4404 case X86EMUL_MODE_VM86:
4405 case X86EMUL_MODE_PROT16:
4406 def_op_bytes = def_ad_bytes = 2;
4407 break;
4408 case X86EMUL_MODE_PROT32:
4409 def_op_bytes = def_ad_bytes = 4;
4410 break;
4411#ifdef CONFIG_X86_64
4412 case X86EMUL_MODE_PROT64:
4413 def_op_bytes = 4;
4414 def_ad_bytes = 8;
4415 break;
4416#endif
4417 default:
1d2887e2 4418 return EMULATION_FAILED;
dde7e6d1
AK		 4419 }
4420
9dac77fa
AK		 4421 ctxt->op_bytes = def_op_bytes;
4422 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4423
4424 /* Legacy prefixes. */
4425 for (;;) {
e85a1085 4426 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4427 case 0x66: /* operand-size override */
0d7cdee8 4428 op_prefix = true;
dde7e6d1 4429 /* switch between 2/4 bytes */
9dac77fa 4430 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4431 break;
4432 case 0x67: /* address-size override */
4433 if (mode == X86EMUL_MODE_PROT64)
4434 /* switch between 4/8 bytes */
9dac77fa 4435 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4436 else
4437 /* switch between 2/4 bytes */
9dac77fa 4438 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4439 break;
4440 case 0x26: /* ES override */
4441 case 0x2e: /* CS override */
4442 case 0x36: /* SS override */
4443 case 0x3e: /* DS override */
573e80fe
BD		 4444 has_seg_override = true;
4445 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4446 break;
4447 case 0x64: /* FS override */
4448 case 0x65: /* GS override */
573e80fe
BD		 4449 has_seg_override = true;
4450 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4451 break;
4452 case 0x40 ... 0x4f: /* REX */
4453 if (mode != X86EMUL_MODE_PROT64)
4454 goto done_prefixes;
9dac77fa 4455 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4456 continue;
4457 case 0xf0: /* LOCK */
9dac77fa 4458 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4459 break;
4460 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4461 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4462 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4463 break;
4464 default:
4465 goto done_prefixes;
4466 }
4467
4468 /* Any legacy prefix after a REX prefix nullifies its effect. */
4469
9dac77fa 4470 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4471 }
4472
4473done_prefixes:
4474
4475 /* REX prefix. */
9dac77fa
AK		 4476 if (ctxt->rex_prefix & 8)
4477 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4478
4479 /* Opcode byte(s). */
9dac77fa 4480 opcode = opcode_table[ctxt->b];
d3ad6243 4481 /* Two-byte opcode? */
9dac77fa 4482 if (ctxt->b == 0x0f) {
1ce19dc1 4483 ctxt->opcode_len = 2;
e85a1085 4484 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4485 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4486
4487 /* 0F_38 opcode map */
4488 if (ctxt->b == 0x38) {
4489 ctxt->opcode_len = 3;
4490 ctxt->b = insn_fetch(u8, ctxt);
4491 opcode = opcode_map_0f_38[ctxt->b];
4492 }
dde7e6d1 4493 }
9dac77fa 4494 ctxt->d = opcode.flags;
dde7e6d1 4495
9f4260e7
TY		 4496 if (ctxt->d & ModRM)
4497 ctxt->modrm = insn_fetch(u8, ctxt);
4498
7fe864dc
NA		 4499 /* vex-prefix instructions are not implemented */
4500 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4501 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4502 ctxt->d = NotImpl;
4503 }
4504
9dac77fa
AK		 4505 while (ctxt->d & GroupMask) {
4506 switch (ctxt->d & GroupMask) {
46561646 4507 case Group:
9dac77fa 4508 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4509 opcode = opcode.u.group[goffset];
4510 break;
4511 case GroupDual:
9dac77fa
AK		 4512 goffset = (ctxt->modrm >> 3) & 7;
4513 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4514 opcode = opcode.u.gdual->mod3[goffset];
4515 else
4516 opcode = opcode.u.gdual->mod012[goffset];
4517 break;
4518 case RMExt:
9dac77fa 4519 goffset = ctxt->modrm & 7;
01de8b09 4520 opcode = opcode.u.group[goffset];
46561646
AK		 4521 break;
4522 case Prefix:
9dac77fa 4523 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4524 return EMULATION_FAILED;
9dac77fa 4525 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4526 switch (simd_prefix) {
4527 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4528 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4529 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4530 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4531 }
4532 break;
045a282c
GN		 4533 case Escape:
4534 if (ctxt->modrm > 0xbf)
4535 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4536 else
4537 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4538 break;
46561646 4539 default:
1d2887e2 4540 return EMULATION_FAILED;
0d7cdee8 4541 }
46561646 4542
b1ea50b2 4543 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4544 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4545 }
4546
e24186e0
PB		 4547 /* Unrecognised? */
4548 if (ctxt->d == 0)
4549 return EMULATION_FAILED;
4550
9dac77fa 4551 ctxt->execute = opcode.u.execute;
dde7e6d1 4552
3a6095a0
NA		 4553 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4554 return EMULATION_FAILED;
4555
d40a6898 4556 if (unlikely(ctxt->d &
ed9aad21
NA		 4557 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4558 No16))) {
d40a6898
PB		 4559 /*
4560 * These are copied unconditionally here, and checked unconditionally
4561 * in x86_emulate_insn.
4562 */
4563 ctxt->check_perm = opcode.check_perm;
4564 ctxt->intercept = opcode.intercept;
dde7e6d1 4565
d40a6898
PB		 4566 if (ctxt->d & NotImpl)
4567 return EMULATION_FAILED;
d867162c 4568
58b7075d
NA		 4569 if (mode == X86EMUL_MODE_PROT64) {
4570 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4571 ctxt->op_bytes = 8;
4572 else if (ctxt->d & NearBranch)
4573 ctxt->op_bytes = 8;
4574 }
7f9b4b75 4575
d40a6898
PB		 4576 if (ctxt->d & Op3264) {
4577 if (mode == X86EMUL_MODE_PROT64)
4578 ctxt->op_bytes = 8;
4579 else
4580 ctxt->op_bytes = 4;
4581 }
4582
ed9aad21
NA		 4583 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4584 ctxt->op_bytes = 4;
4585
d40a6898
PB		 4586 if (ctxt->d & Sse)
4587 ctxt->op_bytes = 16;
4588 else if (ctxt->d & Mmx)
4589 ctxt->op_bytes = 8;
4590 }
1253791d 4591
dde7e6d1 4592 /* ModRM and SIB bytes. */
9dac77fa 4593 if (ctxt->d & ModRM) {
f09ed83e 4594 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4595 if (!has_seg_override) {
4596 has_seg_override = true;
4597 ctxt->seg_override = ctxt->modrm_seg;
4598 }
9dac77fa 4599 } else if (ctxt->d & MemAbs)
f09ed83e 4600 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4601 if (rc != X86EMUL_CONTINUE)
4602 goto done;
4603
573e80fe
BD		 4604 if (!has_seg_override)
4605 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4606
573e80fe 4607 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4608
dde7e6d1
AK		 4609 /*
4610 * Decode and fetch the source operand: register, memory
4611 * or immediate.
4612 */
0fe59128 4613 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4614 if (rc != X86EMUL_CONTINUE)
4615 goto done;
4616
dde7e6d1
AK		 4617 /*
4618 * Decode and fetch the second source operand: register, memory
4619 * or immediate.
4620 */
4dd6a57d 4621 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4622 if (rc != X86EMUL_CONTINUE)
4623 goto done;
4624
dde7e6d1 4625 /* Decode and fetch the destination operand: register or memory. */
a9945549 4626 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4627
41061cdb 4628 if (ctxt->rip_relative)
1c1c35ae
NA		 4629 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4630 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4631
a430c916 4632done:
1d2887e2 4633 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4634}
4635
1cb3f3ae
XG		 4636bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4637{
4638 return ctxt->d & PageTable;
4639}
4640
3e2f65d5
GN		 4641static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4642{
3e2f65d5
GN		 4643 /* The second termination condition only applies for REPE
4644 * and REPNE. Test if the repeat string operation prefix is
4645 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4646 * corresponding termination condition according to:
4647 * - if REPE/REPZ and ZF = 0 then done
4648 * - if REPNE/REPNZ and ZF = 1 then done
4649 */
9dac77fa
AK		 4650 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4651 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4652 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4653 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4654 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4655 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4656 return true;
4657
4658 return false;
4659}
4660
cbe2c9d3
AK		 4661static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4662{
4663 bool fault = false;
4664
4665 ctxt->ops->get_fpu(ctxt);
4666 asm volatile("1: fwait \n\t"
4667 "2: \n\t"
4668 ".pushsection .fixup,\"ax\" \n\t"
4669 "3: \n\t"
4670 "movb $1, %[fault] \n\t"
4671 "jmp 2b \n\t"
4672 ".popsection \n\t"
4673 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4674 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4675 ctxt->ops->put_fpu(ctxt);
4676
4677 if (unlikely(fault))
4678 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4679
4680 return X86EMUL_CONTINUE;
4681}
4682
4683static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4684 struct operand *op)
4685{
4686 if (op->type == OP_MM)
4687 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4688}
4689
e28bbd44
AK		 4690static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4691{
4692 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4693 if (!(ctxt->d & ByteOp))
4694 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4695 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4696 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4697 [fastop]"+S"(fop)
4698 : "c"(ctxt->src2.val));
e28bbd44 4699 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4700 if (!fop) /* exception is returned in fop variable */
4701 return emulate_de(ctxt);
e28bbd44
AK		 4702 return X86EMUL_CONTINUE;
4703}
dd856efa 4704
1498507a
BD		 4705void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4706{
573e80fe
BD		 4707 memset(&ctxt->rip_relative, 0,
4708 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4709
1498507a
BD		 4710 ctxt->io_read.pos = 0;
4711 ctxt->io_read.end = 0;
1498507a
BD		 4712 ctxt->mem_read.end = 0;
4713}
4714
7b105ca2 4715int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4716{
0225fb50 4717 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4718 int rc = X86EMUL_CONTINUE;
9dac77fa 4719 int saved_dst_type = ctxt->dst.type;
8b4caf66 4720
9dac77fa 4721 ctxt->mem_read.pos = 0;
310b5d30 4722
e24186e0
PB		 4723 /* LOCK prefix is allowed only with some instructions */
4724 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4725 rc = emulate_ud(ctxt);
1161624f
GN		 4726 goto done;
4727 }
4728
e24186e0 4729 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4730 rc = emulate_ud(ctxt);
d380a5e4
GN		 4731 goto done;
4732 }
4733
d40a6898
PB		 4734 if (unlikely(ctxt->d &
4735 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4736 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4737 (ctxt->d & Undefined)) {
4738 rc = emulate_ud(ctxt);
4739 goto done;
4740 }
1253791d 4741
d40a6898
PB		 4742 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4743 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4744 rc = emulate_ud(ctxt);
cbe2c9d3 4745 goto done;
d40a6898 4746 }
cbe2c9d3 4747
d40a6898
PB		 4748 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4749 rc = emulate_nm(ctxt);
c4f035c6 4750 goto done;
d40a6898 4751 }
c4f035c6 4752
d40a6898
PB		 4753 if (ctxt->d & Mmx) {
4754 rc = flush_pending_x87_faults(ctxt);
4755 if (rc != X86EMUL_CONTINUE)
4756 goto done;
4757 /*
4758 * Now that we know the fpu is exception safe, we can fetch
4759 * operands from it.
4760 */
4761 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4762 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4763 if (!(ctxt->d & Mov))
4764 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4765 }
e92805ac 4766
685bbf4a 4767 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4768 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4769 X86_ICPT_PRE_EXCEPT);
4770 if (rc != X86EMUL_CONTINUE)
4771 goto done;
4772 }
8ea7d6ae 4773
d40a6898
PB		 4774 /* Privileged instruction can be executed only in CPL=0 */
4775 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4776 if (ctxt->d & PrivUD)
4777 rc = emulate_ud(ctxt);
4778 else
4779 rc = emulate_gp(ctxt, 0);
d09beabd 4780 goto done;
d40a6898 4781 }
d09beabd 4782
d40a6898
PB		 4783 /* Instruction can only be executed in protected mode */
4784 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4785 rc = emulate_ud(ctxt);
c4f035c6 4786 goto done;
d40a6898 4787 }
c4f035c6 4788
d40a6898 4789 /* Do instruction specific permission checks */
685bbf4a 4790 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4791 rc = ctxt->check_perm(ctxt);
4792 if (rc != X86EMUL_CONTINUE)
4793 goto done;
4794 }
4795
685bbf4a 4796 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4797 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4798 X86_ICPT_POST_EXCEPT);
4799 if (rc != X86EMUL_CONTINUE)
4800 goto done;
4801 }
4802
4803 if (ctxt->rep_prefix && (ctxt->d & String)) {
4804 /* All REP prefixes have the same first termination condition */
4805 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4806 ctxt->eip = ctxt->_eip;
4467c3f1 4807 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4808 goto done;
4809 }
b9fa9d6b 4810 }
b9fa9d6b
AK		 4811 }
4812
9dac77fa
AK		 4813 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4814 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4815 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4816 if (rc != X86EMUL_CONTINUE)
8b4caf66 4817 goto done;
9dac77fa 4818 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4819 }
4820
9dac77fa
AK		 4821 if (ctxt->src2.type == OP_MEM) {
4822 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4823 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4824 if (rc != X86EMUL_CONTINUE)
4825 goto done;
4826 }
4827
9dac77fa 4828 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4829 goto special_insn;
4830
4831
9dac77fa 4832 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4833 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4834 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4835 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4836 if (rc != X86EMUL_CONTINUE)
4837 goto done;
038e51de 4838 }
9dac77fa 4839 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4840
018a98db
AK		 4841special_insn:
4842
685bbf4a 4843 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4844 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4845 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4846 if (rc != X86EMUL_CONTINUE)
4847 goto done;
4848 }
4849
b9a1ecb9
NA		 4850 if (ctxt->rep_prefix && (ctxt->d & String))
4851 ctxt->eflags |= EFLG_RF;
4852 else
4853 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4854
9dac77fa 4855 if (ctxt->execute) {
e28bbd44
AK		 4856 if (ctxt->d & Fastop) {
4857 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4858 rc = fastop(ctxt, fop);
4859 if (rc != X86EMUL_CONTINUE)
4860 goto done;
4861 goto writeback;
4862 }
9dac77fa 4863 rc = ctxt->execute(ctxt);
ef65c889
AK		 4864 if (rc != X86EMUL_CONTINUE)
4865 goto done;
4866 goto writeback;
4867 }
4868
1ce19dc1 4869 if (ctxt->opcode_len == 2)
6aa8b732 4870 goto twobyte_insn;
0bc5eedb
BP		 4871 else if (ctxt->opcode_len == 3)
4872 goto threebyte_insn;
6aa8b732 4873
9dac77fa 4874 switch (ctxt->b) {
6aa8b732 4875 case 0x63: /* movsxd */
8b4caf66 4876 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4877 goto cannot_emulate;
9dac77fa 4878 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4879 break;
b2833e3c 4880 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4881 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4882 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4883 break;
7e0b54b1 4884 case 0x8d: /* lea r16/r32, m */
9dac77fa 4885 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4886 break;
3d9e77df 4887 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4888 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4889 ctxt->dst.type = OP_NONE;
4890 else
4891 rc = em_xchg(ctxt);
e4f973ae 4892 break;
e8b6fa70 4893 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4894 switch (ctxt->op_bytes) {
4895 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4896 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4897 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4898 }
4899 break;
6e154e56 4900 case 0xcc: /* int3 */
5c5df76b
TY		 4901 rc = emulate_int(ctxt, 3);
4902 break;
6e154e56 4903 case 0xcd: /* int n */
9dac77fa 4904 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4905 break;
4906 case 0xce: /* into */
5c5df76b
TY		 4907 if (ctxt->eflags & EFLG_OF)
4908 rc = emulate_int(ctxt, 4);
6e154e56 4909 break;
1a52e051 4910 case 0xe9: /* jmp rel */
db5b0762 4911 case 0xeb: /* jmp rel short */
234f3ce4 4912 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4913 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4914 break;
111de5d6 4915 case 0xf4: /* hlt */
6c3287f7 4916 ctxt->ops->halt(ctxt);
19fdfa0d 4917 break;
111de5d6
AK		 4918 case 0xf5: /* cmc */
4919 /* complement carry flag from eflags reg */
4920 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4921 break;
4922 case 0xf8: /* clc */
4923 ctxt->eflags &= ~EFLG_CF;
111de5d6 4924 break;
8744aa9a
MG		 4925 case 0xf9: /* stc */
4926 ctxt->eflags |= EFLG_CF;
4927 break;
fb4616f4
MG		 4928 case 0xfc: /* cld */
4929 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4930 break;
4931 case 0xfd: /* std */
4932 ctxt->eflags |= EFLG_DF;
fb4616f4 4933 break;
91269b8f
AK		 4934 default:
4935 goto cannot_emulate;
6aa8b732 4936 }
018a98db 4937
7d9ddaed
AK		 4938 if (rc != X86EMUL_CONTINUE)
4939 goto done;
4940
018a98db 4941writeback:
fb32b1ed
AK		 4942 if (ctxt->d & SrcWrite) {
4943 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4944 rc = writeback(ctxt, &ctxt->src);
4945 if (rc != X86EMUL_CONTINUE)
4946 goto done;
4947 }
ee212297
NA		 4948 if (!(ctxt->d & NoWrite)) {
4949 rc = writeback(ctxt, &ctxt->dst);
4950 if (rc != X86EMUL_CONTINUE)
4951 goto done;
4952 }
018a98db 4953
5cd21917
GN		 4954 /*
4955 * restore dst type in case the decoding will be reused
4956 * (happens for string instruction )
4957 */
9dac77fa 4958 ctxt->dst.type = saved_dst_type;
5cd21917 4959
9dac77fa 4960 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4961 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4962
9dac77fa 4963 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4964 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4965
9dac77fa 4966 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4967 unsigned int count;
9dac77fa 4968 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4969 if ((ctxt->d & SrcMask) == SrcSI)
4970 count = ctxt->src.count;
4971 else
4972 count = ctxt->dst.count;
01485a22 4973 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 4974
d2ddd1c4
GN		 4975 if (!string_insn_completed(ctxt)) {
4976 /*
4977 * Re-enter guest when pio read ahead buffer is empty
4978 * or, if it is not used, after each 1024 iteration.
4979 */
dd856efa 4980 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4981 (r->end == 0 || r->end != r->pos)) {
4982 /*
4983 * Reset read cache. Usually happens before
4984 * decode, but since instruction is restarted
4985 * we have to do it here.
4986 */
9dac77fa 4987 ctxt->mem_read.end = 0;
dd856efa 4988 writeback_registers(ctxt);
d2ddd1c4
GN		 4989 return EMULATION_RESTART;
4990 }
4991 goto done; /* skip rip writeback */
0fa6ccbd 4992 }
b9a1ecb9 4993 ctxt->eflags &= ~EFLG_RF;
5cd21917 4994 }
d2ddd1c4 4995
9dac77fa 4996 ctxt->eip = ctxt->_eip;
018a98db
AK		 4997
4998done:
e0ad0b47
PB		 4999 if (rc == X86EMUL_PROPAGATE_FAULT) {
5000 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5001 ctxt->have_exception = true;
e0ad0b47 5002 }
775fde86
JR		 5003 if (rc == X86EMUL_INTERCEPTED)
5004 return EMULATION_INTERCEPTED;
5005
dd856efa
AK		 5006 if (rc == X86EMUL_CONTINUE)
5007 writeback_registers(ctxt);
5008
d2ddd1c4 5009 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5010
5011twobyte_insn:
9dac77fa 5012 switch (ctxt->b) {
018a98db 5013 case 0x09: /* wbinvd */
cfb22375 5014 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5015 break;
5016 case 0x08: /* invd */
018a98db
AK		 5017 case 0x0d: /* GrpP (prefetch) */
5018 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5019 case 0x1f: /* nop */
018a98db
AK		 5020 break;
5021 case 0x20: /* mov cr, reg */
9dac77fa 5022 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5023 break;
6aa8b732 5024 case 0x21: /* mov from dr to reg */
9dac77fa 5025 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5026 break;
6aa8b732 5027 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5028 if (test_cc(ctxt->b, ctxt->eflags))
5029 ctxt->dst.val = ctxt->src.val;
5030 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5031 ctxt->op_bytes != 4)
9dac77fa 5032 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5033 break;
b2833e3c 5034 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5035 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5036 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5037 break;
ee45b58e 5038 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5039 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5040 break;
6aa8b732 5041 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5042 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5043 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5044 : (u16) ctxt->src.val;
6aa8b732 5045 break;
6aa8b732 5046 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5047 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5048 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5049 (s16) ctxt->src.val;
6aa8b732 5050 break;
91269b8f
AK		 5051 default:
5052 goto cannot_emulate;
6aa8b732 5053 }
7d9ddaed 5054
0bc5eedb
BP		 5055threebyte_insn:
5056
7d9ddaed
AK		 5057 if (rc != X86EMUL_CONTINUE)
5058 goto done;
5059
6aa8b732
AK		 5060 goto writeback;
5061
5062cannot_emulate:
a0c0ab2f 5063 return EMULATION_FAILED;
6aa8b732 5064}
dd856efa
AK		 5065
5066void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5067{
5068 invalidate_registers(ctxt);
5069}
5070
5071void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5072{
5073 writeback_registers(ctxt);
5074}
Linux kernel - Deliverables
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