Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
221d059d | 12 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
23 | #ifndef __KERNEL__ | |
24 | #include <stdio.h> | |
25 | #include <stdint.h> | |
26 | #include <public/xen.h> | |
d77c26fc | 27 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 28 | #else |
edf88417 | 29 | #include <linux/kvm_host.h> |
5fdbf976 | 30 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
31 | #define DPRINTF(x...) do {} while (0) |
32 | #endif | |
6aa8b732 | 33 | #include <linux/module.h> |
56e82318 | 34 | #include <asm/kvm_emulate.h> |
6aa8b732 | 35 | |
3eeb3288 | 36 | #include "x86.h" |
38ba30ba | 37 | #include "tss.h" |
e99f0507 | 38 | |
6aa8b732 AK |
39 | /* |
40 | * Opcode effective-address decode tables. | |
41 | * Note that we only emulate instructions that have at least one memory | |
42 | * operand (excluding implicit stack references). We assume that stack | |
43 | * references and instruction fetches will never occur in special memory | |
44 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
45 | * not be handled. | |
46 | */ | |
47 | ||
48 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 49 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 50 | /* Destination operand type. */ |
ab85b12b AK |
51 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
52 | #define DstReg (2<<1) /* Register operand. */ | |
53 | #define DstMem (3<<1) /* Memory operand. */ | |
54 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
55 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
56 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
57 | #define DstMask (7<<1) | |
6aa8b732 | 58 | /* Source operand type. */ |
9c9fddd0 GT |
59 | #define SrcNone (0<<4) /* No source operand. */ |
60 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
61 | #define SrcReg (1<<4) /* Register operand. */ | |
62 | #define SrcMem (2<<4) /* Memory operand. */ | |
63 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
64 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
65 | #define SrcImm (5<<4) /* Immediate operand. */ | |
66 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 67 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 68 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 69 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 70 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
71 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
72 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 73 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
341de7e3 | 74 | #define SrcMask (0xf<<4) |
6aa8b732 | 75 | /* Generic ModRM decode. */ |
341de7e3 | 76 | #define ModRM (1<<8) |
6aa8b732 | 77 | /* Destination is only written; never read. */ |
341de7e3 GN |
78 | #define Mov (1<<9) |
79 | #define BitOp (1<<10) | |
80 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
81 | #define String (1<<12) /* String instruction (rep capable) */ |
82 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
83 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
84 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
d8769fed | 85 | /* Misc flags */ |
5a506b12 | 86 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 87 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 88 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 89 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 90 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 91 | #define No64 (1<<28) |
0dc8d10f GT |
92 | /* Source 2 operand type */ |
93 | #define Src2None (0<<29) | |
94 | #define Src2CL (1<<29) | |
95 | #define Src2ImmByte (2<<29) | |
96 | #define Src2One (3<<29) | |
97 | #define Src2Mask (7<<29) | |
6aa8b732 | 98 | |
d0e53325 AK |
99 | #define X2(x...) x, x |
100 | #define X3(x...) X2(x), x | |
101 | #define X4(x...) X2(x), X2(x) | |
102 | #define X5(x...) X4(x), x | |
103 | #define X6(x...) X4(x), X2(x) | |
104 | #define X7(x...) X4(x), X3(x) | |
105 | #define X8(x...) X4(x), X4(x) | |
106 | #define X16(x...) X8(x), X8(x) | |
83babbca | 107 | |
d65b1dee AK |
108 | struct opcode { |
109 | u32 flags; | |
120df890 | 110 | union { |
ef65c889 | 111 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
112 | struct opcode *group; |
113 | struct group_dual *gdual; | |
114 | } u; | |
115 | }; | |
116 | ||
117 | struct group_dual { | |
118 | struct opcode mod012[8]; | |
119 | struct opcode mod3[8]; | |
d65b1dee AK |
120 | }; |
121 | ||
6aa8b732 | 122 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
123 | #define EFLG_ID (1<<21) |
124 | #define EFLG_VIP (1<<20) | |
125 | #define EFLG_VIF (1<<19) | |
126 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
127 | #define EFLG_VM (1<<17) |
128 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
129 | #define EFLG_IOPL (3<<12) |
130 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
131 | #define EFLG_OF (1<<11) |
132 | #define EFLG_DF (1<<10) | |
b1d86143 | 133 | #define EFLG_IF (1<<9) |
d4c6a154 | 134 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
135 | #define EFLG_SF (1<<7) |
136 | #define EFLG_ZF (1<<6) | |
137 | #define EFLG_AF (1<<4) | |
138 | #define EFLG_PF (1<<2) | |
139 | #define EFLG_CF (1<<0) | |
140 | ||
62bd430e MG |
141 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
142 | #define EFLG_RESERVED_ONE_MASK 2 | |
143 | ||
6aa8b732 AK |
144 | /* |
145 | * Instruction emulation: | |
146 | * Most instructions are emulated directly via a fragment of inline assembly | |
147 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
148 | * any modified flags. | |
149 | */ | |
150 | ||
05b3e0c2 | 151 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
152 | #define _LO32 "k" /* force 32-bit operand */ |
153 | #define _STK "%%rsp" /* stack pointer */ | |
154 | #elif defined(__i386__) | |
155 | #define _LO32 "" /* force 32-bit operand */ | |
156 | #define _STK "%%esp" /* stack pointer */ | |
157 | #endif | |
158 | ||
159 | /* | |
160 | * These EFLAGS bits are restored from saved value during emulation, and | |
161 | * any changes are written back to the saved value after emulation. | |
162 | */ | |
163 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
164 | ||
165 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
166 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
167 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
168 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
169 | "push %"_tmp"; " \ | |
170 | "push %"_tmp"; " \ | |
171 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
172 | "andl %"_LO32 _tmp",("_STK"); " \ | |
173 | "pushf; " \ | |
174 | "notl %"_LO32 _tmp"; " \ | |
175 | "andl %"_LO32 _tmp",("_STK"); " \ | |
176 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
177 | "pop %"_tmp"; " \ | |
178 | "orl %"_LO32 _tmp",("_STK"); " \ | |
179 | "popf; " \ | |
180 | "pop %"_sav"; " | |
6aa8b732 AK |
181 | |
182 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
183 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
184 | /* _sav |= EFLAGS & _msk; */ \ | |
185 | "pushf; " \ | |
186 | "pop %"_tmp"; " \ | |
187 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
188 | "orl %"_LO32 _tmp",%"_sav"; " | |
189 | ||
dda96d8f AK |
190 | #ifdef CONFIG_X86_64 |
191 | #define ON64(x) x | |
192 | #else | |
193 | #define ON64(x) | |
194 | #endif | |
195 | ||
6b7ad61f AK |
196 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
197 | do { \ | |
198 | __asm__ __volatile__ ( \ | |
199 | _PRE_EFLAGS("0", "4", "2") \ | |
200 | _op _suffix " %"_x"3,%1; " \ | |
201 | _POST_EFLAGS("0", "4", "2") \ | |
202 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
203 | "=&r" (_tmp) \ | |
204 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 205 | } while (0) |
6b7ad61f AK |
206 | |
207 | ||
6aa8b732 AK |
208 | /* Raw emulation: instruction has two explicit operands. */ |
209 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
210 | do { \ |
211 | unsigned long _tmp; \ | |
212 | \ | |
213 | switch ((_dst).bytes) { \ | |
214 | case 2: \ | |
215 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
216 | break; \ | |
217 | case 4: \ | |
218 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
219 | break; \ | |
220 | case 8: \ | |
221 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
222 | break; \ | |
223 | } \ | |
6aa8b732 AK |
224 | } while (0) |
225 | ||
226 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
227 | do { \ | |
6b7ad61f | 228 | unsigned long _tmp; \ |
d77c26fc | 229 | switch ((_dst).bytes) { \ |
6aa8b732 | 230 | case 1: \ |
6b7ad61f | 231 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
232 | break; \ |
233 | default: \ | |
234 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
235 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
236 | break; \ | |
237 | } \ | |
238 | } while (0) | |
239 | ||
240 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
241 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
242 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
243 | "b", "c", "b", "c", "b", "c", "b", "c") | |
244 | ||
245 | /* Source operand is byte, word, long or quad sized. */ | |
246 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
247 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
248 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
249 | ||
250 | /* Source operand is word, long or quad sized. */ | |
251 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
252 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
253 | "w", "r", _LO32, "r", "", "r") | |
254 | ||
d175226a GT |
255 | /* Instruction has three operands and one operand is stored in ECX register */ |
256 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
257 | do { \ | |
258 | unsigned long _tmp; \ | |
259 | _type _clv = (_cl).val; \ | |
260 | _type _srcv = (_src).val; \ | |
261 | _type _dstv = (_dst).val; \ | |
262 | \ | |
263 | __asm__ __volatile__ ( \ | |
264 | _PRE_EFLAGS("0", "5", "2") \ | |
265 | _op _suffix " %4,%1 \n" \ | |
266 | _POST_EFLAGS("0", "5", "2") \ | |
267 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
268 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
269 | ); \ | |
270 | \ | |
271 | (_cl).val = (unsigned long) _clv; \ | |
272 | (_src).val = (unsigned long) _srcv; \ | |
273 | (_dst).val = (unsigned long) _dstv; \ | |
274 | } while (0) | |
275 | ||
276 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
277 | do { \ | |
278 | switch ((_dst).bytes) { \ | |
279 | case 2: \ | |
280 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
281 | "w", unsigned short); \ | |
282 | break; \ | |
283 | case 4: \ | |
284 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
285 | "l", unsigned int); \ | |
286 | break; \ | |
287 | case 8: \ | |
288 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
289 | "q", unsigned long)); \ | |
290 | break; \ | |
291 | } \ | |
292 | } while (0) | |
293 | ||
dda96d8f | 294 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
295 | do { \ |
296 | unsigned long _tmp; \ | |
297 | \ | |
dda96d8f AK |
298 | __asm__ __volatile__ ( \ |
299 | _PRE_EFLAGS("0", "3", "2") \ | |
300 | _op _suffix " %1; " \ | |
301 | _POST_EFLAGS("0", "3", "2") \ | |
302 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
303 | "=&r" (_tmp) \ | |
304 | : "i" (EFLAGS_MASK)); \ | |
305 | } while (0) | |
306 | ||
307 | /* Instruction has only one explicit operand (no source operand). */ | |
308 | #define emulate_1op(_op, _dst, _eflags) \ | |
309 | do { \ | |
d77c26fc | 310 | switch ((_dst).bytes) { \ |
dda96d8f AK |
311 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
312 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
313 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
314 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
315 | } \ |
316 | } while (0) | |
317 | ||
6aa8b732 AK |
318 | /* Fetch next part of the instruction being emulated. */ |
319 | #define insn_fetch(_type, _size, _eip) \ | |
320 | ({ unsigned long _x; \ | |
62266869 | 321 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 322 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
323 | goto done; \ |
324 | (_eip) += (_size); \ | |
325 | (_type)_x; \ | |
326 | }) | |
327 | ||
414e6277 GN |
328 | #define insn_fetch_arr(_arr, _size, _eip) \ |
329 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
330 | if (rc != X86EMUL_CONTINUE) \ | |
331 | goto done; \ | |
332 | (_eip) += (_size); \ | |
333 | }) | |
334 | ||
ddcb2885 HH |
335 | static inline unsigned long ad_mask(struct decode_cache *c) |
336 | { | |
337 | return (1UL << (c->ad_bytes << 3)) - 1; | |
338 | } | |
339 | ||
6aa8b732 | 340 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
341 | static inline unsigned long |
342 | address_mask(struct decode_cache *c, unsigned long reg) | |
343 | { | |
344 | if (c->ad_bytes == sizeof(unsigned long)) | |
345 | return reg; | |
346 | else | |
347 | return reg & ad_mask(c); | |
348 | } | |
349 | ||
350 | static inline unsigned long | |
351 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
352 | { | |
353 | return base + address_mask(c, reg); | |
354 | } | |
355 | ||
7a957275 HH |
356 | static inline void |
357 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
358 | { | |
359 | if (c->ad_bytes == sizeof(unsigned long)) | |
360 | *reg += inc; | |
361 | else | |
362 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
363 | } | |
6aa8b732 | 364 | |
7a957275 HH |
365 | static inline void jmp_rel(struct decode_cache *c, int rel) |
366 | { | |
367 | register_address_increment(c, &c->eip, rel); | |
368 | } | |
098c937b | 369 | |
7a5b56df AK |
370 | static void set_seg_override(struct decode_cache *c, int seg) |
371 | { | |
372 | c->has_seg_override = true; | |
373 | c->seg_override = seg; | |
374 | } | |
375 | ||
79168fd1 GN |
376 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
377 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
378 | { |
379 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
380 | return 0; | |
381 | ||
79168fd1 | 382 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
383 | } |
384 | ||
385 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 386 | struct x86_emulate_ops *ops, |
7a5b56df AK |
387 | struct decode_cache *c) |
388 | { | |
389 | if (!c->has_seg_override) | |
390 | return 0; | |
391 | ||
79168fd1 | 392 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
393 | } |
394 | ||
79168fd1 GN |
395 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
396 | struct x86_emulate_ops *ops) | |
7a5b56df | 397 | { |
79168fd1 | 398 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
399 | } |
400 | ||
79168fd1 GN |
401 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
402 | struct x86_emulate_ops *ops) | |
7a5b56df | 403 | { |
79168fd1 | 404 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
405 | } |
406 | ||
54b8486f GN |
407 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
408 | u32 error, bool valid) | |
409 | { | |
410 | ctxt->exception = vec; | |
411 | ctxt->error_code = error; | |
412 | ctxt->error_code_valid = valid; | |
413 | ctxt->restart = false; | |
414 | } | |
415 | ||
416 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
417 | { | |
418 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
419 | } | |
420 | ||
421 | static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
422 | int err) | |
423 | { | |
424 | ctxt->cr2 = addr; | |
425 | emulate_exception(ctxt, PF_VECTOR, err, true); | |
426 | } | |
427 | ||
428 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
429 | { | |
430 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
431 | } | |
432 | ||
433 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
434 | { | |
435 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
436 | } | |
437 | ||
62266869 AK |
438 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
439 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 440 | unsigned long eip, u8 *dest) |
62266869 AK |
441 | { |
442 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
443 | int rc; | |
2fb53ad8 | 444 | int size, cur_size; |
62266869 | 445 | |
2fb53ad8 AK |
446 | if (eip == fc->end) { |
447 | cur_size = fc->end - fc->start; | |
448 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
449 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
450 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 451 | if (rc != X86EMUL_CONTINUE) |
62266869 | 452 | return rc; |
2fb53ad8 | 453 | fc->end += size; |
62266869 | 454 | } |
2fb53ad8 | 455 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 456 | return X86EMUL_CONTINUE; |
62266869 AK |
457 | } |
458 | ||
459 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
460 | struct x86_emulate_ops *ops, | |
461 | unsigned long eip, void *dest, unsigned size) | |
462 | { | |
3e2815e9 | 463 | int rc; |
62266869 | 464 | |
eb3c79e6 | 465 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 466 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 467 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
468 | while (size--) { |
469 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 470 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
471 | return rc; |
472 | } | |
3e2815e9 | 473 | return X86EMUL_CONTINUE; |
62266869 AK |
474 | } |
475 | ||
1e3c5cb0 RR |
476 | /* |
477 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
478 | * pointer into the block that addresses the relevant register. | |
479 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
480 | */ | |
481 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
482 | int highbyte_regs) | |
6aa8b732 AK |
483 | { |
484 | void *p; | |
485 | ||
486 | p = ®s[modrm_reg]; | |
487 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
488 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
489 | return p; | |
490 | } | |
491 | ||
492 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
493 | struct x86_emulate_ops *ops, | |
1a6440ae | 494 | ulong addr, |
6aa8b732 AK |
495 | u16 *size, unsigned long *address, int op_bytes) |
496 | { | |
497 | int rc; | |
498 | ||
499 | if (op_bytes == 2) | |
500 | op_bytes = 3; | |
501 | *address = 0; | |
1a6440ae | 502 | rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL); |
1b30eaa8 | 503 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 504 | return rc; |
1a6440ae | 505 | rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL); |
6aa8b732 AK |
506 | return rc; |
507 | } | |
508 | ||
bbe9abbd NK |
509 | static int test_cc(unsigned int condition, unsigned int flags) |
510 | { | |
511 | int rc = 0; | |
512 | ||
513 | switch ((condition & 15) >> 1) { | |
514 | case 0: /* o */ | |
515 | rc |= (flags & EFLG_OF); | |
516 | break; | |
517 | case 1: /* b/c/nae */ | |
518 | rc |= (flags & EFLG_CF); | |
519 | break; | |
520 | case 2: /* z/e */ | |
521 | rc |= (flags & EFLG_ZF); | |
522 | break; | |
523 | case 3: /* be/na */ | |
524 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
525 | break; | |
526 | case 4: /* s */ | |
527 | rc |= (flags & EFLG_SF); | |
528 | break; | |
529 | case 5: /* p/pe */ | |
530 | rc |= (flags & EFLG_PF); | |
531 | break; | |
532 | case 7: /* le/ng */ | |
533 | rc |= (flags & EFLG_ZF); | |
534 | /* fall through */ | |
535 | case 6: /* l/nge */ | |
536 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
537 | break; | |
538 | } | |
539 | ||
540 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
541 | return (!!rc ^ (condition & 1)); | |
542 | } | |
543 | ||
91ff3cb4 AK |
544 | static void fetch_register_operand(struct operand *op) |
545 | { | |
546 | switch (op->bytes) { | |
547 | case 1: | |
548 | op->val = *(u8 *)op->addr.reg; | |
549 | break; | |
550 | case 2: | |
551 | op->val = *(u16 *)op->addr.reg; | |
552 | break; | |
553 | case 4: | |
554 | op->val = *(u32 *)op->addr.reg; | |
555 | break; | |
556 | case 8: | |
557 | op->val = *(u64 *)op->addr.reg; | |
558 | break; | |
559 | } | |
560 | } | |
561 | ||
3c118e24 AK |
562 | static void decode_register_operand(struct operand *op, |
563 | struct decode_cache *c, | |
3c118e24 AK |
564 | int inhibit_bytereg) |
565 | { | |
33615aa9 | 566 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 567 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
568 | |
569 | if (!(c->d & ModRM)) | |
570 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
571 | op->type = OP_REG; |
572 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 573 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
574 | op->bytes = 1; |
575 | } else { | |
1a6440ae | 576 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 577 | op->bytes = c->op_bytes; |
3c118e24 | 578 | } |
91ff3cb4 | 579 | fetch_register_operand(op); |
3c118e24 AK |
580 | op->orig_val = op->val; |
581 | } | |
582 | ||
1c73ef66 | 583 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
584 | struct x86_emulate_ops *ops, |
585 | struct operand *op) | |
1c73ef66 AK |
586 | { |
587 | struct decode_cache *c = &ctxt->decode; | |
588 | u8 sib; | |
f5b4edcd | 589 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 590 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 591 | ulong modrm_ea = 0; |
1c73ef66 AK |
592 | |
593 | if (c->rex_prefix) { | |
594 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
595 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
596 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
597 | } | |
598 | ||
599 | c->modrm = insn_fetch(u8, 1, c->eip); | |
600 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
601 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
602 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 603 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
604 | |
605 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
606 | op->type = OP_REG; |
607 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
608 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 609 | c->regs, c->d & ByteOp); |
2dbd0dd7 | 610 | fetch_register_operand(op); |
1c73ef66 AK |
611 | return rc; |
612 | } | |
613 | ||
2dbd0dd7 AK |
614 | op->type = OP_MEM; |
615 | ||
1c73ef66 AK |
616 | if (c->ad_bytes == 2) { |
617 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
618 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
619 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
620 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
621 | ||
622 | /* 16-bit ModR/M decode. */ | |
623 | switch (c->modrm_mod) { | |
624 | case 0: | |
625 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 626 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
627 | break; |
628 | case 1: | |
2dbd0dd7 | 629 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
630 | break; |
631 | case 2: | |
2dbd0dd7 | 632 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
633 | break; |
634 | } | |
635 | switch (c->modrm_rm) { | |
636 | case 0: | |
2dbd0dd7 | 637 | modrm_ea += bx + si; |
1c73ef66 AK |
638 | break; |
639 | case 1: | |
2dbd0dd7 | 640 | modrm_ea += bx + di; |
1c73ef66 AK |
641 | break; |
642 | case 2: | |
2dbd0dd7 | 643 | modrm_ea += bp + si; |
1c73ef66 AK |
644 | break; |
645 | case 3: | |
2dbd0dd7 | 646 | modrm_ea += bp + di; |
1c73ef66 AK |
647 | break; |
648 | case 4: | |
2dbd0dd7 | 649 | modrm_ea += si; |
1c73ef66 AK |
650 | break; |
651 | case 5: | |
2dbd0dd7 | 652 | modrm_ea += di; |
1c73ef66 AK |
653 | break; |
654 | case 6: | |
655 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 656 | modrm_ea += bp; |
1c73ef66 AK |
657 | break; |
658 | case 7: | |
2dbd0dd7 | 659 | modrm_ea += bx; |
1c73ef66 AK |
660 | break; |
661 | } | |
662 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
663 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 664 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 665 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
666 | } else { |
667 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 668 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
669 | sib = insn_fetch(u8, 1, c->eip); |
670 | index_reg |= (sib >> 3) & 7; | |
671 | base_reg |= sib & 7; | |
672 | scale = sib >> 6; | |
673 | ||
dc71d0f1 | 674 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 675 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 676 | else |
2dbd0dd7 | 677 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 678 | if (index_reg != 4) |
2dbd0dd7 | 679 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
680 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
681 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 682 | c->rip_relative = 1; |
84411d85 | 683 | } else |
2dbd0dd7 | 684 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
685 | switch (c->modrm_mod) { |
686 | case 0: | |
687 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 688 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
689 | break; |
690 | case 1: | |
2dbd0dd7 | 691 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
692 | break; |
693 | case 2: | |
2dbd0dd7 | 694 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
695 | break; |
696 | } | |
697 | } | |
2dbd0dd7 | 698 | op->addr.mem = modrm_ea; |
1c73ef66 AK |
699 | done: |
700 | return rc; | |
701 | } | |
702 | ||
703 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
704 | struct x86_emulate_ops *ops, |
705 | struct operand *op) | |
1c73ef66 AK |
706 | { |
707 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 708 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 709 | |
2dbd0dd7 | 710 | op->type = OP_MEM; |
1c73ef66 AK |
711 | switch (c->ad_bytes) { |
712 | case 2: | |
2dbd0dd7 | 713 | op->addr.mem = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
714 | break; |
715 | case 4: | |
2dbd0dd7 | 716 | op->addr.mem = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
717 | break; |
718 | case 8: | |
2dbd0dd7 | 719 | op->addr.mem = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
720 | break; |
721 | } | |
722 | done: | |
723 | return rc; | |
724 | } | |
725 | ||
dde7e6d1 AK |
726 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
727 | struct x86_emulate_ops *ops, | |
728 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 729 | { |
dde7e6d1 AK |
730 | int rc; |
731 | struct read_cache *mc = &ctxt->decode.mem_read; | |
732 | u32 err; | |
6aa8b732 | 733 | |
dde7e6d1 AK |
734 | while (size) { |
735 | int n = min(size, 8u); | |
736 | size -= n; | |
737 | if (mc->pos < mc->end) | |
738 | goto read_cached; | |
5cd21917 | 739 | |
dde7e6d1 AK |
740 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
741 | ctxt->vcpu); | |
742 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
743 | emulate_pf(ctxt, addr, err); | |
744 | if (rc != X86EMUL_CONTINUE) | |
745 | return rc; | |
746 | mc->end += n; | |
6aa8b732 | 747 | |
dde7e6d1 AK |
748 | read_cached: |
749 | memcpy(dest, mc->data + mc->pos, n); | |
750 | mc->pos += n; | |
751 | dest += n; | |
752 | addr += n; | |
6aa8b732 | 753 | } |
dde7e6d1 AK |
754 | return X86EMUL_CONTINUE; |
755 | } | |
6aa8b732 | 756 | |
dde7e6d1 AK |
757 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
758 | struct x86_emulate_ops *ops, | |
759 | unsigned int size, unsigned short port, | |
760 | void *dest) | |
761 | { | |
762 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 763 | |
dde7e6d1 AK |
764 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
765 | struct decode_cache *c = &ctxt->decode; | |
766 | unsigned int in_page, n; | |
767 | unsigned int count = c->rep_prefix ? | |
768 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
769 | in_page = (ctxt->eflags & EFLG_DF) ? | |
770 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
771 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
772 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
773 | count); | |
774 | if (n == 0) | |
775 | n = 1; | |
776 | rc->pos = rc->end = 0; | |
777 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
778 | return 0; | |
779 | rc->end = n * size; | |
6aa8b732 AK |
780 | } |
781 | ||
dde7e6d1 AK |
782 | memcpy(dest, rc->data + rc->pos, size); |
783 | rc->pos += size; | |
784 | return 1; | |
785 | } | |
6aa8b732 | 786 | |
dde7e6d1 AK |
787 | static u32 desc_limit_scaled(struct desc_struct *desc) |
788 | { | |
789 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 790 | |
dde7e6d1 AK |
791 | return desc->g ? (limit << 12) | 0xfff : limit; |
792 | } | |
6aa8b732 | 793 | |
dde7e6d1 AK |
794 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
795 | struct x86_emulate_ops *ops, | |
796 | u16 selector, struct desc_ptr *dt) | |
797 | { | |
798 | if (selector & 1 << 2) { | |
799 | struct desc_struct desc; | |
800 | memset (dt, 0, sizeof *dt); | |
801 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
802 | return; | |
e09d082c | 803 | |
dde7e6d1 AK |
804 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
805 | dt->address = get_desc_base(&desc); | |
806 | } else | |
807 | ops->get_gdt(dt, ctxt->vcpu); | |
808 | } | |
120df890 | 809 | |
dde7e6d1 AK |
810 | /* allowed just for 8 bytes segments */ |
811 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
812 | struct x86_emulate_ops *ops, | |
813 | u16 selector, struct desc_struct *desc) | |
814 | { | |
815 | struct desc_ptr dt; | |
816 | u16 index = selector >> 3; | |
817 | int ret; | |
818 | u32 err; | |
819 | ulong addr; | |
120df890 | 820 | |
dde7e6d1 | 821 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 822 | |
dde7e6d1 AK |
823 | if (dt.size < index * 8 + 7) { |
824 | emulate_gp(ctxt, selector & 0xfffc); | |
825 | return X86EMUL_PROPAGATE_FAULT; | |
e09d082c | 826 | } |
dde7e6d1 AK |
827 | addr = dt.address + index * 8; |
828 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
829 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
830 | emulate_pf(ctxt, addr, err); | |
e09d082c | 831 | |
dde7e6d1 AK |
832 | return ret; |
833 | } | |
ef65c889 | 834 | |
dde7e6d1 AK |
835 | /* allowed just for 8 bytes segments */ |
836 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
837 | struct x86_emulate_ops *ops, | |
838 | u16 selector, struct desc_struct *desc) | |
839 | { | |
840 | struct desc_ptr dt; | |
841 | u16 index = selector >> 3; | |
842 | u32 err; | |
843 | ulong addr; | |
844 | int ret; | |
6aa8b732 | 845 | |
dde7e6d1 | 846 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 847 | |
dde7e6d1 AK |
848 | if (dt.size < index * 8 + 7) { |
849 | emulate_gp(ctxt, selector & 0xfffc); | |
850 | return X86EMUL_PROPAGATE_FAULT; | |
851 | } | |
6aa8b732 | 852 | |
dde7e6d1 AK |
853 | addr = dt.address + index * 8; |
854 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
855 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
856 | emulate_pf(ctxt, addr, err); | |
c7e75a3d | 857 | |
dde7e6d1 AK |
858 | return ret; |
859 | } | |
c7e75a3d | 860 | |
dde7e6d1 AK |
861 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
862 | struct x86_emulate_ops *ops, | |
863 | u16 selector, int seg) | |
864 | { | |
865 | struct desc_struct seg_desc; | |
866 | u8 dpl, rpl, cpl; | |
867 | unsigned err_vec = GP_VECTOR; | |
868 | u32 err_code = 0; | |
869 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
870 | int ret; | |
69f55cb1 | 871 | |
dde7e6d1 | 872 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 873 | |
dde7e6d1 AK |
874 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
875 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
876 | /* set real mode segment descriptor */ | |
877 | set_desc_base(&seg_desc, selector << 4); | |
878 | set_desc_limit(&seg_desc, 0xffff); | |
879 | seg_desc.type = 3; | |
880 | seg_desc.p = 1; | |
881 | seg_desc.s = 1; | |
882 | goto load; | |
883 | } | |
884 | ||
885 | /* NULL selector is not valid for TR, CS and SS */ | |
886 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
887 | && null_selector) | |
888 | goto exception; | |
889 | ||
890 | /* TR should be in GDT only */ | |
891 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
892 | goto exception; | |
893 | ||
894 | if (null_selector) /* for NULL selector skip all following checks */ | |
895 | goto load; | |
896 | ||
897 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
898 | if (ret != X86EMUL_CONTINUE) | |
899 | return ret; | |
900 | ||
901 | err_code = selector & 0xfffc; | |
902 | err_vec = GP_VECTOR; | |
903 | ||
904 | /* can't load system descriptor into segment selecor */ | |
905 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
906 | goto exception; | |
907 | ||
908 | if (!seg_desc.p) { | |
909 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
910 | goto exception; | |
911 | } | |
912 | ||
913 | rpl = selector & 3; | |
914 | dpl = seg_desc.dpl; | |
915 | cpl = ops->cpl(ctxt->vcpu); | |
916 | ||
917 | switch (seg) { | |
918 | case VCPU_SREG_SS: | |
919 | /* | |
920 | * segment is not a writable data segment or segment | |
921 | * selector's RPL != CPL or segment selector's RPL != CPL | |
922 | */ | |
923 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
924 | goto exception; | |
6aa8b732 | 925 | break; |
dde7e6d1 AK |
926 | case VCPU_SREG_CS: |
927 | if (!(seg_desc.type & 8)) | |
928 | goto exception; | |
929 | ||
930 | if (seg_desc.type & 4) { | |
931 | /* conforming */ | |
932 | if (dpl > cpl) | |
933 | goto exception; | |
934 | } else { | |
935 | /* nonconforming */ | |
936 | if (rpl > cpl || dpl != cpl) | |
937 | goto exception; | |
938 | } | |
939 | /* CS(RPL) <- CPL */ | |
940 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 941 | break; |
dde7e6d1 AK |
942 | case VCPU_SREG_TR: |
943 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
944 | goto exception; | |
945 | break; | |
946 | case VCPU_SREG_LDTR: | |
947 | if (seg_desc.s || seg_desc.type != 2) | |
948 | goto exception; | |
949 | break; | |
950 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 951 | /* |
dde7e6d1 AK |
952 | * segment is not a data or readable code segment or |
953 | * ((segment is a data or nonconforming code segment) | |
954 | * and (both RPL and CPL > DPL)) | |
4e62417b | 955 | */ |
dde7e6d1 AK |
956 | if ((seg_desc.type & 0xa) == 0x8 || |
957 | (((seg_desc.type & 0xc) != 0xc) && | |
958 | (rpl > dpl && cpl > dpl))) | |
959 | goto exception; | |
6aa8b732 | 960 | break; |
dde7e6d1 AK |
961 | } |
962 | ||
963 | if (seg_desc.s) { | |
964 | /* mark segment as accessed */ | |
965 | seg_desc.type |= 1; | |
966 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
967 | if (ret != X86EMUL_CONTINUE) | |
968 | return ret; | |
969 | } | |
970 | load: | |
971 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
972 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
973 | return X86EMUL_CONTINUE; | |
974 | exception: | |
975 | emulate_exception(ctxt, err_vec, err_code, true); | |
976 | return X86EMUL_PROPAGATE_FAULT; | |
977 | } | |
978 | ||
979 | static inline int writeback(struct x86_emulate_ctxt *ctxt, | |
980 | struct x86_emulate_ops *ops) | |
981 | { | |
982 | int rc; | |
983 | struct decode_cache *c = &ctxt->decode; | |
984 | u32 err; | |
985 | ||
986 | switch (c->dst.type) { | |
987 | case OP_REG: | |
988 | /* The 4-byte case *is* correct: | |
989 | * in 64-bit mode we zero-extend. | |
990 | */ | |
991 | switch (c->dst.bytes) { | |
6aa8b732 | 992 | case 1: |
1a6440ae | 993 | *(u8 *)c->dst.addr.reg = (u8)c->dst.val; |
6aa8b732 AK |
994 | break; |
995 | case 2: | |
1a6440ae | 996 | *(u16 *)c->dst.addr.reg = (u16)c->dst.val; |
6aa8b732 AK |
997 | break; |
998 | case 4: | |
1a6440ae | 999 | *c->dst.addr.reg = (u32)c->dst.val; |
dde7e6d1 AK |
1000 | break; /* 64b: zero-ext */ |
1001 | case 8: | |
1a6440ae | 1002 | *c->dst.addr.reg = c->dst.val; |
6aa8b732 AK |
1003 | break; |
1004 | } | |
1005 | break; | |
dde7e6d1 AK |
1006 | case OP_MEM: |
1007 | if (c->lock_prefix) | |
1008 | rc = ops->cmpxchg_emulated( | |
1a6440ae | 1009 | c->dst.addr.mem, |
dde7e6d1 AK |
1010 | &c->dst.orig_val, |
1011 | &c->dst.val, | |
1012 | c->dst.bytes, | |
1013 | &err, | |
1014 | ctxt->vcpu); | |
341de7e3 | 1015 | else |
dde7e6d1 | 1016 | rc = ops->write_emulated( |
1a6440ae | 1017 | c->dst.addr.mem, |
dde7e6d1 AK |
1018 | &c->dst.val, |
1019 | c->dst.bytes, | |
1020 | &err, | |
1021 | ctxt->vcpu); | |
1022 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1a6440ae | 1023 | emulate_pf(ctxt, c->dst.addr.mem, err); |
dde7e6d1 AK |
1024 | if (rc != X86EMUL_CONTINUE) |
1025 | return rc; | |
a682e354 | 1026 | break; |
dde7e6d1 AK |
1027 | case OP_NONE: |
1028 | /* no writeback */ | |
414e6277 | 1029 | break; |
dde7e6d1 | 1030 | default: |
414e6277 | 1031 | break; |
6aa8b732 | 1032 | } |
dde7e6d1 AK |
1033 | return X86EMUL_CONTINUE; |
1034 | } | |
6aa8b732 | 1035 | |
dde7e6d1 AK |
1036 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1037 | struct x86_emulate_ops *ops) | |
1038 | { | |
1039 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1040 | |
dde7e6d1 AK |
1041 | c->dst.type = OP_MEM; |
1042 | c->dst.bytes = c->op_bytes; | |
1043 | c->dst.val = c->src.val; | |
1044 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
1a6440ae AK |
1045 | c->dst.addr.mem = register_address(c, ss_base(ctxt, ops), |
1046 | c->regs[VCPU_REGS_RSP]); | |
dde7e6d1 | 1047 | } |
69f55cb1 | 1048 | |
dde7e6d1 AK |
1049 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1050 | struct x86_emulate_ops *ops, | |
1051 | void *dest, int len) | |
1052 | { | |
1053 | struct decode_cache *c = &ctxt->decode; | |
1054 | int rc; | |
8b4caf66 | 1055 | |
dde7e6d1 AK |
1056 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
1057 | c->regs[VCPU_REGS_RSP]), | |
1058 | dest, len); | |
1059 | if (rc != X86EMUL_CONTINUE) | |
1060 | return rc; | |
1061 | ||
1062 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1063 | return rc; | |
8b4caf66 LV |
1064 | } |
1065 | ||
dde7e6d1 AK |
1066 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1067 | struct x86_emulate_ops *ops, | |
1068 | void *dest, int len) | |
9de41573 GN |
1069 | { |
1070 | int rc; | |
dde7e6d1 AK |
1071 | unsigned long val, change_mask; |
1072 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1073 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1074 | |
dde7e6d1 AK |
1075 | rc = emulate_pop(ctxt, ops, &val, len); |
1076 | if (rc != X86EMUL_CONTINUE) | |
1077 | return rc; | |
9de41573 | 1078 | |
dde7e6d1 AK |
1079 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1080 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1081 | |
dde7e6d1 AK |
1082 | switch(ctxt->mode) { |
1083 | case X86EMUL_MODE_PROT64: | |
1084 | case X86EMUL_MODE_PROT32: | |
1085 | case X86EMUL_MODE_PROT16: | |
1086 | if (cpl == 0) | |
1087 | change_mask |= EFLG_IOPL; | |
1088 | if (cpl <= iopl) | |
1089 | change_mask |= EFLG_IF; | |
1090 | break; | |
1091 | case X86EMUL_MODE_VM86: | |
1092 | if (iopl < 3) { | |
1093 | emulate_gp(ctxt, 0); | |
1094 | return X86EMUL_PROPAGATE_FAULT; | |
1095 | } | |
1096 | change_mask |= EFLG_IF; | |
1097 | break; | |
1098 | default: /* real mode */ | |
1099 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1100 | break; | |
9de41573 | 1101 | } |
dde7e6d1 AK |
1102 | |
1103 | *(unsigned long *)dest = | |
1104 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1105 | ||
1106 | return rc; | |
9de41573 GN |
1107 | } |
1108 | ||
dde7e6d1 AK |
1109 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1110 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1111 | { |
dde7e6d1 | 1112 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1113 | |
dde7e6d1 | 1114 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1115 | |
dde7e6d1 | 1116 | emulate_push(ctxt, ops); |
7b262e90 GN |
1117 | } |
1118 | ||
dde7e6d1 AK |
1119 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1120 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1121 | { |
dde7e6d1 AK |
1122 | struct decode_cache *c = &ctxt->decode; |
1123 | unsigned long selector; | |
1124 | int rc; | |
38ba30ba | 1125 | |
dde7e6d1 AK |
1126 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1127 | if (rc != X86EMUL_CONTINUE) | |
1128 | return rc; | |
1129 | ||
1130 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1131 | return rc; | |
38ba30ba GN |
1132 | } |
1133 | ||
dde7e6d1 AK |
1134 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1135 | struct x86_emulate_ops *ops) | |
38ba30ba | 1136 | { |
dde7e6d1 AK |
1137 | struct decode_cache *c = &ctxt->decode; |
1138 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1139 | int rc = X86EMUL_CONTINUE; | |
1140 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1141 | |
dde7e6d1 AK |
1142 | while (reg <= VCPU_REGS_RDI) { |
1143 | (reg == VCPU_REGS_RSP) ? | |
1144 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1145 | |
dde7e6d1 | 1146 | emulate_push(ctxt, ops); |
38ba30ba | 1147 | |
dde7e6d1 AK |
1148 | rc = writeback(ctxt, ops); |
1149 | if (rc != X86EMUL_CONTINUE) | |
1150 | return rc; | |
38ba30ba | 1151 | |
dde7e6d1 | 1152 | ++reg; |
38ba30ba | 1153 | } |
38ba30ba | 1154 | |
dde7e6d1 AK |
1155 | /* Disable writeback. */ |
1156 | c->dst.type = OP_NONE; | |
1157 | ||
1158 | return rc; | |
38ba30ba GN |
1159 | } |
1160 | ||
dde7e6d1 AK |
1161 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1162 | struct x86_emulate_ops *ops) | |
38ba30ba | 1163 | { |
dde7e6d1 AK |
1164 | struct decode_cache *c = &ctxt->decode; |
1165 | int rc = X86EMUL_CONTINUE; | |
1166 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1167 | |
dde7e6d1 AK |
1168 | while (reg >= VCPU_REGS_RAX) { |
1169 | if (reg == VCPU_REGS_RSP) { | |
1170 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1171 | c->op_bytes); | |
1172 | --reg; | |
1173 | } | |
38ba30ba | 1174 | |
dde7e6d1 AK |
1175 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1176 | if (rc != X86EMUL_CONTINUE) | |
1177 | break; | |
1178 | --reg; | |
38ba30ba | 1179 | } |
dde7e6d1 | 1180 | return rc; |
38ba30ba GN |
1181 | } |
1182 | ||
6e154e56 MG |
1183 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1184 | struct x86_emulate_ops *ops, int irq) | |
1185 | { | |
1186 | struct decode_cache *c = &ctxt->decode; | |
1187 | int rc = X86EMUL_CONTINUE; | |
1188 | struct desc_ptr dt; | |
1189 | gva_t cs_addr; | |
1190 | gva_t eip_addr; | |
1191 | u16 cs, eip; | |
1192 | u32 err; | |
1193 | ||
1194 | /* TODO: Add limit checks */ | |
1195 | c->src.val = ctxt->eflags; | |
1196 | emulate_push(ctxt, ops); | |
1197 | ||
1198 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1199 | ||
1200 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1201 | emulate_push(ctxt, ops); | |
1202 | ||
1203 | c->src.val = c->eip; | |
1204 | emulate_push(ctxt, ops); | |
1205 | ||
1206 | ops->get_idt(&dt, ctxt->vcpu); | |
1207 | ||
1208 | eip_addr = dt.address + (irq << 2); | |
1209 | cs_addr = dt.address + (irq << 2) + 2; | |
1210 | ||
1211 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err); | |
1212 | if (rc != X86EMUL_CONTINUE) | |
1213 | return rc; | |
1214 | ||
1215 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err); | |
1216 | if (rc != X86EMUL_CONTINUE) | |
1217 | return rc; | |
1218 | ||
1219 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1220 | if (rc != X86EMUL_CONTINUE) | |
1221 | return rc; | |
1222 | ||
1223 | c->eip = eip; | |
1224 | ||
1225 | return rc; | |
1226 | } | |
1227 | ||
1228 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1229 | struct x86_emulate_ops *ops, int irq) | |
1230 | { | |
1231 | switch(ctxt->mode) { | |
1232 | case X86EMUL_MODE_REAL: | |
1233 | return emulate_int_real(ctxt, ops, irq); | |
1234 | case X86EMUL_MODE_VM86: | |
1235 | case X86EMUL_MODE_PROT16: | |
1236 | case X86EMUL_MODE_PROT32: | |
1237 | case X86EMUL_MODE_PROT64: | |
1238 | default: | |
1239 | /* Protected mode interrupts unimplemented yet */ | |
1240 | return X86EMUL_UNHANDLEABLE; | |
1241 | } | |
1242 | } | |
1243 | ||
dde7e6d1 AK |
1244 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1245 | struct x86_emulate_ops *ops) | |
38ba30ba | 1246 | { |
dde7e6d1 AK |
1247 | struct decode_cache *c = &ctxt->decode; |
1248 | int rc = X86EMUL_CONTINUE; | |
1249 | unsigned long temp_eip = 0; | |
1250 | unsigned long temp_eflags = 0; | |
1251 | unsigned long cs = 0; | |
1252 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1253 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1254 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1255 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1256 | |
dde7e6d1 | 1257 | /* TODO: Add stack limit check */ |
38ba30ba | 1258 | |
dde7e6d1 | 1259 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1260 | |
dde7e6d1 AK |
1261 | if (rc != X86EMUL_CONTINUE) |
1262 | return rc; | |
38ba30ba | 1263 | |
dde7e6d1 AK |
1264 | if (temp_eip & ~0xffff) { |
1265 | emulate_gp(ctxt, 0); | |
1266 | return X86EMUL_PROPAGATE_FAULT; | |
1267 | } | |
38ba30ba | 1268 | |
dde7e6d1 | 1269 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1270 | |
dde7e6d1 AK |
1271 | if (rc != X86EMUL_CONTINUE) |
1272 | return rc; | |
38ba30ba | 1273 | |
dde7e6d1 | 1274 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1275 | |
dde7e6d1 AK |
1276 | if (rc != X86EMUL_CONTINUE) |
1277 | return rc; | |
38ba30ba | 1278 | |
dde7e6d1 | 1279 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1280 | |
dde7e6d1 AK |
1281 | if (rc != X86EMUL_CONTINUE) |
1282 | return rc; | |
38ba30ba | 1283 | |
dde7e6d1 | 1284 | c->eip = temp_eip; |
38ba30ba | 1285 | |
38ba30ba | 1286 | |
dde7e6d1 AK |
1287 | if (c->op_bytes == 4) |
1288 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1289 | else if (c->op_bytes == 2) { | |
1290 | ctxt->eflags &= ~0xffff; | |
1291 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1292 | } |
dde7e6d1 AK |
1293 | |
1294 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1295 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1296 | ||
1297 | return rc; | |
38ba30ba GN |
1298 | } |
1299 | ||
dde7e6d1 AK |
1300 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1301 | struct x86_emulate_ops* ops) | |
c37eda13 | 1302 | { |
dde7e6d1 AK |
1303 | switch(ctxt->mode) { |
1304 | case X86EMUL_MODE_REAL: | |
1305 | return emulate_iret_real(ctxt, ops); | |
1306 | case X86EMUL_MODE_VM86: | |
1307 | case X86EMUL_MODE_PROT16: | |
1308 | case X86EMUL_MODE_PROT32: | |
1309 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1310 | default: |
dde7e6d1 AK |
1311 | /* iret from protected mode unimplemented yet */ |
1312 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1313 | } |
c37eda13 WY |
1314 | } |
1315 | ||
dde7e6d1 | 1316 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1317 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1318 | { |
1319 | struct decode_cache *c = &ctxt->decode; | |
1320 | ||
dde7e6d1 | 1321 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1322 | } |
1323 | ||
dde7e6d1 | 1324 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1325 | { |
05f086f8 | 1326 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1327 | switch (c->modrm_reg) { |
1328 | case 0: /* rol */ | |
05f086f8 | 1329 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1330 | break; |
1331 | case 1: /* ror */ | |
05f086f8 | 1332 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1333 | break; |
1334 | case 2: /* rcl */ | |
05f086f8 | 1335 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1336 | break; |
1337 | case 3: /* rcr */ | |
05f086f8 | 1338 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1339 | break; |
1340 | case 4: /* sal/shl */ | |
1341 | case 6: /* sal/shl */ | |
05f086f8 | 1342 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1343 | break; |
1344 | case 5: /* shr */ | |
05f086f8 | 1345 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1346 | break; |
1347 | case 7: /* sar */ | |
05f086f8 | 1348 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1349 | break; |
1350 | } | |
1351 | } | |
1352 | ||
1353 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1354 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1355 | { |
1356 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1357 | |
1358 | switch (c->modrm_reg) { | |
1359 | case 0 ... 1: /* test */ | |
05f086f8 | 1360 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1361 | break; |
1362 | case 2: /* not */ | |
1363 | c->dst.val = ~c->dst.val; | |
1364 | break; | |
1365 | case 3: /* neg */ | |
05f086f8 | 1366 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1367 | break; |
1368 | default: | |
aca06a83 | 1369 | return 0; |
8cdbd2c9 | 1370 | } |
aca06a83 | 1371 | return 1; |
8cdbd2c9 LV |
1372 | } |
1373 | ||
1374 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1375 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1376 | { |
1377 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1378 | |
1379 | switch (c->modrm_reg) { | |
1380 | case 0: /* inc */ | |
05f086f8 | 1381 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1382 | break; |
1383 | case 1: /* dec */ | |
05f086f8 | 1384 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1385 | break; |
d19292e4 MG |
1386 | case 2: /* call near abs */ { |
1387 | long int old_eip; | |
1388 | old_eip = c->eip; | |
1389 | c->eip = c->src.val; | |
1390 | c->src.val = old_eip; | |
79168fd1 | 1391 | emulate_push(ctxt, ops); |
d19292e4 MG |
1392 | break; |
1393 | } | |
8cdbd2c9 | 1394 | case 4: /* jmp abs */ |
fd60754e | 1395 | c->eip = c->src.val; |
8cdbd2c9 LV |
1396 | break; |
1397 | case 6: /* push */ | |
79168fd1 | 1398 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1399 | break; |
8cdbd2c9 | 1400 | } |
1b30eaa8 | 1401 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1402 | } |
1403 | ||
1404 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1405 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1406 | { |
1407 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1408 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1409 | |
1410 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1411 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1412 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1413 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1414 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1415 | } else { |
16518d5a AK |
1416 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1417 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1418 | |
05f086f8 | 1419 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1420 | } |
1b30eaa8 | 1421 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1422 | } |
1423 | ||
a77ab5ea AK |
1424 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1425 | struct x86_emulate_ops *ops) | |
1426 | { | |
1427 | struct decode_cache *c = &ctxt->decode; | |
1428 | int rc; | |
1429 | unsigned long cs; | |
1430 | ||
1431 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1432 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1433 | return rc; |
1434 | if (c->op_bytes == 4) | |
1435 | c->eip = (u32)c->eip; | |
1436 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1437 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1438 | return rc; |
2e873022 | 1439 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1440 | return rc; |
1441 | } | |
1442 | ||
e66bb2cc AP |
1443 | static inline void |
1444 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1445 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1446 | struct desc_struct *ss) | |
e66bb2cc | 1447 | { |
79168fd1 GN |
1448 | memset(cs, 0, sizeof(struct desc_struct)); |
1449 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1450 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1451 | |
1452 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1453 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1454 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1455 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1456 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1457 | cs->s = 1; | |
1458 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1459 | cs->p = 1; |
1460 | cs->d = 1; | |
e66bb2cc | 1461 | |
79168fd1 GN |
1462 | set_desc_base(ss, 0); /* flat segment */ |
1463 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1464 | ss->g = 1; /* 4kb granularity */ |
1465 | ss->s = 1; | |
1466 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1467 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1468 | ss->dpl = 0; |
79168fd1 | 1469 | ss->p = 1; |
e66bb2cc AP |
1470 | } |
1471 | ||
1472 | static int | |
3fb1b5db | 1473 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1474 | { |
1475 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1476 | struct desc_struct cs, ss; |
e66bb2cc | 1477 | u64 msr_data; |
79168fd1 | 1478 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1479 | |
1480 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1481 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1482 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1483 | emulate_ud(ctxt); |
2e901c4c GN |
1484 | return X86EMUL_PROPAGATE_FAULT; |
1485 | } | |
e66bb2cc | 1486 | |
79168fd1 | 1487 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1488 | |
3fb1b5db | 1489 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1490 | msr_data >>= 32; |
79168fd1 GN |
1491 | cs_sel = (u16)(msr_data & 0xfffc); |
1492 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1493 | |
1494 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1495 | cs.d = 0; |
e66bb2cc AP |
1496 | cs.l = 1; |
1497 | } | |
79168fd1 GN |
1498 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1499 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1500 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1501 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1502 | |
1503 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1504 | if (is_long_mode(ctxt->vcpu)) { | |
1505 | #ifdef CONFIG_X86_64 | |
1506 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1507 | ||
3fb1b5db GN |
1508 | ops->get_msr(ctxt->vcpu, |
1509 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1510 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1511 | c->eip = msr_data; |
1512 | ||
3fb1b5db | 1513 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1514 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1515 | #endif | |
1516 | } else { | |
1517 | /* legacy mode */ | |
3fb1b5db | 1518 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1519 | c->eip = (u32)msr_data; |
1520 | ||
1521 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1522 | } | |
1523 | ||
e54cfa97 | 1524 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1525 | } |
1526 | ||
8c604352 | 1527 | static int |
3fb1b5db | 1528 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1529 | { |
1530 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1531 | struct desc_struct cs, ss; |
8c604352 | 1532 | u64 msr_data; |
79168fd1 | 1533 | u16 cs_sel, ss_sel; |
8c604352 | 1534 | |
a0044755 GN |
1535 | /* inject #GP if in real mode */ |
1536 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 1537 | emulate_gp(ctxt, 0); |
2e901c4c | 1538 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1539 | } |
1540 | ||
1541 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1542 | * Therefore, we inject an #UD. | |
1543 | */ | |
2e901c4c | 1544 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 1545 | emulate_ud(ctxt); |
2e901c4c GN |
1546 | return X86EMUL_PROPAGATE_FAULT; |
1547 | } | |
8c604352 | 1548 | |
79168fd1 | 1549 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1550 | |
3fb1b5db | 1551 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1552 | switch (ctxt->mode) { |
1553 | case X86EMUL_MODE_PROT32: | |
1554 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 1555 | emulate_gp(ctxt, 0); |
e54cfa97 | 1556 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1557 | } |
1558 | break; | |
1559 | case X86EMUL_MODE_PROT64: | |
1560 | if (msr_data == 0x0) { | |
54b8486f | 1561 | emulate_gp(ctxt, 0); |
e54cfa97 | 1562 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1563 | } |
1564 | break; | |
1565 | } | |
1566 | ||
1567 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1568 | cs_sel = (u16)msr_data; |
1569 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1570 | ss_sel = cs_sel + 8; | |
1571 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1572 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1573 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1574 | cs.d = 0; |
8c604352 AP |
1575 | cs.l = 1; |
1576 | } | |
1577 | ||
79168fd1 GN |
1578 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1579 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1580 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1581 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 1582 | |
3fb1b5db | 1583 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1584 | c->eip = msr_data; |
1585 | ||
3fb1b5db | 1586 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1587 | c->regs[VCPU_REGS_RSP] = msr_data; |
1588 | ||
e54cfa97 | 1589 | return X86EMUL_CONTINUE; |
8c604352 AP |
1590 | } |
1591 | ||
4668f050 | 1592 | static int |
3fb1b5db | 1593 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1594 | { |
1595 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1596 | struct desc_struct cs, ss; |
4668f050 AP |
1597 | u64 msr_data; |
1598 | int usermode; | |
79168fd1 | 1599 | u16 cs_sel, ss_sel; |
4668f050 | 1600 | |
a0044755 GN |
1601 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1602 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1603 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1604 | emulate_gp(ctxt, 0); |
2e901c4c | 1605 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1606 | } |
1607 | ||
79168fd1 | 1608 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1609 | |
1610 | if ((c->rex_prefix & 0x8) != 0x0) | |
1611 | usermode = X86EMUL_MODE_PROT64; | |
1612 | else | |
1613 | usermode = X86EMUL_MODE_PROT32; | |
1614 | ||
1615 | cs.dpl = 3; | |
1616 | ss.dpl = 3; | |
3fb1b5db | 1617 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1618 | switch (usermode) { |
1619 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1620 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 1621 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 1622 | emulate_gp(ctxt, 0); |
e54cfa97 | 1623 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1624 | } |
79168fd1 | 1625 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1626 | break; |
1627 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1628 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 1629 | if (msr_data == 0x0) { |
54b8486f | 1630 | emulate_gp(ctxt, 0); |
e54cfa97 | 1631 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1632 | } |
79168fd1 GN |
1633 | ss_sel = cs_sel + 8; |
1634 | cs.d = 0; | |
4668f050 AP |
1635 | cs.l = 1; |
1636 | break; | |
1637 | } | |
79168fd1 GN |
1638 | cs_sel |= SELECTOR_RPL_MASK; |
1639 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1640 | |
79168fd1 GN |
1641 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1642 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1643 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1644 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 1645 | |
bdb475a3 GN |
1646 | c->eip = c->regs[VCPU_REGS_RDX]; |
1647 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1648 | |
e54cfa97 | 1649 | return X86EMUL_CONTINUE; |
4668f050 AP |
1650 | } |
1651 | ||
9c537244 GN |
1652 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1653 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1654 | { |
1655 | int iopl; | |
1656 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1657 | return false; | |
1658 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1659 | return true; | |
1660 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1661 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1662 | } |
1663 | ||
1664 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1665 | struct x86_emulate_ops *ops, | |
1666 | u16 port, u16 len) | |
1667 | { | |
79168fd1 | 1668 | struct desc_struct tr_seg; |
f850e2e6 GN |
1669 | int r; |
1670 | u16 io_bitmap_ptr; | |
1671 | u8 perm, bit_idx = port & 0x7; | |
1672 | unsigned mask = (1 << len) - 1; | |
1673 | ||
79168fd1 GN |
1674 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
1675 | if (!tr_seg.p) | |
f850e2e6 | 1676 | return false; |
79168fd1 | 1677 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1678 | return false; |
79168fd1 GN |
1679 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
1680 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
1681 | if (r != X86EMUL_CONTINUE) |
1682 | return false; | |
79168fd1 | 1683 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1684 | return false; |
79168fd1 GN |
1685 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
1686 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1687 | if (r != X86EMUL_CONTINUE) |
1688 | return false; | |
1689 | if ((perm >> bit_idx) & mask) | |
1690 | return false; | |
1691 | return true; | |
1692 | } | |
1693 | ||
1694 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1695 | struct x86_emulate_ops *ops, | |
1696 | u16 port, u16 len) | |
1697 | { | |
4fc40f07 GN |
1698 | if (ctxt->perm_ok) |
1699 | return true; | |
1700 | ||
9c537244 | 1701 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1702 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1703 | return false; | |
4fc40f07 GN |
1704 | |
1705 | ctxt->perm_ok = true; | |
1706 | ||
f850e2e6 GN |
1707 | return true; |
1708 | } | |
1709 | ||
38ba30ba GN |
1710 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1711 | struct x86_emulate_ops *ops, | |
1712 | struct tss_segment_16 *tss) | |
1713 | { | |
1714 | struct decode_cache *c = &ctxt->decode; | |
1715 | ||
1716 | tss->ip = c->eip; | |
1717 | tss->flag = ctxt->eflags; | |
1718 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1719 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1720 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1721 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1722 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1723 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1724 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1725 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1726 | ||
1727 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1728 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1729 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1730 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1731 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1732 | } | |
1733 | ||
1734 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1735 | struct x86_emulate_ops *ops, | |
1736 | struct tss_segment_16 *tss) | |
1737 | { | |
1738 | struct decode_cache *c = &ctxt->decode; | |
1739 | int ret; | |
1740 | ||
1741 | c->eip = tss->ip; | |
1742 | ctxt->eflags = tss->flag | 2; | |
1743 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1744 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1745 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1746 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1747 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1748 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1749 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1750 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1751 | ||
1752 | /* | |
1753 | * SDM says that segment selectors are loaded before segment | |
1754 | * descriptors | |
1755 | */ | |
1756 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1757 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1758 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1759 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1760 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1761 | ||
1762 | /* | |
1763 | * Now load segment descriptors. If fault happenes at this stage | |
1764 | * it is handled in a context of new task | |
1765 | */ | |
1766 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1767 | if (ret != X86EMUL_CONTINUE) | |
1768 | return ret; | |
1769 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1770 | if (ret != X86EMUL_CONTINUE) | |
1771 | return ret; | |
1772 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1773 | if (ret != X86EMUL_CONTINUE) | |
1774 | return ret; | |
1775 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1776 | if (ret != X86EMUL_CONTINUE) | |
1777 | return ret; | |
1778 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1779 | if (ret != X86EMUL_CONTINUE) | |
1780 | return ret; | |
1781 | ||
1782 | return X86EMUL_CONTINUE; | |
1783 | } | |
1784 | ||
1785 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1786 | struct x86_emulate_ops *ops, | |
1787 | u16 tss_selector, u16 old_tss_sel, | |
1788 | ulong old_tss_base, struct desc_struct *new_desc) | |
1789 | { | |
1790 | struct tss_segment_16 tss_seg; | |
1791 | int ret; | |
1792 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1793 | ||
1794 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1795 | &err); | |
1796 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1797 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1798 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1799 | return ret; |
1800 | } | |
1801 | ||
1802 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1803 | ||
1804 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1805 | &err); | |
1806 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1807 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1808 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1809 | return ret; |
1810 | } | |
1811 | ||
1812 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1813 | &err); | |
1814 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1815 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1816 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1817 | return ret; |
1818 | } | |
1819 | ||
1820 | if (old_tss_sel != 0xffff) { | |
1821 | tss_seg.prev_task_link = old_tss_sel; | |
1822 | ||
1823 | ret = ops->write_std(new_tss_base, | |
1824 | &tss_seg.prev_task_link, | |
1825 | sizeof tss_seg.prev_task_link, | |
1826 | ctxt->vcpu, &err); | |
1827 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1828 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1829 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1830 | return ret; |
1831 | } | |
1832 | } | |
1833 | ||
1834 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
1835 | } | |
1836 | ||
1837 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
1838 | struct x86_emulate_ops *ops, | |
1839 | struct tss_segment_32 *tss) | |
1840 | { | |
1841 | struct decode_cache *c = &ctxt->decode; | |
1842 | ||
1843 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
1844 | tss->eip = c->eip; | |
1845 | tss->eflags = ctxt->eflags; | |
1846 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
1847 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
1848 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
1849 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
1850 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
1851 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
1852 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
1853 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
1854 | ||
1855 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1856 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1857 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1858 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1859 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
1860 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
1861 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1862 | } | |
1863 | ||
1864 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
1865 | struct x86_emulate_ops *ops, | |
1866 | struct tss_segment_32 *tss) | |
1867 | { | |
1868 | struct decode_cache *c = &ctxt->decode; | |
1869 | int ret; | |
1870 | ||
0f12244f | 1871 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 1872 | emulate_gp(ctxt, 0); |
0f12244f GN |
1873 | return X86EMUL_PROPAGATE_FAULT; |
1874 | } | |
38ba30ba GN |
1875 | c->eip = tss->eip; |
1876 | ctxt->eflags = tss->eflags | 2; | |
1877 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
1878 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
1879 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
1880 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
1881 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
1882 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
1883 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
1884 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
1885 | ||
1886 | /* | |
1887 | * SDM says that segment selectors are loaded before segment | |
1888 | * descriptors | |
1889 | */ | |
1890 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
1891 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1892 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1893 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1894 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1895 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
1896 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
1897 | ||
1898 | /* | |
1899 | * Now load segment descriptors. If fault happenes at this stage | |
1900 | * it is handled in a context of new task | |
1901 | */ | |
1902 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
1903 | if (ret != X86EMUL_CONTINUE) | |
1904 | return ret; | |
1905 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1906 | if (ret != X86EMUL_CONTINUE) | |
1907 | return ret; | |
1908 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1909 | if (ret != X86EMUL_CONTINUE) | |
1910 | return ret; | |
1911 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1912 | if (ret != X86EMUL_CONTINUE) | |
1913 | return ret; | |
1914 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1915 | if (ret != X86EMUL_CONTINUE) | |
1916 | return ret; | |
1917 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
1918 | if (ret != X86EMUL_CONTINUE) | |
1919 | return ret; | |
1920 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
1921 | if (ret != X86EMUL_CONTINUE) | |
1922 | return ret; | |
1923 | ||
1924 | return X86EMUL_CONTINUE; | |
1925 | } | |
1926 | ||
1927 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
1928 | struct x86_emulate_ops *ops, | |
1929 | u16 tss_selector, u16 old_tss_sel, | |
1930 | ulong old_tss_base, struct desc_struct *new_desc) | |
1931 | { | |
1932 | struct tss_segment_32 tss_seg; | |
1933 | int ret; | |
1934 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1935 | ||
1936 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1937 | &err); | |
1938 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1939 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1940 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1941 | return ret; |
1942 | } | |
1943 | ||
1944 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
1945 | ||
1946 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1947 | &err); | |
1948 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1949 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1950 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1951 | return ret; |
1952 | } | |
1953 | ||
1954 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1955 | &err); | |
1956 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1957 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1958 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1959 | return ret; |
1960 | } | |
1961 | ||
1962 | if (old_tss_sel != 0xffff) { | |
1963 | tss_seg.prev_task_link = old_tss_sel; | |
1964 | ||
1965 | ret = ops->write_std(new_tss_base, | |
1966 | &tss_seg.prev_task_link, | |
1967 | sizeof tss_seg.prev_task_link, | |
1968 | ctxt->vcpu, &err); | |
1969 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1970 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1971 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1972 | return ret; |
1973 | } | |
1974 | } | |
1975 | ||
1976 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
1977 | } | |
1978 | ||
1979 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
1980 | struct x86_emulate_ops *ops, |
1981 | u16 tss_selector, int reason, | |
1982 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
1983 | { |
1984 | struct desc_struct curr_tss_desc, next_tss_desc; | |
1985 | int ret; | |
1986 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
1987 | ulong old_tss_base = | |
5951c442 | 1988 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 1989 | u32 desc_limit; |
38ba30ba GN |
1990 | |
1991 | /* FIXME: old_tss_base == ~0 ? */ | |
1992 | ||
1993 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
1994 | if (ret != X86EMUL_CONTINUE) | |
1995 | return ret; | |
1996 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
1997 | if (ret != X86EMUL_CONTINUE) | |
1998 | return ret; | |
1999 | ||
2000 | /* FIXME: check that next_tss_desc is tss */ | |
2001 | ||
2002 | if (reason != TASK_SWITCH_IRET) { | |
2003 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2004 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2005 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2006 | return X86EMUL_PROPAGATE_FAULT; |
2007 | } | |
2008 | } | |
2009 | ||
ceffb459 GN |
2010 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2011 | if (!next_tss_desc.p || | |
2012 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2013 | desc_limit < 0x2b)) { | |
54b8486f | 2014 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2015 | return X86EMUL_PROPAGATE_FAULT; |
2016 | } | |
2017 | ||
2018 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2019 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2020 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2021 | &curr_tss_desc); | |
2022 | } | |
2023 | ||
2024 | if (reason == TASK_SWITCH_IRET) | |
2025 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2026 | ||
2027 | /* set back link to prev task only if NT bit is set in eflags | |
2028 | note that old_tss_sel is not used afetr this point */ | |
2029 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2030 | old_tss_sel = 0xffff; | |
2031 | ||
2032 | if (next_tss_desc.type & 8) | |
2033 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2034 | old_tss_base, &next_tss_desc); | |
2035 | else | |
2036 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2037 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2038 | if (ret != X86EMUL_CONTINUE) |
2039 | return ret; | |
38ba30ba GN |
2040 | |
2041 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2042 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2043 | ||
2044 | if (reason != TASK_SWITCH_IRET) { | |
2045 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2046 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2047 | &next_tss_desc); | |
2048 | } | |
2049 | ||
2050 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2051 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2052 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2053 | ||
e269fb21 JK |
2054 | if (has_error_code) { |
2055 | struct decode_cache *c = &ctxt->decode; | |
2056 | ||
2057 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2058 | c->lock_prefix = 0; | |
2059 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2060 | emulate_push(ctxt, ops); |
e269fb21 JK |
2061 | } |
2062 | ||
38ba30ba GN |
2063 | return ret; |
2064 | } | |
2065 | ||
2066 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2067 | u16 tss_selector, int reason, |
2068 | bool has_error_code, u32 error_code) | |
38ba30ba | 2069 | { |
9aabc88f | 2070 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2071 | struct decode_cache *c = &ctxt->decode; |
2072 | int rc; | |
2073 | ||
38ba30ba | 2074 | c->eip = ctxt->eip; |
e269fb21 | 2075 | c->dst.type = OP_NONE; |
38ba30ba | 2076 | |
e269fb21 JK |
2077 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2078 | has_error_code, error_code); | |
38ba30ba GN |
2079 | |
2080 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2081 | rc = writeback(ctxt, ops); |
95c55886 GN |
2082 | if (rc == X86EMUL_CONTINUE) |
2083 | ctxt->eip = c->eip; | |
38ba30ba GN |
2084 | } |
2085 | ||
19d04437 | 2086 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2087 | } |
2088 | ||
a682e354 | 2089 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2090 | int reg, struct operand *op) |
a682e354 GN |
2091 | { |
2092 | struct decode_cache *c = &ctxt->decode; | |
2093 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2094 | ||
d9271123 | 2095 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
1a6440ae | 2096 | op->addr.mem = register_address(c, base, c->regs[reg]); |
a682e354 GN |
2097 | } |
2098 | ||
63540382 AK |
2099 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2100 | { | |
2101 | emulate_push(ctxt, ctxt->ops); | |
2102 | return X86EMUL_CONTINUE; | |
2103 | } | |
2104 | ||
73fba5f4 AK |
2105 | #define D(_y) { .flags = (_y) } |
2106 | #define N D(0) | |
2107 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2108 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2109 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
2110 | ||
2111 | static struct opcode group1[] = { | |
2112 | X7(D(Lock)), N | |
2113 | }; | |
2114 | ||
2115 | static struct opcode group1A[] = { | |
2116 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2117 | }; | |
2118 | ||
2119 | static struct opcode group3[] = { | |
2120 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2121 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
2122 | X4(D(Undefined)), | |
2123 | }; | |
2124 | ||
2125 | static struct opcode group4[] = { | |
2126 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2127 | N, N, N, N, N, N, | |
2128 | }; | |
2129 | ||
2130 | static struct opcode group5[] = { | |
2131 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
2132 | D(SrcMem | ModRM | Stack), N, | |
2133 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), | |
2134 | D(SrcMem | ModRM | Stack), N, | |
2135 | }; | |
2136 | ||
2137 | static struct group_dual group7 = { { | |
2138 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2139 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2140 | D(SrcMem16 | ModRM | Mov | Priv), |
2141 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 AK |
2142 | }, { |
2143 | D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv), | |
2144 | D(SrcNone | ModRM | DstMem | Mov), N, | |
2145 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2146 | } }; | |
2147 | ||
2148 | static struct opcode group8[] = { | |
2149 | N, N, N, N, | |
2150 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2151 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2152 | }; | |
2153 | ||
2154 | static struct group_dual group9 = { { | |
2155 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2156 | }, { | |
2157 | N, N, N, N, N, N, N, N, | |
2158 | } }; | |
2159 | ||
2160 | static struct opcode opcode_table[256] = { | |
2161 | /* 0x00 - 0x07 */ | |
2162 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2163 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2164 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2165 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2166 | /* 0x08 - 0x0F */ | |
2167 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2168 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2169 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2170 | D(ImplicitOps | Stack | No64), N, | |
2171 | /* 0x10 - 0x17 */ | |
2172 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2173 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2174 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2175 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2176 | /* 0x18 - 0x1F */ | |
2177 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2178 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2179 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2180 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2181 | /* 0x20 - 0x27 */ | |
2182 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2183 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2184 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2185 | /* 0x28 - 0x2F */ | |
2186 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2187 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2188 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2189 | /* 0x30 - 0x37 */ | |
2190 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2191 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2192 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2193 | /* 0x38 - 0x3F */ | |
2194 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2195 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2196 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2197 | N, N, | |
2198 | /* 0x40 - 0x4F */ | |
2199 | X16(D(DstReg)), | |
2200 | /* 0x50 - 0x57 */ | |
63540382 | 2201 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2202 | /* 0x58 - 0x5F */ |
2203 | X8(D(DstReg | Stack)), | |
2204 | /* 0x60 - 0x67 */ | |
2205 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2206 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2207 | N, N, N, N, | |
2208 | /* 0x68 - 0x6F */ | |
63540382 AK |
2209 | I(SrcImm | Mov | Stack, em_push), N, |
2210 | I(SrcImmByte | Mov | Stack, em_push), N, | |
73fba5f4 AK |
2211 | D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */ |
2212 | D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
2213 | /* 0x70 - 0x7F */ | |
2214 | X16(D(SrcImmByte)), | |
2215 | /* 0x80 - 0x87 */ | |
2216 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2217 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2218 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2219 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
2220 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2221 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2222 | /* 0x88 - 0x8F */ | |
2223 | D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov), | |
2224 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov), | |
342fc630 | 2225 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2226 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2227 | /* 0x90 - 0x97 */ | |
3d9e77df | 2228 | X8(D(SrcAcc | DstReg)), |
73fba5f4 AK |
2229 | /* 0x98 - 0x9F */ |
2230 | N, N, D(SrcImmFAddr | No64), N, | |
2231 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, | |
2232 | /* 0xA0 - 0xA7 */ | |
2233 | D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs), | |
2234 | D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs), | |
2235 | D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String), | |
2236 | D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String), | |
2237 | /* 0xA8 - 0xAF */ | |
06cb7046 WY |
2238 | D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), |
2239 | D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String), | |
73fba5f4 AK |
2240 | D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String), |
2241 | D(ByteOp | DstDI | String), D(DstDI | String), | |
2242 | /* 0xB0 - 0xB7 */ | |
2243 | X8(D(ByteOp | DstReg | SrcImm | Mov)), | |
2244 | /* 0xB8 - 0xBF */ | |
2245 | X8(D(DstReg | SrcImm | Mov)), | |
2246 | /* 0xC0 - 0xC7 */ | |
2247 | D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM), | |
2248 | N, D(ImplicitOps | Stack), N, N, | |
2249 | D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov), | |
2250 | /* 0xC8 - 0xCF */ | |
2251 | N, N, N, D(ImplicitOps | Stack), | |
2252 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2253 | /* 0xD0 - 0xD7 */ | |
c034da8b | 2254 | D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM), |
73fba5f4 AK |
2255 | D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM), |
2256 | N, N, N, N, | |
2257 | /* 0xD8 - 0xDF */ | |
2258 | N, N, N, N, N, N, N, N, | |
2259 | /* 0xE0 - 0xE7 */ | |
2260 | N, N, N, N, | |
2261 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), | |
2262 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), | |
2263 | /* 0xE8 - 0xEF */ | |
2264 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2265 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
2266 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
2267 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
2268 | /* 0xF0 - 0xF7 */ | |
2269 | N, N, N, N, | |
2270 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2271 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2272 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2273 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2274 | }; | |
2275 | ||
2276 | static struct opcode twobyte_table[256] = { | |
2277 | /* 0x00 - 0x0F */ | |
2278 | N, GD(0, &group7), N, N, | |
2279 | N, D(ImplicitOps), D(ImplicitOps | Priv), N, | |
2280 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, | |
2281 | N, D(ImplicitOps | ModRM), N, N, | |
2282 | /* 0x10 - 0x1F */ | |
2283 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2284 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2285 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2286 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2287 | N, N, N, N, |
2288 | N, N, N, N, N, N, N, N, | |
2289 | /* 0x30 - 0x3F */ | |
2290 | D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N, | |
2291 | D(ImplicitOps), D(ImplicitOps | Priv), N, N, | |
2292 | N, N, N, N, N, N, N, N, | |
2293 | /* 0x40 - 0x4F */ | |
2294 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2295 | /* 0x50 - 0x5F */ | |
2296 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2297 | /* 0x60 - 0x6F */ | |
2298 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2299 | /* 0x70 - 0x7F */ | |
2300 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2301 | /* 0x80 - 0x8F */ | |
2302 | X16(D(SrcImm)), | |
2303 | /* 0x90 - 0x9F */ | |
2304 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2305 | /* 0xA0 - 0xA7 */ | |
2306 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2307 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2308 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2309 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2310 | /* 0xA8 - 0xAF */ | |
2311 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2312 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2313 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2314 | D(DstMem | SrcReg | Src2CL | ModRM), | |
2315 | D(ModRM), N, | |
2316 | /* 0xB0 - 0xB7 */ | |
2317 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2318 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2319 | N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov), | |
2320 | D(DstReg | SrcMem16 | ModRM | Mov), | |
2321 | /* 0xB8 - 0xBF */ | |
2322 | N, N, | |
2323 | G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2324 | N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov), | |
2325 | D(DstReg | SrcMem16 | ModRM | Mov), | |
2326 | /* 0xC0 - 0xCF */ | |
2327 | N, N, N, D(DstMem | SrcReg | ModRM | Mov), | |
2328 | N, N, N, GD(0, &group9), | |
2329 | N, N, N, N, N, N, N, N, | |
2330 | /* 0xD0 - 0xDF */ | |
2331 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2332 | /* 0xE0 - 0xEF */ | |
2333 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2334 | /* 0xF0 - 0xFF */ | |
2335 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2336 | }; | |
2337 | ||
2338 | #undef D | |
2339 | #undef N | |
2340 | #undef G | |
2341 | #undef GD | |
2342 | #undef I | |
2343 | ||
dde7e6d1 AK |
2344 | int |
2345 | x86_decode_insn(struct x86_emulate_ctxt *ctxt) | |
2346 | { | |
2347 | struct x86_emulate_ops *ops = ctxt->ops; | |
2348 | struct decode_cache *c = &ctxt->decode; | |
2349 | int rc = X86EMUL_CONTINUE; | |
2350 | int mode = ctxt->mode; | |
2351 | int def_op_bytes, def_ad_bytes, dual, goffset; | |
2352 | struct opcode opcode, *g_mod012, *g_mod3; | |
2dbd0dd7 | 2353 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 AK |
2354 | |
2355 | /* we cannot decode insn before we complete previous rep insn */ | |
2356 | WARN_ON(ctxt->restart); | |
2357 | ||
2358 | c->eip = ctxt->eip; | |
2359 | c->fetch.start = c->fetch.end = c->eip; | |
2360 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); | |
2361 | ||
2362 | switch (mode) { | |
2363 | case X86EMUL_MODE_REAL: | |
2364 | case X86EMUL_MODE_VM86: | |
2365 | case X86EMUL_MODE_PROT16: | |
2366 | def_op_bytes = def_ad_bytes = 2; | |
2367 | break; | |
2368 | case X86EMUL_MODE_PROT32: | |
2369 | def_op_bytes = def_ad_bytes = 4; | |
2370 | break; | |
2371 | #ifdef CONFIG_X86_64 | |
2372 | case X86EMUL_MODE_PROT64: | |
2373 | def_op_bytes = 4; | |
2374 | def_ad_bytes = 8; | |
2375 | break; | |
2376 | #endif | |
2377 | default: | |
2378 | return -1; | |
2379 | } | |
2380 | ||
2381 | c->op_bytes = def_op_bytes; | |
2382 | c->ad_bytes = def_ad_bytes; | |
2383 | ||
2384 | /* Legacy prefixes. */ | |
2385 | for (;;) { | |
2386 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2387 | case 0x66: /* operand-size override */ | |
2388 | /* switch between 2/4 bytes */ | |
2389 | c->op_bytes = def_op_bytes ^ 6; | |
2390 | break; | |
2391 | case 0x67: /* address-size override */ | |
2392 | if (mode == X86EMUL_MODE_PROT64) | |
2393 | /* switch between 4/8 bytes */ | |
2394 | c->ad_bytes = def_ad_bytes ^ 12; | |
2395 | else | |
2396 | /* switch between 2/4 bytes */ | |
2397 | c->ad_bytes = def_ad_bytes ^ 6; | |
2398 | break; | |
2399 | case 0x26: /* ES override */ | |
2400 | case 0x2e: /* CS override */ | |
2401 | case 0x36: /* SS override */ | |
2402 | case 0x3e: /* DS override */ | |
2403 | set_seg_override(c, (c->b >> 3) & 3); | |
2404 | break; | |
2405 | case 0x64: /* FS override */ | |
2406 | case 0x65: /* GS override */ | |
2407 | set_seg_override(c, c->b & 7); | |
2408 | break; | |
2409 | case 0x40 ... 0x4f: /* REX */ | |
2410 | if (mode != X86EMUL_MODE_PROT64) | |
2411 | goto done_prefixes; | |
2412 | c->rex_prefix = c->b; | |
2413 | continue; | |
2414 | case 0xf0: /* LOCK */ | |
2415 | c->lock_prefix = 1; | |
2416 | break; | |
2417 | case 0xf2: /* REPNE/REPNZ */ | |
2418 | c->rep_prefix = REPNE_PREFIX; | |
2419 | break; | |
2420 | case 0xf3: /* REP/REPE/REPZ */ | |
2421 | c->rep_prefix = REPE_PREFIX; | |
2422 | break; | |
2423 | default: | |
2424 | goto done_prefixes; | |
2425 | } | |
2426 | ||
2427 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2428 | ||
2429 | c->rex_prefix = 0; | |
2430 | } | |
2431 | ||
2432 | done_prefixes: | |
2433 | ||
2434 | /* REX prefix. */ | |
1e87e3ef AK |
2435 | if (c->rex_prefix & 8) |
2436 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2437 | |
2438 | /* Opcode byte(s). */ | |
2439 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2440 | /* Two-byte opcode? */ |
2441 | if (c->b == 0x0f) { | |
2442 | c->twobyte = 1; | |
2443 | c->b = insn_fetch(u8, 1, c->eip); | |
2444 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2445 | } |
2446 | c->d = opcode.flags; | |
2447 | ||
2448 | if (c->d & Group) { | |
2449 | dual = c->d & GroupDual; | |
2450 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2451 | --c->eip; | |
2452 | ||
2453 | if (c->d & GroupDual) { | |
2454 | g_mod012 = opcode.u.gdual->mod012; | |
2455 | g_mod3 = opcode.u.gdual->mod3; | |
2456 | } else | |
2457 | g_mod012 = g_mod3 = opcode.u.group; | |
2458 | ||
2459 | c->d &= ~(Group | GroupDual); | |
2460 | ||
2461 | goffset = (c->modrm >> 3) & 7; | |
2462 | ||
2463 | if ((c->modrm >> 6) == 3) | |
2464 | opcode = g_mod3[goffset]; | |
2465 | else | |
2466 | opcode = g_mod012[goffset]; | |
2467 | c->d |= opcode.flags; | |
2468 | } | |
2469 | ||
2470 | c->execute = opcode.u.execute; | |
2471 | ||
2472 | /* Unrecognised? */ | |
2473 | if (c->d == 0 || (c->d & Undefined)) { | |
2474 | DPRINTF("Cannot emulate %02x\n", c->b); | |
2475 | return -1; | |
2476 | } | |
2477 | ||
2478 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) | |
2479 | c->op_bytes = 8; | |
2480 | ||
7f9b4b75 AK |
2481 | if (c->d & Op3264) { |
2482 | if (mode == X86EMUL_MODE_PROT64) | |
2483 | c->op_bytes = 8; | |
2484 | else | |
2485 | c->op_bytes = 4; | |
2486 | } | |
2487 | ||
dde7e6d1 | 2488 | /* ModRM and SIB bytes. */ |
09ee57cd | 2489 | if (c->d & ModRM) { |
2dbd0dd7 | 2490 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2491 | if (!c->has_seg_override) |
2492 | set_seg_override(c, c->modrm_seg); | |
2493 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2494 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2495 | if (rc != X86EMUL_CONTINUE) |
2496 | goto done; | |
2497 | ||
2498 | if (!c->has_seg_override) | |
2499 | set_seg_override(c, VCPU_SREG_DS); | |
2500 | ||
2dbd0dd7 AK |
2501 | if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d)) |
2502 | memop.addr.mem += seg_override_base(ctxt, ops, c); | |
dde7e6d1 | 2503 | |
2dbd0dd7 AK |
2504 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
2505 | memop.addr.mem = (u32)memop.addr.mem; | |
dde7e6d1 | 2506 | |
2dbd0dd7 AK |
2507 | if (memop.type == OP_MEM && c->rip_relative) |
2508 | memop.addr.mem += c->eip; | |
dde7e6d1 AK |
2509 | |
2510 | /* | |
2511 | * Decode and fetch the source operand: register, memory | |
2512 | * or immediate. | |
2513 | */ | |
2514 | switch (c->d & SrcMask) { | |
2515 | case SrcNone: | |
2516 | break; | |
2517 | case SrcReg: | |
2518 | decode_register_operand(&c->src, c, 0); | |
2519 | break; | |
2520 | case SrcMem16: | |
2dbd0dd7 | 2521 | memop.bytes = 2; |
dde7e6d1 AK |
2522 | goto srcmem_common; |
2523 | case SrcMem32: | |
2dbd0dd7 | 2524 | memop.bytes = 4; |
dde7e6d1 AK |
2525 | goto srcmem_common; |
2526 | case SrcMem: | |
2dbd0dd7 | 2527 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2528 | c->op_bytes; |
dde7e6d1 | 2529 | srcmem_common: |
2dbd0dd7 | 2530 | c->src = memop; |
dde7e6d1 AK |
2531 | break; |
2532 | case SrcImm: | |
2533 | case SrcImmU: | |
2534 | c->src.type = OP_IMM; | |
1a6440ae | 2535 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2536 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
2537 | if (c->src.bytes == 8) | |
2538 | c->src.bytes = 4; | |
2539 | /* NB. Immediates are sign-extended as necessary. */ | |
2540 | switch (c->src.bytes) { | |
2541 | case 1: | |
2542 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2543 | break; | |
2544 | case 2: | |
2545 | c->src.val = insn_fetch(s16, 2, c->eip); | |
2546 | break; | |
2547 | case 4: | |
2548 | c->src.val = insn_fetch(s32, 4, c->eip); | |
2549 | break; | |
2550 | } | |
2551 | if ((c->d & SrcMask) == SrcImmU) { | |
2552 | switch (c->src.bytes) { | |
2553 | case 1: | |
2554 | c->src.val &= 0xff; | |
2555 | break; | |
2556 | case 2: | |
2557 | c->src.val &= 0xffff; | |
2558 | break; | |
2559 | case 4: | |
2560 | c->src.val &= 0xffffffff; | |
2561 | break; | |
2562 | } | |
2563 | } | |
2564 | break; | |
2565 | case SrcImmByte: | |
2566 | case SrcImmUByte: | |
2567 | c->src.type = OP_IMM; | |
1a6440ae | 2568 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2569 | c->src.bytes = 1; |
2570 | if ((c->d & SrcMask) == SrcImmByte) | |
2571 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2572 | else | |
2573 | c->src.val = insn_fetch(u8, 1, c->eip); | |
2574 | break; | |
2575 | case SrcAcc: | |
2576 | c->src.type = OP_REG; | |
2577 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2578 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2579 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2580 | break; |
2581 | case SrcOne: | |
2582 | c->src.bytes = 1; | |
2583 | c->src.val = 1; | |
2584 | break; | |
2585 | case SrcSI: | |
2586 | c->src.type = OP_MEM; | |
2587 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2588 | c->src.addr.mem = |
dde7e6d1 AK |
2589 | register_address(c, seg_override_base(ctxt, ops, c), |
2590 | c->regs[VCPU_REGS_RSI]); | |
2591 | c->src.val = 0; | |
2592 | break; | |
2593 | case SrcImmFAddr: | |
2594 | c->src.type = OP_IMM; | |
1a6440ae | 2595 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2596 | c->src.bytes = c->op_bytes + 2; |
2597 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2598 | break; | |
2599 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2600 | memop.bytes = c->op_bytes + 2; |
2601 | goto srcmem_common; | |
dde7e6d1 AK |
2602 | break; |
2603 | } | |
2604 | ||
2605 | /* | |
2606 | * Decode and fetch the second source operand: register, memory | |
2607 | * or immediate. | |
2608 | */ | |
2609 | switch (c->d & Src2Mask) { | |
2610 | case Src2None: | |
2611 | break; | |
2612 | case Src2CL: | |
2613 | c->src2.bytes = 1; | |
2614 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2615 | break; | |
2616 | case Src2ImmByte: | |
2617 | c->src2.type = OP_IMM; | |
1a6440ae | 2618 | c->src2.addr.mem = c->eip; |
dde7e6d1 AK |
2619 | c->src2.bytes = 1; |
2620 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
2621 | break; | |
2622 | case Src2One: | |
2623 | c->src2.bytes = 1; | |
2624 | c->src2.val = 1; | |
2625 | break; | |
2626 | } | |
2627 | ||
2628 | /* Decode and fetch the destination operand: register or memory. */ | |
2629 | switch (c->d & DstMask) { | |
dde7e6d1 AK |
2630 | case DstReg: |
2631 | decode_register_operand(&c->dst, c, | |
2632 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); | |
2633 | break; | |
2634 | case DstMem: | |
2635 | case DstMem64: | |
2dbd0dd7 | 2636 | c->dst = memop; |
dde7e6d1 AK |
2637 | if ((c->d & DstMask) == DstMem64) |
2638 | c->dst.bytes = 8; | |
2639 | else | |
2640 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2dbd0dd7 | 2641 | if (c->dst.type == OP_MEM && (c->d & BitOp)) { |
dde7e6d1 AK |
2642 | unsigned long mask = ~(c->dst.bytes * 8 - 1); |
2643 | ||
1a6440ae | 2644 | c->dst.addr.mem = c->dst.addr.mem + |
dde7e6d1 AK |
2645 | (c->src.val & mask) / 8; |
2646 | } | |
2dbd0dd7 | 2647 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
2648 | break; |
2649 | case DstAcc: | |
2650 | c->dst.type = OP_REG; | |
2651 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2652 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2653 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
2654 | c->dst.orig_val = c->dst.val; |
2655 | break; | |
2656 | case DstDI: | |
2657 | c->dst.type = OP_MEM; | |
2658 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2659 | c->dst.addr.mem = |
dde7e6d1 AK |
2660 | register_address(c, es_base(ctxt, ops), |
2661 | c->regs[VCPU_REGS_RDI]); | |
2662 | c->dst.val = 0; | |
2663 | break; | |
36089fed WY |
2664 | case ImplicitOps: |
2665 | /* Special instructions do their own operand decoding. */ | |
2666 | default: | |
2667 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2668 | return 0; | |
dde7e6d1 AK |
2669 | } |
2670 | ||
2671 | done: | |
2672 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
2673 | } | |
2674 | ||
8b4caf66 | 2675 | int |
9aabc88f | 2676 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 2677 | { |
9aabc88f | 2678 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 2679 | u64 msr_data; |
8b4caf66 | 2680 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2681 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2682 | int saved_dst_type = c->dst.type; |
6e154e56 | 2683 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 2684 | |
9de41573 | 2685 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2686 | |
1161624f | 2687 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2688 | emulate_ud(ctxt); |
1161624f GN |
2689 | goto done; |
2690 | } | |
2691 | ||
d380a5e4 | 2692 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2693 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2694 | emulate_ud(ctxt); |
d380a5e4 GN |
2695 | goto done; |
2696 | } | |
2697 | ||
e92805ac | 2698 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2699 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 2700 | emulate_gp(ctxt, 0); |
e92805ac GN |
2701 | goto done; |
2702 | } | |
2703 | ||
b9fa9d6b | 2704 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2705 | ctxt->restart = true; |
b9fa9d6b | 2706 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2707 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 GN |
2708 | string_done: |
2709 | ctxt->restart = false; | |
95c55886 | 2710 | ctxt->eip = c->eip; |
b9fa9d6b AK |
2711 | goto done; |
2712 | } | |
2713 | /* The second termination condition only applies for REPE | |
2714 | * and REPNE. Test if the repeat string operation prefix is | |
2715 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2716 | * corresponding termination condition according to: | |
2717 | * - if REPE/REPZ and ZF = 0 then done | |
2718 | * - if REPNE/REPNZ and ZF = 1 then done | |
2719 | */ | |
2720 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
5cd21917 | 2721 | (c->b == 0xae) || (c->b == 0xaf)) { |
b9fa9d6b | 2722 | if ((c->rep_prefix == REPE_PREFIX) && |
5cd21917 GN |
2723 | ((ctxt->eflags & EFLG_ZF) == 0)) |
2724 | goto string_done; | |
b9fa9d6b | 2725 | if ((c->rep_prefix == REPNE_PREFIX) && |
5cd21917 GN |
2726 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) |
2727 | goto string_done; | |
b9fa9d6b | 2728 | } |
063db061 | 2729 | c->eip = ctxt->eip; |
b9fa9d6b AK |
2730 | } |
2731 | ||
8b4caf66 | 2732 | if (c->src.type == OP_MEM) { |
2dbd0dd7 AK |
2733 | if (c->d & NoAccess) |
2734 | goto no_fetch; | |
1a6440ae | 2735 | rc = read_emulated(ctxt, ops, c->src.addr.mem, |
414e6277 | 2736 | c->src.valptr, c->src.bytes); |
b60d513c | 2737 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 2738 | goto done; |
16518d5a | 2739 | c->src.orig_val64 = c->src.val64; |
2dbd0dd7 AK |
2740 | no_fetch: |
2741 | ; | |
8b4caf66 LV |
2742 | } |
2743 | ||
e35b7b9c | 2744 | if (c->src2.type == OP_MEM) { |
1a6440ae | 2745 | rc = read_emulated(ctxt, ops, c->src2.addr.mem, |
9de41573 | 2746 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
2747 | if (rc != X86EMUL_CONTINUE) |
2748 | goto done; | |
2749 | } | |
2750 | ||
8b4caf66 LV |
2751 | if ((c->d & DstMask) == ImplicitOps) |
2752 | goto special_insn; | |
2753 | ||
2754 | ||
69f55cb1 GN |
2755 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2756 | /* optimisation - avoid slow emulated read if Mov */ | |
1a6440ae | 2757 | rc = read_emulated(ctxt, ops, c->dst.addr.mem, |
9de41573 | 2758 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
2759 | if (rc != X86EMUL_CONTINUE) |
2760 | goto done; | |
038e51de | 2761 | } |
e4e03ded | 2762 | c->dst.orig_val = c->dst.val; |
038e51de | 2763 | |
018a98db AK |
2764 | special_insn: |
2765 | ||
ef65c889 AK |
2766 | if (c->execute) { |
2767 | rc = c->execute(ctxt); | |
2768 | if (rc != X86EMUL_CONTINUE) | |
2769 | goto done; | |
2770 | goto writeback; | |
2771 | } | |
2772 | ||
e4e03ded | 2773 | if (c->twobyte) |
6aa8b732 AK |
2774 | goto twobyte_insn; |
2775 | ||
e4e03ded | 2776 | switch (c->b) { |
6aa8b732 AK |
2777 | case 0x00 ... 0x05: |
2778 | add: /* add */ | |
05f086f8 | 2779 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2780 | break; |
0934ac9d | 2781 | case 0x06: /* push es */ |
79168fd1 | 2782 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
2783 | break; |
2784 | case 0x07: /* pop es */ | |
0934ac9d | 2785 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2786 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2787 | goto done; |
2788 | break; | |
6aa8b732 AK |
2789 | case 0x08 ... 0x0d: |
2790 | or: /* or */ | |
05f086f8 | 2791 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2792 | break; |
0934ac9d | 2793 | case 0x0e: /* push cs */ |
79168fd1 | 2794 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 2795 | break; |
6aa8b732 AK |
2796 | case 0x10 ... 0x15: |
2797 | adc: /* adc */ | |
05f086f8 | 2798 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2799 | break; |
0934ac9d | 2800 | case 0x16: /* push ss */ |
79168fd1 | 2801 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
2802 | break; |
2803 | case 0x17: /* pop ss */ | |
0934ac9d | 2804 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2805 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2806 | goto done; |
2807 | break; | |
6aa8b732 AK |
2808 | case 0x18 ... 0x1d: |
2809 | sbb: /* sbb */ | |
05f086f8 | 2810 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2811 | break; |
0934ac9d | 2812 | case 0x1e: /* push ds */ |
79168fd1 | 2813 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
2814 | break; |
2815 | case 0x1f: /* pop ds */ | |
0934ac9d | 2816 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2817 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2818 | goto done; |
2819 | break; | |
aa3a816b | 2820 | case 0x20 ... 0x25: |
6aa8b732 | 2821 | and: /* and */ |
05f086f8 | 2822 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2823 | break; |
2824 | case 0x28 ... 0x2d: | |
2825 | sub: /* sub */ | |
05f086f8 | 2826 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2827 | break; |
2828 | case 0x30 ... 0x35: | |
2829 | xor: /* xor */ | |
05f086f8 | 2830 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2831 | break; |
2832 | case 0x38 ... 0x3d: | |
2833 | cmp: /* cmp */ | |
05f086f8 | 2834 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2835 | break; |
33615aa9 AK |
2836 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2837 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2838 | break; | |
2839 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2840 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2841 | break; | |
33615aa9 AK |
2842 | case 0x58 ... 0x5f: /* pop reg */ |
2843 | pop_instruction: | |
350f69dc | 2844 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2845 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2846 | goto done; |
33615aa9 | 2847 | break; |
abcf14b5 | 2848 | case 0x60: /* pusha */ |
c37eda13 WY |
2849 | rc = emulate_pusha(ctxt, ops); |
2850 | if (rc != X86EMUL_CONTINUE) | |
2851 | goto done; | |
abcf14b5 MG |
2852 | break; |
2853 | case 0x61: /* popa */ | |
2854 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2855 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2856 | goto done; |
2857 | break; | |
6aa8b732 | 2858 | case 0x63: /* movsxd */ |
8b4caf66 | 2859 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2860 | goto cannot_emulate; |
e4e03ded | 2861 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2862 | break; |
018a98db AK |
2863 | case 0x6c: /* insb */ |
2864 | case 0x6d: /* insw/insd */ | |
7972995b | 2865 | c->dst.bytes = min(c->dst.bytes, 4u); |
f850e2e6 | 2866 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2867 | c->dst.bytes)) { |
54b8486f | 2868 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2869 | goto done; |
2870 | } | |
7b262e90 GN |
2871 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, |
2872 | c->regs[VCPU_REGS_RDX], &c->dst.val)) | |
7972995b GN |
2873 | goto done; /* IO is needed, skip writeback */ |
2874 | break; | |
018a98db AK |
2875 | case 0x6e: /* outsb */ |
2876 | case 0x6f: /* outsw/outsd */ | |
7972995b | 2877 | c->src.bytes = min(c->src.bytes, 4u); |
f850e2e6 | 2878 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2879 | c->src.bytes)) { |
54b8486f | 2880 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2881 | goto done; |
2882 | } | |
7972995b GN |
2883 | ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], |
2884 | &c->src.val, 1, ctxt->vcpu); | |
2885 | ||
2886 | c->dst.type = OP_NONE; /* nothing to writeback */ | |
2887 | break; | |
b2833e3c | 2888 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2889 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2890 | jmp_rel(c, c->src.val); |
018a98db | 2891 | break; |
6aa8b732 | 2892 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2893 | switch (c->modrm_reg) { |
6aa8b732 AK |
2894 | case 0: |
2895 | goto add; | |
2896 | case 1: | |
2897 | goto or; | |
2898 | case 2: | |
2899 | goto adc; | |
2900 | case 3: | |
2901 | goto sbb; | |
2902 | case 4: | |
2903 | goto and; | |
2904 | case 5: | |
2905 | goto sub; | |
2906 | case 6: | |
2907 | goto xor; | |
2908 | case 7: | |
2909 | goto cmp; | |
2910 | } | |
2911 | break; | |
2912 | case 0x84 ... 0x85: | |
dfb507c4 | 2913 | test: |
05f086f8 | 2914 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2915 | break; |
2916 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2917 | xchg: |
6aa8b732 | 2918 | /* Write back the register source. */ |
e4e03ded | 2919 | switch (c->dst.bytes) { |
6aa8b732 | 2920 | case 1: |
1a6440ae | 2921 | *(u8 *) c->src.addr.reg = (u8) c->dst.val; |
6aa8b732 AK |
2922 | break; |
2923 | case 2: | |
1a6440ae | 2924 | *(u16 *) c->src.addr.reg = (u16) c->dst.val; |
6aa8b732 AK |
2925 | break; |
2926 | case 4: | |
1a6440ae | 2927 | *c->src.addr.reg = (u32) c->dst.val; |
6aa8b732 AK |
2928 | break; /* 64b reg: zero-extend */ |
2929 | case 8: | |
1a6440ae | 2930 | *c->src.addr.reg = c->dst.val; |
6aa8b732 AK |
2931 | break; |
2932 | } | |
2933 | /* | |
2934 | * Write back the memory destination with implicit LOCK | |
2935 | * prefix. | |
2936 | */ | |
e4e03ded LV |
2937 | c->dst.val = c->src.val; |
2938 | c->lock_prefix = 1; | |
6aa8b732 | 2939 | break; |
6aa8b732 | 2940 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2941 | goto mov; |
79168fd1 GN |
2942 | case 0x8c: /* mov r/m, sreg */ |
2943 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 2944 | emulate_ud(ctxt); |
5e3ae6c5 | 2945 | goto done; |
38d5bc6d | 2946 | } |
79168fd1 | 2947 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 2948 | break; |
7e0b54b1 | 2949 | case 0x8d: /* lea r16/r32, m */ |
342fc630 | 2950 | c->dst.val = c->src.addr.mem; |
7e0b54b1 | 2951 | break; |
4257198a GT |
2952 | case 0x8e: { /* mov seg, r/m16 */ |
2953 | uint16_t sel; | |
4257198a GT |
2954 | |
2955 | sel = c->src.val; | |
8b9f4414 | 2956 | |
c697518a GN |
2957 | if (c->modrm_reg == VCPU_SREG_CS || |
2958 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 2959 | emulate_ud(ctxt); |
8b9f4414 GN |
2960 | goto done; |
2961 | } | |
2962 | ||
310b5d30 | 2963 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 2964 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 2965 | |
2e873022 | 2966 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
2967 | |
2968 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2969 | break; | |
2970 | } | |
6aa8b732 | 2971 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 2972 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 2973 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 2974 | goto done; |
6aa8b732 | 2975 | break; |
3d9e77df AK |
2976 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
2977 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 2978 | break; |
b13354f8 | 2979 | goto xchg; |
fd2a7608 | 2980 | case 0x9c: /* pushf */ |
05f086f8 | 2981 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 2982 | emulate_push(ctxt, ops); |
8cdbd2c9 | 2983 | break; |
535eabcf | 2984 | case 0x9d: /* popf */ |
2b48cc75 | 2985 | c->dst.type = OP_REG; |
1a6440ae | 2986 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 2987 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
2988 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
2989 | if (rc != X86EMUL_CONTINUE) | |
2990 | goto done; | |
2991 | break; | |
5d55f299 | 2992 | case 0xa0 ... 0xa3: /* mov */ |
6aa8b732 | 2993 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 2994 | goto mov; |
6aa8b732 | 2995 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 2996 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a6440ae | 2997 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem); |
a682e354 | 2998 | goto cmp; |
dfb507c4 MG |
2999 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3000 | goto test; | |
6aa8b732 | 3001 | case 0xaa ... 0xab: /* stos */ |
6aa8b732 | 3002 | case 0xac ... 0xad: /* lods */ |
a682e354 | 3003 | goto mov; |
6aa8b732 AK |
3004 | case 0xae ... 0xaf: /* scas */ |
3005 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
3006 | goto cannot_emulate; | |
a5e2e82b | 3007 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 3008 | goto mov; |
018a98db AK |
3009 | case 0xc0 ... 0xc1: |
3010 | emulate_grp2(ctxt); | |
3011 | break; | |
111de5d6 | 3012 | case 0xc3: /* ret */ |
cf5de4f8 | 3013 | c->dst.type = OP_REG; |
1a6440ae | 3014 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3015 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3016 | goto pop_instruction; |
018a98db AK |
3017 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
3018 | mov: | |
3019 | c->dst.val = c->src.val; | |
3020 | break; | |
a77ab5ea AK |
3021 | case 0xcb: /* ret far */ |
3022 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e MG |
3023 | if (rc != X86EMUL_CONTINUE) |
3024 | goto done; | |
3025 | break; | |
6e154e56 MG |
3026 | case 0xcc: /* int3 */ |
3027 | irq = 3; | |
3028 | goto do_interrupt; | |
3029 | case 0xcd: /* int n */ | |
3030 | irq = c->src.val; | |
3031 | do_interrupt: | |
3032 | rc = emulate_int(ctxt, ops, irq); | |
3033 | if (rc != X86EMUL_CONTINUE) | |
3034 | goto done; | |
3035 | break; | |
3036 | case 0xce: /* into */ | |
3037 | if (ctxt->eflags & EFLG_OF) { | |
3038 | irq = 4; | |
3039 | goto do_interrupt; | |
3040 | } | |
3041 | break; | |
62bd430e MG |
3042 | case 0xcf: /* iret */ |
3043 | rc = emulate_iret(ctxt, ops); | |
3044 | ||
1b30eaa8 | 3045 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
3046 | goto done; |
3047 | break; | |
018a98db | 3048 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3049 | emulate_grp2(ctxt); |
3050 | break; | |
3051 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3052 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3053 | emulate_grp2(ctxt); | |
3054 | break; | |
a6a3034c MG |
3055 | case 0xe4: /* inb */ |
3056 | case 0xe5: /* in */ | |
cf8f70bf | 3057 | goto do_io_in; |
a6a3034c MG |
3058 | case 0xe6: /* outb */ |
3059 | case 0xe7: /* out */ | |
cf8f70bf | 3060 | goto do_io_out; |
1a52e051 | 3061 | case 0xe8: /* call (near) */ { |
d53c4777 | 3062 | long int rel = c->src.val; |
e4e03ded | 3063 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3064 | jmp_rel(c, rel); |
79168fd1 | 3065 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3066 | break; |
1a52e051 NK |
3067 | } |
3068 | case 0xe9: /* jmp rel */ | |
954cd36f | 3069 | goto jmp; |
414e6277 GN |
3070 | case 0xea: { /* jmp far */ |
3071 | unsigned short sel; | |
ea79849d | 3072 | jump_far: |
414e6277 GN |
3073 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3074 | ||
3075 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3076 | goto done; |
954cd36f | 3077 | |
414e6277 GN |
3078 | c->eip = 0; |
3079 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3080 | break; |
414e6277 | 3081 | } |
954cd36f GT |
3082 | case 0xeb: |
3083 | jmp: /* jmp rel short */ | |
7a957275 | 3084 | jmp_rel(c, c->src.val); |
a01af5ec | 3085 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3086 | break; |
a6a3034c MG |
3087 | case 0xec: /* in al,dx */ |
3088 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3089 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3090 | do_io_in: | |
3091 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3092 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3093 | emulate_gp(ctxt, 0); |
cf8f70bf GN |
3094 | goto done; |
3095 | } | |
7b262e90 GN |
3096 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3097 | &c->dst.val)) | |
cf8f70bf GN |
3098 | goto done; /* IO is needed */ |
3099 | break; | |
ce7a0ad3 WY |
3100 | case 0xee: /* out dx,al */ |
3101 | case 0xef: /* out dx,(e/r)ax */ | |
cf8f70bf GN |
3102 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3103 | do_io_out: | |
3104 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3105 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3106 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
3107 | goto done; |
3108 | } | |
cf8f70bf GN |
3109 | ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, |
3110 | ctxt->vcpu); | |
3111 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 3112 | break; |
111de5d6 | 3113 | case 0xf4: /* hlt */ |
ad312c7c | 3114 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3115 | break; |
111de5d6 AK |
3116 | case 0xf5: /* cmc */ |
3117 | /* complement carry flag from eflags reg */ | |
3118 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3119 | break; |
018a98db | 3120 | case 0xf6 ... 0xf7: /* Grp3 */ |
aca06a83 GN |
3121 | if (!emulate_grp3(ctxt, ops)) |
3122 | goto cannot_emulate; | |
018a98db | 3123 | break; |
111de5d6 AK |
3124 | case 0xf8: /* clc */ |
3125 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3126 | break; |
8744aa9a MG |
3127 | case 0xf9: /* stc */ |
3128 | ctxt->eflags |= EFLG_CF; | |
3129 | break; | |
111de5d6 | 3130 | case 0xfa: /* cli */ |
07cbc6c1 | 3131 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3132 | emulate_gp(ctxt, 0); |
07cbc6c1 | 3133 | goto done; |
36089fed | 3134 | } else |
f850e2e6 | 3135 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3136 | break; |
3137 | case 0xfb: /* sti */ | |
07cbc6c1 | 3138 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3139 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3140 | goto done; |
3141 | } else { | |
95cb2295 | 3142 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3143 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3144 | } |
111de5d6 | 3145 | break; |
fb4616f4 MG |
3146 | case 0xfc: /* cld */ |
3147 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3148 | break; |
3149 | case 0xfd: /* std */ | |
3150 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3151 | break; |
ea79849d GN |
3152 | case 0xfe: /* Grp4 */ |
3153 | grp45: | |
018a98db | 3154 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 3155 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3156 | goto done; |
3157 | break; | |
ea79849d GN |
3158 | case 0xff: /* Grp5 */ |
3159 | if (c->modrm_reg == 5) | |
3160 | goto jump_far; | |
3161 | goto grp45; | |
91269b8f AK |
3162 | default: |
3163 | goto cannot_emulate; | |
6aa8b732 | 3164 | } |
018a98db AK |
3165 | |
3166 | writeback: | |
3167 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3168 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3169 | goto done; |
3170 | ||
5cd21917 GN |
3171 | /* |
3172 | * restore dst type in case the decoding will be reused | |
3173 | * (happens for string instruction ) | |
3174 | */ | |
3175 | c->dst.type = saved_dst_type; | |
3176 | ||
a682e354 | 3177 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3178 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3179 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3180 | |
3181 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3182 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3183 | &c->dst); | |
d9271123 | 3184 | |
5cd21917 | 3185 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3186 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3187 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
7b262e90 GN |
3188 | /* |
3189 | * Re-enter guest when pio read ahead buffer is empty or, | |
3190 | * if it is not used, after each 1024 iteration. | |
3191 | */ | |
3192 | if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || | |
3193 | (rc->end != 0 && rc->end == rc->pos)) | |
5cd21917 GN |
3194 | ctxt->restart = false; |
3195 | } | |
9de41573 GN |
3196 | /* |
3197 | * reset read cache here in case string instruction is restared | |
3198 | * without decoding | |
3199 | */ | |
3200 | ctxt->decode.mem_read.end = 0; | |
95c55886 | 3201 | ctxt->eip = c->eip; |
018a98db AK |
3202 | |
3203 | done: | |
cb404fe0 | 3204 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3205 | |
3206 | twobyte_insn: | |
e4e03ded | 3207 | switch (c->b) { |
6aa8b732 | 3208 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3209 | switch (c->modrm_reg) { |
6aa8b732 AK |
3210 | u16 size; |
3211 | unsigned long address; | |
3212 | ||
aca7f966 | 3213 | case 0: /* vmcall */ |
e4e03ded | 3214 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3215 | goto cannot_emulate; |
3216 | ||
7aa81cc0 | 3217 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3218 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3219 | goto done; |
3220 | ||
33e3885d | 3221 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3222 | c->eip = ctxt->eip; |
16286d08 AK |
3223 | /* Disable writeback. */ |
3224 | c->dst.type = OP_NONE; | |
aca7f966 | 3225 | break; |
6aa8b732 | 3226 | case 2: /* lgdt */ |
1a6440ae | 3227 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3228 | &size, &address, c->op_bytes); |
1b30eaa8 | 3229 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3230 | goto done; |
3231 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3232 | /* Disable writeback. */ |
3233 | c->dst.type = OP_NONE; | |
6aa8b732 | 3234 | break; |
aca7f966 | 3235 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3236 | if (c->modrm_mod == 3) { |
3237 | switch (c->modrm_rm) { | |
3238 | case 1: | |
3239 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3240 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3241 | goto done; |
3242 | break; | |
3243 | default: | |
3244 | goto cannot_emulate; | |
3245 | } | |
aca7f966 | 3246 | } else { |
1a6440ae | 3247 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3248 | &size, &address, |
e4e03ded | 3249 | c->op_bytes); |
1b30eaa8 | 3250 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3251 | goto done; |
3252 | realmode_lidt(ctxt->vcpu, size, address); | |
3253 | } | |
16286d08 AK |
3254 | /* Disable writeback. */ |
3255 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3256 | break; |
3257 | case 4: /* smsw */ | |
16286d08 | 3258 | c->dst.bytes = 2; |
52a46617 | 3259 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3260 | break; |
3261 | case 6: /* lmsw */ | |
9928ff60 | 3262 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3263 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3264 | c->dst.type = OP_NONE; |
6aa8b732 | 3265 | break; |
6e1e5ffe | 3266 | case 5: /* not defined */ |
54b8486f | 3267 | emulate_ud(ctxt); |
6e1e5ffe | 3268 | goto done; |
6aa8b732 | 3269 | case 7: /* invlpg*/ |
1f6f0580 | 3270 | emulate_invlpg(ctxt->vcpu, c->src.addr.mem); |
16286d08 AK |
3271 | /* Disable writeback. */ |
3272 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3273 | break; |
3274 | default: | |
3275 | goto cannot_emulate; | |
3276 | } | |
3277 | break; | |
e99f0507 | 3278 | case 0x05: /* syscall */ |
3fb1b5db | 3279 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3280 | if (rc != X86EMUL_CONTINUE) |
3281 | goto done; | |
e66bb2cc AP |
3282 | else |
3283 | goto writeback; | |
e99f0507 | 3284 | break; |
018a98db AK |
3285 | case 0x06: |
3286 | emulate_clts(ctxt->vcpu); | |
018a98db | 3287 | break; |
018a98db | 3288 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3289 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3290 | break; |
3291 | case 0x08: /* invd */ | |
018a98db AK |
3292 | case 0x0d: /* GrpP (prefetch) */ |
3293 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3294 | break; |
3295 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3296 | switch (c->modrm_reg) { |
3297 | case 1: | |
3298 | case 5 ... 7: | |
3299 | case 9 ... 15: | |
54b8486f | 3300 | emulate_ud(ctxt); |
6aebfa6e GN |
3301 | goto done; |
3302 | } | |
1a0c7d44 | 3303 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3304 | break; |
6aa8b732 | 3305 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3306 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3307 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3308 | emulate_ud(ctxt); |
1e470be5 GN |
3309 | goto done; |
3310 | } | |
b27f3856 | 3311 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3312 | break; |
018a98db | 3313 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3314 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3315 | emulate_gp(ctxt, 0); |
0f12244f GN |
3316 | goto done; |
3317 | } | |
018a98db AK |
3318 | c->dst.type = OP_NONE; |
3319 | break; | |
6aa8b732 | 3320 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3321 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3322 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3323 | emulate_ud(ctxt); |
1e470be5 GN |
3324 | goto done; |
3325 | } | |
35aa5375 | 3326 | |
b27f3856 | 3327 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3328 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3329 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3330 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3331 | emulate_gp(ctxt, 0); |
338dbc97 GN |
3332 | goto done; |
3333 | } | |
3334 | ||
a01af5ec | 3335 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3336 | break; |
018a98db AK |
3337 | case 0x30: |
3338 | /* wrmsr */ | |
3339 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3340 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3341 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3342 | emulate_gp(ctxt, 0); |
fd525365 | 3343 | goto done; |
018a98db AK |
3344 | } |
3345 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3346 | break; |
3347 | case 0x32: | |
3348 | /* rdmsr */ | |
3fb1b5db | 3349 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3350 | emulate_gp(ctxt, 0); |
fd525365 | 3351 | goto done; |
018a98db AK |
3352 | } else { |
3353 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3354 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3355 | } | |
3356 | rc = X86EMUL_CONTINUE; | |
018a98db | 3357 | break; |
e99f0507 | 3358 | case 0x34: /* sysenter */ |
3fb1b5db | 3359 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3360 | if (rc != X86EMUL_CONTINUE) |
3361 | goto done; | |
8c604352 AP |
3362 | else |
3363 | goto writeback; | |
e99f0507 AP |
3364 | break; |
3365 | case 0x35: /* sysexit */ | |
3fb1b5db | 3366 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3367 | if (rc != X86EMUL_CONTINUE) |
3368 | goto done; | |
4668f050 AP |
3369 | else |
3370 | goto writeback; | |
e99f0507 | 3371 | break; |
6aa8b732 | 3372 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3373 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3374 | if (!test_cc(c->b, ctxt->eflags)) |
3375 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3376 | break; |
b2833e3c | 3377 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3378 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3379 | jmp_rel(c, c->src.val); |
018a98db | 3380 | break; |
0934ac9d | 3381 | case 0xa0: /* push fs */ |
79168fd1 | 3382 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3383 | break; |
3384 | case 0xa1: /* pop fs */ | |
3385 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3386 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3387 | goto done; |
3388 | break; | |
7de75248 NK |
3389 | case 0xa3: |
3390 | bt: /* bt */ | |
e4f8e039 | 3391 | c->dst.type = OP_NONE; |
e4e03ded LV |
3392 | /* only subword offset */ |
3393 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3394 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3395 | break; |
9bf8ea42 GT |
3396 | case 0xa4: /* shld imm8, r, r/m */ |
3397 | case 0xa5: /* shld cl, r, r/m */ | |
3398 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3399 | break; | |
0934ac9d | 3400 | case 0xa8: /* push gs */ |
79168fd1 | 3401 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3402 | break; |
3403 | case 0xa9: /* pop gs */ | |
3404 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3405 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3406 | goto done; |
3407 | break; | |
7de75248 NK |
3408 | case 0xab: |
3409 | bts: /* bts */ | |
e4e03ded LV |
3410 | /* only subword offset */ |
3411 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3412 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3413 | break; |
9bf8ea42 GT |
3414 | case 0xac: /* shrd imm8, r, r/m */ |
3415 | case 0xad: /* shrd cl, r, r/m */ | |
3416 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3417 | break; | |
2a7c5b8b GC |
3418 | case 0xae: /* clflush */ |
3419 | break; | |
6aa8b732 AK |
3420 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3421 | /* | |
3422 | * Save real source value, then compare EAX against | |
3423 | * destination. | |
3424 | */ | |
e4e03ded LV |
3425 | c->src.orig_val = c->src.val; |
3426 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3427 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3428 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3429 | /* Success: write back to memory. */ |
e4e03ded | 3430 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3431 | } else { |
3432 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3433 | c->dst.type = OP_REG; |
1a6440ae | 3434 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3435 | } |
3436 | break; | |
6aa8b732 AK |
3437 | case 0xb3: |
3438 | btr: /* btr */ | |
e4e03ded LV |
3439 | /* only subword offset */ |
3440 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3441 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3442 | break; |
6aa8b732 | 3443 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3444 | c->dst.bytes = c->op_bytes; |
3445 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3446 | : (u16) c->src.val; | |
6aa8b732 | 3447 | break; |
6aa8b732 | 3448 | case 0xba: /* Grp8 */ |
e4e03ded | 3449 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3450 | case 0: |
3451 | goto bt; | |
3452 | case 1: | |
3453 | goto bts; | |
3454 | case 2: | |
3455 | goto btr; | |
3456 | case 3: | |
3457 | goto btc; | |
3458 | } | |
3459 | break; | |
7de75248 NK |
3460 | case 0xbb: |
3461 | btc: /* btc */ | |
e4e03ded LV |
3462 | /* only subword offset */ |
3463 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3464 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3465 | break; |
6aa8b732 | 3466 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3467 | c->dst.bytes = c->op_bytes; |
3468 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3469 | (s16) c->src.val; | |
6aa8b732 | 3470 | break; |
a012e65a | 3471 | case 0xc3: /* movnti */ |
e4e03ded LV |
3472 | c->dst.bytes = c->op_bytes; |
3473 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3474 | (u64) c->src.val; | |
a012e65a | 3475 | break; |
6aa8b732 | 3476 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3477 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3478 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3479 | goto done; |
3480 | break; | |
91269b8f AK |
3481 | default: |
3482 | goto cannot_emulate; | |
6aa8b732 AK |
3483 | } |
3484 | goto writeback; | |
3485 | ||
3486 | cannot_emulate: | |
e4e03ded | 3487 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3488 | return -1; |
3489 | } |