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KVM: x86 emulator: use aligned variants of SSE register ops
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
dd856efa
AK		 205static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
206{
207 if (!(ctxt->regs_valid & (1 << nr))) {
208 ctxt->regs_valid |= 1 << nr;
209 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
210 }
211 return ctxt->_regs[nr];
212}
213
214static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
215{
216 ctxt->regs_valid |= 1 << nr;
217 ctxt->regs_dirty |= 1 << nr;
218 return &ctxt->_regs[nr];
219}
220
221static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
222{
223 reg_read(ctxt, nr);
224 return reg_write(ctxt, nr);
225}
226
227static void writeback_registers(struct x86_emulate_ctxt *ctxt)
228{
229 unsigned reg;
230
231 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
232 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
233}
234
235static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
236{
237 ctxt->regs_dirty = 0;
238 ctxt->regs_valid = 0;
239}
240
6aa8b732
AK		 241/*
242 * Instruction emulation:
243 * Most instructions are emulated directly via a fragment of inline assembly
244 * code. This allows us to save/restore EFLAGS and thus very easily pick up
245 * any modified flags.
246 */
247
05b3e0c2 248#if defined(CONFIG_X86_64)
6aa8b732
AK		 249#define _LO32 "k" /* force 32-bit operand */
250#define _STK "%%rsp" /* stack pointer */
251#elif defined(__i386__)
252#define _LO32 "" /* force 32-bit operand */
253#define _STK "%%esp" /* stack pointer */
254#endif
255
256/*
257 * These EFLAGS bits are restored from saved value during emulation, and
258 * any changes are written back to the saved value after emulation.
259 */
260#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
261
262/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 263#define _PRE_EFLAGS(_sav, _msk, _tmp) \
264 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
265 "movl %"_sav",%"_LO32 _tmp"; " \
266 "push %"_tmp"; " \
267 "push %"_tmp"; " \
268 "movl %"_msk",%"_LO32 _tmp"; " \
269 "andl %"_LO32 _tmp",("_STK"); " \
270 "pushf; " \
271 "notl %"_LO32 _tmp"; " \
272 "andl %"_LO32 _tmp",("_STK"); " \
273 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
274 "pop %"_tmp"; " \
275 "orl %"_LO32 _tmp",("_STK"); " \
276 "popf; " \
277 "pop %"_sav"; "
6aa8b732
AK		 278
279/* After executing instruction: write-back necessary bits in EFLAGS. */
280#define _POST_EFLAGS(_sav, _msk, _tmp) \
281 /* _sav |= EFLAGS & _msk; */ \
282 "pushf; " \
283 "pop %"_tmp"; " \
284 "andl %"_msk",%"_LO32 _tmp"; " \
285 "orl %"_LO32 _tmp",%"_sav"; "
286
dda96d8f
AK		 287#ifdef CONFIG_X86_64
288#define ON64(x) x
289#else
290#define ON64(x)
291#endif
292
a31b9cea 293#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 294 do { \
295 __asm__ __volatile__ ( \
296 _PRE_EFLAGS("0", "4", "2") \
297 _op _suffix " %"_x"3,%1; " \
298 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 299 : "=m" ((ctxt)->eflags), \
300 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 301 "=&r" (_tmp) \
a31b9cea 302 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 303 } while (0)
6b7ad61f
AK		 304
305
6aa8b732 306/* Raw emulation: instruction has two explicit operands. */
a31b9cea 307#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 308 do { \
309 unsigned long _tmp; \
310 \
a31b9cea 311 switch ((ctxt)->dst.bytes) { \
6b7ad61f 312 case 2: \
a31b9cea 313 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 314 break; \
315 case 4: \
a31b9cea 316 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 317 break; \
318 case 8: \
a31b9cea 319 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 320 break; \
321 } \
6aa8b732
AK		 322 } while (0)
323
a31b9cea 324#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 325 do { \
6b7ad61f 326 unsigned long _tmp; \
a31b9cea 327 switch ((ctxt)->dst.bytes) { \
6aa8b732 328 case 1: \
a31b9cea 329 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 330 break; \
331 default: \
a31b9cea 332 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 333 _wx, _wy, _lx, _ly, _qx, _qy); \
334 break; \
335 } \
336 } while (0)
337
338/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 339#define emulate_2op_SrcB(ctxt, _op) \
340 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 341
342/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 343#define emulate_2op_SrcV(ctxt, _op) \
344 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 345
346/* Source operand is word, long or quad sized. */
a31b9cea
AK		 347#define emulate_2op_SrcV_nobyte(ctxt, _op) \
348 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 349
d175226a 350/* Instruction has three operands and one operand is stored in ECX register */
29053a60 351#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 352 do { \
353 unsigned long _tmp; \
761441b9
AK		 354 _type _clv = (ctxt)->src2.val; \
355 _type _srcv = (ctxt)->src.val; \
356 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 357 \
358 __asm__ __volatile__ ( \
359 _PRE_EFLAGS("0", "5", "2") \
360 _op _suffix " %4,%1 \n" \
361 _POST_EFLAGS("0", "5", "2") \
761441b9 362 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 363 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
364 ); \
365 \
761441b9
AK		 366 (ctxt)->src2.val = (unsigned long) _clv; \
367 (ctxt)->src2.val = (unsigned long) _srcv; \
368 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 369 } while (0)
370
761441b9 371#define emulate_2op_cl(ctxt, _op) \
7295261c 372 do { \
761441b9 373 switch ((ctxt)->dst.bytes) { \
7295261c 374 case 2: \
29053a60 375 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 376 break; \
377 case 4: \
29053a60 378 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 379 break; \
380 case 8: \
29053a60 381 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 382 break; \
383 } \
d175226a
GT		 384 } while (0)
385
d1eef45d 386#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 387 do { \
388 unsigned long _tmp; \
389 \
dda96d8f
AK		 390 __asm__ __volatile__ ( \
391 _PRE_EFLAGS("0", "3", "2") \
392 _op _suffix " %1; " \
393 _POST_EFLAGS("0", "3", "2") \
d1eef45d 394 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 395 "=&r" (_tmp) \
396 : "i" (EFLAGS_MASK)); \
397 } while (0)
398
399/* Instruction has only one explicit operand (no source operand). */
d1eef45d 400#define emulate_1op(ctxt, _op) \
dda96d8f 401 do { \
d1eef45d
AK		 402 switch ((ctxt)->dst.bytes) { \
403 case 1: __emulate_1op(ctxt, _op, "b"); break; \
404 case 2: __emulate_1op(ctxt, _op, "w"); break; \
405 case 4: __emulate_1op(ctxt, _op, "l"); break; \
406 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 407 } \
408 } while (0)
409
e8f2b1d6 410#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 411 do { \
412 unsigned long _tmp; \
dd856efa
AK		 413 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
414 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 415 \
416 __asm__ __volatile__ ( \
417 _PRE_EFLAGS("0", "5", "1") \
418 "1: \n\t" \
419 _op _suffix " %6; " \
420 "2: \n\t" \
421 _POST_EFLAGS("0", "5", "1") \
422 ".pushsection .fixup,\"ax\" \n\t" \
423 "3: movb $1, %4 \n\t" \
424 "jmp 2b \n\t" \
425 ".popsection \n\t" \
426 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 427 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
428 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
429 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
430 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 431 } while (0)
432
3f9f53b0 433/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 434#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 435 do { \
e8f2b1d6 436 switch((ctxt)->src.bytes) { \
7295261c 437 case 1: \
e8f2b1d6 438 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 439 break; \
440 case 2: \
e8f2b1d6 441 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 442 break; \
443 case 4: \
e8f2b1d6 444 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 445 break; \
446 case 8: ON64( \
e8f2b1d6 447 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 448 break; \
449 } \
450 } while (0)
451
8a76d7f2
JR		 452static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
453 enum x86_intercept intercept,
454 enum x86_intercept_stage stage)
455{
456 struct x86_instruction_info info = {
457 .intercept = intercept,
9dac77fa
AK		 458 .rep_prefix = ctxt->rep_prefix,
459 .modrm_mod = ctxt->modrm_mod,
460 .modrm_reg = ctxt->modrm_reg,
461 .modrm_rm = ctxt->modrm_rm,
462 .src_val = ctxt->src.val64,
463 .src_bytes = ctxt->src.bytes,
464 .dst_bytes = ctxt->dst.bytes,
465 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 466 .next_rip = ctxt->eip,
467 };
468
2953538e 469 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 470}
471
f47cfa31
AK		 472static void assign_masked(ulong *dest, ulong src, ulong mask)
473{
474 *dest = (*dest & ~mask) | (src & mask);
475}
476
9dac77fa 477static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 478{
9dac77fa 479 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 480}
481
f47cfa31
AK		 482static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
483{
484 u16 sel;
485 struct desc_struct ss;
486
487 if (ctxt->mode == X86EMUL_MODE_PROT64)
488 return ~0UL;
489 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
490 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
491}
492
612e89f0
AK		 493static int stack_size(struct x86_emulate_ctxt *ctxt)
494{
495 return (__fls(stack_mask(ctxt)) + 1) >> 3;
496}
497
6aa8b732 498/* Access/update address held in a register, based on addressing mode. */
e4706772 499static inline unsigned long
9dac77fa 500address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 501{
9dac77fa 502 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 503 return reg;
504 else
9dac77fa 505 return reg & ad_mask(ctxt);
e4706772
HH		 506}
507
508static inline unsigned long
9dac77fa 509register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 510{
9dac77fa 511 return address_mask(ctxt, reg);
e4706772
HH		 512}
513
5ad105e5
AK		 514static void masked_increment(ulong *reg, ulong mask, int inc)
515{
516 assign_masked(reg, *reg + inc, mask);
517}
518
7a957275 519static inline void
9dac77fa 520register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 521{
5ad105e5
AK		 522 ulong mask;
523
9dac77fa 524 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 525 mask = ~0UL;
7a957275 526 else
5ad105e5
AK		 527 mask = ad_mask(ctxt);
528 masked_increment(reg, mask, inc);
529}
530
531static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
532{
dd856efa 533 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 534}
6aa8b732 535
9dac77fa 536static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 537{
9dac77fa 538 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 539}
098c937b 540
56697687
AK		 541static u32 desc_limit_scaled(struct desc_struct *desc)
542{
543 u32 limit = get_desc_limit(desc);
544
545 return desc->g ? (limit << 12) | 0xfff : limit;
546}
547
9dac77fa 548static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 549{
9dac77fa
AK		 550 ctxt->has_seg_override = true;
551 ctxt->seg_override = seg;
7a5b56df
AK		 552}
553
7b105ca2 554static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 555{
556 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
557 return 0;
558
7b105ca2 559 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 560}
561
9dac77fa 562static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 563{
9dac77fa 564 if (!ctxt->has_seg_override)
7a5b56df
AK		 565 return 0;
566
9dac77fa 567 return ctxt->seg_override;
7a5b56df
AK		 568}
569
35d3d4a1
AK		 570static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
571 u32 error, bool valid)
54b8486f 572{
da9cb575
AK		 573 ctxt->exception.vector = vec;
574 ctxt->exception.error_code = error;
575 ctxt->exception.error_code_valid = valid;
35d3d4a1 576 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 577}
578
3b88e41a
JR		 579static int emulate_db(struct x86_emulate_ctxt *ctxt)
580{
581 return emulate_exception(ctxt, DB_VECTOR, 0, false);
582}
583
35d3d4a1 584static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 585{
35d3d4a1 586 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 587}
588
618ff15d
AK		 589static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
590{
591 return emulate_exception(ctxt, SS_VECTOR, err, true);
592}
593
35d3d4a1 594static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 595{
35d3d4a1 596 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 597}
598
35d3d4a1 599static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 600{
35d3d4a1 601 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 602}
603
34d1f490
AK		 604static int emulate_de(struct x86_emulate_ctxt *ctxt)
605{
35d3d4a1 606 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 607}
608
1253791d
AK		 609static int emulate_nm(struct x86_emulate_ctxt *ctxt)
610{
611 return emulate_exception(ctxt, NM_VECTOR, 0, false);
612}
613
1aa36616
AK		 614static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
615{
616 u16 selector;
617 struct desc_struct desc;
618
619 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
620 return selector;
621}
622
623static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
624 unsigned seg)
625{
626 u16 dummy;
627 u32 base3;
628 struct desc_struct desc;
629
630 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
631 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
632}
633
1c11b376
AK		 634/*
635 * x86 defines three classes of vector instructions: explicitly
636 * aligned, explicitly unaligned, and the rest, which change behaviour
637 * depending on whether they're AVX encoded or not.
638 *
639 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
640 * subject to the same check.
641 */
642static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
643{
644 if (likely(size < 16))
645 return false;
646
647 if (ctxt->d & Aligned)
648 return true;
649 else if (ctxt->d & Unaligned)
650 return false;
651 else if (ctxt->d & Avx)
652 return false;
653 else
654 return true;
655}
656
3d9b938e 657static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 658 struct segmented_address addr,
3d9b938e 659 unsigned size, bool write, bool fetch,
52fd8b44
AK		 660 ulong *linear)
661{
618ff15d
AK		 662 struct desc_struct desc;
663 bool usable;
52fd8b44 664 ulong la;
618ff15d 665 u32 lim;
1aa36616 666 u16 sel;
618ff15d 667 unsigned cpl, rpl;
52fd8b44 668
7b105ca2 669 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 670 switch (ctxt->mode) {
618ff15d
AK		 671 case X86EMUL_MODE_PROT64:
672 if (((signed long)la << 16) >> 16 != la)
673 return emulate_gp(ctxt, 0);
674 break;
675 default:
1aa36616
AK		 676 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
677 addr.seg);
618ff15d
AK		 678 if (!usable)
679 goto bad;
680 /* code segment or read-only data segment */
681 if (((desc.type & 8) || !(desc.type & 2)) && write)
682 goto bad;
683 /* unreadable code segment */
3d9b938e 684 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 685 goto bad;
686 lim = desc_limit_scaled(&desc);
687 if ((desc.type & 8) || !(desc.type & 4)) {
688 /* expand-up segment */
689 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
690 goto bad;
691 } else {
fc058680 692 /* expand-down segment */
618ff15d
AK		 693 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
694 goto bad;
695 lim = desc.d ? 0xffffffff : 0xffff;
696 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
697 goto bad;
698 }
717746e3 699 cpl = ctxt->ops->cpl(ctxt);
a5625189
AK		 700 if (ctxt->mode == X86EMUL_MODE_REAL)
701 rpl = 0;
702 else
703 rpl = sel & 3;
618ff15d
AK		 704 cpl = max(cpl, rpl);
705 if (!(desc.type & 8)) {
706 /* data segment */
707 if (cpl > desc.dpl)
708 goto bad;
709 } else if ((desc.type & 8) && !(desc.type & 4)) {
710 /* nonconforming code segment */
711 if (cpl != desc.dpl)
712 goto bad;
713 } else if ((desc.type & 8) && (desc.type & 4)) {
714 /* conforming code segment */
715 if (cpl < desc.dpl)
716 goto bad;
717 }
718 break;
719 }
9dac77fa 720 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 721 la &= (u32)-1;
1c11b376
AK		 722 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
723 return emulate_gp(ctxt, 0);
52fd8b44
AK		 724 *linear = la;
725 return X86EMUL_CONTINUE;
618ff15d
AK		 726bad:
727 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 728 return emulate_ss(ctxt, sel);
618ff15d 729 else
0afbe2f8 730 return emulate_gp(ctxt, sel);
52fd8b44
AK		 731}
732
3d9b938e
NE		 733static int linearize(struct x86_emulate_ctxt *ctxt,
734 struct segmented_address addr,
735 unsigned size, bool write,
736 ulong *linear)
737{
738 return __linearize(ctxt, addr, size, write, false, linear);
739}
740
741
3ca3ac4d
AK		 742static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
743 struct segmented_address addr,
744 void *data,
745 unsigned size)
746{
9fa088f4
AK		 747 int rc;
748 ulong linear;
749
83b8795a 750 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 751 if (rc != X86EMUL_CONTINUE)
752 return rc;
0f65dd70 753 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 754}
755
807941b1
TY		 756/*
757 * Fetch the next byte of the instruction being emulated which is pointed to
758 * by ctxt->_eip, then increment ctxt->_eip.
759 *
760 * Also prefetch the remaining bytes of the instruction without crossing page
761 * boundary if they are not in fetch_cache yet.
762 */
763static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 764{
9dac77fa 765 struct fetch_cache *fc = &ctxt->fetch;
62266869 766 int rc;
2fb53ad8 767 int size, cur_size;
62266869 768
807941b1 769 if (ctxt->_eip == fc->end) {
3d9b938e 770 unsigned long linear;
807941b1
TY		 771 struct segmented_address addr = { .seg = VCPU_SREG_CS,
772 .ea = ctxt->_eip };
2fb53ad8 773 cur_size = fc->end - fc->start;
807941b1
TY		 774 size = min(15UL - cur_size,
775 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 776 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 777 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 778 return rc;
ef5d75cc
TY		 779 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
780 size, &ctxt->exception);
7d88bb48 781 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 782 return rc;
2fb53ad8 783 fc->end += size;
62266869 784 }
807941b1
TY		 785 *dest = fc->data[ctxt->_eip - fc->start];
786 ctxt->_eip++;
3e2815e9 787 return X86EMUL_CONTINUE;
62266869
AK		 788}
789
790static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 791 void *dest, unsigned size)
62266869 792{
3e2815e9 793 int rc;
62266869 794
eb3c79e6 795 /* x86 instructions are limited to 15 bytes. */
7d88bb48 796 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 797 return X86EMUL_UNHANDLEABLE;
62266869 798 while (size--) {
807941b1 799 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 800 if (rc != X86EMUL_CONTINUE)
62266869
AK		 801 return rc;
802 }
3e2815e9 803 return X86EMUL_CONTINUE;
62266869
AK		 804}
805
67cbc90d 806/* Fetch next part of the instruction being emulated. */
e85a1085 807#define insn_fetch(_type, _ctxt) \
67cbc90d 808({ unsigned long _x; \
e85a1085 809 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 810 if (rc != X86EMUL_CONTINUE) \
811 goto done; \
67cbc90d
TY		 812 (_type)_x; \
813})
814
807941b1
TY		 815#define insn_fetch_arr(_arr, _size, _ctxt) \
816({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 817 if (rc != X86EMUL_CONTINUE) \
818 goto done; \
67cbc90d
TY		 819})
820
1e3c5cb0
RR		 821/*
822 * Given the 'reg' portion of a ModRM byte, and a register block, return a
823 * pointer into the block that addresses the relevant register.
824 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
825 */
dd856efa 826static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 827 int highbyte_regs)
6aa8b732
AK		 828{
829 void *p;
830
6aa8b732 831 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 832 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
833 else
834 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 835 return p;
836}
837
838static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 839 struct segmented_address addr,
6aa8b732
AK		 840 u16 *size, unsigned long *address, int op_bytes)
841{
842 int rc;
843
844 if (op_bytes == 2)
845 op_bytes = 3;
846 *address = 0;
3ca3ac4d 847 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 848 if (rc != X86EMUL_CONTINUE)
6aa8b732 849 return rc;
30b31ab6 850 addr.ea += 2;
3ca3ac4d 851 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 852 return rc;
853}
854
bbe9abbd
NK		 855static int test_cc(unsigned int condition, unsigned int flags)
856{
857 int rc = 0;
858
859 switch ((condition & 15) >> 1) {
860 case 0: /* o */
861 rc |= (flags & EFLG_OF);
862 break;
863 case 1: /* b/c/nae */
864 rc |= (flags & EFLG_CF);
865 break;
866 case 2: /* z/e */
867 rc |= (flags & EFLG_ZF);
868 break;
869 case 3: /* be/na */
870 rc |= (flags & (EFLG_CF|EFLG_ZF));
871 break;
872 case 4: /* s */
873 rc |= (flags & EFLG_SF);
874 break;
875 case 5: /* p/pe */
876 rc |= (flags & EFLG_PF);
877 break;
878 case 7: /* le/ng */
879 rc |= (flags & EFLG_ZF);
880 /* fall through */
881 case 6: /* l/nge */
882 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
883 break;
884 }
885
886 /* Odd condition identifiers (lsb == 1) have inverted sense. */
887 return (!!rc ^ (condition & 1));
888}
889
91ff3cb4
AK		 890static void fetch_register_operand(struct operand *op)
891{
892 switch (op->bytes) {
893 case 1:
894 op->val = *(u8 *)op->addr.reg;
895 break;
896 case 2:
897 op->val = *(u16 *)op->addr.reg;
898 break;
899 case 4:
900 op->val = *(u32 *)op->addr.reg;
901 break;
902 case 8:
903 op->val = *(u64 *)op->addr.reg;
904 break;
905 }
906}
907
1253791d
AK		 908static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
909{
910 ctxt->ops->get_fpu(ctxt);
911 switch (reg) {
89a87c67
MK		 912 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
913 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
914 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
915 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
916 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
917 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
918 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
919 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 920#ifdef CONFIG_X86_64
89a87c67
MK		 921 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
922 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
923 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
924 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
925 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
926 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
927 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
928 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 929#endif
930 default: BUG();
931 }
932 ctxt->ops->put_fpu(ctxt);
933}
934
935static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
936 int reg)
937{
938 ctxt->ops->get_fpu(ctxt);
939 switch (reg) {
89a87c67
MK		 940 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
941 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
942 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
943 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
944 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
945 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
946 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
947 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 948#ifdef CONFIG_X86_64
89a87c67
MK		 949 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
950 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
951 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
952 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
953 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
954 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
955 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
956 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 957#endif
958 default: BUG();
959 }
960 ctxt->ops->put_fpu(ctxt);
961}
962
cbe2c9d3
AK		 963static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
964{
965 ctxt->ops->get_fpu(ctxt);
966 switch (reg) {
967 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
968 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
969 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
970 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
971 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
972 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
973 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
974 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
975 default: BUG();
976 }
977 ctxt->ops->put_fpu(ctxt);
978}
979
980static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
981{
982 ctxt->ops->get_fpu(ctxt);
983 switch (reg) {
984 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
985 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
986 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
987 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
988 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
989 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
990 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
991 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
992 default: BUG();
993 }
994 ctxt->ops->put_fpu(ctxt);
995}
996
1253791d 997static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 998 struct operand *op)
3c118e24 999{
9dac77fa
AK		 1000 unsigned reg = ctxt->modrm_reg;
1001 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1002
9dac77fa
AK		 1003 if (!(ctxt->d & ModRM))
1004 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1005
9dac77fa 1006 if (ctxt->d & Sse) {
1253791d
AK		 1007 op->type = OP_XMM;
1008 op->bytes = 16;
1009 op->addr.xmm = reg;
1010 read_sse_reg(ctxt, &op->vec_val, reg);
1011 return;
1012 }
cbe2c9d3
AK		 1013 if (ctxt->d & Mmx) {
1014 reg &= 7;
1015 op->type = OP_MM;
1016 op->bytes = 8;
1017 op->addr.mm = reg;
1018 return;
1019 }
1253791d 1020
3c118e24 1021 op->type = OP_REG;
2adb5ad9 1022 if (ctxt->d & ByteOp) {
dd856efa 1023 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1024 op->bytes = 1;
1025 } else {
dd856efa 1026 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1027 op->bytes = ctxt->op_bytes;
3c118e24 1028 }
91ff3cb4 1029 fetch_register_operand(op);
3c118e24
AK		 1030 op->orig_val = op->val;
1031}
1032
a6e3407b
AK		 1033static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1034{
1035 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1036 ctxt->modrm_seg = VCPU_SREG_SS;
1037}
1038
1c73ef66 1039static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1040 struct operand *op)
1c73ef66 1041{
1c73ef66 1042 u8 sib;
f5b4edcd 1043 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1044 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1045 ulong modrm_ea = 0;
1c73ef66 1046
9dac77fa
AK		 1047 if (ctxt->rex_prefix) {
1048 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1049 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1050 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1051 }
1052
9dac77fa
AK		 1053 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1054 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1055 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1056 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1057
9dac77fa 1058 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1059 op->type = OP_REG;
9dac77fa 1060 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1061 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1062 if (ctxt->d & Sse) {
1253791d
AK		 1063 op->type = OP_XMM;
1064 op->bytes = 16;
9dac77fa
AK		 1065 op->addr.xmm = ctxt->modrm_rm;
1066 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1067 return rc;
1068 }
cbe2c9d3
AK		 1069 if (ctxt->d & Mmx) {
1070 op->type = OP_MM;
1071 op->bytes = 8;
1072 op->addr.xmm = ctxt->modrm_rm & 7;
1073 return rc;
1074 }
2dbd0dd7 1075 fetch_register_operand(op);
1c73ef66
AK		 1076 return rc;
1077 }
1078
2dbd0dd7
AK		 1079 op->type = OP_MEM;
1080
9dac77fa 1081 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1082 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1083 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1084 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1085 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1086
1087 /* 16-bit ModR/M decode. */
9dac77fa 1088 switch (ctxt->modrm_mod) {
1c73ef66 1089 case 0:
9dac77fa 1090 if (ctxt->modrm_rm == 6)
e85a1085 1091 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1092 break;
1093 case 1:
e85a1085 1094 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1095 break;
1096 case 2:
e85a1085 1097 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1098 break;
1099 }
9dac77fa 1100 switch (ctxt->modrm_rm) {
1c73ef66 1101 case 0:
2dbd0dd7 1102 modrm_ea += bx + si;
1c73ef66
AK		 1103 break;
1104 case 1:
2dbd0dd7 1105 modrm_ea += bx + di;
1c73ef66
AK		 1106 break;
1107 case 2:
2dbd0dd7 1108 modrm_ea += bp + si;
1c73ef66
AK		 1109 break;
1110 case 3:
2dbd0dd7 1111 modrm_ea += bp + di;
1c73ef66
AK		 1112 break;
1113 case 4:
2dbd0dd7 1114 modrm_ea += si;
1c73ef66
AK		 1115 break;
1116 case 5:
2dbd0dd7 1117 modrm_ea += di;
1c73ef66
AK		 1118 break;
1119 case 6:
9dac77fa 1120 if (ctxt->modrm_mod != 0)
2dbd0dd7 1121 modrm_ea += bp;
1c73ef66
AK		 1122 break;
1123 case 7:
2dbd0dd7 1124 modrm_ea += bx;
1c73ef66
AK		 1125 break;
1126 }
9dac77fa
AK		 1127 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1128 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1129 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1130 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1131 } else {
1132 /* 32/64-bit ModR/M decode. */
9dac77fa 1133 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1134 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1135 index_reg |= (sib >> 3) & 7;
1136 base_reg |= sib & 7;
1137 scale = sib >> 6;
1138
9dac77fa 1139 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1140 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1141 else {
dd856efa 1142 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1143 adjust_modrm_seg(ctxt, base_reg);
1144 }
dc71d0f1 1145 if (index_reg != 4)
dd856efa 1146 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1147 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1148 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1149 ctxt->rip_relative = 1;
a6e3407b
AK		 1150 } else {
1151 base_reg = ctxt->modrm_rm;
dd856efa 1152 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1153 adjust_modrm_seg(ctxt, base_reg);
1154 }
9dac77fa 1155 switch (ctxt->modrm_mod) {
1c73ef66 1156 case 0:
9dac77fa 1157 if (ctxt->modrm_rm == 5)
e85a1085 1158 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1159 break;
1160 case 1:
e85a1085 1161 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1162 break;
1163 case 2:
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1165 break;
1166 }
1167 }
90de84f5 1168 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1169done:
1170 return rc;
1171}
1172
1173static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1174 struct operand *op)
1c73ef66 1175{
3e2815e9 1176 int rc = X86EMUL_CONTINUE;
1c73ef66 1177
2dbd0dd7 1178 op->type = OP_MEM;
9dac77fa 1179 switch (ctxt->ad_bytes) {
1c73ef66 1180 case 2:
e85a1085 1181 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1182 break;
1183 case 4:
e85a1085 1184 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1185 break;
1186 case 8:
e85a1085 1187 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1188 break;
1189 }
1190done:
1191 return rc;
1192}
1193
9dac77fa 1194static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1195{
7129eeca 1196 long sv = 0, mask;
35c843c4 1197
9dac77fa
AK		 1198 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1199 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1200
9dac77fa
AK		 1201 if (ctxt->src.bytes == 2)
1202 sv = (s16)ctxt->src.val & (s16)mask;
1203 else if (ctxt->src.bytes == 4)
1204 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1205
9dac77fa 1206 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1207 }
ba7ff2b7
WY		 1208
1209 /* only subword offset */
9dac77fa 1210 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1211}
1212
dde7e6d1 1213static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1214 unsigned long addr, void *dest, unsigned size)
6aa8b732 1215{
dde7e6d1 1216 int rc;
9dac77fa 1217 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1218
f23b070e
XG		 1219 if (mc->pos < mc->end)
1220 goto read_cached;
6aa8b732 1221
f23b070e
XG		 1222 WARN_ON((mc->end + size) >= sizeof(mc->data));
1223
1224 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1225 &ctxt->exception);
1226 if (rc != X86EMUL_CONTINUE)
1227 return rc;
1228
1229 mc->end += size;
1230
1231read_cached:
1232 memcpy(dest, mc->data + mc->pos, size);
1233 mc->pos += size;
dde7e6d1
AK		 1234 return X86EMUL_CONTINUE;
1235}
6aa8b732 1236
3ca3ac4d
AK		 1237static int segmented_read(struct x86_emulate_ctxt *ctxt,
1238 struct segmented_address addr,
1239 void *data,
1240 unsigned size)
1241{
9fa088f4
AK		 1242 int rc;
1243 ulong linear;
1244
83b8795a 1245 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1246 if (rc != X86EMUL_CONTINUE)
1247 return rc;
7b105ca2 1248 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1249}
1250
1251static int segmented_write(struct x86_emulate_ctxt *ctxt,
1252 struct segmented_address addr,
1253 const void *data,
1254 unsigned size)
1255{
9fa088f4
AK		 1256 int rc;
1257 ulong linear;
1258
83b8795a 1259 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1260 if (rc != X86EMUL_CONTINUE)
1261 return rc;
0f65dd70
AK		 1262 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1263 &ctxt->exception);
3ca3ac4d
AK		 1264}
1265
1266static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1267 struct segmented_address addr,
1268 const void *orig_data, const void *data,
1269 unsigned size)
1270{
9fa088f4
AK		 1271 int rc;
1272 ulong linear;
1273
83b8795a 1274 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
0f65dd70
AK		 1277 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1278 size, &ctxt->exception);
3ca3ac4d
AK		 1279}
1280
dde7e6d1 1281static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1282 unsigned int size, unsigned short port,
1283 void *dest)
1284{
9dac77fa 1285 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1286
dde7e6d1 1287 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1288 unsigned int in_page, n;
9dac77fa 1289 unsigned int count = ctxt->rep_prefix ?
dd856efa 1290 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1291 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1292 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1293 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1294 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1295 count);
1296 if (n == 0)
1297 n = 1;
1298 rc->pos = rc->end = 0;
7b105ca2 1299 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1300 return 0;
1301 rc->end = n * size;
6aa8b732
AK		 1302 }
1303
dde7e6d1
AK		 1304 memcpy(dest, rc->data + rc->pos, size);
1305 rc->pos += size;
1306 return 1;
1307}
6aa8b732 1308
7f3d35fd
KW		 1309static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1310 u16 index, struct desc_struct *desc)
1311{
1312 struct desc_ptr dt;
1313 ulong addr;
1314
1315 ctxt->ops->get_idt(ctxt, &dt);
1316
1317 if (dt.size < index * 8 + 7)
1318 return emulate_gp(ctxt, index << 3 | 0x2);
1319
1320 addr = dt.address + index * 8;
1321 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1322 &ctxt->exception);
1323}
1324
dde7e6d1 1325static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1326 u16 selector, struct desc_ptr *dt)
1327{
7b105ca2
TY		 1328 struct x86_emulate_ops *ops = ctxt->ops;
1329
dde7e6d1
AK		 1330 if (selector & 1 << 2) {
1331 struct desc_struct desc;
1aa36616
AK		 1332 u16 sel;
1333
dde7e6d1 1334 memset (dt, 0, sizeof *dt);
1aa36616 1335 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1336 return;
e09d082c 1337
dde7e6d1
AK		 1338 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1339 dt->address = get_desc_base(&desc);
1340 } else
4bff1e86 1341 ops->get_gdt(ctxt, dt);
dde7e6d1 1342}
120df890 1343
dde7e6d1
AK		 1344/* allowed just for 8 bytes segments */
1345static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1346 u16 selector, struct desc_struct *desc,
1347 ulong *desc_addr_p)
dde7e6d1
AK		 1348{
1349 struct desc_ptr dt;
1350 u16 index = selector >> 3;
dde7e6d1 1351 ulong addr;
120df890 1352
7b105ca2 1353 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1354
35d3d4a1
AK		 1355 if (dt.size < index * 8 + 7)
1356 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1357
e919464b 1358 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1359 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1360 &ctxt->exception);
dde7e6d1 1361}
ef65c889 1362
dde7e6d1
AK		 1363/* allowed just for 8 bytes segments */
1364static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1365 u16 selector, struct desc_struct *desc)
1366{
1367 struct desc_ptr dt;
1368 u16 index = selector >> 3;
dde7e6d1 1369 ulong addr;
6aa8b732 1370
7b105ca2 1371 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1372
35d3d4a1
AK		 1373 if (dt.size < index * 8 + 7)
1374 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1375
dde7e6d1 1376 addr = dt.address + index * 8;
7b105ca2
TY		 1377 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1378 &ctxt->exception);
dde7e6d1 1379}
c7e75a3d 1380
5601d05b 1381/* Does not support long mode */
dde7e6d1 1382static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1383 u16 selector, int seg)
1384{
869be99c 1385 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1386 u8 dpl, rpl, cpl;
1387 unsigned err_vec = GP_VECTOR;
1388 u32 err_code = 0;
1389 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1390 ulong desc_addr;
dde7e6d1 1391 int ret;
03ebebeb 1392 u16 dummy;
69f55cb1 1393
dde7e6d1 1394 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1395
dde7e6d1
AK		 1396 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1397 || ctxt->mode == X86EMUL_MODE_REAL) {
1398 /* set real mode segment descriptor */
03ebebeb 1399 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1400 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1401 goto load;
1402 }
1403
79d5b4c3
AK		 1404 rpl = selector & 3;
1405 cpl = ctxt->ops->cpl(ctxt);
1406
1407 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1408 if ((seg == VCPU_SREG_CS
1409 || (seg == VCPU_SREG_SS
1410 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1411 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1412 && null_selector)
1413 goto exception;
1414
1415 /* TR should be in GDT only */
1416 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1417 goto exception;
1418
1419 if (null_selector) /* for NULL selector skip all following checks */
1420 goto load;
1421
e919464b 1422 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1423 if (ret != X86EMUL_CONTINUE)
1424 return ret;
1425
1426 err_code = selector & 0xfffc;
1427 err_vec = GP_VECTOR;
1428
fc058680 1429 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1430 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1431 goto exception;
1432
1433 if (!seg_desc.p) {
1434 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1435 goto exception;
1436 }
1437
dde7e6d1 1438 dpl = seg_desc.dpl;
dde7e6d1
AK		 1439
1440 switch (seg) {
1441 case VCPU_SREG_SS:
1442 /*
1443 * segment is not a writable data segment or segment
1444 * selector's RPL != CPL or segment selector's RPL != CPL
1445 */
1446 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1447 goto exception;
6aa8b732 1448 break;
dde7e6d1
AK		 1449 case VCPU_SREG_CS:
1450 if (!(seg_desc.type & 8))
1451 goto exception;
1452
1453 if (seg_desc.type & 4) {
1454 /* conforming */
1455 if (dpl > cpl)
1456 goto exception;
1457 } else {
1458 /* nonconforming */
1459 if (rpl > cpl || dpl != cpl)
1460 goto exception;
1461 }
1462 /* CS(RPL) <- CPL */
1463 selector = (selector & 0xfffc) | cpl;
6aa8b732 1464 break;
dde7e6d1
AK		 1465 case VCPU_SREG_TR:
1466 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1467 goto exception;
869be99c
AK		 1468 old_desc = seg_desc;
1469 seg_desc.type |= 2; /* busy */
1470 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1471 sizeof(seg_desc), &ctxt->exception);
1472 if (ret != X86EMUL_CONTINUE)
1473 return ret;
dde7e6d1
AK		 1474 break;
1475 case VCPU_SREG_LDTR:
1476 if (seg_desc.s || seg_desc.type != 2)
1477 goto exception;
1478 break;
1479 default: /* DS, ES, FS, or GS */
4e62417b 1480 /*
dde7e6d1
AK		 1481 * segment is not a data or readable code segment or
1482 * ((segment is a data or nonconforming code segment)
1483 * and (both RPL and CPL > DPL))
4e62417b 1484 */
dde7e6d1
AK		 1485 if ((seg_desc.type & 0xa) == 0x8 ||
1486 (((seg_desc.type & 0xc) != 0xc) &&
1487 (rpl > dpl && cpl > dpl)))
1488 goto exception;
6aa8b732 1489 break;
dde7e6d1
AK		 1490 }
1491
1492 if (seg_desc.s) {
1493 /* mark segment as accessed */
1494 seg_desc.type |= 1;
7b105ca2 1495 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1496 if (ret != X86EMUL_CONTINUE)
1497 return ret;
1498 }
1499load:
7b105ca2 1500 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1501 return X86EMUL_CONTINUE;
1502exception:
1503 emulate_exception(ctxt, err_vec, err_code, true);
1504 return X86EMUL_PROPAGATE_FAULT;
1505}
1506
31be40b3
WY		 1507static void write_register_operand(struct operand *op)
1508{
1509 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1510 switch (op->bytes) {
1511 case 1:
1512 *(u8 *)op->addr.reg = (u8)op->val;
1513 break;
1514 case 2:
1515 *(u16 *)op->addr.reg = (u16)op->val;
1516 break;
1517 case 4:
1518 *op->addr.reg = (u32)op->val;
1519 break; /* 64b: zero-extend */
1520 case 8:
1521 *op->addr.reg = op->val;
1522 break;
1523 }
1524}
1525
adddcecf 1526static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1527{
1528 int rc;
dde7e6d1 1529
9dac77fa 1530 switch (ctxt->dst.type) {
dde7e6d1 1531 case OP_REG:
9dac77fa 1532 write_register_operand(&ctxt->dst);
6aa8b732 1533 break;
dde7e6d1 1534 case OP_MEM:
9dac77fa 1535 if (ctxt->lock_prefix)
3ca3ac4d 1536 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1537 ctxt->dst.addr.mem,
1538 &ctxt->dst.orig_val,
1539 &ctxt->dst.val,
1540 ctxt->dst.bytes);
341de7e3 1541 else
3ca3ac4d 1542 rc = segmented_write(ctxt,
9dac77fa
AK		 1543 ctxt->dst.addr.mem,
1544 &ctxt->dst.val,
1545 ctxt->dst.bytes);
dde7e6d1
AK		 1546 if (rc != X86EMUL_CONTINUE)
1547 return rc;
a682e354 1548 break;
1253791d 1549 case OP_XMM:
9dac77fa 1550 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1551 break;
cbe2c9d3
AK		 1552 case OP_MM:
1553 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1554 break;
dde7e6d1
AK		 1555 case OP_NONE:
1556 /* no writeback */
414e6277 1557 break;
dde7e6d1 1558 default:
414e6277 1559 break;
6aa8b732 1560 }
dde7e6d1
AK		 1561 return X86EMUL_CONTINUE;
1562}
6aa8b732 1563
51ddff50 1564static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1565{
4179bb02 1566 struct segmented_address addr;
0dc8d10f 1567
5ad105e5 1568 rsp_increment(ctxt, -bytes);
dd856efa 1569 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1570 addr.seg = VCPU_SREG_SS;
1571
51ddff50
AK		 1572 return segmented_write(ctxt, addr, data, bytes);
1573}
1574
1575static int em_push(struct x86_emulate_ctxt *ctxt)
1576{
4179bb02 1577 /* Disable writeback. */
9dac77fa 1578 ctxt->dst.type = OP_NONE;
51ddff50 1579 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1580}
69f55cb1 1581
dde7e6d1 1582static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1583 void *dest, int len)
1584{
dde7e6d1 1585 int rc;
90de84f5 1586 struct segmented_address addr;
8b4caf66 1587
dd856efa 1588 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1589 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1590 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1591 if (rc != X86EMUL_CONTINUE)
1592 return rc;
1593
5ad105e5 1594 rsp_increment(ctxt, len);
dde7e6d1 1595 return rc;
8b4caf66
LV		 1596}
1597
c54fe504
TY		 1598static int em_pop(struct x86_emulate_ctxt *ctxt)
1599{
9dac77fa 1600 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1601}
1602
dde7e6d1 1603static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1604 void *dest, int len)
9de41573
GN		 1605{
1606 int rc;
dde7e6d1
AK		 1607 unsigned long val, change_mask;
1608 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1609 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1610
3b9be3bf 1611 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1612 if (rc != X86EMUL_CONTINUE)
1613 return rc;
9de41573 1614
dde7e6d1
AK		 1615 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1616 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1617
dde7e6d1
AK		 1618 switch(ctxt->mode) {
1619 case X86EMUL_MODE_PROT64:
1620 case X86EMUL_MODE_PROT32:
1621 case X86EMUL_MODE_PROT16:
1622 if (cpl == 0)
1623 change_mask |= EFLG_IOPL;
1624 if (cpl <= iopl)
1625 change_mask |= EFLG_IF;
1626 break;
1627 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1628 if (iopl < 3)
1629 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1630 change_mask |= EFLG_IF;
1631 break;
1632 default: /* real mode */
1633 change_mask |= (EFLG_IOPL | EFLG_IF);
1634 break;
9de41573 1635 }
dde7e6d1
AK		 1636
1637 *(unsigned long *)dest =
1638 (ctxt->eflags & ~change_mask) | (val & change_mask);
1639
1640 return rc;
9de41573
GN		 1641}
1642
62aaa2f0
TY		 1643static int em_popf(struct x86_emulate_ctxt *ctxt)
1644{
9dac77fa
AK		 1645 ctxt->dst.type = OP_REG;
1646 ctxt->dst.addr.reg = &ctxt->eflags;
1647 ctxt->dst.bytes = ctxt->op_bytes;
1648 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1649}
1650
612e89f0
AK		 1651static int em_enter(struct x86_emulate_ctxt *ctxt)
1652{
1653 int rc;
1654 unsigned frame_size = ctxt->src.val;
1655 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1656 ulong rbp;
612e89f0
AK		 1657
1658 if (nesting_level)
1659 return X86EMUL_UNHANDLEABLE;
1660
dd856efa
AK		 1661 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1662 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1663 if (rc != X86EMUL_CONTINUE)
1664 return rc;
dd856efa 1665 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1666 stack_mask(ctxt));
dd856efa
AK		 1667 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1668 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1669 stack_mask(ctxt));
1670 return X86EMUL_CONTINUE;
1671}
1672
f47cfa31
AK		 1673static int em_leave(struct x86_emulate_ctxt *ctxt)
1674{
dd856efa 1675 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1676 stack_mask(ctxt));
dd856efa 1677 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1678}
1679
1cd196ea 1680static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1681{
1cd196ea
AK		 1682 int seg = ctxt->src2.val;
1683
9dac77fa 1684 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1685
4487b3b4 1686 return em_push(ctxt);
7b262e90
GN		 1687}
1688
1cd196ea 1689static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1690{
1cd196ea 1691 int seg = ctxt->src2.val;
dde7e6d1
AK		 1692 unsigned long selector;
1693 int rc;
38ba30ba 1694
9dac77fa 1695 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1696 if (rc != X86EMUL_CONTINUE)
1697 return rc;
1698
7b105ca2 1699 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1700 return rc;
38ba30ba
GN		 1701}
1702
b96a7fad 1703static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1704{
dd856efa 1705 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1706 int rc = X86EMUL_CONTINUE;
1707 int reg = VCPU_REGS_RAX;
38ba30ba 1708
dde7e6d1
AK		 1709 while (reg <= VCPU_REGS_RDI) {
1710 (reg == VCPU_REGS_RSP) ?
dd856efa 1711 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1712
4487b3b4 1713 rc = em_push(ctxt);
dde7e6d1
AK		 1714 if (rc != X86EMUL_CONTINUE)
1715 return rc;
38ba30ba 1716
dde7e6d1 1717 ++reg;
38ba30ba 1718 }
38ba30ba 1719
dde7e6d1 1720 return rc;
38ba30ba
GN		 1721}
1722
62aaa2f0
TY		 1723static int em_pushf(struct x86_emulate_ctxt *ctxt)
1724{
9dac77fa 1725 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1726 return em_push(ctxt);
1727}
1728
b96a7fad 1729static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1730{
dde7e6d1
AK		 1731 int rc = X86EMUL_CONTINUE;
1732 int reg = VCPU_REGS_RDI;
38ba30ba 1733
dde7e6d1
AK		 1734 while (reg >= VCPU_REGS_RAX) {
1735 if (reg == VCPU_REGS_RSP) {
5ad105e5 1736 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1737 --reg;
1738 }
38ba30ba 1739
dd856efa 1740 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1741 if (rc != X86EMUL_CONTINUE)
1742 break;
1743 --reg;
38ba30ba 1744 }
dde7e6d1 1745 return rc;
38ba30ba
GN		 1746}
1747
dd856efa 1748static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1749{
7b105ca2 1750 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1751 int rc;
6e154e56
MG		 1752 struct desc_ptr dt;
1753 gva_t cs_addr;
1754 gva_t eip_addr;
1755 u16 cs, eip;
6e154e56
MG		 1756
1757 /* TODO: Add limit checks */
9dac77fa 1758 ctxt->src.val = ctxt->eflags;
4487b3b4 1759 rc = em_push(ctxt);
5c56e1cf
AK		 1760 if (rc != X86EMUL_CONTINUE)
1761 return rc;
6e154e56
MG		 1762
1763 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1764
9dac77fa 1765 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1766 rc = em_push(ctxt);
5c56e1cf
AK		 1767 if (rc != X86EMUL_CONTINUE)
1768 return rc;
6e154e56 1769
9dac77fa 1770 ctxt->src.val = ctxt->_eip;
4487b3b4 1771 rc = em_push(ctxt);
5c56e1cf
AK		 1772 if (rc != X86EMUL_CONTINUE)
1773 return rc;
1774
4bff1e86 1775 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1776
1777 eip_addr = dt.address + (irq << 2);
1778 cs_addr = dt.address + (irq << 2) + 2;
1779
0f65dd70 1780 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1781 if (rc != X86EMUL_CONTINUE)
1782 return rc;
1783
0f65dd70 1784 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1785 if (rc != X86EMUL_CONTINUE)
1786 return rc;
1787
7b105ca2 1788 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1789 if (rc != X86EMUL_CONTINUE)
1790 return rc;
1791
9dac77fa 1792 ctxt->_eip = eip;
6e154e56
MG		 1793
1794 return rc;
1795}
1796
dd856efa
AK		 1797int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1798{
1799 int rc;
1800
1801 invalidate_registers(ctxt);
1802 rc = __emulate_int_real(ctxt, irq);
1803 if (rc == X86EMUL_CONTINUE)
1804 writeback_registers(ctxt);
1805 return rc;
1806}
1807
7b105ca2 1808static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1809{
1810 switch(ctxt->mode) {
1811 case X86EMUL_MODE_REAL:
dd856efa 1812 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1813 case X86EMUL_MODE_VM86:
1814 case X86EMUL_MODE_PROT16:
1815 case X86EMUL_MODE_PROT32:
1816 case X86EMUL_MODE_PROT64:
1817 default:
1818 /* Protected mode interrupts unimplemented yet */
1819 return X86EMUL_UNHANDLEABLE;
1820 }
1821}
1822
7b105ca2 1823static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1824{
dde7e6d1
AK		 1825 int rc = X86EMUL_CONTINUE;
1826 unsigned long temp_eip = 0;
1827 unsigned long temp_eflags = 0;
1828 unsigned long cs = 0;
1829 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1830 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1831 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1832 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1833
dde7e6d1 1834 /* TODO: Add stack limit check */
38ba30ba 1835
9dac77fa 1836 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1837
dde7e6d1
AK		 1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
38ba30ba 1840
35d3d4a1
AK		 1841 if (temp_eip & ~0xffff)
1842 return emulate_gp(ctxt, 0);
38ba30ba 1843
9dac77fa 1844 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1845
dde7e6d1
AK		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
38ba30ba 1848
9dac77fa 1849 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1850
dde7e6d1
AK		 1851 if (rc != X86EMUL_CONTINUE)
1852 return rc;
38ba30ba 1853
7b105ca2 1854 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1855
dde7e6d1
AK		 1856 if (rc != X86EMUL_CONTINUE)
1857 return rc;
38ba30ba 1858
9dac77fa 1859 ctxt->_eip = temp_eip;
38ba30ba 1860
38ba30ba 1861
9dac77fa 1862 if (ctxt->op_bytes == 4)
dde7e6d1 1863 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1864 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1865 ctxt->eflags &= ~0xffff;
1866 ctxt->eflags |= temp_eflags;
38ba30ba 1867 }
dde7e6d1
AK		 1868
1869 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1870 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1871
1872 return rc;
38ba30ba
GN		 1873}
1874
e01991e7 1875static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1876{
dde7e6d1
AK		 1877 switch(ctxt->mode) {
1878 case X86EMUL_MODE_REAL:
7b105ca2 1879 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1880 case X86EMUL_MODE_VM86:
1881 case X86EMUL_MODE_PROT16:
1882 case X86EMUL_MODE_PROT32:
1883 case X86EMUL_MODE_PROT64:
c37eda13 1884 default:
dde7e6d1
AK		 1885 /* iret from protected mode unimplemented yet */
1886 return X86EMUL_UNHANDLEABLE;
c37eda13 1887 }
c37eda13
WY		 1888}
1889
d2f62766
TY		 1890static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1891{
d2f62766
TY		 1892 int rc;
1893 unsigned short sel;
1894
9dac77fa 1895 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1896
7b105ca2 1897 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1898 if (rc != X86EMUL_CONTINUE)
1899 return rc;
1900
9dac77fa
AK		 1901 ctxt->_eip = 0;
1902 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1903 return X86EMUL_CONTINUE;
1904}
1905
51187683 1906static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1907{
9dac77fa 1908 switch (ctxt->modrm_reg) {
8cdbd2c9 1909 case 0: /* rol */
a31b9cea 1910 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1911 break;
1912 case 1: /* ror */
a31b9cea 1913 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1914 break;
1915 case 2: /* rcl */
a31b9cea 1916 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1917 break;
1918 case 3: /* rcr */
a31b9cea 1919 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1920 break;
1921 case 4: /* sal/shl */
1922 case 6: /* sal/shl */
a31b9cea 1923 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1924 break;
1925 case 5: /* shr */
a31b9cea 1926 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1927 break;
1928 case 7: /* sar */
a31b9cea 1929 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1930 break;
1931 }
51187683 1932 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1933}
1934
3329ece1
AK		 1935static int em_not(struct x86_emulate_ctxt *ctxt)
1936{
1937 ctxt->dst.val = ~ctxt->dst.val;
1938 return X86EMUL_CONTINUE;
1939}
1940
1941static int em_neg(struct x86_emulate_ctxt *ctxt)
1942{
1943 emulate_1op(ctxt, "neg");
1944 return X86EMUL_CONTINUE;
1945}
1946
1947static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1948{
1949 u8 ex = 0;
1950
1951 emulate_1op_rax_rdx(ctxt, "mul", ex);
1952 return X86EMUL_CONTINUE;
1953}
1954
1955static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1956{
1957 u8 ex = 0;
1958
1959 emulate_1op_rax_rdx(ctxt, "imul", ex);
1960 return X86EMUL_CONTINUE;
1961}
1962
1963static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1964{
34d1f490 1965 u8 de = 0;
8cdbd2c9 1966
3329ece1
AK		 1967 emulate_1op_rax_rdx(ctxt, "div", de);
1968 if (de)
1969 return emulate_de(ctxt);
1970 return X86EMUL_CONTINUE;
1971}
1972
1973static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1974{
1975 u8 de = 0;
1976
1977 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1978 if (de)
1979 return emulate_de(ctxt);
8c5eee30 1980 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1981}
1982
51187683 1983static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1984{
4179bb02 1985 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1986
9dac77fa 1987 switch (ctxt->modrm_reg) {
8cdbd2c9 1988 case 0: /* inc */
d1eef45d 1989 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1990 break;
1991 case 1: /* dec */
d1eef45d 1992 emulate_1op(ctxt, "dec");
8cdbd2c9 1993 break;
d19292e4
MG		 1994 case 2: /* call near abs */ {
1995 long int old_eip;
9dac77fa
AK		 1996 old_eip = ctxt->_eip;
1997 ctxt->_eip = ctxt->src.val;
1998 ctxt->src.val = old_eip;
4487b3b4 1999 rc = em_push(ctxt);
d19292e4
MG		 2000 break;
2001 }
8cdbd2c9 2002 case 4: /* jmp abs */
9dac77fa 2003 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2004 break;
d2f62766
TY		 2005 case 5: /* jmp far */
2006 rc = em_jmp_far(ctxt);
2007 break;
8cdbd2c9 2008 case 6: /* push */
4487b3b4 2009 rc = em_push(ctxt);
8cdbd2c9 2010 break;
8cdbd2c9 2011 }
4179bb02 2012 return rc;
8cdbd2c9
LV		 2013}
2014
e0dac408 2015static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2016{
9dac77fa 2017 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2018
dd856efa
AK		 2019 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2020 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2021 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2022 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2023 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2024 } else {
dd856efa
AK		 2025 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2026 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2027
05f086f8 2028 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2029 }
1b30eaa8 2030 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2031}
2032
ebda02c2
TY		 2033static int em_ret(struct x86_emulate_ctxt *ctxt)
2034{
9dac77fa
AK		 2035 ctxt->dst.type = OP_REG;
2036 ctxt->dst.addr.reg = &ctxt->_eip;
2037 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2038 return em_pop(ctxt);
2039}
2040
e01991e7 2041static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2042{
a77ab5ea
AK		 2043 int rc;
2044 unsigned long cs;
2045
9dac77fa 2046 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2047 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2048 return rc;
9dac77fa
AK		 2049 if (ctxt->op_bytes == 4)
2050 ctxt->_eip = (u32)ctxt->_eip;
2051 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2052 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2053 return rc;
7b105ca2 2054 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2055 return rc;
2056}
2057
e940b5c2
TY		 2058static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2059{
2060 /* Save real source value, then compare EAX against destination. */
2061 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2062 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2063 emulate_2op_SrcV(ctxt, "cmp");
2064
2065 if (ctxt->eflags & EFLG_ZF) {
2066 /* Success: write back to memory. */
2067 ctxt->dst.val = ctxt->src.orig_val;
2068 } else {
2069 /* Failure: write the value we saw to EAX. */
2070 ctxt->dst.type = OP_REG;
dd856efa 2071 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2072 }
2073 return X86EMUL_CONTINUE;
2074}
2075
d4b4325f 2076static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2077{
d4b4325f 2078 int seg = ctxt->src2.val;
09b5f4d3
WY		 2079 unsigned short sel;
2080 int rc;
2081
9dac77fa 2082 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2083
7b105ca2 2084 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2085 if (rc != X86EMUL_CONTINUE)
2086 return rc;
2087
9dac77fa 2088 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2089 return rc;
2090}
2091
7b105ca2 2092static void
e66bb2cc 2093setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2094 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2095{
e66bb2cc 2096 cs->l = 0; /* will be adjusted later */
79168fd1 2097 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2098 cs->g = 1; /* 4kb granularity */
79168fd1 2099 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2100 cs->type = 0x0b; /* Read, Execute, Accessed */
2101 cs->s = 1;
2102 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2103 cs->p = 1;
2104 cs->d = 1;
99245b50 2105 cs->avl = 0;
e66bb2cc 2106
79168fd1
GN		 2107 set_desc_base(ss, 0); /* flat segment */
2108 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2109 ss->g = 1; /* 4kb granularity */
2110 ss->s = 1;
2111 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2112 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2113 ss->dpl = 0;
79168fd1 2114 ss->p = 1;
99245b50
GN		 2115 ss->l = 0;
2116 ss->avl = 0;
e66bb2cc
AP		 2117}
2118
1a18a69b
AK		 2119static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2120{
2121 u32 eax, ebx, ecx, edx;
2122
2123 eax = ecx = 0;
0017f93a
AK		 2124 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2125 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2126 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2127 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2128}
2129
c2226fc9
SB		 2130static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2131{
2132 struct x86_emulate_ops *ops = ctxt->ops;
2133 u32 eax, ebx, ecx, edx;
2134
2135 /*
2136 * syscall should always be enabled in longmode - so only become
2137 * vendor specific (cpuid) if other modes are active...
2138 */
2139 if (ctxt->mode == X86EMUL_MODE_PROT64)
2140 return true;
2141
2142 eax = 0x00000000;
2143 ecx = 0x00000000;
0017f93a
AK		 2144 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2145 /*
2146 * Intel ("GenuineIntel")
2147 * remark: Intel CPUs only support "syscall" in 64bit
2148 * longmode. Also an 64bit guest with a
2149 * 32bit compat-app running will #UD !! While this
2150 * behaviour can be fixed (by emulating) into AMD
2151 * response - CPUs of AMD can't behave like Intel.
2152 */
2153 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2154 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2155 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2156 return false;
2157
2158 /* AMD ("AuthenticAMD") */
2159 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2160 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2161 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2162 return true;
2163
2164 /* AMD ("AMDisbetter!") */
2165 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2166 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2167 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2168 return true;
c2226fc9
SB		 2169
2170 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2171 return false;
2172}
2173
e01991e7 2174static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2175{
7b105ca2 2176 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2177 struct desc_struct cs, ss;
e66bb2cc 2178 u64 msr_data;
79168fd1 2179 u16 cs_sel, ss_sel;
c2ad2bb3 2180 u64 efer = 0;
e66bb2cc
AP		 2181
2182 /* syscall is not available in real mode */
2e901c4c 2183 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2184 ctxt->mode == X86EMUL_MODE_VM86)
2185 return emulate_ud(ctxt);
e66bb2cc 2186
c2226fc9
SB		 2187 if (!(em_syscall_is_enabled(ctxt)))
2188 return emulate_ud(ctxt);
2189
c2ad2bb3 2190 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2191 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2192
c2226fc9
SB		 2193 if (!(efer & EFER_SCE))
2194 return emulate_ud(ctxt);
2195
717746e3 2196 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2197 msr_data >>= 32;
79168fd1
GN		 2198 cs_sel = (u16)(msr_data & 0xfffc);
2199 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2200
c2ad2bb3 2201 if (efer & EFER_LMA) {
79168fd1 2202 cs.d = 0;
e66bb2cc
AP		 2203 cs.l = 1;
2204 }
1aa36616
AK		 2205 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2206 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2207
dd856efa 2208 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2209 if (efer & EFER_LMA) {
e66bb2cc 2210#ifdef CONFIG_X86_64
dd856efa 2211 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2212
717746e3 2213 ops->get_msr(ctxt,
3fb1b5db
GN		 2214 ctxt->mode == X86EMUL_MODE_PROT64 ?
2215 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2216 ctxt->_eip = msr_data;
e66bb2cc 2217
717746e3 2218 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2219 ctxt->eflags &= ~(msr_data | EFLG_RF);
2220#endif
2221 } else {
2222 /* legacy mode */
717746e3 2223 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2224 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2225
2226 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2227 }
2228
e54cfa97 2229 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2230}
2231
e01991e7 2232static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2233{
7b105ca2 2234 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2235 struct desc_struct cs, ss;
8c604352 2236 u64 msr_data;
79168fd1 2237 u16 cs_sel, ss_sel;
c2ad2bb3 2238 u64 efer = 0;
8c604352 2239
7b105ca2 2240 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2241 /* inject #GP if in real mode */
35d3d4a1
AK		 2242 if (ctxt->mode == X86EMUL_MODE_REAL)
2243 return emulate_gp(ctxt, 0);
8c604352 2244
1a18a69b
AK		 2245 /*
2246 * Not recognized on AMD in compat mode (but is recognized in legacy
2247 * mode).
2248 */
2249 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2250 && !vendor_intel(ctxt))
2251 return emulate_ud(ctxt);
2252
8c604352
AP		 2253 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2254 * Therefore, we inject an #UD.
2255 */
35d3d4a1
AK		 2256 if (ctxt->mode == X86EMUL_MODE_PROT64)
2257 return emulate_ud(ctxt);
8c604352 2258
7b105ca2 2259 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2260
717746e3 2261 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2262 switch (ctxt->mode) {
2263 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2264 if ((msr_data & 0xfffc) == 0x0)
2265 return emulate_gp(ctxt, 0);
8c604352
AP		 2266 break;
2267 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2268 if (msr_data == 0x0)
2269 return emulate_gp(ctxt, 0);
8c604352
AP		 2270 break;
2271 }
2272
2273 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2274 cs_sel = (u16)msr_data;
2275 cs_sel &= ~SELECTOR_RPL_MASK;
2276 ss_sel = cs_sel + 8;
2277 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2278 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2279 cs.d = 0;
8c604352
AP		 2280 cs.l = 1;
2281 }
2282
1aa36616
AK		 2283 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2284 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2285
717746e3 2286 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2287 ctxt->_eip = msr_data;
8c604352 2288
717746e3 2289 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2290 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2291
e54cfa97 2292 return X86EMUL_CONTINUE;
8c604352
AP		 2293}
2294
e01991e7 2295static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2296{
7b105ca2 2297 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2298 struct desc_struct cs, ss;
4668f050
AP		 2299 u64 msr_data;
2300 int usermode;
1249b96e 2301 u16 cs_sel = 0, ss_sel = 0;
4668f050 2302
a0044755
GN		 2303 /* inject #GP if in real mode or Virtual 8086 mode */
2304 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2305 ctxt->mode == X86EMUL_MODE_VM86)
2306 return emulate_gp(ctxt, 0);
4668f050 2307
7b105ca2 2308 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2309
9dac77fa 2310 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2311 usermode = X86EMUL_MODE_PROT64;
2312 else
2313 usermode = X86EMUL_MODE_PROT32;
2314
2315 cs.dpl = 3;
2316 ss.dpl = 3;
717746e3 2317 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2318 switch (usermode) {
2319 case X86EMUL_MODE_PROT32:
79168fd1 2320 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2321 if ((msr_data & 0xfffc) == 0x0)
2322 return emulate_gp(ctxt, 0);
79168fd1 2323 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2324 break;
2325 case X86EMUL_MODE_PROT64:
79168fd1 2326 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2327 if (msr_data == 0x0)
2328 return emulate_gp(ctxt, 0);
79168fd1
GN		 2329 ss_sel = cs_sel + 8;
2330 cs.d = 0;
4668f050
AP		 2331 cs.l = 1;
2332 break;
2333 }
79168fd1
GN		 2334 cs_sel |= SELECTOR_RPL_MASK;
2335 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2336
1aa36616
AK		 2337 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2338 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2339
dd856efa
AK		 2340 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2341 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2342
e54cfa97 2343 return X86EMUL_CONTINUE;
4668f050
AP		 2344}
2345
7b105ca2 2346static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2347{
2348 int iopl;
2349 if (ctxt->mode == X86EMUL_MODE_REAL)
2350 return false;
2351 if (ctxt->mode == X86EMUL_MODE_VM86)
2352 return true;
2353 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2354 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2355}
2356
2357static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2358 u16 port, u16 len)
2359{
7b105ca2 2360 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2361 struct desc_struct tr_seg;
5601d05b 2362 u32 base3;
f850e2e6 2363 int r;
1aa36616 2364 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2365 unsigned mask = (1 << len) - 1;
5601d05b 2366 unsigned long base;
f850e2e6 2367
1aa36616 2368 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2369 if (!tr_seg.p)
f850e2e6 2370 return false;
79168fd1 2371 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2372 return false;
5601d05b
GN		 2373 base = get_desc_base(&tr_seg);
2374#ifdef CONFIG_X86_64
2375 base |= ((u64)base3) << 32;
2376#endif
0f65dd70 2377 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2378 if (r != X86EMUL_CONTINUE)
2379 return false;
79168fd1 2380 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2381 return false;
0f65dd70 2382 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2383 if (r != X86EMUL_CONTINUE)
2384 return false;
2385 if ((perm >> bit_idx) & mask)
2386 return false;
2387 return true;
2388}
2389
2390static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2391 u16 port, u16 len)
2392{
4fc40f07
GN		 2393 if (ctxt->perm_ok)
2394 return true;
2395
7b105ca2
TY		 2396 if (emulator_bad_iopl(ctxt))
2397 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2398 return false;
4fc40f07
GN		 2399
2400 ctxt->perm_ok = true;
2401
f850e2e6
GN		 2402 return true;
2403}
2404
38ba30ba 2405static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2406 struct tss_segment_16 *tss)
2407{
9dac77fa 2408 tss->ip = ctxt->_eip;
38ba30ba 2409 tss->flag = ctxt->eflags;
dd856efa
AK		 2410 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2411 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2412 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2413 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2414 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2415 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2416 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2417 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2418
1aa36616
AK		 2419 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2420 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2421 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2422 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2423 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2424}
2425
2426static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2427 struct tss_segment_16 *tss)
2428{
38ba30ba
GN		 2429 int ret;
2430
9dac77fa 2431 ctxt->_eip = tss->ip;
38ba30ba 2432 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2433 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2434 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2435 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2436 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2437 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2438 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2439 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2440 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2441
2442 /*
2443 * SDM says that segment selectors are loaded before segment
2444 * descriptors
2445 */
1aa36616
AK		 2446 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2447 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2448 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2449 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2450 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2451
2452 /*
fc058680 2453 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2454 * it is handled in a context of new task
2455 */
7b105ca2 2456 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2457 if (ret != X86EMUL_CONTINUE)
2458 return ret;
7b105ca2 2459 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2460 if (ret != X86EMUL_CONTINUE)
2461 return ret;
7b105ca2 2462 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2463 if (ret != X86EMUL_CONTINUE)
2464 return ret;
7b105ca2 2465 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2466 if (ret != X86EMUL_CONTINUE)
2467 return ret;
7b105ca2 2468 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2469 if (ret != X86EMUL_CONTINUE)
2470 return ret;
2471
2472 return X86EMUL_CONTINUE;
2473}
2474
2475static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2476 u16 tss_selector, u16 old_tss_sel,
2477 ulong old_tss_base, struct desc_struct *new_desc)
2478{
7b105ca2 2479 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2480 struct tss_segment_16 tss_seg;
2481 int ret;
bcc55cba 2482 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2483
0f65dd70 2484 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2485 &ctxt->exception);
db297e3d 2486 if (ret != X86EMUL_CONTINUE)
38ba30ba 2487 /* FIXME: need to provide precise fault address */
38ba30ba 2488 return ret;
38ba30ba 2489
7b105ca2 2490 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2491
0f65dd70 2492 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2493 &ctxt->exception);
db297e3d 2494 if (ret != X86EMUL_CONTINUE)
38ba30ba 2495 /* FIXME: need to provide precise fault address */
38ba30ba 2496 return ret;
38ba30ba 2497
0f65dd70 2498 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2499 &ctxt->exception);
db297e3d 2500 if (ret != X86EMUL_CONTINUE)
38ba30ba 2501 /* FIXME: need to provide precise fault address */
38ba30ba 2502 return ret;
38ba30ba
GN		 2503
2504 if (old_tss_sel != 0xffff) {
2505 tss_seg.prev_task_link = old_tss_sel;
2506
0f65dd70 2507 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2508 &tss_seg.prev_task_link,
2509 sizeof tss_seg.prev_task_link,
0f65dd70 2510 &ctxt->exception);
db297e3d 2511 if (ret != X86EMUL_CONTINUE)
38ba30ba 2512 /* FIXME: need to provide precise fault address */
38ba30ba 2513 return ret;
38ba30ba
GN		 2514 }
2515
7b105ca2 2516 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2517}
2518
2519static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2520 struct tss_segment_32 *tss)
2521{
7b105ca2 2522 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2523 tss->eip = ctxt->_eip;
38ba30ba 2524 tss->eflags = ctxt->eflags;
dd856efa
AK		 2525 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2526 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2527 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2528 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2529 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2530 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2531 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2532 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2533
1aa36616
AK		 2534 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2535 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2536 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2537 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2538 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2539 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2540 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2541}
2542
2543static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2544 struct tss_segment_32 *tss)
2545{
38ba30ba
GN		 2546 int ret;
2547
7b105ca2 2548 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2549 return emulate_gp(ctxt, 0);
9dac77fa 2550 ctxt->_eip = tss->eip;
38ba30ba 2551 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2552
2553 /* General purpose registers */
dd856efa
AK		 2554 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2555 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2556 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2557 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2558 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2559 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2560 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2561 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2562
2563 /*
2564 * SDM says that segment selectors are loaded before segment
2565 * descriptors
2566 */
1aa36616
AK		 2567 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2568 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2569 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2570 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2571 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2572 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2573 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2574
4cee4798
KW		 2575 /*
2576 * If we're switching between Protected Mode and VM86, we need to make
2577 * sure to update the mode before loading the segment descriptors so
2578 * that the selectors are interpreted correctly.
2579 *
2580 * Need to get rflags to the vcpu struct immediately because it
2581 * influences the CPL which is checked at least when loading the segment
2582 * descriptors and when pushing an error code to the new kernel stack.
2583 *
2584 * TODO Introduce a separate ctxt->ops->set_cpl callback
2585 */
2586 if (ctxt->eflags & X86_EFLAGS_VM)
2587 ctxt->mode = X86EMUL_MODE_VM86;
2588 else
2589 ctxt->mode = X86EMUL_MODE_PROT32;
2590
2591 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2592
38ba30ba
GN		 2593 /*
2594 * Now load segment descriptors. If fault happenes at this stage
2595 * it is handled in a context of new task
2596 */
7b105ca2 2597 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2598 if (ret != X86EMUL_CONTINUE)
2599 return ret;
7b105ca2 2600 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
7b105ca2 2603 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
7b105ca2 2606 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2607 if (ret != X86EMUL_CONTINUE)
2608 return ret;
7b105ca2 2609 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2610 if (ret != X86EMUL_CONTINUE)
2611 return ret;
7b105ca2 2612 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2613 if (ret != X86EMUL_CONTINUE)
2614 return ret;
7b105ca2 2615 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2616 if (ret != X86EMUL_CONTINUE)
2617 return ret;
2618
2619 return X86EMUL_CONTINUE;
2620}
2621
2622static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2623 u16 tss_selector, u16 old_tss_sel,
2624 ulong old_tss_base, struct desc_struct *new_desc)
2625{
7b105ca2 2626 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2627 struct tss_segment_32 tss_seg;
2628 int ret;
bcc55cba 2629 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2630
0f65dd70 2631 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2632 &ctxt->exception);
db297e3d 2633 if (ret != X86EMUL_CONTINUE)
38ba30ba 2634 /* FIXME: need to provide precise fault address */
38ba30ba 2635 return ret;
38ba30ba 2636
7b105ca2 2637 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2638
0f65dd70 2639 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2640 &ctxt->exception);
db297e3d 2641 if (ret != X86EMUL_CONTINUE)
38ba30ba 2642 /* FIXME: need to provide precise fault address */
38ba30ba 2643 return ret;
38ba30ba 2644
0f65dd70 2645 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba
GN		 2650
2651 if (old_tss_sel != 0xffff) {
2652 tss_seg.prev_task_link = old_tss_sel;
2653
0f65dd70 2654 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2655 &tss_seg.prev_task_link,
2656 sizeof tss_seg.prev_task_link,
0f65dd70 2657 &ctxt->exception);
db297e3d 2658 if (ret != X86EMUL_CONTINUE)
38ba30ba 2659 /* FIXME: need to provide precise fault address */
38ba30ba 2660 return ret;
38ba30ba
GN		 2661 }
2662
7b105ca2 2663 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2664}
2665
2666static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2667 u16 tss_selector, int idt_index, int reason,
e269fb21 2668 bool has_error_code, u32 error_code)
38ba30ba 2669{
7b105ca2 2670 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2671 struct desc_struct curr_tss_desc, next_tss_desc;
2672 int ret;
1aa36616 2673 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2674 ulong old_tss_base =
4bff1e86 2675 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2676 u32 desc_limit;
e919464b 2677 ulong desc_addr;
38ba30ba
GN		 2678
2679 /* FIXME: old_tss_base == ~0 ? */
2680
e919464b 2681 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2682 if (ret != X86EMUL_CONTINUE)
2683 return ret;
e919464b 2684 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2685 if (ret != X86EMUL_CONTINUE)
2686 return ret;
2687
2688 /* FIXME: check that next_tss_desc is tss */
2689
7f3d35fd
KW		 2690 /*
2691 * Check privileges. The three cases are task switch caused by...
2692 *
2693 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2694 * 2. Exception/IRQ/iret: No check is performed
fc058680 2695 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2696 */
2697 if (reason == TASK_SWITCH_GATE) {
2698 if (idt_index != -1) {
2699 /* Software interrupts */
2700 struct desc_struct task_gate_desc;
2701 int dpl;
2702
2703 ret = read_interrupt_descriptor(ctxt, idt_index,
2704 &task_gate_desc);
2705 if (ret != X86EMUL_CONTINUE)
2706 return ret;
2707
2708 dpl = task_gate_desc.dpl;
2709 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2710 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2711 }
2712 } else if (reason != TASK_SWITCH_IRET) {
2713 int dpl = next_tss_desc.dpl;
2714 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2715 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2716 }
2717
7f3d35fd 2718
ceffb459
GN		 2719 desc_limit = desc_limit_scaled(&next_tss_desc);
2720 if (!next_tss_desc.p ||
2721 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2722 desc_limit < 0x2b)) {
54b8486f 2723 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2724 return X86EMUL_PROPAGATE_FAULT;
2725 }
2726
2727 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2728 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2729 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2730 }
2731
2732 if (reason == TASK_SWITCH_IRET)
2733 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2734
2735 /* set back link to prev task only if NT bit is set in eflags
fc058680 2736 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2737 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2738 old_tss_sel = 0xffff;
2739
2740 if (next_tss_desc.type & 8)
7b105ca2 2741 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2742 old_tss_base, &next_tss_desc);
2743 else
7b105ca2 2744 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2745 old_tss_base, &next_tss_desc);
0760d448
JK		 2746 if (ret != X86EMUL_CONTINUE)
2747 return ret;
38ba30ba
GN		 2748
2749 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2750 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2751
2752 if (reason != TASK_SWITCH_IRET) {
2753 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2754 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2755 }
2756
717746e3 2757 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2758 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2759
e269fb21 2760 if (has_error_code) {
9dac77fa
AK		 2761 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2762 ctxt->lock_prefix = 0;
2763 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2764 ret = em_push(ctxt);
e269fb21
JK		 2765 }
2766
38ba30ba
GN		 2767 return ret;
2768}
2769
2770int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2771 u16 tss_selector, int idt_index, int reason,
e269fb21 2772 bool has_error_code, u32 error_code)
38ba30ba 2773{
38ba30ba
GN		 2774 int rc;
2775
dd856efa 2776 invalidate_registers(ctxt);
9dac77fa
AK		 2777 ctxt->_eip = ctxt->eip;
2778 ctxt->dst.type = OP_NONE;
38ba30ba 2779
7f3d35fd 2780 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2781 has_error_code, error_code);
38ba30ba 2782
dd856efa 2783 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2784 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2785 writeback_registers(ctxt);
2786 }
38ba30ba 2787
a0c0ab2f 2788 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2789}
2790
90de84f5 2791static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2792 int reg, struct operand *op)
a682e354 2793{
a682e354
GN		 2794 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2795
dd856efa
AK		 2796 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2797 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
90de84f5 2798 op->addr.mem.seg = seg;
a682e354
GN		 2799}
2800
7af04fc0
AK		 2801static int em_das(struct x86_emulate_ctxt *ctxt)
2802{
7af04fc0
AK		 2803 u8 al, old_al;
2804 bool af, cf, old_cf;
2805
2806 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2807 al = ctxt->dst.val;
7af04fc0
AK		 2808
2809 old_al = al;
2810 old_cf = cf;
2811 cf = false;
2812 af = ctxt->eflags & X86_EFLAGS_AF;
2813 if ((al & 0x0f) > 9 || af) {
2814 al -= 6;
2815 cf = old_cf | (al >= 250);
2816 af = true;
2817 } else {
2818 af = false;
2819 }
2820 if (old_al > 0x99 || old_cf) {
2821 al -= 0x60;
2822 cf = true;
2823 }
2824
9dac77fa 2825 ctxt->dst.val = al;
7af04fc0 2826 /* Set PF, ZF, SF */
9dac77fa
AK		 2827 ctxt->src.type = OP_IMM;
2828 ctxt->src.val = 0;
2829 ctxt->src.bytes = 1;
a31b9cea 2830 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2831 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2832 if (cf)
2833 ctxt->eflags |= X86_EFLAGS_CF;
2834 if (af)
2835 ctxt->eflags |= X86_EFLAGS_AF;
2836 return X86EMUL_CONTINUE;
2837}
2838
d4ddafcd
TY		 2839static int em_call(struct x86_emulate_ctxt *ctxt)
2840{
2841 long rel = ctxt->src.val;
2842
2843 ctxt->src.val = (unsigned long)ctxt->_eip;
2844 jmp_rel(ctxt, rel);
2845 return em_push(ctxt);
2846}
2847
0ef753b8
AK		 2848static int em_call_far(struct x86_emulate_ctxt *ctxt)
2849{
0ef753b8
AK		 2850 u16 sel, old_cs;
2851 ulong old_eip;
2852 int rc;
2853
1aa36616 2854 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2855 old_eip = ctxt->_eip;
0ef753b8 2856
9dac77fa 2857 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2858 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2859 return X86EMUL_CONTINUE;
2860
9dac77fa
AK		 2861 ctxt->_eip = 0;
2862 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2863
9dac77fa 2864 ctxt->src.val = old_cs;
4487b3b4 2865 rc = em_push(ctxt);
0ef753b8
AK		 2866 if (rc != X86EMUL_CONTINUE)
2867 return rc;
2868
9dac77fa 2869 ctxt->src.val = old_eip;
4487b3b4 2870 return em_push(ctxt);
0ef753b8
AK		 2871}
2872
40ece7c7
AK		 2873static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2874{
40ece7c7
AK		 2875 int rc;
2876
9dac77fa
AK		 2877 ctxt->dst.type = OP_REG;
2878 ctxt->dst.addr.reg = &ctxt->_eip;
2879 ctxt->dst.bytes = ctxt->op_bytes;
2880 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2881 if (rc != X86EMUL_CONTINUE)
2882 return rc;
5ad105e5 2883 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2884 return X86EMUL_CONTINUE;
2885}
2886
d67fc27a
TY		 2887static int em_add(struct x86_emulate_ctxt *ctxt)
2888{
a31b9cea 2889 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2890 return X86EMUL_CONTINUE;
2891}
2892
2893static int em_or(struct x86_emulate_ctxt *ctxt)
2894{
a31b9cea 2895 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2896 return X86EMUL_CONTINUE;
2897}
2898
2899static int em_adc(struct x86_emulate_ctxt *ctxt)
2900{
a31b9cea 2901 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2902 return X86EMUL_CONTINUE;
2903}
2904
2905static int em_sbb(struct x86_emulate_ctxt *ctxt)
2906{
a31b9cea 2907 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2908 return X86EMUL_CONTINUE;
2909}
2910
2911static int em_and(struct x86_emulate_ctxt *ctxt)
2912{
a31b9cea 2913 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2914 return X86EMUL_CONTINUE;
2915}
2916
2917static int em_sub(struct x86_emulate_ctxt *ctxt)
2918{
a31b9cea 2919 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2920 return X86EMUL_CONTINUE;
2921}
2922
2923static int em_xor(struct x86_emulate_ctxt *ctxt)
2924{
a31b9cea 2925 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2926 return X86EMUL_CONTINUE;
2927}
2928
2929static int em_cmp(struct x86_emulate_ctxt *ctxt)
2930{
a31b9cea 2931 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2932 /* Disable writeback. */
9dac77fa 2933 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2934 return X86EMUL_CONTINUE;
2935}
2936
9f21ca59
TY		 2937static int em_test(struct x86_emulate_ctxt *ctxt)
2938{
a31b9cea 2939 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2940 /* Disable writeback. */
2941 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2942 return X86EMUL_CONTINUE;
2943}
2944
e4f973ae
TY		 2945static int em_xchg(struct x86_emulate_ctxt *ctxt)
2946{
e4f973ae 2947 /* Write back the register source. */
9dac77fa
AK		 2948 ctxt->src.val = ctxt->dst.val;
2949 write_register_operand(&ctxt->src);
e4f973ae
TY		 2950
2951 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2952 ctxt->dst.val = ctxt->src.orig_val;
2953 ctxt->lock_prefix = 1;
e4f973ae
TY		 2954 return X86EMUL_CONTINUE;
2955}
2956
5c82aa29 2957static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2958{
a31b9cea 2959 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2960 return X86EMUL_CONTINUE;
2961}
2962
5c82aa29
AK		 2963static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2964{
9dac77fa 2965 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2966 return em_imul(ctxt);
2967}
2968
61429142
AK		 2969static int em_cwd(struct x86_emulate_ctxt *ctxt)
2970{
9dac77fa
AK		 2971 ctxt->dst.type = OP_REG;
2972 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2973 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2974 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2975
2976 return X86EMUL_CONTINUE;
2977}
2978
48bb5d3c
AK		 2979static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2980{
48bb5d3c
AK		 2981 u64 tsc = 0;
2982
717746e3 2983 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2984 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2985 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2986 return X86EMUL_CONTINUE;
2987}
2988
222d21aa
AK		 2989static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2990{
2991 u64 pmc;
2992
dd856efa 2993 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2994 return emulate_gp(ctxt, 0);
dd856efa
AK		 2995 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2996 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2997 return X86EMUL_CONTINUE;
2998}
2999
b9eac5f4
AK		 3000static int em_mov(struct x86_emulate_ctxt *ctxt)
3001{
49597d81 3002 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3003 return X86EMUL_CONTINUE;
3004}
3005
bc00f8d2
TY		 3006static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3007{
3008 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3009 return emulate_gp(ctxt, 0);
3010
3011 /* Disable writeback. */
3012 ctxt->dst.type = OP_NONE;
3013 return X86EMUL_CONTINUE;
3014}
3015
3016static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3017{
3018 unsigned long val;
3019
3020 if (ctxt->mode == X86EMUL_MODE_PROT64)
3021 val = ctxt->src.val & ~0ULL;
3022 else
3023 val = ctxt->src.val & ~0U;
3024
3025 /* #UD condition is already handled. */
3026 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3027 return emulate_gp(ctxt, 0);
3028
3029 /* Disable writeback. */
3030 ctxt->dst.type = OP_NONE;
3031 return X86EMUL_CONTINUE;
3032}
3033
e1e210b0
TY		 3034static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3035{
3036 u64 msr_data;
3037
dd856efa
AK		 3038 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3039 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3040 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3041 return emulate_gp(ctxt, 0);
3042
3043 return X86EMUL_CONTINUE;
3044}
3045
3046static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3047{
3048 u64 msr_data;
3049
dd856efa 3050 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3051 return emulate_gp(ctxt, 0);
3052
dd856efa
AK		 3053 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3054 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3055 return X86EMUL_CONTINUE;
3056}
3057
1bd5f469
TY		 3058static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3059{
9dac77fa 3060 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3061 return emulate_ud(ctxt);
3062
9dac77fa 3063 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3064 return X86EMUL_CONTINUE;
3065}
3066
3067static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3068{
9dac77fa 3069 u16 sel = ctxt->src.val;
1bd5f469 3070
9dac77fa 3071 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3072 return emulate_ud(ctxt);
3073
9dac77fa 3074 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3075 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3076
3077 /* Disable writeback. */
9dac77fa
AK		 3078 ctxt->dst.type = OP_NONE;
3079 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3080}
3081
a14e579f
AK		 3082static int em_lldt(struct x86_emulate_ctxt *ctxt)
3083{
3084 u16 sel = ctxt->src.val;
3085
3086 /* Disable writeback. */
3087 ctxt->dst.type = OP_NONE;
3088 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3089}
3090
80890006
AK		 3091static int em_ltr(struct x86_emulate_ctxt *ctxt)
3092{
3093 u16 sel = ctxt->src.val;
3094
3095 /* Disable writeback. */
3096 ctxt->dst.type = OP_NONE;
3097 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3098}
3099
38503911
AK		 3100static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3101{
9fa088f4
AK		 3102 int rc;
3103 ulong linear;
3104
9dac77fa 3105 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3106 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3107 ctxt->ops->invlpg(ctxt, linear);
38503911 3108 /* Disable writeback. */
9dac77fa 3109 ctxt->dst.type = OP_NONE;
38503911
AK		 3110 return X86EMUL_CONTINUE;
3111}
3112
2d04a05b
AK		 3113static int em_clts(struct x86_emulate_ctxt *ctxt)
3114{
3115 ulong cr0;
3116
3117 cr0 = ctxt->ops->get_cr(ctxt, 0);
3118 cr0 &= ~X86_CR0_TS;
3119 ctxt->ops->set_cr(ctxt, 0, cr0);
3120 return X86EMUL_CONTINUE;
3121}
3122
26d05cc7
AK		 3123static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3124{
26d05cc7
AK		 3125 int rc;
3126
9dac77fa 3127 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3128 return X86EMUL_UNHANDLEABLE;
3129
3130 rc = ctxt->ops->fix_hypercall(ctxt);
3131 if (rc != X86EMUL_CONTINUE)
3132 return rc;
3133
3134 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3135 ctxt->_eip = ctxt->eip;
26d05cc7 3136 /* Disable writeback. */
9dac77fa 3137 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3138 return X86EMUL_CONTINUE;
3139}
3140
96051572
AK		 3141static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3142 void (*get)(struct x86_emulate_ctxt *ctxt,
3143 struct desc_ptr *ptr))
3144{
3145 struct desc_ptr desc_ptr;
3146
3147 if (ctxt->mode == X86EMUL_MODE_PROT64)
3148 ctxt->op_bytes = 8;
3149 get(ctxt, &desc_ptr);
3150 if (ctxt->op_bytes == 2) {
3151 ctxt->op_bytes = 4;
3152 desc_ptr.address &= 0x00ffffff;
3153 }
3154 /* Disable writeback. */
3155 ctxt->dst.type = OP_NONE;
3156 return segmented_write(ctxt, ctxt->dst.addr.mem,
3157 &desc_ptr, 2 + ctxt->op_bytes);
3158}
3159
3160static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3161{
3162 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3163}
3164
3165static int em_sidt(struct x86_emulate_ctxt *ctxt)
3166{
3167 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3168}
3169
26d05cc7
AK		 3170static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3171{
26d05cc7
AK		 3172 struct desc_ptr desc_ptr;
3173 int rc;
3174
510425ff
AK		 3175 if (ctxt->mode == X86EMUL_MODE_PROT64)
3176 ctxt->op_bytes = 8;
9dac77fa 3177 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3178 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3179 ctxt->op_bytes);
26d05cc7
AK		 3180 if (rc != X86EMUL_CONTINUE)
3181 return rc;
3182 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3183 /* Disable writeback. */
9dac77fa 3184 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3185 return X86EMUL_CONTINUE;
3186}
3187
5ef39c71 3188static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3189{
26d05cc7
AK		 3190 int rc;
3191
5ef39c71
AK		 3192 rc = ctxt->ops->fix_hypercall(ctxt);
3193
26d05cc7 3194 /* Disable writeback. */
9dac77fa 3195 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3196 return rc;
3197}
3198
3199static int em_lidt(struct x86_emulate_ctxt *ctxt)
3200{
26d05cc7
AK		 3201 struct desc_ptr desc_ptr;
3202 int rc;
3203
510425ff
AK		 3204 if (ctxt->mode == X86EMUL_MODE_PROT64)
3205 ctxt->op_bytes = 8;
9dac77fa 3206 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3207 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3208 ctxt->op_bytes);
26d05cc7
AK		 3209 if (rc != X86EMUL_CONTINUE)
3210 return rc;
3211 ctxt->ops->set_idt(ctxt, &desc_ptr);
3212 /* Disable writeback. */
9dac77fa 3213 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3214 return X86EMUL_CONTINUE;
3215}
3216
3217static int em_smsw(struct x86_emulate_ctxt *ctxt)
3218{
9dac77fa
AK		 3219 ctxt->dst.bytes = 2;
3220 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3221 return X86EMUL_CONTINUE;
3222}
3223
3224static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3225{
26d05cc7 3226 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3227 | (ctxt->src.val & 0x0f));
3228 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3229 return X86EMUL_CONTINUE;
3230}
3231
d06e03ad
TY		 3232static int em_loop(struct x86_emulate_ctxt *ctxt)
3233{
dd856efa
AK		 3234 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3235 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3236 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3237 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3238
3239 return X86EMUL_CONTINUE;
3240}
3241
3242static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3243{
dd856efa 3244 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3245 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3246
3247 return X86EMUL_CONTINUE;
3248}
3249
d7841a4b
TY		 3250static int em_in(struct x86_emulate_ctxt *ctxt)
3251{
3252 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3253 &ctxt->dst.val))
3254 return X86EMUL_IO_NEEDED;
3255
3256 return X86EMUL_CONTINUE;
3257}
3258
3259static int em_out(struct x86_emulate_ctxt *ctxt)
3260{
3261 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3262 &ctxt->src.val, 1);
3263 /* Disable writeback. */
3264 ctxt->dst.type = OP_NONE;
3265 return X86EMUL_CONTINUE;
3266}
3267
f411e6cd
TY		 3268static int em_cli(struct x86_emulate_ctxt *ctxt)
3269{
3270 if (emulator_bad_iopl(ctxt))
3271 return emulate_gp(ctxt, 0);
3272
3273 ctxt->eflags &= ~X86_EFLAGS_IF;
3274 return X86EMUL_CONTINUE;
3275}
3276
3277static int em_sti(struct x86_emulate_ctxt *ctxt)
3278{
3279 if (emulator_bad_iopl(ctxt))
3280 return emulate_gp(ctxt, 0);
3281
3282 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3283 ctxt->eflags |= X86_EFLAGS_IF;
3284 return X86EMUL_CONTINUE;
3285}
3286
ce7faab2
TY		 3287static int em_bt(struct x86_emulate_ctxt *ctxt)
3288{
3289 /* Disable writeback. */
3290 ctxt->dst.type = OP_NONE;
3291 /* only subword offset */
3292 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3293
3294 emulate_2op_SrcV_nobyte(ctxt, "bt");
3295 return X86EMUL_CONTINUE;
3296}
3297
3298static int em_bts(struct x86_emulate_ctxt *ctxt)
3299{
3300 emulate_2op_SrcV_nobyte(ctxt, "bts");
3301 return X86EMUL_CONTINUE;
3302}
3303
3304static int em_btr(struct x86_emulate_ctxt *ctxt)
3305{
3306 emulate_2op_SrcV_nobyte(ctxt, "btr");
3307 return X86EMUL_CONTINUE;
3308}
3309
3310static int em_btc(struct x86_emulate_ctxt *ctxt)
3311{
3312 emulate_2op_SrcV_nobyte(ctxt, "btc");
3313 return X86EMUL_CONTINUE;
3314}
3315
ff227392
TY		 3316static int em_bsf(struct x86_emulate_ctxt *ctxt)
3317{
d54e4237 3318 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3319 return X86EMUL_CONTINUE;
3320}
3321
3322static int em_bsr(struct x86_emulate_ctxt *ctxt)
3323{
d54e4237 3324 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3325 return X86EMUL_CONTINUE;
3326}
3327
6d6eede4
AK		 3328static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3329{
3330 u32 eax, ebx, ecx, edx;
3331
dd856efa
AK		 3332 eax = reg_read(ctxt, VCPU_REGS_RAX);
3333 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3334 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3335 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3336 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3337 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3338 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3339 return X86EMUL_CONTINUE;
3340}
3341
2dd7caa0
AK		 3342static int em_lahf(struct x86_emulate_ctxt *ctxt)
3343{
dd856efa
AK		 3344 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3345 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3346 return X86EMUL_CONTINUE;
3347}
3348
9299836e
AK		 3349static int em_bswap(struct x86_emulate_ctxt *ctxt)
3350{
3351 switch (ctxt->op_bytes) {
3352#ifdef CONFIG_X86_64
3353 case 8:
3354 asm("bswap %0" : "+r"(ctxt->dst.val));
3355 break;
3356#endif
3357 default:
3358 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3359 break;
3360 }
3361 return X86EMUL_CONTINUE;
3362}
3363
cfec82cb
JR		 3364static bool valid_cr(int nr)
3365{
3366 switch (nr) {
3367 case 0:
3368 case 2 ... 4:
3369 case 8:
3370 return true;
3371 default:
3372 return false;
3373 }
3374}
3375
3376static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3377{
9dac77fa 3378 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3379 return emulate_ud(ctxt);
3380
3381 return X86EMUL_CONTINUE;
3382}
3383
3384static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3385{
9dac77fa
AK		 3386 u64 new_val = ctxt->src.val64;
3387 int cr = ctxt->modrm_reg;
c2ad2bb3 3388 u64 efer = 0;
cfec82cb
JR		 3389
3390 static u64 cr_reserved_bits[] = {
3391 0xffffffff00000000ULL,
3392 0, 0, 0, /* CR3 checked later */
3393 CR4_RESERVED_BITS,
3394 0, 0, 0,
3395 CR8_RESERVED_BITS,
3396 };
3397
3398 if (!valid_cr(cr))
3399 return emulate_ud(ctxt);
3400
3401 if (new_val & cr_reserved_bits[cr])
3402 return emulate_gp(ctxt, 0);
3403
3404 switch (cr) {
3405 case 0: {
c2ad2bb3 3406 u64 cr4;
cfec82cb
JR		 3407 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3408 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3409 return emulate_gp(ctxt, 0);
3410
717746e3
AK		 3411 cr4 = ctxt->ops->get_cr(ctxt, 4);
3412 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3413
3414 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3415 !(cr4 & X86_CR4_PAE))
3416 return emulate_gp(ctxt, 0);
3417
3418 break;
3419 }
3420 case 3: {
3421 u64 rsvd = 0;
3422
c2ad2bb3
AK		 3423 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3424 if (efer & EFER_LMA)
cfec82cb 3425 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3426 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3427 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3428 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3429 rsvd = CR3_NONPAE_RESERVED_BITS;
3430
3431 if (new_val & rsvd)
3432 return emulate_gp(ctxt, 0);
3433
3434 break;
3435 }
3436 case 4: {
717746e3 3437 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3438
3439 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3440 return emulate_gp(ctxt, 0);
3441
3442 break;
3443 }
3444 }
3445
3446 return X86EMUL_CONTINUE;
3447}
3448
3b88e41a
JR		 3449static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3450{
3451 unsigned long dr7;
3452
717746e3 3453 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3454
3455 /* Check if DR7.Global_Enable is set */
3456 return dr7 & (1 << 13);
3457}
3458
3459static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3460{
9dac77fa 3461 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3462 u64 cr4;
3463
3464 if (dr > 7)
3465 return emulate_ud(ctxt);
3466
717746e3 3467 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3468 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3469 return emulate_ud(ctxt);
3470
3471 if (check_dr7_gd(ctxt))
3472 return emulate_db(ctxt);
3473
3474 return X86EMUL_CONTINUE;
3475}
3476
3477static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3478{
9dac77fa
AK		 3479 u64 new_val = ctxt->src.val64;
3480 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3481
3482 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3483 return emulate_gp(ctxt, 0);
3484
3485 return check_dr_read(ctxt);
3486}
3487
01de8b09
JR		 3488static int check_svme(struct x86_emulate_ctxt *ctxt)
3489{
3490 u64 efer;
3491
717746e3 3492 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3493
3494 if (!(efer & EFER_SVME))
3495 return emulate_ud(ctxt);
3496
3497 return X86EMUL_CONTINUE;
3498}
3499
3500static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3501{
dd856efa 3502 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3503
3504 /* Valid physical address? */
d4224449 3505 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3506 return emulate_gp(ctxt, 0);
3507
3508 return check_svme(ctxt);
3509}
3510
d7eb8203
JR		 3511static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3512{
717746e3 3513 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3514
717746e3 3515 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3516 return emulate_ud(ctxt);
3517
3518 return X86EMUL_CONTINUE;
3519}
3520
8061252e
JR		 3521static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3522{
717746e3 3523 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3524 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3525
717746e3 3526 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3527 (rcx > 3))
3528 return emulate_gp(ctxt, 0);
3529
3530 return X86EMUL_CONTINUE;
3531}
3532
f6511935
JR		 3533static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3534{
9dac77fa
AK		 3535 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3536 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3537 return emulate_gp(ctxt, 0);
3538
3539 return X86EMUL_CONTINUE;
3540}
3541
3542static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3543{
9dac77fa
AK		 3544 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3545 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3546 return emulate_gp(ctxt, 0);
3547
3548 return X86EMUL_CONTINUE;
3549}
3550
73fba5f4 3551#define D(_y) { .flags = (_y) }
c4f035c6 3552#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3553#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3554 .check_perm = (_p) }
73fba5f4 3555#define N D(0)
01de8b09 3556#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3557#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3558#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3559#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3560#define II(_f, _e, _i) \
3561 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3562#define IIP(_f, _e, _i, _p) \
3563 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3564 .check_perm = (_p) }
aa97bb48 3565#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3566
8d8f4e9f 3567#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3568#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3569#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3570#define I2bvIP(_f, _e, _i, _p) \
3571 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3572
d67fc27a
TY		 3573#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3574 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3575 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3576
d7eb8203 3577static struct opcode group7_rm1[] = {
1c2545be
TY		 3578 DI(SrcNone | Priv, monitor),
3579 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3580 N, N, N, N, N, N,
3581};
3582
01de8b09 3583static struct opcode group7_rm3[] = {
1c2545be
TY		 3584 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3585 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3586 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3587 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3588 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3589 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3590 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3591 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3592};
6230f7fc 3593
d7eb8203
JR		 3594static struct opcode group7_rm7[] = {
3595 N,
1c2545be 3596 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3597 N, N, N, N, N, N,
3598};
d67fc27a 3599
73fba5f4 3600static struct opcode group1[] = {
d67fc27a 3601 I(Lock, em_add),
d5ae7ce8 3602 I(Lock | PageTable, em_or),
d67fc27a
TY		 3603 I(Lock, em_adc),
3604 I(Lock, em_sbb),
d5ae7ce8 3605 I(Lock | PageTable, em_and),
d67fc27a
TY		 3606 I(Lock, em_sub),
3607 I(Lock, em_xor),
3608 I(0, em_cmp),
73fba5f4
AK		 3609};
3610
3611static struct opcode group1A[] = {
1c2545be 3612 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3613};
3614
3615static struct opcode group3[] = {
1c2545be
TY		 3616 I(DstMem | SrcImm, em_test),
3617 I(DstMem | SrcImm, em_test),
3618 I(DstMem | SrcNone | Lock, em_not),
3619 I(DstMem | SrcNone | Lock, em_neg),
3620 I(SrcMem, em_mul_ex),
3621 I(SrcMem, em_imul_ex),
3622 I(SrcMem, em_div_ex),
3623 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3624};
3625
3626static struct opcode group4[] = {
1c2545be
TY		 3627 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3628 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3629 N, N, N, N, N, N,
3630};
3631
3632static struct opcode group5[] = {
1c2545be
TY		 3633 I(DstMem | SrcNone | Lock, em_grp45),
3634 I(DstMem | SrcNone | Lock, em_grp45),
3635 I(SrcMem | Stack, em_grp45),
3636 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3637 I(SrcMem | Stack, em_grp45),
3638 I(SrcMemFAddr | ImplicitOps, em_grp45),
3639 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3640};
3641
dee6bb70 3642static struct opcode group6[] = {
1c2545be
TY		 3643 DI(Prot, sldt),
3644 DI(Prot, str),
a14e579f 3645 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3646 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3647 N, N, N, N,
3648};
3649
73fba5f4 3650static struct group_dual group7 = { {
96051572
AK		 3651 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3652 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3653 II(SrcMem | Priv, em_lgdt, lgdt),
3654 II(SrcMem | Priv, em_lidt, lidt),
3655 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3656 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3657 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3658}, {
1c2545be 3659 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3660 EXT(0, group7_rm1),
01de8b09 3661 N, EXT(0, group7_rm3),
1c2545be
TY		 3662 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3663 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3664 EXT(0, group7_rm7),
73fba5f4
AK		 3665} };
3666
3667static struct opcode group8[] = {
3668 N, N, N, N,
1c2545be
TY		 3669 I(DstMem | SrcImmByte, em_bt),
3670 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3671 I(DstMem | SrcImmByte | Lock, em_btr),
3672 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3673};
3674
3675static struct group_dual group9 = { {
1c2545be 3676 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3677}, {
3678 N, N, N, N, N, N, N, N,
3679} };
3680
a4d4a7c1 3681static struct opcode group11[] = {
1c2545be 3682 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3683 X7(D(Undefined)),
a4d4a7c1
AK		 3684};
3685
aa97bb48 3686static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3687 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3688};
3689
3e114eb4
AK		 3690static struct gprefix pfx_vmovntpx = {
3691 I(0, em_mov), N, N, N,
3692};
3693
73fba5f4
AK		 3694static struct opcode opcode_table[256] = {
3695 /* 0x00 - 0x07 */
d67fc27a 3696 I6ALU(Lock, em_add),
1cd196ea
AK		 3697 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3698 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3699 /* 0x08 - 0x0F */
d5ae7ce8 3700 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3701 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3702 N,
73fba5f4 3703 /* 0x10 - 0x17 */
d67fc27a 3704 I6ALU(Lock, em_adc),
1cd196ea
AK		 3705 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3706 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3707 /* 0x18 - 0x1F */
d67fc27a 3708 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3709 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3710 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3711 /* 0x20 - 0x27 */
d5ae7ce8 3712 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3713 /* 0x28 - 0x2F */
d67fc27a 3714 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3715 /* 0x30 - 0x37 */
d67fc27a 3716 I6ALU(Lock, em_xor), N, N,
73fba5f4 3717 /* 0x38 - 0x3F */
d67fc27a 3718 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3719 /* 0x40 - 0x4F */
3720 X16(D(DstReg)),
3721 /* 0x50 - 0x57 */
63540382 3722 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3723 /* 0x58 - 0x5F */
c54fe504 3724 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3725 /* 0x60 - 0x67 */
b96a7fad
TY		 3726 I(ImplicitOps | Stack | No64, em_pusha),
3727 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3728 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3729 N, N, N, N,
3730 /* 0x68 - 0x6F */
d46164db
AK		 3731 I(SrcImm | Mov | Stack, em_push),
3732 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3733 I(SrcImmByte | Mov | Stack, em_push),
3734 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3735 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3736 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3737 /* 0x70 - 0x7F */
3738 X16(D(SrcImmByte)),
3739 /* 0x80 - 0x87 */
1c2545be
TY		 3740 G(ByteOp | DstMem | SrcImm, group1),
3741 G(DstMem | SrcImm, group1),
3742 G(ByteOp | DstMem | SrcImm | No64, group1),
3743 G(DstMem | SrcImmByte, group1),
9f21ca59 3744 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3745 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3746 /* 0x88 - 0x8F */
d5ae7ce8 3747 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3748 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3749 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3750 D(ModRM | SrcMem | NoAccess | DstReg),
3751 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3752 G(0, group1A),
73fba5f4 3753 /* 0x90 - 0x97 */
bf608f88 3754 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3755 /* 0x98 - 0x9F */
61429142 3756 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3757 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3758 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3759 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3760 /* 0xA0 - 0xA7 */
b9eac5f4 3761 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3762 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3763 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3764 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3765 /* 0xA8 - 0xAF */
9f21ca59 3766 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3767 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3768 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3769 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3770 /* 0xB0 - 0xB7 */
b9eac5f4 3771 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3772 /* 0xB8 - 0xBF */
b9eac5f4 3773 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3774 /* 0xC0 - 0xC7 */
d2c6c7ad 3775 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3776 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3777 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3778 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3779 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3780 G(ByteOp, group11), G(0, group11),
73fba5f4 3781 /* 0xC8 - 0xCF */
612e89f0
AK		 3782 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3783 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3784 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3785 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3786 /* 0xD0 - 0xD7 */
d2c6c7ad 3787 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3788 N, N, N, N,
3789 /* 0xD8 - 0xDF */
3790 N, N, N, N, N, N, N, N,
3791 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3792 X3(I(SrcImmByte, em_loop)),
3793 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3794 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3795 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3796 /* 0xE8 - 0xEF */
d4ddafcd 3797 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3798 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3799 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3800 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3801 /* 0xF0 - 0xF7 */
bf608f88 3802 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3803 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3804 G(ByteOp, group3), G(0, group3),
73fba5f4 3805 /* 0xF8 - 0xFF */
f411e6cd
TY		 3806 D(ImplicitOps), D(ImplicitOps),
3807 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3808 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3809};
3810
3811static struct opcode twobyte_table[256] = {
3812 /* 0x00 - 0x0F */
dee6bb70 3813 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3814 N, I(ImplicitOps | VendorSpecific, em_syscall),
3815 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3816 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3817 N, D(ImplicitOps | ModRM), N, N,
3818 /* 0x10 - 0x1F */
3819 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3820 /* 0x20 - 0x2F */
cfec82cb 3821 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3822 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3823 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3824 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3825 N, N, N, N,
3e114eb4
AK		 3826 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3827 N, N, N, N,
73fba5f4 3828 /* 0x30 - 0x3F */
e1e210b0 3829 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3830 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3831 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3832 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3833 I(ImplicitOps | VendorSpecific, em_sysenter),
3834 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3835 N, N,
73fba5f4
AK		 3836 N, N, N, N, N, N, N, N,
3837 /* 0x40 - 0x4F */
3838 X16(D(DstReg | SrcMem | ModRM | Mov)),
3839 /* 0x50 - 0x5F */
3840 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3841 /* 0x60 - 0x6F */
aa97bb48
AK		 3842 N, N, N, N,
3843 N, N, N, N,
3844 N, N, N, N,
3845 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3846 /* 0x70 - 0x7F */
aa97bb48
AK		 3847 N, N, N, N,
3848 N, N, N, N,
3849 N, N, N, N,
3850 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3851 /* 0x80 - 0x8F */
3852 X16(D(SrcImm)),
3853 /* 0x90 - 0x9F */
ee45b58e 3854 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3855 /* 0xA0 - 0xA7 */
1cd196ea 3856 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3857 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3858 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3859 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3860 /* 0xA8 - 0xAF */
1cd196ea 3861 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3862 DI(ImplicitOps, rsm),
ce7faab2 3863 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3864 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3865 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3866 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3867 /* 0xB0 - 0xB7 */
e940b5c2 3868 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3869 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3870 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3871 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3872 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3873 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3874 /* 0xB8 - 0xBF */
3875 N, N,
ce7faab2
TY		 3876 G(BitOp, group8),
3877 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3878 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3879 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3880 /* 0xC0 - 0xC7 */
739ae406 3881 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3882 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3883 N, N, N, GD(0, &group9),
9299836e
AK		 3884 /* 0xC8 - 0xCF */
3885 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3886 /* 0xD0 - 0xDF */
3887 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3888 /* 0xE0 - 0xEF */
3889 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3890 /* 0xF0 - 0xFF */
3891 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3892};
3893
3894#undef D
3895#undef N
3896#undef G
3897#undef GD
3898#undef I
aa97bb48 3899#undef GP
01de8b09 3900#undef EXT
73fba5f4 3901
8d8f4e9f 3902#undef D2bv
f6511935 3903#undef D2bvIP
8d8f4e9f 3904#undef I2bv
d7841a4b 3905#undef I2bvIP
d67fc27a 3906#undef I6ALU
8d8f4e9f 3907
9dac77fa 3908static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3909{
3910 unsigned size;
3911
9dac77fa 3912 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3913 if (size == 8)
3914 size = 4;
3915 return size;
3916}
3917
3918static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3919 unsigned size, bool sign_extension)
3920{
39f21ee5
AK		 3921 int rc = X86EMUL_CONTINUE;
3922
3923 op->type = OP_IMM;
3924 op->bytes = size;
9dac77fa 3925 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3926 /* NB. Immediates are sign-extended as necessary. */
3927 switch (op->bytes) {
3928 case 1:
e85a1085 3929 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3930 break;
3931 case 2:
e85a1085 3932 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3933 break;
3934 case 4:
e85a1085 3935 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3936 break;
3937 }
3938 if (!sign_extension) {
3939 switch (op->bytes) {
3940 case 1:
3941 op->val &= 0xff;
3942 break;
3943 case 2:
3944 op->val &= 0xffff;
3945 break;
3946 case 4:
3947 op->val &= 0xffffffff;
3948 break;
3949 }
3950 }
3951done:
3952 return rc;
3953}
3954
a9945549
AK		 3955static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3956 unsigned d)
3957{
3958 int rc = X86EMUL_CONTINUE;
3959
3960 switch (d) {
3961 case OpReg:
2adb5ad9 3962 decode_register_operand(ctxt, op);
a9945549
AK		 3963 break;
3964 case OpImmUByte:
608aabe3 3965 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3966 break;
3967 case OpMem:
41ddf978 3968 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3969 mem_common:
3970 *op = ctxt->memop;
3971 ctxt->memopp = op;
3972 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3973 fetch_bit_operand(ctxt);
3974 op->orig_val = op->val;
3975 break;
41ddf978
AK		 3976 case OpMem64:
3977 ctxt->memop.bytes = 8;
3978 goto mem_common;
a9945549
AK		 3979 case OpAcc:
3980 op->type = OP_REG;
3981 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 3982 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 3983 fetch_register_operand(op);
3984 op->orig_val = op->val;
3985 break;
3986 case OpDI:
3987 op->type = OP_MEM;
3988 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3989 op->addr.mem.ea =
dd856efa 3990 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 3991 op->addr.mem.seg = VCPU_SREG_ES;
3992 op->val = 0;
3993 break;
3994 case OpDX:
3995 op->type = OP_REG;
3996 op->bytes = 2;
dd856efa 3997 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 3998 fetch_register_operand(op);
3999 break;
4dd6a57d
AK		 4000 case OpCL:
4001 op->bytes = 1;
dd856efa 4002 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4003 break;
4004 case OpImmByte:
4005 rc = decode_imm(ctxt, op, 1, true);
4006 break;
4007 case OpOne:
4008 op->bytes = 1;
4009 op->val = 1;
4010 break;
4011 case OpImm:
4012 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4013 break;
28867cee
AK		 4014 case OpMem8:
4015 ctxt->memop.bytes = 1;
4016 goto mem_common;
0fe59128
AK		 4017 case OpMem16:
4018 ctxt->memop.bytes = 2;
4019 goto mem_common;
4020 case OpMem32:
4021 ctxt->memop.bytes = 4;
4022 goto mem_common;
4023 case OpImmU16:
4024 rc = decode_imm(ctxt, op, 2, false);
4025 break;
4026 case OpImmU:
4027 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4028 break;
4029 case OpSI:
4030 op->type = OP_MEM;
4031 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4032 op->addr.mem.ea =
dd856efa 4033 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4034 op->addr.mem.seg = seg_override(ctxt);
4035 op->val = 0;
4036 break;
4037 case OpImmFAddr:
4038 op->type = OP_IMM;
4039 op->addr.mem.ea = ctxt->_eip;
4040 op->bytes = ctxt->op_bytes + 2;
4041 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4042 break;
4043 case OpMemFAddr:
4044 ctxt->memop.bytes = ctxt->op_bytes + 2;
4045 goto mem_common;
c191a7a0
AK		 4046 case OpES:
4047 op->val = VCPU_SREG_ES;
4048 break;
4049 case OpCS:
4050 op->val = VCPU_SREG_CS;
4051 break;
4052 case OpSS:
4053 op->val = VCPU_SREG_SS;
4054 break;
4055 case OpDS:
4056 op->val = VCPU_SREG_DS;
4057 break;
4058 case OpFS:
4059 op->val = VCPU_SREG_FS;
4060 break;
4061 case OpGS:
4062 op->val = VCPU_SREG_GS;
4063 break;
a9945549
AK		 4064 case OpImplicit:
4065 /* Special instructions do their own operand decoding. */
4066 default:
4067 op->type = OP_NONE; /* Disable writeback. */
4068 break;
4069 }
4070
4071done:
4072 return rc;
4073}
4074
ef5d75cc 4075int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4076{
dde7e6d1
AK		 4077 int rc = X86EMUL_CONTINUE;
4078 int mode = ctxt->mode;
46561646 4079 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4080 bool op_prefix = false;
46561646 4081 struct opcode opcode;
dde7e6d1 4082
f09ed83e
AK		 4083 ctxt->memop.type = OP_NONE;
4084 ctxt->memopp = NULL;
9dac77fa
AK		 4085 ctxt->_eip = ctxt->eip;
4086 ctxt->fetch.start = ctxt->_eip;
4087 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4088 if (insn_len > 0)
9dac77fa 4089 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4090
4091 switch (mode) {
4092 case X86EMUL_MODE_REAL:
4093 case X86EMUL_MODE_VM86:
4094 case X86EMUL_MODE_PROT16:
4095 def_op_bytes = def_ad_bytes = 2;
4096 break;
4097 case X86EMUL_MODE_PROT32:
4098 def_op_bytes = def_ad_bytes = 4;
4099 break;
4100#ifdef CONFIG_X86_64
4101 case X86EMUL_MODE_PROT64:
4102 def_op_bytes = 4;
4103 def_ad_bytes = 8;
4104 break;
4105#endif
4106 default:
1d2887e2 4107 return EMULATION_FAILED;
dde7e6d1
AK		 4108 }
4109
9dac77fa
AK		 4110 ctxt->op_bytes = def_op_bytes;
4111 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4112
4113 /* Legacy prefixes. */
4114 for (;;) {
e85a1085 4115 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4116 case 0x66: /* operand-size override */
0d7cdee8 4117 op_prefix = true;
dde7e6d1 4118 /* switch between 2/4 bytes */
9dac77fa 4119 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4120 break;
4121 case 0x67: /* address-size override */
4122 if (mode == X86EMUL_MODE_PROT64)
4123 /* switch between 4/8 bytes */
9dac77fa 4124 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4125 else
4126 /* switch between 2/4 bytes */
9dac77fa 4127 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4128 break;
4129 case 0x26: /* ES override */
4130 case 0x2e: /* CS override */
4131 case 0x36: /* SS override */
4132 case 0x3e: /* DS override */
9dac77fa 4133 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4134 break;
4135 case 0x64: /* FS override */
4136 case 0x65: /* GS override */
9dac77fa 4137 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4138 break;
4139 case 0x40 ... 0x4f: /* REX */
4140 if (mode != X86EMUL_MODE_PROT64)
4141 goto done_prefixes;
9dac77fa 4142 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4143 continue;
4144 case 0xf0: /* LOCK */
9dac77fa 4145 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4146 break;
4147 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4148 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4149 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4150 break;
4151 default:
4152 goto done_prefixes;
4153 }
4154
4155 /* Any legacy prefix after a REX prefix nullifies its effect. */
4156
9dac77fa 4157 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4158 }
4159
4160done_prefixes:
4161
4162 /* REX prefix. */
9dac77fa
AK		 4163 if (ctxt->rex_prefix & 8)
4164 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4165
4166 /* Opcode byte(s). */
9dac77fa 4167 opcode = opcode_table[ctxt->b];
d3ad6243 4168 /* Two-byte opcode? */
9dac77fa
AK		 4169 if (ctxt->b == 0x0f) {
4170 ctxt->twobyte = 1;
e85a1085 4171 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4172 opcode = twobyte_table[ctxt->b];
dde7e6d1 4173 }
9dac77fa 4174 ctxt->d = opcode.flags;
dde7e6d1 4175
9f4260e7
TY		 4176 if (ctxt->d & ModRM)
4177 ctxt->modrm = insn_fetch(u8, ctxt);
4178
9dac77fa
AK		 4179 while (ctxt->d & GroupMask) {
4180 switch (ctxt->d & GroupMask) {
46561646 4181 case Group:
9dac77fa 4182 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4183 opcode = opcode.u.group[goffset];
4184 break;
4185 case GroupDual:
9dac77fa
AK		 4186 goffset = (ctxt->modrm >> 3) & 7;
4187 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4188 opcode = opcode.u.gdual->mod3[goffset];
4189 else
4190 opcode = opcode.u.gdual->mod012[goffset];
4191 break;
4192 case RMExt:
9dac77fa 4193 goffset = ctxt->modrm & 7;
01de8b09 4194 opcode = opcode.u.group[goffset];
46561646
AK		 4195 break;
4196 case Prefix:
9dac77fa 4197 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4198 return EMULATION_FAILED;
9dac77fa 4199 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4200 switch (simd_prefix) {
4201 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4202 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4203 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4204 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4205 }
4206 break;
4207 default:
1d2887e2 4208 return EMULATION_FAILED;
0d7cdee8 4209 }
46561646 4210
b1ea50b2 4211 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4212 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4213 }
4214
9dac77fa
AK		 4215 ctxt->execute = opcode.u.execute;
4216 ctxt->check_perm = opcode.check_perm;
4217 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4218
4219 /* Unrecognised? */
9dac77fa 4220 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4221 return EMULATION_FAILED;
dde7e6d1 4222
9dac77fa 4223 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4224 return EMULATION_FAILED;
d867162c 4225
9dac77fa
AK		 4226 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4227 ctxt->op_bytes = 8;
dde7e6d1 4228
9dac77fa 4229 if (ctxt->d & Op3264) {
7f9b4b75 4230 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4231 ctxt->op_bytes = 8;
7f9b4b75 4232 else
9dac77fa 4233 ctxt->op_bytes = 4;
7f9b4b75
AK		 4234 }
4235
9dac77fa
AK		 4236 if (ctxt->d & Sse)
4237 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4238 else if (ctxt->d & Mmx)
4239 ctxt->op_bytes = 8;
1253791d 4240
dde7e6d1 4241 /* ModRM and SIB bytes. */
9dac77fa 4242 if (ctxt->d & ModRM) {
f09ed83e 4243 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4244 if (!ctxt->has_seg_override)
4245 set_seg_override(ctxt, ctxt->modrm_seg);
4246 } else if (ctxt->d & MemAbs)
f09ed83e 4247 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4248 if (rc != X86EMUL_CONTINUE)
4249 goto done;
4250
9dac77fa
AK		 4251 if (!ctxt->has_seg_override)
4252 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4253
f09ed83e 4254 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4255
f09ed83e
AK		 4256 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4257 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4258
dde7e6d1
AK		 4259 /*
4260 * Decode and fetch the source operand: register, memory
4261 * or immediate.
4262 */
0fe59128 4263 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4264 if (rc != X86EMUL_CONTINUE)
4265 goto done;
4266
dde7e6d1
AK		 4267 /*
4268 * Decode and fetch the second source operand: register, memory
4269 * or immediate.
4270 */
4dd6a57d 4271 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4272 if (rc != X86EMUL_CONTINUE)
4273 goto done;
4274
dde7e6d1 4275 /* Decode and fetch the destination operand: register or memory. */
a9945549 4276 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4277
4278done:
f09ed83e
AK		 4279 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4280 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4281
1d2887e2 4282 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4283}
4284
1cb3f3ae
XG		 4285bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4286{
4287 return ctxt->d & PageTable;
4288}
4289
3e2f65d5
GN		 4290static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4291{
3e2f65d5
GN		 4292 /* The second termination condition only applies for REPE
4293 * and REPNE. Test if the repeat string operation prefix is
4294 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4295 * corresponding termination condition according to:
4296 * - if REPE/REPZ and ZF = 0 then done
4297 * - if REPNE/REPNZ and ZF = 1 then done
4298 */
9dac77fa
AK		 4299 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4300 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4301 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4302 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4303 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4304 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4305 return true;
4306
4307 return false;
4308}
4309
cbe2c9d3
AK		 4310static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4311{
4312 bool fault = false;
4313
4314 ctxt->ops->get_fpu(ctxt);
4315 asm volatile("1: fwait \n\t"
4316 "2: \n\t"
4317 ".pushsection .fixup,\"ax\" \n\t"
4318 "3: \n\t"
4319 "movb $1, %[fault] \n\t"
4320 "jmp 2b \n\t"
4321 ".popsection \n\t"
4322 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4323 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4324 ctxt->ops->put_fpu(ctxt);
4325
4326 if (unlikely(fault))
4327 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4328
4329 return X86EMUL_CONTINUE;
4330}
4331
4332static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4333 struct operand *op)
4334{
4335 if (op->type == OP_MM)
4336 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4337}
4338
dd856efa 4339
7b105ca2 4340int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4341{
9aabc88f 4342 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4343 int rc = X86EMUL_CONTINUE;
9dac77fa 4344 int saved_dst_type = ctxt->dst.type;
8b4caf66 4345
9dac77fa 4346 ctxt->mem_read.pos = 0;
310b5d30 4347
9dac77fa 4348 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4349 rc = emulate_ud(ctxt);
1161624f
GN		 4350 goto done;
4351 }
4352
d380a5e4 4353 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4354 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4355 rc = emulate_ud(ctxt);
d380a5e4
GN		 4356 goto done;
4357 }
4358
9dac77fa 4359 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4360 rc = emulate_ud(ctxt);
081bca0e
AK		 4361 goto done;
4362 }
4363
cbe2c9d3
AK		 4364 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4365 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4366 rc = emulate_ud(ctxt);
4367 goto done;
4368 }
4369
cbe2c9d3 4370 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4371 rc = emulate_nm(ctxt);
4372 goto done;
4373 }
4374
cbe2c9d3
AK		 4375 if (ctxt->d & Mmx) {
4376 rc = flush_pending_x87_faults(ctxt);
4377 if (rc != X86EMUL_CONTINUE)
4378 goto done;
4379 /*
4380 * Now that we know the fpu is exception safe, we can fetch
4381 * operands from it.
4382 */
4383 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4384 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4385 if (!(ctxt->d & Mov))
4386 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4387 }
4388
9dac77fa
AK		 4389 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4390 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4391 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4392 if (rc != X86EMUL_CONTINUE)
4393 goto done;
4394 }
4395
e92805ac 4396 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4397 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4398 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4399 goto done;
4400 }
4401
8ea7d6ae 4402 /* Instruction can only be executed in protected mode */
9dac77fa 4403 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4404 rc = emulate_ud(ctxt);
4405 goto done;
4406 }
4407
d09beabd 4408 /* Do instruction specific permission checks */
9dac77fa
AK		 4409 if (ctxt->check_perm) {
4410 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4411 if (rc != X86EMUL_CONTINUE)
4412 goto done;
4413 }
4414
9dac77fa
AK		 4415 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4416 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4417 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4418 if (rc != X86EMUL_CONTINUE)
4419 goto done;
4420 }
4421
9dac77fa 4422 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4423 /* All REP prefixes have the same first termination condition */
dd856efa 4424 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4425 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4426 goto done;
4427 }
b9fa9d6b
AK		 4428 }
4429
9dac77fa
AK		 4430 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4431 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4432 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4433 if (rc != X86EMUL_CONTINUE)
8b4caf66 4434 goto done;
9dac77fa 4435 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4436 }
4437
9dac77fa
AK		 4438 if (ctxt->src2.type == OP_MEM) {
4439 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4440 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4441 if (rc != X86EMUL_CONTINUE)
4442 goto done;
4443 }
4444
9dac77fa 4445 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4446 goto special_insn;
4447
4448
9dac77fa 4449 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4450 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4451 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4452 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4453 if (rc != X86EMUL_CONTINUE)
4454 goto done;
038e51de 4455 }
9dac77fa 4456 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4457
018a98db
AK		 4458special_insn:
4459
9dac77fa
AK		 4460 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4461 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4462 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4463 if (rc != X86EMUL_CONTINUE)
4464 goto done;
4465 }
4466
9dac77fa
AK		 4467 if (ctxt->execute) {
4468 rc = ctxt->execute(ctxt);
ef65c889
AK		 4469 if (rc != X86EMUL_CONTINUE)
4470 goto done;
4471 goto writeback;
4472 }
4473
9dac77fa 4474 if (ctxt->twobyte)
6aa8b732
AK		 4475 goto twobyte_insn;
4476
9dac77fa 4477 switch (ctxt->b) {
33615aa9 4478 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4479 emulate_1op(ctxt, "inc");
33615aa9
AK		 4480 break;
4481 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4482 emulate_1op(ctxt, "dec");
33615aa9 4483 break;
6aa8b732 4484 case 0x63: /* movsxd */
8b4caf66 4485 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4486 goto cannot_emulate;
9dac77fa 4487 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4488 break;
b2833e3c 4489 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4490 if (test_cc(ctxt->b, ctxt->eflags))
4491 jmp_rel(ctxt, ctxt->src.val);
018a98db 4492 break;
7e0b54b1 4493 case 0x8d: /* lea r16/r32, m */
9dac77fa 4494 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4495 break;
3d9e77df 4496 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4497 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4498 break;
e4f973ae
TY		 4499 rc = em_xchg(ctxt);
4500 break;
e8b6fa70 4501 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4502 switch (ctxt->op_bytes) {
4503 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4504 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4505 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4506 }
4507 break;
018a98db 4508 case 0xc0 ... 0xc1:
51187683 4509 rc = em_grp2(ctxt);
018a98db 4510 break;
6e154e56 4511 case 0xcc: /* int3 */
5c5df76b
TY		 4512 rc = emulate_int(ctxt, 3);
4513 break;
6e154e56 4514 case 0xcd: /* int n */
9dac77fa 4515 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4516 break;
4517 case 0xce: /* into */
5c5df76b
TY		 4518 if (ctxt->eflags & EFLG_OF)
4519 rc = emulate_int(ctxt, 4);
6e154e56 4520 break;
018a98db 4521 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4522 rc = em_grp2(ctxt);
018a98db
AK		 4523 break;
4524 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4525 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4526 rc = em_grp2(ctxt);
018a98db 4527 break;
1a52e051 4528 case 0xe9: /* jmp rel */
db5b0762 4529 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4530 jmp_rel(ctxt, ctxt->src.val);
4531 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4532 break;
111de5d6 4533 case 0xf4: /* hlt */
6c3287f7 4534 ctxt->ops->halt(ctxt);
19fdfa0d 4535 break;
111de5d6
AK		 4536 case 0xf5: /* cmc */
4537 /* complement carry flag from eflags reg */
4538 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4539 break;
4540 case 0xf8: /* clc */
4541 ctxt->eflags &= ~EFLG_CF;
111de5d6 4542 break;
8744aa9a
MG		 4543 case 0xf9: /* stc */
4544 ctxt->eflags |= EFLG_CF;
4545 break;
fb4616f4
MG		 4546 case 0xfc: /* cld */
4547 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4548 break;
4549 case 0xfd: /* std */
4550 ctxt->eflags |= EFLG_DF;
fb4616f4 4551 break;
91269b8f
AK		 4552 default:
4553 goto cannot_emulate;
6aa8b732 4554 }
018a98db 4555
7d9ddaed
AK		 4556 if (rc != X86EMUL_CONTINUE)
4557 goto done;
4558
018a98db 4559writeback:
adddcecf 4560 rc = writeback(ctxt);
1b30eaa8 4561 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4562 goto done;
4563
5cd21917
GN		 4564 /*
4565 * restore dst type in case the decoding will be reused
4566 * (happens for string instruction )
4567 */
9dac77fa 4568 ctxt->dst.type = saved_dst_type;
5cd21917 4569
9dac77fa
AK		 4570 if ((ctxt->d & SrcMask) == SrcSI)
4571 string_addr_inc(ctxt, seg_override(ctxt),
4572 VCPU_REGS_RSI, &ctxt->src);
a682e354 4573
9dac77fa 4574 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4575 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4576 &ctxt->dst);
d9271123 4577
9dac77fa
AK		 4578 if (ctxt->rep_prefix && (ctxt->d & String)) {
4579 struct read_cache *r = &ctxt->io_read;
dd856efa 4580 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3e2f65d5 4581
d2ddd1c4
GN		 4582 if (!string_insn_completed(ctxt)) {
4583 /*
4584 * Re-enter guest when pio read ahead buffer is empty
4585 * or, if it is not used, after each 1024 iteration.
4586 */
dd856efa 4587 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4588 (r->end == 0 || r->end != r->pos)) {
4589 /*
4590 * Reset read cache. Usually happens before
4591 * decode, but since instruction is restarted
4592 * we have to do it here.
4593 */
9dac77fa 4594 ctxt->mem_read.end = 0;
dd856efa 4595 writeback_registers(ctxt);
d2ddd1c4
GN		 4596 return EMULATION_RESTART;
4597 }
4598 goto done; /* skip rip writeback */
0fa6ccbd 4599 }
5cd21917 4600 }
d2ddd1c4 4601
9dac77fa 4602 ctxt->eip = ctxt->_eip;
018a98db
AK		 4603
4604done:
da9cb575
AK		 4605 if (rc == X86EMUL_PROPAGATE_FAULT)
4606 ctxt->have_exception = true;
775fde86
JR		 4607 if (rc == X86EMUL_INTERCEPTED)
4608 return EMULATION_INTERCEPTED;
4609
dd856efa
AK		 4610 if (rc == X86EMUL_CONTINUE)
4611 writeback_registers(ctxt);
4612
d2ddd1c4 4613 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4614
4615twobyte_insn:
9dac77fa 4616 switch (ctxt->b) {
018a98db 4617 case 0x09: /* wbinvd */
cfb22375 4618 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4619 break;
4620 case 0x08: /* invd */
018a98db
AK		 4621 case 0x0d: /* GrpP (prefetch) */
4622 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4623 break;
4624 case 0x20: /* mov cr, reg */
9dac77fa 4625 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4626 break;
6aa8b732 4627 case 0x21: /* mov from dr to reg */
9dac77fa 4628 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4629 break;
6aa8b732 4630 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4631 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4632 if (!test_cc(ctxt->b, ctxt->eflags))
4633 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4634 break;
b2833e3c 4635 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4636 if (test_cc(ctxt->b, ctxt->eflags))
4637 jmp_rel(ctxt, ctxt->src.val);
018a98db 4638 break;
ee45b58e 4639 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4640 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4641 break;
9bf8ea42
GT		 4642 case 0xa4: /* shld imm8, r, r/m */
4643 case 0xa5: /* shld cl, r, r/m */
761441b9 4644 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4645 break;
9bf8ea42
GT		 4646 case 0xac: /* shrd imm8, r, r/m */
4647 case 0xad: /* shrd cl, r, r/m */
761441b9 4648 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4649 break;
2a7c5b8b
GC		 4650 case 0xae: /* clflush */
4651 break;
6aa8b732 4652 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4653 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4654 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4655 : (u16) ctxt->src.val;
6aa8b732 4656 break;
6aa8b732 4657 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4658 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4659 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4660 (s16) ctxt->src.val;
6aa8b732 4661 break;
92f738a5 4662 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4663 emulate_2op_SrcV(ctxt, "add");
92f738a5 4664 /* Write back the register source. */
9dac77fa
AK		 4665 ctxt->src.val = ctxt->dst.orig_val;
4666 write_register_operand(&ctxt->src);
92f738a5 4667 break;
a012e65a 4668 case 0xc3: /* movnti */
9dac77fa
AK		 4669 ctxt->dst.bytes = ctxt->op_bytes;
4670 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4671 (u64) ctxt->src.val;
a012e65a 4672 break;
91269b8f
AK		 4673 default:
4674 goto cannot_emulate;
6aa8b732 4675 }
7d9ddaed
AK		 4676
4677 if (rc != X86EMUL_CONTINUE)
4678 goto done;
4679
6aa8b732
AK		 4680 goto writeback;
4681
4682cannot_emulate:
a0c0ab2f 4683 return EMULATION_FAILED;
6aa8b732 4684}
dd856efa
AK		 4685
4686void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4687{
4688 invalidate_registers(ctxt);
4689}
4690
4691void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4692{
4693 writeback_registers(ctxt);
4694}
Linux kernel - Deliverables
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