Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
6aa8b732 AK |
31 | /* |
32 | * Opcode effective-address decode tables. | |
33 | * Note that we only emulate instructions that have at least one memory | |
34 | * operand (excluding implicit stack references). We assume that stack | |
35 | * references and instruction fetches will never occur in special memory | |
36 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
37 | * not be handled. | |
38 | */ | |
39 | ||
40 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 41 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 42 | /* Destination operand type. */ |
ab85b12b AK |
43 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
44 | #define DstReg (2<<1) /* Register operand. */ | |
45 | #define DstMem (3<<1) /* Memory operand. */ | |
46 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
47 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
48 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 49 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 50 | #define DstMask (7<<1) |
6aa8b732 | 51 | /* Source operand type. */ |
9c9fddd0 | 52 | #define SrcNone (0<<4) /* No source operand. */ |
9c9fddd0 GT |
53 | #define SrcReg (1<<4) /* Register operand. */ |
54 | #define SrcMem (2<<4) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<4) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 59 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 60 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 61 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 62 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
63 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
64 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 65 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
b250e605 | 66 | #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */ |
341de7e3 | 67 | #define SrcMask (0xf<<4) |
6aa8b732 | 68 | /* Generic ModRM decode. */ |
341de7e3 | 69 | #define ModRM (1<<8) |
6aa8b732 | 70 | /* Destination is only written; never read. */ |
341de7e3 GN |
71 | #define Mov (1<<9) |
72 | #define BitOp (1<<10) | |
73 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
74 | #define String (1<<12) /* String instruction (rep capable) */ |
75 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
76 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
77 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
0d7cdee8 | 78 | #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */ |
1253791d | 79 | #define Sse (1<<17) /* SSE Vector instruction */ |
01de8b09 | 80 | #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */ |
d8769fed | 81 | /* Misc flags */ |
8ea7d6ae | 82 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 83 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 84 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 85 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 86 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 87 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 88 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 89 | #define No64 (1<<28) |
0dc8d10f GT |
90 | /* Source 2 operand type */ |
91 | #define Src2None (0<<29) | |
92 | #define Src2CL (1<<29) | |
93 | #define Src2ImmByte (2<<29) | |
94 | #define Src2One (3<<29) | |
7db41eb7 | 95 | #define Src2Imm (4<<29) |
0dc8d10f | 96 | #define Src2Mask (7<<29) |
6aa8b732 | 97 | |
d0e53325 AK |
98 | #define X2(x...) x, x |
99 | #define X3(x...) X2(x), x | |
100 | #define X4(x...) X2(x), X2(x) | |
101 | #define X5(x...) X4(x), x | |
102 | #define X6(x...) X4(x), X2(x) | |
103 | #define X7(x...) X4(x), X3(x) | |
104 | #define X8(x...) X4(x), X4(x) | |
105 | #define X16(x...) X8(x), X8(x) | |
83babbca | 106 | |
d65b1dee AK |
107 | struct opcode { |
108 | u32 flags; | |
c4f035c6 | 109 | u8 intercept; |
120df890 | 110 | union { |
ef65c889 | 111 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
112 | struct opcode *group; |
113 | struct group_dual *gdual; | |
0d7cdee8 | 114 | struct gprefix *gprefix; |
120df890 | 115 | } u; |
d09beabd | 116 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
117 | }; |
118 | ||
119 | struct group_dual { | |
120 | struct opcode mod012[8]; | |
121 | struct opcode mod3[8]; | |
d65b1dee AK |
122 | }; |
123 | ||
0d7cdee8 AK |
124 | struct gprefix { |
125 | struct opcode pfx_no; | |
126 | struct opcode pfx_66; | |
127 | struct opcode pfx_f2; | |
128 | struct opcode pfx_f3; | |
129 | }; | |
130 | ||
6aa8b732 | 131 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
132 | #define EFLG_ID (1<<21) |
133 | #define EFLG_VIP (1<<20) | |
134 | #define EFLG_VIF (1<<19) | |
135 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
136 | #define EFLG_VM (1<<17) |
137 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
138 | #define EFLG_IOPL (3<<12) |
139 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
140 | #define EFLG_OF (1<<11) |
141 | #define EFLG_DF (1<<10) | |
b1d86143 | 142 | #define EFLG_IF (1<<9) |
d4c6a154 | 143 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
144 | #define EFLG_SF (1<<7) |
145 | #define EFLG_ZF (1<<6) | |
146 | #define EFLG_AF (1<<4) | |
147 | #define EFLG_PF (1<<2) | |
148 | #define EFLG_CF (1<<0) | |
149 | ||
62bd430e MG |
150 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
151 | #define EFLG_RESERVED_ONE_MASK 2 | |
152 | ||
6aa8b732 AK |
153 | /* |
154 | * Instruction emulation: | |
155 | * Most instructions are emulated directly via a fragment of inline assembly | |
156 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
157 | * any modified flags. | |
158 | */ | |
159 | ||
05b3e0c2 | 160 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
161 | #define _LO32 "k" /* force 32-bit operand */ |
162 | #define _STK "%%rsp" /* stack pointer */ | |
163 | #elif defined(__i386__) | |
164 | #define _LO32 "" /* force 32-bit operand */ | |
165 | #define _STK "%%esp" /* stack pointer */ | |
166 | #endif | |
167 | ||
168 | /* | |
169 | * These EFLAGS bits are restored from saved value during emulation, and | |
170 | * any changes are written back to the saved value after emulation. | |
171 | */ | |
172 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
173 | ||
174 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
175 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
176 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
177 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
178 | "push %"_tmp"; " \ | |
179 | "push %"_tmp"; " \ | |
180 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
181 | "andl %"_LO32 _tmp",("_STK"); " \ | |
182 | "pushf; " \ | |
183 | "notl %"_LO32 _tmp"; " \ | |
184 | "andl %"_LO32 _tmp",("_STK"); " \ | |
185 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
186 | "pop %"_tmp"; " \ | |
187 | "orl %"_LO32 _tmp",("_STK"); " \ | |
188 | "popf; " \ | |
189 | "pop %"_sav"; " | |
6aa8b732 AK |
190 | |
191 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
192 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
193 | /* _sav |= EFLAGS & _msk; */ \ | |
194 | "pushf; " \ | |
195 | "pop %"_tmp"; " \ | |
196 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
197 | "orl %"_LO32 _tmp",%"_sav"; " | |
198 | ||
dda96d8f AK |
199 | #ifdef CONFIG_X86_64 |
200 | #define ON64(x) x | |
201 | #else | |
202 | #define ON64(x) | |
203 | #endif | |
204 | ||
b3b3d25a | 205 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
206 | do { \ |
207 | __asm__ __volatile__ ( \ | |
208 | _PRE_EFLAGS("0", "4", "2") \ | |
209 | _op _suffix " %"_x"3,%1; " \ | |
210 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 211 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
212 | "=&r" (_tmp) \ |
213 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 214 | } while (0) |
6b7ad61f AK |
215 | |
216 | ||
6aa8b732 AK |
217 | /* Raw emulation: instruction has two explicit operands. */ |
218 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
219 | do { \ |
220 | unsigned long _tmp; \ | |
221 | \ | |
222 | switch ((_dst).bytes) { \ | |
223 | case 2: \ | |
b3b3d25a | 224 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
225 | break; \ |
226 | case 4: \ | |
b3b3d25a | 227 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
228 | break; \ |
229 | case 8: \ | |
b3b3d25a | 230 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
231 | break; \ |
232 | } \ | |
6aa8b732 AK |
233 | } while (0) |
234 | ||
235 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
236 | do { \ | |
6b7ad61f | 237 | unsigned long _tmp; \ |
d77c26fc | 238 | switch ((_dst).bytes) { \ |
6aa8b732 | 239 | case 1: \ |
b3b3d25a | 240 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
241 | break; \ |
242 | default: \ | |
243 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
244 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
245 | break; \ | |
246 | } \ | |
247 | } while (0) | |
248 | ||
249 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
250 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
251 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
252 | "b", "c", "b", "c", "b", "c", "b", "c") | |
253 | ||
254 | /* Source operand is byte, word, long or quad sized. */ | |
255 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
256 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
257 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
258 | ||
259 | /* Source operand is word, long or quad sized. */ | |
260 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
261 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
262 | "w", "r", _LO32, "r", "", "r") | |
263 | ||
d175226a GT |
264 | /* Instruction has three operands and one operand is stored in ECX register */ |
265 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
266 | do { \ | |
267 | unsigned long _tmp; \ | |
268 | _type _clv = (_cl).val; \ | |
269 | _type _srcv = (_src).val; \ | |
270 | _type _dstv = (_dst).val; \ | |
271 | \ | |
272 | __asm__ __volatile__ ( \ | |
273 | _PRE_EFLAGS("0", "5", "2") \ | |
274 | _op _suffix " %4,%1 \n" \ | |
275 | _POST_EFLAGS("0", "5", "2") \ | |
276 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
277 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
278 | ); \ | |
279 | \ | |
280 | (_cl).val = (unsigned long) _clv; \ | |
281 | (_src).val = (unsigned long) _srcv; \ | |
282 | (_dst).val = (unsigned long) _dstv; \ | |
283 | } while (0) | |
284 | ||
285 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
286 | do { \ | |
287 | switch ((_dst).bytes) { \ | |
288 | case 2: \ | |
289 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
290 | "w", unsigned short); \ | |
291 | break; \ | |
292 | case 4: \ | |
293 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
294 | "l", unsigned int); \ | |
295 | break; \ | |
296 | case 8: \ | |
297 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
298 | "q", unsigned long)); \ | |
299 | break; \ | |
300 | } \ | |
301 | } while (0) | |
302 | ||
dda96d8f | 303 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
304 | do { \ |
305 | unsigned long _tmp; \ | |
306 | \ | |
dda96d8f AK |
307 | __asm__ __volatile__ ( \ |
308 | _PRE_EFLAGS("0", "3", "2") \ | |
309 | _op _suffix " %1; " \ | |
310 | _POST_EFLAGS("0", "3", "2") \ | |
311 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
312 | "=&r" (_tmp) \ | |
313 | : "i" (EFLAGS_MASK)); \ | |
314 | } while (0) | |
315 | ||
316 | /* Instruction has only one explicit operand (no source operand). */ | |
317 | #define emulate_1op(_op, _dst, _eflags) \ | |
318 | do { \ | |
d77c26fc | 319 | switch ((_dst).bytes) { \ |
dda96d8f AK |
320 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
321 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
322 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
323 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
324 | } \ |
325 | } while (0) | |
326 | ||
3f9f53b0 MG |
327 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
328 | do { \ | |
329 | unsigned long _tmp; \ | |
330 | \ | |
331 | __asm__ __volatile__ ( \ | |
332 | _PRE_EFLAGS("0", "4", "1") \ | |
333 | _op _suffix " %5; " \ | |
334 | _POST_EFLAGS("0", "4", "1") \ | |
335 | : "=m" (_eflags), "=&r" (_tmp), \ | |
336 | "+a" (_rax), "+d" (_rdx) \ | |
337 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
338 | "a" (_rax), "d" (_rdx)); \ | |
339 | } while (0) | |
340 | ||
f6b3597b AK |
341 | #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \ |
342 | do { \ | |
343 | unsigned long _tmp; \ | |
344 | \ | |
345 | __asm__ __volatile__ ( \ | |
346 | _PRE_EFLAGS("0", "5", "1") \ | |
347 | "1: \n\t" \ | |
348 | _op _suffix " %6; " \ | |
349 | "2: \n\t" \ | |
350 | _POST_EFLAGS("0", "5", "1") \ | |
351 | ".pushsection .fixup,\"ax\" \n\t" \ | |
352 | "3: movb $1, %4 \n\t" \ | |
353 | "jmp 2b \n\t" \ | |
354 | ".popsection \n\t" \ | |
355 | _ASM_EXTABLE(1b, 3b) \ | |
356 | : "=m" (_eflags), "=&r" (_tmp), \ | |
357 | "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \ | |
358 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
359 | "a" (_rax), "d" (_rdx)); \ | |
360 | } while (0) | |
361 | ||
3f9f53b0 MG |
362 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
363 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
364 | do { \ | |
365 | switch((_src).bytes) { \ | |
366 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
367 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
368 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
369 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
370 | } \ | |
371 | } while (0) | |
372 | ||
f6b3597b AK |
373 | #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \ |
374 | do { \ | |
375 | switch((_src).bytes) { \ | |
376 | case 1: \ | |
377 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
378 | _eflags, "b", _ex); \ | |
379 | break; \ | |
380 | case 2: \ | |
381 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
382 | _eflags, "w", _ex); \ | |
383 | break; \ | |
384 | case 4: \ | |
385 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
386 | _eflags, "l", _ex); \ | |
387 | break; \ | |
388 | case 8: ON64( \ | |
389 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
390 | _eflags, "q", _ex)); \ | |
391 | break; \ | |
392 | } \ | |
393 | } while (0) | |
394 | ||
6aa8b732 AK |
395 | /* Fetch next part of the instruction being emulated. */ |
396 | #define insn_fetch(_type, _size, _eip) \ | |
397 | ({ unsigned long _x; \ | |
62266869 | 398 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 399 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
400 | goto done; \ |
401 | (_eip) += (_size); \ | |
402 | (_type)_x; \ | |
403 | }) | |
404 | ||
414e6277 GN |
405 | #define insn_fetch_arr(_arr, _size, _eip) \ |
406 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
407 | if (rc != X86EMUL_CONTINUE) \ | |
408 | goto done; \ | |
409 | (_eip) += (_size); \ | |
410 | }) | |
411 | ||
8a76d7f2 JR |
412 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
413 | enum x86_intercept intercept, | |
414 | enum x86_intercept_stage stage) | |
415 | { | |
416 | struct x86_instruction_info info = { | |
417 | .intercept = intercept, | |
418 | .rep_prefix = ctxt->decode.rep_prefix, | |
419 | .modrm_mod = ctxt->decode.modrm_mod, | |
420 | .modrm_reg = ctxt->decode.modrm_reg, | |
421 | .modrm_rm = ctxt->decode.modrm_rm, | |
422 | .src_val = ctxt->decode.src.val64, | |
423 | .src_bytes = ctxt->decode.src.bytes, | |
424 | .dst_bytes = ctxt->decode.dst.bytes, | |
425 | .ad_bytes = ctxt->decode.ad_bytes, | |
426 | .next_rip = ctxt->eip, | |
427 | }; | |
428 | ||
429 | return ctxt->ops->intercept(ctxt->vcpu, &info, stage); | |
430 | } | |
431 | ||
ddcb2885 HH |
432 | static inline unsigned long ad_mask(struct decode_cache *c) |
433 | { | |
434 | return (1UL << (c->ad_bytes << 3)) - 1; | |
435 | } | |
436 | ||
6aa8b732 | 437 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
438 | static inline unsigned long |
439 | address_mask(struct decode_cache *c, unsigned long reg) | |
440 | { | |
441 | if (c->ad_bytes == sizeof(unsigned long)) | |
442 | return reg; | |
443 | else | |
444 | return reg & ad_mask(c); | |
445 | } | |
446 | ||
447 | static inline unsigned long | |
90de84f5 | 448 | register_address(struct decode_cache *c, unsigned long reg) |
e4706772 | 449 | { |
90de84f5 | 450 | return address_mask(c, reg); |
e4706772 HH |
451 | } |
452 | ||
7a957275 HH |
453 | static inline void |
454 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
455 | { | |
456 | if (c->ad_bytes == sizeof(unsigned long)) | |
457 | *reg += inc; | |
458 | else | |
459 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
460 | } | |
6aa8b732 | 461 | |
7a957275 HH |
462 | static inline void jmp_rel(struct decode_cache *c, int rel) |
463 | { | |
464 | register_address_increment(c, &c->eip, rel); | |
465 | } | |
098c937b | 466 | |
7a5b56df AK |
467 | static void set_seg_override(struct decode_cache *c, int seg) |
468 | { | |
469 | c->has_seg_override = true; | |
470 | c->seg_override = seg; | |
471 | } | |
472 | ||
79168fd1 GN |
473 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
474 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
475 | { |
476 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
477 | return 0; | |
478 | ||
79168fd1 | 479 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
480 | } |
481 | ||
90de84f5 AK |
482 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt, |
483 | struct x86_emulate_ops *ops, | |
484 | struct decode_cache *c) | |
7a5b56df AK |
485 | { |
486 | if (!c->has_seg_override) | |
487 | return 0; | |
488 | ||
90de84f5 | 489 | return c->seg_override; |
7a5b56df AK |
490 | } |
491 | ||
90de84f5 AK |
492 | static ulong linear(struct x86_emulate_ctxt *ctxt, |
493 | struct segmented_address addr) | |
7a5b56df | 494 | { |
90de84f5 AK |
495 | struct decode_cache *c = &ctxt->decode; |
496 | ulong la; | |
7a5b56df | 497 | |
90de84f5 AK |
498 | la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea; |
499 | if (c->ad_bytes != 8) | |
500 | la &= (u32)-1; | |
501 | return la; | |
7a5b56df AK |
502 | } |
503 | ||
35d3d4a1 AK |
504 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
505 | u32 error, bool valid) | |
54b8486f | 506 | { |
da9cb575 AK |
507 | ctxt->exception.vector = vec; |
508 | ctxt->exception.error_code = error; | |
509 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 510 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
511 | } |
512 | ||
3b88e41a JR |
513 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
514 | { | |
515 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
516 | } | |
517 | ||
35d3d4a1 | 518 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 519 | { |
35d3d4a1 | 520 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
521 | } |
522 | ||
35d3d4a1 | 523 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 524 | { |
35d3d4a1 | 525 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
526 | } |
527 | ||
35d3d4a1 | 528 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 529 | { |
35d3d4a1 | 530 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
531 | } |
532 | ||
34d1f490 AK |
533 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
534 | { | |
35d3d4a1 | 535 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
536 | } |
537 | ||
1253791d AK |
538 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
539 | { | |
540 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
541 | } | |
542 | ||
62266869 AK |
543 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
544 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 545 | unsigned long eip, u8 *dest) |
62266869 AK |
546 | { |
547 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
548 | int rc; | |
2fb53ad8 | 549 | int size, cur_size; |
62266869 | 550 | |
2fb53ad8 AK |
551 | if (eip == fc->end) { |
552 | cur_size = fc->end - fc->start; | |
553 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
554 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
bcc55cba | 555 | size, ctxt->vcpu, &ctxt->exception); |
3e2815e9 | 556 | if (rc != X86EMUL_CONTINUE) |
62266869 | 557 | return rc; |
2fb53ad8 | 558 | fc->end += size; |
62266869 | 559 | } |
2fb53ad8 | 560 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 561 | return X86EMUL_CONTINUE; |
62266869 AK |
562 | } |
563 | ||
564 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
565 | struct x86_emulate_ops *ops, | |
566 | unsigned long eip, void *dest, unsigned size) | |
567 | { | |
3e2815e9 | 568 | int rc; |
62266869 | 569 | |
eb3c79e6 | 570 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 571 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 572 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
573 | while (size--) { |
574 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 575 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
576 | return rc; |
577 | } | |
3e2815e9 | 578 | return X86EMUL_CONTINUE; |
62266869 AK |
579 | } |
580 | ||
1e3c5cb0 RR |
581 | /* |
582 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
583 | * pointer into the block that addresses the relevant register. | |
584 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
585 | */ | |
586 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
587 | int highbyte_regs) | |
6aa8b732 AK |
588 | { |
589 | void *p; | |
590 | ||
591 | p = ®s[modrm_reg]; | |
592 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
593 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
594 | return p; | |
595 | } | |
596 | ||
597 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
598 | struct x86_emulate_ops *ops, | |
90de84f5 | 599 | struct segmented_address addr, |
6aa8b732 AK |
600 | u16 *size, unsigned long *address, int op_bytes) |
601 | { | |
602 | int rc; | |
603 | ||
604 | if (op_bytes == 2) | |
605 | op_bytes = 3; | |
606 | *address = 0; | |
90de84f5 | 607 | rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2, |
bcc55cba | 608 | ctxt->vcpu, &ctxt->exception); |
1b30eaa8 | 609 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 610 | return rc; |
30b31ab6 AK |
611 | addr.ea += 2; |
612 | rc = ops->read_std(linear(ctxt, addr), address, op_bytes, | |
bcc55cba | 613 | ctxt->vcpu, &ctxt->exception); |
6aa8b732 AK |
614 | return rc; |
615 | } | |
616 | ||
bbe9abbd NK |
617 | static int test_cc(unsigned int condition, unsigned int flags) |
618 | { | |
619 | int rc = 0; | |
620 | ||
621 | switch ((condition & 15) >> 1) { | |
622 | case 0: /* o */ | |
623 | rc |= (flags & EFLG_OF); | |
624 | break; | |
625 | case 1: /* b/c/nae */ | |
626 | rc |= (flags & EFLG_CF); | |
627 | break; | |
628 | case 2: /* z/e */ | |
629 | rc |= (flags & EFLG_ZF); | |
630 | break; | |
631 | case 3: /* be/na */ | |
632 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
633 | break; | |
634 | case 4: /* s */ | |
635 | rc |= (flags & EFLG_SF); | |
636 | break; | |
637 | case 5: /* p/pe */ | |
638 | rc |= (flags & EFLG_PF); | |
639 | break; | |
640 | case 7: /* le/ng */ | |
641 | rc |= (flags & EFLG_ZF); | |
642 | /* fall through */ | |
643 | case 6: /* l/nge */ | |
644 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
645 | break; | |
646 | } | |
647 | ||
648 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
649 | return (!!rc ^ (condition & 1)); | |
650 | } | |
651 | ||
91ff3cb4 AK |
652 | static void fetch_register_operand(struct operand *op) |
653 | { | |
654 | switch (op->bytes) { | |
655 | case 1: | |
656 | op->val = *(u8 *)op->addr.reg; | |
657 | break; | |
658 | case 2: | |
659 | op->val = *(u16 *)op->addr.reg; | |
660 | break; | |
661 | case 4: | |
662 | op->val = *(u32 *)op->addr.reg; | |
663 | break; | |
664 | case 8: | |
665 | op->val = *(u64 *)op->addr.reg; | |
666 | break; | |
667 | } | |
668 | } | |
669 | ||
1253791d AK |
670 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
671 | { | |
672 | ctxt->ops->get_fpu(ctxt); | |
673 | switch (reg) { | |
674 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
675 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
676 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
677 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
678 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
679 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
680 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
681 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
682 | #ifdef CONFIG_X86_64 | |
683 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
684 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
685 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
686 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
687 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
688 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
689 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
690 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
691 | #endif | |
692 | default: BUG(); | |
693 | } | |
694 | ctxt->ops->put_fpu(ctxt); | |
695 | } | |
696 | ||
697 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
698 | int reg) | |
699 | { | |
700 | ctxt->ops->get_fpu(ctxt); | |
701 | switch (reg) { | |
702 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
703 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
704 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
705 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
706 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
707 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
708 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
709 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
710 | #ifdef CONFIG_X86_64 | |
711 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
712 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
713 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
714 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
715 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
716 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
717 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
718 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
719 | #endif | |
720 | default: BUG(); | |
721 | } | |
722 | ctxt->ops->put_fpu(ctxt); | |
723 | } | |
724 | ||
725 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
726 | struct operand *op, | |
3c118e24 | 727 | struct decode_cache *c, |
3c118e24 AK |
728 | int inhibit_bytereg) |
729 | { | |
33615aa9 | 730 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 731 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
732 | |
733 | if (!(c->d & ModRM)) | |
734 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
1253791d AK |
735 | |
736 | if (c->d & Sse) { | |
737 | op->type = OP_XMM; | |
738 | op->bytes = 16; | |
739 | op->addr.xmm = reg; | |
740 | read_sse_reg(ctxt, &op->vec_val, reg); | |
741 | return; | |
742 | } | |
743 | ||
3c118e24 AK |
744 | op->type = OP_REG; |
745 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 746 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
747 | op->bytes = 1; |
748 | } else { | |
1a6440ae | 749 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 750 | op->bytes = c->op_bytes; |
3c118e24 | 751 | } |
91ff3cb4 | 752 | fetch_register_operand(op); |
3c118e24 AK |
753 | op->orig_val = op->val; |
754 | } | |
755 | ||
1c73ef66 | 756 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
757 | struct x86_emulate_ops *ops, |
758 | struct operand *op) | |
1c73ef66 AK |
759 | { |
760 | struct decode_cache *c = &ctxt->decode; | |
761 | u8 sib; | |
f5b4edcd | 762 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 763 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 764 | ulong modrm_ea = 0; |
1c73ef66 AK |
765 | |
766 | if (c->rex_prefix) { | |
767 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
768 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
769 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
770 | } | |
771 | ||
772 | c->modrm = insn_fetch(u8, 1, c->eip); | |
773 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
774 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
775 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 776 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
777 | |
778 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
779 | op->type = OP_REG; |
780 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
781 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 782 | c->regs, c->d & ByteOp); |
1253791d AK |
783 | if (c->d & Sse) { |
784 | op->type = OP_XMM; | |
785 | op->bytes = 16; | |
786 | op->addr.xmm = c->modrm_rm; | |
787 | read_sse_reg(ctxt, &op->vec_val, c->modrm_rm); | |
788 | return rc; | |
789 | } | |
2dbd0dd7 | 790 | fetch_register_operand(op); |
1c73ef66 AK |
791 | return rc; |
792 | } | |
793 | ||
2dbd0dd7 AK |
794 | op->type = OP_MEM; |
795 | ||
1c73ef66 AK |
796 | if (c->ad_bytes == 2) { |
797 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
798 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
799 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
800 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
801 | ||
802 | /* 16-bit ModR/M decode. */ | |
803 | switch (c->modrm_mod) { | |
804 | case 0: | |
805 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 806 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
807 | break; |
808 | case 1: | |
2dbd0dd7 | 809 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
810 | break; |
811 | case 2: | |
2dbd0dd7 | 812 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
813 | break; |
814 | } | |
815 | switch (c->modrm_rm) { | |
816 | case 0: | |
2dbd0dd7 | 817 | modrm_ea += bx + si; |
1c73ef66 AK |
818 | break; |
819 | case 1: | |
2dbd0dd7 | 820 | modrm_ea += bx + di; |
1c73ef66 AK |
821 | break; |
822 | case 2: | |
2dbd0dd7 | 823 | modrm_ea += bp + si; |
1c73ef66 AK |
824 | break; |
825 | case 3: | |
2dbd0dd7 | 826 | modrm_ea += bp + di; |
1c73ef66 AK |
827 | break; |
828 | case 4: | |
2dbd0dd7 | 829 | modrm_ea += si; |
1c73ef66 AK |
830 | break; |
831 | case 5: | |
2dbd0dd7 | 832 | modrm_ea += di; |
1c73ef66 AK |
833 | break; |
834 | case 6: | |
835 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 836 | modrm_ea += bp; |
1c73ef66 AK |
837 | break; |
838 | case 7: | |
2dbd0dd7 | 839 | modrm_ea += bx; |
1c73ef66 AK |
840 | break; |
841 | } | |
842 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
843 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 844 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 845 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
846 | } else { |
847 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 848 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
849 | sib = insn_fetch(u8, 1, c->eip); |
850 | index_reg |= (sib >> 3) & 7; | |
851 | base_reg |= sib & 7; | |
852 | scale = sib >> 6; | |
853 | ||
dc71d0f1 | 854 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 855 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 856 | else |
2dbd0dd7 | 857 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 858 | if (index_reg != 4) |
2dbd0dd7 | 859 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
860 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
861 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 862 | c->rip_relative = 1; |
84411d85 | 863 | } else |
2dbd0dd7 | 864 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
865 | switch (c->modrm_mod) { |
866 | case 0: | |
867 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 868 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
869 | break; |
870 | case 1: | |
2dbd0dd7 | 871 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
872 | break; |
873 | case 2: | |
2dbd0dd7 | 874 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
875 | break; |
876 | } | |
877 | } | |
90de84f5 | 878 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
879 | done: |
880 | return rc; | |
881 | } | |
882 | ||
883 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
884 | struct x86_emulate_ops *ops, |
885 | struct operand *op) | |
1c73ef66 AK |
886 | { |
887 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 888 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 889 | |
2dbd0dd7 | 890 | op->type = OP_MEM; |
1c73ef66 AK |
891 | switch (c->ad_bytes) { |
892 | case 2: | |
90de84f5 | 893 | op->addr.mem.ea = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
894 | break; |
895 | case 4: | |
90de84f5 | 896 | op->addr.mem.ea = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
897 | break; |
898 | case 8: | |
90de84f5 | 899 | op->addr.mem.ea = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
900 | break; |
901 | } | |
902 | done: | |
903 | return rc; | |
904 | } | |
905 | ||
35c843c4 WY |
906 | static void fetch_bit_operand(struct decode_cache *c) |
907 | { | |
7129eeca | 908 | long sv = 0, mask; |
35c843c4 | 909 | |
3885f18f | 910 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
911 | mask = ~(c->dst.bytes * 8 - 1); |
912 | ||
913 | if (c->src.bytes == 2) | |
914 | sv = (s16)c->src.val & (s16)mask; | |
915 | else if (c->src.bytes == 4) | |
916 | sv = (s32)c->src.val & (s32)mask; | |
917 | ||
90de84f5 | 918 | c->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 919 | } |
ba7ff2b7 WY |
920 | |
921 | /* only subword offset */ | |
922 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
923 | } |
924 | ||
dde7e6d1 AK |
925 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
926 | struct x86_emulate_ops *ops, | |
927 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 928 | { |
dde7e6d1 AK |
929 | int rc; |
930 | struct read_cache *mc = &ctxt->decode.mem_read; | |
6aa8b732 | 931 | |
dde7e6d1 AK |
932 | while (size) { |
933 | int n = min(size, 8u); | |
934 | size -= n; | |
935 | if (mc->pos < mc->end) | |
936 | goto read_cached; | |
5cd21917 | 937 | |
bcc55cba AK |
938 | rc = ops->read_emulated(addr, mc->data + mc->end, n, |
939 | &ctxt->exception, ctxt->vcpu); | |
dde7e6d1 AK |
940 | if (rc != X86EMUL_CONTINUE) |
941 | return rc; | |
942 | mc->end += n; | |
6aa8b732 | 943 | |
dde7e6d1 AK |
944 | read_cached: |
945 | memcpy(dest, mc->data + mc->pos, n); | |
946 | mc->pos += n; | |
947 | dest += n; | |
948 | addr += n; | |
6aa8b732 | 949 | } |
dde7e6d1 AK |
950 | return X86EMUL_CONTINUE; |
951 | } | |
6aa8b732 | 952 | |
dde7e6d1 AK |
953 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
954 | struct x86_emulate_ops *ops, | |
955 | unsigned int size, unsigned short port, | |
956 | void *dest) | |
957 | { | |
958 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 959 | |
dde7e6d1 AK |
960 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
961 | struct decode_cache *c = &ctxt->decode; | |
962 | unsigned int in_page, n; | |
963 | unsigned int count = c->rep_prefix ? | |
964 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
965 | in_page = (ctxt->eflags & EFLG_DF) ? | |
966 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
967 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
968 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
969 | count); | |
970 | if (n == 0) | |
971 | n = 1; | |
972 | rc->pos = rc->end = 0; | |
973 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
974 | return 0; | |
975 | rc->end = n * size; | |
6aa8b732 AK |
976 | } |
977 | ||
dde7e6d1 AK |
978 | memcpy(dest, rc->data + rc->pos, size); |
979 | rc->pos += size; | |
980 | return 1; | |
981 | } | |
6aa8b732 | 982 | |
dde7e6d1 AK |
983 | static u32 desc_limit_scaled(struct desc_struct *desc) |
984 | { | |
985 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 986 | |
dde7e6d1 AK |
987 | return desc->g ? (limit << 12) | 0xfff : limit; |
988 | } | |
6aa8b732 | 989 | |
dde7e6d1 AK |
990 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
991 | struct x86_emulate_ops *ops, | |
992 | u16 selector, struct desc_ptr *dt) | |
993 | { | |
994 | if (selector & 1 << 2) { | |
995 | struct desc_struct desc; | |
996 | memset (dt, 0, sizeof *dt); | |
5601d05b GN |
997 | if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR, |
998 | ctxt->vcpu)) | |
dde7e6d1 | 999 | return; |
e09d082c | 1000 | |
dde7e6d1 AK |
1001 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1002 | dt->address = get_desc_base(&desc); | |
1003 | } else | |
1004 | ops->get_gdt(dt, ctxt->vcpu); | |
1005 | } | |
120df890 | 1006 | |
dde7e6d1 AK |
1007 | /* allowed just for 8 bytes segments */ |
1008 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1009 | struct x86_emulate_ops *ops, | |
1010 | u16 selector, struct desc_struct *desc) | |
1011 | { | |
1012 | struct desc_ptr dt; | |
1013 | u16 index = selector >> 3; | |
1014 | int ret; | |
dde7e6d1 | 1015 | ulong addr; |
120df890 | 1016 | |
dde7e6d1 | 1017 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 1018 | |
35d3d4a1 AK |
1019 | if (dt.size < index * 8 + 7) |
1020 | return emulate_gp(ctxt, selector & 0xfffc); | |
dde7e6d1 | 1021 | addr = dt.address + index * 8; |
bcc55cba AK |
1022 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, |
1023 | &ctxt->exception); | |
e09d082c | 1024 | |
dde7e6d1 AK |
1025 | return ret; |
1026 | } | |
ef65c889 | 1027 | |
dde7e6d1 AK |
1028 | /* allowed just for 8 bytes segments */ |
1029 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1030 | struct x86_emulate_ops *ops, | |
1031 | u16 selector, struct desc_struct *desc) | |
1032 | { | |
1033 | struct desc_ptr dt; | |
1034 | u16 index = selector >> 3; | |
dde7e6d1 AK |
1035 | ulong addr; |
1036 | int ret; | |
6aa8b732 | 1037 | |
dde7e6d1 | 1038 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 1039 | |
35d3d4a1 AK |
1040 | if (dt.size < index * 8 + 7) |
1041 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1042 | |
dde7e6d1 | 1043 | addr = dt.address + index * 8; |
bcc55cba AK |
1044 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, |
1045 | &ctxt->exception); | |
c7e75a3d | 1046 | |
dde7e6d1 AK |
1047 | return ret; |
1048 | } | |
c7e75a3d | 1049 | |
5601d05b | 1050 | /* Does not support long mode */ |
dde7e6d1 AK |
1051 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
1052 | struct x86_emulate_ops *ops, | |
1053 | u16 selector, int seg) | |
1054 | { | |
1055 | struct desc_struct seg_desc; | |
1056 | u8 dpl, rpl, cpl; | |
1057 | unsigned err_vec = GP_VECTOR; | |
1058 | u32 err_code = 0; | |
1059 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1060 | int ret; | |
69f55cb1 | 1061 | |
dde7e6d1 | 1062 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1063 | |
dde7e6d1 AK |
1064 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1065 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1066 | /* set real mode segment descriptor */ | |
1067 | set_desc_base(&seg_desc, selector << 4); | |
1068 | set_desc_limit(&seg_desc, 0xffff); | |
1069 | seg_desc.type = 3; | |
1070 | seg_desc.p = 1; | |
1071 | seg_desc.s = 1; | |
1072 | goto load; | |
1073 | } | |
1074 | ||
1075 | /* NULL selector is not valid for TR, CS and SS */ | |
1076 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1077 | && null_selector) | |
1078 | goto exception; | |
1079 | ||
1080 | /* TR should be in GDT only */ | |
1081 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1082 | goto exception; | |
1083 | ||
1084 | if (null_selector) /* for NULL selector skip all following checks */ | |
1085 | goto load; | |
1086 | ||
1087 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1088 | if (ret != X86EMUL_CONTINUE) | |
1089 | return ret; | |
1090 | ||
1091 | err_code = selector & 0xfffc; | |
1092 | err_vec = GP_VECTOR; | |
1093 | ||
1094 | /* can't load system descriptor into segment selecor */ | |
1095 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1096 | goto exception; | |
1097 | ||
1098 | if (!seg_desc.p) { | |
1099 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1100 | goto exception; | |
1101 | } | |
1102 | ||
1103 | rpl = selector & 3; | |
1104 | dpl = seg_desc.dpl; | |
1105 | cpl = ops->cpl(ctxt->vcpu); | |
1106 | ||
1107 | switch (seg) { | |
1108 | case VCPU_SREG_SS: | |
1109 | /* | |
1110 | * segment is not a writable data segment or segment | |
1111 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1112 | */ | |
1113 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1114 | goto exception; | |
6aa8b732 | 1115 | break; |
dde7e6d1 AK |
1116 | case VCPU_SREG_CS: |
1117 | if (!(seg_desc.type & 8)) | |
1118 | goto exception; | |
1119 | ||
1120 | if (seg_desc.type & 4) { | |
1121 | /* conforming */ | |
1122 | if (dpl > cpl) | |
1123 | goto exception; | |
1124 | } else { | |
1125 | /* nonconforming */ | |
1126 | if (rpl > cpl || dpl != cpl) | |
1127 | goto exception; | |
1128 | } | |
1129 | /* CS(RPL) <- CPL */ | |
1130 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1131 | break; |
dde7e6d1 AK |
1132 | case VCPU_SREG_TR: |
1133 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1134 | goto exception; | |
1135 | break; | |
1136 | case VCPU_SREG_LDTR: | |
1137 | if (seg_desc.s || seg_desc.type != 2) | |
1138 | goto exception; | |
1139 | break; | |
1140 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1141 | /* |
dde7e6d1 AK |
1142 | * segment is not a data or readable code segment or |
1143 | * ((segment is a data or nonconforming code segment) | |
1144 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1145 | */ |
dde7e6d1 AK |
1146 | if ((seg_desc.type & 0xa) == 0x8 || |
1147 | (((seg_desc.type & 0xc) != 0xc) && | |
1148 | (rpl > dpl && cpl > dpl))) | |
1149 | goto exception; | |
6aa8b732 | 1150 | break; |
dde7e6d1 AK |
1151 | } |
1152 | ||
1153 | if (seg_desc.s) { | |
1154 | /* mark segment as accessed */ | |
1155 | seg_desc.type |= 1; | |
1156 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1157 | if (ret != X86EMUL_CONTINUE) | |
1158 | return ret; | |
1159 | } | |
1160 | load: | |
1161 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
5601d05b | 1162 | ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu); |
dde7e6d1 AK |
1163 | return X86EMUL_CONTINUE; |
1164 | exception: | |
1165 | emulate_exception(ctxt, err_vec, err_code, true); | |
1166 | return X86EMUL_PROPAGATE_FAULT; | |
1167 | } | |
1168 | ||
31be40b3 WY |
1169 | static void write_register_operand(struct operand *op) |
1170 | { | |
1171 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1172 | switch (op->bytes) { | |
1173 | case 1: | |
1174 | *(u8 *)op->addr.reg = (u8)op->val; | |
1175 | break; | |
1176 | case 2: | |
1177 | *(u16 *)op->addr.reg = (u16)op->val; | |
1178 | break; | |
1179 | case 4: | |
1180 | *op->addr.reg = (u32)op->val; | |
1181 | break; /* 64b: zero-extend */ | |
1182 | case 8: | |
1183 | *op->addr.reg = op->val; | |
1184 | break; | |
1185 | } | |
1186 | } | |
1187 | ||
dde7e6d1 AK |
1188 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1189 | struct x86_emulate_ops *ops) | |
1190 | { | |
1191 | int rc; | |
1192 | struct decode_cache *c = &ctxt->decode; | |
dde7e6d1 AK |
1193 | |
1194 | switch (c->dst.type) { | |
1195 | case OP_REG: | |
31be40b3 | 1196 | write_register_operand(&c->dst); |
6aa8b732 | 1197 | break; |
dde7e6d1 AK |
1198 | case OP_MEM: |
1199 | if (c->lock_prefix) | |
1200 | rc = ops->cmpxchg_emulated( | |
90de84f5 | 1201 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1202 | &c->dst.orig_val, |
1203 | &c->dst.val, | |
1204 | c->dst.bytes, | |
bcc55cba | 1205 | &ctxt->exception, |
dde7e6d1 | 1206 | ctxt->vcpu); |
341de7e3 | 1207 | else |
dde7e6d1 | 1208 | rc = ops->write_emulated( |
90de84f5 | 1209 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1210 | &c->dst.val, |
1211 | c->dst.bytes, | |
bcc55cba | 1212 | &ctxt->exception, |
dde7e6d1 | 1213 | ctxt->vcpu); |
dde7e6d1 AK |
1214 | if (rc != X86EMUL_CONTINUE) |
1215 | return rc; | |
a682e354 | 1216 | break; |
1253791d AK |
1217 | case OP_XMM: |
1218 | write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm); | |
1219 | break; | |
dde7e6d1 AK |
1220 | case OP_NONE: |
1221 | /* no writeback */ | |
414e6277 | 1222 | break; |
dde7e6d1 | 1223 | default: |
414e6277 | 1224 | break; |
6aa8b732 | 1225 | } |
dde7e6d1 AK |
1226 | return X86EMUL_CONTINUE; |
1227 | } | |
6aa8b732 | 1228 | |
dde7e6d1 AK |
1229 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1230 | struct x86_emulate_ops *ops) | |
1231 | { | |
1232 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1233 | |
dde7e6d1 AK |
1234 | c->dst.type = OP_MEM; |
1235 | c->dst.bytes = c->op_bytes; | |
1236 | c->dst.val = c->src.val; | |
1237 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
90de84f5 AK |
1238 | c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1239 | c->dst.addr.mem.seg = VCPU_SREG_SS; | |
dde7e6d1 | 1240 | } |
69f55cb1 | 1241 | |
dde7e6d1 AK |
1242 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1243 | struct x86_emulate_ops *ops, | |
1244 | void *dest, int len) | |
1245 | { | |
1246 | struct decode_cache *c = &ctxt->decode; | |
1247 | int rc; | |
90de84f5 | 1248 | struct segmented_address addr; |
8b4caf66 | 1249 | |
90de84f5 AK |
1250 | addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1251 | addr.seg = VCPU_SREG_SS; | |
1252 | rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len); | |
dde7e6d1 AK |
1253 | if (rc != X86EMUL_CONTINUE) |
1254 | return rc; | |
1255 | ||
1256 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1257 | return rc; | |
8b4caf66 LV |
1258 | } |
1259 | ||
dde7e6d1 AK |
1260 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1261 | struct x86_emulate_ops *ops, | |
1262 | void *dest, int len) | |
9de41573 GN |
1263 | { |
1264 | int rc; | |
dde7e6d1 AK |
1265 | unsigned long val, change_mask; |
1266 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1267 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1268 | |
dde7e6d1 AK |
1269 | rc = emulate_pop(ctxt, ops, &val, len); |
1270 | if (rc != X86EMUL_CONTINUE) | |
1271 | return rc; | |
9de41573 | 1272 | |
dde7e6d1 AK |
1273 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1274 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1275 | |
dde7e6d1 AK |
1276 | switch(ctxt->mode) { |
1277 | case X86EMUL_MODE_PROT64: | |
1278 | case X86EMUL_MODE_PROT32: | |
1279 | case X86EMUL_MODE_PROT16: | |
1280 | if (cpl == 0) | |
1281 | change_mask |= EFLG_IOPL; | |
1282 | if (cpl <= iopl) | |
1283 | change_mask |= EFLG_IF; | |
1284 | break; | |
1285 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1286 | if (iopl < 3) |
1287 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1288 | change_mask |= EFLG_IF; |
1289 | break; | |
1290 | default: /* real mode */ | |
1291 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1292 | break; | |
9de41573 | 1293 | } |
dde7e6d1 AK |
1294 | |
1295 | *(unsigned long *)dest = | |
1296 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1297 | ||
1298 | return rc; | |
9de41573 GN |
1299 | } |
1300 | ||
dde7e6d1 AK |
1301 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1302 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1303 | { |
dde7e6d1 | 1304 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1305 | |
dde7e6d1 | 1306 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1307 | |
dde7e6d1 | 1308 | emulate_push(ctxt, ops); |
7b262e90 GN |
1309 | } |
1310 | ||
dde7e6d1 AK |
1311 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1312 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1313 | { |
dde7e6d1 AK |
1314 | struct decode_cache *c = &ctxt->decode; |
1315 | unsigned long selector; | |
1316 | int rc; | |
38ba30ba | 1317 | |
dde7e6d1 AK |
1318 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1319 | if (rc != X86EMUL_CONTINUE) | |
1320 | return rc; | |
1321 | ||
1322 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1323 | return rc; | |
38ba30ba GN |
1324 | } |
1325 | ||
dde7e6d1 AK |
1326 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1327 | struct x86_emulate_ops *ops) | |
38ba30ba | 1328 | { |
dde7e6d1 AK |
1329 | struct decode_cache *c = &ctxt->decode; |
1330 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1331 | int rc = X86EMUL_CONTINUE; | |
1332 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1333 | |
dde7e6d1 AK |
1334 | while (reg <= VCPU_REGS_RDI) { |
1335 | (reg == VCPU_REGS_RSP) ? | |
1336 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1337 | |
dde7e6d1 | 1338 | emulate_push(ctxt, ops); |
38ba30ba | 1339 | |
dde7e6d1 AK |
1340 | rc = writeback(ctxt, ops); |
1341 | if (rc != X86EMUL_CONTINUE) | |
1342 | return rc; | |
38ba30ba | 1343 | |
dde7e6d1 | 1344 | ++reg; |
38ba30ba | 1345 | } |
38ba30ba | 1346 | |
dde7e6d1 AK |
1347 | /* Disable writeback. */ |
1348 | c->dst.type = OP_NONE; | |
1349 | ||
1350 | return rc; | |
38ba30ba GN |
1351 | } |
1352 | ||
dde7e6d1 AK |
1353 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1354 | struct x86_emulate_ops *ops) | |
38ba30ba | 1355 | { |
dde7e6d1 AK |
1356 | struct decode_cache *c = &ctxt->decode; |
1357 | int rc = X86EMUL_CONTINUE; | |
1358 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1359 | |
dde7e6d1 AK |
1360 | while (reg >= VCPU_REGS_RAX) { |
1361 | if (reg == VCPU_REGS_RSP) { | |
1362 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1363 | c->op_bytes); | |
1364 | --reg; | |
1365 | } | |
38ba30ba | 1366 | |
dde7e6d1 AK |
1367 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1368 | if (rc != X86EMUL_CONTINUE) | |
1369 | break; | |
1370 | --reg; | |
38ba30ba | 1371 | } |
dde7e6d1 | 1372 | return rc; |
38ba30ba GN |
1373 | } |
1374 | ||
6e154e56 MG |
1375 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1376 | struct x86_emulate_ops *ops, int irq) | |
1377 | { | |
1378 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1379 | int rc; |
6e154e56 MG |
1380 | struct desc_ptr dt; |
1381 | gva_t cs_addr; | |
1382 | gva_t eip_addr; | |
1383 | u16 cs, eip; | |
6e154e56 MG |
1384 | |
1385 | /* TODO: Add limit checks */ | |
1386 | c->src.val = ctxt->eflags; | |
1387 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1388 | rc = writeback(ctxt, ops); |
1389 | if (rc != X86EMUL_CONTINUE) | |
1390 | return rc; | |
6e154e56 MG |
1391 | |
1392 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1393 | ||
1394 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1395 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1396 | rc = writeback(ctxt, ops); |
1397 | if (rc != X86EMUL_CONTINUE) | |
1398 | return rc; | |
6e154e56 MG |
1399 | |
1400 | c->src.val = c->eip; | |
1401 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1402 | rc = writeback(ctxt, ops); |
1403 | if (rc != X86EMUL_CONTINUE) | |
1404 | return rc; | |
1405 | ||
1406 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1407 | |
1408 | ops->get_idt(&dt, ctxt->vcpu); | |
1409 | ||
1410 | eip_addr = dt.address + (irq << 2); | |
1411 | cs_addr = dt.address + (irq << 2) + 2; | |
1412 | ||
bcc55cba | 1413 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1414 | if (rc != X86EMUL_CONTINUE) |
1415 | return rc; | |
1416 | ||
bcc55cba | 1417 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1418 | if (rc != X86EMUL_CONTINUE) |
1419 | return rc; | |
1420 | ||
1421 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1422 | if (rc != X86EMUL_CONTINUE) | |
1423 | return rc; | |
1424 | ||
1425 | c->eip = eip; | |
1426 | ||
1427 | return rc; | |
1428 | } | |
1429 | ||
1430 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1431 | struct x86_emulate_ops *ops, int irq) | |
1432 | { | |
1433 | switch(ctxt->mode) { | |
1434 | case X86EMUL_MODE_REAL: | |
1435 | return emulate_int_real(ctxt, ops, irq); | |
1436 | case X86EMUL_MODE_VM86: | |
1437 | case X86EMUL_MODE_PROT16: | |
1438 | case X86EMUL_MODE_PROT32: | |
1439 | case X86EMUL_MODE_PROT64: | |
1440 | default: | |
1441 | /* Protected mode interrupts unimplemented yet */ | |
1442 | return X86EMUL_UNHANDLEABLE; | |
1443 | } | |
1444 | } | |
1445 | ||
dde7e6d1 AK |
1446 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1447 | struct x86_emulate_ops *ops) | |
38ba30ba | 1448 | { |
dde7e6d1 AK |
1449 | struct decode_cache *c = &ctxt->decode; |
1450 | int rc = X86EMUL_CONTINUE; | |
1451 | unsigned long temp_eip = 0; | |
1452 | unsigned long temp_eflags = 0; | |
1453 | unsigned long cs = 0; | |
1454 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1455 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1456 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1457 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1458 | |
dde7e6d1 | 1459 | /* TODO: Add stack limit check */ |
38ba30ba | 1460 | |
dde7e6d1 | 1461 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1462 | |
dde7e6d1 AK |
1463 | if (rc != X86EMUL_CONTINUE) |
1464 | return rc; | |
38ba30ba | 1465 | |
35d3d4a1 AK |
1466 | if (temp_eip & ~0xffff) |
1467 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1468 | |
dde7e6d1 | 1469 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1470 | |
dde7e6d1 AK |
1471 | if (rc != X86EMUL_CONTINUE) |
1472 | return rc; | |
38ba30ba | 1473 | |
dde7e6d1 | 1474 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1475 | |
dde7e6d1 AK |
1476 | if (rc != X86EMUL_CONTINUE) |
1477 | return rc; | |
38ba30ba | 1478 | |
dde7e6d1 | 1479 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1480 | |
dde7e6d1 AK |
1481 | if (rc != X86EMUL_CONTINUE) |
1482 | return rc; | |
38ba30ba | 1483 | |
dde7e6d1 | 1484 | c->eip = temp_eip; |
38ba30ba | 1485 | |
38ba30ba | 1486 | |
dde7e6d1 AK |
1487 | if (c->op_bytes == 4) |
1488 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1489 | else if (c->op_bytes == 2) { | |
1490 | ctxt->eflags &= ~0xffff; | |
1491 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1492 | } |
dde7e6d1 AK |
1493 | |
1494 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1495 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1496 | ||
1497 | return rc; | |
38ba30ba GN |
1498 | } |
1499 | ||
dde7e6d1 AK |
1500 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1501 | struct x86_emulate_ops* ops) | |
c37eda13 | 1502 | { |
dde7e6d1 AK |
1503 | switch(ctxt->mode) { |
1504 | case X86EMUL_MODE_REAL: | |
1505 | return emulate_iret_real(ctxt, ops); | |
1506 | case X86EMUL_MODE_VM86: | |
1507 | case X86EMUL_MODE_PROT16: | |
1508 | case X86EMUL_MODE_PROT32: | |
1509 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1510 | default: |
dde7e6d1 AK |
1511 | /* iret from protected mode unimplemented yet */ |
1512 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1513 | } |
c37eda13 WY |
1514 | } |
1515 | ||
dde7e6d1 | 1516 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1517 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1518 | { |
1519 | struct decode_cache *c = &ctxt->decode; | |
1520 | ||
dde7e6d1 | 1521 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1522 | } |
1523 | ||
dde7e6d1 | 1524 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1525 | { |
05f086f8 | 1526 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1527 | switch (c->modrm_reg) { |
1528 | case 0: /* rol */ | |
05f086f8 | 1529 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1530 | break; |
1531 | case 1: /* ror */ | |
05f086f8 | 1532 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1533 | break; |
1534 | case 2: /* rcl */ | |
05f086f8 | 1535 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1536 | break; |
1537 | case 3: /* rcr */ | |
05f086f8 | 1538 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1539 | break; |
1540 | case 4: /* sal/shl */ | |
1541 | case 6: /* sal/shl */ | |
05f086f8 | 1542 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1543 | break; |
1544 | case 5: /* shr */ | |
05f086f8 | 1545 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1546 | break; |
1547 | case 7: /* sar */ | |
05f086f8 | 1548 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1549 | break; |
1550 | } | |
1551 | } | |
1552 | ||
1553 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1554 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1555 | { |
1556 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1557 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1558 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
34d1f490 | 1559 | u8 de = 0; |
8cdbd2c9 LV |
1560 | |
1561 | switch (c->modrm_reg) { | |
1562 | case 0 ... 1: /* test */ | |
05f086f8 | 1563 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1564 | break; |
1565 | case 2: /* not */ | |
1566 | c->dst.val = ~c->dst.val; | |
1567 | break; | |
1568 | case 3: /* neg */ | |
05f086f8 | 1569 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1570 | break; |
3f9f53b0 MG |
1571 | case 4: /* mul */ |
1572 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1573 | break; | |
1574 | case 5: /* imul */ | |
1575 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1576 | break; | |
1577 | case 6: /* div */ | |
34d1f490 AK |
1578 | emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx, |
1579 | ctxt->eflags, de); | |
3f9f53b0 MG |
1580 | break; |
1581 | case 7: /* idiv */ | |
34d1f490 AK |
1582 | emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx, |
1583 | ctxt->eflags, de); | |
3f9f53b0 | 1584 | break; |
8cdbd2c9 | 1585 | default: |
8c5eee30 | 1586 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1587 | } |
34d1f490 AK |
1588 | if (de) |
1589 | return emulate_de(ctxt); | |
8c5eee30 | 1590 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1591 | } |
1592 | ||
1593 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1594 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1595 | { |
1596 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1597 | |
1598 | switch (c->modrm_reg) { | |
1599 | case 0: /* inc */ | |
05f086f8 | 1600 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1601 | break; |
1602 | case 1: /* dec */ | |
05f086f8 | 1603 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1604 | break; |
d19292e4 MG |
1605 | case 2: /* call near abs */ { |
1606 | long int old_eip; | |
1607 | old_eip = c->eip; | |
1608 | c->eip = c->src.val; | |
1609 | c->src.val = old_eip; | |
79168fd1 | 1610 | emulate_push(ctxt, ops); |
d19292e4 MG |
1611 | break; |
1612 | } | |
8cdbd2c9 | 1613 | case 4: /* jmp abs */ |
fd60754e | 1614 | c->eip = c->src.val; |
8cdbd2c9 LV |
1615 | break; |
1616 | case 6: /* push */ | |
79168fd1 | 1617 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1618 | break; |
8cdbd2c9 | 1619 | } |
1b30eaa8 | 1620 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1621 | } |
1622 | ||
1623 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1624 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1625 | { |
1626 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1627 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1628 | |
1629 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1630 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1631 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1632 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1633 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1634 | } else { |
16518d5a AK |
1635 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1636 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1637 | |
05f086f8 | 1638 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1639 | } |
1b30eaa8 | 1640 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1641 | } |
1642 | ||
a77ab5ea AK |
1643 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1644 | struct x86_emulate_ops *ops) | |
1645 | { | |
1646 | struct decode_cache *c = &ctxt->decode; | |
1647 | int rc; | |
1648 | unsigned long cs; | |
1649 | ||
1650 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1651 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1652 | return rc; |
1653 | if (c->op_bytes == 4) | |
1654 | c->eip = (u32)c->eip; | |
1655 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1656 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1657 | return rc; |
2e873022 | 1658 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1659 | return rc; |
1660 | } | |
1661 | ||
09b5f4d3 WY |
1662 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, |
1663 | struct x86_emulate_ops *ops, int seg) | |
1664 | { | |
1665 | struct decode_cache *c = &ctxt->decode; | |
1666 | unsigned short sel; | |
1667 | int rc; | |
1668 | ||
1669 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
1670 | ||
1671 | rc = load_segment_descriptor(ctxt, ops, sel, seg); | |
1672 | if (rc != X86EMUL_CONTINUE) | |
1673 | return rc; | |
1674 | ||
1675 | c->dst.val = c->src.val; | |
1676 | return rc; | |
1677 | } | |
1678 | ||
e66bb2cc AP |
1679 | static inline void |
1680 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1681 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1682 | struct desc_struct *ss) | |
e66bb2cc | 1683 | { |
79168fd1 | 1684 | memset(cs, 0, sizeof(struct desc_struct)); |
5601d05b | 1685 | ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1686 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1687 | |
1688 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1689 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1690 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1691 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1692 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1693 | cs->s = 1; | |
1694 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1695 | cs->p = 1; |
1696 | cs->d = 1; | |
e66bb2cc | 1697 | |
79168fd1 GN |
1698 | set_desc_base(ss, 0); /* flat segment */ |
1699 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1700 | ss->g = 1; /* 4kb granularity */ |
1701 | ss->s = 1; | |
1702 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1703 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1704 | ss->dpl = 0; |
79168fd1 | 1705 | ss->p = 1; |
e66bb2cc AP |
1706 | } |
1707 | ||
1708 | static int | |
3fb1b5db | 1709 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1710 | { |
1711 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1712 | struct desc_struct cs, ss; |
e66bb2cc | 1713 | u64 msr_data; |
79168fd1 | 1714 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1715 | |
1716 | /* syscall is not available in real mode */ | |
2e901c4c | 1717 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
1718 | ctxt->mode == X86EMUL_MODE_VM86) |
1719 | return emulate_ud(ctxt); | |
e66bb2cc | 1720 | |
79168fd1 | 1721 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1722 | |
3fb1b5db | 1723 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1724 | msr_data >>= 32; |
79168fd1 GN |
1725 | cs_sel = (u16)(msr_data & 0xfffc); |
1726 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1727 | |
1728 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1729 | cs.d = 0; |
e66bb2cc AP |
1730 | cs.l = 1; |
1731 | } | |
5601d05b | 1732 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1733 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1734 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1735 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
e66bb2cc AP |
1736 | |
1737 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1738 | if (is_long_mode(ctxt->vcpu)) { | |
1739 | #ifdef CONFIG_X86_64 | |
1740 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1741 | ||
3fb1b5db GN |
1742 | ops->get_msr(ctxt->vcpu, |
1743 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1744 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1745 | c->eip = msr_data; |
1746 | ||
3fb1b5db | 1747 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1748 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1749 | #endif | |
1750 | } else { | |
1751 | /* legacy mode */ | |
3fb1b5db | 1752 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1753 | c->eip = (u32)msr_data; |
1754 | ||
1755 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1756 | } | |
1757 | ||
e54cfa97 | 1758 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1759 | } |
1760 | ||
8c604352 | 1761 | static int |
3fb1b5db | 1762 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1763 | { |
1764 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1765 | struct desc_struct cs, ss; |
8c604352 | 1766 | u64 msr_data; |
79168fd1 | 1767 | u16 cs_sel, ss_sel; |
8c604352 | 1768 | |
a0044755 | 1769 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
1770 | if (ctxt->mode == X86EMUL_MODE_REAL) |
1771 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1772 | |
1773 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1774 | * Therefore, we inject an #UD. | |
1775 | */ | |
35d3d4a1 AK |
1776 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
1777 | return emulate_ud(ctxt); | |
8c604352 | 1778 | |
79168fd1 | 1779 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1780 | |
3fb1b5db | 1781 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1782 | switch (ctxt->mode) { |
1783 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
1784 | if ((msr_data & 0xfffc) == 0x0) |
1785 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1786 | break; |
1787 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
1788 | if (msr_data == 0x0) |
1789 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1790 | break; |
1791 | } | |
1792 | ||
1793 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1794 | cs_sel = (u16)msr_data; |
1795 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1796 | ss_sel = cs_sel + 8; | |
1797 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1798 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1799 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1800 | cs.d = 0; |
8c604352 AP |
1801 | cs.l = 1; |
1802 | } | |
1803 | ||
5601d05b | 1804 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1805 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1806 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1807 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
8c604352 | 1808 | |
3fb1b5db | 1809 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1810 | c->eip = msr_data; |
1811 | ||
3fb1b5db | 1812 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1813 | c->regs[VCPU_REGS_RSP] = msr_data; |
1814 | ||
e54cfa97 | 1815 | return X86EMUL_CONTINUE; |
8c604352 AP |
1816 | } |
1817 | ||
4668f050 | 1818 | static int |
3fb1b5db | 1819 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1820 | { |
1821 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1822 | struct desc_struct cs, ss; |
4668f050 AP |
1823 | u64 msr_data; |
1824 | int usermode; | |
79168fd1 | 1825 | u16 cs_sel, ss_sel; |
4668f050 | 1826 | |
a0044755 GN |
1827 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1828 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
1829 | ctxt->mode == X86EMUL_MODE_VM86) |
1830 | return emulate_gp(ctxt, 0); | |
4668f050 | 1831 | |
79168fd1 | 1832 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1833 | |
1834 | if ((c->rex_prefix & 0x8) != 0x0) | |
1835 | usermode = X86EMUL_MODE_PROT64; | |
1836 | else | |
1837 | usermode = X86EMUL_MODE_PROT32; | |
1838 | ||
1839 | cs.dpl = 3; | |
1840 | ss.dpl = 3; | |
3fb1b5db | 1841 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1842 | switch (usermode) { |
1843 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1844 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
1845 | if ((msr_data & 0xfffc) == 0x0) |
1846 | return emulate_gp(ctxt, 0); | |
79168fd1 | 1847 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1848 | break; |
1849 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1850 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
1851 | if (msr_data == 0x0) |
1852 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
1853 | ss_sel = cs_sel + 8; |
1854 | cs.d = 0; | |
4668f050 AP |
1855 | cs.l = 1; |
1856 | break; | |
1857 | } | |
79168fd1 GN |
1858 | cs_sel |= SELECTOR_RPL_MASK; |
1859 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1860 | |
5601d05b | 1861 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1862 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1863 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1864 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
4668f050 | 1865 | |
bdb475a3 GN |
1866 | c->eip = c->regs[VCPU_REGS_RDX]; |
1867 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1868 | |
e54cfa97 | 1869 | return X86EMUL_CONTINUE; |
4668f050 AP |
1870 | } |
1871 | ||
9c537244 GN |
1872 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1873 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1874 | { |
1875 | int iopl; | |
1876 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1877 | return false; | |
1878 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1879 | return true; | |
1880 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1881 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1882 | } |
1883 | ||
1884 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1885 | struct x86_emulate_ops *ops, | |
1886 | u16 port, u16 len) | |
1887 | { | |
79168fd1 | 1888 | struct desc_struct tr_seg; |
5601d05b | 1889 | u32 base3; |
f850e2e6 | 1890 | int r; |
399a40c9 | 1891 | u16 io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 1892 | unsigned mask = (1 << len) - 1; |
5601d05b | 1893 | unsigned long base; |
f850e2e6 | 1894 | |
5601d05b | 1895 | ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu); |
79168fd1 | 1896 | if (!tr_seg.p) |
f850e2e6 | 1897 | return false; |
79168fd1 | 1898 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1899 | return false; |
5601d05b GN |
1900 | base = get_desc_base(&tr_seg); |
1901 | #ifdef CONFIG_X86_64 | |
1902 | base |= ((u64)base3) << 32; | |
1903 | #endif | |
1904 | r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1905 | if (r != X86EMUL_CONTINUE) |
1906 | return false; | |
79168fd1 | 1907 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1908 | return false; |
399a40c9 | 1909 | r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu, |
5601d05b | 1910 | NULL); |
f850e2e6 GN |
1911 | if (r != X86EMUL_CONTINUE) |
1912 | return false; | |
1913 | if ((perm >> bit_idx) & mask) | |
1914 | return false; | |
1915 | return true; | |
1916 | } | |
1917 | ||
1918 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1919 | struct x86_emulate_ops *ops, | |
1920 | u16 port, u16 len) | |
1921 | { | |
4fc40f07 GN |
1922 | if (ctxt->perm_ok) |
1923 | return true; | |
1924 | ||
9c537244 | 1925 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1926 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1927 | return false; | |
4fc40f07 GN |
1928 | |
1929 | ctxt->perm_ok = true; | |
1930 | ||
f850e2e6 GN |
1931 | return true; |
1932 | } | |
1933 | ||
38ba30ba GN |
1934 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1935 | struct x86_emulate_ops *ops, | |
1936 | struct tss_segment_16 *tss) | |
1937 | { | |
1938 | struct decode_cache *c = &ctxt->decode; | |
1939 | ||
1940 | tss->ip = c->eip; | |
1941 | tss->flag = ctxt->eflags; | |
1942 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1943 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1944 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1945 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1946 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1947 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1948 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1949 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1950 | ||
1951 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1952 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1953 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1954 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1955 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1956 | } | |
1957 | ||
1958 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1959 | struct x86_emulate_ops *ops, | |
1960 | struct tss_segment_16 *tss) | |
1961 | { | |
1962 | struct decode_cache *c = &ctxt->decode; | |
1963 | int ret; | |
1964 | ||
1965 | c->eip = tss->ip; | |
1966 | ctxt->eflags = tss->flag | 2; | |
1967 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1968 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1969 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1970 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1971 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1972 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1973 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1974 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1975 | ||
1976 | /* | |
1977 | * SDM says that segment selectors are loaded before segment | |
1978 | * descriptors | |
1979 | */ | |
1980 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1981 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1982 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1983 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1984 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1985 | ||
1986 | /* | |
1987 | * Now load segment descriptors. If fault happenes at this stage | |
1988 | * it is handled in a context of new task | |
1989 | */ | |
1990 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1991 | if (ret != X86EMUL_CONTINUE) | |
1992 | return ret; | |
1993 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1994 | if (ret != X86EMUL_CONTINUE) | |
1995 | return ret; | |
1996 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1997 | if (ret != X86EMUL_CONTINUE) | |
1998 | return ret; | |
1999 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2000 | if (ret != X86EMUL_CONTINUE) | |
2001 | return ret; | |
2002 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2003 | if (ret != X86EMUL_CONTINUE) | |
2004 | return ret; | |
2005 | ||
2006 | return X86EMUL_CONTINUE; | |
2007 | } | |
2008 | ||
2009 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
2010 | struct x86_emulate_ops *ops, | |
2011 | u16 tss_selector, u16 old_tss_sel, | |
2012 | ulong old_tss_base, struct desc_struct *new_desc) | |
2013 | { | |
2014 | struct tss_segment_16 tss_seg; | |
2015 | int ret; | |
bcc55cba | 2016 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2017 | |
2018 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2019 | &ctxt->exception); |
db297e3d | 2020 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2021 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2022 | return ret; |
38ba30ba GN |
2023 | |
2024 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
2025 | ||
2026 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2027 | &ctxt->exception); |
db297e3d | 2028 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2029 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2030 | return ret; |
38ba30ba GN |
2031 | |
2032 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2033 | &ctxt->exception); |
db297e3d | 2034 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2035 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2036 | return ret; |
38ba30ba GN |
2037 | |
2038 | if (old_tss_sel != 0xffff) { | |
2039 | tss_seg.prev_task_link = old_tss_sel; | |
2040 | ||
2041 | ret = ops->write_std(new_tss_base, | |
2042 | &tss_seg.prev_task_link, | |
2043 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2044 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2045 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2046 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2047 | return ret; |
38ba30ba GN |
2048 | } |
2049 | ||
2050 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2051 | } | |
2052 | ||
2053 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2054 | struct x86_emulate_ops *ops, | |
2055 | struct tss_segment_32 *tss) | |
2056 | { | |
2057 | struct decode_cache *c = &ctxt->decode; | |
2058 | ||
2059 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2060 | tss->eip = c->eip; | |
2061 | tss->eflags = ctxt->eflags; | |
2062 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2063 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2064 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2065 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2066 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2067 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2068 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2069 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2070 | ||
2071 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2072 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2073 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2074 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2075 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2076 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2077 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2078 | } | |
2079 | ||
2080 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2081 | struct x86_emulate_ops *ops, | |
2082 | struct tss_segment_32 *tss) | |
2083 | { | |
2084 | struct decode_cache *c = &ctxt->decode; | |
2085 | int ret; | |
2086 | ||
35d3d4a1 AK |
2087 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) |
2088 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2089 | c->eip = tss->eip; |
2090 | ctxt->eflags = tss->eflags | 2; | |
2091 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2092 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2093 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2094 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2095 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2096 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2097 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2098 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2099 | ||
2100 | /* | |
2101 | * SDM says that segment selectors are loaded before segment | |
2102 | * descriptors | |
2103 | */ | |
2104 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2105 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2106 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2107 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2108 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2109 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2110 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2111 | ||
2112 | /* | |
2113 | * Now load segment descriptors. If fault happenes at this stage | |
2114 | * it is handled in a context of new task | |
2115 | */ | |
2116 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2117 | if (ret != X86EMUL_CONTINUE) | |
2118 | return ret; | |
2119 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2120 | if (ret != X86EMUL_CONTINUE) | |
2121 | return ret; | |
2122 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2123 | if (ret != X86EMUL_CONTINUE) | |
2124 | return ret; | |
2125 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2126 | if (ret != X86EMUL_CONTINUE) | |
2127 | return ret; | |
2128 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2129 | if (ret != X86EMUL_CONTINUE) | |
2130 | return ret; | |
2131 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2132 | if (ret != X86EMUL_CONTINUE) | |
2133 | return ret; | |
2134 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2135 | if (ret != X86EMUL_CONTINUE) | |
2136 | return ret; | |
2137 | ||
2138 | return X86EMUL_CONTINUE; | |
2139 | } | |
2140 | ||
2141 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2142 | struct x86_emulate_ops *ops, | |
2143 | u16 tss_selector, u16 old_tss_sel, | |
2144 | ulong old_tss_base, struct desc_struct *new_desc) | |
2145 | { | |
2146 | struct tss_segment_32 tss_seg; | |
2147 | int ret; | |
bcc55cba | 2148 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2149 | |
2150 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2151 | &ctxt->exception); |
db297e3d | 2152 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2153 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2154 | return ret; |
38ba30ba GN |
2155 | |
2156 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2157 | ||
2158 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2159 | &ctxt->exception); |
db297e3d | 2160 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2161 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2162 | return ret; |
38ba30ba GN |
2163 | |
2164 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2165 | &ctxt->exception); |
db297e3d | 2166 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2167 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2168 | return ret; |
38ba30ba GN |
2169 | |
2170 | if (old_tss_sel != 0xffff) { | |
2171 | tss_seg.prev_task_link = old_tss_sel; | |
2172 | ||
2173 | ret = ops->write_std(new_tss_base, | |
2174 | &tss_seg.prev_task_link, | |
2175 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2176 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2177 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2178 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2179 | return ret; |
38ba30ba GN |
2180 | } |
2181 | ||
2182 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2183 | } | |
2184 | ||
2185 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2186 | struct x86_emulate_ops *ops, |
2187 | u16 tss_selector, int reason, | |
2188 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2189 | { |
2190 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2191 | int ret; | |
2192 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2193 | ulong old_tss_base = | |
5951c442 | 2194 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2195 | u32 desc_limit; |
38ba30ba GN |
2196 | |
2197 | /* FIXME: old_tss_base == ~0 ? */ | |
2198 | ||
2199 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2200 | if (ret != X86EMUL_CONTINUE) | |
2201 | return ret; | |
2202 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2203 | if (ret != X86EMUL_CONTINUE) | |
2204 | return ret; | |
2205 | ||
2206 | /* FIXME: check that next_tss_desc is tss */ | |
2207 | ||
2208 | if (reason != TASK_SWITCH_IRET) { | |
2209 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
35d3d4a1 AK |
2210 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) |
2211 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2212 | } |
2213 | ||
ceffb459 GN |
2214 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2215 | if (!next_tss_desc.p || | |
2216 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2217 | desc_limit < 0x2b)) { | |
54b8486f | 2218 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2219 | return X86EMUL_PROPAGATE_FAULT; |
2220 | } | |
2221 | ||
2222 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2223 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2224 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2225 | &curr_tss_desc); | |
2226 | } | |
2227 | ||
2228 | if (reason == TASK_SWITCH_IRET) | |
2229 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2230 | ||
2231 | /* set back link to prev task only if NT bit is set in eflags | |
2232 | note that old_tss_sel is not used afetr this point */ | |
2233 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2234 | old_tss_sel = 0xffff; | |
2235 | ||
2236 | if (next_tss_desc.type & 8) | |
2237 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2238 | old_tss_base, &next_tss_desc); | |
2239 | else | |
2240 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2241 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2242 | if (ret != X86EMUL_CONTINUE) |
2243 | return ret; | |
38ba30ba GN |
2244 | |
2245 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2246 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2247 | ||
2248 | if (reason != TASK_SWITCH_IRET) { | |
2249 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2250 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2251 | &next_tss_desc); | |
2252 | } | |
2253 | ||
2254 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
5601d05b | 2255 | ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu); |
38ba30ba GN |
2256 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); |
2257 | ||
e269fb21 JK |
2258 | if (has_error_code) { |
2259 | struct decode_cache *c = &ctxt->decode; | |
2260 | ||
2261 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2262 | c->lock_prefix = 0; | |
2263 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2264 | emulate_push(ctxt, ops); |
e269fb21 JK |
2265 | } |
2266 | ||
38ba30ba GN |
2267 | return ret; |
2268 | } | |
2269 | ||
2270 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2271 | u16 tss_selector, int reason, |
2272 | bool has_error_code, u32 error_code) | |
38ba30ba | 2273 | { |
9aabc88f | 2274 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2275 | struct decode_cache *c = &ctxt->decode; |
2276 | int rc; | |
2277 | ||
38ba30ba | 2278 | c->eip = ctxt->eip; |
e269fb21 | 2279 | c->dst.type = OP_NONE; |
38ba30ba | 2280 | |
e269fb21 JK |
2281 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2282 | has_error_code, error_code); | |
38ba30ba GN |
2283 | |
2284 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2285 | rc = writeback(ctxt, ops); |
95c55886 GN |
2286 | if (rc == X86EMUL_CONTINUE) |
2287 | ctxt->eip = c->eip; | |
38ba30ba GN |
2288 | } |
2289 | ||
a0c0ab2f | 2290 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2291 | } |
2292 | ||
90de84f5 | 2293 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2294 | int reg, struct operand *op) |
a682e354 GN |
2295 | { |
2296 | struct decode_cache *c = &ctxt->decode; | |
2297 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2298 | ||
d9271123 | 2299 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
90de84f5 AK |
2300 | op->addr.mem.ea = register_address(c, c->regs[reg]); |
2301 | op->addr.mem.seg = seg; | |
a682e354 GN |
2302 | } |
2303 | ||
63540382 AK |
2304 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2305 | { | |
2306 | emulate_push(ctxt, ctxt->ops); | |
2307 | return X86EMUL_CONTINUE; | |
2308 | } | |
2309 | ||
7af04fc0 AK |
2310 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2311 | { | |
2312 | struct decode_cache *c = &ctxt->decode; | |
2313 | u8 al, old_al; | |
2314 | bool af, cf, old_cf; | |
2315 | ||
2316 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2317 | al = c->dst.val; | |
2318 | ||
2319 | old_al = al; | |
2320 | old_cf = cf; | |
2321 | cf = false; | |
2322 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2323 | if ((al & 0x0f) > 9 || af) { | |
2324 | al -= 6; | |
2325 | cf = old_cf | (al >= 250); | |
2326 | af = true; | |
2327 | } else { | |
2328 | af = false; | |
2329 | } | |
2330 | if (old_al > 0x99 || old_cf) { | |
2331 | al -= 0x60; | |
2332 | cf = true; | |
2333 | } | |
2334 | ||
2335 | c->dst.val = al; | |
2336 | /* Set PF, ZF, SF */ | |
2337 | c->src.type = OP_IMM; | |
2338 | c->src.val = 0; | |
2339 | c->src.bytes = 1; | |
2340 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2341 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2342 | if (cf) | |
2343 | ctxt->eflags |= X86_EFLAGS_CF; | |
2344 | if (af) | |
2345 | ctxt->eflags |= X86_EFLAGS_AF; | |
2346 | return X86EMUL_CONTINUE; | |
2347 | } | |
2348 | ||
0ef753b8 AK |
2349 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2350 | { | |
2351 | struct decode_cache *c = &ctxt->decode; | |
2352 | u16 sel, old_cs; | |
2353 | ulong old_eip; | |
2354 | int rc; | |
2355 | ||
2356 | old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2357 | old_eip = c->eip; | |
2358 | ||
2359 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
2360 | if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS)) | |
2361 | return X86EMUL_CONTINUE; | |
2362 | ||
2363 | c->eip = 0; | |
2364 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
2365 | ||
2366 | c->src.val = old_cs; | |
2367 | emulate_push(ctxt, ctxt->ops); | |
2368 | rc = writeback(ctxt, ctxt->ops); | |
2369 | if (rc != X86EMUL_CONTINUE) | |
2370 | return rc; | |
2371 | ||
2372 | c->src.val = old_eip; | |
2373 | emulate_push(ctxt, ctxt->ops); | |
2374 | rc = writeback(ctxt, ctxt->ops); | |
2375 | if (rc != X86EMUL_CONTINUE) | |
2376 | return rc; | |
2377 | ||
2378 | c->dst.type = OP_NONE; | |
2379 | ||
2380 | return X86EMUL_CONTINUE; | |
2381 | } | |
2382 | ||
40ece7c7 AK |
2383 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2384 | { | |
2385 | struct decode_cache *c = &ctxt->decode; | |
2386 | int rc; | |
2387 | ||
2388 | c->dst.type = OP_REG; | |
2389 | c->dst.addr.reg = &c->eip; | |
2390 | c->dst.bytes = c->op_bytes; | |
2391 | rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes); | |
2392 | if (rc != X86EMUL_CONTINUE) | |
2393 | return rc; | |
2394 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val); | |
2395 | return X86EMUL_CONTINUE; | |
2396 | } | |
2397 | ||
5c82aa29 | 2398 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 AK |
2399 | { |
2400 | struct decode_cache *c = &ctxt->decode; | |
2401 | ||
f3a1b9f4 AK |
2402 | emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags); |
2403 | return X86EMUL_CONTINUE; | |
2404 | } | |
2405 | ||
5c82aa29 AK |
2406 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2407 | { | |
2408 | struct decode_cache *c = &ctxt->decode; | |
2409 | ||
2410 | c->dst.val = c->src2.val; | |
2411 | return em_imul(ctxt); | |
2412 | } | |
2413 | ||
61429142 AK |
2414 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2415 | { | |
2416 | struct decode_cache *c = &ctxt->decode; | |
2417 | ||
2418 | c->dst.type = OP_REG; | |
2419 | c->dst.bytes = c->src.bytes; | |
2420 | c->dst.addr.reg = &c->regs[VCPU_REGS_RDX]; | |
2421 | c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1); | |
2422 | ||
2423 | return X86EMUL_CONTINUE; | |
2424 | } | |
2425 | ||
48bb5d3c AK |
2426 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2427 | { | |
48bb5d3c AK |
2428 | struct decode_cache *c = &ctxt->decode; |
2429 | u64 tsc = 0; | |
2430 | ||
48bb5d3c AK |
2431 | ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc); |
2432 | c->regs[VCPU_REGS_RAX] = (u32)tsc; | |
2433 | c->regs[VCPU_REGS_RDX] = tsc >> 32; | |
2434 | return X86EMUL_CONTINUE; | |
2435 | } | |
2436 | ||
b9eac5f4 AK |
2437 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2438 | { | |
2439 | struct decode_cache *c = &ctxt->decode; | |
2440 | c->dst.val = c->src.val; | |
2441 | return X86EMUL_CONTINUE; | |
2442 | } | |
2443 | ||
aa97bb48 AK |
2444 | static int em_movdqu(struct x86_emulate_ctxt *ctxt) |
2445 | { | |
2446 | struct decode_cache *c = &ctxt->decode; | |
2447 | memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes); | |
2448 | return X86EMUL_CONTINUE; | |
2449 | } | |
2450 | ||
cfec82cb JR |
2451 | static bool valid_cr(int nr) |
2452 | { | |
2453 | switch (nr) { | |
2454 | case 0: | |
2455 | case 2 ... 4: | |
2456 | case 8: | |
2457 | return true; | |
2458 | default: | |
2459 | return false; | |
2460 | } | |
2461 | } | |
2462 | ||
2463 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
2464 | { | |
2465 | struct decode_cache *c = &ctxt->decode; | |
2466 | ||
2467 | if (!valid_cr(c->modrm_reg)) | |
2468 | return emulate_ud(ctxt); | |
2469 | ||
2470 | return X86EMUL_CONTINUE; | |
2471 | } | |
2472 | ||
2473 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
2474 | { | |
2475 | struct decode_cache *c = &ctxt->decode; | |
2476 | u64 new_val = c->src.val64; | |
2477 | int cr = c->modrm_reg; | |
2478 | ||
2479 | static u64 cr_reserved_bits[] = { | |
2480 | 0xffffffff00000000ULL, | |
2481 | 0, 0, 0, /* CR3 checked later */ | |
2482 | CR4_RESERVED_BITS, | |
2483 | 0, 0, 0, | |
2484 | CR8_RESERVED_BITS, | |
2485 | }; | |
2486 | ||
2487 | if (!valid_cr(cr)) | |
2488 | return emulate_ud(ctxt); | |
2489 | ||
2490 | if (new_val & cr_reserved_bits[cr]) | |
2491 | return emulate_gp(ctxt, 0); | |
2492 | ||
2493 | switch (cr) { | |
2494 | case 0: { | |
2495 | u64 cr4, efer; | |
2496 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || | |
2497 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
2498 | return emulate_gp(ctxt, 0); | |
2499 | ||
2500 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2501 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2502 | ||
2503 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
2504 | !(cr4 & X86_CR4_PAE)) | |
2505 | return emulate_gp(ctxt, 0); | |
2506 | ||
2507 | break; | |
2508 | } | |
2509 | case 3: { | |
2510 | u64 rsvd = 0; | |
2511 | ||
2512 | if (is_long_mode(ctxt->vcpu)) | |
2513 | rsvd = CR3_L_MODE_RESERVED_BITS; | |
2514 | else if (is_pae(ctxt->vcpu)) | |
2515 | rsvd = CR3_PAE_RESERVED_BITS; | |
2516 | else if (is_paging(ctxt->vcpu)) | |
2517 | rsvd = CR3_NONPAE_RESERVED_BITS; | |
2518 | ||
2519 | if (new_val & rsvd) | |
2520 | return emulate_gp(ctxt, 0); | |
2521 | ||
2522 | break; | |
2523 | } | |
2524 | case 4: { | |
2525 | u64 cr4, efer; | |
2526 | ||
2527 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2528 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2529 | ||
2530 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
2531 | return emulate_gp(ctxt, 0); | |
2532 | ||
2533 | break; | |
2534 | } | |
2535 | } | |
2536 | ||
2537 | return X86EMUL_CONTINUE; | |
2538 | } | |
2539 | ||
3b88e41a JR |
2540 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
2541 | { | |
2542 | unsigned long dr7; | |
2543 | ||
2544 | ctxt->ops->get_dr(7, &dr7, ctxt->vcpu); | |
2545 | ||
2546 | /* Check if DR7.Global_Enable is set */ | |
2547 | return dr7 & (1 << 13); | |
2548 | } | |
2549 | ||
2550 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
2551 | { | |
2552 | struct decode_cache *c = &ctxt->decode; | |
2553 | int dr = c->modrm_reg; | |
2554 | u64 cr4; | |
2555 | ||
2556 | if (dr > 7) | |
2557 | return emulate_ud(ctxt); | |
2558 | ||
2559 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2560 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) | |
2561 | return emulate_ud(ctxt); | |
2562 | ||
2563 | if (check_dr7_gd(ctxt)) | |
2564 | return emulate_db(ctxt); | |
2565 | ||
2566 | return X86EMUL_CONTINUE; | |
2567 | } | |
2568 | ||
2569 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
2570 | { | |
2571 | struct decode_cache *c = &ctxt->decode; | |
2572 | u64 new_val = c->src.val64; | |
2573 | int dr = c->modrm_reg; | |
2574 | ||
2575 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
2576 | return emulate_gp(ctxt, 0); | |
2577 | ||
2578 | return check_dr_read(ctxt); | |
2579 | } | |
2580 | ||
01de8b09 JR |
2581 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
2582 | { | |
2583 | u64 efer; | |
2584 | ||
2585 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2586 | ||
2587 | if (!(efer & EFER_SVME)) | |
2588 | return emulate_ud(ctxt); | |
2589 | ||
2590 | return X86EMUL_CONTINUE; | |
2591 | } | |
2592 | ||
2593 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
2594 | { | |
2595 | u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX); | |
2596 | ||
2597 | /* Valid physical address? */ | |
2598 | if (rax & 0xffff000000000000) | |
2599 | return emulate_gp(ctxt, 0); | |
2600 | ||
2601 | return check_svme(ctxt); | |
2602 | } | |
2603 | ||
d7eb8203 JR |
2604 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
2605 | { | |
2606 | u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2607 | ||
2608 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu)) | |
2609 | return emulate_ud(ctxt); | |
2610 | ||
2611 | return X86EMUL_CONTINUE; | |
2612 | } | |
2613 | ||
8061252e JR |
2614 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
2615 | { | |
2616 | u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2617 | u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX); | |
2618 | ||
2619 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) || | |
2620 | (rcx > 3)) | |
2621 | return emulate_gp(ctxt, 0); | |
2622 | ||
2623 | return X86EMUL_CONTINUE; | |
2624 | } | |
2625 | ||
f6511935 JR |
2626 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
2627 | { | |
2628 | struct decode_cache *c = &ctxt->decode; | |
2629 | ||
2630 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2631 | if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes)) | |
2632 | return emulate_gp(ctxt, 0); | |
2633 | ||
2634 | return X86EMUL_CONTINUE; | |
2635 | } | |
2636 | ||
2637 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
2638 | { | |
2639 | struct decode_cache *c = &ctxt->decode; | |
2640 | ||
2641 | c->src.bytes = min(c->src.bytes, 4u); | |
2642 | if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes)) | |
2643 | return emulate_gp(ctxt, 0); | |
2644 | ||
2645 | return X86EMUL_CONTINUE; | |
2646 | } | |
2647 | ||
73fba5f4 | 2648 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 2649 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
2650 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
2651 | .check_perm = (_p) } | |
73fba5f4 | 2652 | #define N D(0) |
01de8b09 | 2653 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
73fba5f4 AK |
2654 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } |
2655 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2656 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
c4f035c6 AK |
2657 | #define II(_f, _e, _i) \ |
2658 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
2659 | #define IIP(_f, _e, _i, _p) \ |
2660 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
2661 | .check_perm = (_p) } | |
aa97bb48 | 2662 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 2663 | |
8d8f4e9f | 2664 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 2665 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f AK |
2666 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
2667 | ||
6230f7fc AK |
2668 | #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \ |
2669 | D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \ | |
2670 | D2bv(((_f) & ~Lock) | DstAcc | SrcImm) | |
2671 | ||
d7eb8203 JR |
2672 | static struct opcode group7_rm1[] = { |
2673 | DI(SrcNone | ModRM | Priv, monitor), | |
2674 | DI(SrcNone | ModRM | Priv, mwait), | |
2675 | N, N, N, N, N, N, | |
2676 | }; | |
2677 | ||
01de8b09 JR |
2678 | static struct opcode group7_rm3[] = { |
2679 | DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), | |
8b18bc37 | 2680 | DIP(SrcNone | ModRM | Prot | VendorSpecific, vmmcall, check_svme), |
01de8b09 JR |
2681 | DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), |
2682 | DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), | |
2683 | DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), | |
2684 | DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), | |
2685 | DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), | |
2686 | DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), | |
2687 | }; | |
6230f7fc | 2688 | |
d7eb8203 JR |
2689 | static struct opcode group7_rm7[] = { |
2690 | N, | |
2691 | DIP(SrcNone | ModRM, rdtscp, check_rdtsc), | |
2692 | N, N, N, N, N, N, | |
2693 | }; | |
73fba5f4 AK |
2694 | static struct opcode group1[] = { |
2695 | X7(D(Lock)), N | |
2696 | }; | |
2697 | ||
2698 | static struct opcode group1A[] = { | |
2699 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2700 | }; | |
2701 | ||
2702 | static struct opcode group3[] = { | |
2703 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2704 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2705 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2706 | }; |
2707 | ||
2708 | static struct opcode group4[] = { | |
2709 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2710 | N, N, N, N, N, N, | |
2711 | }; | |
2712 | ||
2713 | static struct opcode group5[] = { | |
2714 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
2715 | D(SrcMem | ModRM | Stack), |
2716 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
2717 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
2718 | D(SrcMem | ModRM | Stack), N, | |
2719 | }; | |
2720 | ||
dee6bb70 JR |
2721 | static struct opcode group6[] = { |
2722 | DI(ModRM | Prot, sldt), | |
2723 | DI(ModRM | Prot, str), | |
2724 | DI(ModRM | Prot | Priv, lldt), | |
2725 | DI(ModRM | Prot | Priv, ltr), | |
2726 | N, N, N, N, | |
2727 | }; | |
2728 | ||
73fba5f4 | 2729 | static struct group_dual group7 = { { |
dee6bb70 JR |
2730 | DI(ModRM | Mov | DstMem | Priv, sgdt), |
2731 | DI(ModRM | Mov | DstMem | Priv, sidt), | |
2732 | DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt), | |
3c6e276f AK |
2733 | DI(SrcNone | ModRM | DstMem | Mov, smsw), N, |
2734 | DI(SrcMem16 | ModRM | Mov | Priv, lmsw), | |
2735 | DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg), | |
73fba5f4 | 2736 | }, { |
d7eb8203 | 2737 | D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1), |
01de8b09 | 2738 | N, EXT(0, group7_rm3), |
3c6e276f | 2739 | DI(SrcNone | ModRM | DstMem | Mov, smsw), N, |
d7eb8203 | 2740 | DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7), |
73fba5f4 AK |
2741 | } }; |
2742 | ||
2743 | static struct opcode group8[] = { | |
2744 | N, N, N, N, | |
2745 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2746 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2747 | }; | |
2748 | ||
2749 | static struct group_dual group9 = { { | |
2750 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2751 | }, { | |
2752 | N, N, N, N, N, N, N, N, | |
2753 | } }; | |
2754 | ||
a4d4a7c1 AK |
2755 | static struct opcode group11[] = { |
2756 | I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)), | |
2757 | }; | |
2758 | ||
aa97bb48 AK |
2759 | static struct gprefix pfx_0f_6f_0f_7f = { |
2760 | N, N, N, I(Sse, em_movdqu), | |
2761 | }; | |
2762 | ||
73fba5f4 AK |
2763 | static struct opcode opcode_table[256] = { |
2764 | /* 0x00 - 0x07 */ | |
6230f7fc | 2765 | D6ALU(Lock), |
73fba5f4 AK |
2766 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2767 | /* 0x08 - 0x0F */ | |
6230f7fc | 2768 | D6ALU(Lock), |
73fba5f4 AK |
2769 | D(ImplicitOps | Stack | No64), N, |
2770 | /* 0x10 - 0x17 */ | |
6230f7fc | 2771 | D6ALU(Lock), |
73fba5f4 AK |
2772 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2773 | /* 0x18 - 0x1F */ | |
6230f7fc | 2774 | D6ALU(Lock), |
73fba5f4 AK |
2775 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2776 | /* 0x20 - 0x27 */ | |
6230f7fc | 2777 | D6ALU(Lock), N, N, |
73fba5f4 | 2778 | /* 0x28 - 0x2F */ |
6230f7fc | 2779 | D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 2780 | /* 0x30 - 0x37 */ |
6230f7fc | 2781 | D6ALU(Lock), N, N, |
73fba5f4 | 2782 | /* 0x38 - 0x3F */ |
6230f7fc | 2783 | D6ALU(0), N, N, |
73fba5f4 AK |
2784 | /* 0x40 - 0x4F */ |
2785 | X16(D(DstReg)), | |
2786 | /* 0x50 - 0x57 */ | |
63540382 | 2787 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2788 | /* 0x58 - 0x5F */ |
2789 | X8(D(DstReg | Stack)), | |
2790 | /* 0x60 - 0x67 */ | |
2791 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2792 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2793 | N, N, N, N, | |
2794 | /* 0x68 - 0x6F */ | |
d46164db AK |
2795 | I(SrcImm | Mov | Stack, em_push), |
2796 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
2797 | I(SrcImmByte | Mov | Stack, em_push), |
2798 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
f6511935 JR |
2799 | D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */ |
2800 | D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
2801 | /* 0x70 - 0x7F */ |
2802 | X16(D(SrcImmByte)), | |
2803 | /* 0x80 - 0x87 */ | |
2804 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2805 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2806 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2807 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
76e8e68d | 2808 | D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock), |
73fba5f4 | 2809 | /* 0x88 - 0x8F */ |
b9eac5f4 AK |
2810 | I2bv(DstMem | SrcReg | ModRM | Mov, em_mov), |
2811 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), | |
342fc630 | 2812 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2813 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2814 | /* 0x90 - 0x97 */ | |
bf608f88 | 2815 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 2816 | /* 0x98 - 0x9F */ |
61429142 | 2817 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 2818 | I(SrcImmFAddr | No64, em_call_far), N, |
3c6e276f | 2819 | DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N, |
73fba5f4 | 2820 | /* 0xA0 - 0xA7 */ |
b9eac5f4 AK |
2821 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
2822 | I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov), | |
2823 | I2bv(SrcSI | DstDI | Mov | String, em_mov), | |
2824 | D2bv(SrcSI | DstDI | String), | |
73fba5f4 | 2825 | /* 0xA8 - 0xAF */ |
50748613 | 2826 | D2bv(DstAcc | SrcImm), |
b9eac5f4 AK |
2827 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
2828 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
48fe67b5 | 2829 | D2bv(SrcAcc | DstDI | String), |
73fba5f4 | 2830 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 2831 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2832 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 2833 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2834 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 2835 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 AK |
2836 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
2837 | D(ImplicitOps | Stack), | |
09b5f4d3 | 2838 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
a4d4a7c1 | 2839 | G(ByteOp, group11), G(0, group11), |
73fba5f4 AK |
2840 | /* 0xC8 - 0xCF */ |
2841 | N, N, N, D(ImplicitOps | Stack), | |
3c6e276f AK |
2842 | D(ImplicitOps), DI(SrcImmByte, intn), |
2843 | D(ImplicitOps | No64), DI(ImplicitOps, iret), | |
73fba5f4 | 2844 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 2845 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
2846 | N, N, N, N, |
2847 | /* 0xD8 - 0xDF */ | |
2848 | N, N, N, N, N, N, N, N, | |
2849 | /* 0xE0 - 0xE7 */ | |
e4abac67 | 2850 | X4(D(SrcImmByte)), |
f6511935 JR |
2851 | D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in), |
2852 | D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out), | |
73fba5f4 AK |
2853 | /* 0xE8 - 0xEF */ |
2854 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2855 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
f6511935 JR |
2856 | D2bvIP(SrcNone | DstAcc, in, check_perm_in), |
2857 | D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out), | |
73fba5f4 | 2858 | /* 0xF0 - 0xF7 */ |
bf608f88 | 2859 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
2860 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
2861 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 2862 | /* 0xF8 - 0xFF */ |
8744aa9a | 2863 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2864 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2865 | }; | |
2866 | ||
2867 | static struct opcode twobyte_table[256] = { | |
2868 | /* 0x00 - 0x0F */ | |
dee6bb70 | 2869 | G(0, group6), GD(0, &group7), N, N, |
cfec82cb | 2870 | N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N, |
3c6e276f | 2871 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
2872 | N, D(ImplicitOps | ModRM), N, N, |
2873 | /* 0x10 - 0x1F */ | |
2874 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2875 | /* 0x20 - 0x2F */ | |
cfec82cb | 2876 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 2877 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
cfec82cb | 2878 | DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write), |
3b88e41a | 2879 | DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write), |
73fba5f4 AK |
2880 | N, N, N, N, |
2881 | N, N, N, N, N, N, N, N, | |
2882 | /* 0x30 - 0x3F */ | |
8061252e JR |
2883 | DI(ImplicitOps | Priv, wrmsr), |
2884 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), | |
2885 | DI(ImplicitOps | Priv, rdmsr), | |
2886 | DIP(ImplicitOps | Priv, rdpmc, check_rdpmc), | |
d867162c AK |
2887 | D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific), |
2888 | N, N, | |
73fba5f4 AK |
2889 | N, N, N, N, N, N, N, N, |
2890 | /* 0x40 - 0x4F */ | |
2891 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2892 | /* 0x50 - 0x5F */ | |
2893 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2894 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
2895 | N, N, N, N, |
2896 | N, N, N, N, | |
2897 | N, N, N, N, | |
2898 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 2899 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
2900 | N, N, N, N, |
2901 | N, N, N, N, | |
2902 | N, N, N, N, | |
2903 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
2904 | /* 0x80 - 0x8F */ |
2905 | X16(D(SrcImm)), | |
2906 | /* 0x90 - 0x9F */ | |
ee45b58e | 2907 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2908 | /* 0xA0 - 0xA7 */ |
2909 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 2910 | DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp), |
73fba5f4 AK |
2911 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
2912 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2913 | /* 0xA8 - 0xAF */ | |
2914 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 2915 | DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
73fba5f4 AK |
2916 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
2917 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 2918 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 2919 | /* 0xB0 - 0xB7 */ |
739ae406 | 2920 | D2bv(DstMem | SrcReg | ModRM | Lock), |
09b5f4d3 WY |
2921 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
2922 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
2923 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
2924 | /* 0xB8 - 0xBF */ |
2925 | N, N, | |
ba7ff2b7 | 2926 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2927 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2928 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2929 | /* 0xC0 - 0xCF */ |
739ae406 | 2930 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 2931 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
2932 | N, N, N, GD(0, &group9), |
2933 | N, N, N, N, N, N, N, N, | |
2934 | /* 0xD0 - 0xDF */ | |
2935 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2936 | /* 0xE0 - 0xEF */ | |
2937 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2938 | /* 0xF0 - 0xFF */ | |
2939 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2940 | }; | |
2941 | ||
2942 | #undef D | |
2943 | #undef N | |
2944 | #undef G | |
2945 | #undef GD | |
2946 | #undef I | |
aa97bb48 | 2947 | #undef GP |
01de8b09 | 2948 | #undef EXT |
73fba5f4 | 2949 | |
8d8f4e9f | 2950 | #undef D2bv |
f6511935 | 2951 | #undef D2bvIP |
8d8f4e9f | 2952 | #undef I2bv |
6230f7fc | 2953 | #undef D6ALU |
8d8f4e9f | 2954 | |
39f21ee5 AK |
2955 | static unsigned imm_size(struct decode_cache *c) |
2956 | { | |
2957 | unsigned size; | |
2958 | ||
2959 | size = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2960 | if (size == 8) | |
2961 | size = 4; | |
2962 | return size; | |
2963 | } | |
2964 | ||
2965 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
2966 | unsigned size, bool sign_extension) | |
2967 | { | |
2968 | struct decode_cache *c = &ctxt->decode; | |
2969 | struct x86_emulate_ops *ops = ctxt->ops; | |
2970 | int rc = X86EMUL_CONTINUE; | |
2971 | ||
2972 | op->type = OP_IMM; | |
2973 | op->bytes = size; | |
90de84f5 | 2974 | op->addr.mem.ea = c->eip; |
39f21ee5 AK |
2975 | /* NB. Immediates are sign-extended as necessary. */ |
2976 | switch (op->bytes) { | |
2977 | case 1: | |
2978 | op->val = insn_fetch(s8, 1, c->eip); | |
2979 | break; | |
2980 | case 2: | |
2981 | op->val = insn_fetch(s16, 2, c->eip); | |
2982 | break; | |
2983 | case 4: | |
2984 | op->val = insn_fetch(s32, 4, c->eip); | |
2985 | break; | |
2986 | } | |
2987 | if (!sign_extension) { | |
2988 | switch (op->bytes) { | |
2989 | case 1: | |
2990 | op->val &= 0xff; | |
2991 | break; | |
2992 | case 2: | |
2993 | op->val &= 0xffff; | |
2994 | break; | |
2995 | case 4: | |
2996 | op->val &= 0xffffffff; | |
2997 | break; | |
2998 | } | |
2999 | } | |
3000 | done: | |
3001 | return rc; | |
3002 | } | |
3003 | ||
dde7e6d1 | 3004 | int |
dc25e89e | 3005 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 AK |
3006 | { |
3007 | struct x86_emulate_ops *ops = ctxt->ops; | |
3008 | struct decode_cache *c = &ctxt->decode; | |
3009 | int rc = X86EMUL_CONTINUE; | |
3010 | int mode = ctxt->mode; | |
0d7cdee8 AK |
3011 | int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix; |
3012 | bool op_prefix = false; | |
dde7e6d1 | 3013 | struct opcode opcode, *g_mod012, *g_mod3; |
2dbd0dd7 | 3014 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 | 3015 | |
dde7e6d1 | 3016 | c->eip = ctxt->eip; |
dc25e89e AP |
3017 | c->fetch.start = c->eip; |
3018 | c->fetch.end = c->fetch.start + insn_len; | |
3019 | if (insn_len > 0) | |
3020 | memcpy(c->fetch.data, insn, insn_len); | |
dde7e6d1 AK |
3021 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); |
3022 | ||
3023 | switch (mode) { | |
3024 | case X86EMUL_MODE_REAL: | |
3025 | case X86EMUL_MODE_VM86: | |
3026 | case X86EMUL_MODE_PROT16: | |
3027 | def_op_bytes = def_ad_bytes = 2; | |
3028 | break; | |
3029 | case X86EMUL_MODE_PROT32: | |
3030 | def_op_bytes = def_ad_bytes = 4; | |
3031 | break; | |
3032 | #ifdef CONFIG_X86_64 | |
3033 | case X86EMUL_MODE_PROT64: | |
3034 | def_op_bytes = 4; | |
3035 | def_ad_bytes = 8; | |
3036 | break; | |
3037 | #endif | |
3038 | default: | |
3039 | return -1; | |
3040 | } | |
3041 | ||
3042 | c->op_bytes = def_op_bytes; | |
3043 | c->ad_bytes = def_ad_bytes; | |
3044 | ||
3045 | /* Legacy prefixes. */ | |
3046 | for (;;) { | |
3047 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
3048 | case 0x66: /* operand-size override */ | |
0d7cdee8 | 3049 | op_prefix = true; |
dde7e6d1 AK |
3050 | /* switch between 2/4 bytes */ |
3051 | c->op_bytes = def_op_bytes ^ 6; | |
3052 | break; | |
3053 | case 0x67: /* address-size override */ | |
3054 | if (mode == X86EMUL_MODE_PROT64) | |
3055 | /* switch between 4/8 bytes */ | |
3056 | c->ad_bytes = def_ad_bytes ^ 12; | |
3057 | else | |
3058 | /* switch between 2/4 bytes */ | |
3059 | c->ad_bytes = def_ad_bytes ^ 6; | |
3060 | break; | |
3061 | case 0x26: /* ES override */ | |
3062 | case 0x2e: /* CS override */ | |
3063 | case 0x36: /* SS override */ | |
3064 | case 0x3e: /* DS override */ | |
3065 | set_seg_override(c, (c->b >> 3) & 3); | |
3066 | break; | |
3067 | case 0x64: /* FS override */ | |
3068 | case 0x65: /* GS override */ | |
3069 | set_seg_override(c, c->b & 7); | |
3070 | break; | |
3071 | case 0x40 ... 0x4f: /* REX */ | |
3072 | if (mode != X86EMUL_MODE_PROT64) | |
3073 | goto done_prefixes; | |
3074 | c->rex_prefix = c->b; | |
3075 | continue; | |
3076 | case 0xf0: /* LOCK */ | |
3077 | c->lock_prefix = 1; | |
3078 | break; | |
3079 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 3080 | case 0xf3: /* REP/REPE/REPZ */ |
1d6b114f | 3081 | c->rep_prefix = c->b; |
dde7e6d1 AK |
3082 | break; |
3083 | default: | |
3084 | goto done_prefixes; | |
3085 | } | |
3086 | ||
3087 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
3088 | ||
3089 | c->rex_prefix = 0; | |
3090 | } | |
3091 | ||
3092 | done_prefixes: | |
3093 | ||
3094 | /* REX prefix. */ | |
1e87e3ef AK |
3095 | if (c->rex_prefix & 8) |
3096 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
3097 | |
3098 | /* Opcode byte(s). */ | |
3099 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
3100 | /* Two-byte opcode? */ |
3101 | if (c->b == 0x0f) { | |
3102 | c->twobyte = 1; | |
3103 | c->b = insn_fetch(u8, 1, c->eip); | |
3104 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
3105 | } |
3106 | c->d = opcode.flags; | |
3107 | ||
3108 | if (c->d & Group) { | |
3109 | dual = c->d & GroupDual; | |
3110 | c->modrm = insn_fetch(u8, 1, c->eip); | |
3111 | --c->eip; | |
3112 | ||
3113 | if (c->d & GroupDual) { | |
3114 | g_mod012 = opcode.u.gdual->mod012; | |
3115 | g_mod3 = opcode.u.gdual->mod3; | |
3116 | } else | |
3117 | g_mod012 = g_mod3 = opcode.u.group; | |
3118 | ||
3119 | c->d &= ~(Group | GroupDual); | |
3120 | ||
3121 | goffset = (c->modrm >> 3) & 7; | |
3122 | ||
3123 | if ((c->modrm >> 6) == 3) | |
3124 | opcode = g_mod3[goffset]; | |
3125 | else | |
3126 | opcode = g_mod012[goffset]; | |
01de8b09 JR |
3127 | |
3128 | if (opcode.flags & RMExt) { | |
3129 | goffset = c->modrm & 7; | |
3130 | opcode = opcode.u.group[goffset]; | |
3131 | } | |
3132 | ||
dde7e6d1 AK |
3133 | c->d |= opcode.flags; |
3134 | } | |
3135 | ||
0d7cdee8 AK |
3136 | if (c->d & Prefix) { |
3137 | if (c->rep_prefix && op_prefix) | |
3138 | return X86EMUL_UNHANDLEABLE; | |
3139 | simd_prefix = op_prefix ? 0x66 : c->rep_prefix; | |
3140 | switch (simd_prefix) { | |
3141 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
3142 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
3143 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
3144 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
3145 | } | |
3146 | c->d |= opcode.flags; | |
3147 | } | |
3148 | ||
dde7e6d1 | 3149 | c->execute = opcode.u.execute; |
d09beabd | 3150 | c->check_perm = opcode.check_perm; |
c4f035c6 | 3151 | c->intercept = opcode.intercept; |
dde7e6d1 AK |
3152 | |
3153 | /* Unrecognised? */ | |
d53db5ef | 3154 | if (c->d == 0 || (c->d & Undefined)) |
dde7e6d1 | 3155 | return -1; |
dde7e6d1 | 3156 | |
d867162c AK |
3157 | if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
3158 | return -1; | |
3159 | ||
dde7e6d1 AK |
3160 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
3161 | c->op_bytes = 8; | |
3162 | ||
7f9b4b75 AK |
3163 | if (c->d & Op3264) { |
3164 | if (mode == X86EMUL_MODE_PROT64) | |
3165 | c->op_bytes = 8; | |
3166 | else | |
3167 | c->op_bytes = 4; | |
3168 | } | |
3169 | ||
1253791d AK |
3170 | if (c->d & Sse) |
3171 | c->op_bytes = 16; | |
3172 | ||
dde7e6d1 | 3173 | /* ModRM and SIB bytes. */ |
09ee57cd | 3174 | if (c->d & ModRM) { |
2dbd0dd7 | 3175 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
3176 | if (!c->has_seg_override) |
3177 | set_seg_override(c, c->modrm_seg); | |
3178 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 3179 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
3180 | if (rc != X86EMUL_CONTINUE) |
3181 | goto done; | |
3182 | ||
3183 | if (!c->has_seg_override) | |
3184 | set_seg_override(c, VCPU_SREG_DS); | |
3185 | ||
90de84f5 | 3186 | memop.addr.mem.seg = seg_override(ctxt, ops, c); |
dde7e6d1 | 3187 | |
2dbd0dd7 | 3188 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
90de84f5 | 3189 | memop.addr.mem.ea = (u32)memop.addr.mem.ea; |
dde7e6d1 | 3190 | |
2dbd0dd7 | 3191 | if (memop.type == OP_MEM && c->rip_relative) |
90de84f5 | 3192 | memop.addr.mem.ea += c->eip; |
dde7e6d1 AK |
3193 | |
3194 | /* | |
3195 | * Decode and fetch the source operand: register, memory | |
3196 | * or immediate. | |
3197 | */ | |
3198 | switch (c->d & SrcMask) { | |
3199 | case SrcNone: | |
3200 | break; | |
3201 | case SrcReg: | |
1253791d | 3202 | decode_register_operand(ctxt, &c->src, c, 0); |
dde7e6d1 AK |
3203 | break; |
3204 | case SrcMem16: | |
2dbd0dd7 | 3205 | memop.bytes = 2; |
dde7e6d1 AK |
3206 | goto srcmem_common; |
3207 | case SrcMem32: | |
2dbd0dd7 | 3208 | memop.bytes = 4; |
dde7e6d1 AK |
3209 | goto srcmem_common; |
3210 | case SrcMem: | |
2dbd0dd7 | 3211 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 3212 | c->op_bytes; |
dde7e6d1 | 3213 | srcmem_common: |
2dbd0dd7 | 3214 | c->src = memop; |
dde7e6d1 | 3215 | break; |
b250e605 | 3216 | case SrcImmU16: |
39f21ee5 AK |
3217 | rc = decode_imm(ctxt, &c->src, 2, false); |
3218 | break; | |
dde7e6d1 | 3219 | case SrcImm: |
39f21ee5 AK |
3220 | rc = decode_imm(ctxt, &c->src, imm_size(c), true); |
3221 | break; | |
dde7e6d1 | 3222 | case SrcImmU: |
39f21ee5 | 3223 | rc = decode_imm(ctxt, &c->src, imm_size(c), false); |
dde7e6d1 AK |
3224 | break; |
3225 | case SrcImmByte: | |
39f21ee5 AK |
3226 | rc = decode_imm(ctxt, &c->src, 1, true); |
3227 | break; | |
dde7e6d1 | 3228 | case SrcImmUByte: |
39f21ee5 | 3229 | rc = decode_imm(ctxt, &c->src, 1, false); |
dde7e6d1 AK |
3230 | break; |
3231 | case SrcAcc: | |
3232 | c->src.type = OP_REG; | |
3233 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 3234 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 3235 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
3236 | break; |
3237 | case SrcOne: | |
3238 | c->src.bytes = 1; | |
3239 | c->src.val = 1; | |
3240 | break; | |
3241 | case SrcSI: | |
3242 | c->src.type = OP_MEM; | |
3243 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
3244 | c->src.addr.mem.ea = |
3245 | register_address(c, c->regs[VCPU_REGS_RSI]); | |
3246 | c->src.addr.mem.seg = seg_override(ctxt, ops, c), | |
dde7e6d1 AK |
3247 | c->src.val = 0; |
3248 | break; | |
3249 | case SrcImmFAddr: | |
3250 | c->src.type = OP_IMM; | |
90de84f5 | 3251 | c->src.addr.mem.ea = c->eip; |
dde7e6d1 AK |
3252 | c->src.bytes = c->op_bytes + 2; |
3253 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
3254 | break; | |
3255 | case SrcMemFAddr: | |
2dbd0dd7 AK |
3256 | memop.bytes = c->op_bytes + 2; |
3257 | goto srcmem_common; | |
dde7e6d1 AK |
3258 | break; |
3259 | } | |
3260 | ||
39f21ee5 AK |
3261 | if (rc != X86EMUL_CONTINUE) |
3262 | goto done; | |
3263 | ||
dde7e6d1 AK |
3264 | /* |
3265 | * Decode and fetch the second source operand: register, memory | |
3266 | * or immediate. | |
3267 | */ | |
3268 | switch (c->d & Src2Mask) { | |
3269 | case Src2None: | |
3270 | break; | |
3271 | case Src2CL: | |
3272 | c->src2.bytes = 1; | |
3273 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
3274 | break; | |
3275 | case Src2ImmByte: | |
39f21ee5 | 3276 | rc = decode_imm(ctxt, &c->src2, 1, true); |
dde7e6d1 AK |
3277 | break; |
3278 | case Src2One: | |
3279 | c->src2.bytes = 1; | |
3280 | c->src2.val = 1; | |
3281 | break; | |
7db41eb7 AK |
3282 | case Src2Imm: |
3283 | rc = decode_imm(ctxt, &c->src2, imm_size(c), true); | |
3284 | break; | |
dde7e6d1 AK |
3285 | } |
3286 | ||
39f21ee5 AK |
3287 | if (rc != X86EMUL_CONTINUE) |
3288 | goto done; | |
3289 | ||
dde7e6d1 AK |
3290 | /* Decode and fetch the destination operand: register or memory. */ |
3291 | switch (c->d & DstMask) { | |
dde7e6d1 | 3292 | case DstReg: |
1253791d | 3293 | decode_register_operand(ctxt, &c->dst, c, |
dde7e6d1 AK |
3294 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
3295 | break; | |
943858e2 WY |
3296 | case DstImmUByte: |
3297 | c->dst.type = OP_IMM; | |
90de84f5 | 3298 | c->dst.addr.mem.ea = c->eip; |
943858e2 WY |
3299 | c->dst.bytes = 1; |
3300 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
3301 | break; | |
dde7e6d1 AK |
3302 | case DstMem: |
3303 | case DstMem64: | |
2dbd0dd7 | 3304 | c->dst = memop; |
dde7e6d1 AK |
3305 | if ((c->d & DstMask) == DstMem64) |
3306 | c->dst.bytes = 8; | |
3307 | else | |
3308 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
3309 | if (c->d & BitOp) |
3310 | fetch_bit_operand(c); | |
2dbd0dd7 | 3311 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
3312 | break; |
3313 | case DstAcc: | |
3314 | c->dst.type = OP_REG; | |
3315 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 3316 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 3317 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
3318 | c->dst.orig_val = c->dst.val; |
3319 | break; | |
3320 | case DstDI: | |
3321 | c->dst.type = OP_MEM; | |
3322 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
3323 | c->dst.addr.mem.ea = |
3324 | register_address(c, c->regs[VCPU_REGS_RDI]); | |
3325 | c->dst.addr.mem.seg = VCPU_SREG_ES; | |
dde7e6d1 AK |
3326 | c->dst.val = 0; |
3327 | break; | |
36089fed WY |
3328 | case ImplicitOps: |
3329 | /* Special instructions do their own operand decoding. */ | |
3330 | default: | |
3331 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3332 | return 0; | |
dde7e6d1 AK |
3333 | } |
3334 | ||
3335 | done: | |
a0c0ab2f | 3336 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
3337 | } |
3338 | ||
3e2f65d5 GN |
3339 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
3340 | { | |
3341 | struct decode_cache *c = &ctxt->decode; | |
3342 | ||
3343 | /* The second termination condition only applies for REPE | |
3344 | * and REPNE. Test if the repeat string operation prefix is | |
3345 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3346 | * corresponding termination condition according to: | |
3347 | * - if REPE/REPZ and ZF = 0 then done | |
3348 | * - if REPNE/REPNZ and ZF = 1 then done | |
3349 | */ | |
3350 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
3351 | (c->b == 0xae) || (c->b == 0xaf)) | |
3352 | && (((c->rep_prefix == REPE_PREFIX) && | |
3353 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
3354 | || ((c->rep_prefix == REPNE_PREFIX) && | |
3355 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
3356 | return true; | |
3357 | ||
3358 | return false; | |
3359 | } | |
3360 | ||
8b4caf66 | 3361 | int |
9aabc88f | 3362 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 3363 | { |
9aabc88f | 3364 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 3365 | u64 msr_data; |
8b4caf66 | 3366 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 3367 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 3368 | int saved_dst_type = c->dst.type; |
6e154e56 | 3369 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 3370 | |
9de41573 | 3371 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 3372 | |
1161624f | 3373 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
35d3d4a1 | 3374 | rc = emulate_ud(ctxt); |
1161624f GN |
3375 | goto done; |
3376 | } | |
3377 | ||
d380a5e4 | 3378 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 3379 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
35d3d4a1 | 3380 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
3381 | goto done; |
3382 | } | |
3383 | ||
081bca0e | 3384 | if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) { |
35d3d4a1 | 3385 | rc = emulate_ud(ctxt); |
081bca0e AK |
3386 | goto done; |
3387 | } | |
3388 | ||
1253791d AK |
3389 | if ((c->d & Sse) |
3390 | && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM) | |
3391 | || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) { | |
3392 | rc = emulate_ud(ctxt); | |
3393 | goto done; | |
3394 | } | |
3395 | ||
3396 | if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) { | |
3397 | rc = emulate_nm(ctxt); | |
3398 | goto done; | |
3399 | } | |
3400 | ||
c4f035c6 | 3401 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3402 | rc = emulator_check_intercept(ctxt, c->intercept, |
3403 | X86_ICPT_PRE_EXCEPT); | |
c4f035c6 AK |
3404 | if (rc != X86EMUL_CONTINUE) |
3405 | goto done; | |
3406 | } | |
3407 | ||
e92805ac | 3408 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 3409 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
35d3d4a1 | 3410 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
3411 | goto done; |
3412 | } | |
3413 | ||
8ea7d6ae JR |
3414 | /* Instruction can only be executed in protected mode */ |
3415 | if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { | |
3416 | rc = emulate_ud(ctxt); | |
3417 | goto done; | |
3418 | } | |
3419 | ||
d09beabd JR |
3420 | /* Do instruction specific permission checks */ |
3421 | if (c->check_perm) { | |
3422 | rc = c->check_perm(ctxt); | |
3423 | if (rc != X86EMUL_CONTINUE) | |
3424 | goto done; | |
3425 | } | |
3426 | ||
c4f035c6 | 3427 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3428 | rc = emulator_check_intercept(ctxt, c->intercept, |
3429 | X86_ICPT_POST_EXCEPT); | |
c4f035c6 AK |
3430 | if (rc != X86EMUL_CONTINUE) |
3431 | goto done; | |
3432 | } | |
3433 | ||
b9fa9d6b AK |
3434 | if (c->rep_prefix && (c->d & String)) { |
3435 | /* All REP prefixes have the same first termination condition */ | |
c73e197b | 3436 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
95c55886 | 3437 | ctxt->eip = c->eip; |
b9fa9d6b AK |
3438 | goto done; |
3439 | } | |
b9fa9d6b AK |
3440 | } |
3441 | ||
c483c02a | 3442 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
90de84f5 | 3443 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem), |
414e6277 | 3444 | c->src.valptr, c->src.bytes); |
b60d513c | 3445 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 3446 | goto done; |
16518d5a | 3447 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
3448 | } |
3449 | ||
e35b7b9c | 3450 | if (c->src2.type == OP_MEM) { |
90de84f5 | 3451 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem), |
9de41573 | 3452 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
3453 | if (rc != X86EMUL_CONTINUE) |
3454 | goto done; | |
3455 | } | |
3456 | ||
8b4caf66 LV |
3457 | if ((c->d & DstMask) == ImplicitOps) |
3458 | goto special_insn; | |
3459 | ||
3460 | ||
69f55cb1 GN |
3461 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
3462 | /* optimisation - avoid slow emulated read if Mov */ | |
90de84f5 | 3463 | rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem), |
9de41573 | 3464 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
3465 | if (rc != X86EMUL_CONTINUE) |
3466 | goto done; | |
038e51de | 3467 | } |
e4e03ded | 3468 | c->dst.orig_val = c->dst.val; |
038e51de | 3469 | |
018a98db AK |
3470 | special_insn: |
3471 | ||
c4f035c6 | 3472 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3473 | rc = emulator_check_intercept(ctxt, c->intercept, |
3474 | X86_ICPT_POST_MEMACCESS); | |
c4f035c6 AK |
3475 | if (rc != X86EMUL_CONTINUE) |
3476 | goto done; | |
3477 | } | |
3478 | ||
ef65c889 AK |
3479 | if (c->execute) { |
3480 | rc = c->execute(ctxt); | |
3481 | if (rc != X86EMUL_CONTINUE) | |
3482 | goto done; | |
3483 | goto writeback; | |
3484 | } | |
3485 | ||
e4e03ded | 3486 | if (c->twobyte) |
6aa8b732 AK |
3487 | goto twobyte_insn; |
3488 | ||
e4e03ded | 3489 | switch (c->b) { |
6aa8b732 AK |
3490 | case 0x00 ... 0x05: |
3491 | add: /* add */ | |
05f086f8 | 3492 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3493 | break; |
0934ac9d | 3494 | case 0x06: /* push es */ |
79168fd1 | 3495 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
3496 | break; |
3497 | case 0x07: /* pop es */ | |
0934ac9d | 3498 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d | 3499 | break; |
6aa8b732 AK |
3500 | case 0x08 ... 0x0d: |
3501 | or: /* or */ | |
05f086f8 | 3502 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3503 | break; |
0934ac9d | 3504 | case 0x0e: /* push cs */ |
79168fd1 | 3505 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 3506 | break; |
6aa8b732 AK |
3507 | case 0x10 ... 0x15: |
3508 | adc: /* adc */ | |
05f086f8 | 3509 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3510 | break; |
0934ac9d | 3511 | case 0x16: /* push ss */ |
79168fd1 | 3512 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
3513 | break; |
3514 | case 0x17: /* pop ss */ | |
0934ac9d | 3515 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d | 3516 | break; |
6aa8b732 AK |
3517 | case 0x18 ... 0x1d: |
3518 | sbb: /* sbb */ | |
05f086f8 | 3519 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3520 | break; |
0934ac9d | 3521 | case 0x1e: /* push ds */ |
79168fd1 | 3522 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
3523 | break; |
3524 | case 0x1f: /* pop ds */ | |
0934ac9d | 3525 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d | 3526 | break; |
aa3a816b | 3527 | case 0x20 ... 0x25: |
6aa8b732 | 3528 | and: /* and */ |
05f086f8 | 3529 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3530 | break; |
3531 | case 0x28 ... 0x2d: | |
3532 | sub: /* sub */ | |
05f086f8 | 3533 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3534 | break; |
3535 | case 0x30 ... 0x35: | |
3536 | xor: /* xor */ | |
05f086f8 | 3537 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3538 | break; |
3539 | case 0x38 ... 0x3d: | |
3540 | cmp: /* cmp */ | |
05f086f8 | 3541 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3542 | break; |
33615aa9 AK |
3543 | case 0x40 ... 0x47: /* inc r16/r32 */ |
3544 | emulate_1op("inc", c->dst, ctxt->eflags); | |
3545 | break; | |
3546 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
3547 | emulate_1op("dec", c->dst, ctxt->eflags); | |
3548 | break; | |
33615aa9 AK |
3549 | case 0x58 ... 0x5f: /* pop reg */ |
3550 | pop_instruction: | |
350f69dc | 3551 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
33615aa9 | 3552 | break; |
abcf14b5 | 3553 | case 0x60: /* pusha */ |
c37eda13 | 3554 | rc = emulate_pusha(ctxt, ops); |
abcf14b5 MG |
3555 | break; |
3556 | case 0x61: /* popa */ | |
3557 | rc = emulate_popa(ctxt, ops); | |
abcf14b5 | 3558 | break; |
6aa8b732 | 3559 | case 0x63: /* movsxd */ |
8b4caf66 | 3560 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3561 | goto cannot_emulate; |
e4e03ded | 3562 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 3563 | break; |
018a98db AK |
3564 | case 0x6c: /* insb */ |
3565 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
3566 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3567 | goto do_io_in; | |
018a98db AK |
3568 | case 0x6e: /* outsb */ |
3569 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
3570 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
3571 | goto do_io_out; | |
7972995b | 3572 | break; |
b2833e3c | 3573 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 3574 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3575 | jmp_rel(c, c->src.val); |
018a98db | 3576 | break; |
6aa8b732 | 3577 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 3578 | switch (c->modrm_reg) { |
6aa8b732 AK |
3579 | case 0: |
3580 | goto add; | |
3581 | case 1: | |
3582 | goto or; | |
3583 | case 2: | |
3584 | goto adc; | |
3585 | case 3: | |
3586 | goto sbb; | |
3587 | case 4: | |
3588 | goto and; | |
3589 | case 5: | |
3590 | goto sub; | |
3591 | case 6: | |
3592 | goto xor; | |
3593 | case 7: | |
3594 | goto cmp; | |
3595 | } | |
3596 | break; | |
3597 | case 0x84 ... 0x85: | |
dfb507c4 | 3598 | test: |
05f086f8 | 3599 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3600 | break; |
3601 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 3602 | xchg: |
6aa8b732 | 3603 | /* Write back the register source. */ |
31be40b3 WY |
3604 | c->src.val = c->dst.val; |
3605 | write_register_operand(&c->src); | |
6aa8b732 AK |
3606 | /* |
3607 | * Write back the memory destination with implicit LOCK | |
3608 | * prefix. | |
3609 | */ | |
31be40b3 | 3610 | c->dst.val = c->src.orig_val; |
e4e03ded | 3611 | c->lock_prefix = 1; |
6aa8b732 | 3612 | break; |
79168fd1 GN |
3613 | case 0x8c: /* mov r/m, sreg */ |
3614 | if (c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3615 | rc = emulate_ud(ctxt); |
5e3ae6c5 | 3616 | goto done; |
38d5bc6d | 3617 | } |
79168fd1 | 3618 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3619 | break; |
7e0b54b1 | 3620 | case 0x8d: /* lea r16/r32, m */ |
90de84f5 | 3621 | c->dst.val = c->src.addr.mem.ea; |
7e0b54b1 | 3622 | break; |
4257198a GT |
3623 | case 0x8e: { /* mov seg, r/m16 */ |
3624 | uint16_t sel; | |
4257198a GT |
3625 | |
3626 | sel = c->src.val; | |
8b9f4414 | 3627 | |
c697518a GN |
3628 | if (c->modrm_reg == VCPU_SREG_CS || |
3629 | c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3630 | rc = emulate_ud(ctxt); |
8b9f4414 GN |
3631 | goto done; |
3632 | } | |
3633 | ||
310b5d30 | 3634 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3635 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3636 | |
2e873022 | 3637 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3638 | |
3639 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3640 | break; | |
3641 | } | |
6aa8b732 | 3642 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3643 | rc = emulate_grp1a(ctxt, ops); |
6aa8b732 | 3644 | break; |
3d9e77df AK |
3645 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3646 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3647 | break; |
b13354f8 | 3648 | goto xchg; |
e8b6fa70 WY |
3649 | case 0x98: /* cbw/cwde/cdqe */ |
3650 | switch (c->op_bytes) { | |
3651 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3652 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3653 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3654 | } | |
3655 | break; | |
fd2a7608 | 3656 | case 0x9c: /* pushf */ |
05f086f8 | 3657 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3658 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3659 | break; |
535eabcf | 3660 | case 0x9d: /* popf */ |
2b48cc75 | 3661 | c->dst.type = OP_REG; |
1a6440ae | 3662 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3663 | c->dst.bytes = c->op_bytes; |
d4c6a154 | 3664 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
d4c6a154 | 3665 | break; |
6aa8b732 | 3666 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3667 | c->dst.type = OP_NONE; /* Disable writeback. */ |
a682e354 | 3668 | goto cmp; |
dfb507c4 MG |
3669 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3670 | goto test; | |
6aa8b732 | 3671 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3672 | goto cmp; |
018a98db AK |
3673 | case 0xc0 ... 0xc1: |
3674 | emulate_grp2(ctxt); | |
3675 | break; | |
111de5d6 | 3676 | case 0xc3: /* ret */ |
cf5de4f8 | 3677 | c->dst.type = OP_REG; |
1a6440ae | 3678 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3679 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3680 | goto pop_instruction; |
09b5f4d3 WY |
3681 | case 0xc4: /* les */ |
3682 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES); | |
09b5f4d3 WY |
3683 | break; |
3684 | case 0xc5: /* lds */ | |
3685 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS); | |
09b5f4d3 | 3686 | break; |
a77ab5ea AK |
3687 | case 0xcb: /* ret far */ |
3688 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e | 3689 | break; |
6e154e56 MG |
3690 | case 0xcc: /* int3 */ |
3691 | irq = 3; | |
3692 | goto do_interrupt; | |
3693 | case 0xcd: /* int n */ | |
3694 | irq = c->src.val; | |
3695 | do_interrupt: | |
3696 | rc = emulate_int(ctxt, ops, irq); | |
6e154e56 MG |
3697 | break; |
3698 | case 0xce: /* into */ | |
3699 | if (ctxt->eflags & EFLG_OF) { | |
3700 | irq = 4; | |
3701 | goto do_interrupt; | |
3702 | } | |
3703 | break; | |
62bd430e MG |
3704 | case 0xcf: /* iret */ |
3705 | rc = emulate_iret(ctxt, ops); | |
a77ab5ea | 3706 | break; |
018a98db | 3707 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3708 | emulate_grp2(ctxt); |
3709 | break; | |
3710 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3711 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3712 | emulate_grp2(ctxt); | |
3713 | break; | |
f2f31845 WY |
3714 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3715 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3716 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3717 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3718 | jmp_rel(c, c->src.val); | |
3719 | break; | |
e4abac67 WY |
3720 | case 0xe3: /* jcxz/jecxz/jrcxz */ |
3721 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) | |
3722 | jmp_rel(c, c->src.val); | |
3723 | break; | |
a6a3034c MG |
3724 | case 0xe4: /* inb */ |
3725 | case 0xe5: /* in */ | |
cf8f70bf | 3726 | goto do_io_in; |
a6a3034c MG |
3727 | case 0xe6: /* outb */ |
3728 | case 0xe7: /* out */ | |
cf8f70bf | 3729 | goto do_io_out; |
1a52e051 | 3730 | case 0xe8: /* call (near) */ { |
d53c4777 | 3731 | long int rel = c->src.val; |
e4e03ded | 3732 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3733 | jmp_rel(c, rel); |
79168fd1 | 3734 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3735 | break; |
1a52e051 NK |
3736 | } |
3737 | case 0xe9: /* jmp rel */ | |
954cd36f | 3738 | goto jmp; |
414e6277 GN |
3739 | case 0xea: { /* jmp far */ |
3740 | unsigned short sel; | |
ea79849d | 3741 | jump_far: |
414e6277 GN |
3742 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3743 | ||
3744 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3745 | goto done; |
954cd36f | 3746 | |
414e6277 GN |
3747 | c->eip = 0; |
3748 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3749 | break; |
414e6277 | 3750 | } |
954cd36f GT |
3751 | case 0xeb: |
3752 | jmp: /* jmp rel short */ | |
7a957275 | 3753 | jmp_rel(c, c->src.val); |
a01af5ec | 3754 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3755 | break; |
a6a3034c MG |
3756 | case 0xec: /* in al,dx */ |
3757 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3758 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3759 | do_io_in: | |
7b262e90 GN |
3760 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3761 | &c->dst.val)) | |
cf8f70bf GN |
3762 | goto done; /* IO is needed */ |
3763 | break; | |
ce7a0ad3 WY |
3764 | case 0xee: /* out dx,al */ |
3765 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3766 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3767 | do_io_out: |
41167be5 WY |
3768 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3769 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3770 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3771 | break; |
111de5d6 | 3772 | case 0xf4: /* hlt */ |
ad312c7c | 3773 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3774 | break; |
111de5d6 AK |
3775 | case 0xf5: /* cmc */ |
3776 | /* complement carry flag from eflags reg */ | |
3777 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3778 | break; |
018a98db | 3779 | case 0xf6 ... 0xf7: /* Grp3 */ |
34d1f490 | 3780 | rc = emulate_grp3(ctxt, ops); |
018a98db | 3781 | break; |
111de5d6 AK |
3782 | case 0xf8: /* clc */ |
3783 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3784 | break; |
8744aa9a MG |
3785 | case 0xf9: /* stc */ |
3786 | ctxt->eflags |= EFLG_CF; | |
3787 | break; | |
111de5d6 | 3788 | case 0xfa: /* cli */ |
07cbc6c1 | 3789 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3790 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 | 3791 | goto done; |
36089fed | 3792 | } else |
f850e2e6 | 3793 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3794 | break; |
3795 | case 0xfb: /* sti */ | |
07cbc6c1 | 3796 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3797 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3798 | goto done; |
3799 | } else { | |
95cb2295 | 3800 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3801 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3802 | } |
111de5d6 | 3803 | break; |
fb4616f4 MG |
3804 | case 0xfc: /* cld */ |
3805 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3806 | break; |
3807 | case 0xfd: /* std */ | |
3808 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3809 | break; |
ea79849d GN |
3810 | case 0xfe: /* Grp4 */ |
3811 | grp45: | |
018a98db | 3812 | rc = emulate_grp45(ctxt, ops); |
018a98db | 3813 | break; |
ea79849d GN |
3814 | case 0xff: /* Grp5 */ |
3815 | if (c->modrm_reg == 5) | |
3816 | goto jump_far; | |
3817 | goto grp45; | |
91269b8f AK |
3818 | default: |
3819 | goto cannot_emulate; | |
6aa8b732 | 3820 | } |
018a98db | 3821 | |
7d9ddaed AK |
3822 | if (rc != X86EMUL_CONTINUE) |
3823 | goto done; | |
3824 | ||
018a98db AK |
3825 | writeback: |
3826 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3827 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3828 | goto done; |
3829 | ||
5cd21917 GN |
3830 | /* |
3831 | * restore dst type in case the decoding will be reused | |
3832 | * (happens for string instruction ) | |
3833 | */ | |
3834 | c->dst.type = saved_dst_type; | |
3835 | ||
a682e354 | 3836 | if ((c->d & SrcMask) == SrcSI) |
90de84f5 | 3837 | string_addr_inc(ctxt, seg_override(ctxt, ops, c), |
79168fd1 | 3838 | VCPU_REGS_RSI, &c->src); |
a682e354 GN |
3839 | |
3840 | if ((c->d & DstMask) == DstDI) | |
90de84f5 | 3841 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
79168fd1 | 3842 | &c->dst); |
d9271123 | 3843 | |
5cd21917 | 3844 | if (c->rep_prefix && (c->d & String)) { |
6e2fb2ca | 3845 | struct read_cache *r = &ctxt->decode.io_read; |
d9271123 | 3846 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
3e2f65d5 | 3847 | |
d2ddd1c4 GN |
3848 | if (!string_insn_completed(ctxt)) { |
3849 | /* | |
3850 | * Re-enter guest when pio read ahead buffer is empty | |
3851 | * or, if it is not used, after each 1024 iteration. | |
3852 | */ | |
3853 | if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) && | |
3854 | (r->end == 0 || r->end != r->pos)) { | |
3855 | /* | |
3856 | * Reset read cache. Usually happens before | |
3857 | * decode, but since instruction is restarted | |
3858 | * we have to do it here. | |
3859 | */ | |
3860 | ctxt->decode.mem_read.end = 0; | |
3861 | return EMULATION_RESTART; | |
3862 | } | |
3863 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 3864 | } |
5cd21917 | 3865 | } |
d2ddd1c4 GN |
3866 | |
3867 | ctxt->eip = c->eip; | |
018a98db AK |
3868 | |
3869 | done: | |
da9cb575 AK |
3870 | if (rc == X86EMUL_PROPAGATE_FAULT) |
3871 | ctxt->have_exception = true; | |
775fde86 JR |
3872 | if (rc == X86EMUL_INTERCEPTED) |
3873 | return EMULATION_INTERCEPTED; | |
3874 | ||
d2ddd1c4 | 3875 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
3876 | |
3877 | twobyte_insn: | |
e4e03ded | 3878 | switch (c->b) { |
6aa8b732 | 3879 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3880 | switch (c->modrm_reg) { |
6aa8b732 AK |
3881 | u16 size; |
3882 | unsigned long address; | |
3883 | ||
aca7f966 | 3884 | case 0: /* vmcall */ |
e4e03ded | 3885 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3886 | goto cannot_emulate; |
3887 | ||
7aa81cc0 | 3888 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3889 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3890 | goto done; |
3891 | ||
33e3885d | 3892 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3893 | c->eip = ctxt->eip; |
16286d08 AK |
3894 | /* Disable writeback. */ |
3895 | c->dst.type = OP_NONE; | |
aca7f966 | 3896 | break; |
6aa8b732 | 3897 | case 2: /* lgdt */ |
1a6440ae | 3898 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3899 | &size, &address, c->op_bytes); |
1b30eaa8 | 3900 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3901 | goto done; |
3902 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3903 | /* Disable writeback. */ |
3904 | c->dst.type = OP_NONE; | |
6aa8b732 | 3905 | break; |
aca7f966 | 3906 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3907 | if (c->modrm_mod == 3) { |
3908 | switch (c->modrm_rm) { | |
3909 | case 1: | |
3910 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
2b3d2a20 AK |
3911 | break; |
3912 | default: | |
3913 | goto cannot_emulate; | |
3914 | } | |
aca7f966 | 3915 | } else { |
1a6440ae | 3916 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3917 | &size, &address, |
e4e03ded | 3918 | c->op_bytes); |
1b30eaa8 | 3919 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3920 | goto done; |
3921 | realmode_lidt(ctxt->vcpu, size, address); | |
3922 | } | |
16286d08 AK |
3923 | /* Disable writeback. */ |
3924 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3925 | break; |
3926 | case 4: /* smsw */ | |
16286d08 | 3927 | c->dst.bytes = 2; |
52a46617 | 3928 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3929 | break; |
3930 | case 6: /* lmsw */ | |
9928ff60 | 3931 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3932 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3933 | c->dst.type = OP_NONE; |
6aa8b732 | 3934 | break; |
6e1e5ffe | 3935 | case 5: /* not defined */ |
54b8486f | 3936 | emulate_ud(ctxt); |
da9cb575 | 3937 | rc = X86EMUL_PROPAGATE_FAULT; |
6e1e5ffe | 3938 | goto done; |
6aa8b732 | 3939 | case 7: /* invlpg*/ |
90de84f5 AK |
3940 | emulate_invlpg(ctxt->vcpu, |
3941 | linear(ctxt, c->src.addr.mem)); | |
16286d08 AK |
3942 | /* Disable writeback. */ |
3943 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3944 | break; |
3945 | default: | |
3946 | goto cannot_emulate; | |
3947 | } | |
3948 | break; | |
e99f0507 | 3949 | case 0x05: /* syscall */ |
3fb1b5db | 3950 | rc = emulate_syscall(ctxt, ops); |
e99f0507 | 3951 | break; |
018a98db AK |
3952 | case 0x06: |
3953 | emulate_clts(ctxt->vcpu); | |
018a98db | 3954 | break; |
018a98db | 3955 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3956 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3957 | break; |
3958 | case 0x08: /* invd */ | |
018a98db AK |
3959 | case 0x0d: /* GrpP (prefetch) */ |
3960 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3961 | break; |
3962 | case 0x20: /* mov cr, reg */ | |
1a0c7d44 | 3963 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3964 | break; |
6aa8b732 | 3965 | case 0x21: /* mov from dr to reg */ |
b27f3856 | 3966 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3967 | break; |
018a98db | 3968 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3969 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3970 | emulate_gp(ctxt, 0); |
da9cb575 | 3971 | rc = X86EMUL_PROPAGATE_FAULT; |
0f12244f GN |
3972 | goto done; |
3973 | } | |
018a98db AK |
3974 | c->dst.type = OP_NONE; |
3975 | break; | |
6aa8b732 | 3976 | case 0x23: /* mov from reg to dr */ |
b27f3856 | 3977 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3978 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3979 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3980 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3981 | emulate_gp(ctxt, 0); |
da9cb575 | 3982 | rc = X86EMUL_PROPAGATE_FAULT; |
338dbc97 GN |
3983 | goto done; |
3984 | } | |
3985 | ||
a01af5ec | 3986 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3987 | break; |
018a98db AK |
3988 | case 0x30: |
3989 | /* wrmsr */ | |
3990 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3991 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3992 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3993 | emulate_gp(ctxt, 0); |
da9cb575 | 3994 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 3995 | goto done; |
018a98db AK |
3996 | } |
3997 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3998 | break; |
3999 | case 0x32: | |
4000 | /* rdmsr */ | |
3fb1b5db | 4001 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 4002 | emulate_gp(ctxt, 0); |
da9cb575 | 4003 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 4004 | goto done; |
018a98db AK |
4005 | } else { |
4006 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
4007 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
4008 | } | |
4009 | rc = X86EMUL_CONTINUE; | |
018a98db | 4010 | break; |
e99f0507 | 4011 | case 0x34: /* sysenter */ |
3fb1b5db | 4012 | rc = emulate_sysenter(ctxt, ops); |
e99f0507 AP |
4013 | break; |
4014 | case 0x35: /* sysexit */ | |
3fb1b5db | 4015 | rc = emulate_sysexit(ctxt, ops); |
e99f0507 | 4016 | break; |
6aa8b732 | 4017 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 4018 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
4019 | if (!test_cc(c->b, ctxt->eflags)) |
4020 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4021 | break; |
b2833e3c | 4022 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 4023 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 4024 | jmp_rel(c, c->src.val); |
018a98db | 4025 | break; |
ee45b58e WY |
4026 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
4027 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
4028 | break; | |
0934ac9d | 4029 | case 0xa0: /* push fs */ |
79168fd1 | 4030 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
4031 | break; |
4032 | case 0xa1: /* pop fs */ | |
4033 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
0934ac9d | 4034 | break; |
7de75248 NK |
4035 | case 0xa3: |
4036 | bt: /* bt */ | |
e4f8e039 | 4037 | c->dst.type = OP_NONE; |
e4e03ded LV |
4038 | /* only subword offset */ |
4039 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 4040 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 4041 | break; |
9bf8ea42 GT |
4042 | case 0xa4: /* shld imm8, r, r/m */ |
4043 | case 0xa5: /* shld cl, r, r/m */ | |
4044 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
4045 | break; | |
0934ac9d | 4046 | case 0xa8: /* push gs */ |
79168fd1 | 4047 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
4048 | break; |
4049 | case 0xa9: /* pop gs */ | |
4050 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
0934ac9d | 4051 | break; |
7de75248 NK |
4052 | case 0xab: |
4053 | bts: /* bts */ | |
05f086f8 | 4054 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 4055 | break; |
9bf8ea42 GT |
4056 | case 0xac: /* shrd imm8, r, r/m */ |
4057 | case 0xad: /* shrd cl, r, r/m */ | |
4058 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
4059 | break; | |
2a7c5b8b GC |
4060 | case 0xae: /* clflush */ |
4061 | break; | |
6aa8b732 AK |
4062 | case 0xb0 ... 0xb1: /* cmpxchg */ |
4063 | /* | |
4064 | * Save real source value, then compare EAX against | |
4065 | * destination. | |
4066 | */ | |
e4e03ded LV |
4067 | c->src.orig_val = c->src.val; |
4068 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
4069 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
4070 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 4071 | /* Success: write back to memory. */ |
e4e03ded | 4072 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
4073 | } else { |
4074 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 4075 | c->dst.type = OP_REG; |
1a6440ae | 4076 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
4077 | } |
4078 | break; | |
09b5f4d3 WY |
4079 | case 0xb2: /* lss */ |
4080 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS); | |
09b5f4d3 | 4081 | break; |
6aa8b732 AK |
4082 | case 0xb3: |
4083 | btr: /* btr */ | |
05f086f8 | 4084 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 4085 | break; |
09b5f4d3 WY |
4086 | case 0xb4: /* lfs */ |
4087 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS); | |
09b5f4d3 WY |
4088 | break; |
4089 | case 0xb5: /* lgs */ | |
4090 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS); | |
09b5f4d3 | 4091 | break; |
6aa8b732 | 4092 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
4093 | c->dst.bytes = c->op_bytes; |
4094 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
4095 | : (u16) c->src.val; | |
6aa8b732 | 4096 | break; |
6aa8b732 | 4097 | case 0xba: /* Grp8 */ |
e4e03ded | 4098 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
4099 | case 0: |
4100 | goto bt; | |
4101 | case 1: | |
4102 | goto bts; | |
4103 | case 2: | |
4104 | goto btr; | |
4105 | case 3: | |
4106 | goto btc; | |
4107 | } | |
4108 | break; | |
7de75248 NK |
4109 | case 0xbb: |
4110 | btc: /* btc */ | |
05f086f8 | 4111 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 4112 | break; |
d9574a25 WY |
4113 | case 0xbc: { /* bsf */ |
4114 | u8 zf; | |
4115 | __asm__ ("bsf %2, %0; setz %1" | |
4116 | : "=r"(c->dst.val), "=q"(zf) | |
4117 | : "r"(c->src.val)); | |
4118 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
4119 | if (zf) { | |
4120 | ctxt->eflags |= X86_EFLAGS_ZF; | |
4121 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
4122 | } | |
4123 | break; | |
4124 | } | |
4125 | case 0xbd: { /* bsr */ | |
4126 | u8 zf; | |
4127 | __asm__ ("bsr %2, %0; setz %1" | |
4128 | : "=r"(c->dst.val), "=q"(zf) | |
4129 | : "r"(c->src.val)); | |
4130 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
4131 | if (zf) { | |
4132 | ctxt->eflags |= X86_EFLAGS_ZF; | |
4133 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
4134 | } | |
4135 | break; | |
4136 | } | |
6aa8b732 | 4137 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
4138 | c->dst.bytes = c->op_bytes; |
4139 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
4140 | (s16) c->src.val; | |
6aa8b732 | 4141 | break; |
92f738a5 WY |
4142 | case 0xc0 ... 0xc1: /* xadd */ |
4143 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
4144 | /* Write back the register source. */ | |
4145 | c->src.val = c->dst.orig_val; | |
4146 | write_register_operand(&c->src); | |
4147 | break; | |
a012e65a | 4148 | case 0xc3: /* movnti */ |
e4e03ded LV |
4149 | c->dst.bytes = c->op_bytes; |
4150 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
4151 | (u64) c->src.val; | |
a012e65a | 4152 | break; |
6aa8b732 | 4153 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 4154 | rc = emulate_grp9(ctxt, ops); |
8cdbd2c9 | 4155 | break; |
91269b8f AK |
4156 | default: |
4157 | goto cannot_emulate; | |
6aa8b732 | 4158 | } |
7d9ddaed AK |
4159 | |
4160 | if (rc != X86EMUL_CONTINUE) | |
4161 | goto done; | |
4162 | ||
6aa8b732 AK |
4163 | goto writeback; |
4164 | ||
4165 | cannot_emulate: | |
a0c0ab2f | 4166 | return EMULATION_FAILED; |
6aa8b732 | 4167 | } |