Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
b7d491e7 | 27 | #include <linux/stringify.h> |
6aa8b732 | 28 | |
3eeb3288 | 29 | #include "x86.h" |
38ba30ba | 30 | #include "tss.h" |
e99f0507 | 31 | |
a9945549 AK |
32 | /* |
33 | * Operand types | |
34 | */ | |
b1ea50b2 AK |
35 | #define OpNone 0ull |
36 | #define OpImplicit 1ull /* No generic decode */ | |
37 | #define OpReg 2ull /* Register */ | |
38 | #define OpMem 3ull /* Memory */ | |
39 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
40 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
41 | #define OpMem64 6ull /* Memory, 64-bit */ | |
42 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
43 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
44 | #define OpCL 9ull /* CL register (for shifts) */ |
45 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
46 | #define OpOne 11ull /* Implied 1 */ | |
5e2c6883 | 47 | #define OpImm 12ull /* Sign extended up to 32-bit immediate */ |
0fe59128 AK |
48 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
49 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
50 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
51 | #define OpSI 16ull /* SI/ESI/RSI */ | |
52 | #define OpImmFAddr 17ull /* Immediate far address */ | |
53 | #define OpMemFAddr 18ull /* Far address in memory */ | |
54 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
55 | #define OpES 20ull /* ES */ |
56 | #define OpCS 21ull /* CS */ | |
57 | #define OpSS 22ull /* SS */ | |
58 | #define OpDS 23ull /* DS */ | |
59 | #define OpFS 24ull /* FS */ | |
60 | #define OpGS 25ull /* GS */ | |
28867cee | 61 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
5e2c6883 | 62 | #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ |
7fa57952 | 63 | #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ |
820207c8 AK |
64 | #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ |
65 | #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ | |
0fe59128 AK |
66 | |
67 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 68 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 69 | |
6aa8b732 AK |
70 | /* |
71 | * Opcode effective-address decode tables. | |
72 | * Note that we only emulate instructions that have at least one memory | |
73 | * operand (excluding implicit stack references). We assume that stack | |
74 | * references and instruction fetches will never occur in special memory | |
75 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
76 | * not be handled. | |
77 | */ | |
78 | ||
79 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 80 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 81 | /* Destination operand type. */ |
a9945549 AK |
82 | #define DstShift 1 |
83 | #define ImplicitOps (OpImplicit << DstShift) | |
84 | #define DstReg (OpReg << DstShift) | |
85 | #define DstMem (OpMem << DstShift) | |
86 | #define DstAcc (OpAcc << DstShift) | |
87 | #define DstDI (OpDI << DstShift) | |
88 | #define DstMem64 (OpMem64 << DstShift) | |
16bebefe | 89 | #define DstMem16 (OpMem16 << DstShift) |
a9945549 AK |
90 | #define DstImmUByte (OpImmUByte << DstShift) |
91 | #define DstDX (OpDX << DstShift) | |
820207c8 | 92 | #define DstAccLo (OpAccLo << DstShift) |
a9945549 | 93 | #define DstMask (OpMask << DstShift) |
6aa8b732 | 94 | /* Source operand type. */ |
0fe59128 AK |
95 | #define SrcShift 6 |
96 | #define SrcNone (OpNone << SrcShift) | |
97 | #define SrcReg (OpReg << SrcShift) | |
98 | #define SrcMem (OpMem << SrcShift) | |
99 | #define SrcMem16 (OpMem16 << SrcShift) | |
100 | #define SrcMem32 (OpMem32 << SrcShift) | |
101 | #define SrcImm (OpImm << SrcShift) | |
102 | #define SrcImmByte (OpImmByte << SrcShift) | |
103 | #define SrcOne (OpOne << SrcShift) | |
104 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
105 | #define SrcImmU (OpImmU << SrcShift) | |
106 | #define SrcSI (OpSI << SrcShift) | |
7fa57952 | 107 | #define SrcXLat (OpXLat << SrcShift) |
0fe59128 AK |
108 | #define SrcImmFAddr (OpImmFAddr << SrcShift) |
109 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
110 | #define SrcAcc (OpAcc << SrcShift) | |
111 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
5e2c6883 | 112 | #define SrcImm64 (OpImm64 << SrcShift) |
0fe59128 | 113 | #define SrcDX (OpDX << SrcShift) |
28867cee | 114 | #define SrcMem8 (OpMem8 << SrcShift) |
820207c8 | 115 | #define SrcAccHi (OpAccHi << SrcShift) |
0fe59128 | 116 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
117 | #define BitOp (1<<11) |
118 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
119 | #define String (1<<13) /* String instruction (rep capable) */ | |
120 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
121 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
122 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
123 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
124 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
125 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
045a282c | 126 | #define Escape (5<<15) /* Escape to coprocessor instruction */ |
39f062ff | 127 | #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ |
2276b511 | 128 | #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ |
221192bd | 129 | #define Sse (1<<18) /* SSE Vector instruction */ |
20c29ff2 AK |
130 | /* Generic ModRM decode. */ |
131 | #define ModRM (1<<19) | |
132 | /* Destination is only written; never read. */ | |
133 | #define Mov (1<<20) | |
d8769fed | 134 | /* Misc flags */ |
8ea7d6ae | 135 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
b51e974f | 136 | #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ |
5a506b12 | 137 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 138 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 139 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 140 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 141 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 142 | #define No64 (1<<28) |
d5ae7ce8 | 143 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0b789eee | 144 | #define NotImpl (1 << 30) /* instruction is not implemented */ |
0dc8d10f | 145 | /* Source 2 operand type */ |
0b789eee | 146 | #define Src2Shift (31) |
4dd6a57d | 147 | #define Src2None (OpNone << Src2Shift) |
ab2c5ce6 | 148 | #define Src2Mem (OpMem << Src2Shift) |
4dd6a57d AK |
149 | #define Src2CL (OpCL << Src2Shift) |
150 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
151 | #define Src2One (OpOne << Src2Shift) | |
152 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
153 | #define Src2ES (OpES << Src2Shift) |
154 | #define Src2CS (OpCS << Src2Shift) | |
155 | #define Src2SS (OpSS << Src2Shift) | |
156 | #define Src2DS (OpDS << Src2Shift) | |
157 | #define Src2FS (OpFS << Src2Shift) | |
158 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 159 | #define Src2Mask (OpMask << Src2Shift) |
cbe2c9d3 | 160 | #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
1c11b376 AK |
161 | #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
162 | #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ | |
163 | #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ | |
e28bbd44 | 164 | #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ |
b6744dc3 | 165 | #define NoWrite ((u64)1 << 45) /* No writeback */ |
fb32b1ed | 166 | #define SrcWrite ((u64)1 << 46) /* Write back src operand */ |
9b88ae99 | 167 | #define NoMod ((u64)1 << 47) /* Mod field is ignored */ |
d40a6898 PB |
168 | #define Intercept ((u64)1 << 48) /* Has valid intercept field */ |
169 | #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ | |
68efa764 | 170 | #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ |
58b7075d | 171 | #define NearBranch ((u64)1 << 52) /* Near branches */ |
ed9aad21 | 172 | #define No16 ((u64)1 << 53) /* No 16 bit operand */ |
ab708099 | 173 | #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ |
6aa8b732 | 174 | |
820207c8 | 175 | #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) |
6aa8b732 | 176 | |
d0e53325 AK |
177 | #define X2(x...) x, x |
178 | #define X3(x...) X2(x), x | |
179 | #define X4(x...) X2(x), X2(x) | |
180 | #define X5(x...) X4(x), x | |
181 | #define X6(x...) X4(x), X2(x) | |
182 | #define X7(x...) X4(x), X3(x) | |
183 | #define X8(x...) X4(x), X4(x) | |
184 | #define X16(x...) X8(x), X8(x) | |
83babbca | 185 | |
e28bbd44 AK |
186 | #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) |
187 | #define FASTOP_SIZE 8 | |
188 | ||
189 | /* | |
190 | * fastop functions have a special calling convention: | |
191 | * | |
017da7b6 AK |
192 | * dst: rax (in/out) |
193 | * src: rdx (in/out) | |
e28bbd44 AK |
194 | * src2: rcx (in) |
195 | * flags: rflags (in/out) | |
b8c0b6ae | 196 | * ex: rsi (in:fastop pointer, out:zero if exception) |
e28bbd44 AK |
197 | * |
198 | * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for | |
199 | * different operand sizes can be reached by calculation, rather than a jump | |
200 | * table (which would be bigger than the code). | |
201 | * | |
202 | * fastop functions are declared as taking a never-defined fastop parameter, | |
203 | * so they can't be called from C directly. | |
204 | */ | |
205 | ||
206 | struct fastop; | |
207 | ||
d65b1dee | 208 | struct opcode { |
b1ea50b2 AK |
209 | u64 flags : 56; |
210 | u64 intercept : 8; | |
120df890 | 211 | union { |
ef65c889 | 212 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
fd0a0d82 MK |
213 | const struct opcode *group; |
214 | const struct group_dual *gdual; | |
215 | const struct gprefix *gprefix; | |
045a282c | 216 | const struct escape *esc; |
39f062ff | 217 | const struct instr_dual *idual; |
2276b511 | 218 | const struct mode_dual *mdual; |
e28bbd44 | 219 | void (*fastop)(struct fastop *fake); |
120df890 | 220 | } u; |
d09beabd | 221 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
222 | }; |
223 | ||
224 | struct group_dual { | |
225 | struct opcode mod012[8]; | |
226 | struct opcode mod3[8]; | |
d65b1dee AK |
227 | }; |
228 | ||
0d7cdee8 AK |
229 | struct gprefix { |
230 | struct opcode pfx_no; | |
231 | struct opcode pfx_66; | |
232 | struct opcode pfx_f2; | |
233 | struct opcode pfx_f3; | |
234 | }; | |
235 | ||
045a282c GN |
236 | struct escape { |
237 | struct opcode op[8]; | |
238 | struct opcode high[64]; | |
239 | }; | |
240 | ||
39f062ff NA |
241 | struct instr_dual { |
242 | struct opcode mod012; | |
243 | struct opcode mod3; | |
244 | }; | |
245 | ||
2276b511 NA |
246 | struct mode_dual { |
247 | struct opcode mode32; | |
248 | struct opcode mode64; | |
249 | }; | |
250 | ||
6aa8b732 | 251 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
252 | #define EFLG_ID (1<<21) |
253 | #define EFLG_VIP (1<<20) | |
254 | #define EFLG_VIF (1<<19) | |
255 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
256 | #define EFLG_VM (1<<17) |
257 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
258 | #define EFLG_IOPL (3<<12) |
259 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
260 | #define EFLG_OF (1<<11) |
261 | #define EFLG_DF (1<<10) | |
b1d86143 | 262 | #define EFLG_IF (1<<9) |
d4c6a154 | 263 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
264 | #define EFLG_SF (1<<7) |
265 | #define EFLG_ZF (1<<6) | |
266 | #define EFLG_AF (1<<4) | |
267 | #define EFLG_PF (1<<2) | |
268 | #define EFLG_CF (1<<0) | |
269 | ||
62bd430e MG |
270 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
271 | #define EFLG_RESERVED_ONE_MASK 2 | |
272 | ||
3dc4bc4f NA |
273 | enum x86_transfer_type { |
274 | X86_TRANSFER_NONE, | |
275 | X86_TRANSFER_CALL_JMP, | |
276 | X86_TRANSFER_RET, | |
277 | X86_TRANSFER_TASK_SWITCH, | |
278 | }; | |
279 | ||
dd856efa AK |
280 | static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) |
281 | { | |
282 | if (!(ctxt->regs_valid & (1 << nr))) { | |
283 | ctxt->regs_valid |= 1 << nr; | |
284 | ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); | |
285 | } | |
286 | return ctxt->_regs[nr]; | |
287 | } | |
288 | ||
289 | static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
290 | { | |
291 | ctxt->regs_valid |= 1 << nr; | |
292 | ctxt->regs_dirty |= 1 << nr; | |
293 | return &ctxt->_regs[nr]; | |
294 | } | |
295 | ||
296 | static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
297 | { | |
298 | reg_read(ctxt, nr); | |
299 | return reg_write(ctxt, nr); | |
300 | } | |
301 | ||
302 | static void writeback_registers(struct x86_emulate_ctxt *ctxt) | |
303 | { | |
304 | unsigned reg; | |
305 | ||
306 | for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) | |
307 | ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); | |
308 | } | |
309 | ||
310 | static void invalidate_registers(struct x86_emulate_ctxt *ctxt) | |
311 | { | |
312 | ctxt->regs_dirty = 0; | |
313 | ctxt->regs_valid = 0; | |
314 | } | |
315 | ||
6aa8b732 AK |
316 | /* |
317 | * These EFLAGS bits are restored from saved value during emulation, and | |
318 | * any changes are written back to the saved value after emulation. | |
319 | */ | |
320 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
321 | ||
dda96d8f AK |
322 | #ifdef CONFIG_X86_64 |
323 | #define ON64(x) x | |
324 | #else | |
325 | #define ON64(x) | |
326 | #endif | |
327 | ||
4d758349 AK |
328 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); |
329 | ||
b7d491e7 AK |
330 | #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" |
331 | #define FOP_RET "ret \n\t" | |
332 | ||
333 | #define FOP_START(op) \ | |
334 | extern void em_##op(struct fastop *fake); \ | |
335 | asm(".pushsection .text, \"ax\" \n\t" \ | |
336 | ".global em_" #op " \n\t" \ | |
337 | FOP_ALIGN \ | |
338 | "em_" #op ": \n\t" | |
339 | ||
340 | #define FOP_END \ | |
341 | ".popsection") | |
342 | ||
0bdea068 AK |
343 | #define FOPNOP() FOP_ALIGN FOP_RET |
344 | ||
b7d491e7 | 345 | #define FOP1E(op, dst) \ |
b8c0b6ae AK |
346 | FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET |
347 | ||
348 | #define FOP1EEX(op, dst) \ | |
349 | FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) | |
b7d491e7 AK |
350 | |
351 | #define FASTOP1(op) \ | |
352 | FOP_START(op) \ | |
353 | FOP1E(op##b, al) \ | |
354 | FOP1E(op##w, ax) \ | |
355 | FOP1E(op##l, eax) \ | |
356 | ON64(FOP1E(op##q, rax)) \ | |
357 | FOP_END | |
358 | ||
b9fa409b AK |
359 | /* 1-operand, using src2 (for MUL/DIV r/m) */ |
360 | #define FASTOP1SRC2(op, name) \ | |
361 | FOP_START(name) \ | |
362 | FOP1E(op, cl) \ | |
363 | FOP1E(op, cx) \ | |
364 | FOP1E(op, ecx) \ | |
365 | ON64(FOP1E(op, rcx)) \ | |
366 | FOP_END | |
367 | ||
b8c0b6ae AK |
368 | /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ |
369 | #define FASTOP1SRC2EX(op, name) \ | |
370 | FOP_START(name) \ | |
371 | FOP1EEX(op, cl) \ | |
372 | FOP1EEX(op, cx) \ | |
373 | FOP1EEX(op, ecx) \ | |
374 | ON64(FOP1EEX(op, rcx)) \ | |
375 | FOP_END | |
376 | ||
f7857f35 AK |
377 | #define FOP2E(op, dst, src) \ |
378 | FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET | |
379 | ||
380 | #define FASTOP2(op) \ | |
381 | FOP_START(op) \ | |
017da7b6 AK |
382 | FOP2E(op##b, al, dl) \ |
383 | FOP2E(op##w, ax, dx) \ | |
384 | FOP2E(op##l, eax, edx) \ | |
385 | ON64(FOP2E(op##q, rax, rdx)) \ | |
f7857f35 AK |
386 | FOP_END |
387 | ||
11c363ba AK |
388 | /* 2 operand, word only */ |
389 | #define FASTOP2W(op) \ | |
390 | FOP_START(op) \ | |
391 | FOPNOP() \ | |
017da7b6 AK |
392 | FOP2E(op##w, ax, dx) \ |
393 | FOP2E(op##l, eax, edx) \ | |
394 | ON64(FOP2E(op##q, rax, rdx)) \ | |
11c363ba AK |
395 | FOP_END |
396 | ||
007a3b54 AK |
397 | /* 2 operand, src is CL */ |
398 | #define FASTOP2CL(op) \ | |
399 | FOP_START(op) \ | |
400 | FOP2E(op##b, al, cl) \ | |
401 | FOP2E(op##w, ax, cl) \ | |
402 | FOP2E(op##l, eax, cl) \ | |
403 | ON64(FOP2E(op##q, rax, cl)) \ | |
404 | FOP_END | |
405 | ||
5aca3722 NA |
406 | /* 2 operand, src and dest are reversed */ |
407 | #define FASTOP2R(op, name) \ | |
408 | FOP_START(name) \ | |
409 | FOP2E(op##b, dl, al) \ | |
410 | FOP2E(op##w, dx, ax) \ | |
411 | FOP2E(op##l, edx, eax) \ | |
412 | ON64(FOP2E(op##q, rdx, rax)) \ | |
413 | FOP_END | |
414 | ||
0bdea068 AK |
415 | #define FOP3E(op, dst, src, src2) \ |
416 | FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET | |
417 | ||
418 | /* 3-operand, word-only, src2=cl */ | |
419 | #define FASTOP3WCL(op) \ | |
420 | FOP_START(op) \ | |
421 | FOPNOP() \ | |
017da7b6 AK |
422 | FOP3E(op##w, ax, dx, cl) \ |
423 | FOP3E(op##l, eax, edx, cl) \ | |
424 | ON64(FOP3E(op##q, rax, rdx, cl)) \ | |
0bdea068 AK |
425 | FOP_END |
426 | ||
9ae9feba AK |
427 | /* Special case for SETcc - 1 instruction per cc */ |
428 | #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" | |
429 | ||
b8c0b6ae AK |
430 | asm(".global kvm_fastop_exception \n" |
431 | "kvm_fastop_exception: xor %esi, %esi; ret"); | |
432 | ||
9ae9feba AK |
433 | FOP_START(setcc) |
434 | FOP_SETCC(seto) | |
435 | FOP_SETCC(setno) | |
436 | FOP_SETCC(setc) | |
437 | FOP_SETCC(setnc) | |
438 | FOP_SETCC(setz) | |
439 | FOP_SETCC(setnz) | |
440 | FOP_SETCC(setbe) | |
441 | FOP_SETCC(setnbe) | |
442 | FOP_SETCC(sets) | |
443 | FOP_SETCC(setns) | |
444 | FOP_SETCC(setp) | |
445 | FOP_SETCC(setnp) | |
446 | FOP_SETCC(setl) | |
447 | FOP_SETCC(setnl) | |
448 | FOP_SETCC(setle) | |
449 | FOP_SETCC(setnle) | |
450 | FOP_END; | |
451 | ||
326f578f PB |
452 | FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET |
453 | FOP_END; | |
454 | ||
8a76d7f2 JR |
455 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
456 | enum x86_intercept intercept, | |
457 | enum x86_intercept_stage stage) | |
458 | { | |
459 | struct x86_instruction_info info = { | |
460 | .intercept = intercept, | |
9dac77fa AK |
461 | .rep_prefix = ctxt->rep_prefix, |
462 | .modrm_mod = ctxt->modrm_mod, | |
463 | .modrm_reg = ctxt->modrm_reg, | |
464 | .modrm_rm = ctxt->modrm_rm, | |
465 | .src_val = ctxt->src.val64, | |
6cbc5f5a | 466 | .dst_val = ctxt->dst.val64, |
9dac77fa AK |
467 | .src_bytes = ctxt->src.bytes, |
468 | .dst_bytes = ctxt->dst.bytes, | |
469 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
470 | .next_rip = ctxt->eip, |
471 | }; | |
472 | ||
2953538e | 473 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
474 | } |
475 | ||
f47cfa31 AK |
476 | static void assign_masked(ulong *dest, ulong src, ulong mask) |
477 | { | |
478 | *dest = (*dest & ~mask) | (src & mask); | |
479 | } | |
480 | ||
6fd8e127 NA |
481 | static void assign_register(unsigned long *reg, u64 val, int bytes) |
482 | { | |
483 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
484 | switch (bytes) { | |
485 | case 1: | |
486 | *(u8 *)reg = (u8)val; | |
487 | break; | |
488 | case 2: | |
489 | *(u16 *)reg = (u16)val; | |
490 | break; | |
491 | case 4: | |
492 | *reg = (u32)val; | |
493 | break; /* 64b: zero-extend */ | |
494 | case 8: | |
495 | *reg = val; | |
496 | break; | |
497 | } | |
498 | } | |
499 | ||
9dac77fa | 500 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 501 | { |
9dac77fa | 502 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
503 | } |
504 | ||
f47cfa31 AK |
505 | static ulong stack_mask(struct x86_emulate_ctxt *ctxt) |
506 | { | |
507 | u16 sel; | |
508 | struct desc_struct ss; | |
509 | ||
510 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
511 | return ~0UL; | |
512 | ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); | |
513 | return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ | |
514 | } | |
515 | ||
612e89f0 AK |
516 | static int stack_size(struct x86_emulate_ctxt *ctxt) |
517 | { | |
518 | return (__fls(stack_mask(ctxt)) + 1) >> 3; | |
519 | } | |
520 | ||
6aa8b732 | 521 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 522 | static inline unsigned long |
9dac77fa | 523 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 524 | { |
9dac77fa | 525 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
526 | return reg; |
527 | else | |
9dac77fa | 528 | return reg & ad_mask(ctxt); |
e4706772 HH |
529 | } |
530 | ||
531 | static inline unsigned long | |
01485a22 | 532 | register_address(struct x86_emulate_ctxt *ctxt, int reg) |
e4706772 | 533 | { |
01485a22 | 534 | return address_mask(ctxt, reg_read(ctxt, reg)); |
e4706772 HH |
535 | } |
536 | ||
5ad105e5 AK |
537 | static void masked_increment(ulong *reg, ulong mask, int inc) |
538 | { | |
539 | assign_masked(reg, *reg + inc, mask); | |
540 | } | |
541 | ||
7a957275 | 542 | static inline void |
01485a22 | 543 | register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) |
7a957275 | 544 | { |
5ad105e5 AK |
545 | ulong mask; |
546 | ||
9dac77fa | 547 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
5ad105e5 | 548 | mask = ~0UL; |
7a957275 | 549 | else |
5ad105e5 | 550 | mask = ad_mask(ctxt); |
01485a22 | 551 | masked_increment(reg_rmw(ctxt, reg), mask, inc); |
5ad105e5 AK |
552 | } |
553 | ||
554 | static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) | |
555 | { | |
dd856efa | 556 | masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); |
7a957275 | 557 | } |
6aa8b732 | 558 | |
56697687 AK |
559 | static u32 desc_limit_scaled(struct desc_struct *desc) |
560 | { | |
561 | u32 limit = get_desc_limit(desc); | |
562 | ||
563 | return desc->g ? (limit << 12) | 0xfff : limit; | |
564 | } | |
565 | ||
7b105ca2 | 566 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
567 | { |
568 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
569 | return 0; | |
570 | ||
7b105ca2 | 571 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
572 | } |
573 | ||
35d3d4a1 AK |
574 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
575 | u32 error, bool valid) | |
54b8486f | 576 | { |
e0ad0b47 | 577 | WARN_ON(vec > 0x1f); |
da9cb575 AK |
578 | ctxt->exception.vector = vec; |
579 | ctxt->exception.error_code = error; | |
580 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 581 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
582 | } |
583 | ||
3b88e41a JR |
584 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
585 | { | |
586 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
587 | } | |
588 | ||
35d3d4a1 | 589 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 590 | { |
35d3d4a1 | 591 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
592 | } |
593 | ||
618ff15d AK |
594 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
595 | { | |
596 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
597 | } | |
598 | ||
35d3d4a1 | 599 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 600 | { |
35d3d4a1 | 601 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
602 | } |
603 | ||
35d3d4a1 | 604 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 605 | { |
35d3d4a1 | 606 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
607 | } |
608 | ||
34d1f490 AK |
609 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
610 | { | |
35d3d4a1 | 611 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
612 | } |
613 | ||
1253791d AK |
614 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
615 | { | |
616 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
617 | } | |
618 | ||
1aa36616 AK |
619 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
620 | { | |
621 | u16 selector; | |
622 | struct desc_struct desc; | |
623 | ||
624 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
625 | return selector; | |
626 | } | |
627 | ||
628 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
629 | unsigned seg) | |
630 | { | |
631 | u16 dummy; | |
632 | u32 base3; | |
633 | struct desc_struct desc; | |
634 | ||
635 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
636 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
637 | } | |
638 | ||
1c11b376 AK |
639 | /* |
640 | * x86 defines three classes of vector instructions: explicitly | |
641 | * aligned, explicitly unaligned, and the rest, which change behaviour | |
642 | * depending on whether they're AVX encoded or not. | |
643 | * | |
644 | * Also included is CMPXCHG16B which is not a vector instruction, yet it is | |
645 | * subject to the same check. | |
646 | */ | |
647 | static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) | |
648 | { | |
649 | if (likely(size < 16)) | |
650 | return false; | |
651 | ||
652 | if (ctxt->d & Aligned) | |
653 | return true; | |
654 | else if (ctxt->d & Unaligned) | |
655 | return false; | |
656 | else if (ctxt->d & Avx) | |
657 | return false; | |
658 | else | |
659 | return true; | |
660 | } | |
661 | ||
d09155d2 PB |
662 | static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, |
663 | struct segmented_address addr, | |
664 | unsigned *max_size, unsigned size, | |
665 | bool write, bool fetch, | |
d50eaa18 | 666 | enum x86emul_mode mode, ulong *linear) |
52fd8b44 | 667 | { |
618ff15d AK |
668 | struct desc_struct desc; |
669 | bool usable; | |
52fd8b44 | 670 | ulong la; |
618ff15d | 671 | u32 lim; |
1aa36616 | 672 | u16 sel; |
52fd8b44 | 673 | |
7b105ca2 | 674 | la = seg_base(ctxt, addr.seg) + addr.ea; |
fd56e154 | 675 | *max_size = 0; |
d50eaa18 | 676 | switch (mode) { |
618ff15d | 677 | case X86EMUL_MODE_PROT64: |
4be4de7e | 678 | if (is_noncanonical_address(la)) |
abc7d8a4 | 679 | goto bad; |
fd56e154 PB |
680 | |
681 | *max_size = min_t(u64, ~0u, (1ull << 48) - la); | |
682 | if (size > *max_size) | |
683 | goto bad; | |
618ff15d AK |
684 | break; |
685 | default: | |
1aa36616 AK |
686 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
687 | addr.seg); | |
618ff15d AK |
688 | if (!usable) |
689 | goto bad; | |
58b7825b GN |
690 | /* code segment in protected mode or read-only data segment */ |
691 | if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) | |
692 | || !(desc.type & 2)) && write) | |
618ff15d AK |
693 | goto bad; |
694 | /* unreadable code segment */ | |
3d9b938e | 695 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
696 | goto bad; |
697 | lim = desc_limit_scaled(&desc); | |
997b0412 | 698 | if (!(desc.type & 8) && (desc.type & 4)) { |
fc058680 | 699 | /* expand-down segment */ |
fd56e154 | 700 | if (addr.ea <= lim) |
618ff15d AK |
701 | goto bad; |
702 | lim = desc.d ? 0xffffffff : 0xffff; | |
618ff15d | 703 | } |
997b0412 PB |
704 | if (addr.ea > lim) |
705 | goto bad; | |
bac15531 NA |
706 | if (lim == 0xffffffff) |
707 | *max_size = ~0u; | |
708 | else { | |
709 | *max_size = (u64)lim + 1 - addr.ea; | |
710 | if (size > *max_size) | |
711 | goto bad; | |
712 | } | |
31ff6488 | 713 | la &= (u32)-1; |
618ff15d AK |
714 | break; |
715 | } | |
1c11b376 AK |
716 | if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
717 | return emulate_gp(ctxt, 0); | |
52fd8b44 AK |
718 | *linear = la; |
719 | return X86EMUL_CONTINUE; | |
618ff15d AK |
720 | bad: |
721 | if (addr.seg == VCPU_SREG_SS) | |
3606189f | 722 | return emulate_ss(ctxt, 0); |
618ff15d | 723 | else |
3606189f | 724 | return emulate_gp(ctxt, 0); |
52fd8b44 AK |
725 | } |
726 | ||
3d9b938e NE |
727 | static int linearize(struct x86_emulate_ctxt *ctxt, |
728 | struct segmented_address addr, | |
729 | unsigned size, bool write, | |
730 | ulong *linear) | |
731 | { | |
fd56e154 | 732 | unsigned max_size; |
d50eaa18 NA |
733 | return __linearize(ctxt, addr, &max_size, size, write, false, |
734 | ctxt->mode, linear); | |
3d9b938e NE |
735 | } |
736 | ||
d50eaa18 NA |
737 | static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, |
738 | enum x86emul_mode mode) | |
739 | { | |
740 | ulong linear; | |
741 | int rc; | |
742 | unsigned max_size; | |
743 | struct segmented_address addr = { .seg = VCPU_SREG_CS, | |
744 | .ea = dst }; | |
745 | ||
746 | if (ctxt->op_bytes != sizeof(unsigned long)) | |
747 | addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); | |
748 | rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); | |
749 | if (rc == X86EMUL_CONTINUE) | |
750 | ctxt->_eip = addr.ea; | |
751 | return rc; | |
752 | } | |
753 | ||
754 | static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) | |
755 | { | |
756 | return assign_eip(ctxt, dst, ctxt->mode); | |
3d9b938e NE |
757 | } |
758 | ||
d50eaa18 NA |
759 | static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, |
760 | const struct desc_struct *cs_desc) | |
761 | { | |
762 | enum x86emul_mode mode = ctxt->mode; | |
82268083 | 763 | int rc; |
d50eaa18 NA |
764 | |
765 | #ifdef CONFIG_X86_64 | |
82268083 NA |
766 | if (ctxt->mode >= X86EMUL_MODE_PROT16) { |
767 | if (cs_desc->l) { | |
768 | u64 efer = 0; | |
d50eaa18 | 769 | |
82268083 NA |
770 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
771 | if (efer & EFER_LMA) | |
772 | mode = X86EMUL_MODE_PROT64; | |
773 | } else | |
774 | mode = X86EMUL_MODE_PROT32; /* temporary value */ | |
d50eaa18 NA |
775 | } |
776 | #endif | |
777 | if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) | |
778 | mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
82268083 NA |
779 | rc = assign_eip(ctxt, dst, mode); |
780 | if (rc == X86EMUL_CONTINUE) | |
781 | ctxt->mode = mode; | |
782 | return rc; | |
d50eaa18 NA |
783 | } |
784 | ||
785 | static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) | |
786 | { | |
787 | return assign_eip_near(ctxt, ctxt->_eip + rel); | |
788 | } | |
3d9b938e | 789 | |
3ca3ac4d AK |
790 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
791 | struct segmented_address addr, | |
792 | void *data, | |
793 | unsigned size) | |
794 | { | |
9fa088f4 AK |
795 | int rc; |
796 | ulong linear; | |
797 | ||
83b8795a | 798 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
799 | if (rc != X86EMUL_CONTINUE) |
800 | return rc; | |
0f65dd70 | 801 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
802 | } |
803 | ||
807941b1 | 804 | /* |
285ca9e9 | 805 | * Prefetch the remaining bytes of the instruction without crossing page |
807941b1 TY |
806 | * boundary if they are not in fetch_cache yet. |
807 | */ | |
9506d57d | 808 | static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) |
62266869 | 809 | { |
62266869 | 810 | int rc; |
fd56e154 | 811 | unsigned size, max_size; |
285ca9e9 | 812 | unsigned long linear; |
17052f16 | 813 | int cur_size = ctxt->fetch.end - ctxt->fetch.data; |
285ca9e9 | 814 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
17052f16 PB |
815 | .ea = ctxt->eip + cur_size }; |
816 | ||
fd56e154 PB |
817 | /* |
818 | * We do not know exactly how many bytes will be needed, and | |
819 | * __linearize is expensive, so fetch as much as possible. We | |
820 | * just have to avoid going beyond the 15 byte limit, the end | |
821 | * of the segment, or the end of the page. | |
822 | * | |
823 | * __linearize is called with size 0 so that it does not do any | |
824 | * boundary check itself. Instead, we use max_size to check | |
825 | * against op_size. | |
826 | */ | |
d50eaa18 NA |
827 | rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, |
828 | &linear); | |
719d5a9b PB |
829 | if (unlikely(rc != X86EMUL_CONTINUE)) |
830 | return rc; | |
831 | ||
fd56e154 | 832 | size = min_t(unsigned, 15UL ^ cur_size, max_size); |
719d5a9b | 833 | size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); |
5cfc7e0f PB |
834 | |
835 | /* | |
836 | * One instruction can only straddle two pages, | |
837 | * and one has been loaded at the beginning of | |
838 | * x86_decode_insn. So, if not enough bytes | |
839 | * still, we must have hit the 15-byte boundary. | |
840 | */ | |
841 | if (unlikely(size < op_size)) | |
fd56e154 PB |
842 | return emulate_gp(ctxt, 0); |
843 | ||
17052f16 | 844 | rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, |
285ca9e9 PB |
845 | size, &ctxt->exception); |
846 | if (unlikely(rc != X86EMUL_CONTINUE)) | |
847 | return rc; | |
17052f16 | 848 | ctxt->fetch.end += size; |
3e2815e9 | 849 | return X86EMUL_CONTINUE; |
62266869 AK |
850 | } |
851 | ||
9506d57d PB |
852 | static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, |
853 | unsigned size) | |
62266869 | 854 | { |
08da44ae NA |
855 | unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; |
856 | ||
857 | if (unlikely(done_size < size)) | |
858 | return __do_insn_fetch_bytes(ctxt, size - done_size); | |
9506d57d PB |
859 | else |
860 | return X86EMUL_CONTINUE; | |
62266869 AK |
861 | } |
862 | ||
67cbc90d | 863 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 864 | #define insn_fetch(_type, _ctxt) \ |
9506d57d | 865 | ({ _type _x; \ |
9506d57d PB |
866 | \ |
867 | rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ | |
67cbc90d TY |
868 | if (rc != X86EMUL_CONTINUE) \ |
869 | goto done; \ | |
9506d57d | 870 | ctxt->_eip += sizeof(_type); \ |
17052f16 PB |
871 | _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \ |
872 | ctxt->fetch.ptr += sizeof(_type); \ | |
9506d57d | 873 | _x; \ |
67cbc90d TY |
874 | }) |
875 | ||
807941b1 | 876 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
9506d57d | 877 | ({ \ |
9506d57d | 878 | rc = do_insn_fetch_bytes(_ctxt, _size); \ |
67cbc90d TY |
879 | if (rc != X86EMUL_CONTINUE) \ |
880 | goto done; \ | |
9506d57d | 881 | ctxt->_eip += (_size); \ |
17052f16 PB |
882 | memcpy(_arr, ctxt->fetch.ptr, _size); \ |
883 | ctxt->fetch.ptr += (_size); \ | |
67cbc90d TY |
884 | }) |
885 | ||
1e3c5cb0 RR |
886 | /* |
887 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
888 | * pointer into the block that addresses the relevant register. | |
889 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
890 | */ | |
dd856efa | 891 | static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, |
aa9ac1a6 | 892 | int byteop) |
6aa8b732 AK |
893 | { |
894 | void *p; | |
aa9ac1a6 | 895 | int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; |
6aa8b732 | 896 | |
6aa8b732 | 897 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
dd856efa AK |
898 | p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; |
899 | else | |
900 | p = reg_rmw(ctxt, modrm_reg); | |
6aa8b732 AK |
901 | return p; |
902 | } | |
903 | ||
904 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 905 | struct segmented_address addr, |
6aa8b732 AK |
906 | u16 *size, unsigned long *address, int op_bytes) |
907 | { | |
908 | int rc; | |
909 | ||
910 | if (op_bytes == 2) | |
911 | op_bytes = 3; | |
912 | *address = 0; | |
3ca3ac4d | 913 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 914 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 915 | return rc; |
30b31ab6 | 916 | addr.ea += 2; |
3ca3ac4d | 917 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
918 | return rc; |
919 | } | |
920 | ||
34b77652 AK |
921 | FASTOP2(add); |
922 | FASTOP2(or); | |
923 | FASTOP2(adc); | |
924 | FASTOP2(sbb); | |
925 | FASTOP2(and); | |
926 | FASTOP2(sub); | |
927 | FASTOP2(xor); | |
928 | FASTOP2(cmp); | |
929 | FASTOP2(test); | |
930 | ||
b9fa409b AK |
931 | FASTOP1SRC2(mul, mul_ex); |
932 | FASTOP1SRC2(imul, imul_ex); | |
b8c0b6ae AK |
933 | FASTOP1SRC2EX(div, div_ex); |
934 | FASTOP1SRC2EX(idiv, idiv_ex); | |
b9fa409b | 935 | |
34b77652 AK |
936 | FASTOP3WCL(shld); |
937 | FASTOP3WCL(shrd); | |
938 | ||
939 | FASTOP2W(imul); | |
940 | ||
941 | FASTOP1(not); | |
942 | FASTOP1(neg); | |
943 | FASTOP1(inc); | |
944 | FASTOP1(dec); | |
945 | ||
946 | FASTOP2CL(rol); | |
947 | FASTOP2CL(ror); | |
948 | FASTOP2CL(rcl); | |
949 | FASTOP2CL(rcr); | |
950 | FASTOP2CL(shl); | |
951 | FASTOP2CL(shr); | |
952 | FASTOP2CL(sar); | |
953 | ||
954 | FASTOP2W(bsf); | |
955 | FASTOP2W(bsr); | |
956 | FASTOP2W(bt); | |
957 | FASTOP2W(bts); | |
958 | FASTOP2W(btr); | |
959 | FASTOP2W(btc); | |
960 | ||
e47a5f5f AK |
961 | FASTOP2(xadd); |
962 | ||
5aca3722 NA |
963 | FASTOP2R(cmp, cmp_r); |
964 | ||
900efe20 NA |
965 | static int em_bsf_c(struct x86_emulate_ctxt *ctxt) |
966 | { | |
967 | /* If src is zero, do not writeback, but update flags */ | |
968 | if (ctxt->src.val == 0) | |
969 | ctxt->dst.type = OP_NONE; | |
970 | return fastop(ctxt, em_bsf); | |
971 | } | |
972 | ||
973 | static int em_bsr_c(struct x86_emulate_ctxt *ctxt) | |
974 | { | |
975 | /* If src is zero, do not writeback, but update flags */ | |
976 | if (ctxt->src.val == 0) | |
977 | ctxt->dst.type = OP_NONE; | |
978 | return fastop(ctxt, em_bsr); | |
979 | } | |
980 | ||
9ae9feba | 981 | static u8 test_cc(unsigned int condition, unsigned long flags) |
bbe9abbd | 982 | { |
9ae9feba AK |
983 | u8 rc; |
984 | void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); | |
bbe9abbd | 985 | |
9ae9feba | 986 | flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; |
3f0c3d0b | 987 | asm("push %[flags]; popf; call *%[fastop]" |
9ae9feba AK |
988 | : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); |
989 | return rc; | |
bbe9abbd NK |
990 | } |
991 | ||
91ff3cb4 AK |
992 | static void fetch_register_operand(struct operand *op) |
993 | { | |
994 | switch (op->bytes) { | |
995 | case 1: | |
996 | op->val = *(u8 *)op->addr.reg; | |
997 | break; | |
998 | case 2: | |
999 | op->val = *(u16 *)op->addr.reg; | |
1000 | break; | |
1001 | case 4: | |
1002 | op->val = *(u32 *)op->addr.reg; | |
1003 | break; | |
1004 | case 8: | |
1005 | op->val = *(u64 *)op->addr.reg; | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | ||
1253791d AK |
1010 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
1011 | { | |
1012 | ctxt->ops->get_fpu(ctxt); | |
1013 | switch (reg) { | |
89a87c67 MK |
1014 | case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; |
1015 | case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; | |
1016 | case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; | |
1017 | case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; | |
1018 | case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; | |
1019 | case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; | |
1020 | case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; | |
1021 | case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; | |
1253791d | 1022 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
1023 | case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; |
1024 | case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; | |
1025 | case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; | |
1026 | case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; | |
1027 | case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; | |
1028 | case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; | |
1029 | case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; | |
1030 | case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; | |
1253791d AK |
1031 | #endif |
1032 | default: BUG(); | |
1033 | } | |
1034 | ctxt->ops->put_fpu(ctxt); | |
1035 | } | |
1036 | ||
1037 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
1038 | int reg) | |
1039 | { | |
1040 | ctxt->ops->get_fpu(ctxt); | |
1041 | switch (reg) { | |
89a87c67 MK |
1042 | case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; |
1043 | case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; | |
1044 | case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; | |
1045 | case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; | |
1046 | case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; | |
1047 | case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; | |
1048 | case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; | |
1049 | case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; | |
1253791d | 1050 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
1051 | case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; |
1052 | case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; | |
1053 | case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; | |
1054 | case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; | |
1055 | case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; | |
1056 | case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; | |
1057 | case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; | |
1058 | case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; | |
1253791d AK |
1059 | #endif |
1060 | default: BUG(); | |
1061 | } | |
1062 | ctxt->ops->put_fpu(ctxt); | |
1063 | } | |
1064 | ||
cbe2c9d3 AK |
1065 | static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
1066 | { | |
1067 | ctxt->ops->get_fpu(ctxt); | |
1068 | switch (reg) { | |
1069 | case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; | |
1070 | case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; | |
1071 | case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; | |
1072 | case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; | |
1073 | case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; | |
1074 | case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; | |
1075 | case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; | |
1076 | case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; | |
1077 | default: BUG(); | |
1078 | } | |
1079 | ctxt->ops->put_fpu(ctxt); | |
1080 | } | |
1081 | ||
1082 | static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) | |
1083 | { | |
1084 | ctxt->ops->get_fpu(ctxt); | |
1085 | switch (reg) { | |
1086 | case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; | |
1087 | case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; | |
1088 | case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; | |
1089 | case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; | |
1090 | case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; | |
1091 | case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; | |
1092 | case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; | |
1093 | case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; | |
1094 | default: BUG(); | |
1095 | } | |
1096 | ctxt->ops->put_fpu(ctxt); | |
1097 | } | |
1098 | ||
045a282c GN |
1099 | static int em_fninit(struct x86_emulate_ctxt *ctxt) |
1100 | { | |
1101 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1102 | return emulate_nm(ctxt); | |
1103 | ||
1104 | ctxt->ops->get_fpu(ctxt); | |
1105 | asm volatile("fninit"); | |
1106 | ctxt->ops->put_fpu(ctxt); | |
1107 | return X86EMUL_CONTINUE; | |
1108 | } | |
1109 | ||
1110 | static int em_fnstcw(struct x86_emulate_ctxt *ctxt) | |
1111 | { | |
1112 | u16 fcw; | |
1113 | ||
1114 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1115 | return emulate_nm(ctxt); | |
1116 | ||
1117 | ctxt->ops->get_fpu(ctxt); | |
1118 | asm volatile("fnstcw %0": "+m"(fcw)); | |
1119 | ctxt->ops->put_fpu(ctxt); | |
1120 | ||
045a282c GN |
1121 | ctxt->dst.val = fcw; |
1122 | ||
1123 | return X86EMUL_CONTINUE; | |
1124 | } | |
1125 | ||
1126 | static int em_fnstsw(struct x86_emulate_ctxt *ctxt) | |
1127 | { | |
1128 | u16 fsw; | |
1129 | ||
1130 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1131 | return emulate_nm(ctxt); | |
1132 | ||
1133 | ctxt->ops->get_fpu(ctxt); | |
1134 | asm volatile("fnstsw %0": "+m"(fsw)); | |
1135 | ctxt->ops->put_fpu(ctxt); | |
1136 | ||
045a282c GN |
1137 | ctxt->dst.val = fsw; |
1138 | ||
1139 | return X86EMUL_CONTINUE; | |
1140 | } | |
1141 | ||
1253791d | 1142 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, |
2adb5ad9 | 1143 | struct operand *op) |
3c118e24 | 1144 | { |
9dac77fa | 1145 | unsigned reg = ctxt->modrm_reg; |
33615aa9 | 1146 | |
9dac77fa AK |
1147 | if (!(ctxt->d & ModRM)) |
1148 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 1149 | |
9dac77fa | 1150 | if (ctxt->d & Sse) { |
1253791d AK |
1151 | op->type = OP_XMM; |
1152 | op->bytes = 16; | |
1153 | op->addr.xmm = reg; | |
1154 | read_sse_reg(ctxt, &op->vec_val, reg); | |
1155 | return; | |
1156 | } | |
cbe2c9d3 AK |
1157 | if (ctxt->d & Mmx) { |
1158 | reg &= 7; | |
1159 | op->type = OP_MM; | |
1160 | op->bytes = 8; | |
1161 | op->addr.mm = reg; | |
1162 | return; | |
1163 | } | |
1253791d | 1164 | |
3c118e24 | 1165 | op->type = OP_REG; |
6d4d85ec GN |
1166 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
1167 | op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); | |
1168 | ||
91ff3cb4 | 1169 | fetch_register_operand(op); |
3c118e24 AK |
1170 | op->orig_val = op->val; |
1171 | } | |
1172 | ||
a6e3407b AK |
1173 | static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) |
1174 | { | |
1175 | if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) | |
1176 | ctxt->modrm_seg = VCPU_SREG_SS; | |
1177 | } | |
1178 | ||
1c73ef66 | 1179 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 1180 | struct operand *op) |
1c73ef66 | 1181 | { |
1c73ef66 | 1182 | u8 sib; |
02357bdc | 1183 | int index_reg, base_reg, scale; |
3e2815e9 | 1184 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 1185 | ulong modrm_ea = 0; |
1c73ef66 | 1186 | |
02357bdc BD |
1187 | ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ |
1188 | index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ | |
1189 | base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ | |
1c73ef66 | 1190 | |
02357bdc | 1191 | ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; |
9dac77fa | 1192 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; |
02357bdc | 1193 | ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); |
9dac77fa | 1194 | ctxt->modrm_seg = VCPU_SREG_DS; |
1c73ef66 | 1195 | |
9b88ae99 | 1196 | if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { |
2dbd0dd7 | 1197 | op->type = OP_REG; |
9dac77fa | 1198 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
8acb4207 | 1199 | op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, |
aa9ac1a6 | 1200 | ctxt->d & ByteOp); |
9dac77fa | 1201 | if (ctxt->d & Sse) { |
1253791d AK |
1202 | op->type = OP_XMM; |
1203 | op->bytes = 16; | |
9dac77fa AK |
1204 | op->addr.xmm = ctxt->modrm_rm; |
1205 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
1206 | return rc; |
1207 | } | |
cbe2c9d3 AK |
1208 | if (ctxt->d & Mmx) { |
1209 | op->type = OP_MM; | |
1210 | op->bytes = 8; | |
bdc90722 | 1211 | op->addr.mm = ctxt->modrm_rm & 7; |
cbe2c9d3 AK |
1212 | return rc; |
1213 | } | |
2dbd0dd7 | 1214 | fetch_register_operand(op); |
1c73ef66 AK |
1215 | return rc; |
1216 | } | |
1217 | ||
2dbd0dd7 AK |
1218 | op->type = OP_MEM; |
1219 | ||
9dac77fa | 1220 | if (ctxt->ad_bytes == 2) { |
dd856efa AK |
1221 | unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); |
1222 | unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); | |
1223 | unsigned si = reg_read(ctxt, VCPU_REGS_RSI); | |
1224 | unsigned di = reg_read(ctxt, VCPU_REGS_RDI); | |
1c73ef66 AK |
1225 | |
1226 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 1227 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1228 | case 0: |
9dac77fa | 1229 | if (ctxt->modrm_rm == 6) |
e85a1085 | 1230 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1231 | break; |
1232 | case 1: | |
e85a1085 | 1233 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1234 | break; |
1235 | case 2: | |
e85a1085 | 1236 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1237 | break; |
1238 | } | |
9dac77fa | 1239 | switch (ctxt->modrm_rm) { |
1c73ef66 | 1240 | case 0: |
2dbd0dd7 | 1241 | modrm_ea += bx + si; |
1c73ef66 AK |
1242 | break; |
1243 | case 1: | |
2dbd0dd7 | 1244 | modrm_ea += bx + di; |
1c73ef66 AK |
1245 | break; |
1246 | case 2: | |
2dbd0dd7 | 1247 | modrm_ea += bp + si; |
1c73ef66 AK |
1248 | break; |
1249 | case 3: | |
2dbd0dd7 | 1250 | modrm_ea += bp + di; |
1c73ef66 AK |
1251 | break; |
1252 | case 4: | |
2dbd0dd7 | 1253 | modrm_ea += si; |
1c73ef66 AK |
1254 | break; |
1255 | case 5: | |
2dbd0dd7 | 1256 | modrm_ea += di; |
1c73ef66 AK |
1257 | break; |
1258 | case 6: | |
9dac77fa | 1259 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 1260 | modrm_ea += bp; |
1c73ef66 AK |
1261 | break; |
1262 | case 7: | |
2dbd0dd7 | 1263 | modrm_ea += bx; |
1c73ef66 AK |
1264 | break; |
1265 | } | |
9dac77fa AK |
1266 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
1267 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
1268 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 1269 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
1270 | } else { |
1271 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 1272 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 1273 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
1274 | index_reg |= (sib >> 3) & 7; |
1275 | base_reg |= sib & 7; | |
1276 | scale = sib >> 6; | |
1277 | ||
9dac77fa | 1278 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 1279 | modrm_ea += insn_fetch(s32, ctxt); |
a6e3407b | 1280 | else { |
dd856efa | 1281 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b | 1282 | adjust_modrm_seg(ctxt, base_reg); |
ab708099 NA |
1283 | /* Increment ESP on POP [ESP] */ |
1284 | if ((ctxt->d & IncSP) && | |
1285 | base_reg == VCPU_REGS_RSP) | |
1286 | modrm_ea += ctxt->op_bytes; | |
a6e3407b | 1287 | } |
dc71d0f1 | 1288 | if (index_reg != 4) |
dd856efa | 1289 | modrm_ea += reg_read(ctxt, index_reg) << scale; |
9dac77fa | 1290 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { |
5b38ab87 | 1291 | modrm_ea += insn_fetch(s32, ctxt); |
84411d85 | 1292 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 1293 | ctxt->rip_relative = 1; |
a6e3407b AK |
1294 | } else { |
1295 | base_reg = ctxt->modrm_rm; | |
dd856efa | 1296 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1297 | adjust_modrm_seg(ctxt, base_reg); |
1298 | } | |
9dac77fa | 1299 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1300 | case 1: |
e85a1085 | 1301 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1302 | break; |
1303 | case 2: | |
e85a1085 | 1304 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1305 | break; |
1306 | } | |
1307 | } | |
90de84f5 | 1308 | op->addr.mem.ea = modrm_ea; |
41061cdb BD |
1309 | if (ctxt->ad_bytes != 8) |
1310 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
1311 | ||
1c73ef66 AK |
1312 | done: |
1313 | return rc; | |
1314 | } | |
1315 | ||
1316 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1317 | struct operand *op) |
1c73ef66 | 1318 | { |
3e2815e9 | 1319 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1320 | |
2dbd0dd7 | 1321 | op->type = OP_MEM; |
9dac77fa | 1322 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1323 | case 2: |
e85a1085 | 1324 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1325 | break; |
1326 | case 4: | |
e85a1085 | 1327 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1328 | break; |
1329 | case 8: | |
e85a1085 | 1330 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1331 | break; |
1332 | } | |
1333 | done: | |
1334 | return rc; | |
1335 | } | |
1336 | ||
9dac77fa | 1337 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1338 | { |
7129eeca | 1339 | long sv = 0, mask; |
35c843c4 | 1340 | |
9dac77fa | 1341 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
7dec5603 | 1342 | mask = ~((long)ctxt->dst.bytes * 8 - 1); |
35c843c4 | 1343 | |
9dac77fa AK |
1344 | if (ctxt->src.bytes == 2) |
1345 | sv = (s16)ctxt->src.val & (s16)mask; | |
1346 | else if (ctxt->src.bytes == 4) | |
1347 | sv = (s32)ctxt->src.val & (s32)mask; | |
7dec5603 NA |
1348 | else |
1349 | sv = (s64)ctxt->src.val & (s64)mask; | |
35c843c4 | 1350 | |
1c1c35ae NA |
1351 | ctxt->dst.addr.mem.ea = address_mask(ctxt, |
1352 | ctxt->dst.addr.mem.ea + (sv >> 3)); | |
35c843c4 | 1353 | } |
ba7ff2b7 WY |
1354 | |
1355 | /* only subword offset */ | |
9dac77fa | 1356 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1357 | } |
1358 | ||
dde7e6d1 | 1359 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1360 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1361 | { |
dde7e6d1 | 1362 | int rc; |
9dac77fa | 1363 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1364 | |
f23b070e XG |
1365 | if (mc->pos < mc->end) |
1366 | goto read_cached; | |
6aa8b732 | 1367 | |
f23b070e XG |
1368 | WARN_ON((mc->end + size) >= sizeof(mc->data)); |
1369 | ||
1370 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, | |
1371 | &ctxt->exception); | |
1372 | if (rc != X86EMUL_CONTINUE) | |
1373 | return rc; | |
1374 | ||
1375 | mc->end += size; | |
1376 | ||
1377 | read_cached: | |
1378 | memcpy(dest, mc->data + mc->pos, size); | |
1379 | mc->pos += size; | |
dde7e6d1 AK |
1380 | return X86EMUL_CONTINUE; |
1381 | } | |
6aa8b732 | 1382 | |
3ca3ac4d AK |
1383 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1384 | struct segmented_address addr, | |
1385 | void *data, | |
1386 | unsigned size) | |
1387 | { | |
9fa088f4 AK |
1388 | int rc; |
1389 | ulong linear; | |
1390 | ||
83b8795a | 1391 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1392 | if (rc != X86EMUL_CONTINUE) |
1393 | return rc; | |
7b105ca2 | 1394 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1395 | } |
1396 | ||
1397 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1398 | struct segmented_address addr, | |
1399 | const void *data, | |
1400 | unsigned size) | |
1401 | { | |
9fa088f4 AK |
1402 | int rc; |
1403 | ulong linear; | |
1404 | ||
83b8795a | 1405 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1406 | if (rc != X86EMUL_CONTINUE) |
1407 | return rc; | |
0f65dd70 AK |
1408 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1409 | &ctxt->exception); | |
3ca3ac4d AK |
1410 | } |
1411 | ||
1412 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1413 | struct segmented_address addr, | |
1414 | const void *orig_data, const void *data, | |
1415 | unsigned size) | |
1416 | { | |
9fa088f4 AK |
1417 | int rc; |
1418 | ulong linear; | |
1419 | ||
83b8795a | 1420 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1421 | if (rc != X86EMUL_CONTINUE) |
1422 | return rc; | |
0f65dd70 AK |
1423 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1424 | size, &ctxt->exception); | |
3ca3ac4d AK |
1425 | } |
1426 | ||
dde7e6d1 | 1427 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1428 | unsigned int size, unsigned short port, |
1429 | void *dest) | |
1430 | { | |
9dac77fa | 1431 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1432 | |
dde7e6d1 | 1433 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1434 | unsigned int in_page, n; |
9dac77fa | 1435 | unsigned int count = ctxt->rep_prefix ? |
dd856efa | 1436 | address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; |
dde7e6d1 | 1437 | in_page = (ctxt->eflags & EFLG_DF) ? |
dd856efa AK |
1438 | offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : |
1439 | PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); | |
b55a8144 | 1440 | n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); |
dde7e6d1 AK |
1441 | if (n == 0) |
1442 | n = 1; | |
1443 | rc->pos = rc->end = 0; | |
7b105ca2 | 1444 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1445 | return 0; |
1446 | rc->end = n * size; | |
6aa8b732 AK |
1447 | } |
1448 | ||
e6e39f04 NA |
1449 | if (ctxt->rep_prefix && (ctxt->d & String) && |
1450 | !(ctxt->eflags & EFLG_DF)) { | |
b3356bf0 GN |
1451 | ctxt->dst.data = rc->data + rc->pos; |
1452 | ctxt->dst.type = OP_MEM_STR; | |
1453 | ctxt->dst.count = (rc->end - rc->pos) / size; | |
1454 | rc->pos = rc->end; | |
1455 | } else { | |
1456 | memcpy(dest, rc->data + rc->pos, size); | |
1457 | rc->pos += size; | |
1458 | } | |
dde7e6d1 AK |
1459 | return 1; |
1460 | } | |
6aa8b732 | 1461 | |
7f3d35fd KW |
1462 | static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
1463 | u16 index, struct desc_struct *desc) | |
1464 | { | |
1465 | struct desc_ptr dt; | |
1466 | ulong addr; | |
1467 | ||
1468 | ctxt->ops->get_idt(ctxt, &dt); | |
1469 | ||
1470 | if (dt.size < index * 8 + 7) | |
1471 | return emulate_gp(ctxt, index << 3 | 0x2); | |
1472 | ||
1473 | addr = dt.address + index * 8; | |
1474 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1475 | &ctxt->exception); | |
1476 | } | |
1477 | ||
dde7e6d1 | 1478 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1479 | u16 selector, struct desc_ptr *dt) |
1480 | { | |
0225fb50 | 1481 | const struct x86_emulate_ops *ops = ctxt->ops; |
2eedcac8 | 1482 | u32 base3 = 0; |
7b105ca2 | 1483 | |
dde7e6d1 AK |
1484 | if (selector & 1 << 2) { |
1485 | struct desc_struct desc; | |
1aa36616 AK |
1486 | u16 sel; |
1487 | ||
dde7e6d1 | 1488 | memset (dt, 0, sizeof *dt); |
2eedcac8 NA |
1489 | if (!ops->get_segment(ctxt, &sel, &desc, &base3, |
1490 | VCPU_SREG_LDTR)) | |
dde7e6d1 | 1491 | return; |
e09d082c | 1492 | |
dde7e6d1 | 1493 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
2eedcac8 | 1494 | dt->address = get_desc_base(&desc) | ((u64)base3 << 32); |
dde7e6d1 | 1495 | } else |
4bff1e86 | 1496 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1497 | } |
120df890 | 1498 | |
edccda7c NA |
1499 | static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, |
1500 | u16 selector, ulong *desc_addr_p) | |
dde7e6d1 AK |
1501 | { |
1502 | struct desc_ptr dt; | |
1503 | u16 index = selector >> 3; | |
dde7e6d1 | 1504 | ulong addr; |
120df890 | 1505 | |
7b105ca2 | 1506 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1507 | |
35d3d4a1 AK |
1508 | if (dt.size < index * 8 + 7) |
1509 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1510 | |
edccda7c NA |
1511 | addr = dt.address + index * 8; |
1512 | ||
1513 | #ifdef CONFIG_X86_64 | |
1514 | if (addr >> 32 != 0) { | |
1515 | u64 efer = 0; | |
1516 | ||
1517 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
1518 | if (!(efer & EFER_LMA)) | |
1519 | addr &= (u32)-1; | |
1520 | } | |
1521 | #endif | |
1522 | ||
1523 | *desc_addr_p = addr; | |
1524 | return X86EMUL_CONTINUE; | |
1525 | } | |
1526 | ||
1527 | /* allowed just for 8 bytes segments */ | |
1528 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1529 | u16 selector, struct desc_struct *desc, | |
1530 | ulong *desc_addr_p) | |
1531 | { | |
1532 | int rc; | |
1533 | ||
1534 | rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); | |
1535 | if (rc != X86EMUL_CONTINUE) | |
1536 | return rc; | |
1537 | ||
1538 | return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc), | |
7b105ca2 | 1539 | &ctxt->exception); |
dde7e6d1 | 1540 | } |
ef65c889 | 1541 | |
dde7e6d1 AK |
1542 | /* allowed just for 8 bytes segments */ |
1543 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1544 | u16 selector, struct desc_struct *desc) |
1545 | { | |
edccda7c | 1546 | int rc; |
dde7e6d1 | 1547 | ulong addr; |
6aa8b732 | 1548 | |
edccda7c NA |
1549 | rc = get_descriptor_ptr(ctxt, selector, &addr); |
1550 | if (rc != X86EMUL_CONTINUE) | |
1551 | return rc; | |
6aa8b732 | 1552 | |
7b105ca2 TY |
1553 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1554 | &ctxt->exception); | |
dde7e6d1 | 1555 | } |
c7e75a3d | 1556 | |
5601d05b | 1557 | /* Does not support long mode */ |
2356aaeb | 1558 | static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
d1442d85 | 1559 | u16 selector, int seg, u8 cpl, |
3dc4bc4f | 1560 | enum x86_transfer_type transfer, |
d1442d85 | 1561 | struct desc_struct *desc) |
dde7e6d1 | 1562 | { |
869be99c | 1563 | struct desc_struct seg_desc, old_desc; |
2356aaeb | 1564 | u8 dpl, rpl; |
dde7e6d1 AK |
1565 | unsigned err_vec = GP_VECTOR; |
1566 | u32 err_code = 0; | |
1567 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
e919464b | 1568 | ulong desc_addr; |
dde7e6d1 | 1569 | int ret; |
03ebebeb | 1570 | u16 dummy; |
e37a75a1 | 1571 | u32 base3 = 0; |
69f55cb1 | 1572 | |
dde7e6d1 | 1573 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1574 | |
f8da94e9 KW |
1575 | if (ctxt->mode == X86EMUL_MODE_REAL) { |
1576 | /* set real mode segment descriptor (keep limit etc. for | |
1577 | * unreal mode) */ | |
03ebebeb | 1578 | ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); |
dde7e6d1 | 1579 | set_desc_base(&seg_desc, selector << 4); |
dde7e6d1 | 1580 | goto load; |
f8da94e9 KW |
1581 | } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { |
1582 | /* VM86 needs a clean new segment descriptor */ | |
1583 | set_desc_base(&seg_desc, selector << 4); | |
1584 | set_desc_limit(&seg_desc, 0xffff); | |
1585 | seg_desc.type = 3; | |
1586 | seg_desc.p = 1; | |
1587 | seg_desc.s = 1; | |
1588 | seg_desc.dpl = 3; | |
1589 | goto load; | |
dde7e6d1 AK |
1590 | } |
1591 | ||
79d5b4c3 | 1592 | rpl = selector & 3; |
79d5b4c3 AK |
1593 | |
1594 | /* NULL selector is not valid for TR, CS and SS (except for long mode) */ | |
1595 | if ((seg == VCPU_SREG_CS | |
1596 | || (seg == VCPU_SREG_SS | |
1597 | && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) | |
1598 | || seg == VCPU_SREG_TR) | |
dde7e6d1 AK |
1599 | && null_selector) |
1600 | goto exception; | |
1601 | ||
1602 | /* TR should be in GDT only */ | |
1603 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1604 | goto exception; | |
1605 | ||
1606 | if (null_selector) /* for NULL selector skip all following checks */ | |
1607 | goto load; | |
1608 | ||
e919464b | 1609 | ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); |
dde7e6d1 AK |
1610 | if (ret != X86EMUL_CONTINUE) |
1611 | return ret; | |
1612 | ||
1613 | err_code = selector & 0xfffc; | |
3dc4bc4f NA |
1614 | err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : |
1615 | GP_VECTOR; | |
dde7e6d1 | 1616 | |
fc058680 | 1617 | /* can't load system descriptor into segment selector */ |
3dc4bc4f NA |
1618 | if (seg <= VCPU_SREG_GS && !seg_desc.s) { |
1619 | if (transfer == X86_TRANSFER_CALL_JMP) | |
1620 | return X86EMUL_UNHANDLEABLE; | |
dde7e6d1 | 1621 | goto exception; |
3dc4bc4f | 1622 | } |
dde7e6d1 AK |
1623 | |
1624 | if (!seg_desc.p) { | |
1625 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1626 | goto exception; | |
1627 | } | |
1628 | ||
dde7e6d1 | 1629 | dpl = seg_desc.dpl; |
dde7e6d1 AK |
1630 | |
1631 | switch (seg) { | |
1632 | case VCPU_SREG_SS: | |
1633 | /* | |
1634 | * segment is not a writable data segment or segment | |
1635 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1636 | */ | |
1637 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1638 | goto exception; | |
6aa8b732 | 1639 | break; |
dde7e6d1 AK |
1640 | case VCPU_SREG_CS: |
1641 | if (!(seg_desc.type & 8)) | |
1642 | goto exception; | |
1643 | ||
1644 | if (seg_desc.type & 4) { | |
1645 | /* conforming */ | |
1646 | if (dpl > cpl) | |
1647 | goto exception; | |
1648 | } else { | |
1649 | /* nonconforming */ | |
1650 | if (rpl > cpl || dpl != cpl) | |
1651 | goto exception; | |
1652 | } | |
040c8dc8 NA |
1653 | /* in long-mode d/b must be clear if l is set */ |
1654 | if (seg_desc.d && seg_desc.l) { | |
1655 | u64 efer = 0; | |
1656 | ||
1657 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
1658 | if (efer & EFER_LMA) | |
1659 | goto exception; | |
1660 | } | |
1661 | ||
dde7e6d1 AK |
1662 | /* CS(RPL) <- CPL */ |
1663 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1664 | break; |
dde7e6d1 AK |
1665 | case VCPU_SREG_TR: |
1666 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1667 | goto exception; | |
869be99c AK |
1668 | old_desc = seg_desc; |
1669 | seg_desc.type |= 2; /* busy */ | |
1670 | ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, | |
1671 | sizeof(seg_desc), &ctxt->exception); | |
1672 | if (ret != X86EMUL_CONTINUE) | |
1673 | return ret; | |
dde7e6d1 AK |
1674 | break; |
1675 | case VCPU_SREG_LDTR: | |
1676 | if (seg_desc.s || seg_desc.type != 2) | |
1677 | goto exception; | |
1678 | break; | |
1679 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1680 | /* |
dde7e6d1 AK |
1681 | * segment is not a data or readable code segment or |
1682 | * ((segment is a data or nonconforming code segment) | |
1683 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1684 | */ |
dde7e6d1 AK |
1685 | if ((seg_desc.type & 0xa) == 0x8 || |
1686 | (((seg_desc.type & 0xc) != 0xc) && | |
1687 | (rpl > dpl && cpl > dpl))) | |
1688 | goto exception; | |
6aa8b732 | 1689 | break; |
dde7e6d1 AK |
1690 | } |
1691 | ||
1692 | if (seg_desc.s) { | |
1693 | /* mark segment as accessed */ | |
e2cefa74 NA |
1694 | if (!(seg_desc.type & 1)) { |
1695 | seg_desc.type |= 1; | |
1696 | ret = write_segment_descriptor(ctxt, selector, | |
1697 | &seg_desc); | |
1698 | if (ret != X86EMUL_CONTINUE) | |
1699 | return ret; | |
1700 | } | |
e37a75a1 NA |
1701 | } else if (ctxt->mode == X86EMUL_MODE_PROT64) { |
1702 | ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3, | |
1703 | sizeof(base3), &ctxt->exception); | |
1704 | if (ret != X86EMUL_CONTINUE) | |
1705 | return ret; | |
9a9abf6b NA |
1706 | if (is_noncanonical_address(get_desc_base(&seg_desc) | |
1707 | ((u64)base3 << 32))) | |
1708 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1709 | } |
1710 | load: | |
e37a75a1 | 1711 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); |
d1442d85 NA |
1712 | if (desc) |
1713 | *desc = seg_desc; | |
dde7e6d1 AK |
1714 | return X86EMUL_CONTINUE; |
1715 | exception: | |
592f0858 | 1716 | return emulate_exception(ctxt, err_vec, err_code, true); |
dde7e6d1 AK |
1717 | } |
1718 | ||
2356aaeb PB |
1719 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
1720 | u16 selector, int seg) | |
1721 | { | |
1722 | u8 cpl = ctxt->ops->cpl(ctxt); | |
3dc4bc4f NA |
1723 | return __load_segment_descriptor(ctxt, selector, seg, cpl, |
1724 | X86_TRANSFER_NONE, NULL); | |
2356aaeb PB |
1725 | } |
1726 | ||
31be40b3 WY |
1727 | static void write_register_operand(struct operand *op) |
1728 | { | |
6fd8e127 | 1729 | return assign_register(op->addr.reg, op->val, op->bytes); |
31be40b3 WY |
1730 | } |
1731 | ||
fb32b1ed | 1732 | static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) |
dde7e6d1 | 1733 | { |
fb32b1ed | 1734 | switch (op->type) { |
dde7e6d1 | 1735 | case OP_REG: |
fb32b1ed | 1736 | write_register_operand(op); |
6aa8b732 | 1737 | break; |
dde7e6d1 | 1738 | case OP_MEM: |
9dac77fa | 1739 | if (ctxt->lock_prefix) |
f5f87dfb PB |
1740 | return segmented_cmpxchg(ctxt, |
1741 | op->addr.mem, | |
1742 | &op->orig_val, | |
1743 | &op->val, | |
1744 | op->bytes); | |
1745 | else | |
1746 | return segmented_write(ctxt, | |
fb32b1ed | 1747 | op->addr.mem, |
fb32b1ed AK |
1748 | &op->val, |
1749 | op->bytes); | |
a682e354 | 1750 | break; |
b3356bf0 | 1751 | case OP_MEM_STR: |
f5f87dfb PB |
1752 | return segmented_write(ctxt, |
1753 | op->addr.mem, | |
1754 | op->data, | |
1755 | op->bytes * op->count); | |
b3356bf0 | 1756 | break; |
1253791d | 1757 | case OP_XMM: |
fb32b1ed | 1758 | write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); |
1253791d | 1759 | break; |
cbe2c9d3 | 1760 | case OP_MM: |
fb32b1ed | 1761 | write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); |
cbe2c9d3 | 1762 | break; |
dde7e6d1 AK |
1763 | case OP_NONE: |
1764 | /* no writeback */ | |
414e6277 | 1765 | break; |
dde7e6d1 | 1766 | default: |
414e6277 | 1767 | break; |
6aa8b732 | 1768 | } |
dde7e6d1 AK |
1769 | return X86EMUL_CONTINUE; |
1770 | } | |
6aa8b732 | 1771 | |
51ddff50 | 1772 | static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) |
dde7e6d1 | 1773 | { |
4179bb02 | 1774 | struct segmented_address addr; |
0dc8d10f | 1775 | |
5ad105e5 | 1776 | rsp_increment(ctxt, -bytes); |
dd856efa | 1777 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
4179bb02 TY |
1778 | addr.seg = VCPU_SREG_SS; |
1779 | ||
51ddff50 AK |
1780 | return segmented_write(ctxt, addr, data, bytes); |
1781 | } | |
1782 | ||
1783 | static int em_push(struct x86_emulate_ctxt *ctxt) | |
1784 | { | |
4179bb02 | 1785 | /* Disable writeback. */ |
9dac77fa | 1786 | ctxt->dst.type = OP_NONE; |
51ddff50 | 1787 | return push(ctxt, &ctxt->src.val, ctxt->op_bytes); |
dde7e6d1 | 1788 | } |
69f55cb1 | 1789 | |
dde7e6d1 | 1790 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1791 | void *dest, int len) |
1792 | { | |
dde7e6d1 | 1793 | int rc; |
90de84f5 | 1794 | struct segmented_address addr; |
8b4caf66 | 1795 | |
dd856efa | 1796 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
90de84f5 | 1797 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1798 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1799 | if (rc != X86EMUL_CONTINUE) |
1800 | return rc; | |
1801 | ||
5ad105e5 | 1802 | rsp_increment(ctxt, len); |
dde7e6d1 | 1803 | return rc; |
8b4caf66 LV |
1804 | } |
1805 | ||
c54fe504 TY |
1806 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1807 | { | |
9dac77fa | 1808 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1809 | } |
1810 | ||
dde7e6d1 | 1811 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1812 | void *dest, int len) |
9de41573 GN |
1813 | { |
1814 | int rc; | |
dde7e6d1 AK |
1815 | unsigned long val, change_mask; |
1816 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1817 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1818 | |
3b9be3bf | 1819 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1820 | if (rc != X86EMUL_CONTINUE) |
1821 | return rc; | |
9de41573 | 1822 | |
dde7e6d1 | 1823 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
163b135e | 1824 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID; |
9de41573 | 1825 | |
dde7e6d1 AK |
1826 | switch(ctxt->mode) { |
1827 | case X86EMUL_MODE_PROT64: | |
1828 | case X86EMUL_MODE_PROT32: | |
1829 | case X86EMUL_MODE_PROT16: | |
1830 | if (cpl == 0) | |
1831 | change_mask |= EFLG_IOPL; | |
1832 | if (cpl <= iopl) | |
1833 | change_mask |= EFLG_IF; | |
1834 | break; | |
1835 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1836 | if (iopl < 3) |
1837 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1838 | change_mask |= EFLG_IF; |
1839 | break; | |
1840 | default: /* real mode */ | |
1841 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1842 | break; | |
9de41573 | 1843 | } |
dde7e6d1 AK |
1844 | |
1845 | *(unsigned long *)dest = | |
1846 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1847 | ||
1848 | return rc; | |
9de41573 GN |
1849 | } |
1850 | ||
62aaa2f0 TY |
1851 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1852 | { | |
9dac77fa AK |
1853 | ctxt->dst.type = OP_REG; |
1854 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1855 | ctxt->dst.bytes = ctxt->op_bytes; | |
1856 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1857 | } |
1858 | ||
612e89f0 AK |
1859 | static int em_enter(struct x86_emulate_ctxt *ctxt) |
1860 | { | |
1861 | int rc; | |
1862 | unsigned frame_size = ctxt->src.val; | |
1863 | unsigned nesting_level = ctxt->src2.val & 31; | |
dd856efa | 1864 | ulong rbp; |
612e89f0 AK |
1865 | |
1866 | if (nesting_level) | |
1867 | return X86EMUL_UNHANDLEABLE; | |
1868 | ||
dd856efa AK |
1869 | rbp = reg_read(ctxt, VCPU_REGS_RBP); |
1870 | rc = push(ctxt, &rbp, stack_size(ctxt)); | |
612e89f0 AK |
1871 | if (rc != X86EMUL_CONTINUE) |
1872 | return rc; | |
dd856efa | 1873 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), |
612e89f0 | 1874 | stack_mask(ctxt)); |
dd856efa AK |
1875 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), |
1876 | reg_read(ctxt, VCPU_REGS_RSP) - frame_size, | |
612e89f0 AK |
1877 | stack_mask(ctxt)); |
1878 | return X86EMUL_CONTINUE; | |
1879 | } | |
1880 | ||
f47cfa31 AK |
1881 | static int em_leave(struct x86_emulate_ctxt *ctxt) |
1882 | { | |
dd856efa | 1883 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), |
f47cfa31 | 1884 | stack_mask(ctxt)); |
dd856efa | 1885 | return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); |
f47cfa31 AK |
1886 | } |
1887 | ||
1cd196ea | 1888 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1889 | { |
1cd196ea AK |
1890 | int seg = ctxt->src2.val; |
1891 | ||
9dac77fa | 1892 | ctxt->src.val = get_segment_selector(ctxt, seg); |
0fcc207c NA |
1893 | if (ctxt->op_bytes == 4) { |
1894 | rsp_increment(ctxt, -2); | |
1895 | ctxt->op_bytes = 2; | |
1896 | } | |
7b262e90 | 1897 | |
4487b3b4 | 1898 | return em_push(ctxt); |
7b262e90 GN |
1899 | } |
1900 | ||
1cd196ea | 1901 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1902 | { |
1cd196ea | 1903 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1904 | unsigned long selector; |
1905 | int rc; | |
38ba30ba | 1906 | |
3313bc4e | 1907 | rc = emulate_pop(ctxt, &selector, 2); |
dde7e6d1 AK |
1908 | if (rc != X86EMUL_CONTINUE) |
1909 | return rc; | |
1910 | ||
a5457e7b PB |
1911 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1912 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; | |
3313bc4e NA |
1913 | if (ctxt->op_bytes > 2) |
1914 | rsp_increment(ctxt, ctxt->op_bytes - 2); | |
a5457e7b | 1915 | |
7b105ca2 | 1916 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1917 | return rc; |
38ba30ba GN |
1918 | } |
1919 | ||
b96a7fad | 1920 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1921 | { |
dd856efa | 1922 | unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); |
dde7e6d1 AK |
1923 | int rc = X86EMUL_CONTINUE; |
1924 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1925 | |
dde7e6d1 AK |
1926 | while (reg <= VCPU_REGS_RDI) { |
1927 | (reg == VCPU_REGS_RSP) ? | |
dd856efa | 1928 | (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); |
38ba30ba | 1929 | |
4487b3b4 | 1930 | rc = em_push(ctxt); |
dde7e6d1 AK |
1931 | if (rc != X86EMUL_CONTINUE) |
1932 | return rc; | |
38ba30ba | 1933 | |
dde7e6d1 | 1934 | ++reg; |
38ba30ba | 1935 | } |
38ba30ba | 1936 | |
dde7e6d1 | 1937 | return rc; |
38ba30ba GN |
1938 | } |
1939 | ||
62aaa2f0 TY |
1940 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1941 | { | |
bc397a6c | 1942 | ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM; |
62aaa2f0 TY |
1943 | return em_push(ctxt); |
1944 | } | |
1945 | ||
b96a7fad | 1946 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1947 | { |
dde7e6d1 AK |
1948 | int rc = X86EMUL_CONTINUE; |
1949 | int reg = VCPU_REGS_RDI; | |
6fd8e127 | 1950 | u32 val; |
38ba30ba | 1951 | |
dde7e6d1 AK |
1952 | while (reg >= VCPU_REGS_RAX) { |
1953 | if (reg == VCPU_REGS_RSP) { | |
5ad105e5 | 1954 | rsp_increment(ctxt, ctxt->op_bytes); |
dde7e6d1 AK |
1955 | --reg; |
1956 | } | |
38ba30ba | 1957 | |
6fd8e127 | 1958 | rc = emulate_pop(ctxt, &val, ctxt->op_bytes); |
dde7e6d1 AK |
1959 | if (rc != X86EMUL_CONTINUE) |
1960 | break; | |
6fd8e127 | 1961 | assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); |
dde7e6d1 | 1962 | --reg; |
38ba30ba | 1963 | } |
dde7e6d1 | 1964 | return rc; |
38ba30ba GN |
1965 | } |
1966 | ||
dd856efa | 1967 | static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1968 | { |
0225fb50 | 1969 | const struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1970 | int rc; |
6e154e56 MG |
1971 | struct desc_ptr dt; |
1972 | gva_t cs_addr; | |
1973 | gva_t eip_addr; | |
1974 | u16 cs, eip; | |
6e154e56 MG |
1975 | |
1976 | /* TODO: Add limit checks */ | |
9dac77fa | 1977 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1978 | rc = em_push(ctxt); |
5c56e1cf AK |
1979 | if (rc != X86EMUL_CONTINUE) |
1980 | return rc; | |
6e154e56 MG |
1981 | |
1982 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1983 | ||
9dac77fa | 1984 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1985 | rc = em_push(ctxt); |
5c56e1cf AK |
1986 | if (rc != X86EMUL_CONTINUE) |
1987 | return rc; | |
6e154e56 | 1988 | |
9dac77fa | 1989 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1990 | rc = em_push(ctxt); |
5c56e1cf AK |
1991 | if (rc != X86EMUL_CONTINUE) |
1992 | return rc; | |
1993 | ||
4bff1e86 | 1994 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1995 | |
1996 | eip_addr = dt.address + (irq << 2); | |
1997 | cs_addr = dt.address + (irq << 2) + 2; | |
1998 | ||
0f65dd70 | 1999 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
2000 | if (rc != X86EMUL_CONTINUE) |
2001 | return rc; | |
2002 | ||
0f65dd70 | 2003 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
2004 | if (rc != X86EMUL_CONTINUE) |
2005 | return rc; | |
2006 | ||
7b105ca2 | 2007 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
2008 | if (rc != X86EMUL_CONTINUE) |
2009 | return rc; | |
2010 | ||
9dac77fa | 2011 | ctxt->_eip = eip; |
6e154e56 MG |
2012 | |
2013 | return rc; | |
2014 | } | |
2015 | ||
dd856efa AK |
2016 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
2017 | { | |
2018 | int rc; | |
2019 | ||
2020 | invalidate_registers(ctxt); | |
2021 | rc = __emulate_int_real(ctxt, irq); | |
2022 | if (rc == X86EMUL_CONTINUE) | |
2023 | writeback_registers(ctxt); | |
2024 | return rc; | |
2025 | } | |
2026 | ||
7b105ca2 | 2027 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
2028 | { |
2029 | switch(ctxt->mode) { | |
2030 | case X86EMUL_MODE_REAL: | |
dd856efa | 2031 | return __emulate_int_real(ctxt, irq); |
6e154e56 MG |
2032 | case X86EMUL_MODE_VM86: |
2033 | case X86EMUL_MODE_PROT16: | |
2034 | case X86EMUL_MODE_PROT32: | |
2035 | case X86EMUL_MODE_PROT64: | |
2036 | default: | |
2037 | /* Protected mode interrupts unimplemented yet */ | |
2038 | return X86EMUL_UNHANDLEABLE; | |
2039 | } | |
2040 | } | |
2041 | ||
7b105ca2 | 2042 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 2043 | { |
dde7e6d1 AK |
2044 | int rc = X86EMUL_CONTINUE; |
2045 | unsigned long temp_eip = 0; | |
2046 | unsigned long temp_eflags = 0; | |
2047 | unsigned long cs = 0; | |
2048 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
2049 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
2050 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
2051 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 2052 | |
dde7e6d1 | 2053 | /* TODO: Add stack limit check */ |
38ba30ba | 2054 | |
9dac77fa | 2055 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 2056 | |
dde7e6d1 AK |
2057 | if (rc != X86EMUL_CONTINUE) |
2058 | return rc; | |
38ba30ba | 2059 | |
35d3d4a1 AK |
2060 | if (temp_eip & ~0xffff) |
2061 | return emulate_gp(ctxt, 0); | |
38ba30ba | 2062 | |
9dac77fa | 2063 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 2064 | |
dde7e6d1 AK |
2065 | if (rc != X86EMUL_CONTINUE) |
2066 | return rc; | |
38ba30ba | 2067 | |
9dac77fa | 2068 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 2069 | |
dde7e6d1 AK |
2070 | if (rc != X86EMUL_CONTINUE) |
2071 | return rc; | |
38ba30ba | 2072 | |
7b105ca2 | 2073 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 2074 | |
dde7e6d1 AK |
2075 | if (rc != X86EMUL_CONTINUE) |
2076 | return rc; | |
38ba30ba | 2077 | |
9dac77fa | 2078 | ctxt->_eip = temp_eip; |
38ba30ba | 2079 | |
38ba30ba | 2080 | |
9dac77fa | 2081 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 2082 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 2083 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
2084 | ctxt->eflags &= ~0xffff; |
2085 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 2086 | } |
dde7e6d1 AK |
2087 | |
2088 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
2089 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
801806d9 | 2090 | ctxt->ops->set_nmi_mask(ctxt, false); |
dde7e6d1 AK |
2091 | |
2092 | return rc; | |
38ba30ba GN |
2093 | } |
2094 | ||
e01991e7 | 2095 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 2096 | { |
dde7e6d1 AK |
2097 | switch(ctxt->mode) { |
2098 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 2099 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
2100 | case X86EMUL_MODE_VM86: |
2101 | case X86EMUL_MODE_PROT16: | |
2102 | case X86EMUL_MODE_PROT32: | |
2103 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 2104 | default: |
dde7e6d1 AK |
2105 | /* iret from protected mode unimplemented yet */ |
2106 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 2107 | } |
c37eda13 WY |
2108 | } |
2109 | ||
d2f62766 TY |
2110 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
2111 | { | |
d2f62766 | 2112 | int rc; |
d1442d85 NA |
2113 | unsigned short sel, old_sel; |
2114 | struct desc_struct old_desc, new_desc; | |
2115 | const struct x86_emulate_ops *ops = ctxt->ops; | |
2116 | u8 cpl = ctxt->ops->cpl(ctxt); | |
2117 | ||
2118 | /* Assignment of RIP may only fail in 64-bit mode */ | |
2119 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2120 | ops->get_segment(ctxt, &old_sel, &old_desc, NULL, | |
2121 | VCPU_SREG_CS); | |
d2f62766 | 2122 | |
9dac77fa | 2123 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 2124 | |
3dc4bc4f NA |
2125 | rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, |
2126 | X86_TRANSFER_CALL_JMP, | |
d1442d85 | 2127 | &new_desc); |
d2f62766 TY |
2128 | if (rc != X86EMUL_CONTINUE) |
2129 | return rc; | |
2130 | ||
d50eaa18 | 2131 | rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); |
d1442d85 | 2132 | if (rc != X86EMUL_CONTINUE) { |
7e46dddd | 2133 | WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); |
d1442d85 NA |
2134 | /* assigning eip failed; restore the old cs */ |
2135 | ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS); | |
2136 | return rc; | |
2137 | } | |
2138 | return rc; | |
d2f62766 TY |
2139 | } |
2140 | ||
f7784046 | 2141 | static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 2142 | { |
f7784046 NA |
2143 | return assign_eip_near(ctxt, ctxt->src.val); |
2144 | } | |
8cdbd2c9 | 2145 | |
f7784046 NA |
2146 | static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) |
2147 | { | |
2148 | int rc; | |
2149 | long int old_eip; | |
2150 | ||
2151 | old_eip = ctxt->_eip; | |
2152 | rc = assign_eip_near(ctxt, ctxt->src.val); | |
2153 | if (rc != X86EMUL_CONTINUE) | |
2154 | return rc; | |
2155 | ctxt->src.val = old_eip; | |
2156 | rc = em_push(ctxt); | |
4179bb02 | 2157 | return rc; |
8cdbd2c9 LV |
2158 | } |
2159 | ||
e0dac408 | 2160 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 2161 | { |
9dac77fa | 2162 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 2163 | |
aaa05f24 NA |
2164 | if (ctxt->dst.bytes == 16) |
2165 | return X86EMUL_UNHANDLEABLE; | |
2166 | ||
dd856efa AK |
2167 | if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || |
2168 | ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { | |
2169 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); | |
2170 | *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); | |
05f086f8 | 2171 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 2172 | } else { |
dd856efa AK |
2173 | ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | |
2174 | (u32) reg_read(ctxt, VCPU_REGS_RBX); | |
8cdbd2c9 | 2175 | |
05f086f8 | 2176 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 2177 | } |
1b30eaa8 | 2178 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
2179 | } |
2180 | ||
ebda02c2 TY |
2181 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
2182 | { | |
234f3ce4 NA |
2183 | int rc; |
2184 | unsigned long eip; | |
2185 | ||
2186 | rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); | |
2187 | if (rc != X86EMUL_CONTINUE) | |
2188 | return rc; | |
2189 | ||
2190 | return assign_eip_near(ctxt, eip); | |
ebda02c2 TY |
2191 | } |
2192 | ||
e01991e7 | 2193 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 2194 | { |
a77ab5ea | 2195 | int rc; |
d1442d85 NA |
2196 | unsigned long eip, cs; |
2197 | u16 old_cs; | |
9e8919ae | 2198 | int cpl = ctxt->ops->cpl(ctxt); |
d1442d85 NA |
2199 | struct desc_struct old_desc, new_desc; |
2200 | const struct x86_emulate_ops *ops = ctxt->ops; | |
2201 | ||
2202 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2203 | ops->get_segment(ctxt, &old_cs, &old_desc, NULL, | |
2204 | VCPU_SREG_CS); | |
a77ab5ea | 2205 | |
d1442d85 | 2206 | rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); |
1b30eaa8 | 2207 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2208 | return rc; |
9dac77fa | 2209 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
1b30eaa8 | 2210 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2211 | return rc; |
9e8919ae NA |
2212 | /* Outer-privilege level return is not implemented */ |
2213 | if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) | |
2214 | return X86EMUL_UNHANDLEABLE; | |
3dc4bc4f NA |
2215 | rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, |
2216 | X86_TRANSFER_RET, | |
d1442d85 NA |
2217 | &new_desc); |
2218 | if (rc != X86EMUL_CONTINUE) | |
2219 | return rc; | |
d50eaa18 | 2220 | rc = assign_eip_far(ctxt, eip, &new_desc); |
d1442d85 | 2221 | if (rc != X86EMUL_CONTINUE) { |
7e46dddd | 2222 | WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); |
d1442d85 NA |
2223 | ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); |
2224 | } | |
a77ab5ea AK |
2225 | return rc; |
2226 | } | |
2227 | ||
3261107e BR |
2228 | static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) |
2229 | { | |
2230 | int rc; | |
2231 | ||
2232 | rc = em_ret_far(ctxt); | |
2233 | if (rc != X86EMUL_CONTINUE) | |
2234 | return rc; | |
2235 | rsp_increment(ctxt, ctxt->src.val); | |
2236 | return X86EMUL_CONTINUE; | |
2237 | } | |
2238 | ||
e940b5c2 TY |
2239 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
2240 | { | |
2241 | /* Save real source value, then compare EAX against destination. */ | |
37c564f2 NA |
2242 | ctxt->dst.orig_val = ctxt->dst.val; |
2243 | ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); | |
e940b5c2 | 2244 | ctxt->src.orig_val = ctxt->src.val; |
37c564f2 | 2245 | ctxt->src.val = ctxt->dst.orig_val; |
158de57f | 2246 | fastop(ctxt, em_cmp); |
e940b5c2 TY |
2247 | |
2248 | if (ctxt->eflags & EFLG_ZF) { | |
2fcf5c8a NA |
2249 | /* Success: write back to memory; no update of EAX */ |
2250 | ctxt->src.type = OP_NONE; | |
e940b5c2 TY |
2251 | ctxt->dst.val = ctxt->src.orig_val; |
2252 | } else { | |
2253 | /* Failure: write the value we saw to EAX. */ | |
2fcf5c8a NA |
2254 | ctxt->src.type = OP_REG; |
2255 | ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); | |
2256 | ctxt->src.val = ctxt->dst.orig_val; | |
2257 | /* Create write-cycle to dest by writing the same value */ | |
37c564f2 | 2258 | ctxt->dst.val = ctxt->dst.orig_val; |
e940b5c2 TY |
2259 | } |
2260 | return X86EMUL_CONTINUE; | |
2261 | } | |
2262 | ||
d4b4325f | 2263 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 2264 | { |
d4b4325f | 2265 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
2266 | unsigned short sel; |
2267 | int rc; | |
2268 | ||
9dac77fa | 2269 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 2270 | |
7b105ca2 | 2271 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
2272 | if (rc != X86EMUL_CONTINUE) |
2273 | return rc; | |
2274 | ||
9dac77fa | 2275 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
2276 | return rc; |
2277 | } | |
2278 | ||
7b105ca2 | 2279 | static void |
e66bb2cc | 2280 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 2281 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 2282 | { |
e66bb2cc | 2283 | cs->l = 0; /* will be adjusted later */ |
79168fd1 | 2284 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 2285 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 2286 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
2287 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
2288 | cs->s = 1; | |
2289 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
2290 | cs->p = 1; |
2291 | cs->d = 1; | |
99245b50 | 2292 | cs->avl = 0; |
e66bb2cc | 2293 | |
79168fd1 GN |
2294 | set_desc_base(ss, 0); /* flat segment */ |
2295 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
2296 | ss->g = 1; /* 4kb granularity */ |
2297 | ss->s = 1; | |
2298 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 2299 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 2300 | ss->dpl = 0; |
79168fd1 | 2301 | ss->p = 1; |
99245b50 GN |
2302 | ss->l = 0; |
2303 | ss->avl = 0; | |
e66bb2cc AP |
2304 | } |
2305 | ||
1a18a69b AK |
2306 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
2307 | { | |
2308 | u32 eax, ebx, ecx, edx; | |
2309 | ||
2310 | eax = ecx = 0; | |
0017f93a AK |
2311 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2312 | return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1a18a69b AK |
2313 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx |
2314 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
2315 | } | |
2316 | ||
c2226fc9 SB |
2317 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
2318 | { | |
0225fb50 | 2319 | const struct x86_emulate_ops *ops = ctxt->ops; |
c2226fc9 SB |
2320 | u32 eax, ebx, ecx, edx; |
2321 | ||
2322 | /* | |
2323 | * syscall should always be enabled in longmode - so only become | |
2324 | * vendor specific (cpuid) if other modes are active... | |
2325 | */ | |
2326 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2327 | return true; | |
2328 | ||
2329 | eax = 0x00000000; | |
2330 | ecx = 0x00000000; | |
0017f93a AK |
2331 | ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2332 | /* | |
2333 | * Intel ("GenuineIntel") | |
2334 | * remark: Intel CPUs only support "syscall" in 64bit | |
2335 | * longmode. Also an 64bit guest with a | |
2336 | * 32bit compat-app running will #UD !! While this | |
2337 | * behaviour can be fixed (by emulating) into AMD | |
2338 | * response - CPUs of AMD can't behave like Intel. | |
2339 | */ | |
2340 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
2341 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
2342 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
2343 | return false; | |
2344 | ||
2345 | /* AMD ("AuthenticAMD") */ | |
2346 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
2347 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
2348 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
2349 | return true; | |
2350 | ||
2351 | /* AMD ("AMDisbetter!") */ | |
2352 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
2353 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
2354 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
2355 | return true; | |
c2226fc9 SB |
2356 | |
2357 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
2358 | return false; | |
2359 | } | |
2360 | ||
e01991e7 | 2361 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 2362 | { |
0225fb50 | 2363 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2364 | struct desc_struct cs, ss; |
e66bb2cc | 2365 | u64 msr_data; |
79168fd1 | 2366 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2367 | u64 efer = 0; |
e66bb2cc AP |
2368 | |
2369 | /* syscall is not available in real mode */ | |
2e901c4c | 2370 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
2371 | ctxt->mode == X86EMUL_MODE_VM86) |
2372 | return emulate_ud(ctxt); | |
e66bb2cc | 2373 | |
c2226fc9 SB |
2374 | if (!(em_syscall_is_enabled(ctxt))) |
2375 | return emulate_ud(ctxt); | |
2376 | ||
c2ad2bb3 | 2377 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 2378 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 2379 | |
c2226fc9 SB |
2380 | if (!(efer & EFER_SCE)) |
2381 | return emulate_ud(ctxt); | |
2382 | ||
717746e3 | 2383 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 2384 | msr_data >>= 32; |
79168fd1 GN |
2385 | cs_sel = (u16)(msr_data & 0xfffc); |
2386 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 2387 | |
c2ad2bb3 | 2388 | if (efer & EFER_LMA) { |
79168fd1 | 2389 | cs.d = 0; |
e66bb2cc AP |
2390 | cs.l = 1; |
2391 | } | |
1aa36616 AK |
2392 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2393 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 2394 | |
dd856efa | 2395 | *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; |
c2ad2bb3 | 2396 | if (efer & EFER_LMA) { |
e66bb2cc | 2397 | #ifdef CONFIG_X86_64 |
6c6cb69b | 2398 | *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; |
e66bb2cc | 2399 | |
717746e3 | 2400 | ops->get_msr(ctxt, |
3fb1b5db GN |
2401 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
2402 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 2403 | ctxt->_eip = msr_data; |
e66bb2cc | 2404 | |
717746e3 | 2405 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
6c6cb69b | 2406 | ctxt->eflags &= ~msr_data; |
807c1425 | 2407 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; |
e66bb2cc AP |
2408 | #endif |
2409 | } else { | |
2410 | /* legacy mode */ | |
717746e3 | 2411 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2412 | ctxt->_eip = (u32)msr_data; |
e66bb2cc | 2413 | |
6c6cb69b | 2414 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF); |
e66bb2cc AP |
2415 | } |
2416 | ||
e54cfa97 | 2417 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2418 | } |
2419 | ||
e01991e7 | 2420 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2421 | { |
0225fb50 | 2422 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2423 | struct desc_struct cs, ss; |
8c604352 | 2424 | u64 msr_data; |
79168fd1 | 2425 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2426 | u64 efer = 0; |
8c604352 | 2427 | |
7b105ca2 | 2428 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2429 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2430 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2431 | return emulate_gp(ctxt, 0); | |
8c604352 | 2432 | |
1a18a69b AK |
2433 | /* |
2434 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2435 | * mode). | |
2436 | */ | |
f3747379 | 2437 | if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) |
1a18a69b AK |
2438 | && !vendor_intel(ctxt)) |
2439 | return emulate_ud(ctxt); | |
2440 | ||
b2c9d43e | 2441 | /* sysenter/sysexit have not been tested in 64bit mode. */ |
35d3d4a1 | 2442 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
b2c9d43e | 2443 | return X86EMUL_UNHANDLEABLE; |
8c604352 | 2444 | |
7b105ca2 | 2445 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2446 | |
717746e3 | 2447 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
f3747379 NA |
2448 | if ((msr_data & 0xfffc) == 0x0) |
2449 | return emulate_gp(ctxt, 0); | |
8c604352 | 2450 | |
6c6cb69b | 2451 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF); |
f3747379 | 2452 | cs_sel = (u16)msr_data & ~SELECTOR_RPL_MASK; |
79168fd1 | 2453 | ss_sel = cs_sel + 8; |
f3747379 | 2454 | if (efer & EFER_LMA) { |
79168fd1 | 2455 | cs.d = 0; |
8c604352 AP |
2456 | cs.l = 1; |
2457 | } | |
2458 | ||
1aa36616 AK |
2459 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2460 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2461 | |
717746e3 | 2462 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
f3747379 | 2463 | ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; |
8c604352 | 2464 | |
717746e3 | 2465 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
f3747379 NA |
2466 | *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : |
2467 | (u32)msr_data; | |
8c604352 | 2468 | |
e54cfa97 | 2469 | return X86EMUL_CONTINUE; |
8c604352 AP |
2470 | } |
2471 | ||
e01991e7 | 2472 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2473 | { |
0225fb50 | 2474 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2475 | struct desc_struct cs, ss; |
234f3ce4 | 2476 | u64 msr_data, rcx, rdx; |
4668f050 | 2477 | int usermode; |
1249b96e | 2478 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2479 | |
a0044755 GN |
2480 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2481 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2482 | ctxt->mode == X86EMUL_MODE_VM86) |
2483 | return emulate_gp(ctxt, 0); | |
4668f050 | 2484 | |
7b105ca2 | 2485 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2486 | |
9dac77fa | 2487 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2488 | usermode = X86EMUL_MODE_PROT64; |
2489 | else | |
2490 | usermode = X86EMUL_MODE_PROT32; | |
2491 | ||
234f3ce4 NA |
2492 | rcx = reg_read(ctxt, VCPU_REGS_RCX); |
2493 | rdx = reg_read(ctxt, VCPU_REGS_RDX); | |
2494 | ||
4668f050 AP |
2495 | cs.dpl = 3; |
2496 | ss.dpl = 3; | |
717746e3 | 2497 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2498 | switch (usermode) { |
2499 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2500 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2501 | if ((msr_data & 0xfffc) == 0x0) |
2502 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2503 | ss_sel = (u16)(msr_data + 24); |
bf0b682c NA |
2504 | rcx = (u32)rcx; |
2505 | rdx = (u32)rdx; | |
4668f050 AP |
2506 | break; |
2507 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2508 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2509 | if (msr_data == 0x0) |
2510 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2511 | ss_sel = cs_sel + 8; |
2512 | cs.d = 0; | |
4668f050 | 2513 | cs.l = 1; |
234f3ce4 NA |
2514 | if (is_noncanonical_address(rcx) || |
2515 | is_noncanonical_address(rdx)) | |
2516 | return emulate_gp(ctxt, 0); | |
4668f050 AP |
2517 | break; |
2518 | } | |
79168fd1 GN |
2519 | cs_sel |= SELECTOR_RPL_MASK; |
2520 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2521 | |
1aa36616 AK |
2522 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2523 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2524 | |
234f3ce4 NA |
2525 | ctxt->_eip = rdx; |
2526 | *reg_write(ctxt, VCPU_REGS_RSP) = rcx; | |
4668f050 | 2527 | |
e54cfa97 | 2528 | return X86EMUL_CONTINUE; |
4668f050 AP |
2529 | } |
2530 | ||
7b105ca2 | 2531 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2532 | { |
2533 | int iopl; | |
2534 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2535 | return false; | |
2536 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2537 | return true; | |
2538 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2539 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2540 | } |
2541 | ||
2542 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2543 | u16 port, u16 len) |
2544 | { | |
0225fb50 | 2545 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2546 | struct desc_struct tr_seg; |
5601d05b | 2547 | u32 base3; |
f850e2e6 | 2548 | int r; |
1aa36616 | 2549 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2550 | unsigned mask = (1 << len) - 1; |
5601d05b | 2551 | unsigned long base; |
f850e2e6 | 2552 | |
1aa36616 | 2553 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2554 | if (!tr_seg.p) |
f850e2e6 | 2555 | return false; |
79168fd1 | 2556 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2557 | return false; |
5601d05b GN |
2558 | base = get_desc_base(&tr_seg); |
2559 | #ifdef CONFIG_X86_64 | |
2560 | base |= ((u64)base3) << 32; | |
2561 | #endif | |
0f65dd70 | 2562 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2563 | if (r != X86EMUL_CONTINUE) |
2564 | return false; | |
79168fd1 | 2565 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2566 | return false; |
0f65dd70 | 2567 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2568 | if (r != X86EMUL_CONTINUE) |
2569 | return false; | |
2570 | if ((perm >> bit_idx) & mask) | |
2571 | return false; | |
2572 | return true; | |
2573 | } | |
2574 | ||
2575 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2576 | u16 port, u16 len) |
2577 | { | |
4fc40f07 GN |
2578 | if (ctxt->perm_ok) |
2579 | return true; | |
2580 | ||
7b105ca2 TY |
2581 | if (emulator_bad_iopl(ctxt)) |
2582 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2583 | return false; |
4fc40f07 GN |
2584 | |
2585 | ctxt->perm_ok = true; | |
2586 | ||
f850e2e6 GN |
2587 | return true; |
2588 | } | |
2589 | ||
38ba30ba | 2590 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2591 | struct tss_segment_16 *tss) |
2592 | { | |
9dac77fa | 2593 | tss->ip = ctxt->_eip; |
38ba30ba | 2594 | tss->flag = ctxt->eflags; |
dd856efa AK |
2595 | tss->ax = reg_read(ctxt, VCPU_REGS_RAX); |
2596 | tss->cx = reg_read(ctxt, VCPU_REGS_RCX); | |
2597 | tss->dx = reg_read(ctxt, VCPU_REGS_RDX); | |
2598 | tss->bx = reg_read(ctxt, VCPU_REGS_RBX); | |
2599 | tss->sp = reg_read(ctxt, VCPU_REGS_RSP); | |
2600 | tss->bp = reg_read(ctxt, VCPU_REGS_RBP); | |
2601 | tss->si = reg_read(ctxt, VCPU_REGS_RSI); | |
2602 | tss->di = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2603 | |
1aa36616 AK |
2604 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2605 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2606 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2607 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2608 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2609 | } |
2610 | ||
2611 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2612 | struct tss_segment_16 *tss) |
2613 | { | |
38ba30ba | 2614 | int ret; |
2356aaeb | 2615 | u8 cpl; |
38ba30ba | 2616 | |
9dac77fa | 2617 | ctxt->_eip = tss->ip; |
38ba30ba | 2618 | ctxt->eflags = tss->flag | 2; |
dd856efa AK |
2619 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; |
2620 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; | |
2621 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; | |
2622 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; | |
2623 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; | |
2624 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; | |
2625 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; | |
2626 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; | |
38ba30ba GN |
2627 | |
2628 | /* | |
2629 | * SDM says that segment selectors are loaded before segment | |
2630 | * descriptors | |
2631 | */ | |
1aa36616 AK |
2632 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2633 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2634 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2635 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2636 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba | 2637 | |
2356aaeb PB |
2638 | cpl = tss->cs & 3; |
2639 | ||
38ba30ba | 2640 | /* |
fc058680 | 2641 | * Now load segment descriptors. If fault happens at this stage |
38ba30ba GN |
2642 | * it is handled in a context of new task |
2643 | */ | |
d1442d85 | 2644 | ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, |
3dc4bc4f | 2645 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2646 | if (ret != X86EMUL_CONTINUE) |
2647 | return ret; | |
d1442d85 | 2648 | ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, |
3dc4bc4f | 2649 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2650 | if (ret != X86EMUL_CONTINUE) |
2651 | return ret; | |
d1442d85 | 2652 | ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, |
3dc4bc4f | 2653 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2654 | if (ret != X86EMUL_CONTINUE) |
2655 | return ret; | |
d1442d85 | 2656 | ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, |
3dc4bc4f | 2657 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2658 | if (ret != X86EMUL_CONTINUE) |
2659 | return ret; | |
d1442d85 | 2660 | ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, |
3dc4bc4f | 2661 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2662 | if (ret != X86EMUL_CONTINUE) |
2663 | return ret; | |
2664 | ||
2665 | return X86EMUL_CONTINUE; | |
2666 | } | |
2667 | ||
2668 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2669 | u16 tss_selector, u16 old_tss_sel, |
2670 | ulong old_tss_base, struct desc_struct *new_desc) | |
2671 | { | |
0225fb50 | 2672 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2673 | struct tss_segment_16 tss_seg; |
2674 | int ret; | |
bcc55cba | 2675 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2676 | |
0f65dd70 | 2677 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2678 | &ctxt->exception); |
db297e3d | 2679 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2680 | return ret; |
38ba30ba | 2681 | |
7b105ca2 | 2682 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2683 | |
0f65dd70 | 2684 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2685 | &ctxt->exception); |
db297e3d | 2686 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2687 | return ret; |
38ba30ba | 2688 | |
0f65dd70 | 2689 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2690 | &ctxt->exception); |
db297e3d | 2691 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2692 | return ret; |
38ba30ba GN |
2693 | |
2694 | if (old_tss_sel != 0xffff) { | |
2695 | tss_seg.prev_task_link = old_tss_sel; | |
2696 | ||
0f65dd70 | 2697 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2698 | &tss_seg.prev_task_link, |
2699 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2700 | &ctxt->exception); |
db297e3d | 2701 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2702 | return ret; |
38ba30ba GN |
2703 | } |
2704 | ||
7b105ca2 | 2705 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2706 | } |
2707 | ||
2708 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2709 | struct tss_segment_32 *tss) |
2710 | { | |
5c7411e2 | 2711 | /* CR3 and ldt selector are not saved intentionally */ |
9dac77fa | 2712 | tss->eip = ctxt->_eip; |
38ba30ba | 2713 | tss->eflags = ctxt->eflags; |
dd856efa AK |
2714 | tss->eax = reg_read(ctxt, VCPU_REGS_RAX); |
2715 | tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
2716 | tss->edx = reg_read(ctxt, VCPU_REGS_RDX); | |
2717 | tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); | |
2718 | tss->esp = reg_read(ctxt, VCPU_REGS_RSP); | |
2719 | tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); | |
2720 | tss->esi = reg_read(ctxt, VCPU_REGS_RSI); | |
2721 | tss->edi = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2722 | |
1aa36616 AK |
2723 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2724 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2725 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2726 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2727 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2728 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
38ba30ba GN |
2729 | } |
2730 | ||
2731 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2732 | struct tss_segment_32 *tss) |
2733 | { | |
38ba30ba | 2734 | int ret; |
2356aaeb | 2735 | u8 cpl; |
38ba30ba | 2736 | |
7b105ca2 | 2737 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2738 | return emulate_gp(ctxt, 0); |
9dac77fa | 2739 | ctxt->_eip = tss->eip; |
38ba30ba | 2740 | ctxt->eflags = tss->eflags | 2; |
4cee4798 KW |
2741 | |
2742 | /* General purpose registers */ | |
dd856efa AK |
2743 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; |
2744 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; | |
2745 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; | |
2746 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; | |
2747 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; | |
2748 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; | |
2749 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; | |
2750 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; | |
38ba30ba GN |
2751 | |
2752 | /* | |
2753 | * SDM says that segment selectors are loaded before segment | |
2356aaeb PB |
2754 | * descriptors. This is important because CPL checks will |
2755 | * use CS.RPL. | |
38ba30ba | 2756 | */ |
1aa36616 AK |
2757 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2758 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2759 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2760 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2761 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2762 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2763 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba | 2764 | |
4cee4798 KW |
2765 | /* |
2766 | * If we're switching between Protected Mode and VM86, we need to make | |
2767 | * sure to update the mode before loading the segment descriptors so | |
2768 | * that the selectors are interpreted correctly. | |
4cee4798 | 2769 | */ |
2356aaeb | 2770 | if (ctxt->eflags & X86_EFLAGS_VM) { |
4cee4798 | 2771 | ctxt->mode = X86EMUL_MODE_VM86; |
2356aaeb PB |
2772 | cpl = 3; |
2773 | } else { | |
4cee4798 | 2774 | ctxt->mode = X86EMUL_MODE_PROT32; |
2356aaeb PB |
2775 | cpl = tss->cs & 3; |
2776 | } | |
4cee4798 | 2777 | |
38ba30ba GN |
2778 | /* |
2779 | * Now load segment descriptors. If fault happenes at this stage | |
2780 | * it is handled in a context of new task | |
2781 | */ | |
d1442d85 | 2782 | ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, |
3dc4bc4f | 2783 | cpl, X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2784 | if (ret != X86EMUL_CONTINUE) |
2785 | return ret; | |
d1442d85 | 2786 | ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, |
3dc4bc4f | 2787 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2788 | if (ret != X86EMUL_CONTINUE) |
2789 | return ret; | |
d1442d85 | 2790 | ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, |
3dc4bc4f | 2791 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2792 | if (ret != X86EMUL_CONTINUE) |
2793 | return ret; | |
d1442d85 | 2794 | ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, |
3dc4bc4f | 2795 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2796 | if (ret != X86EMUL_CONTINUE) |
2797 | return ret; | |
d1442d85 | 2798 | ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, |
3dc4bc4f | 2799 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2800 | if (ret != X86EMUL_CONTINUE) |
2801 | return ret; | |
d1442d85 | 2802 | ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, |
3dc4bc4f | 2803 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2804 | if (ret != X86EMUL_CONTINUE) |
2805 | return ret; | |
d1442d85 | 2806 | ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, |
3dc4bc4f | 2807 | X86_TRANSFER_TASK_SWITCH, NULL); |
38ba30ba GN |
2808 | if (ret != X86EMUL_CONTINUE) |
2809 | return ret; | |
2810 | ||
2811 | return X86EMUL_CONTINUE; | |
2812 | } | |
2813 | ||
2814 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2815 | u16 tss_selector, u16 old_tss_sel, |
2816 | ulong old_tss_base, struct desc_struct *new_desc) | |
2817 | { | |
0225fb50 | 2818 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2819 | struct tss_segment_32 tss_seg; |
2820 | int ret; | |
bcc55cba | 2821 | u32 new_tss_base = get_desc_base(new_desc); |
5c7411e2 NA |
2822 | u32 eip_offset = offsetof(struct tss_segment_32, eip); |
2823 | u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); | |
38ba30ba | 2824 | |
0f65dd70 | 2825 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2826 | &ctxt->exception); |
db297e3d | 2827 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2828 | return ret; |
38ba30ba | 2829 | |
7b105ca2 | 2830 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2831 | |
5c7411e2 NA |
2832 | /* Only GP registers and segment selectors are saved */ |
2833 | ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, | |
2834 | ldt_sel_offset - eip_offset, &ctxt->exception); | |
db297e3d | 2835 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2836 | return ret; |
38ba30ba | 2837 | |
0f65dd70 | 2838 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2839 | &ctxt->exception); |
db297e3d | 2840 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2841 | return ret; |
38ba30ba GN |
2842 | |
2843 | if (old_tss_sel != 0xffff) { | |
2844 | tss_seg.prev_task_link = old_tss_sel; | |
2845 | ||
0f65dd70 | 2846 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2847 | &tss_seg.prev_task_link, |
2848 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2849 | &ctxt->exception); |
db297e3d | 2850 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2851 | return ret; |
38ba30ba GN |
2852 | } |
2853 | ||
7b105ca2 | 2854 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2855 | } |
2856 | ||
2857 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2858 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2859 | bool has_error_code, u32 error_code) |
38ba30ba | 2860 | { |
0225fb50 | 2861 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2862 | struct desc_struct curr_tss_desc, next_tss_desc; |
2863 | int ret; | |
1aa36616 | 2864 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2865 | ulong old_tss_base = |
4bff1e86 | 2866 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2867 | u32 desc_limit; |
e919464b | 2868 | ulong desc_addr; |
38ba30ba GN |
2869 | |
2870 | /* FIXME: old_tss_base == ~0 ? */ | |
2871 | ||
e919464b | 2872 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); |
38ba30ba GN |
2873 | if (ret != X86EMUL_CONTINUE) |
2874 | return ret; | |
e919464b | 2875 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); |
38ba30ba GN |
2876 | if (ret != X86EMUL_CONTINUE) |
2877 | return ret; | |
2878 | ||
2879 | /* FIXME: check that next_tss_desc is tss */ | |
2880 | ||
7f3d35fd KW |
2881 | /* |
2882 | * Check privileges. The three cases are task switch caused by... | |
2883 | * | |
2884 | * 1. jmp/call/int to task gate: Check against DPL of the task gate | |
2885 | * 2. Exception/IRQ/iret: No check is performed | |
2c2ca2d1 NA |
2886 | * 3. jmp/call to TSS/task-gate: No check is performed since the |
2887 | * hardware checks it before exiting. | |
7f3d35fd KW |
2888 | */ |
2889 | if (reason == TASK_SWITCH_GATE) { | |
2890 | if (idt_index != -1) { | |
2891 | /* Software interrupts */ | |
2892 | struct desc_struct task_gate_desc; | |
2893 | int dpl; | |
2894 | ||
2895 | ret = read_interrupt_descriptor(ctxt, idt_index, | |
2896 | &task_gate_desc); | |
2897 | if (ret != X86EMUL_CONTINUE) | |
2898 | return ret; | |
2899 | ||
2900 | dpl = task_gate_desc.dpl; | |
2901 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2902 | return emulate_gp(ctxt, (idt_index << 3) | 0x2); | |
2903 | } | |
38ba30ba GN |
2904 | } |
2905 | ||
ceffb459 GN |
2906 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2907 | if (!next_tss_desc.p || | |
2908 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2909 | desc_limit < 0x2b)) { | |
592f0858 | 2910 | return emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2911 | } |
2912 | ||
2913 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2914 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2915 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2916 | } |
2917 | ||
2918 | if (reason == TASK_SWITCH_IRET) | |
2919 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2920 | ||
2921 | /* set back link to prev task only if NT bit is set in eflags | |
fc058680 | 2922 | note that old_tss_sel is not used after this point */ |
38ba30ba GN |
2923 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) |
2924 | old_tss_sel = 0xffff; | |
2925 | ||
2926 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2927 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2928 | old_tss_base, &next_tss_desc); |
2929 | else | |
7b105ca2 | 2930 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2931 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2932 | if (ret != X86EMUL_CONTINUE) |
2933 | return ret; | |
38ba30ba GN |
2934 | |
2935 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2936 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2937 | ||
2938 | if (reason != TASK_SWITCH_IRET) { | |
2939 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2940 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2941 | } |
2942 | ||
717746e3 | 2943 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2944 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2945 | |
e269fb21 | 2946 | if (has_error_code) { |
9dac77fa AK |
2947 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2948 | ctxt->lock_prefix = 0; | |
2949 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2950 | ret = em_push(ctxt); |
e269fb21 JK |
2951 | } |
2952 | ||
38ba30ba GN |
2953 | return ret; |
2954 | } | |
2955 | ||
2956 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2957 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2958 | bool has_error_code, u32 error_code) |
38ba30ba | 2959 | { |
38ba30ba GN |
2960 | int rc; |
2961 | ||
dd856efa | 2962 | invalidate_registers(ctxt); |
9dac77fa AK |
2963 | ctxt->_eip = ctxt->eip; |
2964 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2965 | |
7f3d35fd | 2966 | rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
e269fb21 | 2967 | has_error_code, error_code); |
38ba30ba | 2968 | |
dd856efa | 2969 | if (rc == X86EMUL_CONTINUE) { |
9dac77fa | 2970 | ctxt->eip = ctxt->_eip; |
dd856efa AK |
2971 | writeback_registers(ctxt); |
2972 | } | |
38ba30ba | 2973 | |
a0c0ab2f | 2974 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2975 | } |
2976 | ||
f3bd64c6 GN |
2977 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, |
2978 | struct operand *op) | |
a682e354 | 2979 | { |
b3356bf0 | 2980 | int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; |
a682e354 | 2981 | |
01485a22 PB |
2982 | register_address_increment(ctxt, reg, df * op->bytes); |
2983 | op->addr.mem.ea = register_address(ctxt, reg); | |
a682e354 GN |
2984 | } |
2985 | ||
7af04fc0 AK |
2986 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2987 | { | |
7af04fc0 AK |
2988 | u8 al, old_al; |
2989 | bool af, cf, old_cf; | |
2990 | ||
2991 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2992 | al = ctxt->dst.val; |
7af04fc0 AK |
2993 | |
2994 | old_al = al; | |
2995 | old_cf = cf; | |
2996 | cf = false; | |
2997 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2998 | if ((al & 0x0f) > 9 || af) { | |
2999 | al -= 6; | |
3000 | cf = old_cf | (al >= 250); | |
3001 | af = true; | |
3002 | } else { | |
3003 | af = false; | |
3004 | } | |
3005 | if (old_al > 0x99 || old_cf) { | |
3006 | al -= 0x60; | |
3007 | cf = true; | |
3008 | } | |
3009 | ||
9dac77fa | 3010 | ctxt->dst.val = al; |
7af04fc0 | 3011 | /* Set PF, ZF, SF */ |
9dac77fa AK |
3012 | ctxt->src.type = OP_IMM; |
3013 | ctxt->src.val = 0; | |
3014 | ctxt->src.bytes = 1; | |
158de57f | 3015 | fastop(ctxt, em_or); |
7af04fc0 AK |
3016 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
3017 | if (cf) | |
3018 | ctxt->eflags |= X86_EFLAGS_CF; | |
3019 | if (af) | |
3020 | ctxt->eflags |= X86_EFLAGS_AF; | |
3021 | return X86EMUL_CONTINUE; | |
3022 | } | |
3023 | ||
a035d5c6 PB |
3024 | static int em_aam(struct x86_emulate_ctxt *ctxt) |
3025 | { | |
3026 | u8 al, ah; | |
3027 | ||
3028 | if (ctxt->src.val == 0) | |
3029 | return emulate_de(ctxt); | |
3030 | ||
3031 | al = ctxt->dst.val & 0xff; | |
3032 | ah = al / ctxt->src.val; | |
3033 | al %= ctxt->src.val; | |
3034 | ||
3035 | ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); | |
3036 | ||
3037 | /* Set PF, ZF, SF */ | |
3038 | ctxt->src.type = OP_IMM; | |
3039 | ctxt->src.val = 0; | |
3040 | ctxt->src.bytes = 1; | |
3041 | fastop(ctxt, em_or); | |
3042 | ||
3043 | return X86EMUL_CONTINUE; | |
3044 | } | |
3045 | ||
7f662273 GN |
3046 | static int em_aad(struct x86_emulate_ctxt *ctxt) |
3047 | { | |
3048 | u8 al = ctxt->dst.val & 0xff; | |
3049 | u8 ah = (ctxt->dst.val >> 8) & 0xff; | |
3050 | ||
3051 | al = (al + (ah * ctxt->src.val)) & 0xff; | |
3052 | ||
3053 | ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; | |
3054 | ||
f583c29b GN |
3055 | /* Set PF, ZF, SF */ |
3056 | ctxt->src.type = OP_IMM; | |
3057 | ctxt->src.val = 0; | |
3058 | ctxt->src.bytes = 1; | |
3059 | fastop(ctxt, em_or); | |
7f662273 GN |
3060 | |
3061 | return X86EMUL_CONTINUE; | |
3062 | } | |
3063 | ||
d4ddafcd TY |
3064 | static int em_call(struct x86_emulate_ctxt *ctxt) |
3065 | { | |
234f3ce4 | 3066 | int rc; |
d4ddafcd TY |
3067 | long rel = ctxt->src.val; |
3068 | ||
3069 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
234f3ce4 NA |
3070 | rc = jmp_rel(ctxt, rel); |
3071 | if (rc != X86EMUL_CONTINUE) | |
3072 | return rc; | |
d4ddafcd TY |
3073 | return em_push(ctxt); |
3074 | } | |
3075 | ||
0ef753b8 AK |
3076 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
3077 | { | |
0ef753b8 AK |
3078 | u16 sel, old_cs; |
3079 | ulong old_eip; | |
3080 | int rc; | |
d1442d85 NA |
3081 | struct desc_struct old_desc, new_desc; |
3082 | const struct x86_emulate_ops *ops = ctxt->ops; | |
3083 | int cpl = ctxt->ops->cpl(ctxt); | |
82268083 | 3084 | enum x86emul_mode prev_mode = ctxt->mode; |
0ef753b8 | 3085 | |
9dac77fa | 3086 | old_eip = ctxt->_eip; |
d1442d85 | 3087 | ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); |
0ef753b8 | 3088 | |
9dac77fa | 3089 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
3dc4bc4f NA |
3090 | rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, |
3091 | X86_TRANSFER_CALL_JMP, &new_desc); | |
d1442d85 | 3092 | if (rc != X86EMUL_CONTINUE) |
80976dbb | 3093 | return rc; |
0ef753b8 | 3094 | |
d50eaa18 | 3095 | rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); |
d1442d85 NA |
3096 | if (rc != X86EMUL_CONTINUE) |
3097 | goto fail; | |
0ef753b8 | 3098 | |
9dac77fa | 3099 | ctxt->src.val = old_cs; |
4487b3b4 | 3100 | rc = em_push(ctxt); |
0ef753b8 | 3101 | if (rc != X86EMUL_CONTINUE) |
d1442d85 | 3102 | goto fail; |
0ef753b8 | 3103 | |
9dac77fa | 3104 | ctxt->src.val = old_eip; |
d1442d85 NA |
3105 | rc = em_push(ctxt); |
3106 | /* If we failed, we tainted the memory, but the very least we should | |
3107 | restore cs */ | |
82268083 NA |
3108 | if (rc != X86EMUL_CONTINUE) { |
3109 | pr_warn_once("faulting far call emulation tainted memory\n"); | |
d1442d85 | 3110 | goto fail; |
82268083 | 3111 | } |
d1442d85 NA |
3112 | return rc; |
3113 | fail: | |
3114 | ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); | |
82268083 | 3115 | ctxt->mode = prev_mode; |
d1442d85 NA |
3116 | return rc; |
3117 | ||
0ef753b8 AK |
3118 | } |
3119 | ||
40ece7c7 AK |
3120 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
3121 | { | |
40ece7c7 | 3122 | int rc; |
234f3ce4 | 3123 | unsigned long eip; |
40ece7c7 | 3124 | |
234f3ce4 NA |
3125 | rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); |
3126 | if (rc != X86EMUL_CONTINUE) | |
3127 | return rc; | |
3128 | rc = assign_eip_near(ctxt, eip); | |
40ece7c7 AK |
3129 | if (rc != X86EMUL_CONTINUE) |
3130 | return rc; | |
5ad105e5 | 3131 | rsp_increment(ctxt, ctxt->src.val); |
40ece7c7 AK |
3132 | return X86EMUL_CONTINUE; |
3133 | } | |
3134 | ||
e4f973ae TY |
3135 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
3136 | { | |
e4f973ae | 3137 | /* Write back the register source. */ |
9dac77fa AK |
3138 | ctxt->src.val = ctxt->dst.val; |
3139 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
3140 | |
3141 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
3142 | ctxt->dst.val = ctxt->src.orig_val; |
3143 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
3144 | return X86EMUL_CONTINUE; |
3145 | } | |
3146 | ||
5c82aa29 AK |
3147 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
3148 | { | |
9dac77fa | 3149 | ctxt->dst.val = ctxt->src2.val; |
4d758349 | 3150 | return fastop(ctxt, em_imul); |
5c82aa29 AK |
3151 | } |
3152 | ||
61429142 AK |
3153 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
3154 | { | |
9dac77fa AK |
3155 | ctxt->dst.type = OP_REG; |
3156 | ctxt->dst.bytes = ctxt->src.bytes; | |
dd856efa | 3157 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
9dac77fa | 3158 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); |
61429142 AK |
3159 | |
3160 | return X86EMUL_CONTINUE; | |
3161 | } | |
3162 | ||
48bb5d3c AK |
3163 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
3164 | { | |
48bb5d3c AK |
3165 | u64 tsc = 0; |
3166 | ||
717746e3 | 3167 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
dd856efa AK |
3168 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; |
3169 | *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; | |
48bb5d3c AK |
3170 | return X86EMUL_CONTINUE; |
3171 | } | |
3172 | ||
222d21aa AK |
3173 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
3174 | { | |
3175 | u64 pmc; | |
3176 | ||
dd856efa | 3177 | if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) |
222d21aa | 3178 | return emulate_gp(ctxt, 0); |
dd856efa AK |
3179 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; |
3180 | *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; | |
222d21aa AK |
3181 | return X86EMUL_CONTINUE; |
3182 | } | |
3183 | ||
b9eac5f4 AK |
3184 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
3185 | { | |
54cfdb3e | 3186 | memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); |
b9eac5f4 AK |
3187 | return X86EMUL_CONTINUE; |
3188 | } | |
3189 | ||
84cffe49 BP |
3190 | #define FFL(x) bit(X86_FEATURE_##x) |
3191 | ||
3192 | static int em_movbe(struct x86_emulate_ctxt *ctxt) | |
3193 | { | |
3194 | u32 ebx, ecx, edx, eax = 1; | |
3195 | u16 tmp; | |
3196 | ||
3197 | /* | |
3198 | * Check MOVBE is set in the guest-visible CPUID leaf. | |
3199 | */ | |
3200 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); | |
3201 | if (!(ecx & FFL(MOVBE))) | |
3202 | return emulate_ud(ctxt); | |
3203 | ||
3204 | switch (ctxt->op_bytes) { | |
3205 | case 2: | |
3206 | /* | |
3207 | * From MOVBE definition: "...When the operand size is 16 bits, | |
3208 | * the upper word of the destination register remains unchanged | |
3209 | * ..." | |
3210 | * | |
3211 | * Both casting ->valptr and ->val to u16 breaks strict aliasing | |
3212 | * rules so we have to do the operation almost per hand. | |
3213 | */ | |
3214 | tmp = (u16)ctxt->src.val; | |
3215 | ctxt->dst.val &= ~0xffffUL; | |
3216 | ctxt->dst.val |= (unsigned long)swab16(tmp); | |
3217 | break; | |
3218 | case 4: | |
3219 | ctxt->dst.val = swab32((u32)ctxt->src.val); | |
3220 | break; | |
3221 | case 8: | |
3222 | ctxt->dst.val = swab64(ctxt->src.val); | |
3223 | break; | |
3224 | default: | |
592f0858 | 3225 | BUG(); |
84cffe49 BP |
3226 | } |
3227 | return X86EMUL_CONTINUE; | |
3228 | } | |
3229 | ||
bc00f8d2 TY |
3230 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
3231 | { | |
3232 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
3233 | return emulate_gp(ctxt, 0); | |
3234 | ||
3235 | /* Disable writeback. */ | |
3236 | ctxt->dst.type = OP_NONE; | |
3237 | return X86EMUL_CONTINUE; | |
3238 | } | |
3239 | ||
3240 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
3241 | { | |
3242 | unsigned long val; | |
3243 | ||
3244 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3245 | val = ctxt->src.val & ~0ULL; | |
3246 | else | |
3247 | val = ctxt->src.val & ~0U; | |
3248 | ||
3249 | /* #UD condition is already handled. */ | |
3250 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
3251 | return emulate_gp(ctxt, 0); | |
3252 | ||
3253 | /* Disable writeback. */ | |
3254 | ctxt->dst.type = OP_NONE; | |
3255 | return X86EMUL_CONTINUE; | |
3256 | } | |
3257 | ||
e1e210b0 TY |
3258 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
3259 | { | |
3260 | u64 msr_data; | |
3261 | ||
dd856efa AK |
3262 | msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) |
3263 | | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); | |
3264 | if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) | |
e1e210b0 TY |
3265 | return emulate_gp(ctxt, 0); |
3266 | ||
3267 | return X86EMUL_CONTINUE; | |
3268 | } | |
3269 | ||
3270 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
3271 | { | |
3272 | u64 msr_data; | |
3273 | ||
dd856efa | 3274 | if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) |
e1e210b0 TY |
3275 | return emulate_gp(ctxt, 0); |
3276 | ||
dd856efa AK |
3277 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; |
3278 | *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; | |
e1e210b0 TY |
3279 | return X86EMUL_CONTINUE; |
3280 | } | |
3281 | ||
1bd5f469 TY |
3282 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
3283 | { | |
9dac77fa | 3284 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3285 | return emulate_ud(ctxt); |
3286 | ||
9dac77fa | 3287 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
b5bbf10e NA |
3288 | if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) |
3289 | ctxt->dst.bytes = 2; | |
1bd5f469 TY |
3290 | return X86EMUL_CONTINUE; |
3291 | } | |
3292 | ||
3293 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
3294 | { | |
9dac77fa | 3295 | u16 sel = ctxt->src.val; |
1bd5f469 | 3296 | |
9dac77fa | 3297 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3298 | return emulate_ud(ctxt); |
3299 | ||
9dac77fa | 3300 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
3301 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
3302 | ||
3303 | /* Disable writeback. */ | |
9dac77fa AK |
3304 | ctxt->dst.type = OP_NONE; |
3305 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
3306 | } |
3307 | ||
a14e579f AK |
3308 | static int em_lldt(struct x86_emulate_ctxt *ctxt) |
3309 | { | |
3310 | u16 sel = ctxt->src.val; | |
3311 | ||
3312 | /* Disable writeback. */ | |
3313 | ctxt->dst.type = OP_NONE; | |
3314 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); | |
3315 | } | |
3316 | ||
80890006 AK |
3317 | static int em_ltr(struct x86_emulate_ctxt *ctxt) |
3318 | { | |
3319 | u16 sel = ctxt->src.val; | |
3320 | ||
3321 | /* Disable writeback. */ | |
3322 | ctxt->dst.type = OP_NONE; | |
3323 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); | |
3324 | } | |
3325 | ||
38503911 AK |
3326 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
3327 | { | |
9fa088f4 AK |
3328 | int rc; |
3329 | ulong linear; | |
3330 | ||
9dac77fa | 3331 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 3332 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 3333 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 3334 | /* Disable writeback. */ |
9dac77fa | 3335 | ctxt->dst.type = OP_NONE; |
38503911 AK |
3336 | return X86EMUL_CONTINUE; |
3337 | } | |
3338 | ||
2d04a05b AK |
3339 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
3340 | { | |
3341 | ulong cr0; | |
3342 | ||
3343 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
3344 | cr0 &= ~X86_CR0_TS; | |
3345 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
3346 | return X86EMUL_CONTINUE; | |
3347 | } | |
3348 | ||
b34a8051 | 3349 | static int em_hypercall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 3350 | { |
0f54a321 | 3351 | int rc = ctxt->ops->fix_hypercall(ctxt); |
26d05cc7 | 3352 | |
26d05cc7 AK |
3353 | if (rc != X86EMUL_CONTINUE) |
3354 | return rc; | |
3355 | ||
3356 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 3357 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 3358 | /* Disable writeback. */ |
9dac77fa | 3359 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3360 | return X86EMUL_CONTINUE; |
3361 | } | |
3362 | ||
96051572 AK |
3363 | static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, |
3364 | void (*get)(struct x86_emulate_ctxt *ctxt, | |
3365 | struct desc_ptr *ptr)) | |
3366 | { | |
3367 | struct desc_ptr desc_ptr; | |
3368 | ||
3369 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3370 | ctxt->op_bytes = 8; | |
3371 | get(ctxt, &desc_ptr); | |
3372 | if (ctxt->op_bytes == 2) { | |
3373 | ctxt->op_bytes = 4; | |
3374 | desc_ptr.address &= 0x00ffffff; | |
3375 | } | |
3376 | /* Disable writeback. */ | |
3377 | ctxt->dst.type = OP_NONE; | |
3378 | return segmented_write(ctxt, ctxt->dst.addr.mem, | |
3379 | &desc_ptr, 2 + ctxt->op_bytes); | |
3380 | } | |
3381 | ||
3382 | static int em_sgdt(struct x86_emulate_ctxt *ctxt) | |
3383 | { | |
3384 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); | |
3385 | } | |
3386 | ||
3387 | static int em_sidt(struct x86_emulate_ctxt *ctxt) | |
3388 | { | |
3389 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); | |
3390 | } | |
3391 | ||
5b7f6a1e | 3392 | static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) |
26d05cc7 | 3393 | { |
26d05cc7 AK |
3394 | struct desc_ptr desc_ptr; |
3395 | int rc; | |
3396 | ||
510425ff AK |
3397 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3398 | ctxt->op_bytes = 8; | |
9dac77fa | 3399 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 3400 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3401 | ctxt->op_bytes); |
26d05cc7 AK |
3402 | if (rc != X86EMUL_CONTINUE) |
3403 | return rc; | |
9a9abf6b NA |
3404 | if (ctxt->mode == X86EMUL_MODE_PROT64 && |
3405 | is_noncanonical_address(desc_ptr.address)) | |
3406 | return emulate_gp(ctxt, 0); | |
5b7f6a1e NA |
3407 | if (lgdt) |
3408 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
3409 | else | |
3410 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
26d05cc7 | 3411 | /* Disable writeback. */ |
9dac77fa | 3412 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3413 | return X86EMUL_CONTINUE; |
3414 | } | |
3415 | ||
5b7f6a1e NA |
3416 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) |
3417 | { | |
3418 | return em_lgdt_lidt(ctxt, true); | |
3419 | } | |
3420 | ||
26d05cc7 AK |
3421 | static int em_lidt(struct x86_emulate_ctxt *ctxt) |
3422 | { | |
5b7f6a1e | 3423 | return em_lgdt_lidt(ctxt, false); |
26d05cc7 AK |
3424 | } |
3425 | ||
3426 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
3427 | { | |
32e94d06 NA |
3428 | if (ctxt->dst.type == OP_MEM) |
3429 | ctxt->dst.bytes = 2; | |
9dac77fa | 3430 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); |
26d05cc7 AK |
3431 | return X86EMUL_CONTINUE; |
3432 | } | |
3433 | ||
3434 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
3435 | { | |
26d05cc7 | 3436 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
3437 | | (ctxt->src.val & 0x0f)); |
3438 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
3439 | return X86EMUL_CONTINUE; |
3440 | } | |
3441 | ||
d06e03ad TY |
3442 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
3443 | { | |
234f3ce4 NA |
3444 | int rc = X86EMUL_CONTINUE; |
3445 | ||
01485a22 | 3446 | register_address_increment(ctxt, VCPU_REGS_RCX, -1); |
dd856efa | 3447 | if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && |
9dac77fa | 3448 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) |
234f3ce4 | 3449 | rc = jmp_rel(ctxt, ctxt->src.val); |
d06e03ad | 3450 | |
234f3ce4 | 3451 | return rc; |
d06e03ad TY |
3452 | } |
3453 | ||
3454 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
3455 | { | |
234f3ce4 NA |
3456 | int rc = X86EMUL_CONTINUE; |
3457 | ||
dd856efa | 3458 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) |
234f3ce4 | 3459 | rc = jmp_rel(ctxt, ctxt->src.val); |
d06e03ad | 3460 | |
234f3ce4 | 3461 | return rc; |
d06e03ad TY |
3462 | } |
3463 | ||
d7841a4b TY |
3464 | static int em_in(struct x86_emulate_ctxt *ctxt) |
3465 | { | |
3466 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
3467 | &ctxt->dst.val)) | |
3468 | return X86EMUL_IO_NEEDED; | |
3469 | ||
3470 | return X86EMUL_CONTINUE; | |
3471 | } | |
3472 | ||
3473 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
3474 | { | |
3475 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
3476 | &ctxt->src.val, 1); | |
3477 | /* Disable writeback. */ | |
3478 | ctxt->dst.type = OP_NONE; | |
3479 | return X86EMUL_CONTINUE; | |
3480 | } | |
3481 | ||
f411e6cd TY |
3482 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
3483 | { | |
3484 | if (emulator_bad_iopl(ctxt)) | |
3485 | return emulate_gp(ctxt, 0); | |
3486 | ||
3487 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
3488 | return X86EMUL_CONTINUE; | |
3489 | } | |
3490 | ||
3491 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
3492 | { | |
3493 | if (emulator_bad_iopl(ctxt)) | |
3494 | return emulate_gp(ctxt, 0); | |
3495 | ||
3496 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
3497 | ctxt->eflags |= X86_EFLAGS_IF; | |
3498 | return X86EMUL_CONTINUE; | |
3499 | } | |
3500 | ||
6d6eede4 AK |
3501 | static int em_cpuid(struct x86_emulate_ctxt *ctxt) |
3502 | { | |
3503 | u32 eax, ebx, ecx, edx; | |
3504 | ||
dd856efa AK |
3505 | eax = reg_read(ctxt, VCPU_REGS_RAX); |
3506 | ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
6d6eede4 | 3507 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
dd856efa AK |
3508 | *reg_write(ctxt, VCPU_REGS_RAX) = eax; |
3509 | *reg_write(ctxt, VCPU_REGS_RBX) = ebx; | |
3510 | *reg_write(ctxt, VCPU_REGS_RCX) = ecx; | |
3511 | *reg_write(ctxt, VCPU_REGS_RDX) = edx; | |
6d6eede4 AK |
3512 | return X86EMUL_CONTINUE; |
3513 | } | |
3514 | ||
98f73630 PB |
3515 | static int em_sahf(struct x86_emulate_ctxt *ctxt) |
3516 | { | |
3517 | u32 flags; | |
3518 | ||
3519 | flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF; | |
3520 | flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; | |
3521 | ||
3522 | ctxt->eflags &= ~0xffUL; | |
3523 | ctxt->eflags |= flags | X86_EFLAGS_FIXED; | |
3524 | return X86EMUL_CONTINUE; | |
3525 | } | |
3526 | ||
2dd7caa0 AK |
3527 | static int em_lahf(struct x86_emulate_ctxt *ctxt) |
3528 | { | |
dd856efa AK |
3529 | *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; |
3530 | *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; | |
2dd7caa0 AK |
3531 | return X86EMUL_CONTINUE; |
3532 | } | |
3533 | ||
9299836e AK |
3534 | static int em_bswap(struct x86_emulate_ctxt *ctxt) |
3535 | { | |
3536 | switch (ctxt->op_bytes) { | |
3537 | #ifdef CONFIG_X86_64 | |
3538 | case 8: | |
3539 | asm("bswap %0" : "+r"(ctxt->dst.val)); | |
3540 | break; | |
3541 | #endif | |
3542 | default: | |
3543 | asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); | |
3544 | break; | |
3545 | } | |
3546 | return X86EMUL_CONTINUE; | |
3547 | } | |
3548 | ||
13e457e0 NA |
3549 | static int em_clflush(struct x86_emulate_ctxt *ctxt) |
3550 | { | |
3551 | /* emulating clflush regardless of cpuid */ | |
3552 | return X86EMUL_CONTINUE; | |
3553 | } | |
3554 | ||
2276b511 NA |
3555 | static int em_movsxd(struct x86_emulate_ctxt *ctxt) |
3556 | { | |
3557 | ctxt->dst.val = (s32) ctxt->src.val; | |
3558 | return X86EMUL_CONTINUE; | |
3559 | } | |
3560 | ||
cfec82cb JR |
3561 | static bool valid_cr(int nr) |
3562 | { | |
3563 | switch (nr) { | |
3564 | case 0: | |
3565 | case 2 ... 4: | |
3566 | case 8: | |
3567 | return true; | |
3568 | default: | |
3569 | return false; | |
3570 | } | |
3571 | } | |
3572 | ||
3573 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3574 | { | |
9dac77fa | 3575 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3576 | return emulate_ud(ctxt); |
3577 | ||
3578 | return X86EMUL_CONTINUE; | |
3579 | } | |
3580 | ||
3581 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3582 | { | |
9dac77fa AK |
3583 | u64 new_val = ctxt->src.val64; |
3584 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3585 | u64 efer = 0; |
cfec82cb JR |
3586 | |
3587 | static u64 cr_reserved_bits[] = { | |
3588 | 0xffffffff00000000ULL, | |
3589 | 0, 0, 0, /* CR3 checked later */ | |
3590 | CR4_RESERVED_BITS, | |
3591 | 0, 0, 0, | |
3592 | CR8_RESERVED_BITS, | |
3593 | }; | |
3594 | ||
3595 | if (!valid_cr(cr)) | |
3596 | return emulate_ud(ctxt); | |
3597 | ||
3598 | if (new_val & cr_reserved_bits[cr]) | |
3599 | return emulate_gp(ctxt, 0); | |
3600 | ||
3601 | switch (cr) { | |
3602 | case 0: { | |
c2ad2bb3 | 3603 | u64 cr4; |
cfec82cb JR |
3604 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3605 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3606 | return emulate_gp(ctxt, 0); | |
3607 | ||
717746e3 AK |
3608 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3609 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3610 | |
3611 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3612 | !(cr4 & X86_CR4_PAE)) | |
3613 | return emulate_gp(ctxt, 0); | |
3614 | ||
3615 | break; | |
3616 | } | |
3617 | case 3: { | |
3618 | u64 rsvd = 0; | |
3619 | ||
c2ad2bb3 AK |
3620 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3621 | if (efer & EFER_LMA) | |
9d88fca7 | 3622 | rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD; |
cfec82cb JR |
3623 | |
3624 | if (new_val & rsvd) | |
3625 | return emulate_gp(ctxt, 0); | |
3626 | ||
3627 | break; | |
3628 | } | |
3629 | case 4: { | |
717746e3 | 3630 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3631 | |
3632 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3633 | return emulate_gp(ctxt, 0); | |
3634 | ||
3635 | break; | |
3636 | } | |
3637 | } | |
3638 | ||
3639 | return X86EMUL_CONTINUE; | |
3640 | } | |
3641 | ||
3b88e41a JR |
3642 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3643 | { | |
3644 | unsigned long dr7; | |
3645 | ||
717746e3 | 3646 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3647 | |
3648 | /* Check if DR7.Global_Enable is set */ | |
3649 | return dr7 & (1 << 13); | |
3650 | } | |
3651 | ||
3652 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3653 | { | |
9dac77fa | 3654 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3655 | u64 cr4; |
3656 | ||
3657 | if (dr > 7) | |
3658 | return emulate_ud(ctxt); | |
3659 | ||
717746e3 | 3660 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3661 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3662 | return emulate_ud(ctxt); | |
3663 | ||
6d2a0526 NA |
3664 | if (check_dr7_gd(ctxt)) { |
3665 | ulong dr6; | |
3666 | ||
3667 | ctxt->ops->get_dr(ctxt, 6, &dr6); | |
3668 | dr6 &= ~15; | |
3669 | dr6 |= DR6_BD | DR6_RTM; | |
3670 | ctxt->ops->set_dr(ctxt, 6, dr6); | |
3b88e41a | 3671 | return emulate_db(ctxt); |
6d2a0526 | 3672 | } |
3b88e41a JR |
3673 | |
3674 | return X86EMUL_CONTINUE; | |
3675 | } | |
3676 | ||
3677 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3678 | { | |
9dac77fa AK |
3679 | u64 new_val = ctxt->src.val64; |
3680 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3681 | |
3682 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3683 | return emulate_gp(ctxt, 0); | |
3684 | ||
3685 | return check_dr_read(ctxt); | |
3686 | } | |
3687 | ||
01de8b09 JR |
3688 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3689 | { | |
3690 | u64 efer; | |
3691 | ||
717746e3 | 3692 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3693 | |
3694 | if (!(efer & EFER_SVME)) | |
3695 | return emulate_ud(ctxt); | |
3696 | ||
3697 | return X86EMUL_CONTINUE; | |
3698 | } | |
3699 | ||
3700 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3701 | { | |
dd856efa | 3702 | u64 rax = reg_read(ctxt, VCPU_REGS_RAX); |
01de8b09 JR |
3703 | |
3704 | /* Valid physical address? */ | |
d4224449 | 3705 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3706 | return emulate_gp(ctxt, 0); |
3707 | ||
3708 | return check_svme(ctxt); | |
3709 | } | |
3710 | ||
d7eb8203 JR |
3711 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3712 | { | |
717746e3 | 3713 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3714 | |
717746e3 | 3715 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3716 | return emulate_ud(ctxt); |
3717 | ||
3718 | return X86EMUL_CONTINUE; | |
3719 | } | |
3720 | ||
8061252e JR |
3721 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3722 | { | |
717746e3 | 3723 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
dd856efa | 3724 | u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); |
8061252e | 3725 | |
717746e3 | 3726 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
67f4d428 | 3727 | ctxt->ops->check_pmc(ctxt, rcx)) |
8061252e JR |
3728 | return emulate_gp(ctxt, 0); |
3729 | ||
3730 | return X86EMUL_CONTINUE; | |
3731 | } | |
3732 | ||
f6511935 JR |
3733 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3734 | { | |
9dac77fa AK |
3735 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3736 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3737 | return emulate_gp(ctxt, 0); |
3738 | ||
3739 | return X86EMUL_CONTINUE; | |
3740 | } | |
3741 | ||
3742 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3743 | { | |
9dac77fa AK |
3744 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3745 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3746 | return emulate_gp(ctxt, 0); |
3747 | ||
3748 | return X86EMUL_CONTINUE; | |
3749 | } | |
3750 | ||
73fba5f4 | 3751 | #define D(_y) { .flags = (_y) } |
d40a6898 PB |
3752 | #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } |
3753 | #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ | |
3754 | .intercept = x86_intercept_##_i, .check_perm = (_p) } | |
0b789eee | 3755 | #define N D(NotImpl) |
01de8b09 | 3756 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
1c2545be TY |
3757 | #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
3758 | #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } | |
39f062ff | 3759 | #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } |
2276b511 | 3760 | #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } |
045a282c | 3761 | #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } |
73fba5f4 | 3762 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
e28bbd44 | 3763 | #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } |
c4f035c6 | 3764 | #define II(_f, _e, _i) \ |
d40a6898 | 3765 | { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } |
d09beabd | 3766 | #define IIP(_f, _e, _i, _p) \ |
d40a6898 PB |
3767 | { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ |
3768 | .intercept = x86_intercept_##_i, .check_perm = (_p) } | |
aa97bb48 | 3769 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3770 | |
8d8f4e9f | 3771 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3772 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3773 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
f7857f35 | 3774 | #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) |
d7841a4b TY |
3775 | #define I2bvIP(_f, _e, _i, _p) \ |
3776 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3777 | |
fb864fbc AK |
3778 | #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3779 | F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3780 | F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3781 | |
0f54a321 NA |
3782 | static const struct opcode group7_rm0[] = { |
3783 | N, | |
b34a8051 | 3784 | I(SrcNone | Priv | EmulateOnUD, em_hypercall), |
0f54a321 NA |
3785 | N, N, N, N, N, N, |
3786 | }; | |
3787 | ||
fd0a0d82 | 3788 | static const struct opcode group7_rm1[] = { |
1c2545be TY |
3789 | DI(SrcNone | Priv, monitor), |
3790 | DI(SrcNone | Priv, mwait), | |
d7eb8203 JR |
3791 | N, N, N, N, N, N, |
3792 | }; | |
3793 | ||
fd0a0d82 | 3794 | static const struct opcode group7_rm3[] = { |
1c2545be | 3795 | DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), |
b34a8051 | 3796 | II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), |
1c2545be TY |
3797 | DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), |
3798 | DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), | |
3799 | DIP(SrcNone | Prot | Priv, stgi, check_svme), | |
3800 | DIP(SrcNone | Prot | Priv, clgi, check_svme), | |
3801 | DIP(SrcNone | Prot | Priv, skinit, check_svme), | |
3802 | DIP(SrcNone | Prot | Priv, invlpga, check_svme), | |
01de8b09 | 3803 | }; |
6230f7fc | 3804 | |
fd0a0d82 | 3805 | static const struct opcode group7_rm7[] = { |
d7eb8203 | 3806 | N, |
1c2545be | 3807 | DIP(SrcNone, rdtscp, check_rdtsc), |
d7eb8203 JR |
3808 | N, N, N, N, N, N, |
3809 | }; | |
d67fc27a | 3810 | |
fd0a0d82 | 3811 | static const struct opcode group1[] = { |
fb864fbc AK |
3812 | F(Lock, em_add), |
3813 | F(Lock | PageTable, em_or), | |
3814 | F(Lock, em_adc), | |
3815 | F(Lock, em_sbb), | |
3816 | F(Lock | PageTable, em_and), | |
3817 | F(Lock, em_sub), | |
3818 | F(Lock, em_xor), | |
3819 | F(NoWrite, em_cmp), | |
73fba5f4 AK |
3820 | }; |
3821 | ||
fd0a0d82 | 3822 | static const struct opcode group1A[] = { |
ab708099 | 3823 | I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3824 | }; |
3825 | ||
007a3b54 AK |
3826 | static const struct opcode group2[] = { |
3827 | F(DstMem | ModRM, em_rol), | |
3828 | F(DstMem | ModRM, em_ror), | |
3829 | F(DstMem | ModRM, em_rcl), | |
3830 | F(DstMem | ModRM, em_rcr), | |
3831 | F(DstMem | ModRM, em_shl), | |
3832 | F(DstMem | ModRM, em_shr), | |
3833 | F(DstMem | ModRM, em_shl), | |
3834 | F(DstMem | ModRM, em_sar), | |
3835 | }; | |
3836 | ||
fd0a0d82 | 3837 | static const struct opcode group3[] = { |
fb864fbc AK |
3838 | F(DstMem | SrcImm | NoWrite, em_test), |
3839 | F(DstMem | SrcImm | NoWrite, em_test), | |
45a1467d AK |
3840 | F(DstMem | SrcNone | Lock, em_not), |
3841 | F(DstMem | SrcNone | Lock, em_neg), | |
b9fa409b AK |
3842 | F(DstXacc | Src2Mem, em_mul_ex), |
3843 | F(DstXacc | Src2Mem, em_imul_ex), | |
b8c0b6ae AK |
3844 | F(DstXacc | Src2Mem, em_div_ex), |
3845 | F(DstXacc | Src2Mem, em_idiv_ex), | |
73fba5f4 AK |
3846 | }; |
3847 | ||
fd0a0d82 | 3848 | static const struct opcode group4[] = { |
95413dc4 AK |
3849 | F(ByteOp | DstMem | SrcNone | Lock, em_inc), |
3850 | F(ByteOp | DstMem | SrcNone | Lock, em_dec), | |
73fba5f4 AK |
3851 | N, N, N, N, N, N, |
3852 | }; | |
3853 | ||
fd0a0d82 | 3854 | static const struct opcode group5[] = { |
95413dc4 AK |
3855 | F(DstMem | SrcNone | Lock, em_inc), |
3856 | F(DstMem | SrcNone | Lock, em_dec), | |
58b7075d | 3857 | I(SrcMem | NearBranch, em_call_near_abs), |
1c2545be | 3858 | I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), |
58b7075d | 3859 | I(SrcMem | NearBranch, em_jmp_abs), |
f7784046 NA |
3860 | I(SrcMemFAddr | ImplicitOps, em_jmp_far), |
3861 | I(SrcMem | Stack, em_push), D(Undefined), | |
73fba5f4 AK |
3862 | }; |
3863 | ||
fd0a0d82 | 3864 | static const struct opcode group6[] = { |
63ea0a49 NA |
3865 | DI(Prot | DstMem, sldt), |
3866 | DI(Prot | DstMem, str), | |
a14e579f | 3867 | II(Prot | Priv | SrcMem16, em_lldt, lldt), |
80890006 | 3868 | II(Prot | Priv | SrcMem16, em_ltr, ltr), |
dee6bb70 JR |
3869 | N, N, N, N, |
3870 | }; | |
3871 | ||
fd0a0d82 | 3872 | static const struct group_dual group7 = { { |
606b1c3e NA |
3873 | II(Mov | DstMem, em_sgdt, sgdt), |
3874 | II(Mov | DstMem, em_sidt, sidt), | |
1c2545be TY |
3875 | II(SrcMem | Priv, em_lgdt, lgdt), |
3876 | II(SrcMem | Priv, em_lidt, lidt), | |
3877 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, | |
3878 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3879 | II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3880 | }, { |
0f54a321 | 3881 | EXT(0, group7_rm0), |
5ef39c71 | 3882 | EXT(0, group7_rm1), |
01de8b09 | 3883 | N, EXT(0, group7_rm3), |
1c2545be TY |
3884 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
3885 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3886 | EXT(0, group7_rm7), | |
73fba5f4 AK |
3887 | } }; |
3888 | ||
fd0a0d82 | 3889 | static const struct opcode group8[] = { |
73fba5f4 | 3890 | N, N, N, N, |
11c363ba AK |
3891 | F(DstMem | SrcImmByte | NoWrite, em_bt), |
3892 | F(DstMem | SrcImmByte | Lock | PageTable, em_bts), | |
3893 | F(DstMem | SrcImmByte | Lock, em_btr), | |
3894 | F(DstMem | SrcImmByte | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3895 | }; |
3896 | ||
fd0a0d82 | 3897 | static const struct group_dual group9 = { { |
1c2545be | 3898 | N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3899 | }, { |
3900 | N, N, N, N, N, N, N, N, | |
3901 | } }; | |
3902 | ||
fd0a0d82 | 3903 | static const struct opcode group11[] = { |
1c2545be | 3904 | I(DstMem | SrcImm | Mov | PageTable, em_mov), |
d5ae7ce8 | 3905 | X7(D(Undefined)), |
a4d4a7c1 AK |
3906 | }; |
3907 | ||
13e457e0 | 3908 | static const struct gprefix pfx_0f_ae_7 = { |
3f6f1480 | 3909 | I(SrcMem | ByteOp, em_clflush), N, N, N, |
13e457e0 NA |
3910 | }; |
3911 | ||
3912 | static const struct group_dual group15 = { { | |
3913 | N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7), | |
3914 | }, { | |
3915 | N, N, N, N, N, N, N, N, | |
3916 | } }; | |
3917 | ||
fd0a0d82 | 3918 | static const struct gprefix pfx_0f_6f_0f_7f = { |
e5971755 | 3919 | I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
aa97bb48 AK |
3920 | }; |
3921 | ||
39f062ff NA |
3922 | static const struct instr_dual instr_dual_0f_2b = { |
3923 | I(0, em_mov), N | |
3924 | }; | |
3925 | ||
d5b77069 | 3926 | static const struct gprefix pfx_0f_2b = { |
39f062ff | 3927 | ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, |
3e114eb4 AK |
3928 | }; |
3929 | ||
27ce8258 | 3930 | static const struct gprefix pfx_0f_28_0f_29 = { |
6fec27d8 | 3931 | I(Aligned, em_mov), I(Aligned, em_mov), N, N, |
27ce8258 IM |
3932 | }; |
3933 | ||
0a37027e AW |
3934 | static const struct gprefix pfx_0f_e7 = { |
3935 | N, I(Sse, em_mov), N, N, | |
3936 | }; | |
3937 | ||
045a282c | 3938 | static const struct escape escape_d9 = { { |
16bebefe | 3939 | N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), |
045a282c GN |
3940 | }, { |
3941 | /* 0xC0 - 0xC7 */ | |
3942 | N, N, N, N, N, N, N, N, | |
3943 | /* 0xC8 - 0xCF */ | |
3944 | N, N, N, N, N, N, N, N, | |
3945 | /* 0xD0 - 0xC7 */ | |
3946 | N, N, N, N, N, N, N, N, | |
3947 | /* 0xD8 - 0xDF */ | |
3948 | N, N, N, N, N, N, N, N, | |
3949 | /* 0xE0 - 0xE7 */ | |
3950 | N, N, N, N, N, N, N, N, | |
3951 | /* 0xE8 - 0xEF */ | |
3952 | N, N, N, N, N, N, N, N, | |
3953 | /* 0xF0 - 0xF7 */ | |
3954 | N, N, N, N, N, N, N, N, | |
3955 | /* 0xF8 - 0xFF */ | |
3956 | N, N, N, N, N, N, N, N, | |
3957 | } }; | |
3958 | ||
3959 | static const struct escape escape_db = { { | |
3960 | N, N, N, N, N, N, N, N, | |
3961 | }, { | |
3962 | /* 0xC0 - 0xC7 */ | |
3963 | N, N, N, N, N, N, N, N, | |
3964 | /* 0xC8 - 0xCF */ | |
3965 | N, N, N, N, N, N, N, N, | |
3966 | /* 0xD0 - 0xC7 */ | |
3967 | N, N, N, N, N, N, N, N, | |
3968 | /* 0xD8 - 0xDF */ | |
3969 | N, N, N, N, N, N, N, N, | |
3970 | /* 0xE0 - 0xE7 */ | |
3971 | N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, | |
3972 | /* 0xE8 - 0xEF */ | |
3973 | N, N, N, N, N, N, N, N, | |
3974 | /* 0xF0 - 0xF7 */ | |
3975 | N, N, N, N, N, N, N, N, | |
3976 | /* 0xF8 - 0xFF */ | |
3977 | N, N, N, N, N, N, N, N, | |
3978 | } }; | |
3979 | ||
3980 | static const struct escape escape_dd = { { | |
16bebefe | 3981 | N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), |
045a282c GN |
3982 | }, { |
3983 | /* 0xC0 - 0xC7 */ | |
3984 | N, N, N, N, N, N, N, N, | |
3985 | /* 0xC8 - 0xCF */ | |
3986 | N, N, N, N, N, N, N, N, | |
3987 | /* 0xD0 - 0xC7 */ | |
3988 | N, N, N, N, N, N, N, N, | |
3989 | /* 0xD8 - 0xDF */ | |
3990 | N, N, N, N, N, N, N, N, | |
3991 | /* 0xE0 - 0xE7 */ | |
3992 | N, N, N, N, N, N, N, N, | |
3993 | /* 0xE8 - 0xEF */ | |
3994 | N, N, N, N, N, N, N, N, | |
3995 | /* 0xF0 - 0xF7 */ | |
3996 | N, N, N, N, N, N, N, N, | |
3997 | /* 0xF8 - 0xFF */ | |
3998 | N, N, N, N, N, N, N, N, | |
3999 | } }; | |
4000 | ||
39f062ff NA |
4001 | static const struct instr_dual instr_dual_0f_c3 = { |
4002 | I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N | |
4003 | }; | |
4004 | ||
2276b511 NA |
4005 | static const struct mode_dual mode_dual_63 = { |
4006 | N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) | |
4007 | }; | |
4008 | ||
fd0a0d82 | 4009 | static const struct opcode opcode_table[256] = { |
73fba5f4 | 4010 | /* 0x00 - 0x07 */ |
fb864fbc | 4011 | F6ALU(Lock, em_add), |
1cd196ea AK |
4012 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
4013 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 4014 | /* 0x08 - 0x0F */ |
fb864fbc | 4015 | F6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
4016 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
4017 | N, | |
73fba5f4 | 4018 | /* 0x10 - 0x17 */ |
fb864fbc | 4019 | F6ALU(Lock, em_adc), |
1cd196ea AK |
4020 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
4021 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 4022 | /* 0x18 - 0x1F */ |
fb864fbc | 4023 | F6ALU(Lock, em_sbb), |
1cd196ea AK |
4024 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
4025 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 4026 | /* 0x20 - 0x27 */ |
fb864fbc | 4027 | F6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 4028 | /* 0x28 - 0x2F */ |
fb864fbc | 4029 | F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 4030 | /* 0x30 - 0x37 */ |
fb864fbc | 4031 | F6ALU(Lock, em_xor), N, N, |
73fba5f4 | 4032 | /* 0x38 - 0x3F */ |
fb864fbc | 4033 | F6ALU(NoWrite, em_cmp), N, N, |
73fba5f4 | 4034 | /* 0x40 - 0x4F */ |
95413dc4 | 4035 | X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), |
73fba5f4 | 4036 | /* 0x50 - 0x57 */ |
63540382 | 4037 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 4038 | /* 0x58 - 0x5F */ |
c54fe504 | 4039 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 4040 | /* 0x60 - 0x67 */ |
b96a7fad TY |
4041 | I(ImplicitOps | Stack | No64, em_pusha), |
4042 | I(ImplicitOps | Stack | No64, em_popa), | |
2276b511 | 4043 | N, MD(ModRM, &mode_dual_63), |
73fba5f4 AK |
4044 | N, N, N, N, |
4045 | /* 0x68 - 0x6F */ | |
d46164db AK |
4046 | I(SrcImm | Mov | Stack, em_push), |
4047 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
4048 | I(SrcImmByte | Mov | Stack, em_push), |
4049 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
b3356bf0 | 4050 | I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ |
2b5e97e1 | 4051 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ |
73fba5f4 | 4052 | /* 0x70 - 0x7F */ |
58b7075d | 4053 | X16(D(SrcImmByte | NearBranch)), |
73fba5f4 | 4054 | /* 0x80 - 0x87 */ |
1c2545be TY |
4055 | G(ByteOp | DstMem | SrcImm, group1), |
4056 | G(DstMem | SrcImm, group1), | |
4057 | G(ByteOp | DstMem | SrcImm | No64, group1), | |
4058 | G(DstMem | SrcImmByte, group1), | |
fb864fbc | 4059 | F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), |
d5ae7ce8 | 4060 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 4061 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 4062 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 4063 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 4064 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
4065 | D(ModRM | SrcMem | NoAccess | DstReg), |
4066 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
4067 | G(0, group1A), | |
73fba5f4 | 4068 | /* 0x90 - 0x97 */ |
bf608f88 | 4069 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 4070 | /* 0x98 - 0x9F */ |
61429142 | 4071 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 4072 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 | 4073 | II(ImplicitOps | Stack, em_pushf, pushf), |
98f73630 PB |
4074 | II(ImplicitOps | Stack, em_popf, popf), |
4075 | I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), | |
73fba5f4 | 4076 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 4077 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 4078 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 4079 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
5aca3722 | 4080 | F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r), |
73fba5f4 | 4081 | /* 0xA8 - 0xAF */ |
fb864fbc | 4082 | F2bv(DstAcc | SrcImm | NoWrite, em_test), |
b9eac5f4 AK |
4083 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
4084 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
5aca3722 | 4085 | F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), |
73fba5f4 | 4086 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 4087 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 4088 | /* 0xB8 - 0xBF */ |
5e2c6883 | 4089 | X8(I(DstReg | SrcImm64 | Mov, em_mov)), |
73fba5f4 | 4090 | /* 0xC0 - 0xC7 */ |
007a3b54 | 4091 | G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), |
58b7075d NA |
4092 | I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), |
4093 | I(ImplicitOps | NearBranch, em_ret), | |
d4b4325f AK |
4094 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
4095 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 4096 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 4097 | /* 0xC8 - 0xCF */ |
612e89f0 | 4098 | I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), |
16794aaa NA |
4099 | I(ImplicitOps | SrcImmU16, em_ret_far_imm), |
4100 | I(ImplicitOps, em_ret_far), | |
3c6e276f | 4101 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 4102 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 4103 | /* 0xD0 - 0xD7 */ |
007a3b54 AK |
4104 | G(Src2One | ByteOp, group2), G(Src2One, group2), |
4105 | G(Src2CL | ByteOp, group2), G(Src2CL, group2), | |
a035d5c6 | 4106 | I(DstAcc | SrcImmUByte | No64, em_aam), |
326f578f PB |
4107 | I(DstAcc | SrcImmUByte | No64, em_aad), |
4108 | F(DstAcc | ByteOp | No64, em_salc), | |
7fa57952 | 4109 | I(DstAcc | SrcXLat | ByteOp, em_mov), |
73fba5f4 | 4110 | /* 0xD8 - 0xDF */ |
045a282c | 4111 | N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, |
73fba5f4 | 4112 | /* 0xE0 - 0xE7 */ |
58b7075d NA |
4113 | X3(I(SrcImmByte | NearBranch, em_loop)), |
4114 | I(SrcImmByte | NearBranch, em_jcxz), | |
d7841a4b TY |
4115 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
4116 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 4117 | /* 0xE8 - 0xEF */ |
58b7075d NA |
4118 | I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), |
4119 | I(SrcImmFAddr | No64, em_jmp_far), | |
4120 | D(SrcImmByte | ImplicitOps | NearBranch), | |
d7841a4b TY |
4121 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
4122 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 4123 | /* 0xF0 - 0xF7 */ |
bf608f88 | 4124 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
4125 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
4126 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 4127 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
4128 | D(ImplicitOps), D(ImplicitOps), |
4129 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
4130 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
4131 | }; | |
4132 | ||
fd0a0d82 | 4133 | static const struct opcode twobyte_table[256] = { |
73fba5f4 | 4134 | /* 0x00 - 0x0F */ |
dee6bb70 | 4135 | G(0, group6), GD(0, &group7), N, N, |
b51e974f | 4136 | N, I(ImplicitOps | EmulateOnUD, em_syscall), |
db5b0762 | 4137 | II(ImplicitOps | Priv, em_clts, clts), N, |
3c6e276f | 4138 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
3f6f1480 | 4139 | N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, |
73fba5f4 | 4140 | /* 0x10 - 0x1F */ |
103f98ea | 4141 | N, N, N, N, N, N, N, N, |
3f6f1480 NA |
4142 | D(ImplicitOps | ModRM | SrcMem | NoAccess), |
4143 | N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), | |
73fba5f4 | 4144 | /* 0x20 - 0x2F */ |
9b88ae99 NA |
4145 | DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), |
4146 | DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), | |
4147 | IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, | |
4148 | check_cr_write), | |
4149 | IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, | |
4150 | check_dr_write), | |
73fba5f4 | 4151 | N, N, N, N, |
27ce8258 IM |
4152 | GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), |
4153 | GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), | |
d5b77069 | 4154 | N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), |
3e114eb4 | 4155 | N, N, N, N, |
73fba5f4 | 4156 | /* 0x30 - 0x3F */ |
e1e210b0 | 4157 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 4158 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 4159 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 4160 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
b51e974f BP |
4161 | I(ImplicitOps | EmulateOnUD, em_sysenter), |
4162 | I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), | |
d867162c | 4163 | N, N, |
73fba5f4 AK |
4164 | N, N, N, N, N, N, N, N, |
4165 | /* 0x40 - 0x4F */ | |
140bad89 | 4166 | X16(D(DstReg | SrcMem | ModRM)), |
73fba5f4 AK |
4167 | /* 0x50 - 0x5F */ |
4168 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
4169 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
4170 | N, N, N, N, |
4171 | N, N, N, N, | |
4172 | N, N, N, N, | |
4173 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 4174 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
4175 | N, N, N, N, |
4176 | N, N, N, N, | |
4177 | N, N, N, N, | |
4178 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 4179 | /* 0x80 - 0x8F */ |
58b7075d | 4180 | X16(D(SrcImm | NearBranch)), |
73fba5f4 | 4181 | /* 0x90 - 0x9F */ |
ee45b58e | 4182 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 4183 | /* 0xA0 - 0xA7 */ |
1cd196ea | 4184 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
11c363ba AK |
4185 | II(ImplicitOps, em_cpuid, cpuid), |
4186 | F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), | |
0bdea068 AK |
4187 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), |
4188 | F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, | |
73fba5f4 | 4189 | /* 0xA8 - 0xAF */ |
1cd196ea | 4190 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 4191 | DI(ImplicitOps, rsm), |
11c363ba | 4192 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
0bdea068 AK |
4193 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), |
4194 | F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), | |
13e457e0 | 4195 | GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 4196 | /* 0xB0 - 0xB7 */ |
2fcf5c8a | 4197 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), |
d4b4325f | 4198 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
11c363ba | 4199 | F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
4200 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
4201 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 4202 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
4203 | /* 0xB8 - 0xBF */ |
4204 | N, N, | |
ce7faab2 | 4205 | G(BitOp, group8), |
11c363ba | 4206 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), |
900efe20 NA |
4207 | I(DstReg | SrcMem | ModRM, em_bsf_c), |
4208 | I(DstReg | SrcMem | ModRM, em_bsr_c), | |
2adb5ad9 | 4209 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
9299836e | 4210 | /* 0xC0 - 0xC7 */ |
e47a5f5f | 4211 | F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), |
39f062ff | 4212 | N, ID(0, &instr_dual_0f_c3), |
73fba5f4 | 4213 | N, N, N, GD(0, &group9), |
9299836e AK |
4214 | /* 0xC8 - 0xCF */ |
4215 | X8(I(DstReg, em_bswap)), | |
73fba5f4 AK |
4216 | /* 0xD0 - 0xDF */ |
4217 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
4218 | /* 0xE0 - 0xEF */ | |
0a37027e AW |
4219 | N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), |
4220 | N, N, N, N, N, N, N, N, | |
73fba5f4 AK |
4221 | /* 0xF0 - 0xFF */ |
4222 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
4223 | }; | |
4224 | ||
39f062ff NA |
4225 | static const struct instr_dual instr_dual_0f_38_f0 = { |
4226 | I(DstReg | SrcMem | Mov, em_movbe), N | |
4227 | }; | |
4228 | ||
4229 | static const struct instr_dual instr_dual_0f_38_f1 = { | |
4230 | I(DstMem | SrcReg | Mov, em_movbe), N | |
4231 | }; | |
4232 | ||
0bc5eedb | 4233 | static const struct gprefix three_byte_0f_38_f0 = { |
39f062ff | 4234 | ID(0, &instr_dual_0f_38_f0), N, N, N |
0bc5eedb BP |
4235 | }; |
4236 | ||
4237 | static const struct gprefix three_byte_0f_38_f1 = { | |
39f062ff | 4238 | ID(0, &instr_dual_0f_38_f1), N, N, N |
0bc5eedb BP |
4239 | }; |
4240 | ||
4241 | /* | |
4242 | * Insns below are selected by the prefix which indexed by the third opcode | |
4243 | * byte. | |
4244 | */ | |
4245 | static const struct opcode opcode_map_0f_38[256] = { | |
4246 | /* 0x00 - 0x7f */ | |
4247 | X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), | |
84cffe49 BP |
4248 | /* 0x80 - 0xef */ |
4249 | X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), | |
4250 | /* 0xf0 - 0xf1 */ | |
53bb4f78 NA |
4251 | GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), |
4252 | GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), | |
84cffe49 BP |
4253 | /* 0xf2 - 0xff */ |
4254 | N, N, X4(N), X8(N) | |
0bc5eedb BP |
4255 | }; |
4256 | ||
73fba5f4 AK |
4257 | #undef D |
4258 | #undef N | |
4259 | #undef G | |
4260 | #undef GD | |
4261 | #undef I | |
aa97bb48 | 4262 | #undef GP |
01de8b09 | 4263 | #undef EXT |
2276b511 | 4264 | #undef MD |
2b42fce6 | 4265 | #undef ID |
73fba5f4 | 4266 | |
8d8f4e9f | 4267 | #undef D2bv |
f6511935 | 4268 | #undef D2bvIP |
8d8f4e9f | 4269 | #undef I2bv |
d7841a4b | 4270 | #undef I2bvIP |
d67fc27a | 4271 | #undef I6ALU |
8d8f4e9f | 4272 | |
9dac77fa | 4273 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
4274 | { |
4275 | unsigned size; | |
4276 | ||
9dac77fa | 4277 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
4278 | if (size == 8) |
4279 | size = 4; | |
4280 | return size; | |
4281 | } | |
4282 | ||
4283 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
4284 | unsigned size, bool sign_extension) | |
4285 | { | |
39f21ee5 AK |
4286 | int rc = X86EMUL_CONTINUE; |
4287 | ||
4288 | op->type = OP_IMM; | |
4289 | op->bytes = size; | |
9dac77fa | 4290 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
4291 | /* NB. Immediates are sign-extended as necessary. */ |
4292 | switch (op->bytes) { | |
4293 | case 1: | |
e85a1085 | 4294 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
4295 | break; |
4296 | case 2: | |
e85a1085 | 4297 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
4298 | break; |
4299 | case 4: | |
e85a1085 | 4300 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 | 4301 | break; |
5e2c6883 NA |
4302 | case 8: |
4303 | op->val = insn_fetch(s64, ctxt); | |
4304 | break; | |
39f21ee5 AK |
4305 | } |
4306 | if (!sign_extension) { | |
4307 | switch (op->bytes) { | |
4308 | case 1: | |
4309 | op->val &= 0xff; | |
4310 | break; | |
4311 | case 2: | |
4312 | op->val &= 0xffff; | |
4313 | break; | |
4314 | case 4: | |
4315 | op->val &= 0xffffffff; | |
4316 | break; | |
4317 | } | |
4318 | } | |
4319 | done: | |
4320 | return rc; | |
4321 | } | |
4322 | ||
a9945549 AK |
4323 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
4324 | unsigned d) | |
4325 | { | |
4326 | int rc = X86EMUL_CONTINUE; | |
4327 | ||
4328 | switch (d) { | |
4329 | case OpReg: | |
2adb5ad9 | 4330 | decode_register_operand(ctxt, op); |
a9945549 AK |
4331 | break; |
4332 | case OpImmUByte: | |
608aabe3 | 4333 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
4334 | break; |
4335 | case OpMem: | |
41ddf978 | 4336 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
4337 | mem_common: |
4338 | *op = ctxt->memop; | |
4339 | ctxt->memopp = op; | |
96888977 | 4340 | if (ctxt->d & BitOp) |
a9945549 AK |
4341 | fetch_bit_operand(ctxt); |
4342 | op->orig_val = op->val; | |
4343 | break; | |
41ddf978 | 4344 | case OpMem64: |
aaa05f24 | 4345 | ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; |
41ddf978 | 4346 | goto mem_common; |
a9945549 AK |
4347 | case OpAcc: |
4348 | op->type = OP_REG; | |
4349 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
dd856efa | 4350 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
a9945549 AK |
4351 | fetch_register_operand(op); |
4352 | op->orig_val = op->val; | |
4353 | break; | |
820207c8 AK |
4354 | case OpAccLo: |
4355 | op->type = OP_REG; | |
4356 | op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; | |
4357 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); | |
4358 | fetch_register_operand(op); | |
4359 | op->orig_val = op->val; | |
4360 | break; | |
4361 | case OpAccHi: | |
4362 | if (ctxt->d & ByteOp) { | |
4363 | op->type = OP_NONE; | |
4364 | break; | |
4365 | } | |
4366 | op->type = OP_REG; | |
4367 | op->bytes = ctxt->op_bytes; | |
4368 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); | |
4369 | fetch_register_operand(op); | |
4370 | op->orig_val = op->val; | |
4371 | break; | |
a9945549 AK |
4372 | case OpDI: |
4373 | op->type = OP_MEM; | |
4374 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4375 | op->addr.mem.ea = | |
01485a22 | 4376 | register_address(ctxt, VCPU_REGS_RDI); |
a9945549 AK |
4377 | op->addr.mem.seg = VCPU_SREG_ES; |
4378 | op->val = 0; | |
b3356bf0 | 4379 | op->count = 1; |
a9945549 AK |
4380 | break; |
4381 | case OpDX: | |
4382 | op->type = OP_REG; | |
4383 | op->bytes = 2; | |
dd856efa | 4384 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
a9945549 AK |
4385 | fetch_register_operand(op); |
4386 | break; | |
4dd6a57d | 4387 | case OpCL: |
d29b9d7e | 4388 | op->type = OP_IMM; |
4dd6a57d | 4389 | op->bytes = 1; |
dd856efa | 4390 | op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; |
4dd6a57d AK |
4391 | break; |
4392 | case OpImmByte: | |
4393 | rc = decode_imm(ctxt, op, 1, true); | |
4394 | break; | |
4395 | case OpOne: | |
d29b9d7e | 4396 | op->type = OP_IMM; |
4dd6a57d AK |
4397 | op->bytes = 1; |
4398 | op->val = 1; | |
4399 | break; | |
4400 | case OpImm: | |
4401 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
4402 | break; | |
5e2c6883 NA |
4403 | case OpImm64: |
4404 | rc = decode_imm(ctxt, op, ctxt->op_bytes, true); | |
4405 | break; | |
28867cee AK |
4406 | case OpMem8: |
4407 | ctxt->memop.bytes = 1; | |
660696d1 | 4408 | if (ctxt->memop.type == OP_REG) { |
aa9ac1a6 GN |
4409 | ctxt->memop.addr.reg = decode_register(ctxt, |
4410 | ctxt->modrm_rm, true); | |
660696d1 GN |
4411 | fetch_register_operand(&ctxt->memop); |
4412 | } | |
28867cee | 4413 | goto mem_common; |
0fe59128 AK |
4414 | case OpMem16: |
4415 | ctxt->memop.bytes = 2; | |
4416 | goto mem_common; | |
4417 | case OpMem32: | |
4418 | ctxt->memop.bytes = 4; | |
4419 | goto mem_common; | |
4420 | case OpImmU16: | |
4421 | rc = decode_imm(ctxt, op, 2, false); | |
4422 | break; | |
4423 | case OpImmU: | |
4424 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
4425 | break; | |
4426 | case OpSI: | |
4427 | op->type = OP_MEM; | |
4428 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4429 | op->addr.mem.ea = | |
01485a22 | 4430 | register_address(ctxt, VCPU_REGS_RSI); |
573e80fe | 4431 | op->addr.mem.seg = ctxt->seg_override; |
0fe59128 | 4432 | op->val = 0; |
b3356bf0 | 4433 | op->count = 1; |
0fe59128 | 4434 | break; |
7fa57952 PB |
4435 | case OpXLat: |
4436 | op->type = OP_MEM; | |
4437 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4438 | op->addr.mem.ea = | |
01485a22 | 4439 | address_mask(ctxt, |
7fa57952 PB |
4440 | reg_read(ctxt, VCPU_REGS_RBX) + |
4441 | (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); | |
573e80fe | 4442 | op->addr.mem.seg = ctxt->seg_override; |
7fa57952 PB |
4443 | op->val = 0; |
4444 | break; | |
0fe59128 AK |
4445 | case OpImmFAddr: |
4446 | op->type = OP_IMM; | |
4447 | op->addr.mem.ea = ctxt->_eip; | |
4448 | op->bytes = ctxt->op_bytes + 2; | |
4449 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
4450 | break; | |
4451 | case OpMemFAddr: | |
4452 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
4453 | goto mem_common; | |
c191a7a0 | 4454 | case OpES: |
d29b9d7e | 4455 | op->type = OP_IMM; |
c191a7a0 AK |
4456 | op->val = VCPU_SREG_ES; |
4457 | break; | |
4458 | case OpCS: | |
d29b9d7e | 4459 | op->type = OP_IMM; |
c191a7a0 AK |
4460 | op->val = VCPU_SREG_CS; |
4461 | break; | |
4462 | case OpSS: | |
d29b9d7e | 4463 | op->type = OP_IMM; |
c191a7a0 AK |
4464 | op->val = VCPU_SREG_SS; |
4465 | break; | |
4466 | case OpDS: | |
d29b9d7e | 4467 | op->type = OP_IMM; |
c191a7a0 AK |
4468 | op->val = VCPU_SREG_DS; |
4469 | break; | |
4470 | case OpFS: | |
d29b9d7e | 4471 | op->type = OP_IMM; |
c191a7a0 AK |
4472 | op->val = VCPU_SREG_FS; |
4473 | break; | |
4474 | case OpGS: | |
d29b9d7e | 4475 | op->type = OP_IMM; |
c191a7a0 AK |
4476 | op->val = VCPU_SREG_GS; |
4477 | break; | |
a9945549 AK |
4478 | case OpImplicit: |
4479 | /* Special instructions do their own operand decoding. */ | |
4480 | default: | |
4481 | op->type = OP_NONE; /* Disable writeback. */ | |
4482 | break; | |
4483 | } | |
4484 | ||
4485 | done: | |
4486 | return rc; | |
4487 | } | |
4488 | ||
ef5d75cc | 4489 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 4490 | { |
dde7e6d1 AK |
4491 | int rc = X86EMUL_CONTINUE; |
4492 | int mode = ctxt->mode; | |
46561646 | 4493 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 4494 | bool op_prefix = false; |
573e80fe | 4495 | bool has_seg_override = false; |
46561646 | 4496 | struct opcode opcode; |
dde7e6d1 | 4497 | |
f09ed83e AK |
4498 | ctxt->memop.type = OP_NONE; |
4499 | ctxt->memopp = NULL; | |
9dac77fa | 4500 | ctxt->_eip = ctxt->eip; |
17052f16 PB |
4501 | ctxt->fetch.ptr = ctxt->fetch.data; |
4502 | ctxt->fetch.end = ctxt->fetch.data + insn_len; | |
1ce19dc1 | 4503 | ctxt->opcode_len = 1; |
dc25e89e | 4504 | if (insn_len > 0) |
9dac77fa | 4505 | memcpy(ctxt->fetch.data, insn, insn_len); |
285ca9e9 | 4506 | else { |
9506d57d | 4507 | rc = __do_insn_fetch_bytes(ctxt, 1); |
285ca9e9 PB |
4508 | if (rc != X86EMUL_CONTINUE) |
4509 | return rc; | |
4510 | } | |
dde7e6d1 AK |
4511 | |
4512 | switch (mode) { | |
4513 | case X86EMUL_MODE_REAL: | |
4514 | case X86EMUL_MODE_VM86: | |
4515 | case X86EMUL_MODE_PROT16: | |
4516 | def_op_bytes = def_ad_bytes = 2; | |
4517 | break; | |
4518 | case X86EMUL_MODE_PROT32: | |
4519 | def_op_bytes = def_ad_bytes = 4; | |
4520 | break; | |
4521 | #ifdef CONFIG_X86_64 | |
4522 | case X86EMUL_MODE_PROT64: | |
4523 | def_op_bytes = 4; | |
4524 | def_ad_bytes = 8; | |
4525 | break; | |
4526 | #endif | |
4527 | default: | |
1d2887e2 | 4528 | return EMULATION_FAILED; |
dde7e6d1 AK |
4529 | } |
4530 | ||
9dac77fa AK |
4531 | ctxt->op_bytes = def_op_bytes; |
4532 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
4533 | |
4534 | /* Legacy prefixes. */ | |
4535 | for (;;) { | |
e85a1085 | 4536 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 4537 | case 0x66: /* operand-size override */ |
0d7cdee8 | 4538 | op_prefix = true; |
dde7e6d1 | 4539 | /* switch between 2/4 bytes */ |
9dac77fa | 4540 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
4541 | break; |
4542 | case 0x67: /* address-size override */ | |
4543 | if (mode == X86EMUL_MODE_PROT64) | |
4544 | /* switch between 4/8 bytes */ | |
9dac77fa | 4545 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
4546 | else |
4547 | /* switch between 2/4 bytes */ | |
9dac77fa | 4548 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
4549 | break; |
4550 | case 0x26: /* ES override */ | |
4551 | case 0x2e: /* CS override */ | |
4552 | case 0x36: /* SS override */ | |
4553 | case 0x3e: /* DS override */ | |
573e80fe BD |
4554 | has_seg_override = true; |
4555 | ctxt->seg_override = (ctxt->b >> 3) & 3; | |
dde7e6d1 AK |
4556 | break; |
4557 | case 0x64: /* FS override */ | |
4558 | case 0x65: /* GS override */ | |
573e80fe BD |
4559 | has_seg_override = true; |
4560 | ctxt->seg_override = ctxt->b & 7; | |
dde7e6d1 AK |
4561 | break; |
4562 | case 0x40 ... 0x4f: /* REX */ | |
4563 | if (mode != X86EMUL_MODE_PROT64) | |
4564 | goto done_prefixes; | |
9dac77fa | 4565 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
4566 | continue; |
4567 | case 0xf0: /* LOCK */ | |
9dac77fa | 4568 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
4569 | break; |
4570 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 4571 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 4572 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
4573 | break; |
4574 | default: | |
4575 | goto done_prefixes; | |
4576 | } | |
4577 | ||
4578 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
4579 | ||
9dac77fa | 4580 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
4581 | } |
4582 | ||
4583 | done_prefixes: | |
4584 | ||
4585 | /* REX prefix. */ | |
9dac77fa AK |
4586 | if (ctxt->rex_prefix & 8) |
4587 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
4588 | |
4589 | /* Opcode byte(s). */ | |
9dac77fa | 4590 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 4591 | /* Two-byte opcode? */ |
9dac77fa | 4592 | if (ctxt->b == 0x0f) { |
1ce19dc1 | 4593 | ctxt->opcode_len = 2; |
e85a1085 | 4594 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 4595 | opcode = twobyte_table[ctxt->b]; |
0bc5eedb BP |
4596 | |
4597 | /* 0F_38 opcode map */ | |
4598 | if (ctxt->b == 0x38) { | |
4599 | ctxt->opcode_len = 3; | |
4600 | ctxt->b = insn_fetch(u8, ctxt); | |
4601 | opcode = opcode_map_0f_38[ctxt->b]; | |
4602 | } | |
dde7e6d1 | 4603 | } |
9dac77fa | 4604 | ctxt->d = opcode.flags; |
dde7e6d1 | 4605 | |
9f4260e7 TY |
4606 | if (ctxt->d & ModRM) |
4607 | ctxt->modrm = insn_fetch(u8, ctxt); | |
4608 | ||
7fe864dc NA |
4609 | /* vex-prefix instructions are not implemented */ |
4610 | if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && | |
d14cb5df | 4611 | (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { |
7fe864dc NA |
4612 | ctxt->d = NotImpl; |
4613 | } | |
4614 | ||
9dac77fa AK |
4615 | while (ctxt->d & GroupMask) { |
4616 | switch (ctxt->d & GroupMask) { | |
46561646 | 4617 | case Group: |
9dac77fa | 4618 | goffset = (ctxt->modrm >> 3) & 7; |
46561646 AK |
4619 | opcode = opcode.u.group[goffset]; |
4620 | break; | |
4621 | case GroupDual: | |
9dac77fa AK |
4622 | goffset = (ctxt->modrm >> 3) & 7; |
4623 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
4624 | opcode = opcode.u.gdual->mod3[goffset]; |
4625 | else | |
4626 | opcode = opcode.u.gdual->mod012[goffset]; | |
4627 | break; | |
4628 | case RMExt: | |
9dac77fa | 4629 | goffset = ctxt->modrm & 7; |
01de8b09 | 4630 | opcode = opcode.u.group[goffset]; |
46561646 AK |
4631 | break; |
4632 | case Prefix: | |
9dac77fa | 4633 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 4634 | return EMULATION_FAILED; |
9dac77fa | 4635 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
4636 | switch (simd_prefix) { |
4637 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
4638 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
4639 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
4640 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
4641 | } | |
4642 | break; | |
045a282c GN |
4643 | case Escape: |
4644 | if (ctxt->modrm > 0xbf) | |
4645 | opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; | |
4646 | else | |
4647 | opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; | |
4648 | break; | |
39f062ff NA |
4649 | case InstrDual: |
4650 | if ((ctxt->modrm >> 6) == 3) | |
4651 | opcode = opcode.u.idual->mod3; | |
4652 | else | |
4653 | opcode = opcode.u.idual->mod012; | |
4654 | break; | |
2276b511 NA |
4655 | case ModeDual: |
4656 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
4657 | opcode = opcode.u.mdual->mode64; | |
4658 | else | |
4659 | opcode = opcode.u.mdual->mode32; | |
4660 | break; | |
46561646 | 4661 | default: |
1d2887e2 | 4662 | return EMULATION_FAILED; |
0d7cdee8 | 4663 | } |
46561646 | 4664 | |
b1ea50b2 | 4665 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 4666 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
4667 | } |
4668 | ||
e24186e0 PB |
4669 | /* Unrecognised? */ |
4670 | if (ctxt->d == 0) | |
4671 | return EMULATION_FAILED; | |
4672 | ||
9dac77fa | 4673 | ctxt->execute = opcode.u.execute; |
dde7e6d1 | 4674 | |
3a6095a0 NA |
4675 | if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) |
4676 | return EMULATION_FAILED; | |
4677 | ||
d40a6898 | 4678 | if (unlikely(ctxt->d & |
ed9aad21 NA |
4679 | (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| |
4680 | No16))) { | |
d40a6898 PB |
4681 | /* |
4682 | * These are copied unconditionally here, and checked unconditionally | |
4683 | * in x86_emulate_insn. | |
4684 | */ | |
4685 | ctxt->check_perm = opcode.check_perm; | |
4686 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 | 4687 | |
d40a6898 PB |
4688 | if (ctxt->d & NotImpl) |
4689 | return EMULATION_FAILED; | |
d867162c | 4690 | |
58b7075d NA |
4691 | if (mode == X86EMUL_MODE_PROT64) { |
4692 | if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) | |
4693 | ctxt->op_bytes = 8; | |
4694 | else if (ctxt->d & NearBranch) | |
4695 | ctxt->op_bytes = 8; | |
4696 | } | |
7f9b4b75 | 4697 | |
d40a6898 PB |
4698 | if (ctxt->d & Op3264) { |
4699 | if (mode == X86EMUL_MODE_PROT64) | |
4700 | ctxt->op_bytes = 8; | |
4701 | else | |
4702 | ctxt->op_bytes = 4; | |
4703 | } | |
4704 | ||
ed9aad21 NA |
4705 | if ((ctxt->d & No16) && ctxt->op_bytes == 2) |
4706 | ctxt->op_bytes = 4; | |
4707 | ||
d40a6898 PB |
4708 | if (ctxt->d & Sse) |
4709 | ctxt->op_bytes = 16; | |
4710 | else if (ctxt->d & Mmx) | |
4711 | ctxt->op_bytes = 8; | |
4712 | } | |
1253791d | 4713 | |
dde7e6d1 | 4714 | /* ModRM and SIB bytes. */ |
9dac77fa | 4715 | if (ctxt->d & ModRM) { |
f09ed83e | 4716 | rc = decode_modrm(ctxt, &ctxt->memop); |
573e80fe BD |
4717 | if (!has_seg_override) { |
4718 | has_seg_override = true; | |
4719 | ctxt->seg_override = ctxt->modrm_seg; | |
4720 | } | |
9dac77fa | 4721 | } else if (ctxt->d & MemAbs) |
f09ed83e | 4722 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
4723 | if (rc != X86EMUL_CONTINUE) |
4724 | goto done; | |
4725 | ||
573e80fe BD |
4726 | if (!has_seg_override) |
4727 | ctxt->seg_override = VCPU_SREG_DS; | |
dde7e6d1 | 4728 | |
573e80fe | 4729 | ctxt->memop.addr.mem.seg = ctxt->seg_override; |
dde7e6d1 | 4730 | |
dde7e6d1 AK |
4731 | /* |
4732 | * Decode and fetch the source operand: register, memory | |
4733 | * or immediate. | |
4734 | */ | |
0fe59128 | 4735 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
4736 | if (rc != X86EMUL_CONTINUE) |
4737 | goto done; | |
4738 | ||
dde7e6d1 AK |
4739 | /* |
4740 | * Decode and fetch the second source operand: register, memory | |
4741 | * or immediate. | |
4742 | */ | |
4dd6a57d | 4743 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
4744 | if (rc != X86EMUL_CONTINUE) |
4745 | goto done; | |
4746 | ||
dde7e6d1 | 4747 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 4748 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 | 4749 | |
41061cdb | 4750 | if (ctxt->rip_relative) |
1c1c35ae NA |
4751 | ctxt->memopp->addr.mem.ea = address_mask(ctxt, |
4752 | ctxt->memopp->addr.mem.ea + ctxt->_eip); | |
cb16c348 | 4753 | |
a430c916 | 4754 | done: |
1d2887e2 | 4755 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
4756 | } |
4757 | ||
1cb3f3ae XG |
4758 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
4759 | { | |
4760 | return ctxt->d & PageTable; | |
4761 | } | |
4762 | ||
3e2f65d5 GN |
4763 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
4764 | { | |
3e2f65d5 GN |
4765 | /* The second termination condition only applies for REPE |
4766 | * and REPNE. Test if the repeat string operation prefix is | |
4767 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
4768 | * corresponding termination condition according to: | |
4769 | * - if REPE/REPZ and ZF = 0 then done | |
4770 | * - if REPNE/REPNZ and ZF = 1 then done | |
4771 | */ | |
9dac77fa AK |
4772 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
4773 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
4774 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 4775 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 4776 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
4777 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
4778 | return true; | |
4779 | ||
4780 | return false; | |
4781 | } | |
4782 | ||
cbe2c9d3 AK |
4783 | static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) |
4784 | { | |
4785 | bool fault = false; | |
4786 | ||
4787 | ctxt->ops->get_fpu(ctxt); | |
4788 | asm volatile("1: fwait \n\t" | |
4789 | "2: \n\t" | |
4790 | ".pushsection .fixup,\"ax\" \n\t" | |
4791 | "3: \n\t" | |
4792 | "movb $1, %[fault] \n\t" | |
4793 | "jmp 2b \n\t" | |
4794 | ".popsection \n\t" | |
4795 | _ASM_EXTABLE(1b, 3b) | |
38e8a2dd | 4796 | : [fault]"+qm"(fault)); |
cbe2c9d3 AK |
4797 | ctxt->ops->put_fpu(ctxt); |
4798 | ||
4799 | if (unlikely(fault)) | |
4800 | return emulate_exception(ctxt, MF_VECTOR, 0, false); | |
4801 | ||
4802 | return X86EMUL_CONTINUE; | |
4803 | } | |
4804 | ||
4805 | static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, | |
4806 | struct operand *op) | |
4807 | { | |
4808 | if (op->type == OP_MM) | |
4809 | read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); | |
4810 | } | |
4811 | ||
e28bbd44 AK |
4812 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) |
4813 | { | |
4814 | ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; | |
b9fa409b AK |
4815 | if (!(ctxt->d & ByteOp)) |
4816 | fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; | |
e28bbd44 | 4817 | asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" |
b8c0b6ae AK |
4818 | : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), |
4819 | [fastop]"+S"(fop) | |
4820 | : "c"(ctxt->src2.val)); | |
e28bbd44 | 4821 | ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); |
b8c0b6ae AK |
4822 | if (!fop) /* exception is returned in fop variable */ |
4823 | return emulate_de(ctxt); | |
e28bbd44 AK |
4824 | return X86EMUL_CONTINUE; |
4825 | } | |
dd856efa | 4826 | |
1498507a BD |
4827 | void init_decode_cache(struct x86_emulate_ctxt *ctxt) |
4828 | { | |
573e80fe BD |
4829 | memset(&ctxt->rip_relative, 0, |
4830 | (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); | |
1498507a | 4831 | |
1498507a BD |
4832 | ctxt->io_read.pos = 0; |
4833 | ctxt->io_read.end = 0; | |
1498507a BD |
4834 | ctxt->mem_read.end = 0; |
4835 | } | |
4836 | ||
7b105ca2 | 4837 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 4838 | { |
0225fb50 | 4839 | const struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 4840 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 4841 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 4842 | |
9dac77fa | 4843 | ctxt->mem_read.pos = 0; |
310b5d30 | 4844 | |
e24186e0 PB |
4845 | /* LOCK prefix is allowed only with some instructions */ |
4846 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { | |
35d3d4a1 | 4847 | rc = emulate_ud(ctxt); |
1161624f GN |
4848 | goto done; |
4849 | } | |
4850 | ||
e24186e0 | 4851 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 4852 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
4853 | goto done; |
4854 | } | |
4855 | ||
d40a6898 PB |
4856 | if (unlikely(ctxt->d & |
4857 | (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { | |
4858 | if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || | |
4859 | (ctxt->d & Undefined)) { | |
4860 | rc = emulate_ud(ctxt); | |
4861 | goto done; | |
4862 | } | |
1253791d | 4863 | |
d40a6898 PB |
4864 | if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) |
4865 | || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
4866 | rc = emulate_ud(ctxt); | |
cbe2c9d3 | 4867 | goto done; |
d40a6898 | 4868 | } |
cbe2c9d3 | 4869 | |
d40a6898 PB |
4870 | if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
4871 | rc = emulate_nm(ctxt); | |
c4f035c6 | 4872 | goto done; |
d40a6898 | 4873 | } |
c4f035c6 | 4874 | |
d40a6898 PB |
4875 | if (ctxt->d & Mmx) { |
4876 | rc = flush_pending_x87_faults(ctxt); | |
4877 | if (rc != X86EMUL_CONTINUE) | |
4878 | goto done; | |
4879 | /* | |
4880 | * Now that we know the fpu is exception safe, we can fetch | |
4881 | * operands from it. | |
4882 | */ | |
4883 | fetch_possible_mmx_operand(ctxt, &ctxt->src); | |
4884 | fetch_possible_mmx_operand(ctxt, &ctxt->src2); | |
4885 | if (!(ctxt->d & Mov)) | |
4886 | fetch_possible_mmx_operand(ctxt, &ctxt->dst); | |
4887 | } | |
e92805ac | 4888 | |
685bbf4a | 4889 | if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
d40a6898 PB |
4890 | rc = emulator_check_intercept(ctxt, ctxt->intercept, |
4891 | X86_ICPT_PRE_EXCEPT); | |
4892 | if (rc != X86EMUL_CONTINUE) | |
4893 | goto done; | |
4894 | } | |
8ea7d6ae | 4895 | |
64a38292 NA |
4896 | /* Instruction can only be executed in protected mode */ |
4897 | if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { | |
4898 | rc = emulate_ud(ctxt); | |
4899 | goto done; | |
4900 | } | |
4901 | ||
d40a6898 PB |
4902 | /* Privileged instruction can be executed only in CPL=0 */ |
4903 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { | |
68efa764 NA |
4904 | if (ctxt->d & PrivUD) |
4905 | rc = emulate_ud(ctxt); | |
4906 | else | |
4907 | rc = emulate_gp(ctxt, 0); | |
d09beabd | 4908 | goto done; |
d40a6898 | 4909 | } |
d09beabd | 4910 | |
d40a6898 | 4911 | /* Do instruction specific permission checks */ |
685bbf4a | 4912 | if (ctxt->d & CheckPerm) { |
d40a6898 PB |
4913 | rc = ctxt->check_perm(ctxt); |
4914 | if (rc != X86EMUL_CONTINUE) | |
4915 | goto done; | |
4916 | } | |
4917 | ||
685bbf4a | 4918 | if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
d40a6898 PB |
4919 | rc = emulator_check_intercept(ctxt, ctxt->intercept, |
4920 | X86_ICPT_POST_EXCEPT); | |
4921 | if (rc != X86EMUL_CONTINUE) | |
4922 | goto done; | |
4923 | } | |
4924 | ||
4925 | if (ctxt->rep_prefix && (ctxt->d & String)) { | |
4926 | /* All REP prefixes have the same first termination condition */ | |
4927 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { | |
4928 | ctxt->eip = ctxt->_eip; | |
4467c3f1 | 4929 | ctxt->eflags &= ~EFLG_RF; |
d40a6898 PB |
4930 | goto done; |
4931 | } | |
b9fa9d6b | 4932 | } |
b9fa9d6b AK |
4933 | } |
4934 | ||
9dac77fa AK |
4935 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4936 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4937 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4938 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4939 | goto done; |
9dac77fa | 4940 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4941 | } |
4942 | ||
9dac77fa AK |
4943 | if (ctxt->src2.type == OP_MEM) { |
4944 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4945 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4946 | if (rc != X86EMUL_CONTINUE) |
4947 | goto done; | |
4948 | } | |
4949 | ||
9dac77fa | 4950 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4951 | goto special_insn; |
4952 | ||
4953 | ||
9dac77fa | 4954 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4955 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4956 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4957 | &ctxt->dst.val, ctxt->dst.bytes); | |
c205fb7d | 4958 | if (rc != X86EMUL_CONTINUE) { |
d44e1212 PB |
4959 | if (!(ctxt->d & NoWrite) && |
4960 | rc == X86EMUL_PROPAGATE_FAULT && | |
c205fb7d NA |
4961 | ctxt->exception.vector == PF_VECTOR) |
4962 | ctxt->exception.error_code |= PFERR_WRITE_MASK; | |
69f55cb1 | 4963 | goto done; |
c205fb7d | 4964 | } |
038e51de | 4965 | } |
4ff6f8e6 PB |
4966 | /* Copy full 64-bit value for CMPXCHG8B. */ |
4967 | ctxt->dst.orig_val64 = ctxt->dst.val64; | |
038e51de | 4968 | |
018a98db AK |
4969 | special_insn: |
4970 | ||
685bbf4a | 4971 | if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { |
9dac77fa | 4972 | rc = emulator_check_intercept(ctxt, ctxt->intercept, |
8a76d7f2 | 4973 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4974 | if (rc != X86EMUL_CONTINUE) |
4975 | goto done; | |
4976 | } | |
4977 | ||
b9a1ecb9 NA |
4978 | if (ctxt->rep_prefix && (ctxt->d & String)) |
4979 | ctxt->eflags |= EFLG_RF; | |
4980 | else | |
4981 | ctxt->eflags &= ~EFLG_RF; | |
4467c3f1 | 4982 | |
9dac77fa | 4983 | if (ctxt->execute) { |
e28bbd44 AK |
4984 | if (ctxt->d & Fastop) { |
4985 | void (*fop)(struct fastop *) = (void *)ctxt->execute; | |
4986 | rc = fastop(ctxt, fop); | |
4987 | if (rc != X86EMUL_CONTINUE) | |
4988 | goto done; | |
4989 | goto writeback; | |
4990 | } | |
9dac77fa | 4991 | rc = ctxt->execute(ctxt); |
ef65c889 AK |
4992 | if (rc != X86EMUL_CONTINUE) |
4993 | goto done; | |
4994 | goto writeback; | |
4995 | } | |
4996 | ||
1ce19dc1 | 4997 | if (ctxt->opcode_len == 2) |
6aa8b732 | 4998 | goto twobyte_insn; |
0bc5eedb BP |
4999 | else if (ctxt->opcode_len == 3) |
5000 | goto threebyte_insn; | |
6aa8b732 | 5001 | |
9dac77fa | 5002 | switch (ctxt->b) { |
b2833e3c | 5003 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa | 5004 | if (test_cc(ctxt->b, ctxt->eflags)) |
234f3ce4 | 5005 | rc = jmp_rel(ctxt, ctxt->src.val); |
018a98db | 5006 | break; |
7e0b54b1 | 5007 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 5008 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 5009 | break; |
3d9e77df | 5010 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
dd856efa | 5011 | if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) |
a825f5cc NA |
5012 | ctxt->dst.type = OP_NONE; |
5013 | else | |
5014 | rc = em_xchg(ctxt); | |
e4f973ae | 5015 | break; |
e8b6fa70 | 5016 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
5017 | switch (ctxt->op_bytes) { |
5018 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
5019 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
5020 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
5021 | } |
5022 | break; | |
6e154e56 | 5023 | case 0xcc: /* int3 */ |
5c5df76b TY |
5024 | rc = emulate_int(ctxt, 3); |
5025 | break; | |
6e154e56 | 5026 | case 0xcd: /* int n */ |
9dac77fa | 5027 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
5028 | break; |
5029 | case 0xce: /* into */ | |
5c5df76b TY |
5030 | if (ctxt->eflags & EFLG_OF) |
5031 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 5032 | break; |
1a52e051 | 5033 | case 0xe9: /* jmp rel */ |
db5b0762 | 5034 | case 0xeb: /* jmp rel short */ |
234f3ce4 | 5035 | rc = jmp_rel(ctxt, ctxt->src.val); |
9dac77fa | 5036 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 5037 | break; |
111de5d6 | 5038 | case 0xf4: /* hlt */ |
6c3287f7 | 5039 | ctxt->ops->halt(ctxt); |
19fdfa0d | 5040 | break; |
111de5d6 AK |
5041 | case 0xf5: /* cmc */ |
5042 | /* complement carry flag from eflags reg */ | |
5043 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
5044 | break; |
5045 | case 0xf8: /* clc */ | |
5046 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 5047 | break; |
8744aa9a MG |
5048 | case 0xf9: /* stc */ |
5049 | ctxt->eflags |= EFLG_CF; | |
5050 | break; | |
fb4616f4 MG |
5051 | case 0xfc: /* cld */ |
5052 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
5053 | break; |
5054 | case 0xfd: /* std */ | |
5055 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 5056 | break; |
91269b8f AK |
5057 | default: |
5058 | goto cannot_emulate; | |
6aa8b732 | 5059 | } |
018a98db | 5060 | |
7d9ddaed AK |
5061 | if (rc != X86EMUL_CONTINUE) |
5062 | goto done; | |
5063 | ||
018a98db | 5064 | writeback: |
fb32b1ed AK |
5065 | if (ctxt->d & SrcWrite) { |
5066 | BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); | |
5067 | rc = writeback(ctxt, &ctxt->src); | |
5068 | if (rc != X86EMUL_CONTINUE) | |
5069 | goto done; | |
5070 | } | |
ee212297 NA |
5071 | if (!(ctxt->d & NoWrite)) { |
5072 | rc = writeback(ctxt, &ctxt->dst); | |
5073 | if (rc != X86EMUL_CONTINUE) | |
5074 | goto done; | |
5075 | } | |
018a98db | 5076 | |
5cd21917 GN |
5077 | /* |
5078 | * restore dst type in case the decoding will be reused | |
5079 | * (happens for string instruction ) | |
5080 | */ | |
9dac77fa | 5081 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 5082 | |
9dac77fa | 5083 | if ((ctxt->d & SrcMask) == SrcSI) |
f3bd64c6 | 5084 | string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); |
a682e354 | 5085 | |
9dac77fa | 5086 | if ((ctxt->d & DstMask) == DstDI) |
f3bd64c6 | 5087 | string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); |
d9271123 | 5088 | |
9dac77fa | 5089 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b3356bf0 | 5090 | unsigned int count; |
9dac77fa | 5091 | struct read_cache *r = &ctxt->io_read; |
b3356bf0 GN |
5092 | if ((ctxt->d & SrcMask) == SrcSI) |
5093 | count = ctxt->src.count; | |
5094 | else | |
5095 | count = ctxt->dst.count; | |
01485a22 | 5096 | register_address_increment(ctxt, VCPU_REGS_RCX, -count); |
3e2f65d5 | 5097 | |
d2ddd1c4 GN |
5098 | if (!string_insn_completed(ctxt)) { |
5099 | /* | |
5100 | * Re-enter guest when pio read ahead buffer is empty | |
5101 | * or, if it is not used, after each 1024 iteration. | |
5102 | */ | |
dd856efa | 5103 | if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && |
d2ddd1c4 GN |
5104 | (r->end == 0 || r->end != r->pos)) { |
5105 | /* | |
5106 | * Reset read cache. Usually happens before | |
5107 | * decode, but since instruction is restarted | |
5108 | * we have to do it here. | |
5109 | */ | |
9dac77fa | 5110 | ctxt->mem_read.end = 0; |
dd856efa | 5111 | writeback_registers(ctxt); |
d2ddd1c4 GN |
5112 | return EMULATION_RESTART; |
5113 | } | |
5114 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 5115 | } |
b9a1ecb9 | 5116 | ctxt->eflags &= ~EFLG_RF; |
5cd21917 | 5117 | } |
d2ddd1c4 | 5118 | |
9dac77fa | 5119 | ctxt->eip = ctxt->_eip; |
018a98db AK |
5120 | |
5121 | done: | |
e0ad0b47 PB |
5122 | if (rc == X86EMUL_PROPAGATE_FAULT) { |
5123 | WARN_ON(ctxt->exception.vector > 0x1f); | |
da9cb575 | 5124 | ctxt->have_exception = true; |
e0ad0b47 | 5125 | } |
775fde86 JR |
5126 | if (rc == X86EMUL_INTERCEPTED) |
5127 | return EMULATION_INTERCEPTED; | |
5128 | ||
dd856efa AK |
5129 | if (rc == X86EMUL_CONTINUE) |
5130 | writeback_registers(ctxt); | |
5131 | ||
d2ddd1c4 | 5132 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
5133 | |
5134 | twobyte_insn: | |
9dac77fa | 5135 | switch (ctxt->b) { |
018a98db | 5136 | case 0x09: /* wbinvd */ |
cfb22375 | 5137 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
5138 | break; |
5139 | case 0x08: /* invd */ | |
018a98db AK |
5140 | case 0x0d: /* GrpP (prefetch) */ |
5141 | case 0x18: /* Grp16 (prefetch/nop) */ | |
103f98ea | 5142 | case 0x1f: /* nop */ |
018a98db AK |
5143 | break; |
5144 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 5145 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 5146 | break; |
6aa8b732 | 5147 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 5148 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 5149 | break; |
6aa8b732 | 5150 | case 0x40 ... 0x4f: /* cmov */ |
140bad89 NA |
5151 | if (test_cc(ctxt->b, ctxt->eflags)) |
5152 | ctxt->dst.val = ctxt->src.val; | |
b91aa14d | 5153 | else if (ctxt->op_bytes != 4) |
9dac77fa | 5154 | ctxt->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 5155 | break; |
b2833e3c | 5156 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa | 5157 | if (test_cc(ctxt->b, ctxt->eflags)) |
234f3ce4 | 5158 | rc = jmp_rel(ctxt, ctxt->src.val); |
018a98db | 5159 | break; |
ee45b58e | 5160 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 5161 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 5162 | break; |
6aa8b732 | 5163 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa | 5164 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 5165 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val |
9dac77fa | 5166 | : (u16) ctxt->src.val; |
6aa8b732 | 5167 | break; |
6aa8b732 | 5168 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa | 5169 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 5170 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : |
9dac77fa | 5171 | (s16) ctxt->src.val; |
6aa8b732 | 5172 | break; |
91269b8f AK |
5173 | default: |
5174 | goto cannot_emulate; | |
6aa8b732 | 5175 | } |
7d9ddaed | 5176 | |
0bc5eedb BP |
5177 | threebyte_insn: |
5178 | ||
7d9ddaed AK |
5179 | if (rc != X86EMUL_CONTINUE) |
5180 | goto done; | |
5181 | ||
6aa8b732 AK |
5182 | goto writeback; |
5183 | ||
5184 | cannot_emulate: | |
a0c0ab2f | 5185 | return EMULATION_FAILED; |
6aa8b732 | 5186 | } |
dd856efa AK |
5187 | |
5188 | void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) | |
5189 | { | |
5190 | invalidate_registers(ctxt); | |
5191 | } | |
5192 | ||
5193 | void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) | |
5194 | { | |
5195 | writeback_registers(ctxt); | |
5196 | } |