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KVM: x86 emulator: covert SETCC to fastop
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 135/* Source 2 operand type */
d5ae7ce8 136#define Src2Shift (30)
4dd6a57d
AK		 137#define Src2None (OpNone << Src2Shift)
138#define Src2CL (OpCL << Src2Shift)
139#define Src2ImmByte (OpImmByte << Src2Shift)
140#define Src2One (OpOne << Src2Shift)
141#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 142#define Src2ES (OpES << Src2Shift)
143#define Src2CS (OpCS << Src2Shift)
144#define Src2SS (OpSS << Src2Shift)
145#define Src2DS (OpDS << Src2Shift)
146#define Src2FS (OpFS << Src2Shift)
147#define Src2GS (OpGS << Src2Shift)
4dd6a57d 148#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 149#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 150#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
151#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
152#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 153#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 154#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 155
d0e53325
AK		 156#define X2(x...) x, x
157#define X3(x...) X2(x), x
158#define X4(x...) X2(x), X2(x)
159#define X5(x...) X4(x), x
160#define X6(x...) X4(x), X2(x)
161#define X7(x...) X4(x), X3(x)
162#define X8(x...) X4(x), X4(x)
163#define X16(x...) X8(x), X8(x)
83babbca 164
e28bbd44
AK		 165#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
166#define FASTOP_SIZE 8
167
168/*
169 * fastop functions have a special calling convention:
170 *
171 * dst: [rdx]:rax (in/out)
172 * src: rbx (in/out)
173 * src2: rcx (in)
174 * flags: rflags (in/out)
175 *
176 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
177 * different operand sizes can be reached by calculation, rather than a jump
178 * table (which would be bigger than the code).
179 *
180 * fastop functions are declared as taking a never-defined fastop parameter,
181 * so they can't be called from C directly.
182 */
183
184struct fastop;
185
d65b1dee 186struct opcode {
b1ea50b2
AK		 187 u64 flags : 56;
188 u64 intercept : 8;
120df890 189 union {
ef65c889 190 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 191 const struct opcode *group;
192 const struct group_dual *gdual;
193 const struct gprefix *gprefix;
045a282c 194 const struct escape *esc;
e28bbd44 195 void (*fastop)(struct fastop *fake);
120df890 196 } u;
d09beabd 197 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 198};
199
200struct group_dual {
201 struct opcode mod012[8];
202 struct opcode mod3[8];
d65b1dee
AK		 203};
204
0d7cdee8
AK		 205struct gprefix {
206 struct opcode pfx_no;
207 struct opcode pfx_66;
208 struct opcode pfx_f2;
209 struct opcode pfx_f3;
210};
211
045a282c
GN		 212struct escape {
213 struct opcode op[8];
214 struct opcode high[64];
215};
216
6aa8b732 217/* EFLAGS bit definitions. */
d4c6a154
GN		 218#define EFLG_ID (1<<21)
219#define EFLG_VIP (1<<20)
220#define EFLG_VIF (1<<19)
221#define EFLG_AC (1<<18)
b1d86143
AP		 222#define EFLG_VM (1<<17)
223#define EFLG_RF (1<<16)
d4c6a154
GN		 224#define EFLG_IOPL (3<<12)
225#define EFLG_NT (1<<14)
6aa8b732
AK		 226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
b1d86143 228#define EFLG_IF (1<<9)
d4c6a154 229#define EFLG_TF (1<<8)
6aa8b732
AK		 230#define EFLG_SF (1<<7)
231#define EFLG_ZF (1<<6)
232#define EFLG_AF (1<<4)
233#define EFLG_PF (1<<2)
234#define EFLG_CF (1<<0)
235
62bd430e
MG		 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
237#define EFLG_RESERVED_ONE_MASK 2
238
dd856efa
AK		 239static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
240{
241 if (!(ctxt->regs_valid & (1 << nr))) {
242 ctxt->regs_valid |= 1 << nr;
243 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
244 }
245 return ctxt->_regs[nr];
246}
247
248static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
249{
250 ctxt->regs_valid |= 1 << nr;
251 ctxt->regs_dirty |= 1 << nr;
252 return &ctxt->_regs[nr];
253}
254
255static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 reg_read(ctxt, nr);
258 return reg_write(ctxt, nr);
259}
260
261static void writeback_registers(struct x86_emulate_ctxt *ctxt)
262{
263 unsigned reg;
264
265 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
266 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
267}
268
269static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
270{
271 ctxt->regs_dirty = 0;
272 ctxt->regs_valid = 0;
273}
274
6aa8b732
AK		 275/*
276 * Instruction emulation:
277 * Most instructions are emulated directly via a fragment of inline assembly
278 * code. This allows us to save/restore EFLAGS and thus very easily pick up
279 * any modified flags.
280 */
281
05b3e0c2 282#if defined(CONFIG_X86_64)
6aa8b732
AK		 283#define _LO32 "k" /* force 32-bit operand */
284#define _STK "%%rsp" /* stack pointer */
285#elif defined(__i386__)
286#define _LO32 "" /* force 32-bit operand */
287#define _STK "%%esp" /* stack pointer */
288#endif
289
290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
296/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 297#define _PRE_EFLAGS(_sav, _msk, _tmp) \
298 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
299 "movl %"_sav",%"_LO32 _tmp"; " \
300 "push %"_tmp"; " \
301 "push %"_tmp"; " \
302 "movl %"_msk",%"_LO32 _tmp"; " \
303 "andl %"_LO32 _tmp",("_STK"); " \
304 "pushf; " \
305 "notl %"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
308 "pop %"_tmp"; " \
309 "orl %"_LO32 _tmp",("_STK"); " \
310 "popf; " \
311 "pop %"_sav"; "
6aa8b732
AK		 312
313/* After executing instruction: write-back necessary bits in EFLAGS. */
314#define _POST_EFLAGS(_sav, _msk, _tmp) \
315 /* _sav |= EFLAGS & _msk; */ \
316 "pushf; " \
317 "pop %"_tmp"; " \
318 "andl %"_msk",%"_LO32 _tmp"; " \
319 "orl %"_LO32 _tmp",%"_sav"; "
320
dda96d8f
AK		 321#ifdef CONFIG_X86_64
322#define ON64(x) x
323#else
324#define ON64(x)
325#endif
326
a31b9cea 327#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 328 do { \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "2") \
331 _op _suffix " %"_x"3,%1; " \
332 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 333 : "=m" ((ctxt)->eflags), \
334 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 335 "=&r" (_tmp) \
a31b9cea 336 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 337 } while (0)
6b7ad61f
AK		 338
339
6aa8b732 340/* Raw emulation: instruction has two explicit operands. */
a31b9cea 341#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 342 do { \
343 unsigned long _tmp; \
344 \
a31b9cea 345 switch ((ctxt)->dst.bytes) { \
6b7ad61f 346 case 2: \
a31b9cea 347 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 348 break; \
349 case 4: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 351 break; \
352 case 8: \
a31b9cea 353 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 354 break; \
355 } \
6aa8b732
AK		 356 } while (0)
357
a31b9cea 358#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 359 do { \
6b7ad61f 360 unsigned long _tmp; \
a31b9cea 361 switch ((ctxt)->dst.bytes) { \
6aa8b732 362 case 1: \
a31b9cea 363 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 364 break; \
365 default: \
a31b9cea 366 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 367 _wx, _wy, _lx, _ly, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 373#define emulate_2op_SrcB(ctxt, _op) \
374 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 375
376/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 377#define emulate_2op_SrcV(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 379
380/* Source operand is word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV_nobyte(ctxt, _op) \
382 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 383
d175226a 384/* Instruction has three operands and one operand is stored in ECX register */
29053a60 385#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 386 do { \
387 unsigned long _tmp; \
761441b9
AK		 388 _type _clv = (ctxt)->src2.val; \
389 _type _srcv = (ctxt)->src.val; \
390 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 391 \
392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "5", "2") \
394 _op _suffix " %4,%1 \n" \
395 _POST_EFLAGS("0", "5", "2") \
761441b9 396 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 397 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
398 ); \
399 \
761441b9
AK		 400 (ctxt)->src2.val = (unsigned long) _clv; \
401 (ctxt)->src2.val = (unsigned long) _srcv; \
402 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 403 } while (0)
404
761441b9 405#define emulate_2op_cl(ctxt, _op) \
7295261c 406 do { \
761441b9 407 switch ((ctxt)->dst.bytes) { \
7295261c 408 case 2: \
29053a60 409 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 410 break; \
411 case 4: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 413 break; \
414 case 8: \
29053a60 415 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 416 break; \
417 } \
d175226a
GT		 418 } while (0)
419
d1eef45d 420#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 421 do { \
422 unsigned long _tmp; \
423 \
dda96d8f
AK		 424 __asm__ __volatile__ ( \
425 _PRE_EFLAGS("0", "3", "2") \
426 _op _suffix " %1; " \
427 _POST_EFLAGS("0", "3", "2") \
d1eef45d 428 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 429 "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK)); \
431 } while (0)
432
433/* Instruction has only one explicit operand (no source operand). */
d1eef45d 434#define emulate_1op(ctxt, _op) \
dda96d8f 435 do { \
d1eef45d
AK		 436 switch ((ctxt)->dst.bytes) { \
437 case 1: __emulate_1op(ctxt, _op, "b"); break; \
438 case 2: __emulate_1op(ctxt, _op, "w"); break; \
439 case 4: __emulate_1op(ctxt, _op, "l"); break; \
440 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 441 } \
442 } while (0)
443
b7d491e7
AK		 444#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
445#define FOP_RET "ret \n\t"
446
447#define FOP_START(op) \
448 extern void em_##op(struct fastop *fake); \
449 asm(".pushsection .text, \"ax\" \n\t" \
450 ".global em_" #op " \n\t" \
451 FOP_ALIGN \
452 "em_" #op ": \n\t"
453
454#define FOP_END \
455 ".popsection")
456
0bdea068
AK		 457#define FOPNOP() FOP_ALIGN FOP_RET
458
b7d491e7
AK		 459#define FOP1E(op, dst) \
460 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
461
462#define FASTOP1(op) \
463 FOP_START(op) \
464 FOP1E(op##b, al) \
465 FOP1E(op##w, ax) \
466 FOP1E(op##l, eax) \
467 ON64(FOP1E(op##q, rax)) \
468 FOP_END
469
f7857f35
AK		 470#define FOP2E(op, dst, src) \
471 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
472
473#define FASTOP2(op) \
474 FOP_START(op) \
475 FOP2E(op##b, al, bl) \
476 FOP2E(op##w, ax, bx) \
477 FOP2E(op##l, eax, ebx) \
478 ON64(FOP2E(op##q, rax, rbx)) \
479 FOP_END
480
007a3b54
AK		 481/* 2 operand, src is CL */
482#define FASTOP2CL(op) \
483 FOP_START(op) \
484 FOP2E(op##b, al, cl) \
485 FOP2E(op##w, ax, cl) \
486 FOP2E(op##l, eax, cl) \
487 ON64(FOP2E(op##q, rax, cl)) \
488 FOP_END
489
0bdea068
AK		 490#define FOP3E(op, dst, src, src2) \
491 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
492
493/* 3-operand, word-only, src2=cl */
494#define FASTOP3WCL(op) \
495 FOP_START(op) \
496 FOPNOP() \
497 FOP3E(op##w, ax, bx, cl) \
498 FOP3E(op##l, eax, ebx, cl) \
499 ON64(FOP3E(op##q, rax, rbx, cl)) \
500 FOP_END
501
9ae9feba
AK		 502/* Special case for SETcc - 1 instruction per cc */
503#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
504
505FOP_START(setcc)
506FOP_SETCC(seto)
507FOP_SETCC(setno)
508FOP_SETCC(setc)
509FOP_SETCC(setnc)
510FOP_SETCC(setz)
511FOP_SETCC(setnz)
512FOP_SETCC(setbe)
513FOP_SETCC(setnbe)
514FOP_SETCC(sets)
515FOP_SETCC(setns)
516FOP_SETCC(setp)
517FOP_SETCC(setnp)
518FOP_SETCC(setl)
519FOP_SETCC(setnl)
520FOP_SETCC(setle)
521FOP_SETCC(setnle)
522FOP_END;
523
e8f2b1d6 524#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 525 do { \
526 unsigned long _tmp; \
dd856efa
AK		 527 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
528 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 529 \
530 __asm__ __volatile__ ( \
531 _PRE_EFLAGS("0", "5", "1") \
532 "1: \n\t" \
533 _op _suffix " %6; " \
534 "2: \n\t" \
535 _POST_EFLAGS("0", "5", "1") \
536 ".pushsection .fixup,\"ax\" \n\t" \
537 "3: movb $1, %4 \n\t" \
538 "jmp 2b \n\t" \
539 ".popsection \n\t" \
540 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 541 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
542 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 543 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 544 } while (0)
545
3f9f53b0 546/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 547#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 548 do { \
e8f2b1d6 549 switch((ctxt)->src.bytes) { \
7295261c 550 case 1: \
e8f2b1d6 551 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 552 break; \
553 case 2: \
e8f2b1d6 554 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 555 break; \
556 case 4: \
e8f2b1d6 557 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 558 break; \
559 case 8: ON64( \
e8f2b1d6 560 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 561 break; \
562 } \
563 } while (0)
564
8a76d7f2
JR		 565static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
566 enum x86_intercept intercept,
567 enum x86_intercept_stage stage)
568{
569 struct x86_instruction_info info = {
570 .intercept = intercept,
9dac77fa
AK		 571 .rep_prefix = ctxt->rep_prefix,
572 .modrm_mod = ctxt->modrm_mod,
573 .modrm_reg = ctxt->modrm_reg,
574 .modrm_rm = ctxt->modrm_rm,
575 .src_val = ctxt->src.val64,
576 .src_bytes = ctxt->src.bytes,
577 .dst_bytes = ctxt->dst.bytes,
578 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 579 .next_rip = ctxt->eip,
580 };
581
2953538e 582 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 583}
584
f47cfa31
AK		 585static void assign_masked(ulong *dest, ulong src, ulong mask)
586{
587 *dest = (*dest & ~mask) | (src & mask);
588}
589
9dac77fa 590static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 591{
9dac77fa 592 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 593}
594
f47cfa31
AK		 595static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
596{
597 u16 sel;
598 struct desc_struct ss;
599
600 if (ctxt->mode == X86EMUL_MODE_PROT64)
601 return ~0UL;
602 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
603 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
604}
605
612e89f0
AK		 606static int stack_size(struct x86_emulate_ctxt *ctxt)
607{
608 return (__fls(stack_mask(ctxt)) + 1) >> 3;
609}
610
6aa8b732 611/* Access/update address held in a register, based on addressing mode. */
e4706772 612static inline unsigned long
9dac77fa 613address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 614{
9dac77fa 615 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 616 return reg;
617 else
9dac77fa 618 return reg & ad_mask(ctxt);
e4706772
HH		 619}
620
621static inline unsigned long
9dac77fa 622register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 623{
9dac77fa 624 return address_mask(ctxt, reg);
e4706772
HH		 625}
626
5ad105e5
AK		 627static void masked_increment(ulong *reg, ulong mask, int inc)
628{
629 assign_masked(reg, *reg + inc, mask);
630}
631
7a957275 632static inline void
9dac77fa 633register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 634{
5ad105e5
AK		 635 ulong mask;
636
9dac77fa 637 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 638 mask = ~0UL;
7a957275 639 else
5ad105e5
AK		 640 mask = ad_mask(ctxt);
641 masked_increment(reg, mask, inc);
642}
643
644static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
645{
dd856efa 646 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 647}
6aa8b732 648
9dac77fa 649static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 650{
9dac77fa 651 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 652}
098c937b 653
56697687
AK		 654static u32 desc_limit_scaled(struct desc_struct *desc)
655{
656 u32 limit = get_desc_limit(desc);
657
658 return desc->g ? (limit << 12) | 0xfff : limit;
659}
660
9dac77fa 661static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 662{
9dac77fa
AK		 663 ctxt->has_seg_override = true;
664 ctxt->seg_override = seg;
7a5b56df
AK		 665}
666
7b105ca2 667static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 668{
669 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
670 return 0;
671
7b105ca2 672 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 673}
674
9dac77fa 675static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 676{
9dac77fa 677 if (!ctxt->has_seg_override)
7a5b56df
AK		 678 return 0;
679
9dac77fa 680 return ctxt->seg_override;
7a5b56df
AK		 681}
682
35d3d4a1
AK		 683static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
684 u32 error, bool valid)
54b8486f 685{
da9cb575
AK		 686 ctxt->exception.vector = vec;
687 ctxt->exception.error_code = error;
688 ctxt->exception.error_code_valid = valid;
35d3d4a1 689 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 690}
691
3b88e41a
JR		 692static int emulate_db(struct x86_emulate_ctxt *ctxt)
693{
694 return emulate_exception(ctxt, DB_VECTOR, 0, false);
695}
696
35d3d4a1 697static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 698{
35d3d4a1 699 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 700}
701
618ff15d
AK		 702static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
703{
704 return emulate_exception(ctxt, SS_VECTOR, err, true);
705}
706
35d3d4a1 707static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 708{
35d3d4a1 709 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 710}
711
35d3d4a1 712static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 713{
35d3d4a1 714 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 715}
716
34d1f490
AK		 717static int emulate_de(struct x86_emulate_ctxt *ctxt)
718{
35d3d4a1 719 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 720}
721
1253791d
AK		 722static int emulate_nm(struct x86_emulate_ctxt *ctxt)
723{
724 return emulate_exception(ctxt, NM_VECTOR, 0, false);
725}
726
1aa36616
AK		 727static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
728{
729 u16 selector;
730 struct desc_struct desc;
731
732 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
733 return selector;
734}
735
736static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
737 unsigned seg)
738{
739 u16 dummy;
740 u32 base3;
741 struct desc_struct desc;
742
743 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
744 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
745}
746
1c11b376
AK		 747/*
748 * x86 defines three classes of vector instructions: explicitly
749 * aligned, explicitly unaligned, and the rest, which change behaviour
750 * depending on whether they're AVX encoded or not.
751 *
752 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
753 * subject to the same check.
754 */
755static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
756{
757 if (likely(size < 16))
758 return false;
759
760 if (ctxt->d & Aligned)
761 return true;
762 else if (ctxt->d & Unaligned)
763 return false;
764 else if (ctxt->d & Avx)
765 return false;
766 else
767 return true;
768}
769
3d9b938e 770static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 771 struct segmented_address addr,
3d9b938e 772 unsigned size, bool write, bool fetch,
52fd8b44
AK		 773 ulong *linear)
774{
618ff15d
AK		 775 struct desc_struct desc;
776 bool usable;
52fd8b44 777 ulong la;
618ff15d 778 u32 lim;
1aa36616 779 u16 sel;
3a78a4f4 780 unsigned cpl;
52fd8b44 781
7b105ca2 782 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 783 switch (ctxt->mode) {
618ff15d
AK		 784 case X86EMUL_MODE_PROT64:
785 if (((signed long)la << 16) >> 16 != la)
786 return emulate_gp(ctxt, 0);
787 break;
788 default:
1aa36616
AK		 789 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
790 addr.seg);
618ff15d
AK		 791 if (!usable)
792 goto bad;
58b7825b
GN		 793 /* code segment in protected mode or read-only data segment */
794 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
795 || !(desc.type & 2)) && write)
618ff15d
AK		 796 goto bad;
797 /* unreadable code segment */
3d9b938e 798 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 799 goto bad;
800 lim = desc_limit_scaled(&desc);
801 if ((desc.type & 8) || !(desc.type & 4)) {
802 /* expand-up segment */
803 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
804 goto bad;
805 } else {
fc058680 806 /* expand-down segment */
618ff15d
AK		 807 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
808 goto bad;
809 lim = desc.d ? 0xffffffff : 0xffff;
810 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
811 goto bad;
812 }
717746e3 813 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 814 if (!(desc.type & 8)) {
815 /* data segment */
816 if (cpl > desc.dpl)
817 goto bad;
818 } else if ((desc.type & 8) && !(desc.type & 4)) {
819 /* nonconforming code segment */
820 if (cpl != desc.dpl)
821 goto bad;
822 } else if ((desc.type & 8) && (desc.type & 4)) {
823 /* conforming code segment */
824 if (cpl < desc.dpl)
825 goto bad;
826 }
827 break;
828 }
9dac77fa 829 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 830 la &= (u32)-1;
1c11b376
AK		 831 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
832 return emulate_gp(ctxt, 0);
52fd8b44
AK		 833 *linear = la;
834 return X86EMUL_CONTINUE;
618ff15d
AK		 835bad:
836 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 837 return emulate_ss(ctxt, sel);
618ff15d 838 else
0afbe2f8 839 return emulate_gp(ctxt, sel);
52fd8b44
AK		 840}
841
3d9b938e
NE		 842static int linearize(struct x86_emulate_ctxt *ctxt,
843 struct segmented_address addr,
844 unsigned size, bool write,
845 ulong *linear)
846{
847 return __linearize(ctxt, addr, size, write, false, linear);
848}
849
850
3ca3ac4d
AK		 851static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
852 struct segmented_address addr,
853 void *data,
854 unsigned size)
855{
9fa088f4
AK		 856 int rc;
857 ulong linear;
858
83b8795a 859 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 860 if (rc != X86EMUL_CONTINUE)
861 return rc;
0f65dd70 862 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 863}
864
807941b1
TY		 865/*
866 * Fetch the next byte of the instruction being emulated which is pointed to
867 * by ctxt->_eip, then increment ctxt->_eip.
868 *
869 * Also prefetch the remaining bytes of the instruction without crossing page
870 * boundary if they are not in fetch_cache yet.
871 */
872static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 873{
9dac77fa 874 struct fetch_cache *fc = &ctxt->fetch;
62266869 875 int rc;
2fb53ad8 876 int size, cur_size;
62266869 877
807941b1 878 if (ctxt->_eip == fc->end) {
3d9b938e 879 unsigned long linear;
807941b1
TY		 880 struct segmented_address addr = { .seg = VCPU_SREG_CS,
881 .ea = ctxt->_eip };
2fb53ad8 882 cur_size = fc->end - fc->start;
807941b1
TY		 883 size = min(15UL - cur_size,
884 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 885 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 886 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 887 return rc;
ef5d75cc
TY		 888 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
889 size, &ctxt->exception);
7d88bb48 890 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 891 return rc;
2fb53ad8 892 fc->end += size;
62266869 893 }
807941b1
TY		 894 *dest = fc->data[ctxt->_eip - fc->start];
895 ctxt->_eip++;
3e2815e9 896 return X86EMUL_CONTINUE;
62266869
AK		 897}
898
899static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 900 void *dest, unsigned size)
62266869 901{
3e2815e9 902 int rc;
62266869 903
eb3c79e6 904 /* x86 instructions are limited to 15 bytes. */
7d88bb48 905 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 906 return X86EMUL_UNHANDLEABLE;
62266869 907 while (size--) {
807941b1 908 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 909 if (rc != X86EMUL_CONTINUE)
62266869
AK		 910 return rc;
911 }
3e2815e9 912 return X86EMUL_CONTINUE;
62266869
AK		 913}
914
67cbc90d 915/* Fetch next part of the instruction being emulated. */
e85a1085 916#define insn_fetch(_type, _ctxt) \
67cbc90d 917({ unsigned long _x; \
e85a1085 918 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 919 if (rc != X86EMUL_CONTINUE) \
920 goto done; \
67cbc90d
TY		 921 (_type)_x; \
922})
923
807941b1
TY		 924#define insn_fetch_arr(_arr, _size, _ctxt) \
925({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 926 if (rc != X86EMUL_CONTINUE) \
927 goto done; \
67cbc90d
TY		 928})
929
1e3c5cb0
RR		 930/*
931 * Given the 'reg' portion of a ModRM byte, and a register block, return a
932 * pointer into the block that addresses the relevant register.
933 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
934 */
dd856efa 935static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 936 int highbyte_regs)
6aa8b732
AK		 937{
938 void *p;
939
6aa8b732 940 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 941 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
942 else
943 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 944 return p;
945}
946
947static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 948 struct segmented_address addr,
6aa8b732
AK		 949 u16 *size, unsigned long *address, int op_bytes)
950{
951 int rc;
952
953 if (op_bytes == 2)
954 op_bytes = 3;
955 *address = 0;
3ca3ac4d 956 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 957 if (rc != X86EMUL_CONTINUE)
6aa8b732 958 return rc;
30b31ab6 959 addr.ea += 2;
3ca3ac4d 960 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 961 return rc;
962}
963
9ae9feba 964static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 965{
9ae9feba
AK		 966 u8 rc;
967 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 968
9ae9feba
AK		 969 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
970 asm("pushq %[flags]; popf; call *%[fastop]"
971 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
972 return rc;
bbe9abbd
NK		 973}
974
91ff3cb4
AK		 975static void fetch_register_operand(struct operand *op)
976{
977 switch (op->bytes) {
978 case 1:
979 op->val = *(u8 *)op->addr.reg;
980 break;
981 case 2:
982 op->val = *(u16 *)op->addr.reg;
983 break;
984 case 4:
985 op->val = *(u32 *)op->addr.reg;
986 break;
987 case 8:
988 op->val = *(u64 *)op->addr.reg;
989 break;
990 }
991}
992
1253791d
AK		 993static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
994{
995 ctxt->ops->get_fpu(ctxt);
996 switch (reg) {
89a87c67
MK		 997 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
998 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
999 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1000 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1001 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1002 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1003 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1004 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1005#ifdef CONFIG_X86_64
89a87c67
MK		 1006 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1007 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1008 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1009 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1010 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1011 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1012 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1013 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1014#endif
1015 default: BUG();
1016 }
1017 ctxt->ops->put_fpu(ctxt);
1018}
1019
1020static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1021 int reg)
1022{
1023 ctxt->ops->get_fpu(ctxt);
1024 switch (reg) {
89a87c67
MK		 1025 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1026 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1027 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1028 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1029 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1030 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1031 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1032 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1033#ifdef CONFIG_X86_64
89a87c67
MK		 1034 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1035 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1036 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1037 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1038 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1039 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1040 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1041 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1042#endif
1043 default: BUG();
1044 }
1045 ctxt->ops->put_fpu(ctxt);
1046}
1047
cbe2c9d3
AK		 1048static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1049{
1050 ctxt->ops->get_fpu(ctxt);
1051 switch (reg) {
1052 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1053 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1054 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1055 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1056 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1057 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1058 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1059 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1060 default: BUG();
1061 }
1062 ctxt->ops->put_fpu(ctxt);
1063}
1064
1065static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1066{
1067 ctxt->ops->get_fpu(ctxt);
1068 switch (reg) {
1069 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1070 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1071 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1072 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1073 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1074 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1075 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1076 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1077 default: BUG();
1078 }
1079 ctxt->ops->put_fpu(ctxt);
1080}
1081
045a282c
GN		 1082static int em_fninit(struct x86_emulate_ctxt *ctxt)
1083{
1084 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1085 return emulate_nm(ctxt);
1086
1087 ctxt->ops->get_fpu(ctxt);
1088 asm volatile("fninit");
1089 ctxt->ops->put_fpu(ctxt);
1090 return X86EMUL_CONTINUE;
1091}
1092
1093static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1094{
1095 u16 fcw;
1096
1097 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1098 return emulate_nm(ctxt);
1099
1100 ctxt->ops->get_fpu(ctxt);
1101 asm volatile("fnstcw %0": "+m"(fcw));
1102 ctxt->ops->put_fpu(ctxt);
1103
1104 /* force 2 byte destination */
1105 ctxt->dst.bytes = 2;
1106 ctxt->dst.val = fcw;
1107
1108 return X86EMUL_CONTINUE;
1109}
1110
1111static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1112{
1113 u16 fsw;
1114
1115 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1116 return emulate_nm(ctxt);
1117
1118 ctxt->ops->get_fpu(ctxt);
1119 asm volatile("fnstsw %0": "+m"(fsw));
1120 ctxt->ops->put_fpu(ctxt);
1121
1122 /* force 2 byte destination */
1123 ctxt->dst.bytes = 2;
1124 ctxt->dst.val = fsw;
1125
1126 return X86EMUL_CONTINUE;
1127}
1128
1253791d 1129static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1130 struct operand *op)
3c118e24 1131{
9dac77fa
AK		 1132 unsigned reg = ctxt->modrm_reg;
1133 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1134
9dac77fa
AK		 1135 if (!(ctxt->d & ModRM))
1136 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1137
9dac77fa 1138 if (ctxt->d & Sse) {
1253791d
AK		 1139 op->type = OP_XMM;
1140 op->bytes = 16;
1141 op->addr.xmm = reg;
1142 read_sse_reg(ctxt, &op->vec_val, reg);
1143 return;
1144 }
cbe2c9d3
AK		 1145 if (ctxt->d & Mmx) {
1146 reg &= 7;
1147 op->type = OP_MM;
1148 op->bytes = 8;
1149 op->addr.mm = reg;
1150 return;
1151 }
1253791d 1152
3c118e24 1153 op->type = OP_REG;
2adb5ad9 1154 if (ctxt->d & ByteOp) {
dd856efa 1155 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1156 op->bytes = 1;
1157 } else {
dd856efa 1158 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1159 op->bytes = ctxt->op_bytes;
3c118e24 1160 }
91ff3cb4 1161 fetch_register_operand(op);
3c118e24
AK		 1162 op->orig_val = op->val;
1163}
1164
a6e3407b
AK		 1165static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1166{
1167 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1168 ctxt->modrm_seg = VCPU_SREG_SS;
1169}
1170
1c73ef66 1171static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1172 struct operand *op)
1c73ef66 1173{
1c73ef66 1174 u8 sib;
f5b4edcd 1175 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1176 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1177 ulong modrm_ea = 0;
1c73ef66 1178
9dac77fa
AK		 1179 if (ctxt->rex_prefix) {
1180 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1181 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1182 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1183 }
1184
9dac77fa
AK		 1185 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1186 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1187 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1188 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1189
9dac77fa 1190 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1191 op->type = OP_REG;
9dac77fa 1192 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1193 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1194 if (ctxt->d & Sse) {
1253791d
AK		 1195 op->type = OP_XMM;
1196 op->bytes = 16;
9dac77fa
AK		 1197 op->addr.xmm = ctxt->modrm_rm;
1198 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1199 return rc;
1200 }
cbe2c9d3
AK		 1201 if (ctxt->d & Mmx) {
1202 op->type = OP_MM;
1203 op->bytes = 8;
1204 op->addr.xmm = ctxt->modrm_rm & 7;
1205 return rc;
1206 }
2dbd0dd7 1207 fetch_register_operand(op);
1c73ef66
AK		 1208 return rc;
1209 }
1210
2dbd0dd7
AK		 1211 op->type = OP_MEM;
1212
9dac77fa 1213 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1214 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1215 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1216 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1217 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1218
1219 /* 16-bit ModR/M decode. */
9dac77fa 1220 switch (ctxt->modrm_mod) {
1c73ef66 1221 case 0:
9dac77fa 1222 if (ctxt->modrm_rm == 6)
e85a1085 1223 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1224 break;
1225 case 1:
e85a1085 1226 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1227 break;
1228 case 2:
e85a1085 1229 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1230 break;
1231 }
9dac77fa 1232 switch (ctxt->modrm_rm) {
1c73ef66 1233 case 0:
2dbd0dd7 1234 modrm_ea += bx + si;
1c73ef66
AK		 1235 break;
1236 case 1:
2dbd0dd7 1237 modrm_ea += bx + di;
1c73ef66
AK		 1238 break;
1239 case 2:
2dbd0dd7 1240 modrm_ea += bp + si;
1c73ef66
AK		 1241 break;
1242 case 3:
2dbd0dd7 1243 modrm_ea += bp + di;
1c73ef66
AK		 1244 break;
1245 case 4:
2dbd0dd7 1246 modrm_ea += si;
1c73ef66
AK		 1247 break;
1248 case 5:
2dbd0dd7 1249 modrm_ea += di;
1c73ef66
AK		 1250 break;
1251 case 6:
9dac77fa 1252 if (ctxt->modrm_mod != 0)
2dbd0dd7 1253 modrm_ea += bp;
1c73ef66
AK		 1254 break;
1255 case 7:
2dbd0dd7 1256 modrm_ea += bx;
1c73ef66
AK		 1257 break;
1258 }
9dac77fa
AK		 1259 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1260 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1261 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1262 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1263 } else {
1264 /* 32/64-bit ModR/M decode. */
9dac77fa 1265 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1266 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1267 index_reg |= (sib >> 3) & 7;
1268 base_reg |= sib & 7;
1269 scale = sib >> 6;
1270
9dac77fa 1271 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1272 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1273 else {
dd856efa 1274 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1275 adjust_modrm_seg(ctxt, base_reg);
1276 }
dc71d0f1 1277 if (index_reg != 4)
dd856efa 1278 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1279 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1280 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1281 ctxt->rip_relative = 1;
a6e3407b
AK		 1282 } else {
1283 base_reg = ctxt->modrm_rm;
dd856efa 1284 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1285 adjust_modrm_seg(ctxt, base_reg);
1286 }
9dac77fa 1287 switch (ctxt->modrm_mod) {
1c73ef66 1288 case 0:
9dac77fa 1289 if (ctxt->modrm_rm == 5)
e85a1085 1290 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1291 break;
1292 case 1:
e85a1085 1293 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1294 break;
1295 case 2:
e85a1085 1296 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1297 break;
1298 }
1299 }
90de84f5 1300 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1301done:
1302 return rc;
1303}
1304
1305static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1306 struct operand *op)
1c73ef66 1307{
3e2815e9 1308 int rc = X86EMUL_CONTINUE;
1c73ef66 1309
2dbd0dd7 1310 op->type = OP_MEM;
9dac77fa 1311 switch (ctxt->ad_bytes) {
1c73ef66 1312 case 2:
e85a1085 1313 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1314 break;
1315 case 4:
e85a1085 1316 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1317 break;
1318 case 8:
e85a1085 1319 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1320 break;
1321 }
1322done:
1323 return rc;
1324}
1325
9dac77fa 1326static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1327{
7129eeca 1328 long sv = 0, mask;
35c843c4 1329
9dac77fa
AK		 1330 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1331 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1332
9dac77fa
AK		 1333 if (ctxt->src.bytes == 2)
1334 sv = (s16)ctxt->src.val & (s16)mask;
1335 else if (ctxt->src.bytes == 4)
1336 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1337
9dac77fa 1338 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1339 }
ba7ff2b7
WY		 1340
1341 /* only subword offset */
9dac77fa 1342 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1343}
1344
dde7e6d1 1345static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1346 unsigned long addr, void *dest, unsigned size)
6aa8b732 1347{
dde7e6d1 1348 int rc;
9dac77fa 1349 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1350
f23b070e
XG		 1351 if (mc->pos < mc->end)
1352 goto read_cached;
6aa8b732 1353
f23b070e
XG		 1354 WARN_ON((mc->end + size) >= sizeof(mc->data));
1355
1356 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1357 &ctxt->exception);
1358 if (rc != X86EMUL_CONTINUE)
1359 return rc;
1360
1361 mc->end += size;
1362
1363read_cached:
1364 memcpy(dest, mc->data + mc->pos, size);
1365 mc->pos += size;
dde7e6d1
AK		 1366 return X86EMUL_CONTINUE;
1367}
6aa8b732 1368
3ca3ac4d
AK		 1369static int segmented_read(struct x86_emulate_ctxt *ctxt,
1370 struct segmented_address addr,
1371 void *data,
1372 unsigned size)
1373{
9fa088f4
AK		 1374 int rc;
1375 ulong linear;
1376
83b8795a 1377 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1378 if (rc != X86EMUL_CONTINUE)
1379 return rc;
7b105ca2 1380 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1381}
1382
1383static int segmented_write(struct x86_emulate_ctxt *ctxt,
1384 struct segmented_address addr,
1385 const void *data,
1386 unsigned size)
1387{
9fa088f4
AK		 1388 int rc;
1389 ulong linear;
1390
83b8795a 1391 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1392 if (rc != X86EMUL_CONTINUE)
1393 return rc;
0f65dd70
AK		 1394 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1395 &ctxt->exception);
3ca3ac4d
AK		 1396}
1397
1398static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1399 struct segmented_address addr,
1400 const void *orig_data, const void *data,
1401 unsigned size)
1402{
9fa088f4
AK		 1403 int rc;
1404 ulong linear;
1405
83b8795a 1406 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1407 if (rc != X86EMUL_CONTINUE)
1408 return rc;
0f65dd70
AK		 1409 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1410 size, &ctxt->exception);
3ca3ac4d
AK		 1411}
1412
dde7e6d1 1413static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1414 unsigned int size, unsigned short port,
1415 void *dest)
1416{
9dac77fa 1417 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1418
dde7e6d1 1419 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1420 unsigned int in_page, n;
9dac77fa 1421 unsigned int count = ctxt->rep_prefix ?
dd856efa 1422 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1423 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1424 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1425 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1426 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1427 count);
1428 if (n == 0)
1429 n = 1;
1430 rc->pos = rc->end = 0;
7b105ca2 1431 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1432 return 0;
1433 rc->end = n * size;
6aa8b732
AK		 1434 }
1435
b3356bf0
GN		 1436 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1437 ctxt->dst.data = rc->data + rc->pos;
1438 ctxt->dst.type = OP_MEM_STR;
1439 ctxt->dst.count = (rc->end - rc->pos) / size;
1440 rc->pos = rc->end;
1441 } else {
1442 memcpy(dest, rc->data + rc->pos, size);
1443 rc->pos += size;
1444 }
dde7e6d1
AK		 1445 return 1;
1446}
6aa8b732 1447
7f3d35fd
KW		 1448static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1449 u16 index, struct desc_struct *desc)
1450{
1451 struct desc_ptr dt;
1452 ulong addr;
1453
1454 ctxt->ops->get_idt(ctxt, &dt);
1455
1456 if (dt.size < index * 8 + 7)
1457 return emulate_gp(ctxt, index << 3 | 0x2);
1458
1459 addr = dt.address + index * 8;
1460 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1461 &ctxt->exception);
1462}
1463
dde7e6d1 1464static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1465 u16 selector, struct desc_ptr *dt)
1466{
0225fb50 1467 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1468
dde7e6d1
AK		 1469 if (selector & 1 << 2) {
1470 struct desc_struct desc;
1aa36616
AK		 1471 u16 sel;
1472
dde7e6d1 1473 memset (dt, 0, sizeof *dt);
1aa36616 1474 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1475 return;
e09d082c 1476
dde7e6d1
AK		 1477 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1478 dt->address = get_desc_base(&desc);
1479 } else
4bff1e86 1480 ops->get_gdt(ctxt, dt);
dde7e6d1 1481}
120df890 1482
dde7e6d1
AK		 1483/* allowed just for 8 bytes segments */
1484static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1485 u16 selector, struct desc_struct *desc,
1486 ulong *desc_addr_p)
dde7e6d1
AK		 1487{
1488 struct desc_ptr dt;
1489 u16 index = selector >> 3;
dde7e6d1 1490 ulong addr;
120df890 1491
7b105ca2 1492 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1493
35d3d4a1
AK		 1494 if (dt.size < index * 8 + 7)
1495 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1496
e919464b 1497 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1498 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1499 &ctxt->exception);
dde7e6d1 1500}
ef65c889 1501
dde7e6d1
AK		 1502/* allowed just for 8 bytes segments */
1503static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1504 u16 selector, struct desc_struct *desc)
1505{
1506 struct desc_ptr dt;
1507 u16 index = selector >> 3;
dde7e6d1 1508 ulong addr;
6aa8b732 1509
7b105ca2 1510 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1511
35d3d4a1
AK		 1512 if (dt.size < index * 8 + 7)
1513 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1514
dde7e6d1 1515 addr = dt.address + index * 8;
7b105ca2
TY		 1516 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1517 &ctxt->exception);
dde7e6d1 1518}
c7e75a3d 1519
5601d05b 1520/* Does not support long mode */
dde7e6d1 1521static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1522 u16 selector, int seg)
1523{
869be99c 1524 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1525 u8 dpl, rpl, cpl;
1526 unsigned err_vec = GP_VECTOR;
1527 u32 err_code = 0;
1528 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1529 ulong desc_addr;
dde7e6d1 1530 int ret;
03ebebeb 1531 u16 dummy;
69f55cb1 1532
dde7e6d1 1533 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1534
dde7e6d1
AK		 1535 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1536 || ctxt->mode == X86EMUL_MODE_REAL) {
1537 /* set real mode segment descriptor */
03ebebeb 1538 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1539 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1540 goto load;
1541 }
1542
79d5b4c3
AK		 1543 rpl = selector & 3;
1544 cpl = ctxt->ops->cpl(ctxt);
1545
1546 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1547 if ((seg == VCPU_SREG_CS
1548 || (seg == VCPU_SREG_SS
1549 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1550 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1551 && null_selector)
1552 goto exception;
1553
1554 /* TR should be in GDT only */
1555 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1556 goto exception;
1557
1558 if (null_selector) /* for NULL selector skip all following checks */
1559 goto load;
1560
e919464b 1561 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1562 if (ret != X86EMUL_CONTINUE)
1563 return ret;
1564
1565 err_code = selector & 0xfffc;
1566 err_vec = GP_VECTOR;
1567
fc058680 1568 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1569 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1570 goto exception;
1571
1572 if (!seg_desc.p) {
1573 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1574 goto exception;
1575 }
1576
dde7e6d1 1577 dpl = seg_desc.dpl;
dde7e6d1
AK		 1578
1579 switch (seg) {
1580 case VCPU_SREG_SS:
1581 /*
1582 * segment is not a writable data segment or segment
1583 * selector's RPL != CPL or segment selector's RPL != CPL
1584 */
1585 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1586 goto exception;
6aa8b732 1587 break;
dde7e6d1
AK		 1588 case VCPU_SREG_CS:
1589 if (!(seg_desc.type & 8))
1590 goto exception;
1591
1592 if (seg_desc.type & 4) {
1593 /* conforming */
1594 if (dpl > cpl)
1595 goto exception;
1596 } else {
1597 /* nonconforming */
1598 if (rpl > cpl || dpl != cpl)
1599 goto exception;
1600 }
1601 /* CS(RPL) <- CPL */
1602 selector = (selector & 0xfffc) | cpl;
6aa8b732 1603 break;
dde7e6d1
AK		 1604 case VCPU_SREG_TR:
1605 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1606 goto exception;
869be99c
AK		 1607 old_desc = seg_desc;
1608 seg_desc.type |= 2; /* busy */
1609 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1610 sizeof(seg_desc), &ctxt->exception);
1611 if (ret != X86EMUL_CONTINUE)
1612 return ret;
dde7e6d1
AK		 1613 break;
1614 case VCPU_SREG_LDTR:
1615 if (seg_desc.s || seg_desc.type != 2)
1616 goto exception;
1617 break;
1618 default: /* DS, ES, FS, or GS */
4e62417b 1619 /*
dde7e6d1
AK		 1620 * segment is not a data or readable code segment or
1621 * ((segment is a data or nonconforming code segment)
1622 * and (both RPL and CPL > DPL))
4e62417b 1623 */
dde7e6d1
AK		 1624 if ((seg_desc.type & 0xa) == 0x8 ||
1625 (((seg_desc.type & 0xc) != 0xc) &&
1626 (rpl > dpl && cpl > dpl)))
1627 goto exception;
6aa8b732 1628 break;
dde7e6d1
AK		 1629 }
1630
1631 if (seg_desc.s) {
1632 /* mark segment as accessed */
1633 seg_desc.type |= 1;
7b105ca2 1634 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1635 if (ret != X86EMUL_CONTINUE)
1636 return ret;
1637 }
1638load:
7b105ca2 1639 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1640 return X86EMUL_CONTINUE;
1641exception:
1642 emulate_exception(ctxt, err_vec, err_code, true);
1643 return X86EMUL_PROPAGATE_FAULT;
1644}
1645
31be40b3
WY		 1646static void write_register_operand(struct operand *op)
1647{
1648 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1649 switch (op->bytes) {
1650 case 1:
1651 *(u8 *)op->addr.reg = (u8)op->val;
1652 break;
1653 case 2:
1654 *(u16 *)op->addr.reg = (u16)op->val;
1655 break;
1656 case 4:
1657 *op->addr.reg = (u32)op->val;
1658 break; /* 64b: zero-extend */
1659 case 8:
1660 *op->addr.reg = op->val;
1661 break;
1662 }
1663}
1664
adddcecf 1665static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1666{
1667 int rc;
dde7e6d1 1668
b6744dc3
AK		 1669 if (ctxt->d & NoWrite)
1670 return X86EMUL_CONTINUE;
1671
9dac77fa 1672 switch (ctxt->dst.type) {
dde7e6d1 1673 case OP_REG:
9dac77fa 1674 write_register_operand(&ctxt->dst);
6aa8b732 1675 break;
dde7e6d1 1676 case OP_MEM:
9dac77fa 1677 if (ctxt->lock_prefix)
3ca3ac4d 1678 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1679 ctxt->dst.addr.mem,
1680 &ctxt->dst.orig_val,
1681 &ctxt->dst.val,
1682 ctxt->dst.bytes);
341de7e3 1683 else
3ca3ac4d 1684 rc = segmented_write(ctxt,
9dac77fa
AK		 1685 ctxt->dst.addr.mem,
1686 &ctxt->dst.val,
1687 ctxt->dst.bytes);
dde7e6d1
AK		 1688 if (rc != X86EMUL_CONTINUE)
1689 return rc;
a682e354 1690 break;
b3356bf0
GN		 1691 case OP_MEM_STR:
1692 rc = segmented_write(ctxt,
1693 ctxt->dst.addr.mem,
1694 ctxt->dst.data,
1695 ctxt->dst.bytes * ctxt->dst.count);
1696 if (rc != X86EMUL_CONTINUE)
1697 return rc;
1698 break;
1253791d 1699 case OP_XMM:
9dac77fa 1700 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1701 break;
cbe2c9d3
AK		 1702 case OP_MM:
1703 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1704 break;
dde7e6d1
AK		 1705 case OP_NONE:
1706 /* no writeback */
414e6277 1707 break;
dde7e6d1 1708 default:
414e6277 1709 break;
6aa8b732 1710 }
dde7e6d1
AK		 1711 return X86EMUL_CONTINUE;
1712}
6aa8b732 1713
51ddff50 1714static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1715{
4179bb02 1716 struct segmented_address addr;
0dc8d10f 1717
5ad105e5 1718 rsp_increment(ctxt, -bytes);
dd856efa 1719 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1720 addr.seg = VCPU_SREG_SS;
1721
51ddff50
AK		 1722 return segmented_write(ctxt, addr, data, bytes);
1723}
1724
1725static int em_push(struct x86_emulate_ctxt *ctxt)
1726{
4179bb02 1727 /* Disable writeback. */
9dac77fa 1728 ctxt->dst.type = OP_NONE;
51ddff50 1729 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1730}
69f55cb1 1731
dde7e6d1 1732static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1733 void *dest, int len)
1734{
dde7e6d1 1735 int rc;
90de84f5 1736 struct segmented_address addr;
8b4caf66 1737
dd856efa 1738 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1739 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1740 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1741 if (rc != X86EMUL_CONTINUE)
1742 return rc;
1743
5ad105e5 1744 rsp_increment(ctxt, len);
dde7e6d1 1745 return rc;
8b4caf66
LV		 1746}
1747
c54fe504
TY		 1748static int em_pop(struct x86_emulate_ctxt *ctxt)
1749{
9dac77fa 1750 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1751}
1752
dde7e6d1 1753static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1754 void *dest, int len)
9de41573
GN		 1755{
1756 int rc;
dde7e6d1
AK		 1757 unsigned long val, change_mask;
1758 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1759 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1760
3b9be3bf 1761 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
9de41573 1764
dde7e6d1
AK		 1765 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1766 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1767
dde7e6d1
AK		 1768 switch(ctxt->mode) {
1769 case X86EMUL_MODE_PROT64:
1770 case X86EMUL_MODE_PROT32:
1771 case X86EMUL_MODE_PROT16:
1772 if (cpl == 0)
1773 change_mask |= EFLG_IOPL;
1774 if (cpl <= iopl)
1775 change_mask |= EFLG_IF;
1776 break;
1777 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1778 if (iopl < 3)
1779 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1780 change_mask |= EFLG_IF;
1781 break;
1782 default: /* real mode */
1783 change_mask |= (EFLG_IOPL | EFLG_IF);
1784 break;
9de41573 1785 }
dde7e6d1
AK		 1786
1787 *(unsigned long *)dest =
1788 (ctxt->eflags & ~change_mask) | (val & change_mask);
1789
1790 return rc;
9de41573
GN		 1791}
1792
62aaa2f0
TY		 1793static int em_popf(struct x86_emulate_ctxt *ctxt)
1794{
9dac77fa
AK		 1795 ctxt->dst.type = OP_REG;
1796 ctxt->dst.addr.reg = &ctxt->eflags;
1797 ctxt->dst.bytes = ctxt->op_bytes;
1798 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1799}
1800
612e89f0
AK		 1801static int em_enter(struct x86_emulate_ctxt *ctxt)
1802{
1803 int rc;
1804 unsigned frame_size = ctxt->src.val;
1805 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1806 ulong rbp;
612e89f0
AK		 1807
1808 if (nesting_level)
1809 return X86EMUL_UNHANDLEABLE;
1810
dd856efa
AK		 1811 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1812 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1813 if (rc != X86EMUL_CONTINUE)
1814 return rc;
dd856efa 1815 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1816 stack_mask(ctxt));
dd856efa
AK		 1817 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1818 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1819 stack_mask(ctxt));
1820 return X86EMUL_CONTINUE;
1821}
1822
f47cfa31
AK		 1823static int em_leave(struct x86_emulate_ctxt *ctxt)
1824{
dd856efa 1825 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1826 stack_mask(ctxt));
dd856efa 1827 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1828}
1829
1cd196ea 1830static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1831{
1cd196ea
AK		 1832 int seg = ctxt->src2.val;
1833
9dac77fa 1834 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1835
4487b3b4 1836 return em_push(ctxt);
7b262e90
GN		 1837}
1838
1cd196ea 1839static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1840{
1cd196ea 1841 int seg = ctxt->src2.val;
dde7e6d1
AK		 1842 unsigned long selector;
1843 int rc;
38ba30ba 1844
9dac77fa 1845 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
7b105ca2 1849 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1850 return rc;
38ba30ba
GN		 1851}
1852
b96a7fad 1853static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1854{
dd856efa 1855 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1856 int rc = X86EMUL_CONTINUE;
1857 int reg = VCPU_REGS_RAX;
38ba30ba 1858
dde7e6d1
AK		 1859 while (reg <= VCPU_REGS_RDI) {
1860 (reg == VCPU_REGS_RSP) ?
dd856efa 1861 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1862
4487b3b4 1863 rc = em_push(ctxt);
dde7e6d1
AK		 1864 if (rc != X86EMUL_CONTINUE)
1865 return rc;
38ba30ba 1866
dde7e6d1 1867 ++reg;
38ba30ba 1868 }
38ba30ba 1869
dde7e6d1 1870 return rc;
38ba30ba
GN		 1871}
1872
62aaa2f0
TY		 1873static int em_pushf(struct x86_emulate_ctxt *ctxt)
1874{
9dac77fa 1875 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1876 return em_push(ctxt);
1877}
1878
b96a7fad 1879static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1880{
dde7e6d1
AK		 1881 int rc = X86EMUL_CONTINUE;
1882 int reg = VCPU_REGS_RDI;
38ba30ba 1883
dde7e6d1
AK		 1884 while (reg >= VCPU_REGS_RAX) {
1885 if (reg == VCPU_REGS_RSP) {
5ad105e5 1886 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1887 --reg;
1888 }
38ba30ba 1889
dd856efa 1890 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1891 if (rc != X86EMUL_CONTINUE)
1892 break;
1893 --reg;
38ba30ba 1894 }
dde7e6d1 1895 return rc;
38ba30ba
GN		 1896}
1897
dd856efa 1898static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1899{
0225fb50 1900 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1901 int rc;
6e154e56
MG		 1902 struct desc_ptr dt;
1903 gva_t cs_addr;
1904 gva_t eip_addr;
1905 u16 cs, eip;
6e154e56
MG		 1906
1907 /* TODO: Add limit checks */
9dac77fa 1908 ctxt->src.val = ctxt->eflags;
4487b3b4 1909 rc = em_push(ctxt);
5c56e1cf
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
6e154e56
MG		 1912
1913 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1914
9dac77fa 1915 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1916 rc = em_push(ctxt);
5c56e1cf
AK		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
6e154e56 1919
9dac77fa 1920 ctxt->src.val = ctxt->_eip;
4487b3b4 1921 rc = em_push(ctxt);
5c56e1cf
AK		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
1924
4bff1e86 1925 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1926
1927 eip_addr = dt.address + (irq << 2);
1928 cs_addr = dt.address + (irq << 2) + 2;
1929
0f65dd70 1930 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1931 if (rc != X86EMUL_CONTINUE)
1932 return rc;
1933
0f65dd70 1934 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1935 if (rc != X86EMUL_CONTINUE)
1936 return rc;
1937
7b105ca2 1938 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1939 if (rc != X86EMUL_CONTINUE)
1940 return rc;
1941
9dac77fa 1942 ctxt->_eip = eip;
6e154e56
MG		 1943
1944 return rc;
1945}
1946
dd856efa
AK		 1947int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1948{
1949 int rc;
1950
1951 invalidate_registers(ctxt);
1952 rc = __emulate_int_real(ctxt, irq);
1953 if (rc == X86EMUL_CONTINUE)
1954 writeback_registers(ctxt);
1955 return rc;
1956}
1957
7b105ca2 1958static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1959{
1960 switch(ctxt->mode) {
1961 case X86EMUL_MODE_REAL:
dd856efa 1962 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1963 case X86EMUL_MODE_VM86:
1964 case X86EMUL_MODE_PROT16:
1965 case X86EMUL_MODE_PROT32:
1966 case X86EMUL_MODE_PROT64:
1967 default:
1968 /* Protected mode interrupts unimplemented yet */
1969 return X86EMUL_UNHANDLEABLE;
1970 }
1971}
1972
7b105ca2 1973static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1974{
dde7e6d1
AK		 1975 int rc = X86EMUL_CONTINUE;
1976 unsigned long temp_eip = 0;
1977 unsigned long temp_eflags = 0;
1978 unsigned long cs = 0;
1979 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1980 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1981 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1982 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1983
dde7e6d1 1984 /* TODO: Add stack limit check */
38ba30ba 1985
9dac77fa 1986 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1987
dde7e6d1
AK		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
38ba30ba 1990
35d3d4a1
AK		 1991 if (temp_eip & ~0xffff)
1992 return emulate_gp(ctxt, 0);
38ba30ba 1993
9dac77fa 1994 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1995
dde7e6d1
AK		 1996 if (rc != X86EMUL_CONTINUE)
1997 return rc;
38ba30ba 1998
9dac77fa 1999 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2000
dde7e6d1
AK		 2001 if (rc != X86EMUL_CONTINUE)
2002 return rc;
38ba30ba 2003
7b105ca2 2004 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2005
dde7e6d1
AK		 2006 if (rc != X86EMUL_CONTINUE)
2007 return rc;
38ba30ba 2008
9dac77fa 2009 ctxt->_eip = temp_eip;
38ba30ba 2010
38ba30ba 2011
9dac77fa 2012 if (ctxt->op_bytes == 4)
dde7e6d1 2013 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2014 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2015 ctxt->eflags &= ~0xffff;
2016 ctxt->eflags |= temp_eflags;
38ba30ba 2017 }
dde7e6d1
AK		 2018
2019 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2020 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2021
2022 return rc;
38ba30ba
GN		 2023}
2024
e01991e7 2025static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2026{
dde7e6d1
AK		 2027 switch(ctxt->mode) {
2028 case X86EMUL_MODE_REAL:
7b105ca2 2029 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2030 case X86EMUL_MODE_VM86:
2031 case X86EMUL_MODE_PROT16:
2032 case X86EMUL_MODE_PROT32:
2033 case X86EMUL_MODE_PROT64:
c37eda13 2034 default:
dde7e6d1
AK		 2035 /* iret from protected mode unimplemented yet */
2036 return X86EMUL_UNHANDLEABLE;
c37eda13 2037 }
c37eda13
WY		 2038}
2039
d2f62766
TY		 2040static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2041{
d2f62766
TY		 2042 int rc;
2043 unsigned short sel;
2044
9dac77fa 2045 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2046
7b105ca2 2047 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2048 if (rc != X86EMUL_CONTINUE)
2049 return rc;
2050
9dac77fa
AK		 2051 ctxt->_eip = 0;
2052 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2053 return X86EMUL_CONTINUE;
2054}
2055
45a1467d
AK		 2056FASTOP1(not);
2057FASTOP1(neg);
3329ece1 2058
007a3b54
AK		 2059FASTOP2CL(rol);
2060FASTOP2CL(ror);
2061FASTOP2CL(rcl);
2062FASTOP2CL(rcr);
2063FASTOP2CL(shl);
2064FASTOP2CL(shr);
2065FASTOP2CL(sar);
2066
3329ece1
AK		 2067static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2068{
2069 u8 ex = 0;
2070
2071 emulate_1op_rax_rdx(ctxt, "mul", ex);
2072 return X86EMUL_CONTINUE;
2073}
2074
2075static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2076{
2077 u8 ex = 0;
2078
2079 emulate_1op_rax_rdx(ctxt, "imul", ex);
2080 return X86EMUL_CONTINUE;
2081}
2082
2083static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2084{
34d1f490 2085 u8 de = 0;
8cdbd2c9 2086
3329ece1
AK		 2087 emulate_1op_rax_rdx(ctxt, "div", de);
2088 if (de)
2089 return emulate_de(ctxt);
2090 return X86EMUL_CONTINUE;
2091}
2092
2093static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2094{
2095 u8 de = 0;
2096
2097 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2098 if (de)
2099 return emulate_de(ctxt);
8c5eee30 2100 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2101}
2102
51187683 2103static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2104{
4179bb02 2105 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2106
9dac77fa 2107 switch (ctxt->modrm_reg) {
8cdbd2c9 2108 case 0: /* inc */
d1eef45d 2109 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2110 break;
2111 case 1: /* dec */
d1eef45d 2112 emulate_1op(ctxt, "dec");
8cdbd2c9 2113 break;
d19292e4
MG		 2114 case 2: /* call near abs */ {
2115 long int old_eip;
9dac77fa
AK		 2116 old_eip = ctxt->_eip;
2117 ctxt->_eip = ctxt->src.val;
2118 ctxt->src.val = old_eip;
4487b3b4 2119 rc = em_push(ctxt);
d19292e4
MG		 2120 break;
2121 }
8cdbd2c9 2122 case 4: /* jmp abs */
9dac77fa 2123 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2124 break;
d2f62766
TY		 2125 case 5: /* jmp far */
2126 rc = em_jmp_far(ctxt);
2127 break;
8cdbd2c9 2128 case 6: /* push */
4487b3b4 2129 rc = em_push(ctxt);
8cdbd2c9 2130 break;
8cdbd2c9 2131 }
4179bb02 2132 return rc;
8cdbd2c9
LV		 2133}
2134
e0dac408 2135static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2136{
9dac77fa 2137 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2138
dd856efa
AK		 2139 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2140 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2141 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2142 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2143 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2144 } else {
dd856efa
AK		 2145 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2146 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2147
05f086f8 2148 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2149 }
1b30eaa8 2150 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2151}
2152
ebda02c2
TY		 2153static int em_ret(struct x86_emulate_ctxt *ctxt)
2154{
9dac77fa
AK		 2155 ctxt->dst.type = OP_REG;
2156 ctxt->dst.addr.reg = &ctxt->_eip;
2157 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2158 return em_pop(ctxt);
2159}
2160
e01991e7 2161static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2162{
a77ab5ea
AK		 2163 int rc;
2164 unsigned long cs;
2165
9dac77fa 2166 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2167 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2168 return rc;
9dac77fa
AK		 2169 if (ctxt->op_bytes == 4)
2170 ctxt->_eip = (u32)ctxt->_eip;
2171 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2172 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2173 return rc;
7b105ca2 2174 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2175 return rc;
2176}
2177
e940b5c2
TY		 2178static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2179{
2180 /* Save real source value, then compare EAX against destination. */
2181 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2182 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2183 emulate_2op_SrcV(ctxt, "cmp");
2184
2185 if (ctxt->eflags & EFLG_ZF) {
2186 /* Success: write back to memory. */
2187 ctxt->dst.val = ctxt->src.orig_val;
2188 } else {
2189 /* Failure: write the value we saw to EAX. */
2190 ctxt->dst.type = OP_REG;
dd856efa 2191 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2192 }
2193 return X86EMUL_CONTINUE;
2194}
2195
d4b4325f 2196static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2197{
d4b4325f 2198 int seg = ctxt->src2.val;
09b5f4d3
WY		 2199 unsigned short sel;
2200 int rc;
2201
9dac77fa 2202 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2203
7b105ca2 2204 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2205 if (rc != X86EMUL_CONTINUE)
2206 return rc;
2207
9dac77fa 2208 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2209 return rc;
2210}
2211
7b105ca2 2212static void
e66bb2cc 2213setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2214 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2215{
e66bb2cc 2216 cs->l = 0; /* will be adjusted later */
79168fd1 2217 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2218 cs->g = 1; /* 4kb granularity */
79168fd1 2219 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2220 cs->type = 0x0b; /* Read, Execute, Accessed */
2221 cs->s = 1;
2222 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2223 cs->p = 1;
2224 cs->d = 1;
99245b50 2225 cs->avl = 0;
e66bb2cc 2226
79168fd1
GN		 2227 set_desc_base(ss, 0); /* flat segment */
2228 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2229 ss->g = 1; /* 4kb granularity */
2230 ss->s = 1;
2231 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2232 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2233 ss->dpl = 0;
79168fd1 2234 ss->p = 1;
99245b50
GN		 2235 ss->l = 0;
2236 ss->avl = 0;
e66bb2cc
AP		 2237}
2238
1a18a69b
AK		 2239static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2240{
2241 u32 eax, ebx, ecx, edx;
2242
2243 eax = ecx = 0;
0017f93a
AK		 2244 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2245 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2246 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2247 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2248}
2249
c2226fc9
SB		 2250static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2251{
0225fb50 2252 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2253 u32 eax, ebx, ecx, edx;
2254
2255 /*
2256 * syscall should always be enabled in longmode - so only become
2257 * vendor specific (cpuid) if other modes are active...
2258 */
2259 if (ctxt->mode == X86EMUL_MODE_PROT64)
2260 return true;
2261
2262 eax = 0x00000000;
2263 ecx = 0x00000000;
0017f93a
AK		 2264 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2265 /*
2266 * Intel ("GenuineIntel")
2267 * remark: Intel CPUs only support "syscall" in 64bit
2268 * longmode. Also an 64bit guest with a
2269 * 32bit compat-app running will #UD !! While this
2270 * behaviour can be fixed (by emulating) into AMD
2271 * response - CPUs of AMD can't behave like Intel.
2272 */
2273 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2274 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2275 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2276 return false;
2277
2278 /* AMD ("AuthenticAMD") */
2279 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2280 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2281 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2282 return true;
2283
2284 /* AMD ("AMDisbetter!") */
2285 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2286 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2287 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2288 return true;
c2226fc9
SB		 2289
2290 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2291 return false;
2292}
2293
e01991e7 2294static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2295{
0225fb50 2296 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2297 struct desc_struct cs, ss;
e66bb2cc 2298 u64 msr_data;
79168fd1 2299 u16 cs_sel, ss_sel;
c2ad2bb3 2300 u64 efer = 0;
e66bb2cc
AP		 2301
2302 /* syscall is not available in real mode */
2e901c4c 2303 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2304 ctxt->mode == X86EMUL_MODE_VM86)
2305 return emulate_ud(ctxt);
e66bb2cc 2306
c2226fc9
SB		 2307 if (!(em_syscall_is_enabled(ctxt)))
2308 return emulate_ud(ctxt);
2309
c2ad2bb3 2310 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2311 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2312
c2226fc9
SB		 2313 if (!(efer & EFER_SCE))
2314 return emulate_ud(ctxt);
2315
717746e3 2316 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2317 msr_data >>= 32;
79168fd1
GN		 2318 cs_sel = (u16)(msr_data & 0xfffc);
2319 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2320
c2ad2bb3 2321 if (efer & EFER_LMA) {
79168fd1 2322 cs.d = 0;
e66bb2cc
AP		 2323 cs.l = 1;
2324 }
1aa36616
AK		 2325 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2326 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2327
dd856efa 2328 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2329 if (efer & EFER_LMA) {
e66bb2cc 2330#ifdef CONFIG_X86_64
dd856efa 2331 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2332
717746e3 2333 ops->get_msr(ctxt,
3fb1b5db
GN		 2334 ctxt->mode == X86EMUL_MODE_PROT64 ?
2335 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2336 ctxt->_eip = msr_data;
e66bb2cc 2337
717746e3 2338 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2339 ctxt->eflags &= ~(msr_data | EFLG_RF);
2340#endif
2341 } else {
2342 /* legacy mode */
717746e3 2343 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2344 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2345
2346 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2347 }
2348
e54cfa97 2349 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2350}
2351
e01991e7 2352static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2353{
0225fb50 2354 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2355 struct desc_struct cs, ss;
8c604352 2356 u64 msr_data;
79168fd1 2357 u16 cs_sel, ss_sel;
c2ad2bb3 2358 u64 efer = 0;
8c604352 2359
7b105ca2 2360 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2361 /* inject #GP if in real mode */
35d3d4a1
AK		 2362 if (ctxt->mode == X86EMUL_MODE_REAL)
2363 return emulate_gp(ctxt, 0);
8c604352 2364
1a18a69b
AK		 2365 /*
2366 * Not recognized on AMD in compat mode (but is recognized in legacy
2367 * mode).
2368 */
2369 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2370 && !vendor_intel(ctxt))
2371 return emulate_ud(ctxt);
2372
8c604352
AP		 2373 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2374 * Therefore, we inject an #UD.
2375 */
35d3d4a1
AK		 2376 if (ctxt->mode == X86EMUL_MODE_PROT64)
2377 return emulate_ud(ctxt);
8c604352 2378
7b105ca2 2379 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2380
717746e3 2381 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2382 switch (ctxt->mode) {
2383 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2384 if ((msr_data & 0xfffc) == 0x0)
2385 return emulate_gp(ctxt, 0);
8c604352
AP		 2386 break;
2387 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2388 if (msr_data == 0x0)
2389 return emulate_gp(ctxt, 0);
8c604352 2390 break;
9d1b39a9
GN		 2391 default:
2392 break;
8c604352
AP		 2393 }
2394
2395 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2396 cs_sel = (u16)msr_data;
2397 cs_sel &= ~SELECTOR_RPL_MASK;
2398 ss_sel = cs_sel + 8;
2399 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2400 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2401 cs.d = 0;
8c604352
AP		 2402 cs.l = 1;
2403 }
2404
1aa36616
AK		 2405 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2406 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2407
717746e3 2408 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2409 ctxt->_eip = msr_data;
8c604352 2410
717746e3 2411 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2412 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2413
e54cfa97 2414 return X86EMUL_CONTINUE;
8c604352
AP		 2415}
2416
e01991e7 2417static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2418{
0225fb50 2419 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2420 struct desc_struct cs, ss;
4668f050
AP		 2421 u64 msr_data;
2422 int usermode;
1249b96e 2423 u16 cs_sel = 0, ss_sel = 0;
4668f050 2424
a0044755
GN		 2425 /* inject #GP if in real mode or Virtual 8086 mode */
2426 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2427 ctxt->mode == X86EMUL_MODE_VM86)
2428 return emulate_gp(ctxt, 0);
4668f050 2429
7b105ca2 2430 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2431
9dac77fa 2432 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2433 usermode = X86EMUL_MODE_PROT64;
2434 else
2435 usermode = X86EMUL_MODE_PROT32;
2436
2437 cs.dpl = 3;
2438 ss.dpl = 3;
717746e3 2439 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2440 switch (usermode) {
2441 case X86EMUL_MODE_PROT32:
79168fd1 2442 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2443 if ((msr_data & 0xfffc) == 0x0)
2444 return emulate_gp(ctxt, 0);
79168fd1 2445 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2446 break;
2447 case X86EMUL_MODE_PROT64:
79168fd1 2448 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2449 if (msr_data == 0x0)
2450 return emulate_gp(ctxt, 0);
79168fd1
GN		 2451 ss_sel = cs_sel + 8;
2452 cs.d = 0;
4668f050
AP		 2453 cs.l = 1;
2454 break;
2455 }
79168fd1
GN		 2456 cs_sel |= SELECTOR_RPL_MASK;
2457 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2458
1aa36616
AK		 2459 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2460 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2461
dd856efa
AK		 2462 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2463 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2464
e54cfa97 2465 return X86EMUL_CONTINUE;
4668f050
AP		 2466}
2467
7b105ca2 2468static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2469{
2470 int iopl;
2471 if (ctxt->mode == X86EMUL_MODE_REAL)
2472 return false;
2473 if (ctxt->mode == X86EMUL_MODE_VM86)
2474 return true;
2475 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2476 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2477}
2478
2479static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2480 u16 port, u16 len)
2481{
0225fb50 2482 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2483 struct desc_struct tr_seg;
5601d05b 2484 u32 base3;
f850e2e6 2485 int r;
1aa36616 2486 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2487 unsigned mask = (1 << len) - 1;
5601d05b 2488 unsigned long base;
f850e2e6 2489
1aa36616 2490 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2491 if (!tr_seg.p)
f850e2e6 2492 return false;
79168fd1 2493 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2494 return false;
5601d05b
GN		 2495 base = get_desc_base(&tr_seg);
2496#ifdef CONFIG_X86_64
2497 base |= ((u64)base3) << 32;
2498#endif
0f65dd70 2499 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2500 if (r != X86EMUL_CONTINUE)
2501 return false;
79168fd1 2502 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2503 return false;
0f65dd70 2504 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2505 if (r != X86EMUL_CONTINUE)
2506 return false;
2507 if ((perm >> bit_idx) & mask)
2508 return false;
2509 return true;
2510}
2511
2512static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2513 u16 port, u16 len)
2514{
4fc40f07
GN		 2515 if (ctxt->perm_ok)
2516 return true;
2517
7b105ca2
TY		 2518 if (emulator_bad_iopl(ctxt))
2519 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2520 return false;
4fc40f07
GN		 2521
2522 ctxt->perm_ok = true;
2523
f850e2e6
GN		 2524 return true;
2525}
2526
38ba30ba 2527static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2528 struct tss_segment_16 *tss)
2529{
9dac77fa 2530 tss->ip = ctxt->_eip;
38ba30ba 2531 tss->flag = ctxt->eflags;
dd856efa
AK		 2532 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2533 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2534 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2535 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2536 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2537 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2538 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2539 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2540
1aa36616
AK		 2541 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2542 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2543 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2544 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2545 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2546}
2547
2548static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2549 struct tss_segment_16 *tss)
2550{
38ba30ba
GN		 2551 int ret;
2552
9dac77fa 2553 ctxt->_eip = tss->ip;
38ba30ba 2554 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2555 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2556 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2557 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2558 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2559 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2560 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2561 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2562 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2563
2564 /*
2565 * SDM says that segment selectors are loaded before segment
2566 * descriptors
2567 */
1aa36616
AK		 2568 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2569 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2570 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2571 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2572 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2573
2574 /*
fc058680 2575 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2576 * it is handled in a context of new task
2577 */
7b105ca2 2578 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2579 if (ret != X86EMUL_CONTINUE)
2580 return ret;
7b105ca2 2581 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2582 if (ret != X86EMUL_CONTINUE)
2583 return ret;
7b105ca2 2584 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
7b105ca2 2587 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2588 if (ret != X86EMUL_CONTINUE)
2589 return ret;
7b105ca2 2590 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
2593
2594 return X86EMUL_CONTINUE;
2595}
2596
2597static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2598 u16 tss_selector, u16 old_tss_sel,
2599 ulong old_tss_base, struct desc_struct *new_desc)
2600{
0225fb50 2601 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2602 struct tss_segment_16 tss_seg;
2603 int ret;
bcc55cba 2604 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2605
0f65dd70 2606 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2607 &ctxt->exception);
db297e3d 2608 if (ret != X86EMUL_CONTINUE)
38ba30ba 2609 /* FIXME: need to provide precise fault address */
38ba30ba 2610 return ret;
38ba30ba 2611
7b105ca2 2612 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2613
0f65dd70 2614 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2615 &ctxt->exception);
db297e3d 2616 if (ret != X86EMUL_CONTINUE)
38ba30ba 2617 /* FIXME: need to provide precise fault address */
38ba30ba 2618 return ret;
38ba30ba 2619
0f65dd70 2620 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2621 &ctxt->exception);
db297e3d 2622 if (ret != X86EMUL_CONTINUE)
38ba30ba 2623 /* FIXME: need to provide precise fault address */
38ba30ba 2624 return ret;
38ba30ba
GN		 2625
2626 if (old_tss_sel != 0xffff) {
2627 tss_seg.prev_task_link = old_tss_sel;
2628
0f65dd70 2629 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2630 &tss_seg.prev_task_link,
2631 sizeof tss_seg.prev_task_link,
0f65dd70 2632 &ctxt->exception);
db297e3d 2633 if (ret != X86EMUL_CONTINUE)
38ba30ba 2634 /* FIXME: need to provide precise fault address */
38ba30ba 2635 return ret;
38ba30ba
GN		 2636 }
2637
7b105ca2 2638 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2639}
2640
2641static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2642 struct tss_segment_32 *tss)
2643{
7b105ca2 2644 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2645 tss->eip = ctxt->_eip;
38ba30ba 2646 tss->eflags = ctxt->eflags;
dd856efa
AK		 2647 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2648 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2649 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2650 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2651 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2652 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2653 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2654 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2655
1aa36616
AK		 2656 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2657 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2658 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2659 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2660 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2661 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2662 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2663}
2664
2665static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2666 struct tss_segment_32 *tss)
2667{
38ba30ba
GN		 2668 int ret;
2669
7b105ca2 2670 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2671 return emulate_gp(ctxt, 0);
9dac77fa 2672 ctxt->_eip = tss->eip;
38ba30ba 2673 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2674
2675 /* General purpose registers */
dd856efa
AK		 2676 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2677 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2678 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2679 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2680 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2681 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2682 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2683 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2684
2685 /*
2686 * SDM says that segment selectors are loaded before segment
2687 * descriptors
2688 */
1aa36616
AK		 2689 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2690 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2691 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2692 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2693 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2694 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2695 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2696
4cee4798
KW		 2697 /*
2698 * If we're switching between Protected Mode and VM86, we need to make
2699 * sure to update the mode before loading the segment descriptors so
2700 * that the selectors are interpreted correctly.
2701 *
2702 * Need to get rflags to the vcpu struct immediately because it
2703 * influences the CPL which is checked at least when loading the segment
2704 * descriptors and when pushing an error code to the new kernel stack.
2705 *
2706 * TODO Introduce a separate ctxt->ops->set_cpl callback
2707 */
2708 if (ctxt->eflags & X86_EFLAGS_VM)
2709 ctxt->mode = X86EMUL_MODE_VM86;
2710 else
2711 ctxt->mode = X86EMUL_MODE_PROT32;
2712
2713 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2714
38ba30ba
GN		 2715 /*
2716 * Now load segment descriptors. If fault happenes at this stage
2717 * it is handled in a context of new task
2718 */
7b105ca2 2719 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2720 if (ret != X86EMUL_CONTINUE)
2721 return ret;
7b105ca2 2722 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2723 if (ret != X86EMUL_CONTINUE)
2724 return ret;
7b105ca2 2725 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
7b105ca2 2728 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2729 if (ret != X86EMUL_CONTINUE)
2730 return ret;
7b105ca2 2731 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2732 if (ret != X86EMUL_CONTINUE)
2733 return ret;
7b105ca2 2734 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
7b105ca2 2737 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2738 if (ret != X86EMUL_CONTINUE)
2739 return ret;
2740
2741 return X86EMUL_CONTINUE;
2742}
2743
2744static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2745 u16 tss_selector, u16 old_tss_sel,
2746 ulong old_tss_base, struct desc_struct *new_desc)
2747{
0225fb50 2748 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2749 struct tss_segment_32 tss_seg;
2750 int ret;
bcc55cba 2751 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2752
0f65dd70 2753 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2754 &ctxt->exception);
db297e3d 2755 if (ret != X86EMUL_CONTINUE)
38ba30ba 2756 /* FIXME: need to provide precise fault address */
38ba30ba 2757 return ret;
38ba30ba 2758
7b105ca2 2759 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2760
0f65dd70 2761 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2762 &ctxt->exception);
db297e3d 2763 if (ret != X86EMUL_CONTINUE)
38ba30ba 2764 /* FIXME: need to provide precise fault address */
38ba30ba 2765 return ret;
38ba30ba 2766
0f65dd70 2767 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2768 &ctxt->exception);
db297e3d 2769 if (ret != X86EMUL_CONTINUE)
38ba30ba 2770 /* FIXME: need to provide precise fault address */
38ba30ba 2771 return ret;
38ba30ba
GN		 2772
2773 if (old_tss_sel != 0xffff) {
2774 tss_seg.prev_task_link = old_tss_sel;
2775
0f65dd70 2776 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2777 &tss_seg.prev_task_link,
2778 sizeof tss_seg.prev_task_link,
0f65dd70 2779 &ctxt->exception);
db297e3d 2780 if (ret != X86EMUL_CONTINUE)
38ba30ba 2781 /* FIXME: need to provide precise fault address */
38ba30ba 2782 return ret;
38ba30ba
GN		 2783 }
2784
7b105ca2 2785 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2786}
2787
2788static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2789 u16 tss_selector, int idt_index, int reason,
e269fb21 2790 bool has_error_code, u32 error_code)
38ba30ba 2791{
0225fb50 2792 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2793 struct desc_struct curr_tss_desc, next_tss_desc;
2794 int ret;
1aa36616 2795 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2796 ulong old_tss_base =
4bff1e86 2797 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2798 u32 desc_limit;
e919464b 2799 ulong desc_addr;
38ba30ba
GN		 2800
2801 /* FIXME: old_tss_base == ~0 ? */
2802
e919464b 2803 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2804 if (ret != X86EMUL_CONTINUE)
2805 return ret;
e919464b 2806 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2807 if (ret != X86EMUL_CONTINUE)
2808 return ret;
2809
2810 /* FIXME: check that next_tss_desc is tss */
2811
7f3d35fd
KW		 2812 /*
2813 * Check privileges. The three cases are task switch caused by...
2814 *
2815 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2816 * 2. Exception/IRQ/iret: No check is performed
fc058680 2817 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2818 */
2819 if (reason == TASK_SWITCH_GATE) {
2820 if (idt_index != -1) {
2821 /* Software interrupts */
2822 struct desc_struct task_gate_desc;
2823 int dpl;
2824
2825 ret = read_interrupt_descriptor(ctxt, idt_index,
2826 &task_gate_desc);
2827 if (ret != X86EMUL_CONTINUE)
2828 return ret;
2829
2830 dpl = task_gate_desc.dpl;
2831 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2832 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2833 }
2834 } else if (reason != TASK_SWITCH_IRET) {
2835 int dpl = next_tss_desc.dpl;
2836 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2837 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2838 }
2839
7f3d35fd 2840
ceffb459
GN		 2841 desc_limit = desc_limit_scaled(&next_tss_desc);
2842 if (!next_tss_desc.p ||
2843 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2844 desc_limit < 0x2b)) {
54b8486f 2845 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2846 return X86EMUL_PROPAGATE_FAULT;
2847 }
2848
2849 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2850 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2851 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2852 }
2853
2854 if (reason == TASK_SWITCH_IRET)
2855 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2856
2857 /* set back link to prev task only if NT bit is set in eflags
fc058680 2858 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2859 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2860 old_tss_sel = 0xffff;
2861
2862 if (next_tss_desc.type & 8)
7b105ca2 2863 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2864 old_tss_base, &next_tss_desc);
2865 else
7b105ca2 2866 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2867 old_tss_base, &next_tss_desc);
0760d448
JK		 2868 if (ret != X86EMUL_CONTINUE)
2869 return ret;
38ba30ba
GN		 2870
2871 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2872 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2873
2874 if (reason != TASK_SWITCH_IRET) {
2875 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2876 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2877 }
2878
717746e3 2879 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2880 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2881
e269fb21 2882 if (has_error_code) {
9dac77fa
AK		 2883 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2884 ctxt->lock_prefix = 0;
2885 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2886 ret = em_push(ctxt);
e269fb21
JK		 2887 }
2888
38ba30ba
GN		 2889 return ret;
2890}
2891
2892int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2893 u16 tss_selector, int idt_index, int reason,
e269fb21 2894 bool has_error_code, u32 error_code)
38ba30ba 2895{
38ba30ba
GN		 2896 int rc;
2897
dd856efa 2898 invalidate_registers(ctxt);
9dac77fa
AK		 2899 ctxt->_eip = ctxt->eip;
2900 ctxt->dst.type = OP_NONE;
38ba30ba 2901
7f3d35fd 2902 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2903 has_error_code, error_code);
38ba30ba 2904
dd856efa 2905 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2906 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2907 writeback_registers(ctxt);
2908 }
38ba30ba 2909
a0c0ab2f 2910 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2911}
2912
f3bd64c6
GN		 2913static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2914 struct operand *op)
a682e354 2915{
b3356bf0 2916 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2917
dd856efa
AK		 2918 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2919 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2920}
2921
7af04fc0
AK		 2922static int em_das(struct x86_emulate_ctxt *ctxt)
2923{
7af04fc0
AK		 2924 u8 al, old_al;
2925 bool af, cf, old_cf;
2926
2927 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2928 al = ctxt->dst.val;
7af04fc0
AK		 2929
2930 old_al = al;
2931 old_cf = cf;
2932 cf = false;
2933 af = ctxt->eflags & X86_EFLAGS_AF;
2934 if ((al & 0x0f) > 9 || af) {
2935 al -= 6;
2936 cf = old_cf | (al >= 250);
2937 af = true;
2938 } else {
2939 af = false;
2940 }
2941 if (old_al > 0x99 || old_cf) {
2942 al -= 0x60;
2943 cf = true;
2944 }
2945
9dac77fa 2946 ctxt->dst.val = al;
7af04fc0 2947 /* Set PF, ZF, SF */
9dac77fa
AK		 2948 ctxt->src.type = OP_IMM;
2949 ctxt->src.val = 0;
2950 ctxt->src.bytes = 1;
a31b9cea 2951 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2952 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2953 if (cf)
2954 ctxt->eflags |= X86_EFLAGS_CF;
2955 if (af)
2956 ctxt->eflags |= X86_EFLAGS_AF;
2957 return X86EMUL_CONTINUE;
2958}
2959
7f662273
GN		 2960static int em_aad(struct x86_emulate_ctxt *ctxt)
2961{
2962 u8 al = ctxt->dst.val & 0xff;
2963 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2964
2965 al = (al + (ah * ctxt->src.val)) & 0xff;
2966
2967 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2968
2969 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2970
2971 if (!al)
2972 ctxt->eflags |= X86_EFLAGS_ZF;
2973 if (!(al & 1))
2974 ctxt->eflags |= X86_EFLAGS_PF;
2975 if (al & 0x80)
2976 ctxt->eflags |= X86_EFLAGS_SF;
2977
2978 return X86EMUL_CONTINUE;
2979}
2980
d4ddafcd
TY		 2981static int em_call(struct x86_emulate_ctxt *ctxt)
2982{
2983 long rel = ctxt->src.val;
2984
2985 ctxt->src.val = (unsigned long)ctxt->_eip;
2986 jmp_rel(ctxt, rel);
2987 return em_push(ctxt);
2988}
2989
0ef753b8
AK		 2990static int em_call_far(struct x86_emulate_ctxt *ctxt)
2991{
0ef753b8
AK		 2992 u16 sel, old_cs;
2993 ulong old_eip;
2994 int rc;
2995
1aa36616 2996 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2997 old_eip = ctxt->_eip;
0ef753b8 2998
9dac77fa 2999 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3000 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3001 return X86EMUL_CONTINUE;
3002
9dac77fa
AK		 3003 ctxt->_eip = 0;
3004 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3005
9dac77fa 3006 ctxt->src.val = old_cs;
4487b3b4 3007 rc = em_push(ctxt);
0ef753b8
AK		 3008 if (rc != X86EMUL_CONTINUE)
3009 return rc;
3010
9dac77fa 3011 ctxt->src.val = old_eip;
4487b3b4 3012 return em_push(ctxt);
0ef753b8
AK		 3013}
3014
40ece7c7
AK		 3015static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3016{
40ece7c7
AK		 3017 int rc;
3018
9dac77fa
AK		 3019 ctxt->dst.type = OP_REG;
3020 ctxt->dst.addr.reg = &ctxt->_eip;
3021 ctxt->dst.bytes = ctxt->op_bytes;
3022 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3023 if (rc != X86EMUL_CONTINUE)
3024 return rc;
5ad105e5 3025 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3026 return X86EMUL_CONTINUE;
3027}
3028
fb864fbc
AK		 3029FASTOP2(add);
3030FASTOP2(or);
3031FASTOP2(adc);
3032FASTOP2(sbb);
3033FASTOP2(and);
3034FASTOP2(sub);
3035FASTOP2(xor);
3036FASTOP2(cmp);
3037FASTOP2(test);
9f21ca59 3038
0bdea068
AK		 3039FASTOP3WCL(shld);
3040FASTOP3WCL(shrd);
3041
e4f973ae
TY		 3042static int em_xchg(struct x86_emulate_ctxt *ctxt)
3043{
e4f973ae 3044 /* Write back the register source. */
9dac77fa
AK		 3045 ctxt->src.val = ctxt->dst.val;
3046 write_register_operand(&ctxt->src);
e4f973ae
TY		 3047
3048 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3049 ctxt->dst.val = ctxt->src.orig_val;
3050 ctxt->lock_prefix = 1;
e4f973ae
TY		 3051 return X86EMUL_CONTINUE;
3052}
3053
5c82aa29 3054static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 3055{
a31b9cea 3056 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 3057 return X86EMUL_CONTINUE;
3058}
3059
5c82aa29
AK		 3060static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3061{
9dac77fa 3062 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3063 return em_imul(ctxt);
3064}
3065
61429142
AK		 3066static int em_cwd(struct x86_emulate_ctxt *ctxt)
3067{
9dac77fa
AK		 3068 ctxt->dst.type = OP_REG;
3069 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3070 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3071 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3072
3073 return X86EMUL_CONTINUE;
3074}
3075
48bb5d3c
AK		 3076static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3077{
48bb5d3c
AK		 3078 u64 tsc = 0;
3079
717746e3 3080 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3081 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3082 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3083 return X86EMUL_CONTINUE;
3084}
3085
222d21aa
AK		 3086static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3087{
3088 u64 pmc;
3089
dd856efa 3090 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3091 return emulate_gp(ctxt, 0);
dd856efa
AK		 3092 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3093 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3094 return X86EMUL_CONTINUE;
3095}
3096
b9eac5f4
AK		 3097static int em_mov(struct x86_emulate_ctxt *ctxt)
3098{
49597d81 3099 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3100 return X86EMUL_CONTINUE;
3101}
3102
bc00f8d2
TY		 3103static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3104{
3105 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3106 return emulate_gp(ctxt, 0);
3107
3108 /* Disable writeback. */
3109 ctxt->dst.type = OP_NONE;
3110 return X86EMUL_CONTINUE;
3111}
3112
3113static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3114{
3115 unsigned long val;
3116
3117 if (ctxt->mode == X86EMUL_MODE_PROT64)
3118 val = ctxt->src.val & ~0ULL;
3119 else
3120 val = ctxt->src.val & ~0U;
3121
3122 /* #UD condition is already handled. */
3123 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3124 return emulate_gp(ctxt, 0);
3125
3126 /* Disable writeback. */
3127 ctxt->dst.type = OP_NONE;
3128 return X86EMUL_CONTINUE;
3129}
3130
e1e210b0
TY		 3131static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3132{
3133 u64 msr_data;
3134
dd856efa
AK		 3135 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3136 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3137 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3138 return emulate_gp(ctxt, 0);
3139
3140 return X86EMUL_CONTINUE;
3141}
3142
3143static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3144{
3145 u64 msr_data;
3146
dd856efa 3147 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3148 return emulate_gp(ctxt, 0);
3149
dd856efa
AK		 3150 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3151 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3152 return X86EMUL_CONTINUE;
3153}
3154
1bd5f469
TY		 3155static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3156{
9dac77fa 3157 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3158 return emulate_ud(ctxt);
3159
9dac77fa 3160 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3161 return X86EMUL_CONTINUE;
3162}
3163
3164static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3165{
9dac77fa 3166 u16 sel = ctxt->src.val;
1bd5f469 3167
9dac77fa 3168 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3169 return emulate_ud(ctxt);
3170
9dac77fa 3171 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3172 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3173
3174 /* Disable writeback. */
9dac77fa
AK		 3175 ctxt->dst.type = OP_NONE;
3176 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3177}
3178
a14e579f
AK		 3179static int em_lldt(struct x86_emulate_ctxt *ctxt)
3180{
3181 u16 sel = ctxt->src.val;
3182
3183 /* Disable writeback. */
3184 ctxt->dst.type = OP_NONE;
3185 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3186}
3187
80890006
AK		 3188static int em_ltr(struct x86_emulate_ctxt *ctxt)
3189{
3190 u16 sel = ctxt->src.val;
3191
3192 /* Disable writeback. */
3193 ctxt->dst.type = OP_NONE;
3194 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3195}
3196
38503911
AK		 3197static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3198{
9fa088f4
AK		 3199 int rc;
3200 ulong linear;
3201
9dac77fa 3202 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3203 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3204 ctxt->ops->invlpg(ctxt, linear);
38503911 3205 /* Disable writeback. */
9dac77fa 3206 ctxt->dst.type = OP_NONE;
38503911
AK		 3207 return X86EMUL_CONTINUE;
3208}
3209
2d04a05b
AK		 3210static int em_clts(struct x86_emulate_ctxt *ctxt)
3211{
3212 ulong cr0;
3213
3214 cr0 = ctxt->ops->get_cr(ctxt, 0);
3215 cr0 &= ~X86_CR0_TS;
3216 ctxt->ops->set_cr(ctxt, 0, cr0);
3217 return X86EMUL_CONTINUE;
3218}
3219
26d05cc7
AK		 3220static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3221{
26d05cc7
AK		 3222 int rc;
3223
9dac77fa 3224 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3225 return X86EMUL_UNHANDLEABLE;
3226
3227 rc = ctxt->ops->fix_hypercall(ctxt);
3228 if (rc != X86EMUL_CONTINUE)
3229 return rc;
3230
3231 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3232 ctxt->_eip = ctxt->eip;
26d05cc7 3233 /* Disable writeback. */
9dac77fa 3234 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3235 return X86EMUL_CONTINUE;
3236}
3237
96051572
AK		 3238static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3239 void (*get)(struct x86_emulate_ctxt *ctxt,
3240 struct desc_ptr *ptr))
3241{
3242 struct desc_ptr desc_ptr;
3243
3244 if (ctxt->mode == X86EMUL_MODE_PROT64)
3245 ctxt->op_bytes = 8;
3246 get(ctxt, &desc_ptr);
3247 if (ctxt->op_bytes == 2) {
3248 ctxt->op_bytes = 4;
3249 desc_ptr.address &= 0x00ffffff;
3250 }
3251 /* Disable writeback. */
3252 ctxt->dst.type = OP_NONE;
3253 return segmented_write(ctxt, ctxt->dst.addr.mem,
3254 &desc_ptr, 2 + ctxt->op_bytes);
3255}
3256
3257static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3258{
3259 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3260}
3261
3262static int em_sidt(struct x86_emulate_ctxt *ctxt)
3263{
3264 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3265}
3266
26d05cc7
AK		 3267static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3268{
26d05cc7
AK		 3269 struct desc_ptr desc_ptr;
3270 int rc;
3271
510425ff
AK		 3272 if (ctxt->mode == X86EMUL_MODE_PROT64)
3273 ctxt->op_bytes = 8;
9dac77fa 3274 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3275 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3276 ctxt->op_bytes);
26d05cc7
AK		 3277 if (rc != X86EMUL_CONTINUE)
3278 return rc;
3279 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3280 /* Disable writeback. */
9dac77fa 3281 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3282 return X86EMUL_CONTINUE;
3283}
3284
5ef39c71 3285static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3286{
26d05cc7
AK		 3287 int rc;
3288
5ef39c71
AK		 3289 rc = ctxt->ops->fix_hypercall(ctxt);
3290
26d05cc7 3291 /* Disable writeback. */
9dac77fa 3292 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3293 return rc;
3294}
3295
3296static int em_lidt(struct x86_emulate_ctxt *ctxt)
3297{
26d05cc7
AK		 3298 struct desc_ptr desc_ptr;
3299 int rc;
3300
510425ff
AK		 3301 if (ctxt->mode == X86EMUL_MODE_PROT64)
3302 ctxt->op_bytes = 8;
9dac77fa 3303 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3304 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3305 ctxt->op_bytes);
26d05cc7
AK		 3306 if (rc != X86EMUL_CONTINUE)
3307 return rc;
3308 ctxt->ops->set_idt(ctxt, &desc_ptr);
3309 /* Disable writeback. */
9dac77fa 3310 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3311 return X86EMUL_CONTINUE;
3312}
3313
3314static int em_smsw(struct x86_emulate_ctxt *ctxt)
3315{
9dac77fa
AK		 3316 ctxt->dst.bytes = 2;
3317 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3318 return X86EMUL_CONTINUE;
3319}
3320
3321static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3322{
26d05cc7 3323 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3324 | (ctxt->src.val & 0x0f));
3325 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3326 return X86EMUL_CONTINUE;
3327}
3328
d06e03ad
TY		 3329static int em_loop(struct x86_emulate_ctxt *ctxt)
3330{
dd856efa
AK		 3331 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3332 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3333 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3334 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3335
3336 return X86EMUL_CONTINUE;
3337}
3338
3339static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3340{
dd856efa 3341 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3342 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3343
3344 return X86EMUL_CONTINUE;
3345}
3346
d7841a4b
TY		 3347static int em_in(struct x86_emulate_ctxt *ctxt)
3348{
3349 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3350 &ctxt->dst.val))
3351 return X86EMUL_IO_NEEDED;
3352
3353 return X86EMUL_CONTINUE;
3354}
3355
3356static int em_out(struct x86_emulate_ctxt *ctxt)
3357{
3358 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3359 &ctxt->src.val, 1);
3360 /* Disable writeback. */
3361 ctxt->dst.type = OP_NONE;
3362 return X86EMUL_CONTINUE;
3363}
3364
f411e6cd
TY		 3365static int em_cli(struct x86_emulate_ctxt *ctxt)
3366{
3367 if (emulator_bad_iopl(ctxt))
3368 return emulate_gp(ctxt, 0);
3369
3370 ctxt->eflags &= ~X86_EFLAGS_IF;
3371 return X86EMUL_CONTINUE;
3372}
3373
3374static int em_sti(struct x86_emulate_ctxt *ctxt)
3375{
3376 if (emulator_bad_iopl(ctxt))
3377 return emulate_gp(ctxt, 0);
3378
3379 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3380 ctxt->eflags |= X86_EFLAGS_IF;
3381 return X86EMUL_CONTINUE;
3382}
3383
ce7faab2
TY		 3384static int em_bt(struct x86_emulate_ctxt *ctxt)
3385{
3386 /* Disable writeback. */
3387 ctxt->dst.type = OP_NONE;
3388 /* only subword offset */
3389 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3390
3391 emulate_2op_SrcV_nobyte(ctxt, "bt");
3392 return X86EMUL_CONTINUE;
3393}
3394
3395static int em_bts(struct x86_emulate_ctxt *ctxt)
3396{
3397 emulate_2op_SrcV_nobyte(ctxt, "bts");
3398 return X86EMUL_CONTINUE;
3399}
3400
3401static int em_btr(struct x86_emulate_ctxt *ctxt)
3402{
3403 emulate_2op_SrcV_nobyte(ctxt, "btr");
3404 return X86EMUL_CONTINUE;
3405}
3406
3407static int em_btc(struct x86_emulate_ctxt *ctxt)
3408{
3409 emulate_2op_SrcV_nobyte(ctxt, "btc");
3410 return X86EMUL_CONTINUE;
3411}
3412
ff227392
TY		 3413static int em_bsf(struct x86_emulate_ctxt *ctxt)
3414{
d54e4237 3415 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3416 return X86EMUL_CONTINUE;
3417}
3418
3419static int em_bsr(struct x86_emulate_ctxt *ctxt)
3420{
d54e4237 3421 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3422 return X86EMUL_CONTINUE;
3423}
3424
6d6eede4
AK		 3425static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3426{
3427 u32 eax, ebx, ecx, edx;
3428
dd856efa
AK		 3429 eax = reg_read(ctxt, VCPU_REGS_RAX);
3430 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3431 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3432 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3433 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3434 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3435 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3436 return X86EMUL_CONTINUE;
3437}
3438
2dd7caa0
AK		 3439static int em_lahf(struct x86_emulate_ctxt *ctxt)
3440{
dd856efa
AK		 3441 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3442 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3443 return X86EMUL_CONTINUE;
3444}
3445
9299836e
AK		 3446static int em_bswap(struct x86_emulate_ctxt *ctxt)
3447{
3448 switch (ctxt->op_bytes) {
3449#ifdef CONFIG_X86_64
3450 case 8:
3451 asm("bswap %0" : "+r"(ctxt->dst.val));
3452 break;
3453#endif
3454 default:
3455 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3456 break;
3457 }
3458 return X86EMUL_CONTINUE;
3459}
3460
cfec82cb
JR		 3461static bool valid_cr(int nr)
3462{
3463 switch (nr) {
3464 case 0:
3465 case 2 ... 4:
3466 case 8:
3467 return true;
3468 default:
3469 return false;
3470 }
3471}
3472
3473static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3474{
9dac77fa 3475 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3476 return emulate_ud(ctxt);
3477
3478 return X86EMUL_CONTINUE;
3479}
3480
3481static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3482{
9dac77fa
AK		 3483 u64 new_val = ctxt->src.val64;
3484 int cr = ctxt->modrm_reg;
c2ad2bb3 3485 u64 efer = 0;
cfec82cb
JR		 3486
3487 static u64 cr_reserved_bits[] = {
3488 0xffffffff00000000ULL,
3489 0, 0, 0, /* CR3 checked later */
3490 CR4_RESERVED_BITS,
3491 0, 0, 0,
3492 CR8_RESERVED_BITS,
3493 };
3494
3495 if (!valid_cr(cr))
3496 return emulate_ud(ctxt);
3497
3498 if (new_val & cr_reserved_bits[cr])
3499 return emulate_gp(ctxt, 0);
3500
3501 switch (cr) {
3502 case 0: {
c2ad2bb3 3503 u64 cr4;
cfec82cb
JR		 3504 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3505 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3506 return emulate_gp(ctxt, 0);
3507
717746e3
AK		 3508 cr4 = ctxt->ops->get_cr(ctxt, 4);
3509 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3510
3511 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3512 !(cr4 & X86_CR4_PAE))
3513 return emulate_gp(ctxt, 0);
3514
3515 break;
3516 }
3517 case 3: {
3518 u64 rsvd = 0;
3519
c2ad2bb3
AK		 3520 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3521 if (efer & EFER_LMA)
cfec82cb 3522 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3523 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3524 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3525 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3526 rsvd = CR3_NONPAE_RESERVED_BITS;
3527
3528 if (new_val & rsvd)
3529 return emulate_gp(ctxt, 0);
3530
3531 break;
3532 }
3533 case 4: {
717746e3 3534 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3535
3536 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3537 return emulate_gp(ctxt, 0);
3538
3539 break;
3540 }
3541 }
3542
3543 return X86EMUL_CONTINUE;
3544}
3545
3b88e41a
JR		 3546static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3547{
3548 unsigned long dr7;
3549
717746e3 3550 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3551
3552 /* Check if DR7.Global_Enable is set */
3553 return dr7 & (1 << 13);
3554}
3555
3556static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3557{
9dac77fa 3558 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3559 u64 cr4;
3560
3561 if (dr > 7)
3562 return emulate_ud(ctxt);
3563
717746e3 3564 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3565 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3566 return emulate_ud(ctxt);
3567
3568 if (check_dr7_gd(ctxt))
3569 return emulate_db(ctxt);
3570
3571 return X86EMUL_CONTINUE;
3572}
3573
3574static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3575{
9dac77fa
AK		 3576 u64 new_val = ctxt->src.val64;
3577 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3578
3579 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3580 return emulate_gp(ctxt, 0);
3581
3582 return check_dr_read(ctxt);
3583}
3584
01de8b09
JR		 3585static int check_svme(struct x86_emulate_ctxt *ctxt)
3586{
3587 u64 efer;
3588
717746e3 3589 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3590
3591 if (!(efer & EFER_SVME))
3592 return emulate_ud(ctxt);
3593
3594 return X86EMUL_CONTINUE;
3595}
3596
3597static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3598{
dd856efa 3599 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3600
3601 /* Valid physical address? */
d4224449 3602 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3603 return emulate_gp(ctxt, 0);
3604
3605 return check_svme(ctxt);
3606}
3607
d7eb8203
JR		 3608static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3609{
717746e3 3610 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3611
717746e3 3612 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3613 return emulate_ud(ctxt);
3614
3615 return X86EMUL_CONTINUE;
3616}
3617
8061252e
JR		 3618static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3619{
717746e3 3620 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3621 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3622
717746e3 3623 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3624 (rcx > 3))
3625 return emulate_gp(ctxt, 0);
3626
3627 return X86EMUL_CONTINUE;
3628}
3629
f6511935
JR		 3630static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3631{
9dac77fa
AK		 3632 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3633 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3634 return emulate_gp(ctxt, 0);
3635
3636 return X86EMUL_CONTINUE;
3637}
3638
3639static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3640{
9dac77fa
AK		 3641 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3642 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3643 return emulate_gp(ctxt, 0);
3644
3645 return X86EMUL_CONTINUE;
3646}
3647
73fba5f4 3648#define D(_y) { .flags = (_y) }
c4f035c6 3649#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3650#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3651 .check_perm = (_p) }
73fba5f4 3652#define N D(0)
01de8b09 3653#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3654#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3655#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3656#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3657#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3658#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3659#define II(_f, _e, _i) \
3660 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3661#define IIP(_f, _e, _i, _p) \
3662 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3663 .check_perm = (_p) }
aa97bb48 3664#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3665
8d8f4e9f 3666#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3667#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3668#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3669#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3670#define I2bvIP(_f, _e, _i, _p) \
3671 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3672
fb864fbc
AK		 3673#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3674 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3675 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3676
fd0a0d82 3677static const struct opcode group7_rm1[] = {
1c2545be
TY		 3678 DI(SrcNone | Priv, monitor),
3679 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3680 N, N, N, N, N, N,
3681};
3682
fd0a0d82 3683static const struct opcode group7_rm3[] = {
1c2545be
TY		 3684 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3685 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3686 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3687 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3688 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3689 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3690 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3691 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3692};
6230f7fc 3693
fd0a0d82 3694static const struct opcode group7_rm7[] = {
d7eb8203 3695 N,
1c2545be 3696 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3697 N, N, N, N, N, N,
3698};
d67fc27a 3699
fd0a0d82 3700static const struct opcode group1[] = {
fb864fbc
AK		 3701 F(Lock, em_add),
3702 F(Lock | PageTable, em_or),
3703 F(Lock, em_adc),
3704 F(Lock, em_sbb),
3705 F(Lock | PageTable, em_and),
3706 F(Lock, em_sub),
3707 F(Lock, em_xor),
3708 F(NoWrite, em_cmp),
73fba5f4
AK		 3709};
3710
fd0a0d82 3711static const struct opcode group1A[] = {
1c2545be 3712 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3713};
3714
007a3b54
AK		 3715static const struct opcode group2[] = {
3716 F(DstMem | ModRM, em_rol),
3717 F(DstMem | ModRM, em_ror),
3718 F(DstMem | ModRM, em_rcl),
3719 F(DstMem | ModRM, em_rcr),
3720 F(DstMem | ModRM, em_shl),
3721 F(DstMem | ModRM, em_shr),
3722 F(DstMem | ModRM, em_shl),
3723 F(DstMem | ModRM, em_sar),
3724};
3725
fd0a0d82 3726static const struct opcode group3[] = {
fb864fbc
AK		 3727 F(DstMem | SrcImm | NoWrite, em_test),
3728 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3729 F(DstMem | SrcNone | Lock, em_not),
3730 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3731 I(SrcMem, em_mul_ex),
3732 I(SrcMem, em_imul_ex),
3733 I(SrcMem, em_div_ex),
3734 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3735};
3736
fd0a0d82 3737static const struct opcode group4[] = {
1c2545be
TY		 3738 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3739 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3740 N, N, N, N, N, N,
3741};
3742
fd0a0d82 3743static const struct opcode group5[] = {
1c2545be
TY		 3744 I(DstMem | SrcNone | Lock, em_grp45),
3745 I(DstMem | SrcNone | Lock, em_grp45),
3746 I(SrcMem | Stack, em_grp45),
3747 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3748 I(SrcMem | Stack, em_grp45),
3749 I(SrcMemFAddr | ImplicitOps, em_grp45),
3750 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3751};
3752
fd0a0d82 3753static const struct opcode group6[] = {
1c2545be
TY		 3754 DI(Prot, sldt),
3755 DI(Prot, str),
a14e579f 3756 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3757 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3758 N, N, N, N,
3759};
3760
fd0a0d82 3761static const struct group_dual group7 = { {
96051572
AK		 3762 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3763 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3764 II(SrcMem | Priv, em_lgdt, lgdt),
3765 II(SrcMem | Priv, em_lidt, lidt),
3766 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3767 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3768 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3769}, {
1c2545be 3770 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3771 EXT(0, group7_rm1),
01de8b09 3772 N, EXT(0, group7_rm3),
1c2545be
TY		 3773 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3774 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3775 EXT(0, group7_rm7),
73fba5f4
AK		 3776} };
3777
fd0a0d82 3778static const struct opcode group8[] = {
73fba5f4 3779 N, N, N, N,
1c2545be
TY		 3780 I(DstMem | SrcImmByte, em_bt),
3781 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3782 I(DstMem | SrcImmByte | Lock, em_btr),
3783 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3784};
3785
fd0a0d82 3786static const struct group_dual group9 = { {
1c2545be 3787 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3788}, {
3789 N, N, N, N, N, N, N, N,
3790} };
3791
fd0a0d82 3792static const struct opcode group11[] = {
1c2545be 3793 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3794 X7(D(Undefined)),
a4d4a7c1
AK		 3795};
3796
fd0a0d82 3797static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3798 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3799};
3800
fd0a0d82 3801static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3802 I(0, em_mov), N, N, N,
3803};
3804
045a282c
GN		 3805static const struct escape escape_d9 = { {
3806 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3807}, {
3808 /* 0xC0 - 0xC7 */
3809 N, N, N, N, N, N, N, N,
3810 /* 0xC8 - 0xCF */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xD0 - 0xC7 */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xD8 - 0xDF */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xE0 - 0xE7 */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xE8 - 0xEF */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xF0 - 0xF7 */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xF8 - 0xFF */
3823 N, N, N, N, N, N, N, N,
3824} };
3825
3826static const struct escape escape_db = { {
3827 N, N, N, N, N, N, N, N,
3828}, {
3829 /* 0xC0 - 0xC7 */
3830 N, N, N, N, N, N, N, N,
3831 /* 0xC8 - 0xCF */
3832 N, N, N, N, N, N, N, N,
3833 /* 0xD0 - 0xC7 */
3834 N, N, N, N, N, N, N, N,
3835 /* 0xD8 - 0xDF */
3836 N, N, N, N, N, N, N, N,
3837 /* 0xE0 - 0xE7 */
3838 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3839 /* 0xE8 - 0xEF */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xF0 - 0xF7 */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xF8 - 0xFF */
3844 N, N, N, N, N, N, N, N,
3845} };
3846
3847static const struct escape escape_dd = { {
3848 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3849}, {
3850 /* 0xC0 - 0xC7 */
3851 N, N, N, N, N, N, N, N,
3852 /* 0xC8 - 0xCF */
3853 N, N, N, N, N, N, N, N,
3854 /* 0xD0 - 0xC7 */
3855 N, N, N, N, N, N, N, N,
3856 /* 0xD8 - 0xDF */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xE0 - 0xE7 */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xE8 - 0xEF */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xF0 - 0xF7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xF8 - 0xFF */
3865 N, N, N, N, N, N, N, N,
3866} };
3867
fd0a0d82 3868static const struct opcode opcode_table[256] = {
73fba5f4 3869 /* 0x00 - 0x07 */
fb864fbc 3870 F6ALU(Lock, em_add),
1cd196ea
AK		 3871 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3872 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3873 /* 0x08 - 0x0F */
fb864fbc 3874 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3875 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3876 N,
73fba5f4 3877 /* 0x10 - 0x17 */
fb864fbc 3878 F6ALU(Lock, em_adc),
1cd196ea
AK		 3879 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3880 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3881 /* 0x18 - 0x1F */
fb864fbc 3882 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3883 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3884 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3885 /* 0x20 - 0x27 */
fb864fbc 3886 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3887 /* 0x28 - 0x2F */
fb864fbc 3888 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3889 /* 0x30 - 0x37 */
fb864fbc 3890 F6ALU(Lock, em_xor), N, N,
73fba5f4 3891 /* 0x38 - 0x3F */
fb864fbc 3892 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4
AK		 3893 /* 0x40 - 0x4F */
3894 X16(D(DstReg)),
3895 /* 0x50 - 0x57 */
63540382 3896 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3897 /* 0x58 - 0x5F */
c54fe504 3898 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3899 /* 0x60 - 0x67 */
b96a7fad
TY		 3900 I(ImplicitOps | Stack | No64, em_pusha),
3901 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3902 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3903 N, N, N, N,
3904 /* 0x68 - 0x6F */
d46164db
AK		 3905 I(SrcImm | Mov | Stack, em_push),
3906 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3907 I(SrcImmByte | Mov | Stack, em_push),
3908 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3909 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3910 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3911 /* 0x70 - 0x7F */
3912 X16(D(SrcImmByte)),
3913 /* 0x80 - 0x87 */
1c2545be
TY		 3914 G(ByteOp | DstMem | SrcImm, group1),
3915 G(DstMem | SrcImm, group1),
3916 G(ByteOp | DstMem | SrcImm | No64, group1),
3917 G(DstMem | SrcImmByte, group1),
fb864fbc 3918 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3919 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3920 /* 0x88 - 0x8F */
d5ae7ce8 3921 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3922 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3923 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3924 D(ModRM | SrcMem | NoAccess | DstReg),
3925 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3926 G(0, group1A),
73fba5f4 3927 /* 0x90 - 0x97 */
bf608f88 3928 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3929 /* 0x98 - 0x9F */
61429142 3930 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3931 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3932 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3933 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3934 /* 0xA0 - 0xA7 */
b9eac5f4 3935 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3936 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3937 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3938 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3939 /* 0xA8 - 0xAF */
fb864fbc 3940 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3941 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3942 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3943 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3944 /* 0xB0 - 0xB7 */
b9eac5f4 3945 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3946 /* 0xB8 - 0xBF */
5e2c6883 3947 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3948 /* 0xC0 - 0xC7 */
007a3b54 3949 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3950 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3951 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3952 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3953 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3954 G(ByteOp, group11), G(0, group11),
73fba5f4 3955 /* 0xC8 - 0xCF */
612e89f0
AK		 3956 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3957 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3958 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3959 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3960 /* 0xD0 - 0xD7 */
007a3b54
AK		 3961 G(Src2One | ByteOp, group2), G(Src2One, group2),
3962 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
7f662273 3963 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3964 /* 0xD8 - 0xDF */
045a282c 3965 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3966 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3967 X3(I(SrcImmByte, em_loop)),
3968 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3969 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3970 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3971 /* 0xE8 - 0xEF */
d4ddafcd 3972 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3973 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3974 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3975 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3976 /* 0xF0 - 0xF7 */
bf608f88 3977 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3978 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3979 G(ByteOp, group3), G(0, group3),
73fba5f4 3980 /* 0xF8 - 0xFF */
f411e6cd
TY		 3981 D(ImplicitOps), D(ImplicitOps),
3982 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3983 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3984};
3985
fd0a0d82 3986static const struct opcode twobyte_table[256] = {
73fba5f4 3987 /* 0x00 - 0x0F */
dee6bb70 3988 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3989 N, I(ImplicitOps | VendorSpecific, em_syscall),
3990 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3991 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3992 N, D(ImplicitOps | ModRM), N, N,
3993 /* 0x10 - 0x1F */
3994 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3995 /* 0x20 - 0x2F */
cfec82cb 3996 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3997 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3998 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3999 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4000 N, N, N, N,
3e114eb4
AK		 4001 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4002 N, N, N, N,
73fba5f4 4003 /* 0x30 - 0x3F */
e1e210b0 4004 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4005 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4006 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4007 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4008 I(ImplicitOps | VendorSpecific, em_sysenter),
4009 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4010 N, N,
73fba5f4
AK		 4011 N, N, N, N, N, N, N, N,
4012 /* 0x40 - 0x4F */
4013 X16(D(DstReg | SrcMem | ModRM | Mov)),
4014 /* 0x50 - 0x5F */
4015 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4016 /* 0x60 - 0x6F */
aa97bb48
AK		 4017 N, N, N, N,
4018 N, N, N, N,
4019 N, N, N, N,
4020 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4021 /* 0x70 - 0x7F */
aa97bb48
AK		 4022 N, N, N, N,
4023 N, N, N, N,
4024 N, N, N, N,
4025 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4026 /* 0x80 - 0x8F */
4027 X16(D(SrcImm)),
4028 /* 0x90 - 0x9F */
ee45b58e 4029 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4030 /* 0xA0 - 0xA7 */
1cd196ea 4031 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 4032 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
0bdea068
AK		 4033 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4034 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4035 /* 0xA8 - 0xAF */
1cd196ea 4036 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4037 DI(ImplicitOps, rsm),
ce7faab2 4038 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4039 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4040 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
5c82aa29 4041 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4042 /* 0xB0 - 0xB7 */
e940b5c2 4043 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4044 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 4045 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4046 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4047 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4048 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4049 /* 0xB8 - 0xBF */
4050 N, N,
ce7faab2
TY		 4051 G(BitOp, group8),
4052 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 4053 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4054 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4055 /* 0xC0 - 0xC7 */
739ae406 4056 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4057 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4058 N, N, N, GD(0, &group9),
9299836e
AK		 4059 /* 0xC8 - 0xCF */
4060 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4061 /* 0xD0 - 0xDF */
4062 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4063 /* 0xE0 - 0xEF */
4064 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4065 /* 0xF0 - 0xFF */
4066 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4067};
4068
4069#undef D
4070#undef N
4071#undef G
4072#undef GD
4073#undef I
aa97bb48 4074#undef GP
01de8b09 4075#undef EXT
73fba5f4 4076
8d8f4e9f 4077#undef D2bv
f6511935 4078#undef D2bvIP
8d8f4e9f 4079#undef I2bv
d7841a4b 4080#undef I2bvIP
d67fc27a 4081#undef I6ALU
8d8f4e9f 4082
9dac77fa 4083static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4084{
4085 unsigned size;
4086
9dac77fa 4087 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4088 if (size == 8)
4089 size = 4;
4090 return size;
4091}
4092
4093static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4094 unsigned size, bool sign_extension)
4095{
39f21ee5
AK		 4096 int rc = X86EMUL_CONTINUE;
4097
4098 op->type = OP_IMM;
4099 op->bytes = size;
9dac77fa 4100 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4101 /* NB. Immediates are sign-extended as necessary. */
4102 switch (op->bytes) {
4103 case 1:
e85a1085 4104 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4105 break;
4106 case 2:
e85a1085 4107 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4108 break;
4109 case 4:
e85a1085 4110 op->val = insn_fetch(s32, ctxt);
39f21ee5 4111 break;
5e2c6883
NA		 4112 case 8:
4113 op->val = insn_fetch(s64, ctxt);
4114 break;
39f21ee5
AK		 4115 }
4116 if (!sign_extension) {
4117 switch (op->bytes) {
4118 case 1:
4119 op->val &= 0xff;
4120 break;
4121 case 2:
4122 op->val &= 0xffff;
4123 break;
4124 case 4:
4125 op->val &= 0xffffffff;
4126 break;
4127 }
4128 }
4129done:
4130 return rc;
4131}
4132
a9945549
AK		 4133static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4134 unsigned d)
4135{
4136 int rc = X86EMUL_CONTINUE;
4137
4138 switch (d) {
4139 case OpReg:
2adb5ad9 4140 decode_register_operand(ctxt, op);
a9945549
AK		 4141 break;
4142 case OpImmUByte:
608aabe3 4143 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4144 break;
4145 case OpMem:
41ddf978 4146 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4147 mem_common:
4148 *op = ctxt->memop;
4149 ctxt->memopp = op;
4150 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4151 fetch_bit_operand(ctxt);
4152 op->orig_val = op->val;
4153 break;
41ddf978
AK		 4154 case OpMem64:
4155 ctxt->memop.bytes = 8;
4156 goto mem_common;
a9945549
AK		 4157 case OpAcc:
4158 op->type = OP_REG;
4159 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4160 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4161 fetch_register_operand(op);
4162 op->orig_val = op->val;
4163 break;
4164 case OpDI:
4165 op->type = OP_MEM;
4166 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4167 op->addr.mem.ea =
dd856efa 4168 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4169 op->addr.mem.seg = VCPU_SREG_ES;
4170 op->val = 0;
b3356bf0 4171 op->count = 1;
a9945549
AK		 4172 break;
4173 case OpDX:
4174 op->type = OP_REG;
4175 op->bytes = 2;
dd856efa 4176 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4177 fetch_register_operand(op);
4178 break;
4dd6a57d
AK		 4179 case OpCL:
4180 op->bytes = 1;
dd856efa 4181 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4182 break;
4183 case OpImmByte:
4184 rc = decode_imm(ctxt, op, 1, true);
4185 break;
4186 case OpOne:
4187 op->bytes = 1;
4188 op->val = 1;
4189 break;
4190 case OpImm:
4191 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4192 break;
5e2c6883
NA		 4193 case OpImm64:
4194 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4195 break;
28867cee
AK		 4196 case OpMem8:
4197 ctxt->memop.bytes = 1;
4198 goto mem_common;
0fe59128
AK		 4199 case OpMem16:
4200 ctxt->memop.bytes = 2;
4201 goto mem_common;
4202 case OpMem32:
4203 ctxt->memop.bytes = 4;
4204 goto mem_common;
4205 case OpImmU16:
4206 rc = decode_imm(ctxt, op, 2, false);
4207 break;
4208 case OpImmU:
4209 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4210 break;
4211 case OpSI:
4212 op->type = OP_MEM;
4213 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4214 op->addr.mem.ea =
dd856efa 4215 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4216 op->addr.mem.seg = seg_override(ctxt);
4217 op->val = 0;
b3356bf0 4218 op->count = 1;
0fe59128
AK		 4219 break;
4220 case OpImmFAddr:
4221 op->type = OP_IMM;
4222 op->addr.mem.ea = ctxt->_eip;
4223 op->bytes = ctxt->op_bytes + 2;
4224 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4225 break;
4226 case OpMemFAddr:
4227 ctxt->memop.bytes = ctxt->op_bytes + 2;
4228 goto mem_common;
c191a7a0
AK		 4229 case OpES:
4230 op->val = VCPU_SREG_ES;
4231 break;
4232 case OpCS:
4233 op->val = VCPU_SREG_CS;
4234 break;
4235 case OpSS:
4236 op->val = VCPU_SREG_SS;
4237 break;
4238 case OpDS:
4239 op->val = VCPU_SREG_DS;
4240 break;
4241 case OpFS:
4242 op->val = VCPU_SREG_FS;
4243 break;
4244 case OpGS:
4245 op->val = VCPU_SREG_GS;
4246 break;
a9945549
AK		 4247 case OpImplicit:
4248 /* Special instructions do their own operand decoding. */
4249 default:
4250 op->type = OP_NONE; /* Disable writeback. */
4251 break;
4252 }
4253
4254done:
4255 return rc;
4256}
4257
ef5d75cc 4258int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4259{
dde7e6d1
AK		 4260 int rc = X86EMUL_CONTINUE;
4261 int mode = ctxt->mode;
46561646 4262 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4263 bool op_prefix = false;
46561646 4264 struct opcode opcode;
dde7e6d1 4265
f09ed83e
AK		 4266 ctxt->memop.type = OP_NONE;
4267 ctxt->memopp = NULL;
9dac77fa
AK		 4268 ctxt->_eip = ctxt->eip;
4269 ctxt->fetch.start = ctxt->_eip;
4270 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4271 if (insn_len > 0)
9dac77fa 4272 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4273
4274 switch (mode) {
4275 case X86EMUL_MODE_REAL:
4276 case X86EMUL_MODE_VM86:
4277 case X86EMUL_MODE_PROT16:
4278 def_op_bytes = def_ad_bytes = 2;
4279 break;
4280 case X86EMUL_MODE_PROT32:
4281 def_op_bytes = def_ad_bytes = 4;
4282 break;
4283#ifdef CONFIG_X86_64
4284 case X86EMUL_MODE_PROT64:
4285 def_op_bytes = 4;
4286 def_ad_bytes = 8;
4287 break;
4288#endif
4289 default:
1d2887e2 4290 return EMULATION_FAILED;
dde7e6d1
AK		 4291 }
4292
9dac77fa
AK		 4293 ctxt->op_bytes = def_op_bytes;
4294 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4295
4296 /* Legacy prefixes. */
4297 for (;;) {
e85a1085 4298 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4299 case 0x66: /* operand-size override */
0d7cdee8 4300 op_prefix = true;
dde7e6d1 4301 /* switch between 2/4 bytes */
9dac77fa 4302 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4303 break;
4304 case 0x67: /* address-size override */
4305 if (mode == X86EMUL_MODE_PROT64)
4306 /* switch between 4/8 bytes */
9dac77fa 4307 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4308 else
4309 /* switch between 2/4 bytes */
9dac77fa 4310 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4311 break;
4312 case 0x26: /* ES override */
4313 case 0x2e: /* CS override */
4314 case 0x36: /* SS override */
4315 case 0x3e: /* DS override */
9dac77fa 4316 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4317 break;
4318 case 0x64: /* FS override */
4319 case 0x65: /* GS override */
9dac77fa 4320 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4321 break;
4322 case 0x40 ... 0x4f: /* REX */
4323 if (mode != X86EMUL_MODE_PROT64)
4324 goto done_prefixes;
9dac77fa 4325 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4326 continue;
4327 case 0xf0: /* LOCK */
9dac77fa 4328 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4329 break;
4330 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4331 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4332 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4333 break;
4334 default:
4335 goto done_prefixes;
4336 }
4337
4338 /* Any legacy prefix after a REX prefix nullifies its effect. */
4339
9dac77fa 4340 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4341 }
4342
4343done_prefixes:
4344
4345 /* REX prefix. */
9dac77fa
AK		 4346 if (ctxt->rex_prefix & 8)
4347 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4348
4349 /* Opcode byte(s). */
9dac77fa 4350 opcode = opcode_table[ctxt->b];
d3ad6243 4351 /* Two-byte opcode? */
9dac77fa
AK		 4352 if (ctxt->b == 0x0f) {
4353 ctxt->twobyte = 1;
e85a1085 4354 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4355 opcode = twobyte_table[ctxt->b];
dde7e6d1 4356 }
9dac77fa 4357 ctxt->d = opcode.flags;
dde7e6d1 4358
9f4260e7
TY		 4359 if (ctxt->d & ModRM)
4360 ctxt->modrm = insn_fetch(u8, ctxt);
4361
9dac77fa
AK		 4362 while (ctxt->d & GroupMask) {
4363 switch (ctxt->d & GroupMask) {
46561646 4364 case Group:
9dac77fa 4365 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4366 opcode = opcode.u.group[goffset];
4367 break;
4368 case GroupDual:
9dac77fa
AK		 4369 goffset = (ctxt->modrm >> 3) & 7;
4370 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4371 opcode = opcode.u.gdual->mod3[goffset];
4372 else
4373 opcode = opcode.u.gdual->mod012[goffset];
4374 break;
4375 case RMExt:
9dac77fa 4376 goffset = ctxt->modrm & 7;
01de8b09 4377 opcode = opcode.u.group[goffset];
46561646
AK		 4378 break;
4379 case Prefix:
9dac77fa 4380 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4381 return EMULATION_FAILED;
9dac77fa 4382 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4383 switch (simd_prefix) {
4384 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4385 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4386 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4387 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4388 }
4389 break;
045a282c
GN		 4390 case Escape:
4391 if (ctxt->modrm > 0xbf)
4392 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4393 else
4394 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4395 break;
46561646 4396 default:
1d2887e2 4397 return EMULATION_FAILED;
0d7cdee8 4398 }
46561646 4399
b1ea50b2 4400 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4401 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4402 }
4403
9dac77fa
AK		 4404 ctxt->execute = opcode.u.execute;
4405 ctxt->check_perm = opcode.check_perm;
4406 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4407
4408 /* Unrecognised? */
9dac77fa 4409 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4410 return EMULATION_FAILED;
dde7e6d1 4411
9dac77fa 4412 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4413 return EMULATION_FAILED;
d867162c 4414
9dac77fa
AK		 4415 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4416 ctxt->op_bytes = 8;
dde7e6d1 4417
9dac77fa 4418 if (ctxt->d & Op3264) {
7f9b4b75 4419 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4420 ctxt->op_bytes = 8;
7f9b4b75 4421 else
9dac77fa 4422 ctxt->op_bytes = 4;
7f9b4b75
AK		 4423 }
4424
9dac77fa
AK		 4425 if (ctxt->d & Sse)
4426 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4427 else if (ctxt->d & Mmx)
4428 ctxt->op_bytes = 8;
1253791d 4429
dde7e6d1 4430 /* ModRM and SIB bytes. */
9dac77fa 4431 if (ctxt->d & ModRM) {
f09ed83e 4432 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4433 if (!ctxt->has_seg_override)
4434 set_seg_override(ctxt, ctxt->modrm_seg);
4435 } else if (ctxt->d & MemAbs)
f09ed83e 4436 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4437 if (rc != X86EMUL_CONTINUE)
4438 goto done;
4439
9dac77fa
AK		 4440 if (!ctxt->has_seg_override)
4441 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4442
f09ed83e 4443 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4444
f09ed83e
AK		 4445 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4446 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4447
dde7e6d1
AK		 4448 /*
4449 * Decode and fetch the source operand: register, memory
4450 * or immediate.
4451 */
0fe59128 4452 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4453 if (rc != X86EMUL_CONTINUE)
4454 goto done;
4455
dde7e6d1
AK		 4456 /*
4457 * Decode and fetch the second source operand: register, memory
4458 * or immediate.
4459 */
4dd6a57d 4460 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4461 if (rc != X86EMUL_CONTINUE)
4462 goto done;
4463
dde7e6d1 4464 /* Decode and fetch the destination operand: register or memory. */
a9945549 4465 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4466
4467done:
f09ed83e
AK		 4468 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4469 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4470
1d2887e2 4471 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4472}
4473
1cb3f3ae
XG		 4474bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4475{
4476 return ctxt->d & PageTable;
4477}
4478
3e2f65d5
GN		 4479static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4480{
3e2f65d5
GN		 4481 /* The second termination condition only applies for REPE
4482 * and REPNE. Test if the repeat string operation prefix is
4483 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4484 * corresponding termination condition according to:
4485 * - if REPE/REPZ and ZF = 0 then done
4486 * - if REPNE/REPNZ and ZF = 1 then done
4487 */
9dac77fa
AK		 4488 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4489 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4490 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4491 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4492 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4493 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4494 return true;
4495
4496 return false;
4497}
4498
cbe2c9d3
AK		 4499static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4500{
4501 bool fault = false;
4502
4503 ctxt->ops->get_fpu(ctxt);
4504 asm volatile("1: fwait \n\t"
4505 "2: \n\t"
4506 ".pushsection .fixup,\"ax\" \n\t"
4507 "3: \n\t"
4508 "movb $1, %[fault] \n\t"
4509 "jmp 2b \n\t"
4510 ".popsection \n\t"
4511 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4512 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4513 ctxt->ops->put_fpu(ctxt);
4514
4515 if (unlikely(fault))
4516 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4517
4518 return X86EMUL_CONTINUE;
4519}
4520
4521static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4522 struct operand *op)
4523{
4524 if (op->type == OP_MM)
4525 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4526}
4527
e28bbd44
AK		 4528static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4529{
4530 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4531 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4532 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4533 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4534 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4535 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4536 return X86EMUL_CONTINUE;
4537}
dd856efa 4538
7b105ca2 4539int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4540{
0225fb50 4541 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4542 int rc = X86EMUL_CONTINUE;
9dac77fa 4543 int saved_dst_type = ctxt->dst.type;
8b4caf66 4544
9dac77fa 4545 ctxt->mem_read.pos = 0;
310b5d30 4546
9dac77fa 4547 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4548 rc = emulate_ud(ctxt);
1161624f
GN		 4549 goto done;
4550 }
4551
d380a5e4 4552 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4553 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4554 rc = emulate_ud(ctxt);
d380a5e4
GN		 4555 goto done;
4556 }
4557
9dac77fa 4558 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4559 rc = emulate_ud(ctxt);
081bca0e
AK		 4560 goto done;
4561 }
4562
cbe2c9d3
AK		 4563 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4564 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4565 rc = emulate_ud(ctxt);
4566 goto done;
4567 }
4568
cbe2c9d3 4569 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4570 rc = emulate_nm(ctxt);
4571 goto done;
4572 }
4573
cbe2c9d3
AK		 4574 if (ctxt->d & Mmx) {
4575 rc = flush_pending_x87_faults(ctxt);
4576 if (rc != X86EMUL_CONTINUE)
4577 goto done;
4578 /*
4579 * Now that we know the fpu is exception safe, we can fetch
4580 * operands from it.
4581 */
4582 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4583 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4584 if (!(ctxt->d & Mov))
4585 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4586 }
4587
9dac77fa
AK		 4588 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4589 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4590 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593 }
4594
e92805ac 4595 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4596 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4597 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4598 goto done;
4599 }
4600
8ea7d6ae 4601 /* Instruction can only be executed in protected mode */
9d1b39a9 4602 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4603 rc = emulate_ud(ctxt);
4604 goto done;
4605 }
4606
d09beabd 4607 /* Do instruction specific permission checks */
9dac77fa
AK		 4608 if (ctxt->check_perm) {
4609 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4610 if (rc != X86EMUL_CONTINUE)
4611 goto done;
4612 }
4613
9dac77fa
AK		 4614 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4615 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4616 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4617 if (rc != X86EMUL_CONTINUE)
4618 goto done;
4619 }
4620
9dac77fa 4621 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4622 /* All REP prefixes have the same first termination condition */
dd856efa 4623 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4624 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4625 goto done;
4626 }
b9fa9d6b
AK		 4627 }
4628
9dac77fa
AK		 4629 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4630 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4631 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4632 if (rc != X86EMUL_CONTINUE)
8b4caf66 4633 goto done;
9dac77fa 4634 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4635 }
4636
9dac77fa
AK		 4637 if (ctxt->src2.type == OP_MEM) {
4638 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4639 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4640 if (rc != X86EMUL_CONTINUE)
4641 goto done;
4642 }
4643
9dac77fa 4644 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4645 goto special_insn;
4646
4647
9dac77fa 4648 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4649 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4650 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4651 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4652 if (rc != X86EMUL_CONTINUE)
4653 goto done;
038e51de 4654 }
9dac77fa 4655 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4656
018a98db
AK		 4657special_insn:
4658
9dac77fa
AK		 4659 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4660 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4661 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4662 if (rc != X86EMUL_CONTINUE)
4663 goto done;
4664 }
4665
9dac77fa 4666 if (ctxt->execute) {
e28bbd44
AK		 4667 if (ctxt->d & Fastop) {
4668 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4669 rc = fastop(ctxt, fop);
4670 if (rc != X86EMUL_CONTINUE)
4671 goto done;
4672 goto writeback;
4673 }
9dac77fa 4674 rc = ctxt->execute(ctxt);
ef65c889
AK		 4675 if (rc != X86EMUL_CONTINUE)
4676 goto done;
4677 goto writeback;
4678 }
4679
9dac77fa 4680 if (ctxt->twobyte)
6aa8b732
AK		 4681 goto twobyte_insn;
4682
9dac77fa 4683 switch (ctxt->b) {
33615aa9 4684 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4685 emulate_1op(ctxt, "inc");
33615aa9
AK		 4686 break;
4687 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4688 emulate_1op(ctxt, "dec");
33615aa9 4689 break;
6aa8b732 4690 case 0x63: /* movsxd */
8b4caf66 4691 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4692 goto cannot_emulate;
9dac77fa 4693 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4694 break;
b2833e3c 4695 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4696 if (test_cc(ctxt->b, ctxt->eflags))
4697 jmp_rel(ctxt, ctxt->src.val);
018a98db 4698 break;
7e0b54b1 4699 case 0x8d: /* lea r16/r32, m */
9dac77fa 4700 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4701 break;
3d9e77df 4702 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4703 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4704 break;
e4f973ae
TY		 4705 rc = em_xchg(ctxt);
4706 break;
e8b6fa70 4707 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4708 switch (ctxt->op_bytes) {
4709 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4710 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4711 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4712 }
4713 break;
6e154e56 4714 case 0xcc: /* int3 */
5c5df76b
TY		 4715 rc = emulate_int(ctxt, 3);
4716 break;
6e154e56 4717 case 0xcd: /* int n */
9dac77fa 4718 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4719 break;
4720 case 0xce: /* into */
5c5df76b
TY		 4721 if (ctxt->eflags & EFLG_OF)
4722 rc = emulate_int(ctxt, 4);
6e154e56 4723 break;
1a52e051 4724 case 0xe9: /* jmp rel */
db5b0762 4725 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4726 jmp_rel(ctxt, ctxt->src.val);
4727 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4728 break;
111de5d6 4729 case 0xf4: /* hlt */
6c3287f7 4730 ctxt->ops->halt(ctxt);
19fdfa0d 4731 break;
111de5d6
AK		 4732 case 0xf5: /* cmc */
4733 /* complement carry flag from eflags reg */
4734 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4735 break;
4736 case 0xf8: /* clc */
4737 ctxt->eflags &= ~EFLG_CF;
111de5d6 4738 break;
8744aa9a
MG		 4739 case 0xf9: /* stc */
4740 ctxt->eflags |= EFLG_CF;
4741 break;
fb4616f4
MG		 4742 case 0xfc: /* cld */
4743 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4744 break;
4745 case 0xfd: /* std */
4746 ctxt->eflags |= EFLG_DF;
fb4616f4 4747 break;
91269b8f
AK		 4748 default:
4749 goto cannot_emulate;
6aa8b732 4750 }
018a98db 4751
7d9ddaed
AK		 4752 if (rc != X86EMUL_CONTINUE)
4753 goto done;
4754
018a98db 4755writeback:
adddcecf 4756 rc = writeback(ctxt);
1b30eaa8 4757 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4758 goto done;
4759
5cd21917
GN		 4760 /*
4761 * restore dst type in case the decoding will be reused
4762 * (happens for string instruction )
4763 */
9dac77fa 4764 ctxt->dst.type = saved_dst_type;
5cd21917 4765
9dac77fa 4766 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4767 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4768
9dac77fa 4769 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4770 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4771
9dac77fa 4772 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4773 unsigned int count;
9dac77fa 4774 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4775 if ((ctxt->d & SrcMask) == SrcSI)
4776 count = ctxt->src.count;
4777 else
4778 count = ctxt->dst.count;
4779 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4780 -count);
3e2f65d5 4781
d2ddd1c4
GN		 4782 if (!string_insn_completed(ctxt)) {
4783 /*
4784 * Re-enter guest when pio read ahead buffer is empty
4785 * or, if it is not used, after each 1024 iteration.
4786 */
dd856efa 4787 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4788 (r->end == 0 || r->end != r->pos)) {
4789 /*
4790 * Reset read cache. Usually happens before
4791 * decode, but since instruction is restarted
4792 * we have to do it here.
4793 */
9dac77fa 4794 ctxt->mem_read.end = 0;
dd856efa 4795 writeback_registers(ctxt);
d2ddd1c4
GN		 4796 return EMULATION_RESTART;
4797 }
4798 goto done; /* skip rip writeback */
0fa6ccbd 4799 }
5cd21917 4800 }
d2ddd1c4 4801
9dac77fa 4802 ctxt->eip = ctxt->_eip;
018a98db
AK		 4803
4804done:
da9cb575
AK		 4805 if (rc == X86EMUL_PROPAGATE_FAULT)
4806 ctxt->have_exception = true;
775fde86
JR		 4807 if (rc == X86EMUL_INTERCEPTED)
4808 return EMULATION_INTERCEPTED;
4809
dd856efa
AK		 4810 if (rc == X86EMUL_CONTINUE)
4811 writeback_registers(ctxt);
4812
d2ddd1c4 4813 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4814
4815twobyte_insn:
9dac77fa 4816 switch (ctxt->b) {
018a98db 4817 case 0x09: /* wbinvd */
cfb22375 4818 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4819 break;
4820 case 0x08: /* invd */
018a98db
AK		 4821 case 0x0d: /* GrpP (prefetch) */
4822 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4823 break;
4824 case 0x20: /* mov cr, reg */
9dac77fa 4825 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4826 break;
6aa8b732 4827 case 0x21: /* mov from dr to reg */
9dac77fa 4828 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4829 break;
6aa8b732 4830 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4831 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4832 if (!test_cc(ctxt->b, ctxt->eflags))
4833 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4834 break;
b2833e3c 4835 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4836 if (test_cc(ctxt->b, ctxt->eflags))
4837 jmp_rel(ctxt, ctxt->src.val);
018a98db 4838 break;
ee45b58e 4839 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4840 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4841 break;
2a7c5b8b
GC		 4842 case 0xae: /* clflush */
4843 break;
6aa8b732 4844 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4845 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4846 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4847 : (u16) ctxt->src.val;
6aa8b732 4848 break;
6aa8b732 4849 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4850 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4851 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4852 (s16) ctxt->src.val;
6aa8b732 4853 break;
92f738a5 4854 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4855 emulate_2op_SrcV(ctxt, "add");
92f738a5 4856 /* Write back the register source. */
9dac77fa
AK		 4857 ctxt->src.val = ctxt->dst.orig_val;
4858 write_register_operand(&ctxt->src);
92f738a5 4859 break;
a012e65a 4860 case 0xc3: /* movnti */
9dac77fa
AK		 4861 ctxt->dst.bytes = ctxt->op_bytes;
4862 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4863 (u64) ctxt->src.val;
a012e65a 4864 break;
91269b8f
AK		 4865 default:
4866 goto cannot_emulate;
6aa8b732 4867 }
7d9ddaed
AK		 4868
4869 if (rc != X86EMUL_CONTINUE)
4870 goto done;
4871
6aa8b732
AK		 4872 goto writeback;
4873
4874cannot_emulate:
a0c0ab2f 4875 return EMULATION_FAILED;
6aa8b732 4876}
dd856efa
AK		 4877
4878void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4879{
4880 invalidate_registers(ctxt);
4881}
4882
4883void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4884{
4885 writeback_registers(ctxt);
4886}
Linux kernel - Deliverables
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