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KVM guest: make kvm_para_available() check hypervisor bit reading cpuid leaf
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
9dac77fa 436static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 437{
9dac77fa 438 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 439}
440
6aa8b732 441/* Access/update address held in a register, based on addressing mode. */
e4706772 442static inline unsigned long
9dac77fa 443address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 444{
9dac77fa 445 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 446 return reg;
447 else
9dac77fa 448 return reg & ad_mask(ctxt);
e4706772
HH		 449}
450
451static inline unsigned long
9dac77fa 452register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 453{
9dac77fa 454 return address_mask(ctxt, reg);
e4706772
HH		 455}
456
7a957275 457static inline void
9dac77fa 458register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 459{
9dac77fa 460 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 461 *reg += inc;
462 else
9dac77fa 463 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 464}
6aa8b732 465
9dac77fa 466static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 467{
9dac77fa 468 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 469}
098c937b 470
56697687
AK		 471static u32 desc_limit_scaled(struct desc_struct *desc)
472{
473 u32 limit = get_desc_limit(desc);
474
475 return desc->g ? (limit << 12) | 0xfff : limit;
476}
477
9dac77fa 478static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 479{
9dac77fa
AK		 480 ctxt->has_seg_override = true;
481 ctxt->seg_override = seg;
7a5b56df
AK		 482}
483
7b105ca2 484static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 485{
486 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
487 return 0;
488
7b105ca2 489 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 490}
491
9dac77fa 492static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 493{
9dac77fa 494 if (!ctxt->has_seg_override)
7a5b56df
AK		 495 return 0;
496
9dac77fa 497 return ctxt->seg_override;
7a5b56df
AK		 498}
499
35d3d4a1
AK		 500static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
501 u32 error, bool valid)
54b8486f 502{
da9cb575
AK		 503 ctxt->exception.vector = vec;
504 ctxt->exception.error_code = error;
505 ctxt->exception.error_code_valid = valid;
35d3d4a1 506 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 507}
508
3b88e41a
JR		 509static int emulate_db(struct x86_emulate_ctxt *ctxt)
510{
511 return emulate_exception(ctxt, DB_VECTOR, 0, false);
512}
513
35d3d4a1 514static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 515{
35d3d4a1 516 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 517}
518
618ff15d
AK		 519static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
520{
521 return emulate_exception(ctxt, SS_VECTOR, err, true);
522}
523
35d3d4a1 524static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 525{
35d3d4a1 526 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 527}
528
35d3d4a1 529static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 530{
35d3d4a1 531 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 532}
533
34d1f490
AK		 534static int emulate_de(struct x86_emulate_ctxt *ctxt)
535{
35d3d4a1 536 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 537}
538
1253791d
AK		 539static int emulate_nm(struct x86_emulate_ctxt *ctxt)
540{
541 return emulate_exception(ctxt, NM_VECTOR, 0, false);
542}
543
1aa36616
AK		 544static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
545{
546 u16 selector;
547 struct desc_struct desc;
548
549 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
550 return selector;
551}
552
553static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
554 unsigned seg)
555{
556 u16 dummy;
557 u32 base3;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
561 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
562}
563
1c11b376
AK		 564/*
565 * x86 defines three classes of vector instructions: explicitly
566 * aligned, explicitly unaligned, and the rest, which change behaviour
567 * depending on whether they're AVX encoded or not.
568 *
569 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
570 * subject to the same check.
571 */
572static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
573{
574 if (likely(size < 16))
575 return false;
576
577 if (ctxt->d & Aligned)
578 return true;
579 else if (ctxt->d & Unaligned)
580 return false;
581 else if (ctxt->d & Avx)
582 return false;
583 else
584 return true;
585}
586
3d9b938e 587static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 588 struct segmented_address addr,
3d9b938e 589 unsigned size, bool write, bool fetch,
52fd8b44
AK		 590 ulong *linear)
591{
618ff15d
AK		 592 struct desc_struct desc;
593 bool usable;
52fd8b44 594 ulong la;
618ff15d 595 u32 lim;
1aa36616 596 u16 sel;
618ff15d 597 unsigned cpl, rpl;
52fd8b44 598
7b105ca2 599 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 600 switch (ctxt->mode) {
601 case X86EMUL_MODE_REAL:
602 break;
603 case X86EMUL_MODE_PROT64:
604 if (((signed long)la << 16) >> 16 != la)
605 return emulate_gp(ctxt, 0);
606 break;
607 default:
1aa36616
AK		 608 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
609 addr.seg);
618ff15d
AK		 610 if (!usable)
611 goto bad;
612 /* code segment or read-only data segment */
613 if (((desc.type & 8) || !(desc.type & 2)) && write)
614 goto bad;
615 /* unreadable code segment */
3d9b938e 616 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 617 goto bad;
618 lim = desc_limit_scaled(&desc);
619 if ((desc.type & 8) || !(desc.type & 4)) {
620 /* expand-up segment */
621 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
622 goto bad;
623 } else {
624 /* exapand-down segment */
625 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
626 goto bad;
627 lim = desc.d ? 0xffffffff : 0xffff;
628 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
629 goto bad;
630 }
717746e3 631 cpl = ctxt->ops->cpl(ctxt);
1aa36616 632 rpl = sel & 3;
618ff15d
AK		 633 cpl = max(cpl, rpl);
634 if (!(desc.type & 8)) {
635 /* data segment */
636 if (cpl > desc.dpl)
637 goto bad;
638 } else if ((desc.type & 8) && !(desc.type & 4)) {
639 /* nonconforming code segment */
640 if (cpl != desc.dpl)
641 goto bad;
642 } else if ((desc.type & 8) && (desc.type & 4)) {
643 /* conforming code segment */
644 if (cpl < desc.dpl)
645 goto bad;
646 }
647 break;
648 }
9dac77fa 649 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 650 la &= (u32)-1;
1c11b376
AK		 651 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
652 return emulate_gp(ctxt, 0);
52fd8b44
AK		 653 *linear = la;
654 return X86EMUL_CONTINUE;
618ff15d
AK		 655bad:
656 if (addr.seg == VCPU_SREG_SS)
657 return emulate_ss(ctxt, addr.seg);
658 else
659 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 660}
661
3d9b938e
NE		 662static int linearize(struct x86_emulate_ctxt *ctxt,
663 struct segmented_address addr,
664 unsigned size, bool write,
665 ulong *linear)
666{
667 return __linearize(ctxt, addr, size, write, false, linear);
668}
669
670
3ca3ac4d
AK		 671static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
672 struct segmented_address addr,
673 void *data,
674 unsigned size)
675{
9fa088f4
AK		 676 int rc;
677 ulong linear;
678
83b8795a 679 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 680 if (rc != X86EMUL_CONTINUE)
681 return rc;
0f65dd70 682 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 683}
684
807941b1
TY		 685/*
686 * Fetch the next byte of the instruction being emulated which is pointed to
687 * by ctxt->_eip, then increment ctxt->_eip.
688 *
689 * Also prefetch the remaining bytes of the instruction without crossing page
690 * boundary if they are not in fetch_cache yet.
691 */
692static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 693{
9dac77fa 694 struct fetch_cache *fc = &ctxt->fetch;
62266869 695 int rc;
2fb53ad8 696 int size, cur_size;
62266869 697
807941b1 698 if (ctxt->_eip == fc->end) {
3d9b938e 699 unsigned long linear;
807941b1
TY		 700 struct segmented_address addr = { .seg = VCPU_SREG_CS,
701 .ea = ctxt->_eip };
2fb53ad8 702 cur_size = fc->end - fc->start;
807941b1
TY		 703 size = min(15UL - cur_size,
704 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 705 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 706 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 707 return rc;
ef5d75cc
TY		 708 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
709 size, &ctxt->exception);
7d88bb48 710 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 711 return rc;
2fb53ad8 712 fc->end += size;
62266869 713 }
807941b1
TY		 714 *dest = fc->data[ctxt->_eip - fc->start];
715 ctxt->_eip++;
3e2815e9 716 return X86EMUL_CONTINUE;
62266869
AK		 717}
718
719static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 720 void *dest, unsigned size)
62266869 721{
3e2815e9 722 int rc;
62266869 723
eb3c79e6 724 /* x86 instructions are limited to 15 bytes. */
7d88bb48 725 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 726 return X86EMUL_UNHANDLEABLE;
62266869 727 while (size--) {
807941b1 728 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 729 if (rc != X86EMUL_CONTINUE)
62266869
AK		 730 return rc;
731 }
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK		 733}
734
67cbc90d 735/* Fetch next part of the instruction being emulated. */
e85a1085 736#define insn_fetch(_type, _ctxt) \
67cbc90d 737({ unsigned long _x; \
e85a1085 738 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 739 if (rc != X86EMUL_CONTINUE) \
740 goto done; \
67cbc90d
TY		 741 (_type)_x; \
742})
743
807941b1
TY		 744#define insn_fetch_arr(_arr, _size, _ctxt) \
745({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 746 if (rc != X86EMUL_CONTINUE) \
747 goto done; \
67cbc90d
TY		 748})
749
1e3c5cb0
RR		 750/*
751 * Given the 'reg' portion of a ModRM byte, and a register block, return a
752 * pointer into the block that addresses the relevant register.
753 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
754 */
755static void *decode_register(u8 modrm_reg, unsigned long *regs,
756 int highbyte_regs)
6aa8b732
AK		 757{
758 void *p;
759
760 p = &regs[modrm_reg];
761 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
762 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
763 return p;
764}
765
766static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 767 struct segmented_address addr,
6aa8b732
AK		 768 u16 *size, unsigned long *address, int op_bytes)
769{
770 int rc;
771
772 if (op_bytes == 2)
773 op_bytes = 3;
774 *address = 0;
3ca3ac4d 775 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 776 if (rc != X86EMUL_CONTINUE)
6aa8b732 777 return rc;
30b31ab6 778 addr.ea += 2;
3ca3ac4d 779 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 780 return rc;
781}
782
bbe9abbd
NK		 783static int test_cc(unsigned int condition, unsigned int flags)
784{
785 int rc = 0;
786
787 switch ((condition & 15) >> 1) {
788 case 0: /* o */
789 rc |= (flags & EFLG_OF);
790 break;
791 case 1: /* b/c/nae */
792 rc |= (flags & EFLG_CF);
793 break;
794 case 2: /* z/e */
795 rc |= (flags & EFLG_ZF);
796 break;
797 case 3: /* be/na */
798 rc |= (flags & (EFLG_CF|EFLG_ZF));
799 break;
800 case 4: /* s */
801 rc |= (flags & EFLG_SF);
802 break;
803 case 5: /* p/pe */
804 rc |= (flags & EFLG_PF);
805 break;
806 case 7: /* le/ng */
807 rc |= (flags & EFLG_ZF);
808 /* fall through */
809 case 6: /* l/nge */
810 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
811 break;
812 }
813
814 /* Odd condition identifiers (lsb == 1) have inverted sense. */
815 return (!!rc ^ (condition & 1));
816}
817
91ff3cb4
AK		 818static void fetch_register_operand(struct operand *op)
819{
820 switch (op->bytes) {
821 case 1:
822 op->val = *(u8 *)op->addr.reg;
823 break;
824 case 2:
825 op->val = *(u16 *)op->addr.reg;
826 break;
827 case 4:
828 op->val = *(u32 *)op->addr.reg;
829 break;
830 case 8:
831 op->val = *(u64 *)op->addr.reg;
832 break;
833 }
834}
835
1253791d
AK		 836static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
837{
838 ctxt->ops->get_fpu(ctxt);
839 switch (reg) {
840 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
841 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
842 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
843 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
844 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
845 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
846 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
847 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
848#ifdef CONFIG_X86_64
849 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
850 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
851 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
852 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
853 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
854 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
855 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
856 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
857#endif
858 default: BUG();
859 }
860 ctxt->ops->put_fpu(ctxt);
861}
862
863static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
864 int reg)
865{
866 ctxt->ops->get_fpu(ctxt);
867 switch (reg) {
868 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
869 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
870 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
871 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
872 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
873 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
874 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
875 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
876#ifdef CONFIG_X86_64
877 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
878 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
879 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
880 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
881 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
882 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
883 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
884 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
885#endif
886 default: BUG();
887 }
888 ctxt->ops->put_fpu(ctxt);
889}
890
cbe2c9d3
AK		 891static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
892{
893 ctxt->ops->get_fpu(ctxt);
894 switch (reg) {
895 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
896 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
897 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
898 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
899 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
900 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
901 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
902 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
903 default: BUG();
904 }
905 ctxt->ops->put_fpu(ctxt);
906}
907
908static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
909{
910 ctxt->ops->get_fpu(ctxt);
911 switch (reg) {
912 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
913 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
914 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
915 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
916 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
917 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
918 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
919 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
920 default: BUG();
921 }
922 ctxt->ops->put_fpu(ctxt);
923}
924
1253791d 925static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 926 struct operand *op)
3c118e24 927{
9dac77fa
AK		 928 unsigned reg = ctxt->modrm_reg;
929 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 930
9dac77fa
AK		 931 if (!(ctxt->d & ModRM))
932 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 933
9dac77fa 934 if (ctxt->d & Sse) {
1253791d
AK		 935 op->type = OP_XMM;
936 op->bytes = 16;
937 op->addr.xmm = reg;
938 read_sse_reg(ctxt, &op->vec_val, reg);
939 return;
940 }
cbe2c9d3
AK		 941 if (ctxt->d & Mmx) {
942 reg &= 7;
943 op->type = OP_MM;
944 op->bytes = 8;
945 op->addr.mm = reg;
946 return;
947 }
1253791d 948
3c118e24 949 op->type = OP_REG;
2adb5ad9 950 if (ctxt->d & ByteOp) {
9dac77fa 951 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 952 op->bytes = 1;
953 } else {
9dac77fa
AK		 954 op->addr.reg = decode_register(reg, ctxt->regs, 0);
955 op->bytes = ctxt->op_bytes;
3c118e24 956 }
91ff3cb4 957 fetch_register_operand(op);
3c118e24
AK		 958 op->orig_val = op->val;
959}
960
1c73ef66 961static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 962 struct operand *op)
1c73ef66 963{
1c73ef66 964 u8 sib;
f5b4edcd 965 int index_reg = 0, base_reg = 0, scale;
3e2815e9 966 int rc = X86EMUL_CONTINUE;
2dbd0dd7 967 ulong modrm_ea = 0;
1c73ef66 968
9dac77fa
AK		 969 if (ctxt->rex_prefix) {
970 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
971 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
972 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 973 }
974
e85a1085 975 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 976 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
977 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
978 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
979 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 980
9dac77fa 981 if (ctxt->modrm_mod == 3) {
2dbd0dd7 982 op->type = OP_REG;
9dac77fa
AK		 983 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
984 op->addr.reg = decode_register(ctxt->modrm_rm,
985 ctxt->regs, ctxt->d & ByteOp);
986 if (ctxt->d & Sse) {
1253791d
AK		 987 op->type = OP_XMM;
988 op->bytes = 16;
9dac77fa
AK		 989 op->addr.xmm = ctxt->modrm_rm;
990 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 991 return rc;
992 }
cbe2c9d3
AK		 993 if (ctxt->d & Mmx) {
994 op->type = OP_MM;
995 op->bytes = 8;
996 op->addr.xmm = ctxt->modrm_rm & 7;
997 return rc;
998 }
2dbd0dd7 999 fetch_register_operand(op);
1c73ef66
AK		 1000 return rc;
1001 }
1002
2dbd0dd7
AK		 1003 op->type = OP_MEM;
1004
9dac77fa
AK		 1005 if (ctxt->ad_bytes == 2) {
1006 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1007 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1008 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1009 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1010
1011 /* 16-bit ModR/M decode. */
9dac77fa 1012 switch (ctxt->modrm_mod) {
1c73ef66 1013 case 0:
9dac77fa 1014 if (ctxt->modrm_rm == 6)
e85a1085 1015 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1016 break;
1017 case 1:
e85a1085 1018 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1019 break;
1020 case 2:
e85a1085 1021 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1022 break;
1023 }
9dac77fa 1024 switch (ctxt->modrm_rm) {
1c73ef66 1025 case 0:
2dbd0dd7 1026 modrm_ea += bx + si;
1c73ef66
AK		 1027 break;
1028 case 1:
2dbd0dd7 1029 modrm_ea += bx + di;
1c73ef66
AK		 1030 break;
1031 case 2:
2dbd0dd7 1032 modrm_ea += bp + si;
1c73ef66
AK		 1033 break;
1034 case 3:
2dbd0dd7 1035 modrm_ea += bp + di;
1c73ef66
AK		 1036 break;
1037 case 4:
2dbd0dd7 1038 modrm_ea += si;
1c73ef66
AK		 1039 break;
1040 case 5:
2dbd0dd7 1041 modrm_ea += di;
1c73ef66
AK		 1042 break;
1043 case 6:
9dac77fa 1044 if (ctxt->modrm_mod != 0)
2dbd0dd7 1045 modrm_ea += bp;
1c73ef66
AK		 1046 break;
1047 case 7:
2dbd0dd7 1048 modrm_ea += bx;
1c73ef66
AK		 1049 break;
1050 }
9dac77fa
AK		 1051 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1052 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1053 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1054 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1055 } else {
1056 /* 32/64-bit ModR/M decode. */
9dac77fa 1057 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1058 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1059 index_reg |= (sib >> 3) & 7;
1060 base_reg |= sib & 7;
1061 scale = sib >> 6;
1062
9dac77fa 1063 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1064 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 1065 else
9dac77fa 1066 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 1067 if (index_reg != 4)
9dac77fa
AK		 1068 modrm_ea += ctxt->regs[index_reg] << scale;
1069 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1070 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1071 ctxt->rip_relative = 1;
84411d85 1072 } else
9dac77fa
AK		 1073 modrm_ea += ctxt->regs[ctxt->modrm_rm];
1074 switch (ctxt->modrm_mod) {
1c73ef66 1075 case 0:
9dac77fa 1076 if (ctxt->modrm_rm == 5)
e85a1085 1077 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1078 break;
1079 case 1:
e85a1085 1080 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1081 break;
1082 case 2:
e85a1085 1083 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1084 break;
1085 }
1086 }
90de84f5 1087 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1088done:
1089 return rc;
1090}
1091
1092static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1093 struct operand *op)
1c73ef66 1094{
3e2815e9 1095 int rc = X86EMUL_CONTINUE;
1c73ef66 1096
2dbd0dd7 1097 op->type = OP_MEM;
9dac77fa 1098 switch (ctxt->ad_bytes) {
1c73ef66 1099 case 2:
e85a1085 1100 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1101 break;
1102 case 4:
e85a1085 1103 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1104 break;
1105 case 8:
e85a1085 1106 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1107 break;
1108 }
1109done:
1110 return rc;
1111}
1112
9dac77fa 1113static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1114{
7129eeca 1115 long sv = 0, mask;
35c843c4 1116
9dac77fa
AK		 1117 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1118 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1119
9dac77fa
AK		 1120 if (ctxt->src.bytes == 2)
1121 sv = (s16)ctxt->src.val & (s16)mask;
1122 else if (ctxt->src.bytes == 4)
1123 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1124
9dac77fa 1125 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1126 }
ba7ff2b7
WY		 1127
1128 /* only subword offset */
9dac77fa 1129 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1130}
1131
dde7e6d1 1132static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1133 unsigned long addr, void *dest, unsigned size)
6aa8b732 1134{
dde7e6d1 1135 int rc;
9dac77fa 1136 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1137
dde7e6d1
AK		 1138 while (size) {
1139 int n = min(size, 8u);
1140 size -= n;
1141 if (mc->pos < mc->end)
1142 goto read_cached;
5cd21917 1143
7b105ca2
TY		 1144 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1145 &ctxt->exception);
dde7e6d1
AK		 1146 if (rc != X86EMUL_CONTINUE)
1147 return rc;
1148 mc->end += n;
6aa8b732 1149
dde7e6d1
AK		 1150 read_cached:
1151 memcpy(dest, mc->data + mc->pos, n);
1152 mc->pos += n;
1153 dest += n;
1154 addr += n;
6aa8b732 1155 }
dde7e6d1
AK		 1156 return X86EMUL_CONTINUE;
1157}
6aa8b732 1158
3ca3ac4d
AK		 1159static int segmented_read(struct x86_emulate_ctxt *ctxt,
1160 struct segmented_address addr,
1161 void *data,
1162 unsigned size)
1163{
9fa088f4
AK		 1164 int rc;
1165 ulong linear;
1166
83b8795a 1167 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1168 if (rc != X86EMUL_CONTINUE)
1169 return rc;
7b105ca2 1170 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1171}
1172
1173static int segmented_write(struct x86_emulate_ctxt *ctxt,
1174 struct segmented_address addr,
1175 const void *data,
1176 unsigned size)
1177{
9fa088f4
AK		 1178 int rc;
1179 ulong linear;
1180
83b8795a 1181 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1182 if (rc != X86EMUL_CONTINUE)
1183 return rc;
0f65dd70
AK		 1184 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1185 &ctxt->exception);
3ca3ac4d
AK		 1186}
1187
1188static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1189 struct segmented_address addr,
1190 const void *orig_data, const void *data,
1191 unsigned size)
1192{
9fa088f4
AK		 1193 int rc;
1194 ulong linear;
1195
83b8795a 1196 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
0f65dd70
AK		 1199 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1200 size, &ctxt->exception);
3ca3ac4d
AK		 1201}
1202
dde7e6d1 1203static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1204 unsigned int size, unsigned short port,
1205 void *dest)
1206{
9dac77fa 1207 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1208
dde7e6d1 1209 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1210 unsigned int in_page, n;
9dac77fa
AK		 1211 unsigned int count = ctxt->rep_prefix ?
1212 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1213 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1214 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1215 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1216 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1217 count);
1218 if (n == 0)
1219 n = 1;
1220 rc->pos = rc->end = 0;
7b105ca2 1221 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1222 return 0;
1223 rc->end = n * size;
6aa8b732
AK		 1224 }
1225
dde7e6d1
AK		 1226 memcpy(dest, rc->data + rc->pos, size);
1227 rc->pos += size;
1228 return 1;
1229}
6aa8b732 1230
7f3d35fd
KW		 1231static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1232 u16 index, struct desc_struct *desc)
1233{
1234 struct desc_ptr dt;
1235 ulong addr;
1236
1237 ctxt->ops->get_idt(ctxt, &dt);
1238
1239 if (dt.size < index * 8 + 7)
1240 return emulate_gp(ctxt, index << 3 | 0x2);
1241
1242 addr = dt.address + index * 8;
1243 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1244 &ctxt->exception);
1245}
1246
dde7e6d1 1247static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1248 u16 selector, struct desc_ptr *dt)
1249{
7b105ca2
TY		 1250 struct x86_emulate_ops *ops = ctxt->ops;
1251
dde7e6d1
AK		 1252 if (selector & 1 << 2) {
1253 struct desc_struct desc;
1aa36616
AK		 1254 u16 sel;
1255
dde7e6d1 1256 memset (dt, 0, sizeof *dt);
1aa36616 1257 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1258 return;
e09d082c 1259
dde7e6d1
AK		 1260 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1261 dt->address = get_desc_base(&desc);
1262 } else
4bff1e86 1263 ops->get_gdt(ctxt, dt);
dde7e6d1 1264}
120df890 1265
dde7e6d1
AK		 1266/* allowed just for 8 bytes segments */
1267static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1268 u16 selector, struct desc_struct *desc)
1269{
1270 struct desc_ptr dt;
1271 u16 index = selector >> 3;
dde7e6d1 1272 ulong addr;
120df890 1273
7b105ca2 1274 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1275
35d3d4a1
AK		 1276 if (dt.size < index * 8 + 7)
1277 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1278
7b105ca2
TY		 1279 addr = dt.address + index * 8;
1280 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1281 &ctxt->exception);
dde7e6d1 1282}
ef65c889 1283
dde7e6d1
AK		 1284/* allowed just for 8 bytes segments */
1285static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1286 u16 selector, struct desc_struct *desc)
1287{
1288 struct desc_ptr dt;
1289 u16 index = selector >> 3;
dde7e6d1 1290 ulong addr;
6aa8b732 1291
7b105ca2 1292 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1293
35d3d4a1
AK		 1294 if (dt.size < index * 8 + 7)
1295 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1296
dde7e6d1 1297 addr = dt.address + index * 8;
7b105ca2
TY		 1298 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1299 &ctxt->exception);
dde7e6d1 1300}
c7e75a3d 1301
5601d05b 1302/* Does not support long mode */
dde7e6d1 1303static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1304 u16 selector, int seg)
1305{
1306 struct desc_struct seg_desc;
1307 u8 dpl, rpl, cpl;
1308 unsigned err_vec = GP_VECTOR;
1309 u32 err_code = 0;
1310 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1311 int ret;
69f55cb1 1312
dde7e6d1 1313 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1314
dde7e6d1
AK		 1315 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1316 || ctxt->mode == X86EMUL_MODE_REAL) {
1317 /* set real mode segment descriptor */
1318 set_desc_base(&seg_desc, selector << 4);
1319 set_desc_limit(&seg_desc, 0xffff);
1320 seg_desc.type = 3;
1321 seg_desc.p = 1;
1322 seg_desc.s = 1;
66b0ab8f
KW		 1323 if (ctxt->mode == X86EMUL_MODE_VM86)
1324 seg_desc.dpl = 3;
dde7e6d1
AK		 1325 goto load;
1326 }
1327
1328 /* NULL selector is not valid for TR, CS and SS */
1329 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1330 && null_selector)
1331 goto exception;
1332
1333 /* TR should be in GDT only */
1334 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1335 goto exception;
1336
1337 if (null_selector) /* for NULL selector skip all following checks */
1338 goto load;
1339
7b105ca2 1340 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1341 if (ret != X86EMUL_CONTINUE)
1342 return ret;
1343
1344 err_code = selector & 0xfffc;
1345 err_vec = GP_VECTOR;
1346
1347 /* can't load system descriptor into segment selecor */
1348 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1349 goto exception;
1350
1351 if (!seg_desc.p) {
1352 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1353 goto exception;
1354 }
1355
1356 rpl = selector & 3;
1357 dpl = seg_desc.dpl;
7b105ca2 1358 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1359
1360 switch (seg) {
1361 case VCPU_SREG_SS:
1362 /*
1363 * segment is not a writable data segment or segment
1364 * selector's RPL != CPL or segment selector's RPL != CPL
1365 */
1366 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1367 goto exception;
6aa8b732 1368 break;
dde7e6d1
AK		 1369 case VCPU_SREG_CS:
1370 if (!(seg_desc.type & 8))
1371 goto exception;
1372
1373 if (seg_desc.type & 4) {
1374 /* conforming */
1375 if (dpl > cpl)
1376 goto exception;
1377 } else {
1378 /* nonconforming */
1379 if (rpl > cpl || dpl != cpl)
1380 goto exception;
1381 }
1382 /* CS(RPL) <- CPL */
1383 selector = (selector & 0xfffc) | cpl;
6aa8b732 1384 break;
dde7e6d1
AK		 1385 case VCPU_SREG_TR:
1386 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1387 goto exception;
1388 break;
1389 case VCPU_SREG_LDTR:
1390 if (seg_desc.s || seg_desc.type != 2)
1391 goto exception;
1392 break;
1393 default: /* DS, ES, FS, or GS */
4e62417b 1394 /*
dde7e6d1
AK		 1395 * segment is not a data or readable code segment or
1396 * ((segment is a data or nonconforming code segment)
1397 * and (both RPL and CPL > DPL))
4e62417b 1398 */
dde7e6d1
AK		 1399 if ((seg_desc.type & 0xa) == 0x8 ||
1400 (((seg_desc.type & 0xc) != 0xc) &&
1401 (rpl > dpl && cpl > dpl)))
1402 goto exception;
6aa8b732 1403 break;
dde7e6d1
AK		 1404 }
1405
1406 if (seg_desc.s) {
1407 /* mark segment as accessed */
1408 seg_desc.type |= 1;
7b105ca2 1409 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1410 if (ret != X86EMUL_CONTINUE)
1411 return ret;
1412 }
1413load:
7b105ca2 1414 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1415 return X86EMUL_CONTINUE;
1416exception:
1417 emulate_exception(ctxt, err_vec, err_code, true);
1418 return X86EMUL_PROPAGATE_FAULT;
1419}
1420
31be40b3
WY		 1421static void write_register_operand(struct operand *op)
1422{
1423 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1424 switch (op->bytes) {
1425 case 1:
1426 *(u8 *)op->addr.reg = (u8)op->val;
1427 break;
1428 case 2:
1429 *(u16 *)op->addr.reg = (u16)op->val;
1430 break;
1431 case 4:
1432 *op->addr.reg = (u32)op->val;
1433 break; /* 64b: zero-extend */
1434 case 8:
1435 *op->addr.reg = op->val;
1436 break;
1437 }
1438}
1439
adddcecf 1440static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1441{
1442 int rc;
dde7e6d1 1443
9dac77fa 1444 switch (ctxt->dst.type) {
dde7e6d1 1445 case OP_REG:
9dac77fa 1446 write_register_operand(&ctxt->dst);
6aa8b732 1447 break;
dde7e6d1 1448 case OP_MEM:
9dac77fa 1449 if (ctxt->lock_prefix)
3ca3ac4d 1450 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1451 ctxt->dst.addr.mem,
1452 &ctxt->dst.orig_val,
1453 &ctxt->dst.val,
1454 ctxt->dst.bytes);
341de7e3 1455 else
3ca3ac4d 1456 rc = segmented_write(ctxt,
9dac77fa
AK		 1457 ctxt->dst.addr.mem,
1458 &ctxt->dst.val,
1459 ctxt->dst.bytes);
dde7e6d1
AK		 1460 if (rc != X86EMUL_CONTINUE)
1461 return rc;
a682e354 1462 break;
1253791d 1463 case OP_XMM:
9dac77fa 1464 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1465 break;
cbe2c9d3
AK		 1466 case OP_MM:
1467 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1468 break;
dde7e6d1
AK		 1469 case OP_NONE:
1470 /* no writeback */
414e6277 1471 break;
dde7e6d1 1472 default:
414e6277 1473 break;
6aa8b732 1474 }
dde7e6d1
AK		 1475 return X86EMUL_CONTINUE;
1476}
6aa8b732 1477
4487b3b4 1478static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1479{
4179bb02 1480 struct segmented_address addr;
0dc8d10f 1481
9dac77fa
AK		 1482 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1483 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1484 addr.seg = VCPU_SREG_SS;
1485
1486 /* Disable writeback. */
9dac77fa
AK		 1487 ctxt->dst.type = OP_NONE;
1488 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1489}
69f55cb1 1490
dde7e6d1 1491static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1492 void *dest, int len)
1493{
dde7e6d1 1494 int rc;
90de84f5 1495 struct segmented_address addr;
8b4caf66 1496
9dac77fa 1497 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1498 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1499 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1500 if (rc != X86EMUL_CONTINUE)
1501 return rc;
1502
9dac77fa 1503 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1504 return rc;
8b4caf66
LV		 1505}
1506
c54fe504
TY		 1507static int em_pop(struct x86_emulate_ctxt *ctxt)
1508{
9dac77fa 1509 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1510}
1511
dde7e6d1 1512static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1513 void *dest, int len)
9de41573
GN		 1514{
1515 int rc;
dde7e6d1
AK		 1516 unsigned long val, change_mask;
1517 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1518 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1519
3b9be3bf 1520 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1521 if (rc != X86EMUL_CONTINUE)
1522 return rc;
9de41573 1523
dde7e6d1
AK		 1524 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1525 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1526
dde7e6d1
AK		 1527 switch(ctxt->mode) {
1528 case X86EMUL_MODE_PROT64:
1529 case X86EMUL_MODE_PROT32:
1530 case X86EMUL_MODE_PROT16:
1531 if (cpl == 0)
1532 change_mask |= EFLG_IOPL;
1533 if (cpl <= iopl)
1534 change_mask |= EFLG_IF;
1535 break;
1536 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1537 if (iopl < 3)
1538 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1539 change_mask |= EFLG_IF;
1540 break;
1541 default: /* real mode */
1542 change_mask |= (EFLG_IOPL | EFLG_IF);
1543 break;
9de41573 1544 }
dde7e6d1
AK		 1545
1546 *(unsigned long *)dest =
1547 (ctxt->eflags & ~change_mask) | (val & change_mask);
1548
1549 return rc;
9de41573
GN		 1550}
1551
62aaa2f0
TY		 1552static int em_popf(struct x86_emulate_ctxt *ctxt)
1553{
9dac77fa
AK		 1554 ctxt->dst.type = OP_REG;
1555 ctxt->dst.addr.reg = &ctxt->eflags;
1556 ctxt->dst.bytes = ctxt->op_bytes;
1557 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1558}
1559
1cd196ea 1560static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1561{
1cd196ea
AK		 1562 int seg = ctxt->src2.val;
1563
9dac77fa 1564 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1565
4487b3b4 1566 return em_push(ctxt);
7b262e90
GN		 1567}
1568
1cd196ea 1569static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1570{
1cd196ea 1571 int seg = ctxt->src2.val;
dde7e6d1
AK		 1572 unsigned long selector;
1573 int rc;
38ba30ba 1574
9dac77fa 1575 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1576 if (rc != X86EMUL_CONTINUE)
1577 return rc;
1578
7b105ca2 1579 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1580 return rc;
38ba30ba
GN		 1581}
1582
b96a7fad 1583static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1584{
9dac77fa 1585 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1586 int rc = X86EMUL_CONTINUE;
1587 int reg = VCPU_REGS_RAX;
38ba30ba 1588
dde7e6d1
AK		 1589 while (reg <= VCPU_REGS_RDI) {
1590 (reg == VCPU_REGS_RSP) ?
9dac77fa 1591 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1592
4487b3b4 1593 rc = em_push(ctxt);
dde7e6d1
AK		 1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
38ba30ba 1596
dde7e6d1 1597 ++reg;
38ba30ba 1598 }
38ba30ba 1599
dde7e6d1 1600 return rc;
38ba30ba
GN		 1601}
1602
62aaa2f0
TY		 1603static int em_pushf(struct x86_emulate_ctxt *ctxt)
1604{
9dac77fa 1605 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1606 return em_push(ctxt);
1607}
1608
b96a7fad 1609static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1610{
dde7e6d1
AK		 1611 int rc = X86EMUL_CONTINUE;
1612 int reg = VCPU_REGS_RDI;
38ba30ba 1613
dde7e6d1
AK		 1614 while (reg >= VCPU_REGS_RAX) {
1615 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1616 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1617 ctxt->op_bytes);
dde7e6d1
AK		 1618 --reg;
1619 }
38ba30ba 1620
9dac77fa 1621 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1622 if (rc != X86EMUL_CONTINUE)
1623 break;
1624 --reg;
38ba30ba 1625 }
dde7e6d1 1626 return rc;
38ba30ba
GN		 1627}
1628
7b105ca2 1629int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1630{
7b105ca2 1631 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1632 int rc;
6e154e56
MG		 1633 struct desc_ptr dt;
1634 gva_t cs_addr;
1635 gva_t eip_addr;
1636 u16 cs, eip;
6e154e56
MG		 1637
1638 /* TODO: Add limit checks */
9dac77fa 1639 ctxt->src.val = ctxt->eflags;
4487b3b4 1640 rc = em_push(ctxt);
5c56e1cf
AK		 1641 if (rc != X86EMUL_CONTINUE)
1642 return rc;
6e154e56
MG		 1643
1644 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1645
9dac77fa 1646 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1647 rc = em_push(ctxt);
5c56e1cf
AK		 1648 if (rc != X86EMUL_CONTINUE)
1649 return rc;
6e154e56 1650
9dac77fa 1651 ctxt->src.val = ctxt->_eip;
4487b3b4 1652 rc = em_push(ctxt);
5c56e1cf
AK		 1653 if (rc != X86EMUL_CONTINUE)
1654 return rc;
1655
4bff1e86 1656 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1657
1658 eip_addr = dt.address + (irq << 2);
1659 cs_addr = dt.address + (irq << 2) + 2;
1660
0f65dd70 1661 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1662 if (rc != X86EMUL_CONTINUE)
1663 return rc;
1664
0f65dd70 1665 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1666 if (rc != X86EMUL_CONTINUE)
1667 return rc;
1668
7b105ca2 1669 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1670 if (rc != X86EMUL_CONTINUE)
1671 return rc;
1672
9dac77fa 1673 ctxt->_eip = eip;
6e154e56
MG		 1674
1675 return rc;
1676}
1677
7b105ca2 1678static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1679{
1680 switch(ctxt->mode) {
1681 case X86EMUL_MODE_REAL:
7b105ca2 1682 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1683 case X86EMUL_MODE_VM86:
1684 case X86EMUL_MODE_PROT16:
1685 case X86EMUL_MODE_PROT32:
1686 case X86EMUL_MODE_PROT64:
1687 default:
1688 /* Protected mode interrupts unimplemented yet */
1689 return X86EMUL_UNHANDLEABLE;
1690 }
1691}
1692
7b105ca2 1693static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1694{
dde7e6d1
AK		 1695 int rc = X86EMUL_CONTINUE;
1696 unsigned long temp_eip = 0;
1697 unsigned long temp_eflags = 0;
1698 unsigned long cs = 0;
1699 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1700 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1701 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1702 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1703
dde7e6d1 1704 /* TODO: Add stack limit check */
38ba30ba 1705
9dac77fa 1706 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1707
dde7e6d1
AK		 1708 if (rc != X86EMUL_CONTINUE)
1709 return rc;
38ba30ba 1710
35d3d4a1
AK		 1711 if (temp_eip & ~0xffff)
1712 return emulate_gp(ctxt, 0);
38ba30ba 1713
9dac77fa 1714 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1715
dde7e6d1
AK		 1716 if (rc != X86EMUL_CONTINUE)
1717 return rc;
38ba30ba 1718
9dac77fa 1719 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1720
dde7e6d1
AK		 1721 if (rc != X86EMUL_CONTINUE)
1722 return rc;
38ba30ba 1723
7b105ca2 1724 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1725
dde7e6d1
AK		 1726 if (rc != X86EMUL_CONTINUE)
1727 return rc;
38ba30ba 1728
9dac77fa 1729 ctxt->_eip = temp_eip;
38ba30ba 1730
38ba30ba 1731
9dac77fa 1732 if (ctxt->op_bytes == 4)
dde7e6d1 1733 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1734 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1735 ctxt->eflags &= ~0xffff;
1736 ctxt->eflags |= temp_eflags;
38ba30ba 1737 }
dde7e6d1
AK		 1738
1739 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1740 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1741
1742 return rc;
38ba30ba
GN		 1743}
1744
e01991e7 1745static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1746{
dde7e6d1
AK		 1747 switch(ctxt->mode) {
1748 case X86EMUL_MODE_REAL:
7b105ca2 1749 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1750 case X86EMUL_MODE_VM86:
1751 case X86EMUL_MODE_PROT16:
1752 case X86EMUL_MODE_PROT32:
1753 case X86EMUL_MODE_PROT64:
c37eda13 1754 default:
dde7e6d1
AK		 1755 /* iret from protected mode unimplemented yet */
1756 return X86EMUL_UNHANDLEABLE;
c37eda13 1757 }
c37eda13
WY		 1758}
1759
d2f62766
TY		 1760static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1761{
d2f62766
TY		 1762 int rc;
1763 unsigned short sel;
1764
9dac77fa 1765 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1766
7b105ca2 1767 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1768 if (rc != X86EMUL_CONTINUE)
1769 return rc;
1770
9dac77fa
AK		 1771 ctxt->_eip = 0;
1772 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1773 return X86EMUL_CONTINUE;
1774}
1775
51187683 1776static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1777{
9dac77fa 1778 switch (ctxt->modrm_reg) {
8cdbd2c9 1779 case 0: /* rol */
a31b9cea 1780 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1781 break;
1782 case 1: /* ror */
a31b9cea 1783 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1784 break;
1785 case 2: /* rcl */
a31b9cea 1786 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1787 break;
1788 case 3: /* rcr */
a31b9cea 1789 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1790 break;
1791 case 4: /* sal/shl */
1792 case 6: /* sal/shl */
a31b9cea 1793 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1794 break;
1795 case 5: /* shr */
a31b9cea 1796 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1797 break;
1798 case 7: /* sar */
a31b9cea 1799 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1800 break;
1801 }
51187683 1802 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1803}
1804
3329ece1
AK		 1805static int em_not(struct x86_emulate_ctxt *ctxt)
1806{
1807 ctxt->dst.val = ~ctxt->dst.val;
1808 return X86EMUL_CONTINUE;
1809}
1810
1811static int em_neg(struct x86_emulate_ctxt *ctxt)
1812{
1813 emulate_1op(ctxt, "neg");
1814 return X86EMUL_CONTINUE;
1815}
1816
1817static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1818{
1819 u8 ex = 0;
1820
1821 emulate_1op_rax_rdx(ctxt, "mul", ex);
1822 return X86EMUL_CONTINUE;
1823}
1824
1825static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1826{
1827 u8 ex = 0;
1828
1829 emulate_1op_rax_rdx(ctxt, "imul", ex);
1830 return X86EMUL_CONTINUE;
1831}
1832
1833static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1834{
34d1f490 1835 u8 de = 0;
8cdbd2c9 1836
3329ece1
AK		 1837 emulate_1op_rax_rdx(ctxt, "div", de);
1838 if (de)
1839 return emulate_de(ctxt);
1840 return X86EMUL_CONTINUE;
1841}
1842
1843static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1844{
1845 u8 de = 0;
1846
1847 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1848 if (de)
1849 return emulate_de(ctxt);
8c5eee30 1850 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1851}
1852
51187683 1853static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1854{
4179bb02 1855 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1856
9dac77fa 1857 switch (ctxt->modrm_reg) {
8cdbd2c9 1858 case 0: /* inc */
d1eef45d 1859 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1860 break;
1861 case 1: /* dec */
d1eef45d 1862 emulate_1op(ctxt, "dec");
8cdbd2c9 1863 break;
d19292e4
MG		 1864 case 2: /* call near abs */ {
1865 long int old_eip;
9dac77fa
AK		 1866 old_eip = ctxt->_eip;
1867 ctxt->_eip = ctxt->src.val;
1868 ctxt->src.val = old_eip;
4487b3b4 1869 rc = em_push(ctxt);
d19292e4
MG		 1870 break;
1871 }
8cdbd2c9 1872 case 4: /* jmp abs */
9dac77fa 1873 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1874 break;
d2f62766
TY		 1875 case 5: /* jmp far */
1876 rc = em_jmp_far(ctxt);
1877 break;
8cdbd2c9 1878 case 6: /* push */
4487b3b4 1879 rc = em_push(ctxt);
8cdbd2c9 1880 break;
8cdbd2c9 1881 }
4179bb02 1882 return rc;
8cdbd2c9
LV		 1883}
1884
e0dac408 1885static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1886{
9dac77fa 1887 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1888
9dac77fa
AK		 1889 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1890 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1891 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1892 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1893 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1894 } else {
9dac77fa
AK		 1895 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1896 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1897
05f086f8 1898 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1899 }
1b30eaa8 1900 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1901}
1902
ebda02c2
TY		 1903static int em_ret(struct x86_emulate_ctxt *ctxt)
1904{
9dac77fa
AK		 1905 ctxt->dst.type = OP_REG;
1906 ctxt->dst.addr.reg = &ctxt->_eip;
1907 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1908 return em_pop(ctxt);
1909}
1910
e01991e7 1911static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1912{
a77ab5ea
AK		 1913 int rc;
1914 unsigned long cs;
1915
9dac77fa 1916 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1917 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1918 return rc;
9dac77fa
AK		 1919 if (ctxt->op_bytes == 4)
1920 ctxt->_eip = (u32)ctxt->_eip;
1921 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1922 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1923 return rc;
7b105ca2 1924 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1925 return rc;
1926}
1927
e940b5c2
TY		 1928static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1929{
1930 /* Save real source value, then compare EAX against destination. */
1931 ctxt->src.orig_val = ctxt->src.val;
1932 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1933 emulate_2op_SrcV(ctxt, "cmp");
1934
1935 if (ctxt->eflags & EFLG_ZF) {
1936 /* Success: write back to memory. */
1937 ctxt->dst.val = ctxt->src.orig_val;
1938 } else {
1939 /* Failure: write the value we saw to EAX. */
1940 ctxt->dst.type = OP_REG;
1941 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1942 }
1943 return X86EMUL_CONTINUE;
1944}
1945
d4b4325f 1946static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1947{
d4b4325f 1948 int seg = ctxt->src2.val;
09b5f4d3
WY		 1949 unsigned short sel;
1950 int rc;
1951
9dac77fa 1952 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1953
7b105ca2 1954 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1955 if (rc != X86EMUL_CONTINUE)
1956 return rc;
1957
9dac77fa 1958 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1959 return rc;
1960}
1961
7b105ca2 1962static void
e66bb2cc 1963setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1964 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1965{
1aa36616
AK		 1966 u16 selector;
1967
79168fd1 1968 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1969 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1970 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1971
1972 cs->l = 0; /* will be adjusted later */
79168fd1 1973 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1974 cs->g = 1; /* 4kb granularity */
79168fd1 1975 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1976 cs->type = 0x0b; /* Read, Execute, Accessed */
1977 cs->s = 1;
1978 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1979 cs->p = 1;
1980 cs->d = 1;
e66bb2cc 1981
79168fd1
GN		 1982 set_desc_base(ss, 0); /* flat segment */
1983 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1984 ss->g = 1; /* 4kb granularity */
1985 ss->s = 1;
1986 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1987 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1988 ss->dpl = 0;
79168fd1 1989 ss->p = 1;
e66bb2cc
AP		 1990}
1991
1a18a69b
AK		 1992static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
1993{
1994 u32 eax, ebx, ecx, edx;
1995
1996 eax = ecx = 0;
1997 return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)
1998 && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1999 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2000 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2001}
2002
c2226fc9
SB		 2003static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2004{
2005 struct x86_emulate_ops *ops = ctxt->ops;
2006 u32 eax, ebx, ecx, edx;
2007
2008 /*
2009 * syscall should always be enabled in longmode - so only become
2010 * vendor specific (cpuid) if other modes are active...
2011 */
2012 if (ctxt->mode == X86EMUL_MODE_PROT64)
2013 return true;
2014
2015 eax = 0x00000000;
2016 ecx = 0x00000000;
2017 if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) {
2018 /*
2019 * Intel ("GenuineIntel")
2020 * remark: Intel CPUs only support "syscall" in 64bit
2021 * longmode. Also an 64bit guest with a
2022 * 32bit compat-app running will #UD !! While this
2023 * behaviour can be fixed (by emulating) into AMD
2024 * response - CPUs of AMD can't behave like Intel.
2025 */
2026 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2027 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2028 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2029 return false;
2030
2031 /* AMD ("AuthenticAMD") */
2032 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2033 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2034 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2035 return true;
2036
2037 /* AMD ("AMDisbetter!") */
2038 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2039 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2040 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2041 return true;
2042 }
2043
2044 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2045 return false;
2046}
2047
e01991e7 2048static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2049{
7b105ca2 2050 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2051 struct desc_struct cs, ss;
e66bb2cc 2052 u64 msr_data;
79168fd1 2053 u16 cs_sel, ss_sel;
c2ad2bb3 2054 u64 efer = 0;
e66bb2cc
AP		 2055
2056 /* syscall is not available in real mode */
2e901c4c 2057 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2058 ctxt->mode == X86EMUL_MODE_VM86)
2059 return emulate_ud(ctxt);
e66bb2cc 2060
c2226fc9
SB		 2061 if (!(em_syscall_is_enabled(ctxt)))
2062 return emulate_ud(ctxt);
2063
c2ad2bb3 2064 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2065 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2066
c2226fc9
SB		 2067 if (!(efer & EFER_SCE))
2068 return emulate_ud(ctxt);
2069
717746e3 2070 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2071 msr_data >>= 32;
79168fd1
GN		 2072 cs_sel = (u16)(msr_data & 0xfffc);
2073 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2074
c2ad2bb3 2075 if (efer & EFER_LMA) {
79168fd1 2076 cs.d = 0;
e66bb2cc
AP		 2077 cs.l = 1;
2078 }
1aa36616
AK		 2079 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2080 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2081
9dac77fa 2082 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2083 if (efer & EFER_LMA) {
e66bb2cc 2084#ifdef CONFIG_X86_64
9dac77fa 2085 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2086
717746e3 2087 ops->get_msr(ctxt,
3fb1b5db
GN		 2088 ctxt->mode == X86EMUL_MODE_PROT64 ?
2089 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2090 ctxt->_eip = msr_data;
e66bb2cc 2091
717746e3 2092 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2093 ctxt->eflags &= ~(msr_data | EFLG_RF);
2094#endif
2095 } else {
2096 /* legacy mode */
717746e3 2097 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2098 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2099
2100 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2101 }
2102
e54cfa97 2103 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2104}
2105
e01991e7 2106static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2107{
7b105ca2 2108 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2109 struct desc_struct cs, ss;
8c604352 2110 u64 msr_data;
79168fd1 2111 u16 cs_sel, ss_sel;
c2ad2bb3 2112 u64 efer = 0;
8c604352 2113
7b105ca2 2114 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2115 /* inject #GP if in real mode */
35d3d4a1
AK		 2116 if (ctxt->mode == X86EMUL_MODE_REAL)
2117 return emulate_gp(ctxt, 0);
8c604352 2118
1a18a69b
AK		 2119 /*
2120 * Not recognized on AMD in compat mode (but is recognized in legacy
2121 * mode).
2122 */
2123 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2124 && !vendor_intel(ctxt))
2125 return emulate_ud(ctxt);
2126
8c604352
AP		 2127 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2128 * Therefore, we inject an #UD.
2129 */
35d3d4a1
AK		 2130 if (ctxt->mode == X86EMUL_MODE_PROT64)
2131 return emulate_ud(ctxt);
8c604352 2132
7b105ca2 2133 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2134
717746e3 2135 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2136 switch (ctxt->mode) {
2137 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2138 if ((msr_data & 0xfffc) == 0x0)
2139 return emulate_gp(ctxt, 0);
8c604352
AP		 2140 break;
2141 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2142 if (msr_data == 0x0)
2143 return emulate_gp(ctxt, 0);
8c604352
AP		 2144 break;
2145 }
2146
2147 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2148 cs_sel = (u16)msr_data;
2149 cs_sel &= ~SELECTOR_RPL_MASK;
2150 ss_sel = cs_sel + 8;
2151 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2152 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2153 cs.d = 0;
8c604352
AP		 2154 cs.l = 1;
2155 }
2156
1aa36616
AK		 2157 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2158 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2159
717746e3 2160 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2161 ctxt->_eip = msr_data;
8c604352 2162
717746e3 2163 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2164 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2165
e54cfa97 2166 return X86EMUL_CONTINUE;
8c604352
AP		 2167}
2168
e01991e7 2169static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2170{
7b105ca2 2171 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2172 struct desc_struct cs, ss;
4668f050
AP		 2173 u64 msr_data;
2174 int usermode;
1249b96e 2175 u16 cs_sel = 0, ss_sel = 0;
4668f050 2176
a0044755
GN		 2177 /* inject #GP if in real mode or Virtual 8086 mode */
2178 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2179 ctxt->mode == X86EMUL_MODE_VM86)
2180 return emulate_gp(ctxt, 0);
4668f050 2181
7b105ca2 2182 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2183
9dac77fa 2184 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2185 usermode = X86EMUL_MODE_PROT64;
2186 else
2187 usermode = X86EMUL_MODE_PROT32;
2188
2189 cs.dpl = 3;
2190 ss.dpl = 3;
717746e3 2191 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2192 switch (usermode) {
2193 case X86EMUL_MODE_PROT32:
79168fd1 2194 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2195 if ((msr_data & 0xfffc) == 0x0)
2196 return emulate_gp(ctxt, 0);
79168fd1 2197 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2198 break;
2199 case X86EMUL_MODE_PROT64:
79168fd1 2200 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2201 if (msr_data == 0x0)
2202 return emulate_gp(ctxt, 0);
79168fd1
GN		 2203 ss_sel = cs_sel + 8;
2204 cs.d = 0;
4668f050
AP		 2205 cs.l = 1;
2206 break;
2207 }
79168fd1
GN		 2208 cs_sel |= SELECTOR_RPL_MASK;
2209 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2210
1aa36616
AK		 2211 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2212 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2213
9dac77fa
AK		 2214 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2215 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2216
e54cfa97 2217 return X86EMUL_CONTINUE;
4668f050
AP		 2218}
2219
7b105ca2 2220static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2221{
2222 int iopl;
2223 if (ctxt->mode == X86EMUL_MODE_REAL)
2224 return false;
2225 if (ctxt->mode == X86EMUL_MODE_VM86)
2226 return true;
2227 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2228 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2229}
2230
2231static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2232 u16 port, u16 len)
2233{
7b105ca2 2234 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2235 struct desc_struct tr_seg;
5601d05b 2236 u32 base3;
f850e2e6 2237 int r;
1aa36616 2238 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2239 unsigned mask = (1 << len) - 1;
5601d05b 2240 unsigned long base;
f850e2e6 2241
1aa36616 2242 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2243 if (!tr_seg.p)
f850e2e6 2244 return false;
79168fd1 2245 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2246 return false;
5601d05b
GN		 2247 base = get_desc_base(&tr_seg);
2248#ifdef CONFIG_X86_64
2249 base |= ((u64)base3) << 32;
2250#endif
0f65dd70 2251 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2252 if (r != X86EMUL_CONTINUE)
2253 return false;
79168fd1 2254 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2255 return false;
0f65dd70 2256 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2257 if (r != X86EMUL_CONTINUE)
2258 return false;
2259 if ((perm >> bit_idx) & mask)
2260 return false;
2261 return true;
2262}
2263
2264static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2265 u16 port, u16 len)
2266{
4fc40f07
GN		 2267 if (ctxt->perm_ok)
2268 return true;
2269
7b105ca2
TY		 2270 if (emulator_bad_iopl(ctxt))
2271 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2272 return false;
4fc40f07
GN		 2273
2274 ctxt->perm_ok = true;
2275
f850e2e6
GN		 2276 return true;
2277}
2278
38ba30ba 2279static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2280 struct tss_segment_16 *tss)
2281{
9dac77fa 2282 tss->ip = ctxt->_eip;
38ba30ba 2283 tss->flag = ctxt->eflags;
9dac77fa
AK		 2284 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2285 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2286 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2287 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2288 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2289 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2290 tss->si = ctxt->regs[VCPU_REGS_RSI];
2291 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2292
1aa36616
AK		 2293 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2294 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2295 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2296 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2297 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2298}
2299
2300static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2301 struct tss_segment_16 *tss)
2302{
38ba30ba
GN		 2303 int ret;
2304
9dac77fa 2305 ctxt->_eip = tss->ip;
38ba30ba 2306 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2307 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2308 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2309 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2310 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2311 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2312 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2313 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2314 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2315
2316 /*
2317 * SDM says that segment selectors are loaded before segment
2318 * descriptors
2319 */
1aa36616
AK		 2320 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2321 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2322 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2323 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2324 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2325
2326 /*
2327 * Now load segment descriptors. If fault happenes at this stage
2328 * it is handled in a context of new task
2329 */
7b105ca2 2330 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2331 if (ret != X86EMUL_CONTINUE)
2332 return ret;
7b105ca2 2333 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2334 if (ret != X86EMUL_CONTINUE)
2335 return ret;
7b105ca2 2336 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2337 if (ret != X86EMUL_CONTINUE)
2338 return ret;
7b105ca2 2339 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2340 if (ret != X86EMUL_CONTINUE)
2341 return ret;
7b105ca2 2342 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2343 if (ret != X86EMUL_CONTINUE)
2344 return ret;
2345
2346 return X86EMUL_CONTINUE;
2347}
2348
2349static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2350 u16 tss_selector, u16 old_tss_sel,
2351 ulong old_tss_base, struct desc_struct *new_desc)
2352{
7b105ca2 2353 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2354 struct tss_segment_16 tss_seg;
2355 int ret;
bcc55cba 2356 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2357
0f65dd70 2358 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2359 &ctxt->exception);
db297e3d 2360 if (ret != X86EMUL_CONTINUE)
38ba30ba 2361 /* FIXME: need to provide precise fault address */
38ba30ba 2362 return ret;
38ba30ba 2363
7b105ca2 2364 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2365
0f65dd70 2366 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2367 &ctxt->exception);
db297e3d 2368 if (ret != X86EMUL_CONTINUE)
38ba30ba 2369 /* FIXME: need to provide precise fault address */
38ba30ba 2370 return ret;
38ba30ba 2371
0f65dd70 2372 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2373 &ctxt->exception);
db297e3d 2374 if (ret != X86EMUL_CONTINUE)
38ba30ba 2375 /* FIXME: need to provide precise fault address */
38ba30ba 2376 return ret;
38ba30ba
GN		 2377
2378 if (old_tss_sel != 0xffff) {
2379 tss_seg.prev_task_link = old_tss_sel;
2380
0f65dd70 2381 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2382 &tss_seg.prev_task_link,
2383 sizeof tss_seg.prev_task_link,
0f65dd70 2384 &ctxt->exception);
db297e3d 2385 if (ret != X86EMUL_CONTINUE)
38ba30ba 2386 /* FIXME: need to provide precise fault address */
38ba30ba 2387 return ret;
38ba30ba
GN		 2388 }
2389
7b105ca2 2390 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2391}
2392
2393static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2394 struct tss_segment_32 *tss)
2395{
7b105ca2 2396 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2397 tss->eip = ctxt->_eip;
38ba30ba 2398 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2399 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2400 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2401 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2402 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2403 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2404 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2405 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2406 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2407
1aa36616
AK		 2408 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2409 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2410 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2411 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2412 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2413 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2414 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2415}
2416
2417static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2418 struct tss_segment_32 *tss)
2419{
38ba30ba
GN		 2420 int ret;
2421
7b105ca2 2422 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2423 return emulate_gp(ctxt, 0);
9dac77fa 2424 ctxt->_eip = tss->eip;
38ba30ba 2425 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2426
2427 /* General purpose registers */
9dac77fa
AK		 2428 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2429 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2430 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2431 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2432 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2433 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2434 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2435 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2436
2437 /*
2438 * SDM says that segment selectors are loaded before segment
2439 * descriptors
2440 */
1aa36616
AK		 2441 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2442 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2443 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2444 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2445 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2446 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2447 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2448
4cee4798
KW		 2449 /*
2450 * If we're switching between Protected Mode and VM86, we need to make
2451 * sure to update the mode before loading the segment descriptors so
2452 * that the selectors are interpreted correctly.
2453 *
2454 * Need to get rflags to the vcpu struct immediately because it
2455 * influences the CPL which is checked at least when loading the segment
2456 * descriptors and when pushing an error code to the new kernel stack.
2457 *
2458 * TODO Introduce a separate ctxt->ops->set_cpl callback
2459 */
2460 if (ctxt->eflags & X86_EFLAGS_VM)
2461 ctxt->mode = X86EMUL_MODE_VM86;
2462 else
2463 ctxt->mode = X86EMUL_MODE_PROT32;
2464
2465 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2466
38ba30ba
GN		 2467 /*
2468 * Now load segment descriptors. If fault happenes at this stage
2469 * it is handled in a context of new task
2470 */
7b105ca2 2471 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2472 if (ret != X86EMUL_CONTINUE)
2473 return ret;
7b105ca2 2474 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2475 if (ret != X86EMUL_CONTINUE)
2476 return ret;
7b105ca2 2477 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2478 if (ret != X86EMUL_CONTINUE)
2479 return ret;
7b105ca2 2480 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2481 if (ret != X86EMUL_CONTINUE)
2482 return ret;
7b105ca2 2483 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2484 if (ret != X86EMUL_CONTINUE)
2485 return ret;
7b105ca2 2486 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2487 if (ret != X86EMUL_CONTINUE)
2488 return ret;
7b105ca2 2489 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2490 if (ret != X86EMUL_CONTINUE)
2491 return ret;
2492
2493 return X86EMUL_CONTINUE;
2494}
2495
2496static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2497 u16 tss_selector, u16 old_tss_sel,
2498 ulong old_tss_base, struct desc_struct *new_desc)
2499{
7b105ca2 2500 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2501 struct tss_segment_32 tss_seg;
2502 int ret;
bcc55cba 2503 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2504
0f65dd70 2505 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2506 &ctxt->exception);
db297e3d 2507 if (ret != X86EMUL_CONTINUE)
38ba30ba 2508 /* FIXME: need to provide precise fault address */
38ba30ba 2509 return ret;
38ba30ba 2510
7b105ca2 2511 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2512
0f65dd70 2513 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2514 &ctxt->exception);
db297e3d 2515 if (ret != X86EMUL_CONTINUE)
38ba30ba 2516 /* FIXME: need to provide precise fault address */
38ba30ba 2517 return ret;
38ba30ba 2518
0f65dd70 2519 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2520 &ctxt->exception);
db297e3d 2521 if (ret != X86EMUL_CONTINUE)
38ba30ba 2522 /* FIXME: need to provide precise fault address */
38ba30ba 2523 return ret;
38ba30ba
GN		 2524
2525 if (old_tss_sel != 0xffff) {
2526 tss_seg.prev_task_link = old_tss_sel;
2527
0f65dd70 2528 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2529 &tss_seg.prev_task_link,
2530 sizeof tss_seg.prev_task_link,
0f65dd70 2531 &ctxt->exception);
db297e3d 2532 if (ret != X86EMUL_CONTINUE)
38ba30ba 2533 /* FIXME: need to provide precise fault address */
38ba30ba 2534 return ret;
38ba30ba
GN		 2535 }
2536
7b105ca2 2537 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2538}
2539
2540static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2541 u16 tss_selector, int idt_index, int reason,
e269fb21 2542 bool has_error_code, u32 error_code)
38ba30ba 2543{
7b105ca2 2544 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2545 struct desc_struct curr_tss_desc, next_tss_desc;
2546 int ret;
1aa36616 2547 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2548 ulong old_tss_base =
4bff1e86 2549 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2550 u32 desc_limit;
38ba30ba
GN		 2551
2552 /* FIXME: old_tss_base == ~0 ? */
2553
7b105ca2 2554 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2555 if (ret != X86EMUL_CONTINUE)
2556 return ret;
7b105ca2 2557 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2558 if (ret != X86EMUL_CONTINUE)
2559 return ret;
2560
2561 /* FIXME: check that next_tss_desc is tss */
2562
7f3d35fd
KW		 2563 /*
2564 * Check privileges. The three cases are task switch caused by...
2565 *
2566 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2567 * 2. Exception/IRQ/iret: No check is performed
2568 * 3. jmp/call to TSS: Check agains DPL of the TSS
2569 */
2570 if (reason == TASK_SWITCH_GATE) {
2571 if (idt_index != -1) {
2572 /* Software interrupts */
2573 struct desc_struct task_gate_desc;
2574 int dpl;
2575
2576 ret = read_interrupt_descriptor(ctxt, idt_index,
2577 &task_gate_desc);
2578 if (ret != X86EMUL_CONTINUE)
2579 return ret;
2580
2581 dpl = task_gate_desc.dpl;
2582 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2583 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2584 }
2585 } else if (reason != TASK_SWITCH_IRET) {
2586 int dpl = next_tss_desc.dpl;
2587 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2588 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2589 }
2590
7f3d35fd 2591
ceffb459
GN		 2592 desc_limit = desc_limit_scaled(&next_tss_desc);
2593 if (!next_tss_desc.p ||
2594 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2595 desc_limit < 0x2b)) {
54b8486f 2596 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2597 return X86EMUL_PROPAGATE_FAULT;
2598 }
2599
2600 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2601 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2602 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2603 }
2604
2605 if (reason == TASK_SWITCH_IRET)
2606 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2607
2608 /* set back link to prev task only if NT bit is set in eflags
2609 note that old_tss_sel is not used afetr this point */
2610 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2611 old_tss_sel = 0xffff;
2612
2613 if (next_tss_desc.type & 8)
7b105ca2 2614 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2615 old_tss_base, &next_tss_desc);
2616 else
7b105ca2 2617 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2618 old_tss_base, &next_tss_desc);
0760d448
JK		 2619 if (ret != X86EMUL_CONTINUE)
2620 return ret;
38ba30ba
GN		 2621
2622 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2623 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2624
2625 if (reason != TASK_SWITCH_IRET) {
2626 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2627 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2628 }
2629
717746e3 2630 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2631 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2632
e269fb21 2633 if (has_error_code) {
9dac77fa
AK		 2634 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2635 ctxt->lock_prefix = 0;
2636 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2637 ret = em_push(ctxt);
e269fb21
JK		 2638 }
2639
38ba30ba
GN		 2640 return ret;
2641}
2642
2643int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2644 u16 tss_selector, int idt_index, int reason,
e269fb21 2645 bool has_error_code, u32 error_code)
38ba30ba 2646{
38ba30ba
GN		 2647 int rc;
2648
9dac77fa
AK		 2649 ctxt->_eip = ctxt->eip;
2650 ctxt->dst.type = OP_NONE;
38ba30ba 2651
7f3d35fd 2652 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2653 has_error_code, error_code);
38ba30ba 2654
4179bb02 2655 if (rc == X86EMUL_CONTINUE)
9dac77fa 2656 ctxt->eip = ctxt->_eip;
38ba30ba 2657
a0c0ab2f 2658 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2659}
2660
90de84f5 2661static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2662 int reg, struct operand *op)
a682e354 2663{
a682e354
GN		 2664 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2665
9dac77fa
AK		 2666 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2667 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2668 op->addr.mem.seg = seg;
a682e354
GN		 2669}
2670
7af04fc0
AK		 2671static int em_das(struct x86_emulate_ctxt *ctxt)
2672{
7af04fc0
AK		 2673 u8 al, old_al;
2674 bool af, cf, old_cf;
2675
2676 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2677 al = ctxt->dst.val;
7af04fc0
AK		 2678
2679 old_al = al;
2680 old_cf = cf;
2681 cf = false;
2682 af = ctxt->eflags & X86_EFLAGS_AF;
2683 if ((al & 0x0f) > 9 || af) {
2684 al -= 6;
2685 cf = old_cf | (al >= 250);
2686 af = true;
2687 } else {
2688 af = false;
2689 }
2690 if (old_al > 0x99 || old_cf) {
2691 al -= 0x60;
2692 cf = true;
2693 }
2694
9dac77fa 2695 ctxt->dst.val = al;
7af04fc0 2696 /* Set PF, ZF, SF */
9dac77fa
AK		 2697 ctxt->src.type = OP_IMM;
2698 ctxt->src.val = 0;
2699 ctxt->src.bytes = 1;
a31b9cea 2700 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2701 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2702 if (cf)
2703 ctxt->eflags |= X86_EFLAGS_CF;
2704 if (af)
2705 ctxt->eflags |= X86_EFLAGS_AF;
2706 return X86EMUL_CONTINUE;
2707}
2708
d4ddafcd
TY		 2709static int em_call(struct x86_emulate_ctxt *ctxt)
2710{
2711 long rel = ctxt->src.val;
2712
2713 ctxt->src.val = (unsigned long)ctxt->_eip;
2714 jmp_rel(ctxt, rel);
2715 return em_push(ctxt);
2716}
2717
0ef753b8
AK		 2718static int em_call_far(struct x86_emulate_ctxt *ctxt)
2719{
0ef753b8
AK		 2720 u16 sel, old_cs;
2721 ulong old_eip;
2722 int rc;
2723
1aa36616 2724 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2725 old_eip = ctxt->_eip;
0ef753b8 2726
9dac77fa 2727 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2728 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2729 return X86EMUL_CONTINUE;
2730
9dac77fa
AK		 2731 ctxt->_eip = 0;
2732 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2733
9dac77fa 2734 ctxt->src.val = old_cs;
4487b3b4 2735 rc = em_push(ctxt);
0ef753b8
AK		 2736 if (rc != X86EMUL_CONTINUE)
2737 return rc;
2738
9dac77fa 2739 ctxt->src.val = old_eip;
4487b3b4 2740 return em_push(ctxt);
0ef753b8
AK		 2741}
2742
40ece7c7
AK		 2743static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2744{
40ece7c7
AK		 2745 int rc;
2746
9dac77fa
AK		 2747 ctxt->dst.type = OP_REG;
2748 ctxt->dst.addr.reg = &ctxt->_eip;
2749 ctxt->dst.bytes = ctxt->op_bytes;
2750 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2751 if (rc != X86EMUL_CONTINUE)
2752 return rc;
9dac77fa 2753 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2754 return X86EMUL_CONTINUE;
2755}
2756
d67fc27a
TY		 2757static int em_add(struct x86_emulate_ctxt *ctxt)
2758{
a31b9cea 2759 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2760 return X86EMUL_CONTINUE;
2761}
2762
2763static int em_or(struct x86_emulate_ctxt *ctxt)
2764{
a31b9cea 2765 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2766 return X86EMUL_CONTINUE;
2767}
2768
2769static int em_adc(struct x86_emulate_ctxt *ctxt)
2770{
a31b9cea 2771 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2772 return X86EMUL_CONTINUE;
2773}
2774
2775static int em_sbb(struct x86_emulate_ctxt *ctxt)
2776{
a31b9cea 2777 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2778 return X86EMUL_CONTINUE;
2779}
2780
2781static int em_and(struct x86_emulate_ctxt *ctxt)
2782{
a31b9cea 2783 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2784 return X86EMUL_CONTINUE;
2785}
2786
2787static int em_sub(struct x86_emulate_ctxt *ctxt)
2788{
a31b9cea 2789 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2790 return X86EMUL_CONTINUE;
2791}
2792
2793static int em_xor(struct x86_emulate_ctxt *ctxt)
2794{
a31b9cea 2795 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2796 return X86EMUL_CONTINUE;
2797}
2798
2799static int em_cmp(struct x86_emulate_ctxt *ctxt)
2800{
a31b9cea 2801 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2802 /* Disable writeback. */
9dac77fa 2803 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2804 return X86EMUL_CONTINUE;
2805}
2806
9f21ca59
TY		 2807static int em_test(struct x86_emulate_ctxt *ctxt)
2808{
a31b9cea 2809 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2810 /* Disable writeback. */
2811 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2812 return X86EMUL_CONTINUE;
2813}
2814
e4f973ae
TY		 2815static int em_xchg(struct x86_emulate_ctxt *ctxt)
2816{
e4f973ae 2817 /* Write back the register source. */
9dac77fa
AK		 2818 ctxt->src.val = ctxt->dst.val;
2819 write_register_operand(&ctxt->src);
e4f973ae
TY		 2820
2821 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2822 ctxt->dst.val = ctxt->src.orig_val;
2823 ctxt->lock_prefix = 1;
e4f973ae
TY		 2824 return X86EMUL_CONTINUE;
2825}
2826
5c82aa29 2827static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2828{
a31b9cea 2829 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2830 return X86EMUL_CONTINUE;
2831}
2832
5c82aa29
AK		 2833static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2834{
9dac77fa 2835 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2836 return em_imul(ctxt);
2837}
2838
61429142
AK		 2839static int em_cwd(struct x86_emulate_ctxt *ctxt)
2840{
9dac77fa
AK		 2841 ctxt->dst.type = OP_REG;
2842 ctxt->dst.bytes = ctxt->src.bytes;
2843 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2844 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2845
2846 return X86EMUL_CONTINUE;
2847}
2848
48bb5d3c
AK		 2849static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2850{
48bb5d3c
AK		 2851 u64 tsc = 0;
2852
717746e3 2853 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2854 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2855 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2856 return X86EMUL_CONTINUE;
2857}
2858
222d21aa
AK		 2859static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2860{
2861 u64 pmc;
2862
2863 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2864 return emulate_gp(ctxt, 0);
2865 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2866 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2867 return X86EMUL_CONTINUE;
2868}
2869
b9eac5f4
AK		 2870static int em_mov(struct x86_emulate_ctxt *ctxt)
2871{
49597d81 2872 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2873 return X86EMUL_CONTINUE;
2874}
2875
bc00f8d2
TY		 2876static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2877{
2878 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2879 return emulate_gp(ctxt, 0);
2880
2881 /* Disable writeback. */
2882 ctxt->dst.type = OP_NONE;
2883 return X86EMUL_CONTINUE;
2884}
2885
2886static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2887{
2888 unsigned long val;
2889
2890 if (ctxt->mode == X86EMUL_MODE_PROT64)
2891 val = ctxt->src.val & ~0ULL;
2892 else
2893 val = ctxt->src.val & ~0U;
2894
2895 /* #UD condition is already handled. */
2896 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2897 return emulate_gp(ctxt, 0);
2898
2899 /* Disable writeback. */
2900 ctxt->dst.type = OP_NONE;
2901 return X86EMUL_CONTINUE;
2902}
2903
e1e210b0
TY		 2904static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2905{
2906 u64 msr_data;
2907
2908 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2909 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2910 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2911 return emulate_gp(ctxt, 0);
2912
2913 return X86EMUL_CONTINUE;
2914}
2915
2916static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2917{
2918 u64 msr_data;
2919
2920 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2921 return emulate_gp(ctxt, 0);
2922
2923 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2924 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2925 return X86EMUL_CONTINUE;
2926}
2927
1bd5f469
TY		 2928static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2929{
9dac77fa 2930 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2931 return emulate_ud(ctxt);
2932
9dac77fa 2933 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2934 return X86EMUL_CONTINUE;
2935}
2936
2937static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2938{
9dac77fa 2939 u16 sel = ctxt->src.val;
1bd5f469 2940
9dac77fa 2941 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2942 return emulate_ud(ctxt);
2943
9dac77fa 2944 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2945 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2946
2947 /* Disable writeback. */
9dac77fa
AK		 2948 ctxt->dst.type = OP_NONE;
2949 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2950}
2951
38503911
AK		 2952static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2953{
9fa088f4
AK		 2954 int rc;
2955 ulong linear;
2956
9dac77fa 2957 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2958 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2959 ctxt->ops->invlpg(ctxt, linear);
38503911 2960 /* Disable writeback. */
9dac77fa 2961 ctxt->dst.type = OP_NONE;
38503911
AK		 2962 return X86EMUL_CONTINUE;
2963}
2964
2d04a05b
AK		 2965static int em_clts(struct x86_emulate_ctxt *ctxt)
2966{
2967 ulong cr0;
2968
2969 cr0 = ctxt->ops->get_cr(ctxt, 0);
2970 cr0 &= ~X86_CR0_TS;
2971 ctxt->ops->set_cr(ctxt, 0, cr0);
2972 return X86EMUL_CONTINUE;
2973}
2974
26d05cc7
AK		 2975static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2976{
26d05cc7
AK		 2977 int rc;
2978
9dac77fa 2979 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2980 return X86EMUL_UNHANDLEABLE;
2981
2982 rc = ctxt->ops->fix_hypercall(ctxt);
2983 if (rc != X86EMUL_CONTINUE)
2984 return rc;
2985
2986 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2987 ctxt->_eip = ctxt->eip;
26d05cc7 2988 /* Disable writeback. */
9dac77fa 2989 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2990 return X86EMUL_CONTINUE;
2991}
2992
2993static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2994{
26d05cc7
AK		 2995 struct desc_ptr desc_ptr;
2996 int rc;
2997
9dac77fa 2998 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2999 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3000 ctxt->op_bytes);
26d05cc7
AK		 3001 if (rc != X86EMUL_CONTINUE)
3002 return rc;
3003 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3004 /* Disable writeback. */
9dac77fa 3005 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3006 return X86EMUL_CONTINUE;
3007}
3008
5ef39c71 3009static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3010{
26d05cc7
AK		 3011 int rc;
3012
5ef39c71
AK		 3013 rc = ctxt->ops->fix_hypercall(ctxt);
3014
26d05cc7 3015 /* Disable writeback. */
9dac77fa 3016 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3017 return rc;
3018}
3019
3020static int em_lidt(struct x86_emulate_ctxt *ctxt)
3021{
26d05cc7
AK		 3022 struct desc_ptr desc_ptr;
3023 int rc;
3024
9dac77fa 3025 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3026 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3027 ctxt->op_bytes);
26d05cc7
AK		 3028 if (rc != X86EMUL_CONTINUE)
3029 return rc;
3030 ctxt->ops->set_idt(ctxt, &desc_ptr);
3031 /* Disable writeback. */
9dac77fa 3032 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3033 return X86EMUL_CONTINUE;
3034}
3035
3036static int em_smsw(struct x86_emulate_ctxt *ctxt)
3037{
9dac77fa
AK		 3038 ctxt->dst.bytes = 2;
3039 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3040 return X86EMUL_CONTINUE;
3041}
3042
3043static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3044{
26d05cc7 3045 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3046 | (ctxt->src.val & 0x0f));
3047 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3048 return X86EMUL_CONTINUE;
3049}
3050
d06e03ad
TY		 3051static int em_loop(struct x86_emulate_ctxt *ctxt)
3052{
9dac77fa
AK		 3053 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3054 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3055 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3056 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3057
3058 return X86EMUL_CONTINUE;
3059}
3060
3061static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3062{
9dac77fa
AK		 3063 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3064 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3065
3066 return X86EMUL_CONTINUE;
3067}
3068
d7841a4b
TY		 3069static int em_in(struct x86_emulate_ctxt *ctxt)
3070{
3071 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3072 &ctxt->dst.val))
3073 return X86EMUL_IO_NEEDED;
3074
3075 return X86EMUL_CONTINUE;
3076}
3077
3078static int em_out(struct x86_emulate_ctxt *ctxt)
3079{
3080 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3081 &ctxt->src.val, 1);
3082 /* Disable writeback. */
3083 ctxt->dst.type = OP_NONE;
3084 return X86EMUL_CONTINUE;
3085}
3086
f411e6cd
TY		 3087static int em_cli(struct x86_emulate_ctxt *ctxt)
3088{
3089 if (emulator_bad_iopl(ctxt))
3090 return emulate_gp(ctxt, 0);
3091
3092 ctxt->eflags &= ~X86_EFLAGS_IF;
3093 return X86EMUL_CONTINUE;
3094}
3095
3096static int em_sti(struct x86_emulate_ctxt *ctxt)
3097{
3098 if (emulator_bad_iopl(ctxt))
3099 return emulate_gp(ctxt, 0);
3100
3101 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3102 ctxt->eflags |= X86_EFLAGS_IF;
3103 return X86EMUL_CONTINUE;
3104}
3105
ce7faab2
TY		 3106static int em_bt(struct x86_emulate_ctxt *ctxt)
3107{
3108 /* Disable writeback. */
3109 ctxt->dst.type = OP_NONE;
3110 /* only subword offset */
3111 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3112
3113 emulate_2op_SrcV_nobyte(ctxt, "bt");
3114 return X86EMUL_CONTINUE;
3115}
3116
3117static int em_bts(struct x86_emulate_ctxt *ctxt)
3118{
3119 emulate_2op_SrcV_nobyte(ctxt, "bts");
3120 return X86EMUL_CONTINUE;
3121}
3122
3123static int em_btr(struct x86_emulate_ctxt *ctxt)
3124{
3125 emulate_2op_SrcV_nobyte(ctxt, "btr");
3126 return X86EMUL_CONTINUE;
3127}
3128
3129static int em_btc(struct x86_emulate_ctxt *ctxt)
3130{
3131 emulate_2op_SrcV_nobyte(ctxt, "btc");
3132 return X86EMUL_CONTINUE;
3133}
3134
ff227392
TY		 3135static int em_bsf(struct x86_emulate_ctxt *ctxt)
3136{
3137 u8 zf;
3138
3139 __asm__ ("bsf %2, %0; setz %1"
3140 : "=r"(ctxt->dst.val), "=q"(zf)
3141 : "r"(ctxt->src.val));
3142
3143 ctxt->eflags &= ~X86_EFLAGS_ZF;
3144 if (zf) {
3145 ctxt->eflags |= X86_EFLAGS_ZF;
3146 /* Disable writeback. */
3147 ctxt->dst.type = OP_NONE;
3148 }
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int em_bsr(struct x86_emulate_ctxt *ctxt)
3153{
3154 u8 zf;
3155
3156 __asm__ ("bsr %2, %0; setz %1"
3157 : "=r"(ctxt->dst.val), "=q"(zf)
3158 : "r"(ctxt->src.val));
3159
3160 ctxt->eflags &= ~X86_EFLAGS_ZF;
3161 if (zf) {
3162 ctxt->eflags |= X86_EFLAGS_ZF;
3163 /* Disable writeback. */
3164 ctxt->dst.type = OP_NONE;
3165 }
3166 return X86EMUL_CONTINUE;
3167}
3168
cfec82cb
JR		 3169static bool valid_cr(int nr)
3170{
3171 switch (nr) {
3172 case 0:
3173 case 2 ... 4:
3174 case 8:
3175 return true;
3176 default:
3177 return false;
3178 }
3179}
3180
3181static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3182{
9dac77fa 3183 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3184 return emulate_ud(ctxt);
3185
3186 return X86EMUL_CONTINUE;
3187}
3188
3189static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3190{
9dac77fa
AK		 3191 u64 new_val = ctxt->src.val64;
3192 int cr = ctxt->modrm_reg;
c2ad2bb3 3193 u64 efer = 0;
cfec82cb
JR		 3194
3195 static u64 cr_reserved_bits[] = {
3196 0xffffffff00000000ULL,
3197 0, 0, 0, /* CR3 checked later */
3198 CR4_RESERVED_BITS,
3199 0, 0, 0,
3200 CR8_RESERVED_BITS,
3201 };
3202
3203 if (!valid_cr(cr))
3204 return emulate_ud(ctxt);
3205
3206 if (new_val & cr_reserved_bits[cr])
3207 return emulate_gp(ctxt, 0);
3208
3209 switch (cr) {
3210 case 0: {
c2ad2bb3 3211 u64 cr4;
cfec82cb
JR		 3212 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3213 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3214 return emulate_gp(ctxt, 0);
3215
717746e3
AK		 3216 cr4 = ctxt->ops->get_cr(ctxt, 4);
3217 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3218
3219 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3220 !(cr4 & X86_CR4_PAE))
3221 return emulate_gp(ctxt, 0);
3222
3223 break;
3224 }
3225 case 3: {
3226 u64 rsvd = 0;
3227
c2ad2bb3
AK		 3228 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3229 if (efer & EFER_LMA)
cfec82cb 3230 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3231 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3232 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3233 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3234 rsvd = CR3_NONPAE_RESERVED_BITS;
3235
3236 if (new_val & rsvd)
3237 return emulate_gp(ctxt, 0);
3238
3239 break;
3240 }
3241 case 4: {
717746e3 3242 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3243
3244 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3245 return emulate_gp(ctxt, 0);
3246
3247 break;
3248 }
3249 }
3250
3251 return X86EMUL_CONTINUE;
3252}
3253
3b88e41a
JR		 3254static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3255{
3256 unsigned long dr7;
3257
717746e3 3258 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3259
3260 /* Check if DR7.Global_Enable is set */
3261 return dr7 & (1 << 13);
3262}
3263
3264static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3265{
9dac77fa 3266 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3267 u64 cr4;
3268
3269 if (dr > 7)
3270 return emulate_ud(ctxt);
3271
717746e3 3272 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3273 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3274 return emulate_ud(ctxt);
3275
3276 if (check_dr7_gd(ctxt))
3277 return emulate_db(ctxt);
3278
3279 return X86EMUL_CONTINUE;
3280}
3281
3282static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3283{
9dac77fa
AK		 3284 u64 new_val = ctxt->src.val64;
3285 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3286
3287 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3288 return emulate_gp(ctxt, 0);
3289
3290 return check_dr_read(ctxt);
3291}
3292
01de8b09
JR		 3293static int check_svme(struct x86_emulate_ctxt *ctxt)
3294{
3295 u64 efer;
3296
717746e3 3297 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3298
3299 if (!(efer & EFER_SVME))
3300 return emulate_ud(ctxt);
3301
3302 return X86EMUL_CONTINUE;
3303}
3304
3305static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3306{
9dac77fa 3307 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3308
3309 /* Valid physical address? */
d4224449 3310 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3311 return emulate_gp(ctxt, 0);
3312
3313 return check_svme(ctxt);
3314}
3315
d7eb8203
JR		 3316static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3317{
717746e3 3318 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3319
717746e3 3320 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3321 return emulate_ud(ctxt);
3322
3323 return X86EMUL_CONTINUE;
3324}
3325
8061252e
JR		 3326static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3327{
717746e3 3328 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3329 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3330
717746e3 3331 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3332 (rcx > 3))
3333 return emulate_gp(ctxt, 0);
3334
3335 return X86EMUL_CONTINUE;
3336}
3337
f6511935
JR		 3338static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3339{
9dac77fa
AK		 3340 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3341 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3342 return emulate_gp(ctxt, 0);
3343
3344 return X86EMUL_CONTINUE;
3345}
3346
3347static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3348{
9dac77fa
AK		 3349 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3350 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3351 return emulate_gp(ctxt, 0);
3352
3353 return X86EMUL_CONTINUE;
3354}
3355
73fba5f4 3356#define D(_y) { .flags = (_y) }
c4f035c6 3357#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3358#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3359 .check_perm = (_p) }
73fba5f4 3360#define N D(0)
01de8b09 3361#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 3362#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3363#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3364#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3365#define II(_f, _e, _i) \
3366 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3367#define IIP(_f, _e, _i, _p) \
3368 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3369 .check_perm = (_p) }
aa97bb48 3370#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3371
8d8f4e9f 3372#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3373#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3374#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3375#define I2bvIP(_f, _e, _i, _p) \
3376 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3377
d67fc27a
TY		 3378#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3379 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3380 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3381
d7eb8203
JR		 3382static struct opcode group7_rm1[] = {
3383 DI(SrcNone | ModRM | Priv, monitor),
3384 DI(SrcNone | ModRM | Priv, mwait),
3385 N, N, N, N, N, N,
3386};
3387
01de8b09
JR		 3388static struct opcode group7_rm3[] = {
3389 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3390 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3391 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3392 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3393 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3394 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3395 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3396 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3397};
6230f7fc 3398
d7eb8203
JR		 3399static struct opcode group7_rm7[] = {
3400 N,
3401 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3402 N, N, N, N, N, N,
3403};
d67fc27a 3404
73fba5f4 3405static struct opcode group1[] = {
d67fc27a 3406 I(Lock, em_add),
d5ae7ce8 3407 I(Lock | PageTable, em_or),
d67fc27a
TY		 3408 I(Lock, em_adc),
3409 I(Lock, em_sbb),
d5ae7ce8 3410 I(Lock | PageTable, em_and),
d67fc27a
TY		 3411 I(Lock, em_sub),
3412 I(Lock, em_xor),
3413 I(0, em_cmp),
73fba5f4
AK		 3414};
3415
3416static struct opcode group1A[] = {
c15af35f 3417 I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3418};
3419
3420static struct opcode group3[] = {
3329ece1
AK		 3421 I(DstMem | SrcImm | ModRM, em_test),
3422 I(DstMem | SrcImm | ModRM, em_test),
3423 I(DstMem | SrcNone | ModRM | Lock, em_not),
3424 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3425 I(SrcMem | ModRM, em_mul_ex),
3426 I(SrcMem | ModRM, em_imul_ex),
3427 I(SrcMem | ModRM, em_div_ex),
3428 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3429};
3430
3431static struct opcode group4[] = {
c04ec839
TY		 3432 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
3433 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
73fba5f4
AK		 3434 N, N, N, N, N, N,
3435};
3436
3437static struct opcode group5[] = {
c04ec839
TY		 3438 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3439 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3440 I(SrcMem | ModRM | Stack, em_grp45),
0ef753b8 3441 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
c04ec839
TY		 3442 I(SrcMem | ModRM | Stack, em_grp45),
3443 I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45),
3444 I(SrcMem | ModRM | Stack, em_grp45), N,
73fba5f4
AK		 3445};
3446
dee6bb70
JR		 3447static struct opcode group6[] = {
3448 DI(ModRM | Prot, sldt),
3449 DI(ModRM | Prot, str),
3450 DI(ModRM | Prot | Priv, lldt),
3451 DI(ModRM | Prot | Priv, ltr),
3452 N, N, N, N,
3453};
3454
73fba5f4 3455static struct group_dual group7 = { {
dee6bb70
JR		 3456 DI(ModRM | Mov | DstMem | Priv, sgdt),
3457 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3458 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3459 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3460 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3461 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3462 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3463}, {
5ef39c71
AK		 3464 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3465 EXT(0, group7_rm1),
01de8b09 3466 N, EXT(0, group7_rm3),
5ef39c71
AK		 3467 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3468 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3469} };
3470
3471static struct opcode group8[] = {
3472 N, N, N, N,
ce7faab2
TY		 3473 I(DstMem | SrcImmByte | ModRM, em_bt),
3474 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts),
3475 I(DstMem | SrcImmByte | ModRM | Lock, em_btr),
3476 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc),
73fba5f4
AK		 3477};
3478
3479static struct group_dual group9 = { {
e0dac408 3480 N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3481}, {
3482 N, N, N, N, N, N, N, N,
3483} };
3484
a4d4a7c1 3485static struct opcode group11[] = {
d5ae7ce8
XG		 3486 I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov),
3487 X7(D(Undefined)),
a4d4a7c1
AK		 3488};
3489
aa97bb48 3490static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3491 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3492};
3493
3e114eb4
AK		 3494static struct gprefix pfx_vmovntpx = {
3495 I(0, em_mov), N, N, N,
3496};
3497
73fba5f4
AK		 3498static struct opcode opcode_table[256] = {
3499 /* 0x00 - 0x07 */
d67fc27a 3500 I6ALU(Lock, em_add),
1cd196ea
AK		 3501 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3502 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3503 /* 0x08 - 0x0F */
d5ae7ce8 3504 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3505 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3506 N,
73fba5f4 3507 /* 0x10 - 0x17 */
d67fc27a 3508 I6ALU(Lock, em_adc),
1cd196ea
AK		 3509 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3510 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3511 /* 0x18 - 0x1F */
d67fc27a 3512 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3513 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3514 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3515 /* 0x20 - 0x27 */
d5ae7ce8 3516 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3517 /* 0x28 - 0x2F */
d67fc27a 3518 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3519 /* 0x30 - 0x37 */
d67fc27a 3520 I6ALU(Lock, em_xor), N, N,
73fba5f4 3521 /* 0x38 - 0x3F */
d67fc27a 3522 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3523 /* 0x40 - 0x4F */
3524 X16(D(DstReg)),
3525 /* 0x50 - 0x57 */
63540382 3526 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3527 /* 0x58 - 0x5F */
c54fe504 3528 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3529 /* 0x60 - 0x67 */
b96a7fad
TY		 3530 I(ImplicitOps | Stack | No64, em_pusha),
3531 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3532 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3533 N, N, N, N,
3534 /* 0x68 - 0x6F */
d46164db
AK		 3535 I(SrcImm | Mov | Stack, em_push),
3536 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3537 I(SrcImmByte | Mov | Stack, em_push),
3538 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3539 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3540 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3541 /* 0x70 - 0x7F */
3542 X16(D(SrcImmByte)),
3543 /* 0x80 - 0x87 */
3544 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3545 G(DstMem | SrcImm | ModRM | Group, group1),
3546 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3547 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3548 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3549 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3550 /* 0x88 - 0x8F */
d5ae7ce8 3551 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3552 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3553 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3554 D(ModRM | SrcMem | NoAccess | DstReg),
3555 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3556 G(0, group1A),
73fba5f4 3557 /* 0x90 - 0x97 */
bf608f88 3558 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3559 /* 0x98 - 0x9F */
61429142 3560 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3561 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3562 II(ImplicitOps | Stack, em_pushf, pushf),
3563 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3564 /* 0xA0 - 0xA7 */
b9eac5f4 3565 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3566 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3567 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3568 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3569 /* 0xA8 - 0xAF */
9f21ca59 3570 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3571 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3572 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3573 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3574 /* 0xB0 - 0xB7 */
b9eac5f4 3575 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3576 /* 0xB8 - 0xBF */
b9eac5f4 3577 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3578 /* 0xC0 - 0xC7 */
d2c6c7ad 3579 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3580 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3581 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3582 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3583 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3584 G(ByteOp, group11), G(0, group11),
73fba5f4 3585 /* 0xC8 - 0xCF */
db5b0762 3586 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3587 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3588 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3589 /* 0xD0 - 0xD7 */
d2c6c7ad 3590 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3591 N, N, N, N,
3592 /* 0xD8 - 0xDF */
3593 N, N, N, N, N, N, N, N,
3594 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3595 X3(I(SrcImmByte, em_loop)),
3596 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3597 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3598 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3599 /* 0xE8 - 0xEF */
d4ddafcd 3600 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3601 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3602 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3603 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3604 /* 0xF0 - 0xF7 */
bf608f88 3605 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3606 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3607 G(ByteOp, group3), G(0, group3),
73fba5f4 3608 /* 0xF8 - 0xFF */
f411e6cd
TY		 3609 D(ImplicitOps), D(ImplicitOps),
3610 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3611 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3612};
3613
3614static struct opcode twobyte_table[256] = {
3615 /* 0x00 - 0x0F */
dee6bb70 3616 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3617 N, I(ImplicitOps | VendorSpecific, em_syscall),
3618 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3619 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3620 N, D(ImplicitOps | ModRM), N, N,
3621 /* 0x10 - 0x1F */
3622 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3623 /* 0x20 - 0x2F */
cfec82cb 3624 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3625 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3626 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3627 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3628 N, N, N, N,
3e114eb4
AK		 3629 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3630 N, N, N, N,
73fba5f4 3631 /* 0x30 - 0x3F */
e1e210b0 3632 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3633 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3634 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3635 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3636 I(ImplicitOps | VendorSpecific, em_sysenter),
3637 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3638 N, N,
73fba5f4
AK		 3639 N, N, N, N, N, N, N, N,
3640 /* 0x40 - 0x4F */
3641 X16(D(DstReg | SrcMem | ModRM | Mov)),
3642 /* 0x50 - 0x5F */
3643 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3644 /* 0x60 - 0x6F */
aa97bb48
AK		 3645 N, N, N, N,
3646 N, N, N, N,
3647 N, N, N, N,
3648 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3649 /* 0x70 - 0x7F */
aa97bb48
AK		 3650 N, N, N, N,
3651 N, N, N, N,
3652 N, N, N, N,
3653 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3654 /* 0x80 - 0x8F */
3655 X16(D(SrcImm)),
3656 /* 0x90 - 0x9F */
ee45b58e 3657 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3658 /* 0xA0 - 0xA7 */
1cd196ea 3659 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
ce7faab2 3660 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3661 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3662 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3663 /* 0xA8 - 0xAF */
1cd196ea 3664 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3665 DI(ImplicitOps, rsm),
ce7faab2 3666 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3667 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3668 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3669 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3670 /* 0xB0 - 0xB7 */
e940b5c2 3671 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3672 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3673 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3674 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3675 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3676 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3677 /* 0xB8 - 0xBF */
3678 N, N,
ce7faab2
TY		 3679 G(BitOp, group8),
3680 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3681 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3682 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3683 /* 0xC0 - 0xCF */
739ae406 3684 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3685 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3686 N, N, N, GD(0, &group9),
3687 N, N, N, N, N, N, N, N,
3688 /* 0xD0 - 0xDF */
3689 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3690 /* 0xE0 - 0xEF */
3691 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3692 /* 0xF0 - 0xFF */
3693 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3694};
3695
3696#undef D
3697#undef N
3698#undef G
3699#undef GD
3700#undef I
aa97bb48 3701#undef GP
01de8b09 3702#undef EXT
73fba5f4 3703
8d8f4e9f 3704#undef D2bv
f6511935 3705#undef D2bvIP
8d8f4e9f 3706#undef I2bv
d7841a4b 3707#undef I2bvIP
d67fc27a 3708#undef I6ALU
8d8f4e9f 3709
9dac77fa 3710static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3711{
3712 unsigned size;
3713
9dac77fa 3714 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3715 if (size == 8)
3716 size = 4;
3717 return size;
3718}
3719
3720static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3721 unsigned size, bool sign_extension)
3722{
39f21ee5
AK		 3723 int rc = X86EMUL_CONTINUE;
3724
3725 op->type = OP_IMM;
3726 op->bytes = size;
9dac77fa 3727 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3728 /* NB. Immediates are sign-extended as necessary. */
3729 switch (op->bytes) {
3730 case 1:
e85a1085 3731 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3732 break;
3733 case 2:
e85a1085 3734 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3735 break;
3736 case 4:
e85a1085 3737 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3738 break;
3739 }
3740 if (!sign_extension) {
3741 switch (op->bytes) {
3742 case 1:
3743 op->val &= 0xff;
3744 break;
3745 case 2:
3746 op->val &= 0xffff;
3747 break;
3748 case 4:
3749 op->val &= 0xffffffff;
3750 break;
3751 }
3752 }
3753done:
3754 return rc;
3755}
3756
a9945549
AK		 3757static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3758 unsigned d)
3759{
3760 int rc = X86EMUL_CONTINUE;
3761
3762 switch (d) {
3763 case OpReg:
2adb5ad9 3764 decode_register_operand(ctxt, op);
a9945549
AK		 3765 break;
3766 case OpImmUByte:
608aabe3 3767 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3768 break;
3769 case OpMem:
41ddf978 3770 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3771 mem_common:
3772 *op = ctxt->memop;
3773 ctxt->memopp = op;
3774 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3775 fetch_bit_operand(ctxt);
3776 op->orig_val = op->val;
3777 break;
41ddf978
AK		 3778 case OpMem64:
3779 ctxt->memop.bytes = 8;
3780 goto mem_common;
a9945549
AK		 3781 case OpAcc:
3782 op->type = OP_REG;
3783 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3784 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3785 fetch_register_operand(op);
3786 op->orig_val = op->val;
3787 break;
3788 case OpDI:
3789 op->type = OP_MEM;
3790 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3791 op->addr.mem.ea =
3792 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3793 op->addr.mem.seg = VCPU_SREG_ES;
3794 op->val = 0;
3795 break;
3796 case OpDX:
3797 op->type = OP_REG;
3798 op->bytes = 2;
3799 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3800 fetch_register_operand(op);
3801 break;
4dd6a57d
AK		 3802 case OpCL:
3803 op->bytes = 1;
3804 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3805 break;
3806 case OpImmByte:
3807 rc = decode_imm(ctxt, op, 1, true);
3808 break;
3809 case OpOne:
3810 op->bytes = 1;
3811 op->val = 1;
3812 break;
3813 case OpImm:
3814 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3815 break;
28867cee
AK		 3816 case OpMem8:
3817 ctxt->memop.bytes = 1;
3818 goto mem_common;
0fe59128
AK		 3819 case OpMem16:
3820 ctxt->memop.bytes = 2;
3821 goto mem_common;
3822 case OpMem32:
3823 ctxt->memop.bytes = 4;
3824 goto mem_common;
3825 case OpImmU16:
3826 rc = decode_imm(ctxt, op, 2, false);
3827 break;
3828 case OpImmU:
3829 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3830 break;
3831 case OpSI:
3832 op->type = OP_MEM;
3833 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3834 op->addr.mem.ea =
3835 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3836 op->addr.mem.seg = seg_override(ctxt);
3837 op->val = 0;
3838 break;
3839 case OpImmFAddr:
3840 op->type = OP_IMM;
3841 op->addr.mem.ea = ctxt->_eip;
3842 op->bytes = ctxt->op_bytes + 2;
3843 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3844 break;
3845 case OpMemFAddr:
3846 ctxt->memop.bytes = ctxt->op_bytes + 2;
3847 goto mem_common;
c191a7a0
AK		 3848 case OpES:
3849 op->val = VCPU_SREG_ES;
3850 break;
3851 case OpCS:
3852 op->val = VCPU_SREG_CS;
3853 break;
3854 case OpSS:
3855 op->val = VCPU_SREG_SS;
3856 break;
3857 case OpDS:
3858 op->val = VCPU_SREG_DS;
3859 break;
3860 case OpFS:
3861 op->val = VCPU_SREG_FS;
3862 break;
3863 case OpGS:
3864 op->val = VCPU_SREG_GS;
3865 break;
a9945549
AK		 3866 case OpImplicit:
3867 /* Special instructions do their own operand decoding. */
3868 default:
3869 op->type = OP_NONE; /* Disable writeback. */
3870 break;
3871 }
3872
3873done:
3874 return rc;
3875}
3876
ef5d75cc 3877int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3878{
dde7e6d1
AK		 3879 int rc = X86EMUL_CONTINUE;
3880 int mode = ctxt->mode;
46561646 3881 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3882 bool op_prefix = false;
46561646 3883 struct opcode opcode;
dde7e6d1 3884
f09ed83e
AK		 3885 ctxt->memop.type = OP_NONE;
3886 ctxt->memopp = NULL;
9dac77fa
AK		 3887 ctxt->_eip = ctxt->eip;
3888 ctxt->fetch.start = ctxt->_eip;
3889 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3890 if (insn_len > 0)
9dac77fa 3891 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3892
3893 switch (mode) {
3894 case X86EMUL_MODE_REAL:
3895 case X86EMUL_MODE_VM86:
3896 case X86EMUL_MODE_PROT16:
3897 def_op_bytes = def_ad_bytes = 2;
3898 break;
3899 case X86EMUL_MODE_PROT32:
3900 def_op_bytes = def_ad_bytes = 4;
3901 break;
3902#ifdef CONFIG_X86_64
3903 case X86EMUL_MODE_PROT64:
3904 def_op_bytes = 4;
3905 def_ad_bytes = 8;
3906 break;
3907#endif
3908 default:
1d2887e2 3909 return EMULATION_FAILED;
dde7e6d1
AK		 3910 }
3911
9dac77fa
AK		 3912 ctxt->op_bytes = def_op_bytes;
3913 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3914
3915 /* Legacy prefixes. */
3916 for (;;) {
e85a1085 3917 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3918 case 0x66: /* operand-size override */
0d7cdee8 3919 op_prefix = true;
dde7e6d1 3920 /* switch between 2/4 bytes */
9dac77fa 3921 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3922 break;
3923 case 0x67: /* address-size override */
3924 if (mode == X86EMUL_MODE_PROT64)
3925 /* switch between 4/8 bytes */
9dac77fa 3926 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3927 else
3928 /* switch between 2/4 bytes */
9dac77fa 3929 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3930 break;
3931 case 0x26: /* ES override */
3932 case 0x2e: /* CS override */
3933 case 0x36: /* SS override */
3934 case 0x3e: /* DS override */
9dac77fa 3935 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3936 break;
3937 case 0x64: /* FS override */
3938 case 0x65: /* GS override */
9dac77fa 3939 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3940 break;
3941 case 0x40 ... 0x4f: /* REX */
3942 if (mode != X86EMUL_MODE_PROT64)
3943 goto done_prefixes;
9dac77fa 3944 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3945 continue;
3946 case 0xf0: /* LOCK */
9dac77fa 3947 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3948 break;
3949 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3950 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3951 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3952 break;
3953 default:
3954 goto done_prefixes;
3955 }
3956
3957 /* Any legacy prefix after a REX prefix nullifies its effect. */
3958
9dac77fa 3959 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3960 }
3961
3962done_prefixes:
3963
3964 /* REX prefix. */
9dac77fa
AK		 3965 if (ctxt->rex_prefix & 8)
3966 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3967
3968 /* Opcode byte(s). */
9dac77fa 3969 opcode = opcode_table[ctxt->b];
d3ad6243 3970 /* Two-byte opcode? */
9dac77fa
AK		 3971 if (ctxt->b == 0x0f) {
3972 ctxt->twobyte = 1;
e85a1085 3973 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3974 opcode = twobyte_table[ctxt->b];
dde7e6d1 3975 }
9dac77fa 3976 ctxt->d = opcode.flags;
dde7e6d1 3977
9dac77fa
AK		 3978 while (ctxt->d & GroupMask) {
3979 switch (ctxt->d & GroupMask) {
46561646 3980 case Group:
e85a1085 3981 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3982 --ctxt->_eip;
3983 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3984 opcode = opcode.u.group[goffset];
3985 break;
3986 case GroupDual:
e85a1085 3987 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3988 --ctxt->_eip;
3989 goffset = (ctxt->modrm >> 3) & 7;
3990 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3991 opcode = opcode.u.gdual->mod3[goffset];
3992 else
3993 opcode = opcode.u.gdual->mod012[goffset];
3994 break;
3995 case RMExt:
9dac77fa 3996 goffset = ctxt->modrm & 7;
01de8b09 3997 opcode = opcode.u.group[goffset];
46561646
AK		 3998 break;
3999 case Prefix:
9dac77fa 4000 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4001 return EMULATION_FAILED;
9dac77fa 4002 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4003 switch (simd_prefix) {
4004 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4005 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4006 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4007 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4008 }
4009 break;
4010 default:
1d2887e2 4011 return EMULATION_FAILED;
0d7cdee8 4012 }
46561646 4013
b1ea50b2 4014 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4015 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4016 }
4017
9dac77fa
AK		 4018 ctxt->execute = opcode.u.execute;
4019 ctxt->check_perm = opcode.check_perm;
4020 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4021
4022 /* Unrecognised? */
9dac77fa 4023 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4024 return EMULATION_FAILED;
dde7e6d1 4025
9dac77fa 4026 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4027 return EMULATION_FAILED;
d867162c 4028
9dac77fa
AK		 4029 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4030 ctxt->op_bytes = 8;
dde7e6d1 4031
9dac77fa 4032 if (ctxt->d & Op3264) {
7f9b4b75 4033 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4034 ctxt->op_bytes = 8;
7f9b4b75 4035 else
9dac77fa 4036 ctxt->op_bytes = 4;
7f9b4b75
AK		 4037 }
4038
9dac77fa
AK		 4039 if (ctxt->d & Sse)
4040 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4041 else if (ctxt->d & Mmx)
4042 ctxt->op_bytes = 8;
1253791d 4043
dde7e6d1 4044 /* ModRM and SIB bytes. */
9dac77fa 4045 if (ctxt->d & ModRM) {
f09ed83e 4046 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4047 if (!ctxt->has_seg_override)
4048 set_seg_override(ctxt, ctxt->modrm_seg);
4049 } else if (ctxt->d & MemAbs)
f09ed83e 4050 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4051 if (rc != X86EMUL_CONTINUE)
4052 goto done;
4053
9dac77fa
AK		 4054 if (!ctxt->has_seg_override)
4055 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4056
f09ed83e 4057 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4058
f09ed83e
AK		 4059 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4060 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4061
dde7e6d1
AK		 4062 /*
4063 * Decode and fetch the source operand: register, memory
4064 * or immediate.
4065 */
0fe59128 4066 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4067 if (rc != X86EMUL_CONTINUE)
4068 goto done;
4069
dde7e6d1
AK		 4070 /*
4071 * Decode and fetch the second source operand: register, memory
4072 * or immediate.
4073 */
4dd6a57d 4074 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4075 if (rc != X86EMUL_CONTINUE)
4076 goto done;
4077
dde7e6d1 4078 /* Decode and fetch the destination operand: register or memory. */
a9945549 4079 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4080
4081done:
f09ed83e
AK		 4082 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4083 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4084
1d2887e2 4085 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4086}
4087
1cb3f3ae
XG		 4088bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4089{
4090 return ctxt->d & PageTable;
4091}
4092
3e2f65d5
GN		 4093static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4094{
3e2f65d5
GN		 4095 /* The second termination condition only applies for REPE
4096 * and REPNE. Test if the repeat string operation prefix is
4097 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4098 * corresponding termination condition according to:
4099 * - if REPE/REPZ and ZF = 0 then done
4100 * - if REPNE/REPNZ and ZF = 1 then done
4101 */
9dac77fa
AK		 4102 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4103 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4104 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4105 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4106 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4107 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4108 return true;
4109
4110 return false;
4111}
4112
cbe2c9d3
AK		 4113static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4114{
4115 bool fault = false;
4116
4117 ctxt->ops->get_fpu(ctxt);
4118 asm volatile("1: fwait \n\t"
4119 "2: \n\t"
4120 ".pushsection .fixup,\"ax\" \n\t"
4121 "3: \n\t"
4122 "movb $1, %[fault] \n\t"
4123 "jmp 2b \n\t"
4124 ".popsection \n\t"
4125 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4126 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4127 ctxt->ops->put_fpu(ctxt);
4128
4129 if (unlikely(fault))
4130 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4131
4132 return X86EMUL_CONTINUE;
4133}
4134
4135static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4136 struct operand *op)
4137{
4138 if (op->type == OP_MM)
4139 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4140}
4141
7b105ca2 4142int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4143{
9aabc88f 4144 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4145 int rc = X86EMUL_CONTINUE;
9dac77fa 4146 int saved_dst_type = ctxt->dst.type;
8b4caf66 4147
9dac77fa 4148 ctxt->mem_read.pos = 0;
310b5d30 4149
9dac77fa 4150 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4151 rc = emulate_ud(ctxt);
1161624f
GN		 4152 goto done;
4153 }
4154
d380a5e4 4155 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4156 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4157 rc = emulate_ud(ctxt);
d380a5e4
GN		 4158 goto done;
4159 }
4160
9dac77fa 4161 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4162 rc = emulate_ud(ctxt);
081bca0e
AK		 4163 goto done;
4164 }
4165
cbe2c9d3
AK		 4166 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4167 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4168 rc = emulate_ud(ctxt);
4169 goto done;
4170 }
4171
cbe2c9d3 4172 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4173 rc = emulate_nm(ctxt);
4174 goto done;
4175 }
4176
cbe2c9d3
AK		 4177 if (ctxt->d & Mmx) {
4178 rc = flush_pending_x87_faults(ctxt);
4179 if (rc != X86EMUL_CONTINUE)
4180 goto done;
4181 /*
4182 * Now that we know the fpu is exception safe, we can fetch
4183 * operands from it.
4184 */
4185 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4186 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4187 if (!(ctxt->d & Mov))
4188 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4189 }
4190
9dac77fa
AK		 4191 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4192 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4193 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4194 if (rc != X86EMUL_CONTINUE)
4195 goto done;
4196 }
4197
e92805ac 4198 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4199 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4200 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4201 goto done;
4202 }
4203
8ea7d6ae 4204 /* Instruction can only be executed in protected mode */
9dac77fa 4205 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4206 rc = emulate_ud(ctxt);
4207 goto done;
4208 }
4209
d09beabd 4210 /* Do instruction specific permission checks */
9dac77fa
AK		 4211 if (ctxt->check_perm) {
4212 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4213 if (rc != X86EMUL_CONTINUE)
4214 goto done;
4215 }
4216
9dac77fa
AK		 4217 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4218 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4219 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4220 if (rc != X86EMUL_CONTINUE)
4221 goto done;
4222 }
4223
9dac77fa 4224 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4225 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4226 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4227 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4228 goto done;
4229 }
b9fa9d6b
AK		 4230 }
4231
9dac77fa
AK		 4232 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4233 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4234 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4235 if (rc != X86EMUL_CONTINUE)
8b4caf66 4236 goto done;
9dac77fa 4237 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4238 }
4239
9dac77fa
AK		 4240 if (ctxt->src2.type == OP_MEM) {
4241 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4242 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4243 if (rc != X86EMUL_CONTINUE)
4244 goto done;
4245 }
4246
9dac77fa 4247 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4248 goto special_insn;
4249
4250
9dac77fa 4251 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4252 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4253 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4254 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4255 if (rc != X86EMUL_CONTINUE)
4256 goto done;
038e51de 4257 }
9dac77fa 4258 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4259
018a98db
AK		 4260special_insn:
4261
9dac77fa
AK		 4262 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4263 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4264 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4265 if (rc != X86EMUL_CONTINUE)
4266 goto done;
4267 }
4268
9dac77fa
AK		 4269 if (ctxt->execute) {
4270 rc = ctxt->execute(ctxt);
ef65c889
AK		 4271 if (rc != X86EMUL_CONTINUE)
4272 goto done;
4273 goto writeback;
4274 }
4275
9dac77fa 4276 if (ctxt->twobyte)
6aa8b732
AK		 4277 goto twobyte_insn;
4278
9dac77fa 4279 switch (ctxt->b) {
33615aa9 4280 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4281 emulate_1op(ctxt, "inc");
33615aa9
AK		 4282 break;
4283 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4284 emulate_1op(ctxt, "dec");
33615aa9 4285 break;
6aa8b732 4286 case 0x63: /* movsxd */
8b4caf66 4287 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4288 goto cannot_emulate;
9dac77fa 4289 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4290 break;
b2833e3c 4291 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4292 if (test_cc(ctxt->b, ctxt->eflags))
4293 jmp_rel(ctxt, ctxt->src.val);
018a98db 4294 break;
7e0b54b1 4295 case 0x8d: /* lea r16/r32, m */
9dac77fa 4296 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4297 break;
3d9e77df 4298 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4299 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4300 break;
e4f973ae
TY		 4301 rc = em_xchg(ctxt);
4302 break;
e8b6fa70 4303 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4304 switch (ctxt->op_bytes) {
4305 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4306 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4307 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4308 }
4309 break;
018a98db 4310 case 0xc0 ... 0xc1:
51187683 4311 rc = em_grp2(ctxt);
018a98db 4312 break;
6e154e56 4313 case 0xcc: /* int3 */
5c5df76b
TY		 4314 rc = emulate_int(ctxt, 3);
4315 break;
6e154e56 4316 case 0xcd: /* int n */
9dac77fa 4317 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4318 break;
4319 case 0xce: /* into */
5c5df76b
TY		 4320 if (ctxt->eflags & EFLG_OF)
4321 rc = emulate_int(ctxt, 4);
6e154e56 4322 break;
018a98db 4323 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4324 rc = em_grp2(ctxt);
018a98db
AK		 4325 break;
4326 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4327 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4328 rc = em_grp2(ctxt);
018a98db 4329 break;
1a52e051 4330 case 0xe9: /* jmp rel */
db5b0762 4331 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4332 jmp_rel(ctxt, ctxt->src.val);
4333 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4334 break;
111de5d6 4335 case 0xf4: /* hlt */
6c3287f7 4336 ctxt->ops->halt(ctxt);
19fdfa0d 4337 break;
111de5d6
AK		 4338 case 0xf5: /* cmc */
4339 /* complement carry flag from eflags reg */
4340 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4341 break;
4342 case 0xf8: /* clc */
4343 ctxt->eflags &= ~EFLG_CF;
111de5d6 4344 break;
8744aa9a
MG		 4345 case 0xf9: /* stc */
4346 ctxt->eflags |= EFLG_CF;
4347 break;
fb4616f4
MG		 4348 case 0xfc: /* cld */
4349 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4350 break;
4351 case 0xfd: /* std */
4352 ctxt->eflags |= EFLG_DF;
fb4616f4 4353 break;
91269b8f
AK		 4354 default:
4355 goto cannot_emulate;
6aa8b732 4356 }
018a98db 4357
7d9ddaed
AK		 4358 if (rc != X86EMUL_CONTINUE)
4359 goto done;
4360
018a98db 4361writeback:
adddcecf 4362 rc = writeback(ctxt);
1b30eaa8 4363 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4364 goto done;
4365
5cd21917
GN		 4366 /*
4367 * restore dst type in case the decoding will be reused
4368 * (happens for string instruction )
4369 */
9dac77fa 4370 ctxt->dst.type = saved_dst_type;
5cd21917 4371
9dac77fa
AK		 4372 if ((ctxt->d & SrcMask) == SrcSI)
4373 string_addr_inc(ctxt, seg_override(ctxt),
4374 VCPU_REGS_RSI, &ctxt->src);
a682e354 4375
9dac77fa 4376 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4377 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4378 &ctxt->dst);
d9271123 4379
9dac77fa
AK		 4380 if (ctxt->rep_prefix && (ctxt->d & String)) {
4381 struct read_cache *r = &ctxt->io_read;
4382 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4383
d2ddd1c4
GN		 4384 if (!string_insn_completed(ctxt)) {
4385 /*
4386 * Re-enter guest when pio read ahead buffer is empty
4387 * or, if it is not used, after each 1024 iteration.
4388 */
9dac77fa 4389 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4390 (r->end == 0 || r->end != r->pos)) {
4391 /*
4392 * Reset read cache. Usually happens before
4393 * decode, but since instruction is restarted
4394 * we have to do it here.
4395 */
9dac77fa 4396 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4397 return EMULATION_RESTART;
4398 }
4399 goto done; /* skip rip writeback */
0fa6ccbd 4400 }
5cd21917 4401 }
d2ddd1c4 4402
9dac77fa 4403 ctxt->eip = ctxt->_eip;
018a98db
AK		 4404
4405done:
da9cb575
AK		 4406 if (rc == X86EMUL_PROPAGATE_FAULT)
4407 ctxt->have_exception = true;
775fde86
JR		 4408 if (rc == X86EMUL_INTERCEPTED)
4409 return EMULATION_INTERCEPTED;
4410
d2ddd1c4 4411 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4412
4413twobyte_insn:
9dac77fa 4414 switch (ctxt->b) {
018a98db 4415 case 0x09: /* wbinvd */
cfb22375 4416 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4417 break;
4418 case 0x08: /* invd */
018a98db
AK		 4419 case 0x0d: /* GrpP (prefetch) */
4420 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4421 break;
4422 case 0x20: /* mov cr, reg */
9dac77fa 4423 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4424 break;
6aa8b732 4425 case 0x21: /* mov from dr to reg */
9dac77fa 4426 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4427 break;
6aa8b732 4428 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4429 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4430 if (!test_cc(ctxt->b, ctxt->eflags))
4431 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4432 break;
b2833e3c 4433 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4434 if (test_cc(ctxt->b, ctxt->eflags))
4435 jmp_rel(ctxt, ctxt->src.val);
018a98db 4436 break;
ee45b58e 4437 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4438 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4439 break;
9bf8ea42
GT		 4440 case 0xa4: /* shld imm8, r, r/m */
4441 case 0xa5: /* shld cl, r, r/m */
761441b9 4442 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4443 break;
9bf8ea42
GT		 4444 case 0xac: /* shrd imm8, r, r/m */
4445 case 0xad: /* shrd cl, r, r/m */
761441b9 4446 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4447 break;
2a7c5b8b
GC		 4448 case 0xae: /* clflush */
4449 break;
6aa8b732 4450 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4451 ctxt->dst.bytes = ctxt->op_bytes;
4452 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4453 : (u16) ctxt->src.val;
6aa8b732 4454 break;
6aa8b732 4455 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4456 ctxt->dst.bytes = ctxt->op_bytes;
4457 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4458 (s16) ctxt->src.val;
6aa8b732 4459 break;
92f738a5 4460 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4461 emulate_2op_SrcV(ctxt, "add");
92f738a5 4462 /* Write back the register source. */
9dac77fa
AK		 4463 ctxt->src.val = ctxt->dst.orig_val;
4464 write_register_operand(&ctxt->src);
92f738a5 4465 break;
a012e65a 4466 case 0xc3: /* movnti */
9dac77fa
AK		 4467 ctxt->dst.bytes = ctxt->op_bytes;
4468 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4469 (u64) ctxt->src.val;
a012e65a 4470 break;
91269b8f
AK		 4471 default:
4472 goto cannot_emulate;
6aa8b732 4473 }
7d9ddaed
AK		 4474
4475 if (rc != X86EMUL_CONTINUE)
4476 goto done;
4477
6aa8b732
AK		 4478 goto writeback;
4479
4480cannot_emulate:
a0c0ab2f 4481 return EMULATION_FAILED;
6aa8b732 4482}
Linux kernel - Deliverables
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