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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
a9945549 AK |
31 | /* |
32 | * Operand types | |
33 | */ | |
b1ea50b2 AK |
34 | #define OpNone 0ull |
35 | #define OpImplicit 1ull /* No generic decode */ | |
36 | #define OpReg 2ull /* Register */ | |
37 | #define OpMem 3ull /* Memory */ | |
38 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
39 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
40 | #define OpMem64 6ull /* Memory, 64-bit */ | |
41 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
42 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
43 | #define OpCL 9ull /* CL register (for shifts) */ |
44 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
45 | #define OpOne 11ull /* Implied 1 */ | |
46 | #define OpImm 12ull /* Sign extended immediate */ | |
0fe59128 AK |
47 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
48 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
49 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
50 | #define OpSI 16ull /* SI/ESI/RSI */ | |
51 | #define OpImmFAddr 17ull /* Immediate far address */ | |
52 | #define OpMemFAddr 18ull /* Far address in memory */ | |
53 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
54 | #define OpES 20ull /* ES */ |
55 | #define OpCS 21ull /* CS */ | |
56 | #define OpSS 22ull /* SS */ | |
57 | #define OpDS 23ull /* DS */ | |
58 | #define OpFS 24ull /* FS */ | |
59 | #define OpGS 25ull /* GS */ | |
28867cee | 60 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
0fe59128 AK |
61 | |
62 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 63 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 64 | |
6aa8b732 AK |
65 | /* |
66 | * Opcode effective-address decode tables. | |
67 | * Note that we only emulate instructions that have at least one memory | |
68 | * operand (excluding implicit stack references). We assume that stack | |
69 | * references and instruction fetches will never occur in special memory | |
70 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
71 | * not be handled. | |
72 | */ | |
73 | ||
74 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 75 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 76 | /* Destination operand type. */ |
a9945549 AK |
77 | #define DstShift 1 |
78 | #define ImplicitOps (OpImplicit << DstShift) | |
79 | #define DstReg (OpReg << DstShift) | |
80 | #define DstMem (OpMem << DstShift) | |
81 | #define DstAcc (OpAcc << DstShift) | |
82 | #define DstDI (OpDI << DstShift) | |
83 | #define DstMem64 (OpMem64 << DstShift) | |
84 | #define DstImmUByte (OpImmUByte << DstShift) | |
85 | #define DstDX (OpDX << DstShift) | |
86 | #define DstMask (OpMask << DstShift) | |
6aa8b732 | 87 | /* Source operand type. */ |
0fe59128 AK |
88 | #define SrcShift 6 |
89 | #define SrcNone (OpNone << SrcShift) | |
90 | #define SrcReg (OpReg << SrcShift) | |
91 | #define SrcMem (OpMem << SrcShift) | |
92 | #define SrcMem16 (OpMem16 << SrcShift) | |
93 | #define SrcMem32 (OpMem32 << SrcShift) | |
94 | #define SrcImm (OpImm << SrcShift) | |
95 | #define SrcImmByte (OpImmByte << SrcShift) | |
96 | #define SrcOne (OpOne << SrcShift) | |
97 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
98 | #define SrcImmU (OpImmU << SrcShift) | |
99 | #define SrcSI (OpSI << SrcShift) | |
100 | #define SrcImmFAddr (OpImmFAddr << SrcShift) | |
101 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
102 | #define SrcAcc (OpAcc << SrcShift) | |
103 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
104 | #define SrcDX (OpDX << SrcShift) | |
28867cee | 105 | #define SrcMem8 (OpMem8 << SrcShift) |
0fe59128 | 106 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
107 | #define BitOp (1<<11) |
108 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
109 | #define String (1<<13) /* String instruction (rep capable) */ | |
110 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
111 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
112 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
113 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
114 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
115 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
116 | #define Sse (1<<18) /* SSE Vector instruction */ | |
20c29ff2 AK |
117 | /* Generic ModRM decode. */ |
118 | #define ModRM (1<<19) | |
119 | /* Destination is only written; never read. */ | |
120 | #define Mov (1<<20) | |
d8769fed | 121 | /* Misc flags */ |
8ea7d6ae | 122 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 123 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 124 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 125 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 126 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 127 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 128 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 129 | #define No64 (1<<28) |
d5ae7ce8 | 130 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0dc8d10f | 131 | /* Source 2 operand type */ |
d5ae7ce8 | 132 | #define Src2Shift (30) |
4dd6a57d AK |
133 | #define Src2None (OpNone << Src2Shift) |
134 | #define Src2CL (OpCL << Src2Shift) | |
135 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
136 | #define Src2One (OpOne << Src2Shift) | |
137 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
138 | #define Src2ES (OpES << Src2Shift) |
139 | #define Src2CS (OpCS << Src2Shift) | |
140 | #define Src2SS (OpSS << Src2Shift) | |
141 | #define Src2DS (OpDS << Src2Shift) | |
142 | #define Src2FS (OpFS << Src2Shift) | |
143 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 144 | #define Src2Mask (OpMask << Src2Shift) |
6aa8b732 | 145 | |
d0e53325 AK |
146 | #define X2(x...) x, x |
147 | #define X3(x...) X2(x), x | |
148 | #define X4(x...) X2(x), X2(x) | |
149 | #define X5(x...) X4(x), x | |
150 | #define X6(x...) X4(x), X2(x) | |
151 | #define X7(x...) X4(x), X3(x) | |
152 | #define X8(x...) X4(x), X4(x) | |
153 | #define X16(x...) X8(x), X8(x) | |
83babbca | 154 | |
d65b1dee | 155 | struct opcode { |
b1ea50b2 AK |
156 | u64 flags : 56; |
157 | u64 intercept : 8; | |
120df890 | 158 | union { |
ef65c889 | 159 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
160 | struct opcode *group; |
161 | struct group_dual *gdual; | |
0d7cdee8 | 162 | struct gprefix *gprefix; |
120df890 | 163 | } u; |
d09beabd | 164 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
165 | }; |
166 | ||
167 | struct group_dual { | |
168 | struct opcode mod012[8]; | |
169 | struct opcode mod3[8]; | |
d65b1dee AK |
170 | }; |
171 | ||
0d7cdee8 AK |
172 | struct gprefix { |
173 | struct opcode pfx_no; | |
174 | struct opcode pfx_66; | |
175 | struct opcode pfx_f2; | |
176 | struct opcode pfx_f3; | |
177 | }; | |
178 | ||
6aa8b732 | 179 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
180 | #define EFLG_ID (1<<21) |
181 | #define EFLG_VIP (1<<20) | |
182 | #define EFLG_VIF (1<<19) | |
183 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
184 | #define EFLG_VM (1<<17) |
185 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
186 | #define EFLG_IOPL (3<<12) |
187 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
188 | #define EFLG_OF (1<<11) |
189 | #define EFLG_DF (1<<10) | |
b1d86143 | 190 | #define EFLG_IF (1<<9) |
d4c6a154 | 191 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
192 | #define EFLG_SF (1<<7) |
193 | #define EFLG_ZF (1<<6) | |
194 | #define EFLG_AF (1<<4) | |
195 | #define EFLG_PF (1<<2) | |
196 | #define EFLG_CF (1<<0) | |
197 | ||
62bd430e MG |
198 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
199 | #define EFLG_RESERVED_ONE_MASK 2 | |
200 | ||
6aa8b732 AK |
201 | /* |
202 | * Instruction emulation: | |
203 | * Most instructions are emulated directly via a fragment of inline assembly | |
204 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
205 | * any modified flags. | |
206 | */ | |
207 | ||
05b3e0c2 | 208 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
209 | #define _LO32 "k" /* force 32-bit operand */ |
210 | #define _STK "%%rsp" /* stack pointer */ | |
211 | #elif defined(__i386__) | |
212 | #define _LO32 "" /* force 32-bit operand */ | |
213 | #define _STK "%%esp" /* stack pointer */ | |
214 | #endif | |
215 | ||
216 | /* | |
217 | * These EFLAGS bits are restored from saved value during emulation, and | |
218 | * any changes are written back to the saved value after emulation. | |
219 | */ | |
220 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
221 | ||
222 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
223 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
224 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
225 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
226 | "push %"_tmp"; " \ | |
227 | "push %"_tmp"; " \ | |
228 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
229 | "andl %"_LO32 _tmp",("_STK"); " \ | |
230 | "pushf; " \ | |
231 | "notl %"_LO32 _tmp"; " \ | |
232 | "andl %"_LO32 _tmp",("_STK"); " \ | |
233 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
234 | "pop %"_tmp"; " \ | |
235 | "orl %"_LO32 _tmp",("_STK"); " \ | |
236 | "popf; " \ | |
237 | "pop %"_sav"; " | |
6aa8b732 AK |
238 | |
239 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
240 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
241 | /* _sav |= EFLAGS & _msk; */ \ | |
242 | "pushf; " \ | |
243 | "pop %"_tmp"; " \ | |
244 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
245 | "orl %"_LO32 _tmp",%"_sav"; " | |
246 | ||
dda96d8f AK |
247 | #ifdef CONFIG_X86_64 |
248 | #define ON64(x) x | |
249 | #else | |
250 | #define ON64(x) | |
251 | #endif | |
252 | ||
a31b9cea | 253 | #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
254 | do { \ |
255 | __asm__ __volatile__ ( \ | |
256 | _PRE_EFLAGS("0", "4", "2") \ | |
257 | _op _suffix " %"_x"3,%1; " \ | |
258 | _POST_EFLAGS("0", "4", "2") \ | |
a31b9cea AK |
259 | : "=m" ((ctxt)->eflags), \ |
260 | "+q" (*(_dsttype*)&(ctxt)->dst.val), \ | |
6b7ad61f | 261 | "=&r" (_tmp) \ |
a31b9cea | 262 | : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ |
f3fd92fb | 263 | } while (0) |
6b7ad61f AK |
264 | |
265 | ||
6aa8b732 | 266 | /* Raw emulation: instruction has two explicit operands. */ |
a31b9cea | 267 | #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6b7ad61f AK |
268 | do { \ |
269 | unsigned long _tmp; \ | |
270 | \ | |
a31b9cea | 271 | switch ((ctxt)->dst.bytes) { \ |
6b7ad61f | 272 | case 2: \ |
a31b9cea | 273 | ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ |
6b7ad61f AK |
274 | break; \ |
275 | case 4: \ | |
a31b9cea | 276 | ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ |
6b7ad61f AK |
277 | break; \ |
278 | case 8: \ | |
a31b9cea | 279 | ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
280 | break; \ |
281 | } \ | |
6aa8b732 AK |
282 | } while (0) |
283 | ||
a31b9cea | 284 | #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6aa8b732 | 285 | do { \ |
6b7ad61f | 286 | unsigned long _tmp; \ |
a31b9cea | 287 | switch ((ctxt)->dst.bytes) { \ |
6aa8b732 | 288 | case 1: \ |
a31b9cea | 289 | ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ |
6aa8b732 AK |
290 | break; \ |
291 | default: \ | |
a31b9cea | 292 | __emulate_2op_nobyte(ctxt, _op, \ |
6aa8b732 AK |
293 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
294 | break; \ | |
295 | } \ | |
296 | } while (0) | |
297 | ||
298 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
a31b9cea AK |
299 | #define emulate_2op_SrcB(ctxt, _op) \ |
300 | __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") | |
6aa8b732 AK |
301 | |
302 | /* Source operand is byte, word, long or quad sized. */ | |
a31b9cea AK |
303 | #define emulate_2op_SrcV(ctxt, _op) \ |
304 | __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") | |
6aa8b732 AK |
305 | |
306 | /* Source operand is word, long or quad sized. */ | |
a31b9cea AK |
307 | #define emulate_2op_SrcV_nobyte(ctxt, _op) \ |
308 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | |
6aa8b732 | 309 | |
d175226a | 310 | /* Instruction has three operands and one operand is stored in ECX register */ |
29053a60 | 311 | #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ |
7295261c AK |
312 | do { \ |
313 | unsigned long _tmp; \ | |
761441b9 AK |
314 | _type _clv = (ctxt)->src2.val; \ |
315 | _type _srcv = (ctxt)->src.val; \ | |
316 | _type _dstv = (ctxt)->dst.val; \ | |
7295261c AK |
317 | \ |
318 | __asm__ __volatile__ ( \ | |
319 | _PRE_EFLAGS("0", "5", "2") \ | |
320 | _op _suffix " %4,%1 \n" \ | |
321 | _POST_EFLAGS("0", "5", "2") \ | |
761441b9 | 322 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
7295261c AK |
323 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
324 | ); \ | |
325 | \ | |
761441b9 AK |
326 | (ctxt)->src2.val = (unsigned long) _clv; \ |
327 | (ctxt)->src2.val = (unsigned long) _srcv; \ | |
328 | (ctxt)->dst.val = (unsigned long) _dstv; \ | |
d175226a GT |
329 | } while (0) |
330 | ||
761441b9 | 331 | #define emulate_2op_cl(ctxt, _op) \ |
7295261c | 332 | do { \ |
761441b9 | 333 | switch ((ctxt)->dst.bytes) { \ |
7295261c | 334 | case 2: \ |
29053a60 | 335 | __emulate_2op_cl(ctxt, _op, "w", u16); \ |
7295261c AK |
336 | break; \ |
337 | case 4: \ | |
29053a60 | 338 | __emulate_2op_cl(ctxt, _op, "l", u32); \ |
7295261c AK |
339 | break; \ |
340 | case 8: \ | |
29053a60 | 341 | ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ |
7295261c AK |
342 | break; \ |
343 | } \ | |
d175226a GT |
344 | } while (0) |
345 | ||
d1eef45d | 346 | #define __emulate_1op(ctxt, _op, _suffix) \ |
6aa8b732 AK |
347 | do { \ |
348 | unsigned long _tmp; \ | |
349 | \ | |
dda96d8f AK |
350 | __asm__ __volatile__ ( \ |
351 | _PRE_EFLAGS("0", "3", "2") \ | |
352 | _op _suffix " %1; " \ | |
353 | _POST_EFLAGS("0", "3", "2") \ | |
d1eef45d | 354 | : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ |
dda96d8f AK |
355 | "=&r" (_tmp) \ |
356 | : "i" (EFLAGS_MASK)); \ | |
357 | } while (0) | |
358 | ||
359 | /* Instruction has only one explicit operand (no source operand). */ | |
d1eef45d | 360 | #define emulate_1op(ctxt, _op) \ |
dda96d8f | 361 | do { \ |
d1eef45d AK |
362 | switch ((ctxt)->dst.bytes) { \ |
363 | case 1: __emulate_1op(ctxt, _op, "b"); break; \ | |
364 | case 2: __emulate_1op(ctxt, _op, "w"); break; \ | |
365 | case 4: __emulate_1op(ctxt, _op, "l"); break; \ | |
366 | case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ | |
6aa8b732 AK |
367 | } \ |
368 | } while (0) | |
369 | ||
e8f2b1d6 | 370 | #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ |
f6b3597b AK |
371 | do { \ |
372 | unsigned long _tmp; \ | |
e8f2b1d6 AK |
373 | ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \ |
374 | ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \ | |
f6b3597b AK |
375 | \ |
376 | __asm__ __volatile__ ( \ | |
377 | _PRE_EFLAGS("0", "5", "1") \ | |
378 | "1: \n\t" \ | |
379 | _op _suffix " %6; " \ | |
380 | "2: \n\t" \ | |
381 | _POST_EFLAGS("0", "5", "1") \ | |
382 | ".pushsection .fixup,\"ax\" \n\t" \ | |
383 | "3: movb $1, %4 \n\t" \ | |
384 | "jmp 2b \n\t" \ | |
385 | ".popsection \n\t" \ | |
386 | _ASM_EXTABLE(1b, 3b) \ | |
e8f2b1d6 AK |
387 | : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ |
388 | "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ | |
389 | : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ | |
390 | "a" (*rax), "d" (*rdx)); \ | |
f6b3597b AK |
391 | } while (0) |
392 | ||
3f9f53b0 | 393 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
e8f2b1d6 | 394 | #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ |
7295261c | 395 | do { \ |
e8f2b1d6 | 396 | switch((ctxt)->src.bytes) { \ |
7295261c | 397 | case 1: \ |
e8f2b1d6 | 398 | __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ |
7295261c AK |
399 | break; \ |
400 | case 2: \ | |
e8f2b1d6 | 401 | __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ |
7295261c AK |
402 | break; \ |
403 | case 4: \ | |
e8f2b1d6 | 404 | __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ |
f6b3597b AK |
405 | break; \ |
406 | case 8: ON64( \ | |
e8f2b1d6 | 407 | __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ |
f6b3597b AK |
408 | break; \ |
409 | } \ | |
410 | } while (0) | |
411 | ||
8a76d7f2 JR |
412 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
413 | enum x86_intercept intercept, | |
414 | enum x86_intercept_stage stage) | |
415 | { | |
416 | struct x86_instruction_info info = { | |
417 | .intercept = intercept, | |
9dac77fa AK |
418 | .rep_prefix = ctxt->rep_prefix, |
419 | .modrm_mod = ctxt->modrm_mod, | |
420 | .modrm_reg = ctxt->modrm_reg, | |
421 | .modrm_rm = ctxt->modrm_rm, | |
422 | .src_val = ctxt->src.val64, | |
423 | .src_bytes = ctxt->src.bytes, | |
424 | .dst_bytes = ctxt->dst.bytes, | |
425 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
426 | .next_rip = ctxt->eip, |
427 | }; | |
428 | ||
2953538e | 429 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
430 | } |
431 | ||
9dac77fa | 432 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 433 | { |
9dac77fa | 434 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
435 | } |
436 | ||
6aa8b732 | 437 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 438 | static inline unsigned long |
9dac77fa | 439 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 440 | { |
9dac77fa | 441 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
442 | return reg; |
443 | else | |
9dac77fa | 444 | return reg & ad_mask(ctxt); |
e4706772 HH |
445 | } |
446 | ||
447 | static inline unsigned long | |
9dac77fa | 448 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 449 | { |
9dac77fa | 450 | return address_mask(ctxt, reg); |
e4706772 HH |
451 | } |
452 | ||
7a957275 | 453 | static inline void |
9dac77fa | 454 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 455 | { |
9dac77fa | 456 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
7a957275 HH |
457 | *reg += inc; |
458 | else | |
9dac77fa | 459 | *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); |
7a957275 | 460 | } |
6aa8b732 | 461 | |
9dac77fa | 462 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 463 | { |
9dac77fa | 464 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 465 | } |
098c937b | 466 | |
56697687 AK |
467 | static u32 desc_limit_scaled(struct desc_struct *desc) |
468 | { | |
469 | u32 limit = get_desc_limit(desc); | |
470 | ||
471 | return desc->g ? (limit << 12) | 0xfff : limit; | |
472 | } | |
473 | ||
9dac77fa | 474 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 475 | { |
9dac77fa AK |
476 | ctxt->has_seg_override = true; |
477 | ctxt->seg_override = seg; | |
7a5b56df AK |
478 | } |
479 | ||
7b105ca2 | 480 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
481 | { |
482 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
483 | return 0; | |
484 | ||
7b105ca2 | 485 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
486 | } |
487 | ||
9dac77fa | 488 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 489 | { |
9dac77fa | 490 | if (!ctxt->has_seg_override) |
7a5b56df AK |
491 | return 0; |
492 | ||
9dac77fa | 493 | return ctxt->seg_override; |
7a5b56df AK |
494 | } |
495 | ||
35d3d4a1 AK |
496 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
497 | u32 error, bool valid) | |
54b8486f | 498 | { |
da9cb575 AK |
499 | ctxt->exception.vector = vec; |
500 | ctxt->exception.error_code = error; | |
501 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 502 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
503 | } |
504 | ||
3b88e41a JR |
505 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
506 | { | |
507 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
508 | } | |
509 | ||
35d3d4a1 | 510 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 511 | { |
35d3d4a1 | 512 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
513 | } |
514 | ||
618ff15d AK |
515 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
516 | { | |
517 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
518 | } | |
519 | ||
35d3d4a1 | 520 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 521 | { |
35d3d4a1 | 522 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
523 | } |
524 | ||
35d3d4a1 | 525 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 526 | { |
35d3d4a1 | 527 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
528 | } |
529 | ||
34d1f490 AK |
530 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
531 | { | |
35d3d4a1 | 532 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
533 | } |
534 | ||
1253791d AK |
535 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
536 | { | |
537 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
538 | } | |
539 | ||
1aa36616 AK |
540 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
541 | { | |
542 | u16 selector; | |
543 | struct desc_struct desc; | |
544 | ||
545 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
546 | return selector; | |
547 | } | |
548 | ||
549 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
550 | unsigned seg) | |
551 | { | |
552 | u16 dummy; | |
553 | u32 base3; | |
554 | struct desc_struct desc; | |
555 | ||
556 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
557 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
558 | } | |
559 | ||
3d9b938e | 560 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 561 | struct segmented_address addr, |
3d9b938e | 562 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
563 | ulong *linear) |
564 | { | |
618ff15d AK |
565 | struct desc_struct desc; |
566 | bool usable; | |
52fd8b44 | 567 | ulong la; |
618ff15d | 568 | u32 lim; |
1aa36616 | 569 | u16 sel; |
618ff15d | 570 | unsigned cpl, rpl; |
52fd8b44 | 571 | |
7b105ca2 | 572 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d AK |
573 | switch (ctxt->mode) { |
574 | case X86EMUL_MODE_REAL: | |
575 | break; | |
576 | case X86EMUL_MODE_PROT64: | |
577 | if (((signed long)la << 16) >> 16 != la) | |
578 | return emulate_gp(ctxt, 0); | |
579 | break; | |
580 | default: | |
1aa36616 AK |
581 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
582 | addr.seg); | |
618ff15d AK |
583 | if (!usable) |
584 | goto bad; | |
585 | /* code segment or read-only data segment */ | |
586 | if (((desc.type & 8) || !(desc.type & 2)) && write) | |
587 | goto bad; | |
588 | /* unreadable code segment */ | |
3d9b938e | 589 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
590 | goto bad; |
591 | lim = desc_limit_scaled(&desc); | |
592 | if ((desc.type & 8) || !(desc.type & 4)) { | |
593 | /* expand-up segment */ | |
594 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
595 | goto bad; | |
596 | } else { | |
597 | /* exapand-down segment */ | |
598 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) | |
599 | goto bad; | |
600 | lim = desc.d ? 0xffffffff : 0xffff; | |
601 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
602 | goto bad; | |
603 | } | |
717746e3 | 604 | cpl = ctxt->ops->cpl(ctxt); |
1aa36616 | 605 | rpl = sel & 3; |
618ff15d AK |
606 | cpl = max(cpl, rpl); |
607 | if (!(desc.type & 8)) { | |
608 | /* data segment */ | |
609 | if (cpl > desc.dpl) | |
610 | goto bad; | |
611 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
612 | /* nonconforming code segment */ | |
613 | if (cpl != desc.dpl) | |
614 | goto bad; | |
615 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
616 | /* conforming code segment */ | |
617 | if (cpl < desc.dpl) | |
618 | goto bad; | |
619 | } | |
620 | break; | |
621 | } | |
9dac77fa | 622 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 AK |
623 | la &= (u32)-1; |
624 | *linear = la; | |
625 | return X86EMUL_CONTINUE; | |
618ff15d AK |
626 | bad: |
627 | if (addr.seg == VCPU_SREG_SS) | |
628 | return emulate_ss(ctxt, addr.seg); | |
629 | else | |
630 | return emulate_gp(ctxt, addr.seg); | |
52fd8b44 AK |
631 | } |
632 | ||
3d9b938e NE |
633 | static int linearize(struct x86_emulate_ctxt *ctxt, |
634 | struct segmented_address addr, | |
635 | unsigned size, bool write, | |
636 | ulong *linear) | |
637 | { | |
638 | return __linearize(ctxt, addr, size, write, false, linear); | |
639 | } | |
640 | ||
641 | ||
3ca3ac4d AK |
642 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
643 | struct segmented_address addr, | |
644 | void *data, | |
645 | unsigned size) | |
646 | { | |
9fa088f4 AK |
647 | int rc; |
648 | ulong linear; | |
649 | ||
83b8795a | 650 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
651 | if (rc != X86EMUL_CONTINUE) |
652 | return rc; | |
0f65dd70 | 653 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
654 | } |
655 | ||
807941b1 TY |
656 | /* |
657 | * Fetch the next byte of the instruction being emulated which is pointed to | |
658 | * by ctxt->_eip, then increment ctxt->_eip. | |
659 | * | |
660 | * Also prefetch the remaining bytes of the instruction without crossing page | |
661 | * boundary if they are not in fetch_cache yet. | |
662 | */ | |
663 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 664 | { |
9dac77fa | 665 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 666 | int rc; |
2fb53ad8 | 667 | int size, cur_size; |
62266869 | 668 | |
807941b1 | 669 | if (ctxt->_eip == fc->end) { |
3d9b938e | 670 | unsigned long linear; |
807941b1 TY |
671 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
672 | .ea = ctxt->_eip }; | |
2fb53ad8 | 673 | cur_size = fc->end - fc->start; |
807941b1 TY |
674 | size = min(15UL - cur_size, |
675 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 676 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 677 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 678 | return rc; |
ef5d75cc TY |
679 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
680 | size, &ctxt->exception); | |
7d88bb48 | 681 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 682 | return rc; |
2fb53ad8 | 683 | fc->end += size; |
62266869 | 684 | } |
807941b1 TY |
685 | *dest = fc->data[ctxt->_eip - fc->start]; |
686 | ctxt->_eip++; | |
3e2815e9 | 687 | return X86EMUL_CONTINUE; |
62266869 AK |
688 | } |
689 | ||
690 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 691 | void *dest, unsigned size) |
62266869 | 692 | { |
3e2815e9 | 693 | int rc; |
62266869 | 694 | |
eb3c79e6 | 695 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 696 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 697 | return X86EMUL_UNHANDLEABLE; |
62266869 | 698 | while (size--) { |
807941b1 | 699 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 700 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
701 | return rc; |
702 | } | |
3e2815e9 | 703 | return X86EMUL_CONTINUE; |
62266869 AK |
704 | } |
705 | ||
67cbc90d | 706 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 707 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 708 | ({ unsigned long _x; \ |
e85a1085 | 709 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
710 | if (rc != X86EMUL_CONTINUE) \ |
711 | goto done; \ | |
67cbc90d TY |
712 | (_type)_x; \ |
713 | }) | |
714 | ||
807941b1 TY |
715 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
716 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
717 | if (rc != X86EMUL_CONTINUE) \ |
718 | goto done; \ | |
67cbc90d TY |
719 | }) |
720 | ||
1e3c5cb0 RR |
721 | /* |
722 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
723 | * pointer into the block that addresses the relevant register. | |
724 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
725 | */ | |
726 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
727 | int highbyte_regs) | |
6aa8b732 AK |
728 | { |
729 | void *p; | |
730 | ||
731 | p = ®s[modrm_reg]; | |
732 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
733 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
734 | return p; | |
735 | } | |
736 | ||
737 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 738 | struct segmented_address addr, |
6aa8b732 AK |
739 | u16 *size, unsigned long *address, int op_bytes) |
740 | { | |
741 | int rc; | |
742 | ||
743 | if (op_bytes == 2) | |
744 | op_bytes = 3; | |
745 | *address = 0; | |
3ca3ac4d | 746 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 747 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 748 | return rc; |
30b31ab6 | 749 | addr.ea += 2; |
3ca3ac4d | 750 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
751 | return rc; |
752 | } | |
753 | ||
bbe9abbd NK |
754 | static int test_cc(unsigned int condition, unsigned int flags) |
755 | { | |
756 | int rc = 0; | |
757 | ||
758 | switch ((condition & 15) >> 1) { | |
759 | case 0: /* o */ | |
760 | rc |= (flags & EFLG_OF); | |
761 | break; | |
762 | case 1: /* b/c/nae */ | |
763 | rc |= (flags & EFLG_CF); | |
764 | break; | |
765 | case 2: /* z/e */ | |
766 | rc |= (flags & EFLG_ZF); | |
767 | break; | |
768 | case 3: /* be/na */ | |
769 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
770 | break; | |
771 | case 4: /* s */ | |
772 | rc |= (flags & EFLG_SF); | |
773 | break; | |
774 | case 5: /* p/pe */ | |
775 | rc |= (flags & EFLG_PF); | |
776 | break; | |
777 | case 7: /* le/ng */ | |
778 | rc |= (flags & EFLG_ZF); | |
779 | /* fall through */ | |
780 | case 6: /* l/nge */ | |
781 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
782 | break; | |
783 | } | |
784 | ||
785 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
786 | return (!!rc ^ (condition & 1)); | |
787 | } | |
788 | ||
91ff3cb4 AK |
789 | static void fetch_register_operand(struct operand *op) |
790 | { | |
791 | switch (op->bytes) { | |
792 | case 1: | |
793 | op->val = *(u8 *)op->addr.reg; | |
794 | break; | |
795 | case 2: | |
796 | op->val = *(u16 *)op->addr.reg; | |
797 | break; | |
798 | case 4: | |
799 | op->val = *(u32 *)op->addr.reg; | |
800 | break; | |
801 | case 8: | |
802 | op->val = *(u64 *)op->addr.reg; | |
803 | break; | |
804 | } | |
805 | } | |
806 | ||
1253791d AK |
807 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
808 | { | |
809 | ctxt->ops->get_fpu(ctxt); | |
810 | switch (reg) { | |
811 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
812 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
813 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
814 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
815 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
816 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
817 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
818 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
819 | #ifdef CONFIG_X86_64 | |
820 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
821 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
822 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
823 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
824 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
825 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
826 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
827 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
828 | #endif | |
829 | default: BUG(); | |
830 | } | |
831 | ctxt->ops->put_fpu(ctxt); | |
832 | } | |
833 | ||
834 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
835 | int reg) | |
836 | { | |
837 | ctxt->ops->get_fpu(ctxt); | |
838 | switch (reg) { | |
839 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
840 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
841 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
842 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
843 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
844 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
845 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
846 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
847 | #ifdef CONFIG_X86_64 | |
848 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
849 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
850 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
851 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
852 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
853 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
854 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
855 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
856 | #endif | |
857 | default: BUG(); | |
858 | } | |
859 | ctxt->ops->put_fpu(ctxt); | |
860 | } | |
861 | ||
862 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
2adb5ad9 | 863 | struct operand *op) |
3c118e24 | 864 | { |
9dac77fa AK |
865 | unsigned reg = ctxt->modrm_reg; |
866 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 867 | |
9dac77fa AK |
868 | if (!(ctxt->d & ModRM)) |
869 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 870 | |
9dac77fa | 871 | if (ctxt->d & Sse) { |
1253791d AK |
872 | op->type = OP_XMM; |
873 | op->bytes = 16; | |
874 | op->addr.xmm = reg; | |
875 | read_sse_reg(ctxt, &op->vec_val, reg); | |
876 | return; | |
877 | } | |
878 | ||
3c118e24 | 879 | op->type = OP_REG; |
2adb5ad9 | 880 | if (ctxt->d & ByteOp) { |
9dac77fa | 881 | op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs); |
3c118e24 AK |
882 | op->bytes = 1; |
883 | } else { | |
9dac77fa AK |
884 | op->addr.reg = decode_register(reg, ctxt->regs, 0); |
885 | op->bytes = ctxt->op_bytes; | |
3c118e24 | 886 | } |
91ff3cb4 | 887 | fetch_register_operand(op); |
3c118e24 AK |
888 | op->orig_val = op->val; |
889 | } | |
890 | ||
1c73ef66 | 891 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 892 | struct operand *op) |
1c73ef66 | 893 | { |
1c73ef66 | 894 | u8 sib; |
f5b4edcd | 895 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 896 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 897 | ulong modrm_ea = 0; |
1c73ef66 | 898 | |
9dac77fa AK |
899 | if (ctxt->rex_prefix) { |
900 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
901 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
902 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
903 | } |
904 | ||
e85a1085 | 905 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
906 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
907 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
908 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
909 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 910 | |
9dac77fa | 911 | if (ctxt->modrm_mod == 3) { |
2dbd0dd7 | 912 | op->type = OP_REG; |
9dac77fa AK |
913 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
914 | op->addr.reg = decode_register(ctxt->modrm_rm, | |
915 | ctxt->regs, ctxt->d & ByteOp); | |
916 | if (ctxt->d & Sse) { | |
1253791d AK |
917 | op->type = OP_XMM; |
918 | op->bytes = 16; | |
9dac77fa AK |
919 | op->addr.xmm = ctxt->modrm_rm; |
920 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
921 | return rc; |
922 | } | |
2dbd0dd7 | 923 | fetch_register_operand(op); |
1c73ef66 AK |
924 | return rc; |
925 | } | |
926 | ||
2dbd0dd7 AK |
927 | op->type = OP_MEM; |
928 | ||
9dac77fa AK |
929 | if (ctxt->ad_bytes == 2) { |
930 | unsigned bx = ctxt->regs[VCPU_REGS_RBX]; | |
931 | unsigned bp = ctxt->regs[VCPU_REGS_RBP]; | |
932 | unsigned si = ctxt->regs[VCPU_REGS_RSI]; | |
933 | unsigned di = ctxt->regs[VCPU_REGS_RDI]; | |
1c73ef66 AK |
934 | |
935 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 936 | switch (ctxt->modrm_mod) { |
1c73ef66 | 937 | case 0: |
9dac77fa | 938 | if (ctxt->modrm_rm == 6) |
e85a1085 | 939 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
940 | break; |
941 | case 1: | |
e85a1085 | 942 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
943 | break; |
944 | case 2: | |
e85a1085 | 945 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
946 | break; |
947 | } | |
9dac77fa | 948 | switch (ctxt->modrm_rm) { |
1c73ef66 | 949 | case 0: |
2dbd0dd7 | 950 | modrm_ea += bx + si; |
1c73ef66 AK |
951 | break; |
952 | case 1: | |
2dbd0dd7 | 953 | modrm_ea += bx + di; |
1c73ef66 AK |
954 | break; |
955 | case 2: | |
2dbd0dd7 | 956 | modrm_ea += bp + si; |
1c73ef66 AK |
957 | break; |
958 | case 3: | |
2dbd0dd7 | 959 | modrm_ea += bp + di; |
1c73ef66 AK |
960 | break; |
961 | case 4: | |
2dbd0dd7 | 962 | modrm_ea += si; |
1c73ef66 AK |
963 | break; |
964 | case 5: | |
2dbd0dd7 | 965 | modrm_ea += di; |
1c73ef66 AK |
966 | break; |
967 | case 6: | |
9dac77fa | 968 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 969 | modrm_ea += bp; |
1c73ef66 AK |
970 | break; |
971 | case 7: | |
2dbd0dd7 | 972 | modrm_ea += bx; |
1c73ef66 AK |
973 | break; |
974 | } | |
9dac77fa AK |
975 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
976 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
977 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 978 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
979 | } else { |
980 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 981 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 982 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
983 | index_reg |= (sib >> 3) & 7; |
984 | base_reg |= sib & 7; | |
985 | scale = sib >> 6; | |
986 | ||
9dac77fa | 987 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 988 | modrm_ea += insn_fetch(s32, ctxt); |
dc71d0f1 | 989 | else |
9dac77fa | 990 | modrm_ea += ctxt->regs[base_reg]; |
dc71d0f1 | 991 | if (index_reg != 4) |
9dac77fa AK |
992 | modrm_ea += ctxt->regs[index_reg] << scale; |
993 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { | |
84411d85 | 994 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 995 | ctxt->rip_relative = 1; |
84411d85 | 996 | } else |
9dac77fa AK |
997 | modrm_ea += ctxt->regs[ctxt->modrm_rm]; |
998 | switch (ctxt->modrm_mod) { | |
1c73ef66 | 999 | case 0: |
9dac77fa | 1000 | if (ctxt->modrm_rm == 5) |
e85a1085 | 1001 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1002 | break; |
1003 | case 1: | |
e85a1085 | 1004 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1005 | break; |
1006 | case 2: | |
e85a1085 | 1007 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1008 | break; |
1009 | } | |
1010 | } | |
90de84f5 | 1011 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
1012 | done: |
1013 | return rc; | |
1014 | } | |
1015 | ||
1016 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1017 | struct operand *op) |
1c73ef66 | 1018 | { |
3e2815e9 | 1019 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1020 | |
2dbd0dd7 | 1021 | op->type = OP_MEM; |
9dac77fa | 1022 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1023 | case 2: |
e85a1085 | 1024 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1025 | break; |
1026 | case 4: | |
e85a1085 | 1027 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1028 | break; |
1029 | case 8: | |
e85a1085 | 1030 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1031 | break; |
1032 | } | |
1033 | done: | |
1034 | return rc; | |
1035 | } | |
1036 | ||
9dac77fa | 1037 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1038 | { |
7129eeca | 1039 | long sv = 0, mask; |
35c843c4 | 1040 | |
9dac77fa AK |
1041 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1042 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1043 | |
9dac77fa AK |
1044 | if (ctxt->src.bytes == 2) |
1045 | sv = (s16)ctxt->src.val & (s16)mask; | |
1046 | else if (ctxt->src.bytes == 4) | |
1047 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1048 | |
9dac77fa | 1049 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1050 | } |
ba7ff2b7 WY |
1051 | |
1052 | /* only subword offset */ | |
9dac77fa | 1053 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1054 | } |
1055 | ||
dde7e6d1 | 1056 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1057 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1058 | { |
dde7e6d1 | 1059 | int rc; |
9dac77fa | 1060 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1061 | |
dde7e6d1 AK |
1062 | while (size) { |
1063 | int n = min(size, 8u); | |
1064 | size -= n; | |
1065 | if (mc->pos < mc->end) | |
1066 | goto read_cached; | |
5cd21917 | 1067 | |
7b105ca2 TY |
1068 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n, |
1069 | &ctxt->exception); | |
dde7e6d1 AK |
1070 | if (rc != X86EMUL_CONTINUE) |
1071 | return rc; | |
1072 | mc->end += n; | |
6aa8b732 | 1073 | |
dde7e6d1 AK |
1074 | read_cached: |
1075 | memcpy(dest, mc->data + mc->pos, n); | |
1076 | mc->pos += n; | |
1077 | dest += n; | |
1078 | addr += n; | |
6aa8b732 | 1079 | } |
dde7e6d1 AK |
1080 | return X86EMUL_CONTINUE; |
1081 | } | |
6aa8b732 | 1082 | |
3ca3ac4d AK |
1083 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1084 | struct segmented_address addr, | |
1085 | void *data, | |
1086 | unsigned size) | |
1087 | { | |
9fa088f4 AK |
1088 | int rc; |
1089 | ulong linear; | |
1090 | ||
83b8795a | 1091 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1092 | if (rc != X86EMUL_CONTINUE) |
1093 | return rc; | |
7b105ca2 | 1094 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1095 | } |
1096 | ||
1097 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1098 | struct segmented_address addr, | |
1099 | const void *data, | |
1100 | unsigned size) | |
1101 | { | |
9fa088f4 AK |
1102 | int rc; |
1103 | ulong linear; | |
1104 | ||
83b8795a | 1105 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1106 | if (rc != X86EMUL_CONTINUE) |
1107 | return rc; | |
0f65dd70 AK |
1108 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1109 | &ctxt->exception); | |
3ca3ac4d AK |
1110 | } |
1111 | ||
1112 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1113 | struct segmented_address addr, | |
1114 | const void *orig_data, const void *data, | |
1115 | unsigned size) | |
1116 | { | |
9fa088f4 AK |
1117 | int rc; |
1118 | ulong linear; | |
1119 | ||
83b8795a | 1120 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1121 | if (rc != X86EMUL_CONTINUE) |
1122 | return rc; | |
0f65dd70 AK |
1123 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1124 | size, &ctxt->exception); | |
3ca3ac4d AK |
1125 | } |
1126 | ||
dde7e6d1 | 1127 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1128 | unsigned int size, unsigned short port, |
1129 | void *dest) | |
1130 | { | |
9dac77fa | 1131 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1132 | |
dde7e6d1 | 1133 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1134 | unsigned int in_page, n; |
9dac77fa AK |
1135 | unsigned int count = ctxt->rep_prefix ? |
1136 | address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1; | |
dde7e6d1 | 1137 | in_page = (ctxt->eflags & EFLG_DF) ? |
9dac77fa AK |
1138 | offset_in_page(ctxt->regs[VCPU_REGS_RDI]) : |
1139 | PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]); | |
dde7e6d1 AK |
1140 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1141 | count); | |
1142 | if (n == 0) | |
1143 | n = 1; | |
1144 | rc->pos = rc->end = 0; | |
7b105ca2 | 1145 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1146 | return 0; |
1147 | rc->end = n * size; | |
6aa8b732 AK |
1148 | } |
1149 | ||
dde7e6d1 AK |
1150 | memcpy(dest, rc->data + rc->pos, size); |
1151 | rc->pos += size; | |
1152 | return 1; | |
1153 | } | |
6aa8b732 | 1154 | |
dde7e6d1 | 1155 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1156 | u16 selector, struct desc_ptr *dt) |
1157 | { | |
7b105ca2 TY |
1158 | struct x86_emulate_ops *ops = ctxt->ops; |
1159 | ||
dde7e6d1 AK |
1160 | if (selector & 1 << 2) { |
1161 | struct desc_struct desc; | |
1aa36616 AK |
1162 | u16 sel; |
1163 | ||
dde7e6d1 | 1164 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1165 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1166 | return; |
e09d082c | 1167 | |
dde7e6d1 AK |
1168 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1169 | dt->address = get_desc_base(&desc); | |
1170 | } else | |
4bff1e86 | 1171 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1172 | } |
120df890 | 1173 | |
dde7e6d1 AK |
1174 | /* allowed just for 8 bytes segments */ |
1175 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1176 | u16 selector, struct desc_struct *desc) |
1177 | { | |
1178 | struct desc_ptr dt; | |
1179 | u16 index = selector >> 3; | |
dde7e6d1 | 1180 | ulong addr; |
120df890 | 1181 | |
7b105ca2 | 1182 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1183 | |
35d3d4a1 AK |
1184 | if (dt.size < index * 8 + 7) |
1185 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1186 | |
7b105ca2 TY |
1187 | addr = dt.address + index * 8; |
1188 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1189 | &ctxt->exception); | |
dde7e6d1 | 1190 | } |
ef65c889 | 1191 | |
dde7e6d1 AK |
1192 | /* allowed just for 8 bytes segments */ |
1193 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1194 | u16 selector, struct desc_struct *desc) |
1195 | { | |
1196 | struct desc_ptr dt; | |
1197 | u16 index = selector >> 3; | |
dde7e6d1 | 1198 | ulong addr; |
6aa8b732 | 1199 | |
7b105ca2 | 1200 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1201 | |
35d3d4a1 AK |
1202 | if (dt.size < index * 8 + 7) |
1203 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1204 | |
dde7e6d1 | 1205 | addr = dt.address + index * 8; |
7b105ca2 TY |
1206 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1207 | &ctxt->exception); | |
dde7e6d1 | 1208 | } |
c7e75a3d | 1209 | |
5601d05b | 1210 | /* Does not support long mode */ |
dde7e6d1 | 1211 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1212 | u16 selector, int seg) |
1213 | { | |
1214 | struct desc_struct seg_desc; | |
1215 | u8 dpl, rpl, cpl; | |
1216 | unsigned err_vec = GP_VECTOR; | |
1217 | u32 err_code = 0; | |
1218 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1219 | int ret; | |
69f55cb1 | 1220 | |
dde7e6d1 | 1221 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1222 | |
dde7e6d1 AK |
1223 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1224 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1225 | /* set real mode segment descriptor */ | |
1226 | set_desc_base(&seg_desc, selector << 4); | |
1227 | set_desc_limit(&seg_desc, 0xffff); | |
1228 | seg_desc.type = 3; | |
1229 | seg_desc.p = 1; | |
1230 | seg_desc.s = 1; | |
1231 | goto load; | |
1232 | } | |
1233 | ||
1234 | /* NULL selector is not valid for TR, CS and SS */ | |
1235 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1236 | && null_selector) | |
1237 | goto exception; | |
1238 | ||
1239 | /* TR should be in GDT only */ | |
1240 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1241 | goto exception; | |
1242 | ||
1243 | if (null_selector) /* for NULL selector skip all following checks */ | |
1244 | goto load; | |
1245 | ||
7b105ca2 | 1246 | ret = read_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1247 | if (ret != X86EMUL_CONTINUE) |
1248 | return ret; | |
1249 | ||
1250 | err_code = selector & 0xfffc; | |
1251 | err_vec = GP_VECTOR; | |
1252 | ||
1253 | /* can't load system descriptor into segment selecor */ | |
1254 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1255 | goto exception; | |
1256 | ||
1257 | if (!seg_desc.p) { | |
1258 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1259 | goto exception; | |
1260 | } | |
1261 | ||
1262 | rpl = selector & 3; | |
1263 | dpl = seg_desc.dpl; | |
7b105ca2 | 1264 | cpl = ctxt->ops->cpl(ctxt); |
dde7e6d1 AK |
1265 | |
1266 | switch (seg) { | |
1267 | case VCPU_SREG_SS: | |
1268 | /* | |
1269 | * segment is not a writable data segment or segment | |
1270 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1271 | */ | |
1272 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1273 | goto exception; | |
6aa8b732 | 1274 | break; |
dde7e6d1 AK |
1275 | case VCPU_SREG_CS: |
1276 | if (!(seg_desc.type & 8)) | |
1277 | goto exception; | |
1278 | ||
1279 | if (seg_desc.type & 4) { | |
1280 | /* conforming */ | |
1281 | if (dpl > cpl) | |
1282 | goto exception; | |
1283 | } else { | |
1284 | /* nonconforming */ | |
1285 | if (rpl > cpl || dpl != cpl) | |
1286 | goto exception; | |
1287 | } | |
1288 | /* CS(RPL) <- CPL */ | |
1289 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1290 | break; |
dde7e6d1 AK |
1291 | case VCPU_SREG_TR: |
1292 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1293 | goto exception; | |
1294 | break; | |
1295 | case VCPU_SREG_LDTR: | |
1296 | if (seg_desc.s || seg_desc.type != 2) | |
1297 | goto exception; | |
1298 | break; | |
1299 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1300 | /* |
dde7e6d1 AK |
1301 | * segment is not a data or readable code segment or |
1302 | * ((segment is a data or nonconforming code segment) | |
1303 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1304 | */ |
dde7e6d1 AK |
1305 | if ((seg_desc.type & 0xa) == 0x8 || |
1306 | (((seg_desc.type & 0xc) != 0xc) && | |
1307 | (rpl > dpl && cpl > dpl))) | |
1308 | goto exception; | |
6aa8b732 | 1309 | break; |
dde7e6d1 AK |
1310 | } |
1311 | ||
1312 | if (seg_desc.s) { | |
1313 | /* mark segment as accessed */ | |
1314 | seg_desc.type |= 1; | |
7b105ca2 | 1315 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1316 | if (ret != X86EMUL_CONTINUE) |
1317 | return ret; | |
1318 | } | |
1319 | load: | |
7b105ca2 | 1320 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1321 | return X86EMUL_CONTINUE; |
1322 | exception: | |
1323 | emulate_exception(ctxt, err_vec, err_code, true); | |
1324 | return X86EMUL_PROPAGATE_FAULT; | |
1325 | } | |
1326 | ||
31be40b3 WY |
1327 | static void write_register_operand(struct operand *op) |
1328 | { | |
1329 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1330 | switch (op->bytes) { | |
1331 | case 1: | |
1332 | *(u8 *)op->addr.reg = (u8)op->val; | |
1333 | break; | |
1334 | case 2: | |
1335 | *(u16 *)op->addr.reg = (u16)op->val; | |
1336 | break; | |
1337 | case 4: | |
1338 | *op->addr.reg = (u32)op->val; | |
1339 | break; /* 64b: zero-extend */ | |
1340 | case 8: | |
1341 | *op->addr.reg = op->val; | |
1342 | break; | |
1343 | } | |
1344 | } | |
1345 | ||
adddcecf | 1346 | static int writeback(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 AK |
1347 | { |
1348 | int rc; | |
dde7e6d1 | 1349 | |
9dac77fa | 1350 | switch (ctxt->dst.type) { |
dde7e6d1 | 1351 | case OP_REG: |
9dac77fa | 1352 | write_register_operand(&ctxt->dst); |
6aa8b732 | 1353 | break; |
dde7e6d1 | 1354 | case OP_MEM: |
9dac77fa | 1355 | if (ctxt->lock_prefix) |
3ca3ac4d | 1356 | rc = segmented_cmpxchg(ctxt, |
9dac77fa AK |
1357 | ctxt->dst.addr.mem, |
1358 | &ctxt->dst.orig_val, | |
1359 | &ctxt->dst.val, | |
1360 | ctxt->dst.bytes); | |
341de7e3 | 1361 | else |
3ca3ac4d | 1362 | rc = segmented_write(ctxt, |
9dac77fa AK |
1363 | ctxt->dst.addr.mem, |
1364 | &ctxt->dst.val, | |
1365 | ctxt->dst.bytes); | |
dde7e6d1 AK |
1366 | if (rc != X86EMUL_CONTINUE) |
1367 | return rc; | |
a682e354 | 1368 | break; |
1253791d | 1369 | case OP_XMM: |
9dac77fa | 1370 | write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); |
1253791d | 1371 | break; |
dde7e6d1 AK |
1372 | case OP_NONE: |
1373 | /* no writeback */ | |
414e6277 | 1374 | break; |
dde7e6d1 | 1375 | default: |
414e6277 | 1376 | break; |
6aa8b732 | 1377 | } |
dde7e6d1 AK |
1378 | return X86EMUL_CONTINUE; |
1379 | } | |
6aa8b732 | 1380 | |
4487b3b4 | 1381 | static int em_push(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 | 1382 | { |
4179bb02 | 1383 | struct segmented_address addr; |
0dc8d10f | 1384 | |
9dac77fa AK |
1385 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes); |
1386 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); | |
4179bb02 TY |
1387 | addr.seg = VCPU_SREG_SS; |
1388 | ||
1389 | /* Disable writeback. */ | |
9dac77fa AK |
1390 | ctxt->dst.type = OP_NONE; |
1391 | return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes); | |
dde7e6d1 | 1392 | } |
69f55cb1 | 1393 | |
dde7e6d1 | 1394 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1395 | void *dest, int len) |
1396 | { | |
dde7e6d1 | 1397 | int rc; |
90de84f5 | 1398 | struct segmented_address addr; |
8b4caf66 | 1399 | |
9dac77fa | 1400 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); |
90de84f5 | 1401 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1402 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1403 | if (rc != X86EMUL_CONTINUE) |
1404 | return rc; | |
1405 | ||
9dac77fa | 1406 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); |
dde7e6d1 | 1407 | return rc; |
8b4caf66 LV |
1408 | } |
1409 | ||
c54fe504 TY |
1410 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1411 | { | |
9dac77fa | 1412 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1413 | } |
1414 | ||
dde7e6d1 | 1415 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1416 | void *dest, int len) |
9de41573 GN |
1417 | { |
1418 | int rc; | |
dde7e6d1 AK |
1419 | unsigned long val, change_mask; |
1420 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1421 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1422 | |
3b9be3bf | 1423 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1424 | if (rc != X86EMUL_CONTINUE) |
1425 | return rc; | |
9de41573 | 1426 | |
dde7e6d1 AK |
1427 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1428 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1429 | |
dde7e6d1 AK |
1430 | switch(ctxt->mode) { |
1431 | case X86EMUL_MODE_PROT64: | |
1432 | case X86EMUL_MODE_PROT32: | |
1433 | case X86EMUL_MODE_PROT16: | |
1434 | if (cpl == 0) | |
1435 | change_mask |= EFLG_IOPL; | |
1436 | if (cpl <= iopl) | |
1437 | change_mask |= EFLG_IF; | |
1438 | break; | |
1439 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1440 | if (iopl < 3) |
1441 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1442 | change_mask |= EFLG_IF; |
1443 | break; | |
1444 | default: /* real mode */ | |
1445 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1446 | break; | |
9de41573 | 1447 | } |
dde7e6d1 AK |
1448 | |
1449 | *(unsigned long *)dest = | |
1450 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1451 | ||
1452 | return rc; | |
9de41573 GN |
1453 | } |
1454 | ||
62aaa2f0 TY |
1455 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1456 | { | |
9dac77fa AK |
1457 | ctxt->dst.type = OP_REG; |
1458 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1459 | ctxt->dst.bytes = ctxt->op_bytes; | |
1460 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1461 | } |
1462 | ||
1cd196ea | 1463 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1464 | { |
1cd196ea AK |
1465 | int seg = ctxt->src2.val; |
1466 | ||
9dac77fa | 1467 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1468 | |
4487b3b4 | 1469 | return em_push(ctxt); |
7b262e90 GN |
1470 | } |
1471 | ||
1cd196ea | 1472 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1473 | { |
1cd196ea | 1474 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1475 | unsigned long selector; |
1476 | int rc; | |
38ba30ba | 1477 | |
9dac77fa | 1478 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1479 | if (rc != X86EMUL_CONTINUE) |
1480 | return rc; | |
1481 | ||
7b105ca2 | 1482 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1483 | return rc; |
38ba30ba GN |
1484 | } |
1485 | ||
b96a7fad | 1486 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1487 | { |
9dac77fa | 1488 | unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP]; |
dde7e6d1 AK |
1489 | int rc = X86EMUL_CONTINUE; |
1490 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1491 | |
dde7e6d1 AK |
1492 | while (reg <= VCPU_REGS_RDI) { |
1493 | (reg == VCPU_REGS_RSP) ? | |
9dac77fa | 1494 | (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]); |
38ba30ba | 1495 | |
4487b3b4 | 1496 | rc = em_push(ctxt); |
dde7e6d1 AK |
1497 | if (rc != X86EMUL_CONTINUE) |
1498 | return rc; | |
38ba30ba | 1499 | |
dde7e6d1 | 1500 | ++reg; |
38ba30ba | 1501 | } |
38ba30ba | 1502 | |
dde7e6d1 | 1503 | return rc; |
38ba30ba GN |
1504 | } |
1505 | ||
62aaa2f0 TY |
1506 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1507 | { | |
9dac77fa | 1508 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1509 | return em_push(ctxt); |
1510 | } | |
1511 | ||
b96a7fad | 1512 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1513 | { |
dde7e6d1 AK |
1514 | int rc = X86EMUL_CONTINUE; |
1515 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1516 | |
dde7e6d1 AK |
1517 | while (reg >= VCPU_REGS_RAX) { |
1518 | if (reg == VCPU_REGS_RSP) { | |
9dac77fa AK |
1519 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], |
1520 | ctxt->op_bytes); | |
dde7e6d1 AK |
1521 | --reg; |
1522 | } | |
38ba30ba | 1523 | |
9dac77fa | 1524 | rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes); |
dde7e6d1 AK |
1525 | if (rc != X86EMUL_CONTINUE) |
1526 | break; | |
1527 | --reg; | |
38ba30ba | 1528 | } |
dde7e6d1 | 1529 | return rc; |
38ba30ba GN |
1530 | } |
1531 | ||
7b105ca2 | 1532 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1533 | { |
7b105ca2 | 1534 | struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1535 | int rc; |
6e154e56 MG |
1536 | struct desc_ptr dt; |
1537 | gva_t cs_addr; | |
1538 | gva_t eip_addr; | |
1539 | u16 cs, eip; | |
6e154e56 MG |
1540 | |
1541 | /* TODO: Add limit checks */ | |
9dac77fa | 1542 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1543 | rc = em_push(ctxt); |
5c56e1cf AK |
1544 | if (rc != X86EMUL_CONTINUE) |
1545 | return rc; | |
6e154e56 MG |
1546 | |
1547 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1548 | ||
9dac77fa | 1549 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1550 | rc = em_push(ctxt); |
5c56e1cf AK |
1551 | if (rc != X86EMUL_CONTINUE) |
1552 | return rc; | |
6e154e56 | 1553 | |
9dac77fa | 1554 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1555 | rc = em_push(ctxt); |
5c56e1cf AK |
1556 | if (rc != X86EMUL_CONTINUE) |
1557 | return rc; | |
1558 | ||
4bff1e86 | 1559 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1560 | |
1561 | eip_addr = dt.address + (irq << 2); | |
1562 | cs_addr = dt.address + (irq << 2) + 2; | |
1563 | ||
0f65dd70 | 1564 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1565 | if (rc != X86EMUL_CONTINUE) |
1566 | return rc; | |
1567 | ||
0f65dd70 | 1568 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1569 | if (rc != X86EMUL_CONTINUE) |
1570 | return rc; | |
1571 | ||
7b105ca2 | 1572 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1573 | if (rc != X86EMUL_CONTINUE) |
1574 | return rc; | |
1575 | ||
9dac77fa | 1576 | ctxt->_eip = eip; |
6e154e56 MG |
1577 | |
1578 | return rc; | |
1579 | } | |
1580 | ||
7b105ca2 | 1581 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
1582 | { |
1583 | switch(ctxt->mode) { | |
1584 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1585 | return emulate_int_real(ctxt, irq); |
6e154e56 MG |
1586 | case X86EMUL_MODE_VM86: |
1587 | case X86EMUL_MODE_PROT16: | |
1588 | case X86EMUL_MODE_PROT32: | |
1589 | case X86EMUL_MODE_PROT64: | |
1590 | default: | |
1591 | /* Protected mode interrupts unimplemented yet */ | |
1592 | return X86EMUL_UNHANDLEABLE; | |
1593 | } | |
1594 | } | |
1595 | ||
7b105ca2 | 1596 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1597 | { |
dde7e6d1 AK |
1598 | int rc = X86EMUL_CONTINUE; |
1599 | unsigned long temp_eip = 0; | |
1600 | unsigned long temp_eflags = 0; | |
1601 | unsigned long cs = 0; | |
1602 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1603 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1604 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1605 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1606 | |
dde7e6d1 | 1607 | /* TODO: Add stack limit check */ |
38ba30ba | 1608 | |
9dac77fa | 1609 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 1610 | |
dde7e6d1 AK |
1611 | if (rc != X86EMUL_CONTINUE) |
1612 | return rc; | |
38ba30ba | 1613 | |
35d3d4a1 AK |
1614 | if (temp_eip & ~0xffff) |
1615 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1616 | |
9dac77fa | 1617 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 1618 | |
dde7e6d1 AK |
1619 | if (rc != X86EMUL_CONTINUE) |
1620 | return rc; | |
38ba30ba | 1621 | |
9dac77fa | 1622 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 1623 | |
dde7e6d1 AK |
1624 | if (rc != X86EMUL_CONTINUE) |
1625 | return rc; | |
38ba30ba | 1626 | |
7b105ca2 | 1627 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1628 | |
dde7e6d1 AK |
1629 | if (rc != X86EMUL_CONTINUE) |
1630 | return rc; | |
38ba30ba | 1631 | |
9dac77fa | 1632 | ctxt->_eip = temp_eip; |
38ba30ba | 1633 | |
38ba30ba | 1634 | |
9dac77fa | 1635 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 1636 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 1637 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
1638 | ctxt->eflags &= ~0xffff; |
1639 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1640 | } |
dde7e6d1 AK |
1641 | |
1642 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1643 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1644 | ||
1645 | return rc; | |
38ba30ba GN |
1646 | } |
1647 | ||
e01991e7 | 1648 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 1649 | { |
dde7e6d1 AK |
1650 | switch(ctxt->mode) { |
1651 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1652 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
1653 | case X86EMUL_MODE_VM86: |
1654 | case X86EMUL_MODE_PROT16: | |
1655 | case X86EMUL_MODE_PROT32: | |
1656 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1657 | default: |
dde7e6d1 AK |
1658 | /* iret from protected mode unimplemented yet */ |
1659 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1660 | } |
c37eda13 WY |
1661 | } |
1662 | ||
d2f62766 TY |
1663 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
1664 | { | |
d2f62766 TY |
1665 | int rc; |
1666 | unsigned short sel; | |
1667 | ||
9dac77fa | 1668 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 1669 | |
7b105ca2 | 1670 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
1671 | if (rc != X86EMUL_CONTINUE) |
1672 | return rc; | |
1673 | ||
9dac77fa AK |
1674 | ctxt->_eip = 0; |
1675 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
1676 | return X86EMUL_CONTINUE; |
1677 | } | |
1678 | ||
51187683 | 1679 | static int em_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1680 | { |
9dac77fa | 1681 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1682 | case 0: /* rol */ |
a31b9cea | 1683 | emulate_2op_SrcB(ctxt, "rol"); |
8cdbd2c9 LV |
1684 | break; |
1685 | case 1: /* ror */ | |
a31b9cea | 1686 | emulate_2op_SrcB(ctxt, "ror"); |
8cdbd2c9 LV |
1687 | break; |
1688 | case 2: /* rcl */ | |
a31b9cea | 1689 | emulate_2op_SrcB(ctxt, "rcl"); |
8cdbd2c9 LV |
1690 | break; |
1691 | case 3: /* rcr */ | |
a31b9cea | 1692 | emulate_2op_SrcB(ctxt, "rcr"); |
8cdbd2c9 LV |
1693 | break; |
1694 | case 4: /* sal/shl */ | |
1695 | case 6: /* sal/shl */ | |
a31b9cea | 1696 | emulate_2op_SrcB(ctxt, "sal"); |
8cdbd2c9 LV |
1697 | break; |
1698 | case 5: /* shr */ | |
a31b9cea | 1699 | emulate_2op_SrcB(ctxt, "shr"); |
8cdbd2c9 LV |
1700 | break; |
1701 | case 7: /* sar */ | |
a31b9cea | 1702 | emulate_2op_SrcB(ctxt, "sar"); |
8cdbd2c9 LV |
1703 | break; |
1704 | } | |
51187683 | 1705 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1706 | } |
1707 | ||
3329ece1 AK |
1708 | static int em_not(struct x86_emulate_ctxt *ctxt) |
1709 | { | |
1710 | ctxt->dst.val = ~ctxt->dst.val; | |
1711 | return X86EMUL_CONTINUE; | |
1712 | } | |
1713 | ||
1714 | static int em_neg(struct x86_emulate_ctxt *ctxt) | |
1715 | { | |
1716 | emulate_1op(ctxt, "neg"); | |
1717 | return X86EMUL_CONTINUE; | |
1718 | } | |
1719 | ||
1720 | static int em_mul_ex(struct x86_emulate_ctxt *ctxt) | |
1721 | { | |
1722 | u8 ex = 0; | |
1723 | ||
1724 | emulate_1op_rax_rdx(ctxt, "mul", ex); | |
1725 | return X86EMUL_CONTINUE; | |
1726 | } | |
1727 | ||
1728 | static int em_imul_ex(struct x86_emulate_ctxt *ctxt) | |
1729 | { | |
1730 | u8 ex = 0; | |
1731 | ||
1732 | emulate_1op_rax_rdx(ctxt, "imul", ex); | |
1733 | return X86EMUL_CONTINUE; | |
1734 | } | |
1735 | ||
1736 | static int em_div_ex(struct x86_emulate_ctxt *ctxt) | |
8cdbd2c9 | 1737 | { |
34d1f490 | 1738 | u8 de = 0; |
8cdbd2c9 | 1739 | |
3329ece1 AK |
1740 | emulate_1op_rax_rdx(ctxt, "div", de); |
1741 | if (de) | |
1742 | return emulate_de(ctxt); | |
1743 | return X86EMUL_CONTINUE; | |
1744 | } | |
1745 | ||
1746 | static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) | |
1747 | { | |
1748 | u8 de = 0; | |
1749 | ||
1750 | emulate_1op_rax_rdx(ctxt, "idiv", de); | |
34d1f490 AK |
1751 | if (de) |
1752 | return emulate_de(ctxt); | |
8c5eee30 | 1753 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1754 | } |
1755 | ||
51187683 | 1756 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1757 | { |
4179bb02 | 1758 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 1759 | |
9dac77fa | 1760 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1761 | case 0: /* inc */ |
d1eef45d | 1762 | emulate_1op(ctxt, "inc"); |
8cdbd2c9 LV |
1763 | break; |
1764 | case 1: /* dec */ | |
d1eef45d | 1765 | emulate_1op(ctxt, "dec"); |
8cdbd2c9 | 1766 | break; |
d19292e4 MG |
1767 | case 2: /* call near abs */ { |
1768 | long int old_eip; | |
9dac77fa AK |
1769 | old_eip = ctxt->_eip; |
1770 | ctxt->_eip = ctxt->src.val; | |
1771 | ctxt->src.val = old_eip; | |
4487b3b4 | 1772 | rc = em_push(ctxt); |
d19292e4 MG |
1773 | break; |
1774 | } | |
8cdbd2c9 | 1775 | case 4: /* jmp abs */ |
9dac77fa | 1776 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 1777 | break; |
d2f62766 TY |
1778 | case 5: /* jmp far */ |
1779 | rc = em_jmp_far(ctxt); | |
1780 | break; | |
8cdbd2c9 | 1781 | case 6: /* push */ |
4487b3b4 | 1782 | rc = em_push(ctxt); |
8cdbd2c9 | 1783 | break; |
8cdbd2c9 | 1784 | } |
4179bb02 | 1785 | return rc; |
8cdbd2c9 LV |
1786 | } |
1787 | ||
e0dac408 | 1788 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1789 | { |
9dac77fa | 1790 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 1791 | |
9dac77fa AK |
1792 | if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) || |
1793 | ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) { | |
1794 | ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1795 | ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1796 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1797 | } else { |
9dac77fa AK |
1798 | ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) | |
1799 | (u32) ctxt->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1800 | |
05f086f8 | 1801 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1802 | } |
1b30eaa8 | 1803 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1804 | } |
1805 | ||
ebda02c2 TY |
1806 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
1807 | { | |
9dac77fa AK |
1808 | ctxt->dst.type = OP_REG; |
1809 | ctxt->dst.addr.reg = &ctxt->_eip; | |
1810 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
1811 | return em_pop(ctxt); |
1812 | } | |
1813 | ||
e01991e7 | 1814 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 1815 | { |
a77ab5ea AK |
1816 | int rc; |
1817 | unsigned long cs; | |
1818 | ||
9dac77fa | 1819 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 1820 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1821 | return rc; |
9dac77fa AK |
1822 | if (ctxt->op_bytes == 4) |
1823 | ctxt->_eip = (u32)ctxt->_eip; | |
1824 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 1825 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1826 | return rc; |
7b105ca2 | 1827 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1828 | return rc; |
1829 | } | |
1830 | ||
e940b5c2 TY |
1831 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
1832 | { | |
1833 | /* Save real source value, then compare EAX against destination. */ | |
1834 | ctxt->src.orig_val = ctxt->src.val; | |
1835 | ctxt->src.val = ctxt->regs[VCPU_REGS_RAX]; | |
1836 | emulate_2op_SrcV(ctxt, "cmp"); | |
1837 | ||
1838 | if (ctxt->eflags & EFLG_ZF) { | |
1839 | /* Success: write back to memory. */ | |
1840 | ctxt->dst.val = ctxt->src.orig_val; | |
1841 | } else { | |
1842 | /* Failure: write the value we saw to EAX. */ | |
1843 | ctxt->dst.type = OP_REG; | |
1844 | ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX]; | |
1845 | } | |
1846 | return X86EMUL_CONTINUE; | |
1847 | } | |
1848 | ||
d4b4325f | 1849 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 1850 | { |
d4b4325f | 1851 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
1852 | unsigned short sel; |
1853 | int rc; | |
1854 | ||
9dac77fa | 1855 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 1856 | |
7b105ca2 | 1857 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
1858 | if (rc != X86EMUL_CONTINUE) |
1859 | return rc; | |
1860 | ||
9dac77fa | 1861 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
1862 | return rc; |
1863 | } | |
1864 | ||
7b105ca2 | 1865 | static void |
e66bb2cc | 1866 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1867 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 1868 | { |
1aa36616 AK |
1869 | u16 selector; |
1870 | ||
79168fd1 | 1871 | memset(cs, 0, sizeof(struct desc_struct)); |
7b105ca2 | 1872 | ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS); |
79168fd1 | 1873 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1874 | |
1875 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1876 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1877 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1878 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1879 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1880 | cs->s = 1; | |
1881 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1882 | cs->p = 1; |
1883 | cs->d = 1; | |
e66bb2cc | 1884 | |
79168fd1 GN |
1885 | set_desc_base(ss, 0); /* flat segment */ |
1886 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1887 | ss->g = 1; /* 4kb granularity */ |
1888 | ss->s = 1; | |
1889 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1890 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1891 | ss->dpl = 0; |
79168fd1 | 1892 | ss->p = 1; |
e66bb2cc AP |
1893 | } |
1894 | ||
1a18a69b AK |
1895 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
1896 | { | |
1897 | u32 eax, ebx, ecx, edx; | |
1898 | ||
1899 | eax = ecx = 0; | |
1900 | return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx) | |
1901 | && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1902 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx | |
1903 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
1904 | } | |
1905 | ||
c2226fc9 SB |
1906 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
1907 | { | |
1908 | struct x86_emulate_ops *ops = ctxt->ops; | |
1909 | u32 eax, ebx, ecx, edx; | |
1910 | ||
1911 | /* | |
1912 | * syscall should always be enabled in longmode - so only become | |
1913 | * vendor specific (cpuid) if other modes are active... | |
1914 | */ | |
1915 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
1916 | return true; | |
1917 | ||
1918 | eax = 0x00000000; | |
1919 | ecx = 0x00000000; | |
1920 | if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) { | |
1921 | /* | |
1922 | * Intel ("GenuineIntel") | |
1923 | * remark: Intel CPUs only support "syscall" in 64bit | |
1924 | * longmode. Also an 64bit guest with a | |
1925 | * 32bit compat-app running will #UD !! While this | |
1926 | * behaviour can be fixed (by emulating) into AMD | |
1927 | * response - CPUs of AMD can't behave like Intel. | |
1928 | */ | |
1929 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
1930 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
1931 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
1932 | return false; | |
1933 | ||
1934 | /* AMD ("AuthenticAMD") */ | |
1935 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
1936 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
1937 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
1938 | return true; | |
1939 | ||
1940 | /* AMD ("AMDisbetter!") */ | |
1941 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
1942 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
1943 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
1944 | return true; | |
1945 | } | |
1946 | ||
1947 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
1948 | return false; | |
1949 | } | |
1950 | ||
e01991e7 | 1951 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 1952 | { |
7b105ca2 | 1953 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 1954 | struct desc_struct cs, ss; |
e66bb2cc | 1955 | u64 msr_data; |
79168fd1 | 1956 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 1957 | u64 efer = 0; |
e66bb2cc AP |
1958 | |
1959 | /* syscall is not available in real mode */ | |
2e901c4c | 1960 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
1961 | ctxt->mode == X86EMUL_MODE_VM86) |
1962 | return emulate_ud(ctxt); | |
e66bb2cc | 1963 | |
c2226fc9 SB |
1964 | if (!(em_syscall_is_enabled(ctxt))) |
1965 | return emulate_ud(ctxt); | |
1966 | ||
c2ad2bb3 | 1967 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 1968 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 1969 | |
c2226fc9 SB |
1970 | if (!(efer & EFER_SCE)) |
1971 | return emulate_ud(ctxt); | |
1972 | ||
717746e3 | 1973 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 1974 | msr_data >>= 32; |
79168fd1 GN |
1975 | cs_sel = (u16)(msr_data & 0xfffc); |
1976 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 1977 | |
c2ad2bb3 | 1978 | if (efer & EFER_LMA) { |
79168fd1 | 1979 | cs.d = 0; |
e66bb2cc AP |
1980 | cs.l = 1; |
1981 | } | |
1aa36616 AK |
1982 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
1983 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 1984 | |
9dac77fa | 1985 | ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip; |
c2ad2bb3 | 1986 | if (efer & EFER_LMA) { |
e66bb2cc | 1987 | #ifdef CONFIG_X86_64 |
9dac77fa | 1988 | ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 1989 | |
717746e3 | 1990 | ops->get_msr(ctxt, |
3fb1b5db GN |
1991 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
1992 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 1993 | ctxt->_eip = msr_data; |
e66bb2cc | 1994 | |
717746e3 | 1995 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1996 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1997 | #endif | |
1998 | } else { | |
1999 | /* legacy mode */ | |
717746e3 | 2000 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2001 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
2002 | |
2003 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2004 | } | |
2005 | ||
e54cfa97 | 2006 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2007 | } |
2008 | ||
e01991e7 | 2009 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2010 | { |
7b105ca2 | 2011 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2012 | struct desc_struct cs, ss; |
8c604352 | 2013 | u64 msr_data; |
79168fd1 | 2014 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2015 | u64 efer = 0; |
8c604352 | 2016 | |
7b105ca2 | 2017 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2018 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2019 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2020 | return emulate_gp(ctxt, 0); | |
8c604352 | 2021 | |
1a18a69b AK |
2022 | /* |
2023 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2024 | * mode). | |
2025 | */ | |
2026 | if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) | |
2027 | && !vendor_intel(ctxt)) | |
2028 | return emulate_ud(ctxt); | |
2029 | ||
8c604352 AP |
2030 | /* XXX sysenter/sysexit have not been tested in 64bit mode. |
2031 | * Therefore, we inject an #UD. | |
2032 | */ | |
35d3d4a1 AK |
2033 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
2034 | return emulate_ud(ctxt); | |
8c604352 | 2035 | |
7b105ca2 | 2036 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2037 | |
717746e3 | 2038 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2039 | switch (ctxt->mode) { |
2040 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
2041 | if ((msr_data & 0xfffc) == 0x0) |
2042 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2043 | break; |
2044 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
2045 | if (msr_data == 0x0) |
2046 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2047 | break; |
2048 | } | |
2049 | ||
2050 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2051 | cs_sel = (u16)msr_data; |
2052 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2053 | ss_sel = cs_sel + 8; | |
2054 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 2055 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 2056 | cs.d = 0; |
8c604352 AP |
2057 | cs.l = 1; |
2058 | } | |
2059 | ||
1aa36616 AK |
2060 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2061 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2062 | |
717746e3 | 2063 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 2064 | ctxt->_eip = msr_data; |
8c604352 | 2065 | |
717746e3 | 2066 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
9dac77fa | 2067 | ctxt->regs[VCPU_REGS_RSP] = msr_data; |
8c604352 | 2068 | |
e54cfa97 | 2069 | return X86EMUL_CONTINUE; |
8c604352 AP |
2070 | } |
2071 | ||
e01991e7 | 2072 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2073 | { |
7b105ca2 | 2074 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2075 | struct desc_struct cs, ss; |
4668f050 AP |
2076 | u64 msr_data; |
2077 | int usermode; | |
1249b96e | 2078 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2079 | |
a0044755 GN |
2080 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2081 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2082 | ctxt->mode == X86EMUL_MODE_VM86) |
2083 | return emulate_gp(ctxt, 0); | |
4668f050 | 2084 | |
7b105ca2 | 2085 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2086 | |
9dac77fa | 2087 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2088 | usermode = X86EMUL_MODE_PROT64; |
2089 | else | |
2090 | usermode = X86EMUL_MODE_PROT32; | |
2091 | ||
2092 | cs.dpl = 3; | |
2093 | ss.dpl = 3; | |
717746e3 | 2094 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2095 | switch (usermode) { |
2096 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2097 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2098 | if ((msr_data & 0xfffc) == 0x0) |
2099 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2100 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2101 | break; |
2102 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2103 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2104 | if (msr_data == 0x0) |
2105 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2106 | ss_sel = cs_sel + 8; |
2107 | cs.d = 0; | |
4668f050 AP |
2108 | cs.l = 1; |
2109 | break; | |
2110 | } | |
79168fd1 GN |
2111 | cs_sel |= SELECTOR_RPL_MASK; |
2112 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2113 | |
1aa36616 AK |
2114 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2115 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2116 | |
9dac77fa AK |
2117 | ctxt->_eip = ctxt->regs[VCPU_REGS_RDX]; |
2118 | ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX]; | |
4668f050 | 2119 | |
e54cfa97 | 2120 | return X86EMUL_CONTINUE; |
4668f050 AP |
2121 | } |
2122 | ||
7b105ca2 | 2123 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2124 | { |
2125 | int iopl; | |
2126 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2127 | return false; | |
2128 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2129 | return true; | |
2130 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2131 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2132 | } |
2133 | ||
2134 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2135 | u16 port, u16 len) |
2136 | { | |
7b105ca2 | 2137 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2138 | struct desc_struct tr_seg; |
5601d05b | 2139 | u32 base3; |
f850e2e6 | 2140 | int r; |
1aa36616 | 2141 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2142 | unsigned mask = (1 << len) - 1; |
5601d05b | 2143 | unsigned long base; |
f850e2e6 | 2144 | |
1aa36616 | 2145 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2146 | if (!tr_seg.p) |
f850e2e6 | 2147 | return false; |
79168fd1 | 2148 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2149 | return false; |
5601d05b GN |
2150 | base = get_desc_base(&tr_seg); |
2151 | #ifdef CONFIG_X86_64 | |
2152 | base |= ((u64)base3) << 32; | |
2153 | #endif | |
0f65dd70 | 2154 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2155 | if (r != X86EMUL_CONTINUE) |
2156 | return false; | |
79168fd1 | 2157 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2158 | return false; |
0f65dd70 | 2159 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2160 | if (r != X86EMUL_CONTINUE) |
2161 | return false; | |
2162 | if ((perm >> bit_idx) & mask) | |
2163 | return false; | |
2164 | return true; | |
2165 | } | |
2166 | ||
2167 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2168 | u16 port, u16 len) |
2169 | { | |
4fc40f07 GN |
2170 | if (ctxt->perm_ok) |
2171 | return true; | |
2172 | ||
7b105ca2 TY |
2173 | if (emulator_bad_iopl(ctxt)) |
2174 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2175 | return false; |
4fc40f07 GN |
2176 | |
2177 | ctxt->perm_ok = true; | |
2178 | ||
f850e2e6 GN |
2179 | return true; |
2180 | } | |
2181 | ||
38ba30ba | 2182 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2183 | struct tss_segment_16 *tss) |
2184 | { | |
9dac77fa | 2185 | tss->ip = ctxt->_eip; |
38ba30ba | 2186 | tss->flag = ctxt->eflags; |
9dac77fa AK |
2187 | tss->ax = ctxt->regs[VCPU_REGS_RAX]; |
2188 | tss->cx = ctxt->regs[VCPU_REGS_RCX]; | |
2189 | tss->dx = ctxt->regs[VCPU_REGS_RDX]; | |
2190 | tss->bx = ctxt->regs[VCPU_REGS_RBX]; | |
2191 | tss->sp = ctxt->regs[VCPU_REGS_RSP]; | |
2192 | tss->bp = ctxt->regs[VCPU_REGS_RBP]; | |
2193 | tss->si = ctxt->regs[VCPU_REGS_RSI]; | |
2194 | tss->di = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2195 | |
1aa36616 AK |
2196 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2197 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2198 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2199 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2200 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2201 | } |
2202 | ||
2203 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2204 | struct tss_segment_16 *tss) |
2205 | { | |
38ba30ba GN |
2206 | int ret; |
2207 | ||
9dac77fa | 2208 | ctxt->_eip = tss->ip; |
38ba30ba | 2209 | ctxt->eflags = tss->flag | 2; |
9dac77fa AK |
2210 | ctxt->regs[VCPU_REGS_RAX] = tss->ax; |
2211 | ctxt->regs[VCPU_REGS_RCX] = tss->cx; | |
2212 | ctxt->regs[VCPU_REGS_RDX] = tss->dx; | |
2213 | ctxt->regs[VCPU_REGS_RBX] = tss->bx; | |
2214 | ctxt->regs[VCPU_REGS_RSP] = tss->sp; | |
2215 | ctxt->regs[VCPU_REGS_RBP] = tss->bp; | |
2216 | ctxt->regs[VCPU_REGS_RSI] = tss->si; | |
2217 | ctxt->regs[VCPU_REGS_RDI] = tss->di; | |
38ba30ba GN |
2218 | |
2219 | /* | |
2220 | * SDM says that segment selectors are loaded before segment | |
2221 | * descriptors | |
2222 | */ | |
1aa36616 AK |
2223 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2224 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2225 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2226 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2227 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2228 | |
2229 | /* | |
2230 | * Now load segment descriptors. If fault happenes at this stage | |
2231 | * it is handled in a context of new task | |
2232 | */ | |
7b105ca2 | 2233 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2234 | if (ret != X86EMUL_CONTINUE) |
2235 | return ret; | |
7b105ca2 | 2236 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2237 | if (ret != X86EMUL_CONTINUE) |
2238 | return ret; | |
7b105ca2 | 2239 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2240 | if (ret != X86EMUL_CONTINUE) |
2241 | return ret; | |
7b105ca2 | 2242 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2243 | if (ret != X86EMUL_CONTINUE) |
2244 | return ret; | |
7b105ca2 | 2245 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2246 | if (ret != X86EMUL_CONTINUE) |
2247 | return ret; | |
2248 | ||
2249 | return X86EMUL_CONTINUE; | |
2250 | } | |
2251 | ||
2252 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2253 | u16 tss_selector, u16 old_tss_sel, |
2254 | ulong old_tss_base, struct desc_struct *new_desc) | |
2255 | { | |
7b105ca2 | 2256 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2257 | struct tss_segment_16 tss_seg; |
2258 | int ret; | |
bcc55cba | 2259 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2260 | |
0f65dd70 | 2261 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2262 | &ctxt->exception); |
db297e3d | 2263 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2264 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2265 | return ret; |
38ba30ba | 2266 | |
7b105ca2 | 2267 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2268 | |
0f65dd70 | 2269 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2270 | &ctxt->exception); |
db297e3d | 2271 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2272 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2273 | return ret; |
38ba30ba | 2274 | |
0f65dd70 | 2275 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2276 | &ctxt->exception); |
db297e3d | 2277 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2278 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2279 | return ret; |
38ba30ba GN |
2280 | |
2281 | if (old_tss_sel != 0xffff) { | |
2282 | tss_seg.prev_task_link = old_tss_sel; | |
2283 | ||
0f65dd70 | 2284 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2285 | &tss_seg.prev_task_link, |
2286 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2287 | &ctxt->exception); |
db297e3d | 2288 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2289 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2290 | return ret; |
38ba30ba GN |
2291 | } |
2292 | ||
7b105ca2 | 2293 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2294 | } |
2295 | ||
2296 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2297 | struct tss_segment_32 *tss) |
2298 | { | |
7b105ca2 | 2299 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2300 | tss->eip = ctxt->_eip; |
38ba30ba | 2301 | tss->eflags = ctxt->eflags; |
9dac77fa AK |
2302 | tss->eax = ctxt->regs[VCPU_REGS_RAX]; |
2303 | tss->ecx = ctxt->regs[VCPU_REGS_RCX]; | |
2304 | tss->edx = ctxt->regs[VCPU_REGS_RDX]; | |
2305 | tss->ebx = ctxt->regs[VCPU_REGS_RBX]; | |
2306 | tss->esp = ctxt->regs[VCPU_REGS_RSP]; | |
2307 | tss->ebp = ctxt->regs[VCPU_REGS_RBP]; | |
2308 | tss->esi = ctxt->regs[VCPU_REGS_RSI]; | |
2309 | tss->edi = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2310 | |
1aa36616 AK |
2311 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2312 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2313 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2314 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2315 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2316 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2317 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2318 | } |
2319 | ||
2320 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2321 | struct tss_segment_32 *tss) |
2322 | { | |
38ba30ba GN |
2323 | int ret; |
2324 | ||
7b105ca2 | 2325 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2326 | return emulate_gp(ctxt, 0); |
9dac77fa | 2327 | ctxt->_eip = tss->eip; |
38ba30ba | 2328 | ctxt->eflags = tss->eflags | 2; |
9dac77fa AK |
2329 | ctxt->regs[VCPU_REGS_RAX] = tss->eax; |
2330 | ctxt->regs[VCPU_REGS_RCX] = tss->ecx; | |
2331 | ctxt->regs[VCPU_REGS_RDX] = tss->edx; | |
2332 | ctxt->regs[VCPU_REGS_RBX] = tss->ebx; | |
2333 | ctxt->regs[VCPU_REGS_RSP] = tss->esp; | |
2334 | ctxt->regs[VCPU_REGS_RBP] = tss->ebp; | |
2335 | ctxt->regs[VCPU_REGS_RSI] = tss->esi; | |
2336 | ctxt->regs[VCPU_REGS_RDI] = tss->edi; | |
38ba30ba GN |
2337 | |
2338 | /* | |
2339 | * SDM says that segment selectors are loaded before segment | |
2340 | * descriptors | |
2341 | */ | |
1aa36616 AK |
2342 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2343 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2344 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2345 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2346 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2347 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2348 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba GN |
2349 | |
2350 | /* | |
2351 | * Now load segment descriptors. If fault happenes at this stage | |
2352 | * it is handled in a context of new task | |
2353 | */ | |
7b105ca2 | 2354 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2355 | if (ret != X86EMUL_CONTINUE) |
2356 | return ret; | |
7b105ca2 | 2357 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2358 | if (ret != X86EMUL_CONTINUE) |
2359 | return ret; | |
7b105ca2 | 2360 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2361 | if (ret != X86EMUL_CONTINUE) |
2362 | return ret; | |
7b105ca2 | 2363 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2364 | if (ret != X86EMUL_CONTINUE) |
2365 | return ret; | |
7b105ca2 | 2366 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2367 | if (ret != X86EMUL_CONTINUE) |
2368 | return ret; | |
7b105ca2 | 2369 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2370 | if (ret != X86EMUL_CONTINUE) |
2371 | return ret; | |
7b105ca2 | 2372 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2373 | if (ret != X86EMUL_CONTINUE) |
2374 | return ret; | |
2375 | ||
2376 | return X86EMUL_CONTINUE; | |
2377 | } | |
2378 | ||
2379 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2380 | u16 tss_selector, u16 old_tss_sel, |
2381 | ulong old_tss_base, struct desc_struct *new_desc) | |
2382 | { | |
7b105ca2 | 2383 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2384 | struct tss_segment_32 tss_seg; |
2385 | int ret; | |
bcc55cba | 2386 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2387 | |
0f65dd70 | 2388 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2389 | &ctxt->exception); |
db297e3d | 2390 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2391 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2392 | return ret; |
38ba30ba | 2393 | |
7b105ca2 | 2394 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2395 | |
0f65dd70 | 2396 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2397 | &ctxt->exception); |
db297e3d | 2398 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2399 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2400 | return ret; |
38ba30ba | 2401 | |
0f65dd70 | 2402 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2403 | &ctxt->exception); |
db297e3d | 2404 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2405 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2406 | return ret; |
38ba30ba GN |
2407 | |
2408 | if (old_tss_sel != 0xffff) { | |
2409 | tss_seg.prev_task_link = old_tss_sel; | |
2410 | ||
0f65dd70 | 2411 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2412 | &tss_seg.prev_task_link, |
2413 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2414 | &ctxt->exception); |
db297e3d | 2415 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2416 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2417 | return ret; |
38ba30ba GN |
2418 | } |
2419 | ||
7b105ca2 | 2420 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2421 | } |
2422 | ||
2423 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2424 | u16 tss_selector, int reason, |
2425 | bool has_error_code, u32 error_code) | |
38ba30ba | 2426 | { |
7b105ca2 | 2427 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2428 | struct desc_struct curr_tss_desc, next_tss_desc; |
2429 | int ret; | |
1aa36616 | 2430 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2431 | ulong old_tss_base = |
4bff1e86 | 2432 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2433 | u32 desc_limit; |
38ba30ba GN |
2434 | |
2435 | /* FIXME: old_tss_base == ~0 ? */ | |
2436 | ||
7b105ca2 | 2437 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2438 | if (ret != X86EMUL_CONTINUE) |
2439 | return ret; | |
7b105ca2 | 2440 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2441 | if (ret != X86EMUL_CONTINUE) |
2442 | return ret; | |
2443 | ||
2444 | /* FIXME: check that next_tss_desc is tss */ | |
2445 | ||
2446 | if (reason != TASK_SWITCH_IRET) { | |
2447 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
717746e3 | 2448 | ops->cpl(ctxt) > next_tss_desc.dpl) |
35d3d4a1 | 2449 | return emulate_gp(ctxt, 0); |
38ba30ba GN |
2450 | } |
2451 | ||
ceffb459 GN |
2452 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2453 | if (!next_tss_desc.p || | |
2454 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2455 | desc_limit < 0x2b)) { | |
54b8486f | 2456 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2457 | return X86EMUL_PROPAGATE_FAULT; |
2458 | } | |
2459 | ||
2460 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2461 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2462 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2463 | } |
2464 | ||
2465 | if (reason == TASK_SWITCH_IRET) | |
2466 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2467 | ||
2468 | /* set back link to prev task only if NT bit is set in eflags | |
2469 | note that old_tss_sel is not used afetr this point */ | |
2470 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2471 | old_tss_sel = 0xffff; | |
2472 | ||
2473 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2474 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2475 | old_tss_base, &next_tss_desc); |
2476 | else | |
7b105ca2 | 2477 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2478 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2479 | if (ret != X86EMUL_CONTINUE) |
2480 | return ret; | |
38ba30ba GN |
2481 | |
2482 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2483 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2484 | ||
2485 | if (reason != TASK_SWITCH_IRET) { | |
2486 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2487 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2488 | } |
2489 | ||
717746e3 | 2490 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2491 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2492 | |
e269fb21 | 2493 | if (has_error_code) { |
9dac77fa AK |
2494 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2495 | ctxt->lock_prefix = 0; | |
2496 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2497 | ret = em_push(ctxt); |
e269fb21 JK |
2498 | } |
2499 | ||
38ba30ba GN |
2500 | return ret; |
2501 | } | |
2502 | ||
2503 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2504 | u16 tss_selector, int reason, |
2505 | bool has_error_code, u32 error_code) | |
38ba30ba | 2506 | { |
38ba30ba GN |
2507 | int rc; |
2508 | ||
9dac77fa AK |
2509 | ctxt->_eip = ctxt->eip; |
2510 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2511 | |
7b105ca2 | 2512 | rc = emulator_do_task_switch(ctxt, tss_selector, reason, |
e269fb21 | 2513 | has_error_code, error_code); |
38ba30ba | 2514 | |
4179bb02 | 2515 | if (rc == X86EMUL_CONTINUE) |
9dac77fa | 2516 | ctxt->eip = ctxt->_eip; |
38ba30ba | 2517 | |
a0c0ab2f | 2518 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2519 | } |
2520 | ||
90de84f5 | 2521 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2522 | int reg, struct operand *op) |
a682e354 | 2523 | { |
a682e354 GN |
2524 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; |
2525 | ||
9dac77fa AK |
2526 | register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes); |
2527 | op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]); | |
90de84f5 | 2528 | op->addr.mem.seg = seg; |
a682e354 GN |
2529 | } |
2530 | ||
7af04fc0 AK |
2531 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2532 | { | |
7af04fc0 AK |
2533 | u8 al, old_al; |
2534 | bool af, cf, old_cf; | |
2535 | ||
2536 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2537 | al = ctxt->dst.val; |
7af04fc0 AK |
2538 | |
2539 | old_al = al; | |
2540 | old_cf = cf; | |
2541 | cf = false; | |
2542 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2543 | if ((al & 0x0f) > 9 || af) { | |
2544 | al -= 6; | |
2545 | cf = old_cf | (al >= 250); | |
2546 | af = true; | |
2547 | } else { | |
2548 | af = false; | |
2549 | } | |
2550 | if (old_al > 0x99 || old_cf) { | |
2551 | al -= 0x60; | |
2552 | cf = true; | |
2553 | } | |
2554 | ||
9dac77fa | 2555 | ctxt->dst.val = al; |
7af04fc0 | 2556 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2557 | ctxt->src.type = OP_IMM; |
2558 | ctxt->src.val = 0; | |
2559 | ctxt->src.bytes = 1; | |
a31b9cea | 2560 | emulate_2op_SrcV(ctxt, "or"); |
7af04fc0 AK |
2561 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2562 | if (cf) | |
2563 | ctxt->eflags |= X86_EFLAGS_CF; | |
2564 | if (af) | |
2565 | ctxt->eflags |= X86_EFLAGS_AF; | |
2566 | return X86EMUL_CONTINUE; | |
2567 | } | |
2568 | ||
d4ddafcd TY |
2569 | static int em_call(struct x86_emulate_ctxt *ctxt) |
2570 | { | |
2571 | long rel = ctxt->src.val; | |
2572 | ||
2573 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
2574 | jmp_rel(ctxt, rel); | |
2575 | return em_push(ctxt); | |
2576 | } | |
2577 | ||
0ef753b8 AK |
2578 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2579 | { | |
0ef753b8 AK |
2580 | u16 sel, old_cs; |
2581 | ulong old_eip; | |
2582 | int rc; | |
2583 | ||
1aa36616 | 2584 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 2585 | old_eip = ctxt->_eip; |
0ef753b8 | 2586 | |
9dac77fa | 2587 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 2588 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
2589 | return X86EMUL_CONTINUE; |
2590 | ||
9dac77fa AK |
2591 | ctxt->_eip = 0; |
2592 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 2593 | |
9dac77fa | 2594 | ctxt->src.val = old_cs; |
4487b3b4 | 2595 | rc = em_push(ctxt); |
0ef753b8 AK |
2596 | if (rc != X86EMUL_CONTINUE) |
2597 | return rc; | |
2598 | ||
9dac77fa | 2599 | ctxt->src.val = old_eip; |
4487b3b4 | 2600 | return em_push(ctxt); |
0ef753b8 AK |
2601 | } |
2602 | ||
40ece7c7 AK |
2603 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2604 | { | |
40ece7c7 AK |
2605 | int rc; |
2606 | ||
9dac77fa AK |
2607 | ctxt->dst.type = OP_REG; |
2608 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2609 | ctxt->dst.bytes = ctxt->op_bytes; | |
2610 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
2611 | if (rc != X86EMUL_CONTINUE) |
2612 | return rc; | |
9dac77fa | 2613 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); |
40ece7c7 AK |
2614 | return X86EMUL_CONTINUE; |
2615 | } | |
2616 | ||
d67fc27a TY |
2617 | static int em_add(struct x86_emulate_ctxt *ctxt) |
2618 | { | |
a31b9cea | 2619 | emulate_2op_SrcV(ctxt, "add"); |
d67fc27a TY |
2620 | return X86EMUL_CONTINUE; |
2621 | } | |
2622 | ||
2623 | static int em_or(struct x86_emulate_ctxt *ctxt) | |
2624 | { | |
a31b9cea | 2625 | emulate_2op_SrcV(ctxt, "or"); |
d67fc27a TY |
2626 | return X86EMUL_CONTINUE; |
2627 | } | |
2628 | ||
2629 | static int em_adc(struct x86_emulate_ctxt *ctxt) | |
2630 | { | |
a31b9cea | 2631 | emulate_2op_SrcV(ctxt, "adc"); |
d67fc27a TY |
2632 | return X86EMUL_CONTINUE; |
2633 | } | |
2634 | ||
2635 | static int em_sbb(struct x86_emulate_ctxt *ctxt) | |
2636 | { | |
a31b9cea | 2637 | emulate_2op_SrcV(ctxt, "sbb"); |
d67fc27a TY |
2638 | return X86EMUL_CONTINUE; |
2639 | } | |
2640 | ||
2641 | static int em_and(struct x86_emulate_ctxt *ctxt) | |
2642 | { | |
a31b9cea | 2643 | emulate_2op_SrcV(ctxt, "and"); |
d67fc27a TY |
2644 | return X86EMUL_CONTINUE; |
2645 | } | |
2646 | ||
2647 | static int em_sub(struct x86_emulate_ctxt *ctxt) | |
2648 | { | |
a31b9cea | 2649 | emulate_2op_SrcV(ctxt, "sub"); |
d67fc27a TY |
2650 | return X86EMUL_CONTINUE; |
2651 | } | |
2652 | ||
2653 | static int em_xor(struct x86_emulate_ctxt *ctxt) | |
2654 | { | |
a31b9cea | 2655 | emulate_2op_SrcV(ctxt, "xor"); |
d67fc27a TY |
2656 | return X86EMUL_CONTINUE; |
2657 | } | |
2658 | ||
2659 | static int em_cmp(struct x86_emulate_ctxt *ctxt) | |
2660 | { | |
a31b9cea | 2661 | emulate_2op_SrcV(ctxt, "cmp"); |
d67fc27a | 2662 | /* Disable writeback. */ |
9dac77fa | 2663 | ctxt->dst.type = OP_NONE; |
d67fc27a TY |
2664 | return X86EMUL_CONTINUE; |
2665 | } | |
2666 | ||
9f21ca59 TY |
2667 | static int em_test(struct x86_emulate_ctxt *ctxt) |
2668 | { | |
a31b9cea | 2669 | emulate_2op_SrcV(ctxt, "test"); |
caa8a168 AK |
2670 | /* Disable writeback. */ |
2671 | ctxt->dst.type = OP_NONE; | |
9f21ca59 TY |
2672 | return X86EMUL_CONTINUE; |
2673 | } | |
2674 | ||
e4f973ae TY |
2675 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
2676 | { | |
e4f973ae | 2677 | /* Write back the register source. */ |
9dac77fa AK |
2678 | ctxt->src.val = ctxt->dst.val; |
2679 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
2680 | |
2681 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
2682 | ctxt->dst.val = ctxt->src.orig_val; |
2683 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
2684 | return X86EMUL_CONTINUE; |
2685 | } | |
2686 | ||
5c82aa29 | 2687 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 | 2688 | { |
a31b9cea | 2689 | emulate_2op_SrcV_nobyte(ctxt, "imul"); |
f3a1b9f4 AK |
2690 | return X86EMUL_CONTINUE; |
2691 | } | |
2692 | ||
5c82aa29 AK |
2693 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2694 | { | |
9dac77fa | 2695 | ctxt->dst.val = ctxt->src2.val; |
5c82aa29 AK |
2696 | return em_imul(ctxt); |
2697 | } | |
2698 | ||
61429142 AK |
2699 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2700 | { | |
9dac77fa AK |
2701 | ctxt->dst.type = OP_REG; |
2702 | ctxt->dst.bytes = ctxt->src.bytes; | |
2703 | ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
2704 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); | |
61429142 AK |
2705 | |
2706 | return X86EMUL_CONTINUE; | |
2707 | } | |
2708 | ||
48bb5d3c AK |
2709 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2710 | { | |
48bb5d3c AK |
2711 | u64 tsc = 0; |
2712 | ||
717746e3 | 2713 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
9dac77fa AK |
2714 | ctxt->regs[VCPU_REGS_RAX] = (u32)tsc; |
2715 | ctxt->regs[VCPU_REGS_RDX] = tsc >> 32; | |
48bb5d3c AK |
2716 | return X86EMUL_CONTINUE; |
2717 | } | |
2718 | ||
222d21aa AK |
2719 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
2720 | { | |
2721 | u64 pmc; | |
2722 | ||
2723 | if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc)) | |
2724 | return emulate_gp(ctxt, 0); | |
2725 | ctxt->regs[VCPU_REGS_RAX] = (u32)pmc; | |
2726 | ctxt->regs[VCPU_REGS_RDX] = pmc >> 32; | |
2727 | return X86EMUL_CONTINUE; | |
2728 | } | |
2729 | ||
b9eac5f4 AK |
2730 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2731 | { | |
9dac77fa | 2732 | ctxt->dst.val = ctxt->src.val; |
b9eac5f4 AK |
2733 | return X86EMUL_CONTINUE; |
2734 | } | |
2735 | ||
bc00f8d2 TY |
2736 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
2737 | { | |
2738 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
2739 | return emulate_gp(ctxt, 0); | |
2740 | ||
2741 | /* Disable writeback. */ | |
2742 | ctxt->dst.type = OP_NONE; | |
2743 | return X86EMUL_CONTINUE; | |
2744 | } | |
2745 | ||
2746 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
2747 | { | |
2748 | unsigned long val; | |
2749 | ||
2750 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2751 | val = ctxt->src.val & ~0ULL; | |
2752 | else | |
2753 | val = ctxt->src.val & ~0U; | |
2754 | ||
2755 | /* #UD condition is already handled. */ | |
2756 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
2757 | return emulate_gp(ctxt, 0); | |
2758 | ||
2759 | /* Disable writeback. */ | |
2760 | ctxt->dst.type = OP_NONE; | |
2761 | return X86EMUL_CONTINUE; | |
2762 | } | |
2763 | ||
e1e210b0 TY |
2764 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
2765 | { | |
2766 | u64 msr_data; | |
2767 | ||
2768 | msr_data = (u32)ctxt->regs[VCPU_REGS_RAX] | |
2769 | | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32); | |
2770 | if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) | |
2771 | return emulate_gp(ctxt, 0); | |
2772 | ||
2773 | return X86EMUL_CONTINUE; | |
2774 | } | |
2775 | ||
2776 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
2777 | { | |
2778 | u64 msr_data; | |
2779 | ||
2780 | if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) | |
2781 | return emulate_gp(ctxt, 0); | |
2782 | ||
2783 | ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
2784 | ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
2785 | return X86EMUL_CONTINUE; | |
2786 | } | |
2787 | ||
1bd5f469 TY |
2788 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
2789 | { | |
9dac77fa | 2790 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2791 | return emulate_ud(ctxt); |
2792 | ||
9dac77fa | 2793 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
2794 | return X86EMUL_CONTINUE; |
2795 | } | |
2796 | ||
2797 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
2798 | { | |
9dac77fa | 2799 | u16 sel = ctxt->src.val; |
1bd5f469 | 2800 | |
9dac77fa | 2801 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2802 | return emulate_ud(ctxt); |
2803 | ||
9dac77fa | 2804 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
2805 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
2806 | ||
2807 | /* Disable writeback. */ | |
9dac77fa AK |
2808 | ctxt->dst.type = OP_NONE; |
2809 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
2810 | } |
2811 | ||
aa97bb48 AK |
2812 | static int em_movdqu(struct x86_emulate_ctxt *ctxt) |
2813 | { | |
9dac77fa | 2814 | memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes); |
aa97bb48 AK |
2815 | return X86EMUL_CONTINUE; |
2816 | } | |
2817 | ||
38503911 AK |
2818 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
2819 | { | |
9fa088f4 AK |
2820 | int rc; |
2821 | ulong linear; | |
2822 | ||
9dac77fa | 2823 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 2824 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 2825 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 2826 | /* Disable writeback. */ |
9dac77fa | 2827 | ctxt->dst.type = OP_NONE; |
38503911 AK |
2828 | return X86EMUL_CONTINUE; |
2829 | } | |
2830 | ||
2d04a05b AK |
2831 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
2832 | { | |
2833 | ulong cr0; | |
2834 | ||
2835 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
2836 | cr0 &= ~X86_CR0_TS; | |
2837 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
2838 | return X86EMUL_CONTINUE; | |
2839 | } | |
2840 | ||
26d05cc7 AK |
2841 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
2842 | { | |
26d05cc7 AK |
2843 | int rc; |
2844 | ||
9dac77fa | 2845 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
2846 | return X86EMUL_UNHANDLEABLE; |
2847 | ||
2848 | rc = ctxt->ops->fix_hypercall(ctxt); | |
2849 | if (rc != X86EMUL_CONTINUE) | |
2850 | return rc; | |
2851 | ||
2852 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 2853 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 2854 | /* Disable writeback. */ |
9dac77fa | 2855 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2856 | return X86EMUL_CONTINUE; |
2857 | } | |
2858 | ||
2859 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) | |
2860 | { | |
26d05cc7 AK |
2861 | struct desc_ptr desc_ptr; |
2862 | int rc; | |
2863 | ||
9dac77fa | 2864 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 2865 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2866 | ctxt->op_bytes); |
26d05cc7 AK |
2867 | if (rc != X86EMUL_CONTINUE) |
2868 | return rc; | |
2869 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
2870 | /* Disable writeback. */ | |
9dac77fa | 2871 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2872 | return X86EMUL_CONTINUE; |
2873 | } | |
2874 | ||
5ef39c71 | 2875 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 2876 | { |
26d05cc7 AK |
2877 | int rc; |
2878 | ||
5ef39c71 AK |
2879 | rc = ctxt->ops->fix_hypercall(ctxt); |
2880 | ||
26d05cc7 | 2881 | /* Disable writeback. */ |
9dac77fa | 2882 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2883 | return rc; |
2884 | } | |
2885 | ||
2886 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
2887 | { | |
26d05cc7 AK |
2888 | struct desc_ptr desc_ptr; |
2889 | int rc; | |
2890 | ||
9dac77fa | 2891 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 2892 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2893 | ctxt->op_bytes); |
26d05cc7 AK |
2894 | if (rc != X86EMUL_CONTINUE) |
2895 | return rc; | |
2896 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
2897 | /* Disable writeback. */ | |
9dac77fa | 2898 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2899 | return X86EMUL_CONTINUE; |
2900 | } | |
2901 | ||
2902 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
2903 | { | |
9dac77fa AK |
2904 | ctxt->dst.bytes = 2; |
2905 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
2906 | return X86EMUL_CONTINUE; |
2907 | } | |
2908 | ||
2909 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
2910 | { | |
26d05cc7 | 2911 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
2912 | | (ctxt->src.val & 0x0f)); |
2913 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
2914 | return X86EMUL_CONTINUE; |
2915 | } | |
2916 | ||
d06e03ad TY |
2917 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
2918 | { | |
9dac77fa AK |
2919 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); |
2920 | if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) && | |
2921 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) | |
2922 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
2923 | |
2924 | return X86EMUL_CONTINUE; | |
2925 | } | |
2926 | ||
2927 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
2928 | { | |
9dac77fa AK |
2929 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) |
2930 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
2931 | |
2932 | return X86EMUL_CONTINUE; | |
2933 | } | |
2934 | ||
d7841a4b TY |
2935 | static int em_in(struct x86_emulate_ctxt *ctxt) |
2936 | { | |
2937 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
2938 | &ctxt->dst.val)) | |
2939 | return X86EMUL_IO_NEEDED; | |
2940 | ||
2941 | return X86EMUL_CONTINUE; | |
2942 | } | |
2943 | ||
2944 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
2945 | { | |
2946 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
2947 | &ctxt->src.val, 1); | |
2948 | /* Disable writeback. */ | |
2949 | ctxt->dst.type = OP_NONE; | |
2950 | return X86EMUL_CONTINUE; | |
2951 | } | |
2952 | ||
f411e6cd TY |
2953 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
2954 | { | |
2955 | if (emulator_bad_iopl(ctxt)) | |
2956 | return emulate_gp(ctxt, 0); | |
2957 | ||
2958 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
2959 | return X86EMUL_CONTINUE; | |
2960 | } | |
2961 | ||
2962 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
2963 | { | |
2964 | if (emulator_bad_iopl(ctxt)) | |
2965 | return emulate_gp(ctxt, 0); | |
2966 | ||
2967 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
2968 | ctxt->eflags |= X86_EFLAGS_IF; | |
2969 | return X86EMUL_CONTINUE; | |
2970 | } | |
2971 | ||
ce7faab2 TY |
2972 | static int em_bt(struct x86_emulate_ctxt *ctxt) |
2973 | { | |
2974 | /* Disable writeback. */ | |
2975 | ctxt->dst.type = OP_NONE; | |
2976 | /* only subword offset */ | |
2977 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; | |
2978 | ||
2979 | emulate_2op_SrcV_nobyte(ctxt, "bt"); | |
2980 | return X86EMUL_CONTINUE; | |
2981 | } | |
2982 | ||
2983 | static int em_bts(struct x86_emulate_ctxt *ctxt) | |
2984 | { | |
2985 | emulate_2op_SrcV_nobyte(ctxt, "bts"); | |
2986 | return X86EMUL_CONTINUE; | |
2987 | } | |
2988 | ||
2989 | static int em_btr(struct x86_emulate_ctxt *ctxt) | |
2990 | { | |
2991 | emulate_2op_SrcV_nobyte(ctxt, "btr"); | |
2992 | return X86EMUL_CONTINUE; | |
2993 | } | |
2994 | ||
2995 | static int em_btc(struct x86_emulate_ctxt *ctxt) | |
2996 | { | |
2997 | emulate_2op_SrcV_nobyte(ctxt, "btc"); | |
2998 | return X86EMUL_CONTINUE; | |
2999 | } | |
3000 | ||
ff227392 TY |
3001 | static int em_bsf(struct x86_emulate_ctxt *ctxt) |
3002 | { | |
3003 | u8 zf; | |
3004 | ||
3005 | __asm__ ("bsf %2, %0; setz %1" | |
3006 | : "=r"(ctxt->dst.val), "=q"(zf) | |
3007 | : "r"(ctxt->src.val)); | |
3008 | ||
3009 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3010 | if (zf) { | |
3011 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3012 | /* Disable writeback. */ | |
3013 | ctxt->dst.type = OP_NONE; | |
3014 | } | |
3015 | return X86EMUL_CONTINUE; | |
3016 | } | |
3017 | ||
3018 | static int em_bsr(struct x86_emulate_ctxt *ctxt) | |
3019 | { | |
3020 | u8 zf; | |
3021 | ||
3022 | __asm__ ("bsr %2, %0; setz %1" | |
3023 | : "=r"(ctxt->dst.val), "=q"(zf) | |
3024 | : "r"(ctxt->src.val)); | |
3025 | ||
3026 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3027 | if (zf) { | |
3028 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3029 | /* Disable writeback. */ | |
3030 | ctxt->dst.type = OP_NONE; | |
3031 | } | |
3032 | return X86EMUL_CONTINUE; | |
3033 | } | |
3034 | ||
cfec82cb JR |
3035 | static bool valid_cr(int nr) |
3036 | { | |
3037 | switch (nr) { | |
3038 | case 0: | |
3039 | case 2 ... 4: | |
3040 | case 8: | |
3041 | return true; | |
3042 | default: | |
3043 | return false; | |
3044 | } | |
3045 | } | |
3046 | ||
3047 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3048 | { | |
9dac77fa | 3049 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3050 | return emulate_ud(ctxt); |
3051 | ||
3052 | return X86EMUL_CONTINUE; | |
3053 | } | |
3054 | ||
3055 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3056 | { | |
9dac77fa AK |
3057 | u64 new_val = ctxt->src.val64; |
3058 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3059 | u64 efer = 0; |
cfec82cb JR |
3060 | |
3061 | static u64 cr_reserved_bits[] = { | |
3062 | 0xffffffff00000000ULL, | |
3063 | 0, 0, 0, /* CR3 checked later */ | |
3064 | CR4_RESERVED_BITS, | |
3065 | 0, 0, 0, | |
3066 | CR8_RESERVED_BITS, | |
3067 | }; | |
3068 | ||
3069 | if (!valid_cr(cr)) | |
3070 | return emulate_ud(ctxt); | |
3071 | ||
3072 | if (new_val & cr_reserved_bits[cr]) | |
3073 | return emulate_gp(ctxt, 0); | |
3074 | ||
3075 | switch (cr) { | |
3076 | case 0: { | |
c2ad2bb3 | 3077 | u64 cr4; |
cfec82cb JR |
3078 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3079 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3080 | return emulate_gp(ctxt, 0); | |
3081 | ||
717746e3 AK |
3082 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3083 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3084 | |
3085 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3086 | !(cr4 & X86_CR4_PAE)) | |
3087 | return emulate_gp(ctxt, 0); | |
3088 | ||
3089 | break; | |
3090 | } | |
3091 | case 3: { | |
3092 | u64 rsvd = 0; | |
3093 | ||
c2ad2bb3 AK |
3094 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3095 | if (efer & EFER_LMA) | |
cfec82cb | 3096 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 3097 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 3098 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 3099 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
3100 | rsvd = CR3_NONPAE_RESERVED_BITS; |
3101 | ||
3102 | if (new_val & rsvd) | |
3103 | return emulate_gp(ctxt, 0); | |
3104 | ||
3105 | break; | |
3106 | } | |
3107 | case 4: { | |
717746e3 | 3108 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3109 | |
3110 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3111 | return emulate_gp(ctxt, 0); | |
3112 | ||
3113 | break; | |
3114 | } | |
3115 | } | |
3116 | ||
3117 | return X86EMUL_CONTINUE; | |
3118 | } | |
3119 | ||
3b88e41a JR |
3120 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3121 | { | |
3122 | unsigned long dr7; | |
3123 | ||
717746e3 | 3124 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3125 | |
3126 | /* Check if DR7.Global_Enable is set */ | |
3127 | return dr7 & (1 << 13); | |
3128 | } | |
3129 | ||
3130 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3131 | { | |
9dac77fa | 3132 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3133 | u64 cr4; |
3134 | ||
3135 | if (dr > 7) | |
3136 | return emulate_ud(ctxt); | |
3137 | ||
717746e3 | 3138 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3139 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3140 | return emulate_ud(ctxt); | |
3141 | ||
3142 | if (check_dr7_gd(ctxt)) | |
3143 | return emulate_db(ctxt); | |
3144 | ||
3145 | return X86EMUL_CONTINUE; | |
3146 | } | |
3147 | ||
3148 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3149 | { | |
9dac77fa AK |
3150 | u64 new_val = ctxt->src.val64; |
3151 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3152 | |
3153 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3154 | return emulate_gp(ctxt, 0); | |
3155 | ||
3156 | return check_dr_read(ctxt); | |
3157 | } | |
3158 | ||
01de8b09 JR |
3159 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3160 | { | |
3161 | u64 efer; | |
3162 | ||
717746e3 | 3163 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3164 | |
3165 | if (!(efer & EFER_SVME)) | |
3166 | return emulate_ud(ctxt); | |
3167 | ||
3168 | return X86EMUL_CONTINUE; | |
3169 | } | |
3170 | ||
3171 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3172 | { | |
9dac77fa | 3173 | u64 rax = ctxt->regs[VCPU_REGS_RAX]; |
01de8b09 JR |
3174 | |
3175 | /* Valid physical address? */ | |
d4224449 | 3176 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3177 | return emulate_gp(ctxt, 0); |
3178 | ||
3179 | return check_svme(ctxt); | |
3180 | } | |
3181 | ||
d7eb8203 JR |
3182 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3183 | { | |
717746e3 | 3184 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3185 | |
717746e3 | 3186 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3187 | return emulate_ud(ctxt); |
3188 | ||
3189 | return X86EMUL_CONTINUE; | |
3190 | } | |
3191 | ||
8061252e JR |
3192 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3193 | { | |
717746e3 | 3194 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
9dac77fa | 3195 | u64 rcx = ctxt->regs[VCPU_REGS_RCX]; |
8061252e | 3196 | |
717746e3 | 3197 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
3198 | (rcx > 3)) |
3199 | return emulate_gp(ctxt, 0); | |
3200 | ||
3201 | return X86EMUL_CONTINUE; | |
3202 | } | |
3203 | ||
f6511935 JR |
3204 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3205 | { | |
9dac77fa AK |
3206 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3207 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3208 | return emulate_gp(ctxt, 0); |
3209 | ||
3210 | return X86EMUL_CONTINUE; | |
3211 | } | |
3212 | ||
3213 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3214 | { | |
9dac77fa AK |
3215 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3216 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3217 | return emulate_gp(ctxt, 0); |
3218 | ||
3219 | return X86EMUL_CONTINUE; | |
3220 | } | |
3221 | ||
73fba5f4 | 3222 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 3223 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
3224 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
3225 | .check_perm = (_p) } | |
73fba5f4 | 3226 | #define N D(0) |
01de8b09 | 3227 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
73fba5f4 | 3228 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } |
46561646 | 3229 | #define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) } |
73fba5f4 | 3230 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
c4f035c6 AK |
3231 | #define II(_f, _e, _i) \ |
3232 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
3233 | #define IIP(_f, _e, _i, _p) \ |
3234 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
3235 | .check_perm = (_p) } | |
aa97bb48 | 3236 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3237 | |
8d8f4e9f | 3238 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3239 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3240 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
d7841a4b TY |
3241 | #define I2bvIP(_f, _e, _i, _p) \ |
3242 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3243 | |
d67fc27a TY |
3244 | #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3245 | I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3246 | I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3247 | |
d7eb8203 JR |
3248 | static struct opcode group7_rm1[] = { |
3249 | DI(SrcNone | ModRM | Priv, monitor), | |
3250 | DI(SrcNone | ModRM | Priv, mwait), | |
3251 | N, N, N, N, N, N, | |
3252 | }; | |
3253 | ||
01de8b09 JR |
3254 | static struct opcode group7_rm3[] = { |
3255 | DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), | |
5ef39c71 | 3256 | II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall), |
01de8b09 JR |
3257 | DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), |
3258 | DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), | |
3259 | DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), | |
3260 | DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), | |
3261 | DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), | |
3262 | DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), | |
3263 | }; | |
6230f7fc | 3264 | |
d7eb8203 JR |
3265 | static struct opcode group7_rm7[] = { |
3266 | N, | |
3267 | DIP(SrcNone | ModRM, rdtscp, check_rdtsc), | |
3268 | N, N, N, N, N, N, | |
3269 | }; | |
d67fc27a | 3270 | |
73fba5f4 | 3271 | static struct opcode group1[] = { |
d67fc27a | 3272 | I(Lock, em_add), |
d5ae7ce8 | 3273 | I(Lock | PageTable, em_or), |
d67fc27a TY |
3274 | I(Lock, em_adc), |
3275 | I(Lock, em_sbb), | |
d5ae7ce8 | 3276 | I(Lock | PageTable, em_and), |
d67fc27a TY |
3277 | I(Lock, em_sub), |
3278 | I(Lock, em_xor), | |
3279 | I(0, em_cmp), | |
73fba5f4 AK |
3280 | }; |
3281 | ||
3282 | static struct opcode group1A[] = { | |
c15af35f | 3283 | I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3284 | }; |
3285 | ||
3286 | static struct opcode group3[] = { | |
3329ece1 AK |
3287 | I(DstMem | SrcImm | ModRM, em_test), |
3288 | I(DstMem | SrcImm | ModRM, em_test), | |
3289 | I(DstMem | SrcNone | ModRM | Lock, em_not), | |
3290 | I(DstMem | SrcNone | ModRM | Lock, em_neg), | |
3291 | I(SrcMem | ModRM, em_mul_ex), | |
3292 | I(SrcMem | ModRM, em_imul_ex), | |
3293 | I(SrcMem | ModRM, em_div_ex), | |
3294 | I(SrcMem | ModRM, em_idiv_ex), | |
73fba5f4 AK |
3295 | }; |
3296 | ||
3297 | static struct opcode group4[] = { | |
c04ec839 TY |
3298 | I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), |
3299 | I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), | |
73fba5f4 AK |
3300 | N, N, N, N, N, N, |
3301 | }; | |
3302 | ||
3303 | static struct opcode group5[] = { | |
c04ec839 TY |
3304 | I(DstMem | SrcNone | ModRM | Lock, em_grp45), |
3305 | I(DstMem | SrcNone | ModRM | Lock, em_grp45), | |
3306 | I(SrcMem | ModRM | Stack, em_grp45), | |
0ef753b8 | 3307 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), |
c04ec839 TY |
3308 | I(SrcMem | ModRM | Stack, em_grp45), |
3309 | I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45), | |
3310 | I(SrcMem | ModRM | Stack, em_grp45), N, | |
73fba5f4 AK |
3311 | }; |
3312 | ||
dee6bb70 JR |
3313 | static struct opcode group6[] = { |
3314 | DI(ModRM | Prot, sldt), | |
3315 | DI(ModRM | Prot, str), | |
3316 | DI(ModRM | Prot | Priv, lldt), | |
3317 | DI(ModRM | Prot | Priv, ltr), | |
3318 | N, N, N, N, | |
3319 | }; | |
3320 | ||
73fba5f4 | 3321 | static struct group_dual group7 = { { |
dee6bb70 JR |
3322 | DI(ModRM | Mov | DstMem | Priv, sgdt), |
3323 | DI(ModRM | Mov | DstMem | Priv, sidt), | |
5ef39c71 AK |
3324 | II(ModRM | SrcMem | Priv, em_lgdt, lgdt), |
3325 | II(ModRM | SrcMem | Priv, em_lidt, lidt), | |
3326 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, | |
3327 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), | |
3328 | II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3329 | }, { |
5ef39c71 AK |
3330 | I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall), |
3331 | EXT(0, group7_rm1), | |
01de8b09 | 3332 | N, EXT(0, group7_rm3), |
5ef39c71 AK |
3333 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, |
3334 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7), | |
73fba5f4 AK |
3335 | } }; |
3336 | ||
3337 | static struct opcode group8[] = { | |
3338 | N, N, N, N, | |
ce7faab2 TY |
3339 | I(DstMem | SrcImmByte | ModRM, em_bt), |
3340 | I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts), | |
3341 | I(DstMem | SrcImmByte | ModRM | Lock, em_btr), | |
3342 | I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3343 | }; |
3344 | ||
3345 | static struct group_dual group9 = { { | |
e0dac408 | 3346 | N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3347 | }, { |
3348 | N, N, N, N, N, N, N, N, | |
3349 | } }; | |
3350 | ||
a4d4a7c1 | 3351 | static struct opcode group11[] = { |
d5ae7ce8 XG |
3352 | I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov), |
3353 | X7(D(Undefined)), | |
a4d4a7c1 AK |
3354 | }; |
3355 | ||
aa97bb48 AK |
3356 | static struct gprefix pfx_0f_6f_0f_7f = { |
3357 | N, N, N, I(Sse, em_movdqu), | |
3358 | }; | |
3359 | ||
73fba5f4 AK |
3360 | static struct opcode opcode_table[256] = { |
3361 | /* 0x00 - 0x07 */ | |
d67fc27a | 3362 | I6ALU(Lock, em_add), |
1cd196ea AK |
3363 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
3364 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 3365 | /* 0x08 - 0x0F */ |
d5ae7ce8 | 3366 | I6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
3367 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
3368 | N, | |
73fba5f4 | 3369 | /* 0x10 - 0x17 */ |
d67fc27a | 3370 | I6ALU(Lock, em_adc), |
1cd196ea AK |
3371 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
3372 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 3373 | /* 0x18 - 0x1F */ |
d67fc27a | 3374 | I6ALU(Lock, em_sbb), |
1cd196ea AK |
3375 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
3376 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 3377 | /* 0x20 - 0x27 */ |
d5ae7ce8 | 3378 | I6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 3379 | /* 0x28 - 0x2F */ |
d67fc27a | 3380 | I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3381 | /* 0x30 - 0x37 */ |
d67fc27a | 3382 | I6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3383 | /* 0x38 - 0x3F */ |
d67fc27a | 3384 | I6ALU(0, em_cmp), N, N, |
73fba5f4 AK |
3385 | /* 0x40 - 0x4F */ |
3386 | X16(D(DstReg)), | |
3387 | /* 0x50 - 0x57 */ | |
63540382 | 3388 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3389 | /* 0x58 - 0x5F */ |
c54fe504 | 3390 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3391 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3392 | I(ImplicitOps | Stack | No64, em_pusha), |
3393 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3394 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3395 | N, N, N, N, | |
3396 | /* 0x68 - 0x6F */ | |
d46164db AK |
3397 | I(SrcImm | Mov | Stack, em_push), |
3398 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3399 | I(SrcImmByte | Mov | Stack, em_push), |
3400 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
2b5e97e1 TY |
3401 | I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */ |
3402 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
3403 | /* 0x70 - 0x7F */ |
3404 | X16(D(SrcImmByte)), | |
3405 | /* 0x80 - 0x87 */ | |
3406 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
3407 | G(DstMem | SrcImm | ModRM | Group, group1), | |
3408 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
3409 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
9f21ca59 | 3410 | I2bv(DstMem | SrcReg | ModRM, em_test), |
d5ae7ce8 | 3411 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 3412 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 3413 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 3414 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 3415 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
3416 | D(ModRM | SrcMem | NoAccess | DstReg), |
3417 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3418 | G(0, group1A), | |
73fba5f4 | 3419 | /* 0x90 - 0x97 */ |
bf608f88 | 3420 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3421 | /* 0x98 - 0x9F */ |
61429142 | 3422 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3423 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 TY |
3424 | II(ImplicitOps | Stack, em_pushf, pushf), |
3425 | II(ImplicitOps | Stack, em_popf, popf), N, N, | |
73fba5f4 | 3426 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 3427 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 3428 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 3429 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
d67fc27a | 3430 | I2bv(SrcSI | DstDI | String, em_cmp), |
73fba5f4 | 3431 | /* 0xA8 - 0xAF */ |
9f21ca59 | 3432 | I2bv(DstAcc | SrcImm, em_test), |
b9eac5f4 AK |
3433 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3434 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
d67fc27a | 3435 | I2bv(SrcAcc | DstDI | String, em_cmp), |
73fba5f4 | 3436 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3437 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3438 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 3439 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3440 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 3441 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 | 3442 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3443 | I(ImplicitOps | Stack, em_ret), |
d4b4325f AK |
3444 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
3445 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 3446 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3447 | /* 0xC8 - 0xCF */ |
db5b0762 | 3448 | N, N, N, I(ImplicitOps | Stack, em_ret_far), |
3c6e276f | 3449 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3450 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3451 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 3452 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
3453 | N, N, N, N, |
3454 | /* 0xD8 - 0xDF */ | |
3455 | N, N, N, N, N, N, N, N, | |
3456 | /* 0xE0 - 0xE7 */ | |
d06e03ad TY |
3457 | X3(I(SrcImmByte, em_loop)), |
3458 | I(SrcImmByte, em_jcxz), | |
d7841a4b TY |
3459 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
3460 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 3461 | /* 0xE8 - 0xEF */ |
d4ddafcd | 3462 | I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), |
db5b0762 | 3463 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
d7841a4b TY |
3464 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
3465 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 3466 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3467 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3468 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3469 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3470 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3471 | D(ImplicitOps), D(ImplicitOps), |
3472 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3473 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3474 | }; | |
3475 | ||
3476 | static struct opcode twobyte_table[256] = { | |
3477 | /* 0x00 - 0x0F */ | |
dee6bb70 | 3478 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3479 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3480 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3481 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3482 | N, D(ImplicitOps | ModRM), N, N, |
3483 | /* 0x10 - 0x1F */ | |
3484 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
3485 | /* 0x20 - 0x2F */ | |
cfec82cb | 3486 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3487 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
bc00f8d2 TY |
3488 | IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), |
3489 | IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), | |
73fba5f4 AK |
3490 | N, N, N, N, |
3491 | N, N, N, N, N, N, N, N, | |
3492 | /* 0x30 - 0x3F */ | |
e1e210b0 | 3493 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 3494 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 3495 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 3496 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
db5b0762 TY |
3497 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3498 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3499 | N, N, |
73fba5f4 AK |
3500 | N, N, N, N, N, N, N, N, |
3501 | /* 0x40 - 0x4F */ | |
3502 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3503 | /* 0x50 - 0x5F */ | |
3504 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3505 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3506 | N, N, N, N, |
3507 | N, N, N, N, | |
3508 | N, N, N, N, | |
3509 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3510 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3511 | N, N, N, N, |
3512 | N, N, N, N, | |
3513 | N, N, N, N, | |
3514 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
3515 | /* 0x80 - 0x8F */ |
3516 | X16(D(SrcImm)), | |
3517 | /* 0x90 - 0x9F */ | |
ee45b58e | 3518 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 3519 | /* 0xA0 - 0xA7 */ |
1cd196ea | 3520 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
ce7faab2 | 3521 | DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt), |
73fba5f4 AK |
3522 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3523 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
3524 | /* 0xA8 - 0xAF */ | |
1cd196ea | 3525 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 3526 | DI(ImplicitOps, rsm), |
ce7faab2 | 3527 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
73fba5f4 AK |
3528 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3529 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 3530 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 3531 | /* 0xB0 - 0xB7 */ |
e940b5c2 | 3532 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
d4b4325f | 3533 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
ce7faab2 | 3534 | I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
3535 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
3536 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 3537 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
3538 | /* 0xB8 - 0xBF */ |
3539 | N, N, | |
ce7faab2 TY |
3540 | G(BitOp, group8), |
3541 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), | |
ff227392 | 3542 | I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr), |
2adb5ad9 | 3543 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 | 3544 | /* 0xC0 - 0xCF */ |
739ae406 | 3545 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 3546 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
3547 | N, N, N, GD(0, &group9), |
3548 | N, N, N, N, N, N, N, N, | |
3549 | /* 0xD0 - 0xDF */ | |
3550 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3551 | /* 0xE0 - 0xEF */ | |
3552 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3553 | /* 0xF0 - 0xFF */ | |
3554 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
3555 | }; | |
3556 | ||
3557 | #undef D | |
3558 | #undef N | |
3559 | #undef G | |
3560 | #undef GD | |
3561 | #undef I | |
aa97bb48 | 3562 | #undef GP |
01de8b09 | 3563 | #undef EXT |
73fba5f4 | 3564 | |
8d8f4e9f | 3565 | #undef D2bv |
f6511935 | 3566 | #undef D2bvIP |
8d8f4e9f | 3567 | #undef I2bv |
d7841a4b | 3568 | #undef I2bvIP |
d67fc27a | 3569 | #undef I6ALU |
8d8f4e9f | 3570 | |
9dac77fa | 3571 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
3572 | { |
3573 | unsigned size; | |
3574 | ||
9dac77fa | 3575 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
3576 | if (size == 8) |
3577 | size = 4; | |
3578 | return size; | |
3579 | } | |
3580 | ||
3581 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3582 | unsigned size, bool sign_extension) | |
3583 | { | |
39f21ee5 AK |
3584 | int rc = X86EMUL_CONTINUE; |
3585 | ||
3586 | op->type = OP_IMM; | |
3587 | op->bytes = size; | |
9dac77fa | 3588 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
3589 | /* NB. Immediates are sign-extended as necessary. */ |
3590 | switch (op->bytes) { | |
3591 | case 1: | |
e85a1085 | 3592 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
3593 | break; |
3594 | case 2: | |
e85a1085 | 3595 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
3596 | break; |
3597 | case 4: | |
e85a1085 | 3598 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 AK |
3599 | break; |
3600 | } | |
3601 | if (!sign_extension) { | |
3602 | switch (op->bytes) { | |
3603 | case 1: | |
3604 | op->val &= 0xff; | |
3605 | break; | |
3606 | case 2: | |
3607 | op->val &= 0xffff; | |
3608 | break; | |
3609 | case 4: | |
3610 | op->val &= 0xffffffff; | |
3611 | break; | |
3612 | } | |
3613 | } | |
3614 | done: | |
3615 | return rc; | |
3616 | } | |
3617 | ||
a9945549 AK |
3618 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
3619 | unsigned d) | |
3620 | { | |
3621 | int rc = X86EMUL_CONTINUE; | |
3622 | ||
3623 | switch (d) { | |
3624 | case OpReg: | |
2adb5ad9 | 3625 | decode_register_operand(ctxt, op); |
a9945549 AK |
3626 | break; |
3627 | case OpImmUByte: | |
608aabe3 | 3628 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
3629 | break; |
3630 | case OpMem: | |
41ddf978 | 3631 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
3632 | mem_common: |
3633 | *op = ctxt->memop; | |
3634 | ctxt->memopp = op; | |
3635 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
3636 | fetch_bit_operand(ctxt); |
3637 | op->orig_val = op->val; | |
3638 | break; | |
41ddf978 AK |
3639 | case OpMem64: |
3640 | ctxt->memop.bytes = 8; | |
3641 | goto mem_common; | |
a9945549 AK |
3642 | case OpAcc: |
3643 | op->type = OP_REG; | |
3644 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3645 | op->addr.reg = &ctxt->regs[VCPU_REGS_RAX]; | |
3646 | fetch_register_operand(op); | |
3647 | op->orig_val = op->val; | |
3648 | break; | |
3649 | case OpDI: | |
3650 | op->type = OP_MEM; | |
3651 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3652 | op->addr.mem.ea = | |
3653 | register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]); | |
3654 | op->addr.mem.seg = VCPU_SREG_ES; | |
3655 | op->val = 0; | |
3656 | break; | |
3657 | case OpDX: | |
3658 | op->type = OP_REG; | |
3659 | op->bytes = 2; | |
3660 | op->addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
3661 | fetch_register_operand(op); | |
3662 | break; | |
4dd6a57d AK |
3663 | case OpCL: |
3664 | op->bytes = 1; | |
3665 | op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff; | |
3666 | break; | |
3667 | case OpImmByte: | |
3668 | rc = decode_imm(ctxt, op, 1, true); | |
3669 | break; | |
3670 | case OpOne: | |
3671 | op->bytes = 1; | |
3672 | op->val = 1; | |
3673 | break; | |
3674 | case OpImm: | |
3675 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
3676 | break; | |
28867cee AK |
3677 | case OpMem8: |
3678 | ctxt->memop.bytes = 1; | |
3679 | goto mem_common; | |
0fe59128 AK |
3680 | case OpMem16: |
3681 | ctxt->memop.bytes = 2; | |
3682 | goto mem_common; | |
3683 | case OpMem32: | |
3684 | ctxt->memop.bytes = 4; | |
3685 | goto mem_common; | |
3686 | case OpImmU16: | |
3687 | rc = decode_imm(ctxt, op, 2, false); | |
3688 | break; | |
3689 | case OpImmU: | |
3690 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
3691 | break; | |
3692 | case OpSI: | |
3693 | op->type = OP_MEM; | |
3694 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3695 | op->addr.mem.ea = | |
3696 | register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]); | |
3697 | op->addr.mem.seg = seg_override(ctxt); | |
3698 | op->val = 0; | |
3699 | break; | |
3700 | case OpImmFAddr: | |
3701 | op->type = OP_IMM; | |
3702 | op->addr.mem.ea = ctxt->_eip; | |
3703 | op->bytes = ctxt->op_bytes + 2; | |
3704 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
3705 | break; | |
3706 | case OpMemFAddr: | |
3707 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
3708 | goto mem_common; | |
c191a7a0 AK |
3709 | case OpES: |
3710 | op->val = VCPU_SREG_ES; | |
3711 | break; | |
3712 | case OpCS: | |
3713 | op->val = VCPU_SREG_CS; | |
3714 | break; | |
3715 | case OpSS: | |
3716 | op->val = VCPU_SREG_SS; | |
3717 | break; | |
3718 | case OpDS: | |
3719 | op->val = VCPU_SREG_DS; | |
3720 | break; | |
3721 | case OpFS: | |
3722 | op->val = VCPU_SREG_FS; | |
3723 | break; | |
3724 | case OpGS: | |
3725 | op->val = VCPU_SREG_GS; | |
3726 | break; | |
a9945549 AK |
3727 | case OpImplicit: |
3728 | /* Special instructions do their own operand decoding. */ | |
3729 | default: | |
3730 | op->type = OP_NONE; /* Disable writeback. */ | |
3731 | break; | |
3732 | } | |
3733 | ||
3734 | done: | |
3735 | return rc; | |
3736 | } | |
3737 | ||
ef5d75cc | 3738 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 3739 | { |
dde7e6d1 AK |
3740 | int rc = X86EMUL_CONTINUE; |
3741 | int mode = ctxt->mode; | |
46561646 | 3742 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 3743 | bool op_prefix = false; |
46561646 | 3744 | struct opcode opcode; |
dde7e6d1 | 3745 | |
f09ed83e AK |
3746 | ctxt->memop.type = OP_NONE; |
3747 | ctxt->memopp = NULL; | |
9dac77fa AK |
3748 | ctxt->_eip = ctxt->eip; |
3749 | ctxt->fetch.start = ctxt->_eip; | |
3750 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 3751 | if (insn_len > 0) |
9dac77fa | 3752 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
3753 | |
3754 | switch (mode) { | |
3755 | case X86EMUL_MODE_REAL: | |
3756 | case X86EMUL_MODE_VM86: | |
3757 | case X86EMUL_MODE_PROT16: | |
3758 | def_op_bytes = def_ad_bytes = 2; | |
3759 | break; | |
3760 | case X86EMUL_MODE_PROT32: | |
3761 | def_op_bytes = def_ad_bytes = 4; | |
3762 | break; | |
3763 | #ifdef CONFIG_X86_64 | |
3764 | case X86EMUL_MODE_PROT64: | |
3765 | def_op_bytes = 4; | |
3766 | def_ad_bytes = 8; | |
3767 | break; | |
3768 | #endif | |
3769 | default: | |
1d2887e2 | 3770 | return EMULATION_FAILED; |
dde7e6d1 AK |
3771 | } |
3772 | ||
9dac77fa AK |
3773 | ctxt->op_bytes = def_op_bytes; |
3774 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
3775 | |
3776 | /* Legacy prefixes. */ | |
3777 | for (;;) { | |
e85a1085 | 3778 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 3779 | case 0x66: /* operand-size override */ |
0d7cdee8 | 3780 | op_prefix = true; |
dde7e6d1 | 3781 | /* switch between 2/4 bytes */ |
9dac77fa | 3782 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
3783 | break; |
3784 | case 0x67: /* address-size override */ | |
3785 | if (mode == X86EMUL_MODE_PROT64) | |
3786 | /* switch between 4/8 bytes */ | |
9dac77fa | 3787 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
3788 | else |
3789 | /* switch between 2/4 bytes */ | |
9dac77fa | 3790 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
3791 | break; |
3792 | case 0x26: /* ES override */ | |
3793 | case 0x2e: /* CS override */ | |
3794 | case 0x36: /* SS override */ | |
3795 | case 0x3e: /* DS override */ | |
9dac77fa | 3796 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
3797 | break; |
3798 | case 0x64: /* FS override */ | |
3799 | case 0x65: /* GS override */ | |
9dac77fa | 3800 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
3801 | break; |
3802 | case 0x40 ... 0x4f: /* REX */ | |
3803 | if (mode != X86EMUL_MODE_PROT64) | |
3804 | goto done_prefixes; | |
9dac77fa | 3805 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
3806 | continue; |
3807 | case 0xf0: /* LOCK */ | |
9dac77fa | 3808 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
3809 | break; |
3810 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 3811 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 3812 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
3813 | break; |
3814 | default: | |
3815 | goto done_prefixes; | |
3816 | } | |
3817 | ||
3818 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
3819 | ||
9dac77fa | 3820 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
3821 | } |
3822 | ||
3823 | done_prefixes: | |
3824 | ||
3825 | /* REX prefix. */ | |
9dac77fa AK |
3826 | if (ctxt->rex_prefix & 8) |
3827 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
3828 | |
3829 | /* Opcode byte(s). */ | |
9dac77fa | 3830 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 3831 | /* Two-byte opcode? */ |
9dac77fa AK |
3832 | if (ctxt->b == 0x0f) { |
3833 | ctxt->twobyte = 1; | |
e85a1085 | 3834 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 3835 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 3836 | } |
9dac77fa | 3837 | ctxt->d = opcode.flags; |
dde7e6d1 | 3838 | |
9dac77fa AK |
3839 | while (ctxt->d & GroupMask) { |
3840 | switch (ctxt->d & GroupMask) { | |
46561646 | 3841 | case Group: |
e85a1085 | 3842 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3843 | --ctxt->_eip; |
3844 | goffset = (ctxt->modrm >> 3) & 7; | |
46561646 AK |
3845 | opcode = opcode.u.group[goffset]; |
3846 | break; | |
3847 | case GroupDual: | |
e85a1085 | 3848 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3849 | --ctxt->_eip; |
3850 | goffset = (ctxt->modrm >> 3) & 7; | |
3851 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
3852 | opcode = opcode.u.gdual->mod3[goffset]; |
3853 | else | |
3854 | opcode = opcode.u.gdual->mod012[goffset]; | |
3855 | break; | |
3856 | case RMExt: | |
9dac77fa | 3857 | goffset = ctxt->modrm & 7; |
01de8b09 | 3858 | opcode = opcode.u.group[goffset]; |
46561646 AK |
3859 | break; |
3860 | case Prefix: | |
9dac77fa | 3861 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 3862 | return EMULATION_FAILED; |
9dac77fa | 3863 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
3864 | switch (simd_prefix) { |
3865 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
3866 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
3867 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
3868 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
3869 | } | |
3870 | break; | |
3871 | default: | |
1d2887e2 | 3872 | return EMULATION_FAILED; |
0d7cdee8 | 3873 | } |
46561646 | 3874 | |
b1ea50b2 | 3875 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 3876 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
3877 | } |
3878 | ||
9dac77fa AK |
3879 | ctxt->execute = opcode.u.execute; |
3880 | ctxt->check_perm = opcode.check_perm; | |
3881 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
3882 | |
3883 | /* Unrecognised? */ | |
9dac77fa | 3884 | if (ctxt->d == 0 || (ctxt->d & Undefined)) |
1d2887e2 | 3885 | return EMULATION_FAILED; |
dde7e6d1 | 3886 | |
9dac77fa | 3887 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 3888 | return EMULATION_FAILED; |
d867162c | 3889 | |
9dac77fa AK |
3890 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
3891 | ctxt->op_bytes = 8; | |
dde7e6d1 | 3892 | |
9dac77fa | 3893 | if (ctxt->d & Op3264) { |
7f9b4b75 | 3894 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 3895 | ctxt->op_bytes = 8; |
7f9b4b75 | 3896 | else |
9dac77fa | 3897 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
3898 | } |
3899 | ||
9dac77fa AK |
3900 | if (ctxt->d & Sse) |
3901 | ctxt->op_bytes = 16; | |
1253791d | 3902 | |
dde7e6d1 | 3903 | /* ModRM and SIB bytes. */ |
9dac77fa | 3904 | if (ctxt->d & ModRM) { |
f09ed83e | 3905 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
3906 | if (!ctxt->has_seg_override) |
3907 | set_seg_override(ctxt, ctxt->modrm_seg); | |
3908 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 3909 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
3910 | if (rc != X86EMUL_CONTINUE) |
3911 | goto done; | |
3912 | ||
9dac77fa AK |
3913 | if (!ctxt->has_seg_override) |
3914 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 3915 | |
f09ed83e | 3916 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 3917 | |
f09ed83e AK |
3918 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
3919 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 3920 | |
dde7e6d1 AK |
3921 | /* |
3922 | * Decode and fetch the source operand: register, memory | |
3923 | * or immediate. | |
3924 | */ | |
0fe59128 | 3925 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
3926 | if (rc != X86EMUL_CONTINUE) |
3927 | goto done; | |
3928 | ||
dde7e6d1 AK |
3929 | /* |
3930 | * Decode and fetch the second source operand: register, memory | |
3931 | * or immediate. | |
3932 | */ | |
4dd6a57d | 3933 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
3934 | if (rc != X86EMUL_CONTINUE) |
3935 | goto done; | |
3936 | ||
dde7e6d1 | 3937 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 3938 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
3939 | |
3940 | done: | |
f09ed83e AK |
3941 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
3942 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 3943 | |
1d2887e2 | 3944 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
3945 | } |
3946 | ||
1cb3f3ae XG |
3947 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
3948 | { | |
3949 | return ctxt->d & PageTable; | |
3950 | } | |
3951 | ||
3e2f65d5 GN |
3952 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
3953 | { | |
3e2f65d5 GN |
3954 | /* The second termination condition only applies for REPE |
3955 | * and REPNE. Test if the repeat string operation prefix is | |
3956 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3957 | * corresponding termination condition according to: | |
3958 | * - if REPE/REPZ and ZF = 0 then done | |
3959 | * - if REPNE/REPNZ and ZF = 1 then done | |
3960 | */ | |
9dac77fa AK |
3961 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
3962 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
3963 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 3964 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 3965 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
3966 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
3967 | return true; | |
3968 | ||
3969 | return false; | |
3970 | } | |
3971 | ||
7b105ca2 | 3972 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 3973 | { |
9aabc88f | 3974 | struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 3975 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 3976 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 3977 | |
9dac77fa | 3978 | ctxt->mem_read.pos = 0; |
310b5d30 | 3979 | |
9dac77fa | 3980 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { |
35d3d4a1 | 3981 | rc = emulate_ud(ctxt); |
1161624f GN |
3982 | goto done; |
3983 | } | |
3984 | ||
d380a5e4 | 3985 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 3986 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 3987 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
3988 | goto done; |
3989 | } | |
3990 | ||
9dac77fa | 3991 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 3992 | rc = emulate_ud(ctxt); |
081bca0e AK |
3993 | goto done; |
3994 | } | |
3995 | ||
9dac77fa | 3996 | if ((ctxt->d & Sse) |
717746e3 AK |
3997 | && ((ops->get_cr(ctxt, 0) & X86_CR0_EM) |
3998 | || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
3999 | rc = emulate_ud(ctxt); |
4000 | goto done; | |
4001 | } | |
4002 | ||
9dac77fa | 4003 | if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
4004 | rc = emulate_nm(ctxt); |
4005 | goto done; | |
4006 | } | |
4007 | ||
9dac77fa AK |
4008 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4009 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4010 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
4011 | if (rc != X86EMUL_CONTINUE) |
4012 | goto done; | |
4013 | } | |
4014 | ||
e92805ac | 4015 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 4016 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 4017 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
4018 | goto done; |
4019 | } | |
4020 | ||
8ea7d6ae | 4021 | /* Instruction can only be executed in protected mode */ |
9dac77fa | 4022 | if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { |
8ea7d6ae JR |
4023 | rc = emulate_ud(ctxt); |
4024 | goto done; | |
4025 | } | |
4026 | ||
d09beabd | 4027 | /* Do instruction specific permission checks */ |
9dac77fa AK |
4028 | if (ctxt->check_perm) { |
4029 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
4030 | if (rc != X86EMUL_CONTINUE) |
4031 | goto done; | |
4032 | } | |
4033 | ||
9dac77fa AK |
4034 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4035 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4036 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
4037 | if (rc != X86EMUL_CONTINUE) |
4038 | goto done; | |
4039 | } | |
4040 | ||
9dac77fa | 4041 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 4042 | /* All REP prefixes have the same first termination condition */ |
9dac77fa AK |
4043 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) { |
4044 | ctxt->eip = ctxt->_eip; | |
b9fa9d6b AK |
4045 | goto done; |
4046 | } | |
b9fa9d6b AK |
4047 | } |
4048 | ||
9dac77fa AK |
4049 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4050 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4051 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4052 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4053 | goto done; |
9dac77fa | 4054 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4055 | } |
4056 | ||
9dac77fa AK |
4057 | if (ctxt->src2.type == OP_MEM) { |
4058 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4059 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4060 | if (rc != X86EMUL_CONTINUE) |
4061 | goto done; | |
4062 | } | |
4063 | ||
9dac77fa | 4064 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4065 | goto special_insn; |
4066 | ||
4067 | ||
9dac77fa | 4068 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4069 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4070 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4071 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
4072 | if (rc != X86EMUL_CONTINUE) |
4073 | goto done; | |
038e51de | 4074 | } |
9dac77fa | 4075 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 4076 | |
018a98db AK |
4077 | special_insn: |
4078 | ||
9dac77fa AK |
4079 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4080 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4081 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4082 | if (rc != X86EMUL_CONTINUE) |
4083 | goto done; | |
4084 | } | |
4085 | ||
9dac77fa AK |
4086 | if (ctxt->execute) { |
4087 | rc = ctxt->execute(ctxt); | |
ef65c889 AK |
4088 | if (rc != X86EMUL_CONTINUE) |
4089 | goto done; | |
4090 | goto writeback; | |
4091 | } | |
4092 | ||
9dac77fa | 4093 | if (ctxt->twobyte) |
6aa8b732 AK |
4094 | goto twobyte_insn; |
4095 | ||
9dac77fa | 4096 | switch (ctxt->b) { |
33615aa9 | 4097 | case 0x40 ... 0x47: /* inc r16/r32 */ |
d1eef45d | 4098 | emulate_1op(ctxt, "inc"); |
33615aa9 AK |
4099 | break; |
4100 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
d1eef45d | 4101 | emulate_1op(ctxt, "dec"); |
33615aa9 | 4102 | break; |
6aa8b732 | 4103 | case 0x63: /* movsxd */ |
8b4caf66 | 4104 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 4105 | goto cannot_emulate; |
9dac77fa | 4106 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 4107 | break; |
b2833e3c | 4108 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
4109 | if (test_cc(ctxt->b, ctxt->eflags)) |
4110 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4111 | break; |
7e0b54b1 | 4112 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 4113 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 4114 | break; |
3d9e77df | 4115 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
9dac77fa | 4116 | if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX]) |
34698d8c | 4117 | break; |
e4f973ae TY |
4118 | rc = em_xchg(ctxt); |
4119 | break; | |
e8b6fa70 | 4120 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
4121 | switch (ctxt->op_bytes) { |
4122 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
4123 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
4124 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
4125 | } |
4126 | break; | |
018a98db | 4127 | case 0xc0 ... 0xc1: |
51187683 | 4128 | rc = em_grp2(ctxt); |
018a98db | 4129 | break; |
6e154e56 | 4130 | case 0xcc: /* int3 */ |
5c5df76b TY |
4131 | rc = emulate_int(ctxt, 3); |
4132 | break; | |
6e154e56 | 4133 | case 0xcd: /* int n */ |
9dac77fa | 4134 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
4135 | break; |
4136 | case 0xce: /* into */ | |
5c5df76b TY |
4137 | if (ctxt->eflags & EFLG_OF) |
4138 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 4139 | break; |
018a98db | 4140 | case 0xd0 ... 0xd1: /* Grp2 */ |
51187683 | 4141 | rc = em_grp2(ctxt); |
018a98db AK |
4142 | break; |
4143 | case 0xd2 ... 0xd3: /* Grp2 */ | |
9dac77fa | 4144 | ctxt->src.val = ctxt->regs[VCPU_REGS_RCX]; |
51187683 | 4145 | rc = em_grp2(ctxt); |
018a98db | 4146 | break; |
1a52e051 | 4147 | case 0xe9: /* jmp rel */ |
db5b0762 | 4148 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
4149 | jmp_rel(ctxt, ctxt->src.val); |
4150 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 4151 | break; |
111de5d6 | 4152 | case 0xf4: /* hlt */ |
6c3287f7 | 4153 | ctxt->ops->halt(ctxt); |
19fdfa0d | 4154 | break; |
111de5d6 AK |
4155 | case 0xf5: /* cmc */ |
4156 | /* complement carry flag from eflags reg */ | |
4157 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
4158 | break; |
4159 | case 0xf8: /* clc */ | |
4160 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 4161 | break; |
8744aa9a MG |
4162 | case 0xf9: /* stc */ |
4163 | ctxt->eflags |= EFLG_CF; | |
4164 | break; | |
fb4616f4 MG |
4165 | case 0xfc: /* cld */ |
4166 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
4167 | break; |
4168 | case 0xfd: /* std */ | |
4169 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 4170 | break; |
91269b8f AK |
4171 | default: |
4172 | goto cannot_emulate; | |
6aa8b732 | 4173 | } |
018a98db | 4174 | |
7d9ddaed AK |
4175 | if (rc != X86EMUL_CONTINUE) |
4176 | goto done; | |
4177 | ||
018a98db | 4178 | writeback: |
adddcecf | 4179 | rc = writeback(ctxt); |
1b30eaa8 | 4180 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
4181 | goto done; |
4182 | ||
5cd21917 GN |
4183 | /* |
4184 | * restore dst type in case the decoding will be reused | |
4185 | * (happens for string instruction ) | |
4186 | */ | |
9dac77fa | 4187 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 4188 | |
9dac77fa AK |
4189 | if ((ctxt->d & SrcMask) == SrcSI) |
4190 | string_addr_inc(ctxt, seg_override(ctxt), | |
4191 | VCPU_REGS_RSI, &ctxt->src); | |
a682e354 | 4192 | |
9dac77fa | 4193 | if ((ctxt->d & DstMask) == DstDI) |
90de84f5 | 4194 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
9dac77fa | 4195 | &ctxt->dst); |
d9271123 | 4196 | |
9dac77fa AK |
4197 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
4198 | struct read_cache *r = &ctxt->io_read; | |
4199 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); | |
3e2f65d5 | 4200 | |
d2ddd1c4 GN |
4201 | if (!string_insn_completed(ctxt)) { |
4202 | /* | |
4203 | * Re-enter guest when pio read ahead buffer is empty | |
4204 | * or, if it is not used, after each 1024 iteration. | |
4205 | */ | |
9dac77fa | 4206 | if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) && |
d2ddd1c4 GN |
4207 | (r->end == 0 || r->end != r->pos)) { |
4208 | /* | |
4209 | * Reset read cache. Usually happens before | |
4210 | * decode, but since instruction is restarted | |
4211 | * we have to do it here. | |
4212 | */ | |
9dac77fa | 4213 | ctxt->mem_read.end = 0; |
d2ddd1c4 GN |
4214 | return EMULATION_RESTART; |
4215 | } | |
4216 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 4217 | } |
5cd21917 | 4218 | } |
d2ddd1c4 | 4219 | |
9dac77fa | 4220 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4221 | |
4222 | done: | |
da9cb575 AK |
4223 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4224 | ctxt->have_exception = true; | |
775fde86 JR |
4225 | if (rc == X86EMUL_INTERCEPTED) |
4226 | return EMULATION_INTERCEPTED; | |
4227 | ||
d2ddd1c4 | 4228 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4229 | |
4230 | twobyte_insn: | |
9dac77fa | 4231 | switch (ctxt->b) { |
018a98db | 4232 | case 0x09: /* wbinvd */ |
cfb22375 | 4233 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4234 | break; |
4235 | case 0x08: /* invd */ | |
018a98db AK |
4236 | case 0x0d: /* GrpP (prefetch) */ |
4237 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
4238 | break; |
4239 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4240 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4241 | break; |
6aa8b732 | 4242 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4243 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4244 | break; |
6aa8b732 | 4245 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4246 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4247 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4248 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4249 | break; |
b2833e3c | 4250 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4251 | if (test_cc(ctxt->b, ctxt->eflags)) |
4252 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4253 | break; |
ee45b58e | 4254 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4255 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4256 | break; |
9bf8ea42 GT |
4257 | case 0xa4: /* shld imm8, r, r/m */ |
4258 | case 0xa5: /* shld cl, r, r/m */ | |
761441b9 | 4259 | emulate_2op_cl(ctxt, "shld"); |
9bf8ea42 | 4260 | break; |
9bf8ea42 GT |
4261 | case 0xac: /* shrd imm8, r, r/m */ |
4262 | case 0xad: /* shrd cl, r, r/m */ | |
761441b9 | 4263 | emulate_2op_cl(ctxt, "shrd"); |
9bf8ea42 | 4264 | break; |
2a7c5b8b GC |
4265 | case 0xae: /* clflush */ |
4266 | break; | |
6aa8b732 | 4267 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa AK |
4268 | ctxt->dst.bytes = ctxt->op_bytes; |
4269 | ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val | |
4270 | : (u16) ctxt->src.val; | |
6aa8b732 | 4271 | break; |
6aa8b732 | 4272 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa AK |
4273 | ctxt->dst.bytes = ctxt->op_bytes; |
4274 | ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val : | |
4275 | (s16) ctxt->src.val; | |
6aa8b732 | 4276 | break; |
92f738a5 | 4277 | case 0xc0 ... 0xc1: /* xadd */ |
a31b9cea | 4278 | emulate_2op_SrcV(ctxt, "add"); |
92f738a5 | 4279 | /* Write back the register source. */ |
9dac77fa AK |
4280 | ctxt->src.val = ctxt->dst.orig_val; |
4281 | write_register_operand(&ctxt->src); | |
92f738a5 | 4282 | break; |
a012e65a | 4283 | case 0xc3: /* movnti */ |
9dac77fa AK |
4284 | ctxt->dst.bytes = ctxt->op_bytes; |
4285 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4286 | (u64) ctxt->src.val; | |
a012e65a | 4287 | break; |
91269b8f AK |
4288 | default: |
4289 | goto cannot_emulate; | |
6aa8b732 | 4290 | } |
7d9ddaed AK |
4291 | |
4292 | if (rc != X86EMUL_CONTINUE) | |
4293 | goto done; | |
4294 | ||
6aa8b732 AK |
4295 | goto writeback; |
4296 | ||
4297 | cannot_emulate: | |
a0c0ab2f | 4298 | return EMULATION_FAILED; |
6aa8b732 | 4299 | } |