Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
221d059d | 12 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
23 | #ifndef __KERNEL__ | |
24 | #include <stdio.h> | |
25 | #include <stdint.h> | |
26 | #include <public/xen.h> | |
d77c26fc | 27 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 28 | #else |
edf88417 | 29 | #include <linux/kvm_host.h> |
5fdbf976 | 30 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
31 | #define DPRINTF(x...) do {} while (0) |
32 | #endif | |
6aa8b732 | 33 | #include <linux/module.h> |
56e82318 | 34 | #include <asm/kvm_emulate.h> |
6aa8b732 | 35 | |
3eeb3288 | 36 | #include "x86.h" |
38ba30ba | 37 | #include "tss.h" |
e99f0507 | 38 | |
6aa8b732 AK |
39 | /* |
40 | * Opcode effective-address decode tables. | |
41 | * Note that we only emulate instructions that have at least one memory | |
42 | * operand (excluding implicit stack references). We assume that stack | |
43 | * references and instruction fetches will never occur in special memory | |
44 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
45 | * not be handled. | |
46 | */ | |
47 | ||
48 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 49 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 50 | /* Destination operand type. */ |
ab85b12b AK |
51 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
52 | #define DstReg (2<<1) /* Register operand. */ | |
53 | #define DstMem (3<<1) /* Memory operand. */ | |
54 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
55 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
56 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
57 | #define DstMask (7<<1) | |
6aa8b732 | 58 | /* Source operand type. */ |
9c9fddd0 GT |
59 | #define SrcNone (0<<4) /* No source operand. */ |
60 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
61 | #define SrcReg (1<<4) /* Register operand. */ | |
62 | #define SrcMem (2<<4) /* Memory operand. */ | |
63 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
64 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
65 | #define SrcImm (5<<4) /* Immediate operand. */ | |
66 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 67 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 68 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 69 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 70 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
71 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
72 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 73 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
341de7e3 | 74 | #define SrcMask (0xf<<4) |
6aa8b732 | 75 | /* Generic ModRM decode. */ |
341de7e3 | 76 | #define ModRM (1<<8) |
6aa8b732 | 77 | /* Destination is only written; never read. */ |
341de7e3 GN |
78 | #define Mov (1<<9) |
79 | #define BitOp (1<<10) | |
80 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
81 | #define String (1<<12) /* String instruction (rep capable) */ |
82 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
83 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
84 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
d8769fed | 85 | /* Misc flags */ |
5a506b12 | 86 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 87 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 88 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 89 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 90 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 91 | #define No64 (1<<28) |
0dc8d10f GT |
92 | /* Source 2 operand type */ |
93 | #define Src2None (0<<29) | |
94 | #define Src2CL (1<<29) | |
95 | #define Src2ImmByte (2<<29) | |
96 | #define Src2One (3<<29) | |
97 | #define Src2Mask (7<<29) | |
6aa8b732 | 98 | |
d0e53325 AK |
99 | #define X2(x...) x, x |
100 | #define X3(x...) X2(x), x | |
101 | #define X4(x...) X2(x), X2(x) | |
102 | #define X5(x...) X4(x), x | |
103 | #define X6(x...) X4(x), X2(x) | |
104 | #define X7(x...) X4(x), X3(x) | |
105 | #define X8(x...) X4(x), X4(x) | |
106 | #define X16(x...) X8(x), X8(x) | |
83babbca | 107 | |
d65b1dee AK |
108 | struct opcode { |
109 | u32 flags; | |
120df890 | 110 | union { |
ef65c889 | 111 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
112 | struct opcode *group; |
113 | struct group_dual *gdual; | |
114 | } u; | |
115 | }; | |
116 | ||
117 | struct group_dual { | |
118 | struct opcode mod012[8]; | |
119 | struct opcode mod3[8]; | |
d65b1dee AK |
120 | }; |
121 | ||
6aa8b732 | 122 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
123 | #define EFLG_ID (1<<21) |
124 | #define EFLG_VIP (1<<20) | |
125 | #define EFLG_VIF (1<<19) | |
126 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
127 | #define EFLG_VM (1<<17) |
128 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
129 | #define EFLG_IOPL (3<<12) |
130 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
131 | #define EFLG_OF (1<<11) |
132 | #define EFLG_DF (1<<10) | |
b1d86143 | 133 | #define EFLG_IF (1<<9) |
d4c6a154 | 134 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
135 | #define EFLG_SF (1<<7) |
136 | #define EFLG_ZF (1<<6) | |
137 | #define EFLG_AF (1<<4) | |
138 | #define EFLG_PF (1<<2) | |
139 | #define EFLG_CF (1<<0) | |
140 | ||
62bd430e MG |
141 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
142 | #define EFLG_RESERVED_ONE_MASK 2 | |
143 | ||
6aa8b732 AK |
144 | /* |
145 | * Instruction emulation: | |
146 | * Most instructions are emulated directly via a fragment of inline assembly | |
147 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
148 | * any modified flags. | |
149 | */ | |
150 | ||
05b3e0c2 | 151 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
152 | #define _LO32 "k" /* force 32-bit operand */ |
153 | #define _STK "%%rsp" /* stack pointer */ | |
154 | #elif defined(__i386__) | |
155 | #define _LO32 "" /* force 32-bit operand */ | |
156 | #define _STK "%%esp" /* stack pointer */ | |
157 | #endif | |
158 | ||
159 | /* | |
160 | * These EFLAGS bits are restored from saved value during emulation, and | |
161 | * any changes are written back to the saved value after emulation. | |
162 | */ | |
163 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
164 | ||
165 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
166 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
167 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
168 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
169 | "push %"_tmp"; " \ | |
170 | "push %"_tmp"; " \ | |
171 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
172 | "andl %"_LO32 _tmp",("_STK"); " \ | |
173 | "pushf; " \ | |
174 | "notl %"_LO32 _tmp"; " \ | |
175 | "andl %"_LO32 _tmp",("_STK"); " \ | |
176 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
177 | "pop %"_tmp"; " \ | |
178 | "orl %"_LO32 _tmp",("_STK"); " \ | |
179 | "popf; " \ | |
180 | "pop %"_sav"; " | |
6aa8b732 AK |
181 | |
182 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
183 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
184 | /* _sav |= EFLAGS & _msk; */ \ | |
185 | "pushf; " \ | |
186 | "pop %"_tmp"; " \ | |
187 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
188 | "orl %"_LO32 _tmp",%"_sav"; " | |
189 | ||
dda96d8f AK |
190 | #ifdef CONFIG_X86_64 |
191 | #define ON64(x) x | |
192 | #else | |
193 | #define ON64(x) | |
194 | #endif | |
195 | ||
6b7ad61f AK |
196 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
197 | do { \ | |
198 | __asm__ __volatile__ ( \ | |
199 | _PRE_EFLAGS("0", "4", "2") \ | |
200 | _op _suffix " %"_x"3,%1; " \ | |
201 | _POST_EFLAGS("0", "4", "2") \ | |
202 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
203 | "=&r" (_tmp) \ | |
204 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 205 | } while (0) |
6b7ad61f AK |
206 | |
207 | ||
6aa8b732 AK |
208 | /* Raw emulation: instruction has two explicit operands. */ |
209 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
210 | do { \ |
211 | unsigned long _tmp; \ | |
212 | \ | |
213 | switch ((_dst).bytes) { \ | |
214 | case 2: \ | |
215 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
216 | break; \ | |
217 | case 4: \ | |
218 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
219 | break; \ | |
220 | case 8: \ | |
221 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
222 | break; \ | |
223 | } \ | |
6aa8b732 AK |
224 | } while (0) |
225 | ||
226 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
227 | do { \ | |
6b7ad61f | 228 | unsigned long _tmp; \ |
d77c26fc | 229 | switch ((_dst).bytes) { \ |
6aa8b732 | 230 | case 1: \ |
6b7ad61f | 231 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
232 | break; \ |
233 | default: \ | |
234 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
235 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
236 | break; \ | |
237 | } \ | |
238 | } while (0) | |
239 | ||
240 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
241 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
242 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
243 | "b", "c", "b", "c", "b", "c", "b", "c") | |
244 | ||
245 | /* Source operand is byte, word, long or quad sized. */ | |
246 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
247 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
248 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
249 | ||
250 | /* Source operand is word, long or quad sized. */ | |
251 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
252 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
253 | "w", "r", _LO32, "r", "", "r") | |
254 | ||
d175226a GT |
255 | /* Instruction has three operands and one operand is stored in ECX register */ |
256 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
257 | do { \ | |
258 | unsigned long _tmp; \ | |
259 | _type _clv = (_cl).val; \ | |
260 | _type _srcv = (_src).val; \ | |
261 | _type _dstv = (_dst).val; \ | |
262 | \ | |
263 | __asm__ __volatile__ ( \ | |
264 | _PRE_EFLAGS("0", "5", "2") \ | |
265 | _op _suffix " %4,%1 \n" \ | |
266 | _POST_EFLAGS("0", "5", "2") \ | |
267 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
268 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
269 | ); \ | |
270 | \ | |
271 | (_cl).val = (unsigned long) _clv; \ | |
272 | (_src).val = (unsigned long) _srcv; \ | |
273 | (_dst).val = (unsigned long) _dstv; \ | |
274 | } while (0) | |
275 | ||
276 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
277 | do { \ | |
278 | switch ((_dst).bytes) { \ | |
279 | case 2: \ | |
280 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
281 | "w", unsigned short); \ | |
282 | break; \ | |
283 | case 4: \ | |
284 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
285 | "l", unsigned int); \ | |
286 | break; \ | |
287 | case 8: \ | |
288 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
289 | "q", unsigned long)); \ | |
290 | break; \ | |
291 | } \ | |
292 | } while (0) | |
293 | ||
dda96d8f | 294 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
295 | do { \ |
296 | unsigned long _tmp; \ | |
297 | \ | |
dda96d8f AK |
298 | __asm__ __volatile__ ( \ |
299 | _PRE_EFLAGS("0", "3", "2") \ | |
300 | _op _suffix " %1; " \ | |
301 | _POST_EFLAGS("0", "3", "2") \ | |
302 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
303 | "=&r" (_tmp) \ | |
304 | : "i" (EFLAGS_MASK)); \ | |
305 | } while (0) | |
306 | ||
307 | /* Instruction has only one explicit operand (no source operand). */ | |
308 | #define emulate_1op(_op, _dst, _eflags) \ | |
309 | do { \ | |
d77c26fc | 310 | switch ((_dst).bytes) { \ |
dda96d8f AK |
311 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
312 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
313 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
314 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
315 | } \ |
316 | } while (0) | |
317 | ||
3f9f53b0 MG |
318 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
319 | do { \ | |
320 | unsigned long _tmp; \ | |
321 | \ | |
322 | __asm__ __volatile__ ( \ | |
323 | _PRE_EFLAGS("0", "4", "1") \ | |
324 | _op _suffix " %5; " \ | |
325 | _POST_EFLAGS("0", "4", "1") \ | |
326 | : "=m" (_eflags), "=&r" (_tmp), \ | |
327 | "+a" (_rax), "+d" (_rdx) \ | |
328 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
329 | "a" (_rax), "d" (_rdx)); \ | |
330 | } while (0) | |
331 | ||
332 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ | |
333 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
334 | do { \ | |
335 | switch((_src).bytes) { \ | |
336 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
337 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
338 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
339 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
340 | } \ | |
341 | } while (0) | |
342 | ||
6aa8b732 AK |
343 | /* Fetch next part of the instruction being emulated. */ |
344 | #define insn_fetch(_type, _size, _eip) \ | |
345 | ({ unsigned long _x; \ | |
62266869 | 346 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 347 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
348 | goto done; \ |
349 | (_eip) += (_size); \ | |
350 | (_type)_x; \ | |
351 | }) | |
352 | ||
414e6277 GN |
353 | #define insn_fetch_arr(_arr, _size, _eip) \ |
354 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
355 | if (rc != X86EMUL_CONTINUE) \ | |
356 | goto done; \ | |
357 | (_eip) += (_size); \ | |
358 | }) | |
359 | ||
ddcb2885 HH |
360 | static inline unsigned long ad_mask(struct decode_cache *c) |
361 | { | |
362 | return (1UL << (c->ad_bytes << 3)) - 1; | |
363 | } | |
364 | ||
6aa8b732 | 365 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
366 | static inline unsigned long |
367 | address_mask(struct decode_cache *c, unsigned long reg) | |
368 | { | |
369 | if (c->ad_bytes == sizeof(unsigned long)) | |
370 | return reg; | |
371 | else | |
372 | return reg & ad_mask(c); | |
373 | } | |
374 | ||
375 | static inline unsigned long | |
376 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
377 | { | |
378 | return base + address_mask(c, reg); | |
379 | } | |
380 | ||
7a957275 HH |
381 | static inline void |
382 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
383 | { | |
384 | if (c->ad_bytes == sizeof(unsigned long)) | |
385 | *reg += inc; | |
386 | else | |
387 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
388 | } | |
6aa8b732 | 389 | |
7a957275 HH |
390 | static inline void jmp_rel(struct decode_cache *c, int rel) |
391 | { | |
392 | register_address_increment(c, &c->eip, rel); | |
393 | } | |
098c937b | 394 | |
7a5b56df AK |
395 | static void set_seg_override(struct decode_cache *c, int seg) |
396 | { | |
397 | c->has_seg_override = true; | |
398 | c->seg_override = seg; | |
399 | } | |
400 | ||
79168fd1 GN |
401 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
402 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
403 | { |
404 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
405 | return 0; | |
406 | ||
79168fd1 | 407 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
408 | } |
409 | ||
410 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 411 | struct x86_emulate_ops *ops, |
7a5b56df AK |
412 | struct decode_cache *c) |
413 | { | |
414 | if (!c->has_seg_override) | |
415 | return 0; | |
416 | ||
79168fd1 | 417 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
418 | } |
419 | ||
79168fd1 GN |
420 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
421 | struct x86_emulate_ops *ops) | |
7a5b56df | 422 | { |
79168fd1 | 423 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
424 | } |
425 | ||
79168fd1 GN |
426 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
427 | struct x86_emulate_ops *ops) | |
7a5b56df | 428 | { |
79168fd1 | 429 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
430 | } |
431 | ||
54b8486f GN |
432 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
433 | u32 error, bool valid) | |
434 | { | |
435 | ctxt->exception = vec; | |
436 | ctxt->error_code = error; | |
437 | ctxt->error_code_valid = valid; | |
438 | ctxt->restart = false; | |
439 | } | |
440 | ||
441 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
442 | { | |
443 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
444 | } | |
445 | ||
446 | static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
447 | int err) | |
448 | { | |
449 | ctxt->cr2 = addr; | |
450 | emulate_exception(ctxt, PF_VECTOR, err, true); | |
451 | } | |
452 | ||
453 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
454 | { | |
455 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
456 | } | |
457 | ||
458 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
459 | { | |
460 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
461 | } | |
462 | ||
62266869 AK |
463 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
464 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 465 | unsigned long eip, u8 *dest) |
62266869 AK |
466 | { |
467 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
468 | int rc; | |
2fb53ad8 | 469 | int size, cur_size; |
62266869 | 470 | |
2fb53ad8 AK |
471 | if (eip == fc->end) { |
472 | cur_size = fc->end - fc->start; | |
473 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
474 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
475 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 476 | if (rc != X86EMUL_CONTINUE) |
62266869 | 477 | return rc; |
2fb53ad8 | 478 | fc->end += size; |
62266869 | 479 | } |
2fb53ad8 | 480 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 481 | return X86EMUL_CONTINUE; |
62266869 AK |
482 | } |
483 | ||
484 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
485 | struct x86_emulate_ops *ops, | |
486 | unsigned long eip, void *dest, unsigned size) | |
487 | { | |
3e2815e9 | 488 | int rc; |
62266869 | 489 | |
eb3c79e6 | 490 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 491 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 492 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
493 | while (size--) { |
494 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 495 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
496 | return rc; |
497 | } | |
3e2815e9 | 498 | return X86EMUL_CONTINUE; |
62266869 AK |
499 | } |
500 | ||
1e3c5cb0 RR |
501 | /* |
502 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
503 | * pointer into the block that addresses the relevant register. | |
504 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
505 | */ | |
506 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
507 | int highbyte_regs) | |
6aa8b732 AK |
508 | { |
509 | void *p; | |
510 | ||
511 | p = ®s[modrm_reg]; | |
512 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
513 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
514 | return p; | |
515 | } | |
516 | ||
517 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
518 | struct x86_emulate_ops *ops, | |
1a6440ae | 519 | ulong addr, |
6aa8b732 AK |
520 | u16 *size, unsigned long *address, int op_bytes) |
521 | { | |
522 | int rc; | |
523 | ||
524 | if (op_bytes == 2) | |
525 | op_bytes = 3; | |
526 | *address = 0; | |
1a6440ae | 527 | rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL); |
1b30eaa8 | 528 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 529 | return rc; |
1a6440ae | 530 | rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL); |
6aa8b732 AK |
531 | return rc; |
532 | } | |
533 | ||
bbe9abbd NK |
534 | static int test_cc(unsigned int condition, unsigned int flags) |
535 | { | |
536 | int rc = 0; | |
537 | ||
538 | switch ((condition & 15) >> 1) { | |
539 | case 0: /* o */ | |
540 | rc |= (flags & EFLG_OF); | |
541 | break; | |
542 | case 1: /* b/c/nae */ | |
543 | rc |= (flags & EFLG_CF); | |
544 | break; | |
545 | case 2: /* z/e */ | |
546 | rc |= (flags & EFLG_ZF); | |
547 | break; | |
548 | case 3: /* be/na */ | |
549 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
550 | break; | |
551 | case 4: /* s */ | |
552 | rc |= (flags & EFLG_SF); | |
553 | break; | |
554 | case 5: /* p/pe */ | |
555 | rc |= (flags & EFLG_PF); | |
556 | break; | |
557 | case 7: /* le/ng */ | |
558 | rc |= (flags & EFLG_ZF); | |
559 | /* fall through */ | |
560 | case 6: /* l/nge */ | |
561 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
562 | break; | |
563 | } | |
564 | ||
565 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
566 | return (!!rc ^ (condition & 1)); | |
567 | } | |
568 | ||
91ff3cb4 AK |
569 | static void fetch_register_operand(struct operand *op) |
570 | { | |
571 | switch (op->bytes) { | |
572 | case 1: | |
573 | op->val = *(u8 *)op->addr.reg; | |
574 | break; | |
575 | case 2: | |
576 | op->val = *(u16 *)op->addr.reg; | |
577 | break; | |
578 | case 4: | |
579 | op->val = *(u32 *)op->addr.reg; | |
580 | break; | |
581 | case 8: | |
582 | op->val = *(u64 *)op->addr.reg; | |
583 | break; | |
584 | } | |
585 | } | |
586 | ||
3c118e24 AK |
587 | static void decode_register_operand(struct operand *op, |
588 | struct decode_cache *c, | |
3c118e24 AK |
589 | int inhibit_bytereg) |
590 | { | |
33615aa9 | 591 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 592 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
593 | |
594 | if (!(c->d & ModRM)) | |
595 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
596 | op->type = OP_REG; |
597 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 598 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
599 | op->bytes = 1; |
600 | } else { | |
1a6440ae | 601 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 602 | op->bytes = c->op_bytes; |
3c118e24 | 603 | } |
91ff3cb4 | 604 | fetch_register_operand(op); |
3c118e24 AK |
605 | op->orig_val = op->val; |
606 | } | |
607 | ||
1c73ef66 | 608 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
609 | struct x86_emulate_ops *ops, |
610 | struct operand *op) | |
1c73ef66 AK |
611 | { |
612 | struct decode_cache *c = &ctxt->decode; | |
613 | u8 sib; | |
f5b4edcd | 614 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 615 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 616 | ulong modrm_ea = 0; |
1c73ef66 AK |
617 | |
618 | if (c->rex_prefix) { | |
619 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
620 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
621 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
622 | } | |
623 | ||
624 | c->modrm = insn_fetch(u8, 1, c->eip); | |
625 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
626 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
627 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 628 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
629 | |
630 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
631 | op->type = OP_REG; |
632 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
633 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 634 | c->regs, c->d & ByteOp); |
2dbd0dd7 | 635 | fetch_register_operand(op); |
1c73ef66 AK |
636 | return rc; |
637 | } | |
638 | ||
2dbd0dd7 AK |
639 | op->type = OP_MEM; |
640 | ||
1c73ef66 AK |
641 | if (c->ad_bytes == 2) { |
642 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
643 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
644 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
645 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
646 | ||
647 | /* 16-bit ModR/M decode. */ | |
648 | switch (c->modrm_mod) { | |
649 | case 0: | |
650 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 651 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
652 | break; |
653 | case 1: | |
2dbd0dd7 | 654 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
655 | break; |
656 | case 2: | |
2dbd0dd7 | 657 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
658 | break; |
659 | } | |
660 | switch (c->modrm_rm) { | |
661 | case 0: | |
2dbd0dd7 | 662 | modrm_ea += bx + si; |
1c73ef66 AK |
663 | break; |
664 | case 1: | |
2dbd0dd7 | 665 | modrm_ea += bx + di; |
1c73ef66 AK |
666 | break; |
667 | case 2: | |
2dbd0dd7 | 668 | modrm_ea += bp + si; |
1c73ef66 AK |
669 | break; |
670 | case 3: | |
2dbd0dd7 | 671 | modrm_ea += bp + di; |
1c73ef66 AK |
672 | break; |
673 | case 4: | |
2dbd0dd7 | 674 | modrm_ea += si; |
1c73ef66 AK |
675 | break; |
676 | case 5: | |
2dbd0dd7 | 677 | modrm_ea += di; |
1c73ef66 AK |
678 | break; |
679 | case 6: | |
680 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 681 | modrm_ea += bp; |
1c73ef66 AK |
682 | break; |
683 | case 7: | |
2dbd0dd7 | 684 | modrm_ea += bx; |
1c73ef66 AK |
685 | break; |
686 | } | |
687 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
688 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 689 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 690 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
691 | } else { |
692 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 693 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
694 | sib = insn_fetch(u8, 1, c->eip); |
695 | index_reg |= (sib >> 3) & 7; | |
696 | base_reg |= sib & 7; | |
697 | scale = sib >> 6; | |
698 | ||
dc71d0f1 | 699 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 700 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 701 | else |
2dbd0dd7 | 702 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 703 | if (index_reg != 4) |
2dbd0dd7 | 704 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
705 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
706 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 707 | c->rip_relative = 1; |
84411d85 | 708 | } else |
2dbd0dd7 | 709 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
710 | switch (c->modrm_mod) { |
711 | case 0: | |
712 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 713 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
714 | break; |
715 | case 1: | |
2dbd0dd7 | 716 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
717 | break; |
718 | case 2: | |
2dbd0dd7 | 719 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
720 | break; |
721 | } | |
722 | } | |
2dbd0dd7 | 723 | op->addr.mem = modrm_ea; |
1c73ef66 AK |
724 | done: |
725 | return rc; | |
726 | } | |
727 | ||
728 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
729 | struct x86_emulate_ops *ops, |
730 | struct operand *op) | |
1c73ef66 AK |
731 | { |
732 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 733 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 734 | |
2dbd0dd7 | 735 | op->type = OP_MEM; |
1c73ef66 AK |
736 | switch (c->ad_bytes) { |
737 | case 2: | |
2dbd0dd7 | 738 | op->addr.mem = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
739 | break; |
740 | case 4: | |
2dbd0dd7 | 741 | op->addr.mem = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
742 | break; |
743 | case 8: | |
2dbd0dd7 | 744 | op->addr.mem = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
745 | break; |
746 | } | |
747 | done: | |
748 | return rc; | |
749 | } | |
750 | ||
35c843c4 WY |
751 | static void fetch_bit_operand(struct decode_cache *c) |
752 | { | |
753 | long sv, mask; | |
754 | ||
3885f18f | 755 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
756 | mask = ~(c->dst.bytes * 8 - 1); |
757 | ||
758 | if (c->src.bytes == 2) | |
759 | sv = (s16)c->src.val & (s16)mask; | |
760 | else if (c->src.bytes == 4) | |
761 | sv = (s32)c->src.val & (s32)mask; | |
762 | ||
763 | c->dst.addr.mem += (sv >> 3); | |
764 | } | |
ba7ff2b7 WY |
765 | |
766 | /* only subword offset */ | |
767 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
768 | } |
769 | ||
dde7e6d1 AK |
770 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
771 | struct x86_emulate_ops *ops, | |
772 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 773 | { |
dde7e6d1 AK |
774 | int rc; |
775 | struct read_cache *mc = &ctxt->decode.mem_read; | |
776 | u32 err; | |
6aa8b732 | 777 | |
dde7e6d1 AK |
778 | while (size) { |
779 | int n = min(size, 8u); | |
780 | size -= n; | |
781 | if (mc->pos < mc->end) | |
782 | goto read_cached; | |
5cd21917 | 783 | |
dde7e6d1 AK |
784 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
785 | ctxt->vcpu); | |
786 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
787 | emulate_pf(ctxt, addr, err); | |
788 | if (rc != X86EMUL_CONTINUE) | |
789 | return rc; | |
790 | mc->end += n; | |
6aa8b732 | 791 | |
dde7e6d1 AK |
792 | read_cached: |
793 | memcpy(dest, mc->data + mc->pos, n); | |
794 | mc->pos += n; | |
795 | dest += n; | |
796 | addr += n; | |
6aa8b732 | 797 | } |
dde7e6d1 AK |
798 | return X86EMUL_CONTINUE; |
799 | } | |
6aa8b732 | 800 | |
dde7e6d1 AK |
801 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
802 | struct x86_emulate_ops *ops, | |
803 | unsigned int size, unsigned short port, | |
804 | void *dest) | |
805 | { | |
806 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 807 | |
dde7e6d1 AK |
808 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
809 | struct decode_cache *c = &ctxt->decode; | |
810 | unsigned int in_page, n; | |
811 | unsigned int count = c->rep_prefix ? | |
812 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
813 | in_page = (ctxt->eflags & EFLG_DF) ? | |
814 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
815 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
816 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
817 | count); | |
818 | if (n == 0) | |
819 | n = 1; | |
820 | rc->pos = rc->end = 0; | |
821 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
822 | return 0; | |
823 | rc->end = n * size; | |
6aa8b732 AK |
824 | } |
825 | ||
dde7e6d1 AK |
826 | memcpy(dest, rc->data + rc->pos, size); |
827 | rc->pos += size; | |
828 | return 1; | |
829 | } | |
6aa8b732 | 830 | |
dde7e6d1 AK |
831 | static u32 desc_limit_scaled(struct desc_struct *desc) |
832 | { | |
833 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 834 | |
dde7e6d1 AK |
835 | return desc->g ? (limit << 12) | 0xfff : limit; |
836 | } | |
6aa8b732 | 837 | |
dde7e6d1 AK |
838 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
839 | struct x86_emulate_ops *ops, | |
840 | u16 selector, struct desc_ptr *dt) | |
841 | { | |
842 | if (selector & 1 << 2) { | |
843 | struct desc_struct desc; | |
844 | memset (dt, 0, sizeof *dt); | |
845 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
846 | return; | |
e09d082c | 847 | |
dde7e6d1 AK |
848 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
849 | dt->address = get_desc_base(&desc); | |
850 | } else | |
851 | ops->get_gdt(dt, ctxt->vcpu); | |
852 | } | |
120df890 | 853 | |
dde7e6d1 AK |
854 | /* allowed just for 8 bytes segments */ |
855 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
856 | struct x86_emulate_ops *ops, | |
857 | u16 selector, struct desc_struct *desc) | |
858 | { | |
859 | struct desc_ptr dt; | |
860 | u16 index = selector >> 3; | |
861 | int ret; | |
862 | u32 err; | |
863 | ulong addr; | |
120df890 | 864 | |
dde7e6d1 | 865 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 866 | |
dde7e6d1 AK |
867 | if (dt.size < index * 8 + 7) { |
868 | emulate_gp(ctxt, selector & 0xfffc); | |
869 | return X86EMUL_PROPAGATE_FAULT; | |
e09d082c | 870 | } |
dde7e6d1 AK |
871 | addr = dt.address + index * 8; |
872 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
873 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
874 | emulate_pf(ctxt, addr, err); | |
e09d082c | 875 | |
dde7e6d1 AK |
876 | return ret; |
877 | } | |
ef65c889 | 878 | |
dde7e6d1 AK |
879 | /* allowed just for 8 bytes segments */ |
880 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
881 | struct x86_emulate_ops *ops, | |
882 | u16 selector, struct desc_struct *desc) | |
883 | { | |
884 | struct desc_ptr dt; | |
885 | u16 index = selector >> 3; | |
886 | u32 err; | |
887 | ulong addr; | |
888 | int ret; | |
6aa8b732 | 889 | |
dde7e6d1 | 890 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 891 | |
dde7e6d1 AK |
892 | if (dt.size < index * 8 + 7) { |
893 | emulate_gp(ctxt, selector & 0xfffc); | |
894 | return X86EMUL_PROPAGATE_FAULT; | |
895 | } | |
6aa8b732 | 896 | |
dde7e6d1 AK |
897 | addr = dt.address + index * 8; |
898 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
899 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
900 | emulate_pf(ctxt, addr, err); | |
c7e75a3d | 901 | |
dde7e6d1 AK |
902 | return ret; |
903 | } | |
c7e75a3d | 904 | |
dde7e6d1 AK |
905 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
906 | struct x86_emulate_ops *ops, | |
907 | u16 selector, int seg) | |
908 | { | |
909 | struct desc_struct seg_desc; | |
910 | u8 dpl, rpl, cpl; | |
911 | unsigned err_vec = GP_VECTOR; | |
912 | u32 err_code = 0; | |
913 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
914 | int ret; | |
69f55cb1 | 915 | |
dde7e6d1 | 916 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 917 | |
dde7e6d1 AK |
918 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
919 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
920 | /* set real mode segment descriptor */ | |
921 | set_desc_base(&seg_desc, selector << 4); | |
922 | set_desc_limit(&seg_desc, 0xffff); | |
923 | seg_desc.type = 3; | |
924 | seg_desc.p = 1; | |
925 | seg_desc.s = 1; | |
926 | goto load; | |
927 | } | |
928 | ||
929 | /* NULL selector is not valid for TR, CS and SS */ | |
930 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
931 | && null_selector) | |
932 | goto exception; | |
933 | ||
934 | /* TR should be in GDT only */ | |
935 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
936 | goto exception; | |
937 | ||
938 | if (null_selector) /* for NULL selector skip all following checks */ | |
939 | goto load; | |
940 | ||
941 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
942 | if (ret != X86EMUL_CONTINUE) | |
943 | return ret; | |
944 | ||
945 | err_code = selector & 0xfffc; | |
946 | err_vec = GP_VECTOR; | |
947 | ||
948 | /* can't load system descriptor into segment selecor */ | |
949 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
950 | goto exception; | |
951 | ||
952 | if (!seg_desc.p) { | |
953 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
954 | goto exception; | |
955 | } | |
956 | ||
957 | rpl = selector & 3; | |
958 | dpl = seg_desc.dpl; | |
959 | cpl = ops->cpl(ctxt->vcpu); | |
960 | ||
961 | switch (seg) { | |
962 | case VCPU_SREG_SS: | |
963 | /* | |
964 | * segment is not a writable data segment or segment | |
965 | * selector's RPL != CPL or segment selector's RPL != CPL | |
966 | */ | |
967 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
968 | goto exception; | |
6aa8b732 | 969 | break; |
dde7e6d1 AK |
970 | case VCPU_SREG_CS: |
971 | if (!(seg_desc.type & 8)) | |
972 | goto exception; | |
973 | ||
974 | if (seg_desc.type & 4) { | |
975 | /* conforming */ | |
976 | if (dpl > cpl) | |
977 | goto exception; | |
978 | } else { | |
979 | /* nonconforming */ | |
980 | if (rpl > cpl || dpl != cpl) | |
981 | goto exception; | |
982 | } | |
983 | /* CS(RPL) <- CPL */ | |
984 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 985 | break; |
dde7e6d1 AK |
986 | case VCPU_SREG_TR: |
987 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
988 | goto exception; | |
989 | break; | |
990 | case VCPU_SREG_LDTR: | |
991 | if (seg_desc.s || seg_desc.type != 2) | |
992 | goto exception; | |
993 | break; | |
994 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 995 | /* |
dde7e6d1 AK |
996 | * segment is not a data or readable code segment or |
997 | * ((segment is a data or nonconforming code segment) | |
998 | * and (both RPL and CPL > DPL)) | |
4e62417b | 999 | */ |
dde7e6d1 AK |
1000 | if ((seg_desc.type & 0xa) == 0x8 || |
1001 | (((seg_desc.type & 0xc) != 0xc) && | |
1002 | (rpl > dpl && cpl > dpl))) | |
1003 | goto exception; | |
6aa8b732 | 1004 | break; |
dde7e6d1 AK |
1005 | } |
1006 | ||
1007 | if (seg_desc.s) { | |
1008 | /* mark segment as accessed */ | |
1009 | seg_desc.type |= 1; | |
1010 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1011 | if (ret != X86EMUL_CONTINUE) | |
1012 | return ret; | |
1013 | } | |
1014 | load: | |
1015 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1016 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1017 | return X86EMUL_CONTINUE; | |
1018 | exception: | |
1019 | emulate_exception(ctxt, err_vec, err_code, true); | |
1020 | return X86EMUL_PROPAGATE_FAULT; | |
1021 | } | |
1022 | ||
31be40b3 WY |
1023 | static void write_register_operand(struct operand *op) |
1024 | { | |
1025 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1026 | switch (op->bytes) { | |
1027 | case 1: | |
1028 | *(u8 *)op->addr.reg = (u8)op->val; | |
1029 | break; | |
1030 | case 2: | |
1031 | *(u16 *)op->addr.reg = (u16)op->val; | |
1032 | break; | |
1033 | case 4: | |
1034 | *op->addr.reg = (u32)op->val; | |
1035 | break; /* 64b: zero-extend */ | |
1036 | case 8: | |
1037 | *op->addr.reg = op->val; | |
1038 | break; | |
1039 | } | |
1040 | } | |
1041 | ||
dde7e6d1 AK |
1042 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1043 | struct x86_emulate_ops *ops) | |
1044 | { | |
1045 | int rc; | |
1046 | struct decode_cache *c = &ctxt->decode; | |
1047 | u32 err; | |
1048 | ||
1049 | switch (c->dst.type) { | |
1050 | case OP_REG: | |
31be40b3 | 1051 | write_register_operand(&c->dst); |
6aa8b732 | 1052 | break; |
dde7e6d1 AK |
1053 | case OP_MEM: |
1054 | if (c->lock_prefix) | |
1055 | rc = ops->cmpxchg_emulated( | |
1a6440ae | 1056 | c->dst.addr.mem, |
dde7e6d1 AK |
1057 | &c->dst.orig_val, |
1058 | &c->dst.val, | |
1059 | c->dst.bytes, | |
1060 | &err, | |
1061 | ctxt->vcpu); | |
341de7e3 | 1062 | else |
dde7e6d1 | 1063 | rc = ops->write_emulated( |
1a6440ae | 1064 | c->dst.addr.mem, |
dde7e6d1 AK |
1065 | &c->dst.val, |
1066 | c->dst.bytes, | |
1067 | &err, | |
1068 | ctxt->vcpu); | |
1069 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1a6440ae | 1070 | emulate_pf(ctxt, c->dst.addr.mem, err); |
dde7e6d1 AK |
1071 | if (rc != X86EMUL_CONTINUE) |
1072 | return rc; | |
a682e354 | 1073 | break; |
dde7e6d1 AK |
1074 | case OP_NONE: |
1075 | /* no writeback */ | |
414e6277 | 1076 | break; |
dde7e6d1 | 1077 | default: |
414e6277 | 1078 | break; |
6aa8b732 | 1079 | } |
dde7e6d1 AK |
1080 | return X86EMUL_CONTINUE; |
1081 | } | |
6aa8b732 | 1082 | |
dde7e6d1 AK |
1083 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1084 | struct x86_emulate_ops *ops) | |
1085 | { | |
1086 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1087 | |
dde7e6d1 AK |
1088 | c->dst.type = OP_MEM; |
1089 | c->dst.bytes = c->op_bytes; | |
1090 | c->dst.val = c->src.val; | |
1091 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
1a6440ae AK |
1092 | c->dst.addr.mem = register_address(c, ss_base(ctxt, ops), |
1093 | c->regs[VCPU_REGS_RSP]); | |
dde7e6d1 | 1094 | } |
69f55cb1 | 1095 | |
dde7e6d1 AK |
1096 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1097 | struct x86_emulate_ops *ops, | |
1098 | void *dest, int len) | |
1099 | { | |
1100 | struct decode_cache *c = &ctxt->decode; | |
1101 | int rc; | |
8b4caf66 | 1102 | |
dde7e6d1 AK |
1103 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
1104 | c->regs[VCPU_REGS_RSP]), | |
1105 | dest, len); | |
1106 | if (rc != X86EMUL_CONTINUE) | |
1107 | return rc; | |
1108 | ||
1109 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1110 | return rc; | |
8b4caf66 LV |
1111 | } |
1112 | ||
dde7e6d1 AK |
1113 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1114 | struct x86_emulate_ops *ops, | |
1115 | void *dest, int len) | |
9de41573 GN |
1116 | { |
1117 | int rc; | |
dde7e6d1 AK |
1118 | unsigned long val, change_mask; |
1119 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1120 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1121 | |
dde7e6d1 AK |
1122 | rc = emulate_pop(ctxt, ops, &val, len); |
1123 | if (rc != X86EMUL_CONTINUE) | |
1124 | return rc; | |
9de41573 | 1125 | |
dde7e6d1 AK |
1126 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1127 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1128 | |
dde7e6d1 AK |
1129 | switch(ctxt->mode) { |
1130 | case X86EMUL_MODE_PROT64: | |
1131 | case X86EMUL_MODE_PROT32: | |
1132 | case X86EMUL_MODE_PROT16: | |
1133 | if (cpl == 0) | |
1134 | change_mask |= EFLG_IOPL; | |
1135 | if (cpl <= iopl) | |
1136 | change_mask |= EFLG_IF; | |
1137 | break; | |
1138 | case X86EMUL_MODE_VM86: | |
1139 | if (iopl < 3) { | |
1140 | emulate_gp(ctxt, 0); | |
1141 | return X86EMUL_PROPAGATE_FAULT; | |
1142 | } | |
1143 | change_mask |= EFLG_IF; | |
1144 | break; | |
1145 | default: /* real mode */ | |
1146 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1147 | break; | |
9de41573 | 1148 | } |
dde7e6d1 AK |
1149 | |
1150 | *(unsigned long *)dest = | |
1151 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1152 | ||
1153 | return rc; | |
9de41573 GN |
1154 | } |
1155 | ||
dde7e6d1 AK |
1156 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1157 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1158 | { |
dde7e6d1 | 1159 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1160 | |
dde7e6d1 | 1161 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1162 | |
dde7e6d1 | 1163 | emulate_push(ctxt, ops); |
7b262e90 GN |
1164 | } |
1165 | ||
dde7e6d1 AK |
1166 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1167 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1168 | { |
dde7e6d1 AK |
1169 | struct decode_cache *c = &ctxt->decode; |
1170 | unsigned long selector; | |
1171 | int rc; | |
38ba30ba | 1172 | |
dde7e6d1 AK |
1173 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1174 | if (rc != X86EMUL_CONTINUE) | |
1175 | return rc; | |
1176 | ||
1177 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1178 | return rc; | |
38ba30ba GN |
1179 | } |
1180 | ||
dde7e6d1 AK |
1181 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1182 | struct x86_emulate_ops *ops) | |
38ba30ba | 1183 | { |
dde7e6d1 AK |
1184 | struct decode_cache *c = &ctxt->decode; |
1185 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1186 | int rc = X86EMUL_CONTINUE; | |
1187 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1188 | |
dde7e6d1 AK |
1189 | while (reg <= VCPU_REGS_RDI) { |
1190 | (reg == VCPU_REGS_RSP) ? | |
1191 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1192 | |
dde7e6d1 | 1193 | emulate_push(ctxt, ops); |
38ba30ba | 1194 | |
dde7e6d1 AK |
1195 | rc = writeback(ctxt, ops); |
1196 | if (rc != X86EMUL_CONTINUE) | |
1197 | return rc; | |
38ba30ba | 1198 | |
dde7e6d1 | 1199 | ++reg; |
38ba30ba | 1200 | } |
38ba30ba | 1201 | |
dde7e6d1 AK |
1202 | /* Disable writeback. */ |
1203 | c->dst.type = OP_NONE; | |
1204 | ||
1205 | return rc; | |
38ba30ba GN |
1206 | } |
1207 | ||
dde7e6d1 AK |
1208 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1209 | struct x86_emulate_ops *ops) | |
38ba30ba | 1210 | { |
dde7e6d1 AK |
1211 | struct decode_cache *c = &ctxt->decode; |
1212 | int rc = X86EMUL_CONTINUE; | |
1213 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1214 | |
dde7e6d1 AK |
1215 | while (reg >= VCPU_REGS_RAX) { |
1216 | if (reg == VCPU_REGS_RSP) { | |
1217 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1218 | c->op_bytes); | |
1219 | --reg; | |
1220 | } | |
38ba30ba | 1221 | |
dde7e6d1 AK |
1222 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1223 | if (rc != X86EMUL_CONTINUE) | |
1224 | break; | |
1225 | --reg; | |
38ba30ba | 1226 | } |
dde7e6d1 | 1227 | return rc; |
38ba30ba GN |
1228 | } |
1229 | ||
6e154e56 MG |
1230 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1231 | struct x86_emulate_ops *ops, int irq) | |
1232 | { | |
1233 | struct decode_cache *c = &ctxt->decode; | |
1234 | int rc = X86EMUL_CONTINUE; | |
1235 | struct desc_ptr dt; | |
1236 | gva_t cs_addr; | |
1237 | gva_t eip_addr; | |
1238 | u16 cs, eip; | |
1239 | u32 err; | |
1240 | ||
1241 | /* TODO: Add limit checks */ | |
1242 | c->src.val = ctxt->eflags; | |
1243 | emulate_push(ctxt, ops); | |
1244 | ||
1245 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1246 | ||
1247 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1248 | emulate_push(ctxt, ops); | |
1249 | ||
1250 | c->src.val = c->eip; | |
1251 | emulate_push(ctxt, ops); | |
1252 | ||
1253 | ops->get_idt(&dt, ctxt->vcpu); | |
1254 | ||
1255 | eip_addr = dt.address + (irq << 2); | |
1256 | cs_addr = dt.address + (irq << 2) + 2; | |
1257 | ||
1258 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err); | |
1259 | if (rc != X86EMUL_CONTINUE) | |
1260 | return rc; | |
1261 | ||
1262 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err); | |
1263 | if (rc != X86EMUL_CONTINUE) | |
1264 | return rc; | |
1265 | ||
1266 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1267 | if (rc != X86EMUL_CONTINUE) | |
1268 | return rc; | |
1269 | ||
1270 | c->eip = eip; | |
1271 | ||
1272 | return rc; | |
1273 | } | |
1274 | ||
1275 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1276 | struct x86_emulate_ops *ops, int irq) | |
1277 | { | |
1278 | switch(ctxt->mode) { | |
1279 | case X86EMUL_MODE_REAL: | |
1280 | return emulate_int_real(ctxt, ops, irq); | |
1281 | case X86EMUL_MODE_VM86: | |
1282 | case X86EMUL_MODE_PROT16: | |
1283 | case X86EMUL_MODE_PROT32: | |
1284 | case X86EMUL_MODE_PROT64: | |
1285 | default: | |
1286 | /* Protected mode interrupts unimplemented yet */ | |
1287 | return X86EMUL_UNHANDLEABLE; | |
1288 | } | |
1289 | } | |
1290 | ||
dde7e6d1 AK |
1291 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1292 | struct x86_emulate_ops *ops) | |
38ba30ba | 1293 | { |
dde7e6d1 AK |
1294 | struct decode_cache *c = &ctxt->decode; |
1295 | int rc = X86EMUL_CONTINUE; | |
1296 | unsigned long temp_eip = 0; | |
1297 | unsigned long temp_eflags = 0; | |
1298 | unsigned long cs = 0; | |
1299 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1300 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1301 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1302 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1303 | |
dde7e6d1 | 1304 | /* TODO: Add stack limit check */ |
38ba30ba | 1305 | |
dde7e6d1 | 1306 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1307 | |
dde7e6d1 AK |
1308 | if (rc != X86EMUL_CONTINUE) |
1309 | return rc; | |
38ba30ba | 1310 | |
dde7e6d1 AK |
1311 | if (temp_eip & ~0xffff) { |
1312 | emulate_gp(ctxt, 0); | |
1313 | return X86EMUL_PROPAGATE_FAULT; | |
1314 | } | |
38ba30ba | 1315 | |
dde7e6d1 | 1316 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1317 | |
dde7e6d1 AK |
1318 | if (rc != X86EMUL_CONTINUE) |
1319 | return rc; | |
38ba30ba | 1320 | |
dde7e6d1 | 1321 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1322 | |
dde7e6d1 AK |
1323 | if (rc != X86EMUL_CONTINUE) |
1324 | return rc; | |
38ba30ba | 1325 | |
dde7e6d1 | 1326 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1327 | |
dde7e6d1 AK |
1328 | if (rc != X86EMUL_CONTINUE) |
1329 | return rc; | |
38ba30ba | 1330 | |
dde7e6d1 | 1331 | c->eip = temp_eip; |
38ba30ba | 1332 | |
38ba30ba | 1333 | |
dde7e6d1 AK |
1334 | if (c->op_bytes == 4) |
1335 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1336 | else if (c->op_bytes == 2) { | |
1337 | ctxt->eflags &= ~0xffff; | |
1338 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1339 | } |
dde7e6d1 AK |
1340 | |
1341 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1342 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1343 | ||
1344 | return rc; | |
38ba30ba GN |
1345 | } |
1346 | ||
dde7e6d1 AK |
1347 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1348 | struct x86_emulate_ops* ops) | |
c37eda13 | 1349 | { |
dde7e6d1 AK |
1350 | switch(ctxt->mode) { |
1351 | case X86EMUL_MODE_REAL: | |
1352 | return emulate_iret_real(ctxt, ops); | |
1353 | case X86EMUL_MODE_VM86: | |
1354 | case X86EMUL_MODE_PROT16: | |
1355 | case X86EMUL_MODE_PROT32: | |
1356 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1357 | default: |
dde7e6d1 AK |
1358 | /* iret from protected mode unimplemented yet */ |
1359 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1360 | } |
c37eda13 WY |
1361 | } |
1362 | ||
dde7e6d1 | 1363 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1364 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1365 | { |
1366 | struct decode_cache *c = &ctxt->decode; | |
1367 | ||
dde7e6d1 | 1368 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1369 | } |
1370 | ||
dde7e6d1 | 1371 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1372 | { |
05f086f8 | 1373 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1374 | switch (c->modrm_reg) { |
1375 | case 0: /* rol */ | |
05f086f8 | 1376 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1377 | break; |
1378 | case 1: /* ror */ | |
05f086f8 | 1379 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1380 | break; |
1381 | case 2: /* rcl */ | |
05f086f8 | 1382 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1383 | break; |
1384 | case 3: /* rcr */ | |
05f086f8 | 1385 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1386 | break; |
1387 | case 4: /* sal/shl */ | |
1388 | case 6: /* sal/shl */ | |
05f086f8 | 1389 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1390 | break; |
1391 | case 5: /* shr */ | |
05f086f8 | 1392 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1393 | break; |
1394 | case 7: /* sar */ | |
05f086f8 | 1395 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1396 | break; |
1397 | } | |
1398 | } | |
1399 | ||
1400 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1401 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1402 | { |
1403 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1404 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1405 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
8cdbd2c9 LV |
1406 | |
1407 | switch (c->modrm_reg) { | |
1408 | case 0 ... 1: /* test */ | |
05f086f8 | 1409 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1410 | break; |
1411 | case 2: /* not */ | |
1412 | c->dst.val = ~c->dst.val; | |
1413 | break; | |
1414 | case 3: /* neg */ | |
05f086f8 | 1415 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1416 | break; |
3f9f53b0 MG |
1417 | case 4: /* mul */ |
1418 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1419 | break; | |
1420 | case 5: /* imul */ | |
1421 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1422 | break; | |
1423 | case 6: /* div */ | |
1424 | emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags); | |
1425 | break; | |
1426 | case 7: /* idiv */ | |
1427 | emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags); | |
1428 | break; | |
8cdbd2c9 | 1429 | default: |
8c5eee30 | 1430 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1431 | } |
8c5eee30 | 1432 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1433 | } |
1434 | ||
1435 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1436 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1437 | { |
1438 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1439 | |
1440 | switch (c->modrm_reg) { | |
1441 | case 0: /* inc */ | |
05f086f8 | 1442 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1443 | break; |
1444 | case 1: /* dec */ | |
05f086f8 | 1445 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1446 | break; |
d19292e4 MG |
1447 | case 2: /* call near abs */ { |
1448 | long int old_eip; | |
1449 | old_eip = c->eip; | |
1450 | c->eip = c->src.val; | |
1451 | c->src.val = old_eip; | |
79168fd1 | 1452 | emulate_push(ctxt, ops); |
d19292e4 MG |
1453 | break; |
1454 | } | |
8cdbd2c9 | 1455 | case 4: /* jmp abs */ |
fd60754e | 1456 | c->eip = c->src.val; |
8cdbd2c9 LV |
1457 | break; |
1458 | case 6: /* push */ | |
79168fd1 | 1459 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1460 | break; |
8cdbd2c9 | 1461 | } |
1b30eaa8 | 1462 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1463 | } |
1464 | ||
1465 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1466 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1467 | { |
1468 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1469 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1470 | |
1471 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1472 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1473 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1474 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1475 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1476 | } else { |
16518d5a AK |
1477 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1478 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1479 | |
05f086f8 | 1480 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1481 | } |
1b30eaa8 | 1482 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1483 | } |
1484 | ||
a77ab5ea AK |
1485 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1486 | struct x86_emulate_ops *ops) | |
1487 | { | |
1488 | struct decode_cache *c = &ctxt->decode; | |
1489 | int rc; | |
1490 | unsigned long cs; | |
1491 | ||
1492 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1493 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1494 | return rc; |
1495 | if (c->op_bytes == 4) | |
1496 | c->eip = (u32)c->eip; | |
1497 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1498 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1499 | return rc; |
2e873022 | 1500 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1501 | return rc; |
1502 | } | |
1503 | ||
e66bb2cc AP |
1504 | static inline void |
1505 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1506 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1507 | struct desc_struct *ss) | |
e66bb2cc | 1508 | { |
79168fd1 GN |
1509 | memset(cs, 0, sizeof(struct desc_struct)); |
1510 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1511 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1512 | |
1513 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1514 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1515 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1516 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1517 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1518 | cs->s = 1; | |
1519 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1520 | cs->p = 1; |
1521 | cs->d = 1; | |
e66bb2cc | 1522 | |
79168fd1 GN |
1523 | set_desc_base(ss, 0); /* flat segment */ |
1524 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1525 | ss->g = 1; /* 4kb granularity */ |
1526 | ss->s = 1; | |
1527 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1528 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1529 | ss->dpl = 0; |
79168fd1 | 1530 | ss->p = 1; |
e66bb2cc AP |
1531 | } |
1532 | ||
1533 | static int | |
3fb1b5db | 1534 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1535 | { |
1536 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1537 | struct desc_struct cs, ss; |
e66bb2cc | 1538 | u64 msr_data; |
79168fd1 | 1539 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1540 | |
1541 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1542 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1543 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1544 | emulate_ud(ctxt); |
2e901c4c GN |
1545 | return X86EMUL_PROPAGATE_FAULT; |
1546 | } | |
e66bb2cc | 1547 | |
79168fd1 | 1548 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1549 | |
3fb1b5db | 1550 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1551 | msr_data >>= 32; |
79168fd1 GN |
1552 | cs_sel = (u16)(msr_data & 0xfffc); |
1553 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1554 | |
1555 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1556 | cs.d = 0; |
e66bb2cc AP |
1557 | cs.l = 1; |
1558 | } | |
79168fd1 GN |
1559 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1560 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1561 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1562 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1563 | |
1564 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1565 | if (is_long_mode(ctxt->vcpu)) { | |
1566 | #ifdef CONFIG_X86_64 | |
1567 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1568 | ||
3fb1b5db GN |
1569 | ops->get_msr(ctxt->vcpu, |
1570 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1571 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1572 | c->eip = msr_data; |
1573 | ||
3fb1b5db | 1574 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1575 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1576 | #endif | |
1577 | } else { | |
1578 | /* legacy mode */ | |
3fb1b5db | 1579 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1580 | c->eip = (u32)msr_data; |
1581 | ||
1582 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1583 | } | |
1584 | ||
e54cfa97 | 1585 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1586 | } |
1587 | ||
8c604352 | 1588 | static int |
3fb1b5db | 1589 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1590 | { |
1591 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1592 | struct desc_struct cs, ss; |
8c604352 | 1593 | u64 msr_data; |
79168fd1 | 1594 | u16 cs_sel, ss_sel; |
8c604352 | 1595 | |
a0044755 GN |
1596 | /* inject #GP if in real mode */ |
1597 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 1598 | emulate_gp(ctxt, 0); |
2e901c4c | 1599 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1600 | } |
1601 | ||
1602 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1603 | * Therefore, we inject an #UD. | |
1604 | */ | |
2e901c4c | 1605 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 1606 | emulate_ud(ctxt); |
2e901c4c GN |
1607 | return X86EMUL_PROPAGATE_FAULT; |
1608 | } | |
8c604352 | 1609 | |
79168fd1 | 1610 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1611 | |
3fb1b5db | 1612 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1613 | switch (ctxt->mode) { |
1614 | case X86EMUL_MODE_PROT32: | |
1615 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 1616 | emulate_gp(ctxt, 0); |
e54cfa97 | 1617 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1618 | } |
1619 | break; | |
1620 | case X86EMUL_MODE_PROT64: | |
1621 | if (msr_data == 0x0) { | |
54b8486f | 1622 | emulate_gp(ctxt, 0); |
e54cfa97 | 1623 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1624 | } |
1625 | break; | |
1626 | } | |
1627 | ||
1628 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1629 | cs_sel = (u16)msr_data; |
1630 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1631 | ss_sel = cs_sel + 8; | |
1632 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1633 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1634 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1635 | cs.d = 0; |
8c604352 AP |
1636 | cs.l = 1; |
1637 | } | |
1638 | ||
79168fd1 GN |
1639 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1640 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1641 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1642 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 1643 | |
3fb1b5db | 1644 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1645 | c->eip = msr_data; |
1646 | ||
3fb1b5db | 1647 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1648 | c->regs[VCPU_REGS_RSP] = msr_data; |
1649 | ||
e54cfa97 | 1650 | return X86EMUL_CONTINUE; |
8c604352 AP |
1651 | } |
1652 | ||
4668f050 | 1653 | static int |
3fb1b5db | 1654 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1655 | { |
1656 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1657 | struct desc_struct cs, ss; |
4668f050 AP |
1658 | u64 msr_data; |
1659 | int usermode; | |
79168fd1 | 1660 | u16 cs_sel, ss_sel; |
4668f050 | 1661 | |
a0044755 GN |
1662 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1663 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1664 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1665 | emulate_gp(ctxt, 0); |
2e901c4c | 1666 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1667 | } |
1668 | ||
79168fd1 | 1669 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1670 | |
1671 | if ((c->rex_prefix & 0x8) != 0x0) | |
1672 | usermode = X86EMUL_MODE_PROT64; | |
1673 | else | |
1674 | usermode = X86EMUL_MODE_PROT32; | |
1675 | ||
1676 | cs.dpl = 3; | |
1677 | ss.dpl = 3; | |
3fb1b5db | 1678 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1679 | switch (usermode) { |
1680 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1681 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 1682 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 1683 | emulate_gp(ctxt, 0); |
e54cfa97 | 1684 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1685 | } |
79168fd1 | 1686 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1687 | break; |
1688 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1689 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 1690 | if (msr_data == 0x0) { |
54b8486f | 1691 | emulate_gp(ctxt, 0); |
e54cfa97 | 1692 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1693 | } |
79168fd1 GN |
1694 | ss_sel = cs_sel + 8; |
1695 | cs.d = 0; | |
4668f050 AP |
1696 | cs.l = 1; |
1697 | break; | |
1698 | } | |
79168fd1 GN |
1699 | cs_sel |= SELECTOR_RPL_MASK; |
1700 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1701 | |
79168fd1 GN |
1702 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1703 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1704 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1705 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 1706 | |
bdb475a3 GN |
1707 | c->eip = c->regs[VCPU_REGS_RDX]; |
1708 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1709 | |
e54cfa97 | 1710 | return X86EMUL_CONTINUE; |
4668f050 AP |
1711 | } |
1712 | ||
9c537244 GN |
1713 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1714 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1715 | { |
1716 | int iopl; | |
1717 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1718 | return false; | |
1719 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1720 | return true; | |
1721 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1722 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1723 | } |
1724 | ||
1725 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1726 | struct x86_emulate_ops *ops, | |
1727 | u16 port, u16 len) | |
1728 | { | |
79168fd1 | 1729 | struct desc_struct tr_seg; |
f850e2e6 GN |
1730 | int r; |
1731 | u16 io_bitmap_ptr; | |
1732 | u8 perm, bit_idx = port & 0x7; | |
1733 | unsigned mask = (1 << len) - 1; | |
1734 | ||
79168fd1 GN |
1735 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
1736 | if (!tr_seg.p) | |
f850e2e6 | 1737 | return false; |
79168fd1 | 1738 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1739 | return false; |
79168fd1 GN |
1740 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
1741 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
1742 | if (r != X86EMUL_CONTINUE) |
1743 | return false; | |
79168fd1 | 1744 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1745 | return false; |
79168fd1 GN |
1746 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
1747 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1748 | if (r != X86EMUL_CONTINUE) |
1749 | return false; | |
1750 | if ((perm >> bit_idx) & mask) | |
1751 | return false; | |
1752 | return true; | |
1753 | } | |
1754 | ||
1755 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1756 | struct x86_emulate_ops *ops, | |
1757 | u16 port, u16 len) | |
1758 | { | |
4fc40f07 GN |
1759 | if (ctxt->perm_ok) |
1760 | return true; | |
1761 | ||
9c537244 | 1762 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1763 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1764 | return false; | |
4fc40f07 GN |
1765 | |
1766 | ctxt->perm_ok = true; | |
1767 | ||
f850e2e6 GN |
1768 | return true; |
1769 | } | |
1770 | ||
38ba30ba GN |
1771 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1772 | struct x86_emulate_ops *ops, | |
1773 | struct tss_segment_16 *tss) | |
1774 | { | |
1775 | struct decode_cache *c = &ctxt->decode; | |
1776 | ||
1777 | tss->ip = c->eip; | |
1778 | tss->flag = ctxt->eflags; | |
1779 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1780 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1781 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1782 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1783 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1784 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1785 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1786 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1787 | ||
1788 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1789 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1790 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1791 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1792 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1793 | } | |
1794 | ||
1795 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1796 | struct x86_emulate_ops *ops, | |
1797 | struct tss_segment_16 *tss) | |
1798 | { | |
1799 | struct decode_cache *c = &ctxt->decode; | |
1800 | int ret; | |
1801 | ||
1802 | c->eip = tss->ip; | |
1803 | ctxt->eflags = tss->flag | 2; | |
1804 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1805 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1806 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1807 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1808 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1809 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1810 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1811 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1812 | ||
1813 | /* | |
1814 | * SDM says that segment selectors are loaded before segment | |
1815 | * descriptors | |
1816 | */ | |
1817 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1818 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1819 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1820 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1821 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1822 | ||
1823 | /* | |
1824 | * Now load segment descriptors. If fault happenes at this stage | |
1825 | * it is handled in a context of new task | |
1826 | */ | |
1827 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1828 | if (ret != X86EMUL_CONTINUE) | |
1829 | return ret; | |
1830 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1831 | if (ret != X86EMUL_CONTINUE) | |
1832 | return ret; | |
1833 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1834 | if (ret != X86EMUL_CONTINUE) | |
1835 | return ret; | |
1836 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1837 | if (ret != X86EMUL_CONTINUE) | |
1838 | return ret; | |
1839 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1840 | if (ret != X86EMUL_CONTINUE) | |
1841 | return ret; | |
1842 | ||
1843 | return X86EMUL_CONTINUE; | |
1844 | } | |
1845 | ||
1846 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1847 | struct x86_emulate_ops *ops, | |
1848 | u16 tss_selector, u16 old_tss_sel, | |
1849 | ulong old_tss_base, struct desc_struct *new_desc) | |
1850 | { | |
1851 | struct tss_segment_16 tss_seg; | |
1852 | int ret; | |
1853 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1854 | ||
1855 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1856 | &err); | |
1857 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1858 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1859 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1860 | return ret; |
1861 | } | |
1862 | ||
1863 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1864 | ||
1865 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1866 | &err); | |
1867 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1868 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1869 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1870 | return ret; |
1871 | } | |
1872 | ||
1873 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1874 | &err); | |
1875 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1876 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1877 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1878 | return ret; |
1879 | } | |
1880 | ||
1881 | if (old_tss_sel != 0xffff) { | |
1882 | tss_seg.prev_task_link = old_tss_sel; | |
1883 | ||
1884 | ret = ops->write_std(new_tss_base, | |
1885 | &tss_seg.prev_task_link, | |
1886 | sizeof tss_seg.prev_task_link, | |
1887 | ctxt->vcpu, &err); | |
1888 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1889 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1890 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1891 | return ret; |
1892 | } | |
1893 | } | |
1894 | ||
1895 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
1896 | } | |
1897 | ||
1898 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
1899 | struct x86_emulate_ops *ops, | |
1900 | struct tss_segment_32 *tss) | |
1901 | { | |
1902 | struct decode_cache *c = &ctxt->decode; | |
1903 | ||
1904 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
1905 | tss->eip = c->eip; | |
1906 | tss->eflags = ctxt->eflags; | |
1907 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
1908 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
1909 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
1910 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
1911 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
1912 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
1913 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
1914 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
1915 | ||
1916 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1917 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1918 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1919 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1920 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
1921 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
1922 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1923 | } | |
1924 | ||
1925 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
1926 | struct x86_emulate_ops *ops, | |
1927 | struct tss_segment_32 *tss) | |
1928 | { | |
1929 | struct decode_cache *c = &ctxt->decode; | |
1930 | int ret; | |
1931 | ||
0f12244f | 1932 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 1933 | emulate_gp(ctxt, 0); |
0f12244f GN |
1934 | return X86EMUL_PROPAGATE_FAULT; |
1935 | } | |
38ba30ba GN |
1936 | c->eip = tss->eip; |
1937 | ctxt->eflags = tss->eflags | 2; | |
1938 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
1939 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
1940 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
1941 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
1942 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
1943 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
1944 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
1945 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
1946 | ||
1947 | /* | |
1948 | * SDM says that segment selectors are loaded before segment | |
1949 | * descriptors | |
1950 | */ | |
1951 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
1952 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1953 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1954 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1955 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1956 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
1957 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
1958 | ||
1959 | /* | |
1960 | * Now load segment descriptors. If fault happenes at this stage | |
1961 | * it is handled in a context of new task | |
1962 | */ | |
1963 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
1964 | if (ret != X86EMUL_CONTINUE) | |
1965 | return ret; | |
1966 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1967 | if (ret != X86EMUL_CONTINUE) | |
1968 | return ret; | |
1969 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1970 | if (ret != X86EMUL_CONTINUE) | |
1971 | return ret; | |
1972 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1973 | if (ret != X86EMUL_CONTINUE) | |
1974 | return ret; | |
1975 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1976 | if (ret != X86EMUL_CONTINUE) | |
1977 | return ret; | |
1978 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
1979 | if (ret != X86EMUL_CONTINUE) | |
1980 | return ret; | |
1981 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
1982 | if (ret != X86EMUL_CONTINUE) | |
1983 | return ret; | |
1984 | ||
1985 | return X86EMUL_CONTINUE; | |
1986 | } | |
1987 | ||
1988 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
1989 | struct x86_emulate_ops *ops, | |
1990 | u16 tss_selector, u16 old_tss_sel, | |
1991 | ulong old_tss_base, struct desc_struct *new_desc) | |
1992 | { | |
1993 | struct tss_segment_32 tss_seg; | |
1994 | int ret; | |
1995 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1996 | ||
1997 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1998 | &err); | |
1999 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2000 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2001 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2002 | return ret; |
2003 | } | |
2004 | ||
2005 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2006 | ||
2007 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2008 | &err); | |
2009 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2010 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2011 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2012 | return ret; |
2013 | } | |
2014 | ||
2015 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2016 | &err); | |
2017 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2018 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2019 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2020 | return ret; |
2021 | } | |
2022 | ||
2023 | if (old_tss_sel != 0xffff) { | |
2024 | tss_seg.prev_task_link = old_tss_sel; | |
2025 | ||
2026 | ret = ops->write_std(new_tss_base, | |
2027 | &tss_seg.prev_task_link, | |
2028 | sizeof tss_seg.prev_task_link, | |
2029 | ctxt->vcpu, &err); | |
2030 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2031 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2032 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2033 | return ret; |
2034 | } | |
2035 | } | |
2036 | ||
2037 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2038 | } | |
2039 | ||
2040 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2041 | struct x86_emulate_ops *ops, |
2042 | u16 tss_selector, int reason, | |
2043 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2044 | { |
2045 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2046 | int ret; | |
2047 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2048 | ulong old_tss_base = | |
5951c442 | 2049 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2050 | u32 desc_limit; |
38ba30ba GN |
2051 | |
2052 | /* FIXME: old_tss_base == ~0 ? */ | |
2053 | ||
2054 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2055 | if (ret != X86EMUL_CONTINUE) | |
2056 | return ret; | |
2057 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2058 | if (ret != X86EMUL_CONTINUE) | |
2059 | return ret; | |
2060 | ||
2061 | /* FIXME: check that next_tss_desc is tss */ | |
2062 | ||
2063 | if (reason != TASK_SWITCH_IRET) { | |
2064 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2065 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2066 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2067 | return X86EMUL_PROPAGATE_FAULT; |
2068 | } | |
2069 | } | |
2070 | ||
ceffb459 GN |
2071 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2072 | if (!next_tss_desc.p || | |
2073 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2074 | desc_limit < 0x2b)) { | |
54b8486f | 2075 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2076 | return X86EMUL_PROPAGATE_FAULT; |
2077 | } | |
2078 | ||
2079 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2080 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2081 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2082 | &curr_tss_desc); | |
2083 | } | |
2084 | ||
2085 | if (reason == TASK_SWITCH_IRET) | |
2086 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2087 | ||
2088 | /* set back link to prev task only if NT bit is set in eflags | |
2089 | note that old_tss_sel is not used afetr this point */ | |
2090 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2091 | old_tss_sel = 0xffff; | |
2092 | ||
2093 | if (next_tss_desc.type & 8) | |
2094 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2095 | old_tss_base, &next_tss_desc); | |
2096 | else | |
2097 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2098 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2099 | if (ret != X86EMUL_CONTINUE) |
2100 | return ret; | |
38ba30ba GN |
2101 | |
2102 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2103 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2104 | ||
2105 | if (reason != TASK_SWITCH_IRET) { | |
2106 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2107 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2108 | &next_tss_desc); | |
2109 | } | |
2110 | ||
2111 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2112 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2113 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2114 | ||
e269fb21 JK |
2115 | if (has_error_code) { |
2116 | struct decode_cache *c = &ctxt->decode; | |
2117 | ||
2118 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2119 | c->lock_prefix = 0; | |
2120 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2121 | emulate_push(ctxt, ops); |
e269fb21 JK |
2122 | } |
2123 | ||
38ba30ba GN |
2124 | return ret; |
2125 | } | |
2126 | ||
2127 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2128 | u16 tss_selector, int reason, |
2129 | bool has_error_code, u32 error_code) | |
38ba30ba | 2130 | { |
9aabc88f | 2131 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2132 | struct decode_cache *c = &ctxt->decode; |
2133 | int rc; | |
2134 | ||
38ba30ba | 2135 | c->eip = ctxt->eip; |
e269fb21 | 2136 | c->dst.type = OP_NONE; |
38ba30ba | 2137 | |
e269fb21 JK |
2138 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2139 | has_error_code, error_code); | |
38ba30ba GN |
2140 | |
2141 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2142 | rc = writeback(ctxt, ops); |
95c55886 GN |
2143 | if (rc == X86EMUL_CONTINUE) |
2144 | ctxt->eip = c->eip; | |
38ba30ba GN |
2145 | } |
2146 | ||
19d04437 | 2147 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2148 | } |
2149 | ||
a682e354 | 2150 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2151 | int reg, struct operand *op) |
a682e354 GN |
2152 | { |
2153 | struct decode_cache *c = &ctxt->decode; | |
2154 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2155 | ||
d9271123 | 2156 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
1a6440ae | 2157 | op->addr.mem = register_address(c, base, c->regs[reg]); |
a682e354 GN |
2158 | } |
2159 | ||
63540382 AK |
2160 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2161 | { | |
2162 | emulate_push(ctxt, ctxt->ops); | |
2163 | return X86EMUL_CONTINUE; | |
2164 | } | |
2165 | ||
73fba5f4 AK |
2166 | #define D(_y) { .flags = (_y) } |
2167 | #define N D(0) | |
2168 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2169 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2170 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
2171 | ||
2172 | static struct opcode group1[] = { | |
2173 | X7(D(Lock)), N | |
2174 | }; | |
2175 | ||
2176 | static struct opcode group1A[] = { | |
2177 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2178 | }; | |
2179 | ||
2180 | static struct opcode group3[] = { | |
2181 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2182 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2183 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2184 | }; |
2185 | ||
2186 | static struct opcode group4[] = { | |
2187 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2188 | N, N, N, N, N, N, | |
2189 | }; | |
2190 | ||
2191 | static struct opcode group5[] = { | |
2192 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
2193 | D(SrcMem | ModRM | Stack), N, | |
2194 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), | |
2195 | D(SrcMem | ModRM | Stack), N, | |
2196 | }; | |
2197 | ||
2198 | static struct group_dual group7 = { { | |
2199 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2200 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2201 | D(SrcMem16 | ModRM | Mov | Priv), |
2202 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 AK |
2203 | }, { |
2204 | D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv), | |
2205 | D(SrcNone | ModRM | DstMem | Mov), N, | |
2206 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2207 | } }; | |
2208 | ||
2209 | static struct opcode group8[] = { | |
2210 | N, N, N, N, | |
2211 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2212 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2213 | }; | |
2214 | ||
2215 | static struct group_dual group9 = { { | |
2216 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2217 | }, { | |
2218 | N, N, N, N, N, N, N, N, | |
2219 | } }; | |
2220 | ||
2221 | static struct opcode opcode_table[256] = { | |
2222 | /* 0x00 - 0x07 */ | |
2223 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2224 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2225 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2226 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2227 | /* 0x08 - 0x0F */ | |
2228 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2229 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2230 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2231 | D(ImplicitOps | Stack | No64), N, | |
2232 | /* 0x10 - 0x17 */ | |
2233 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2234 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2235 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2236 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2237 | /* 0x18 - 0x1F */ | |
2238 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2239 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2240 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2241 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2242 | /* 0x20 - 0x27 */ | |
2243 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2244 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2245 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2246 | /* 0x28 - 0x2F */ | |
2247 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2248 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2249 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2250 | /* 0x30 - 0x37 */ | |
2251 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2252 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2253 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2254 | /* 0x38 - 0x3F */ | |
2255 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2256 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2257 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2258 | N, N, | |
2259 | /* 0x40 - 0x4F */ | |
2260 | X16(D(DstReg)), | |
2261 | /* 0x50 - 0x57 */ | |
63540382 | 2262 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2263 | /* 0x58 - 0x5F */ |
2264 | X8(D(DstReg | Stack)), | |
2265 | /* 0x60 - 0x67 */ | |
2266 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2267 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2268 | N, N, N, N, | |
2269 | /* 0x68 - 0x6F */ | |
63540382 AK |
2270 | I(SrcImm | Mov | Stack, em_push), N, |
2271 | I(SrcImmByte | Mov | Stack, em_push), N, | |
73fba5f4 AK |
2272 | D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */ |
2273 | D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
2274 | /* 0x70 - 0x7F */ | |
2275 | X16(D(SrcImmByte)), | |
2276 | /* 0x80 - 0x87 */ | |
2277 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2278 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2279 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2280 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
2281 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2282 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2283 | /* 0x88 - 0x8F */ | |
2284 | D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov), | |
2285 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov), | |
342fc630 | 2286 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2287 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2288 | /* 0x90 - 0x97 */ | |
3d9e77df | 2289 | X8(D(SrcAcc | DstReg)), |
73fba5f4 AK |
2290 | /* 0x98 - 0x9F */ |
2291 | N, N, D(SrcImmFAddr | No64), N, | |
2292 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, | |
2293 | /* 0xA0 - 0xA7 */ | |
2294 | D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs), | |
2295 | D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs), | |
2296 | D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String), | |
2297 | D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String), | |
2298 | /* 0xA8 - 0xAF */ | |
06cb7046 WY |
2299 | D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), |
2300 | D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String), | |
73fba5f4 AK |
2301 | D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String), |
2302 | D(ByteOp | DstDI | String), D(DstDI | String), | |
2303 | /* 0xB0 - 0xB7 */ | |
2304 | X8(D(ByteOp | DstReg | SrcImm | Mov)), | |
2305 | /* 0xB8 - 0xBF */ | |
2306 | X8(D(DstReg | SrcImm | Mov)), | |
2307 | /* 0xC0 - 0xC7 */ | |
2308 | D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM), | |
2309 | N, D(ImplicitOps | Stack), N, N, | |
2310 | D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov), | |
2311 | /* 0xC8 - 0xCF */ | |
2312 | N, N, N, D(ImplicitOps | Stack), | |
2313 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2314 | /* 0xD0 - 0xD7 */ | |
c034da8b | 2315 | D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM), |
73fba5f4 AK |
2316 | D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM), |
2317 | N, N, N, N, | |
2318 | /* 0xD8 - 0xDF */ | |
2319 | N, N, N, N, N, N, N, N, | |
2320 | /* 0xE0 - 0xE7 */ | |
2321 | N, N, N, N, | |
2322 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), | |
2323 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), | |
2324 | /* 0xE8 - 0xEF */ | |
2325 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2326 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
2327 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
2328 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
2329 | /* 0xF0 - 0xF7 */ | |
2330 | N, N, N, N, | |
2331 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2332 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2333 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2334 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2335 | }; | |
2336 | ||
2337 | static struct opcode twobyte_table[256] = { | |
2338 | /* 0x00 - 0x0F */ | |
2339 | N, GD(0, &group7), N, N, | |
2340 | N, D(ImplicitOps), D(ImplicitOps | Priv), N, | |
2341 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, | |
2342 | N, D(ImplicitOps | ModRM), N, N, | |
2343 | /* 0x10 - 0x1F */ | |
2344 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2345 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2346 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2347 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2348 | N, N, N, N, |
2349 | N, N, N, N, N, N, N, N, | |
2350 | /* 0x30 - 0x3F */ | |
2351 | D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N, | |
2352 | D(ImplicitOps), D(ImplicitOps | Priv), N, N, | |
2353 | N, N, N, N, N, N, N, N, | |
2354 | /* 0x40 - 0x4F */ | |
2355 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2356 | /* 0x50 - 0x5F */ | |
2357 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2358 | /* 0x60 - 0x6F */ | |
2359 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2360 | /* 0x70 - 0x7F */ | |
2361 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2362 | /* 0x80 - 0x8F */ | |
2363 | X16(D(SrcImm)), | |
2364 | /* 0x90 - 0x9F */ | |
2365 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2366 | /* 0xA0 - 0xA7 */ | |
2367 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2368 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2369 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2370 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2371 | /* 0xA8 - 0xAF */ | |
2372 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2373 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2374 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2375 | D(DstMem | SrcReg | Src2CL | ModRM), | |
2376 | D(ModRM), N, | |
2377 | /* 0xB0 - 0xB7 */ | |
2378 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2379 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2380 | N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov), | |
2381 | D(DstReg | SrcMem16 | ModRM | Mov), | |
2382 | /* 0xB8 - 0xBF */ | |
2383 | N, N, | |
ba7ff2b7 | 2384 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2385 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2386 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2387 | /* 0xC0 - 0xCF */ |
92f738a5 WY |
2388 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), |
2389 | N, D(DstMem | SrcReg | ModRM | Mov), | |
73fba5f4 AK |
2390 | N, N, N, GD(0, &group9), |
2391 | N, N, N, N, N, N, N, N, | |
2392 | /* 0xD0 - 0xDF */ | |
2393 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2394 | /* 0xE0 - 0xEF */ | |
2395 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2396 | /* 0xF0 - 0xFF */ | |
2397 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2398 | }; | |
2399 | ||
2400 | #undef D | |
2401 | #undef N | |
2402 | #undef G | |
2403 | #undef GD | |
2404 | #undef I | |
2405 | ||
dde7e6d1 AK |
2406 | int |
2407 | x86_decode_insn(struct x86_emulate_ctxt *ctxt) | |
2408 | { | |
2409 | struct x86_emulate_ops *ops = ctxt->ops; | |
2410 | struct decode_cache *c = &ctxt->decode; | |
2411 | int rc = X86EMUL_CONTINUE; | |
2412 | int mode = ctxt->mode; | |
2413 | int def_op_bytes, def_ad_bytes, dual, goffset; | |
2414 | struct opcode opcode, *g_mod012, *g_mod3; | |
2dbd0dd7 | 2415 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 AK |
2416 | |
2417 | /* we cannot decode insn before we complete previous rep insn */ | |
2418 | WARN_ON(ctxt->restart); | |
2419 | ||
2420 | c->eip = ctxt->eip; | |
2421 | c->fetch.start = c->fetch.end = c->eip; | |
2422 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); | |
2423 | ||
2424 | switch (mode) { | |
2425 | case X86EMUL_MODE_REAL: | |
2426 | case X86EMUL_MODE_VM86: | |
2427 | case X86EMUL_MODE_PROT16: | |
2428 | def_op_bytes = def_ad_bytes = 2; | |
2429 | break; | |
2430 | case X86EMUL_MODE_PROT32: | |
2431 | def_op_bytes = def_ad_bytes = 4; | |
2432 | break; | |
2433 | #ifdef CONFIG_X86_64 | |
2434 | case X86EMUL_MODE_PROT64: | |
2435 | def_op_bytes = 4; | |
2436 | def_ad_bytes = 8; | |
2437 | break; | |
2438 | #endif | |
2439 | default: | |
2440 | return -1; | |
2441 | } | |
2442 | ||
2443 | c->op_bytes = def_op_bytes; | |
2444 | c->ad_bytes = def_ad_bytes; | |
2445 | ||
2446 | /* Legacy prefixes. */ | |
2447 | for (;;) { | |
2448 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2449 | case 0x66: /* operand-size override */ | |
2450 | /* switch between 2/4 bytes */ | |
2451 | c->op_bytes = def_op_bytes ^ 6; | |
2452 | break; | |
2453 | case 0x67: /* address-size override */ | |
2454 | if (mode == X86EMUL_MODE_PROT64) | |
2455 | /* switch between 4/8 bytes */ | |
2456 | c->ad_bytes = def_ad_bytes ^ 12; | |
2457 | else | |
2458 | /* switch between 2/4 bytes */ | |
2459 | c->ad_bytes = def_ad_bytes ^ 6; | |
2460 | break; | |
2461 | case 0x26: /* ES override */ | |
2462 | case 0x2e: /* CS override */ | |
2463 | case 0x36: /* SS override */ | |
2464 | case 0x3e: /* DS override */ | |
2465 | set_seg_override(c, (c->b >> 3) & 3); | |
2466 | break; | |
2467 | case 0x64: /* FS override */ | |
2468 | case 0x65: /* GS override */ | |
2469 | set_seg_override(c, c->b & 7); | |
2470 | break; | |
2471 | case 0x40 ... 0x4f: /* REX */ | |
2472 | if (mode != X86EMUL_MODE_PROT64) | |
2473 | goto done_prefixes; | |
2474 | c->rex_prefix = c->b; | |
2475 | continue; | |
2476 | case 0xf0: /* LOCK */ | |
2477 | c->lock_prefix = 1; | |
2478 | break; | |
2479 | case 0xf2: /* REPNE/REPNZ */ | |
2480 | c->rep_prefix = REPNE_PREFIX; | |
2481 | break; | |
2482 | case 0xf3: /* REP/REPE/REPZ */ | |
2483 | c->rep_prefix = REPE_PREFIX; | |
2484 | break; | |
2485 | default: | |
2486 | goto done_prefixes; | |
2487 | } | |
2488 | ||
2489 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2490 | ||
2491 | c->rex_prefix = 0; | |
2492 | } | |
2493 | ||
2494 | done_prefixes: | |
2495 | ||
2496 | /* REX prefix. */ | |
1e87e3ef AK |
2497 | if (c->rex_prefix & 8) |
2498 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2499 | |
2500 | /* Opcode byte(s). */ | |
2501 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2502 | /* Two-byte opcode? */ |
2503 | if (c->b == 0x0f) { | |
2504 | c->twobyte = 1; | |
2505 | c->b = insn_fetch(u8, 1, c->eip); | |
2506 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2507 | } |
2508 | c->d = opcode.flags; | |
2509 | ||
2510 | if (c->d & Group) { | |
2511 | dual = c->d & GroupDual; | |
2512 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2513 | --c->eip; | |
2514 | ||
2515 | if (c->d & GroupDual) { | |
2516 | g_mod012 = opcode.u.gdual->mod012; | |
2517 | g_mod3 = opcode.u.gdual->mod3; | |
2518 | } else | |
2519 | g_mod012 = g_mod3 = opcode.u.group; | |
2520 | ||
2521 | c->d &= ~(Group | GroupDual); | |
2522 | ||
2523 | goffset = (c->modrm >> 3) & 7; | |
2524 | ||
2525 | if ((c->modrm >> 6) == 3) | |
2526 | opcode = g_mod3[goffset]; | |
2527 | else | |
2528 | opcode = g_mod012[goffset]; | |
2529 | c->d |= opcode.flags; | |
2530 | } | |
2531 | ||
2532 | c->execute = opcode.u.execute; | |
2533 | ||
2534 | /* Unrecognised? */ | |
2535 | if (c->d == 0 || (c->d & Undefined)) { | |
2536 | DPRINTF("Cannot emulate %02x\n", c->b); | |
2537 | return -1; | |
2538 | } | |
2539 | ||
2540 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) | |
2541 | c->op_bytes = 8; | |
2542 | ||
7f9b4b75 AK |
2543 | if (c->d & Op3264) { |
2544 | if (mode == X86EMUL_MODE_PROT64) | |
2545 | c->op_bytes = 8; | |
2546 | else | |
2547 | c->op_bytes = 4; | |
2548 | } | |
2549 | ||
dde7e6d1 | 2550 | /* ModRM and SIB bytes. */ |
09ee57cd | 2551 | if (c->d & ModRM) { |
2dbd0dd7 | 2552 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2553 | if (!c->has_seg_override) |
2554 | set_seg_override(c, c->modrm_seg); | |
2555 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2556 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2557 | if (rc != X86EMUL_CONTINUE) |
2558 | goto done; | |
2559 | ||
2560 | if (!c->has_seg_override) | |
2561 | set_seg_override(c, VCPU_SREG_DS); | |
2562 | ||
2dbd0dd7 AK |
2563 | if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d)) |
2564 | memop.addr.mem += seg_override_base(ctxt, ops, c); | |
dde7e6d1 | 2565 | |
2dbd0dd7 AK |
2566 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
2567 | memop.addr.mem = (u32)memop.addr.mem; | |
dde7e6d1 | 2568 | |
2dbd0dd7 AK |
2569 | if (memop.type == OP_MEM && c->rip_relative) |
2570 | memop.addr.mem += c->eip; | |
dde7e6d1 AK |
2571 | |
2572 | /* | |
2573 | * Decode and fetch the source operand: register, memory | |
2574 | * or immediate. | |
2575 | */ | |
2576 | switch (c->d & SrcMask) { | |
2577 | case SrcNone: | |
2578 | break; | |
2579 | case SrcReg: | |
2580 | decode_register_operand(&c->src, c, 0); | |
2581 | break; | |
2582 | case SrcMem16: | |
2dbd0dd7 | 2583 | memop.bytes = 2; |
dde7e6d1 AK |
2584 | goto srcmem_common; |
2585 | case SrcMem32: | |
2dbd0dd7 | 2586 | memop.bytes = 4; |
dde7e6d1 AK |
2587 | goto srcmem_common; |
2588 | case SrcMem: | |
2dbd0dd7 | 2589 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2590 | c->op_bytes; |
dde7e6d1 | 2591 | srcmem_common: |
2dbd0dd7 | 2592 | c->src = memop; |
dde7e6d1 AK |
2593 | break; |
2594 | case SrcImm: | |
2595 | case SrcImmU: | |
2596 | c->src.type = OP_IMM; | |
1a6440ae | 2597 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2598 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
2599 | if (c->src.bytes == 8) | |
2600 | c->src.bytes = 4; | |
2601 | /* NB. Immediates are sign-extended as necessary. */ | |
2602 | switch (c->src.bytes) { | |
2603 | case 1: | |
2604 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2605 | break; | |
2606 | case 2: | |
2607 | c->src.val = insn_fetch(s16, 2, c->eip); | |
2608 | break; | |
2609 | case 4: | |
2610 | c->src.val = insn_fetch(s32, 4, c->eip); | |
2611 | break; | |
2612 | } | |
2613 | if ((c->d & SrcMask) == SrcImmU) { | |
2614 | switch (c->src.bytes) { | |
2615 | case 1: | |
2616 | c->src.val &= 0xff; | |
2617 | break; | |
2618 | case 2: | |
2619 | c->src.val &= 0xffff; | |
2620 | break; | |
2621 | case 4: | |
2622 | c->src.val &= 0xffffffff; | |
2623 | break; | |
2624 | } | |
2625 | } | |
2626 | break; | |
2627 | case SrcImmByte: | |
2628 | case SrcImmUByte: | |
2629 | c->src.type = OP_IMM; | |
1a6440ae | 2630 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2631 | c->src.bytes = 1; |
2632 | if ((c->d & SrcMask) == SrcImmByte) | |
2633 | c->src.val = insn_fetch(s8, 1, c->eip); | |
2634 | else | |
2635 | c->src.val = insn_fetch(u8, 1, c->eip); | |
2636 | break; | |
2637 | case SrcAcc: | |
2638 | c->src.type = OP_REG; | |
2639 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2640 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2641 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2642 | break; |
2643 | case SrcOne: | |
2644 | c->src.bytes = 1; | |
2645 | c->src.val = 1; | |
2646 | break; | |
2647 | case SrcSI: | |
2648 | c->src.type = OP_MEM; | |
2649 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2650 | c->src.addr.mem = |
dde7e6d1 AK |
2651 | register_address(c, seg_override_base(ctxt, ops, c), |
2652 | c->regs[VCPU_REGS_RSI]); | |
2653 | c->src.val = 0; | |
2654 | break; | |
2655 | case SrcImmFAddr: | |
2656 | c->src.type = OP_IMM; | |
1a6440ae | 2657 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2658 | c->src.bytes = c->op_bytes + 2; |
2659 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2660 | break; | |
2661 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2662 | memop.bytes = c->op_bytes + 2; |
2663 | goto srcmem_common; | |
dde7e6d1 AK |
2664 | break; |
2665 | } | |
2666 | ||
2667 | /* | |
2668 | * Decode and fetch the second source operand: register, memory | |
2669 | * or immediate. | |
2670 | */ | |
2671 | switch (c->d & Src2Mask) { | |
2672 | case Src2None: | |
2673 | break; | |
2674 | case Src2CL: | |
2675 | c->src2.bytes = 1; | |
2676 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2677 | break; | |
2678 | case Src2ImmByte: | |
2679 | c->src2.type = OP_IMM; | |
1a6440ae | 2680 | c->src2.addr.mem = c->eip; |
dde7e6d1 AK |
2681 | c->src2.bytes = 1; |
2682 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
2683 | break; | |
2684 | case Src2One: | |
2685 | c->src2.bytes = 1; | |
2686 | c->src2.val = 1; | |
2687 | break; | |
2688 | } | |
2689 | ||
2690 | /* Decode and fetch the destination operand: register or memory. */ | |
2691 | switch (c->d & DstMask) { | |
dde7e6d1 AK |
2692 | case DstReg: |
2693 | decode_register_operand(&c->dst, c, | |
2694 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); | |
2695 | break; | |
2696 | case DstMem: | |
2697 | case DstMem64: | |
2dbd0dd7 | 2698 | c->dst = memop; |
dde7e6d1 AK |
2699 | if ((c->d & DstMask) == DstMem64) |
2700 | c->dst.bytes = 8; | |
2701 | else | |
2702 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
2703 | if (c->d & BitOp) |
2704 | fetch_bit_operand(c); | |
2dbd0dd7 | 2705 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
2706 | break; |
2707 | case DstAcc: | |
2708 | c->dst.type = OP_REG; | |
2709 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2710 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2711 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
2712 | c->dst.orig_val = c->dst.val; |
2713 | break; | |
2714 | case DstDI: | |
2715 | c->dst.type = OP_MEM; | |
2716 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2717 | c->dst.addr.mem = |
dde7e6d1 AK |
2718 | register_address(c, es_base(ctxt, ops), |
2719 | c->regs[VCPU_REGS_RDI]); | |
2720 | c->dst.val = 0; | |
2721 | break; | |
36089fed WY |
2722 | case ImplicitOps: |
2723 | /* Special instructions do their own operand decoding. */ | |
2724 | default: | |
2725 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2726 | return 0; | |
dde7e6d1 AK |
2727 | } |
2728 | ||
2729 | done: | |
2730 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
2731 | } | |
2732 | ||
8b4caf66 | 2733 | int |
9aabc88f | 2734 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 2735 | { |
9aabc88f | 2736 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 2737 | u64 msr_data; |
8b4caf66 | 2738 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2739 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2740 | int saved_dst_type = c->dst.type; |
6e154e56 | 2741 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 2742 | |
9de41573 | 2743 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2744 | |
1161624f | 2745 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2746 | emulate_ud(ctxt); |
1161624f GN |
2747 | goto done; |
2748 | } | |
2749 | ||
d380a5e4 | 2750 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2751 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2752 | emulate_ud(ctxt); |
d380a5e4 GN |
2753 | goto done; |
2754 | } | |
2755 | ||
e92805ac | 2756 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2757 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 2758 | emulate_gp(ctxt, 0); |
e92805ac GN |
2759 | goto done; |
2760 | } | |
2761 | ||
b9fa9d6b | 2762 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2763 | ctxt->restart = true; |
b9fa9d6b | 2764 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2765 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 GN |
2766 | string_done: |
2767 | ctxt->restart = false; | |
95c55886 | 2768 | ctxt->eip = c->eip; |
b9fa9d6b AK |
2769 | goto done; |
2770 | } | |
2771 | /* The second termination condition only applies for REPE | |
2772 | * and REPNE. Test if the repeat string operation prefix is | |
2773 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2774 | * corresponding termination condition according to: | |
2775 | * - if REPE/REPZ and ZF = 0 then done | |
2776 | * - if REPNE/REPNZ and ZF = 1 then done | |
2777 | */ | |
2778 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
5cd21917 | 2779 | (c->b == 0xae) || (c->b == 0xaf)) { |
b9fa9d6b | 2780 | if ((c->rep_prefix == REPE_PREFIX) && |
5cd21917 GN |
2781 | ((ctxt->eflags & EFLG_ZF) == 0)) |
2782 | goto string_done; | |
b9fa9d6b | 2783 | if ((c->rep_prefix == REPNE_PREFIX) && |
5cd21917 GN |
2784 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) |
2785 | goto string_done; | |
b9fa9d6b | 2786 | } |
063db061 | 2787 | c->eip = ctxt->eip; |
b9fa9d6b AK |
2788 | } |
2789 | ||
8b4caf66 | 2790 | if (c->src.type == OP_MEM) { |
2dbd0dd7 AK |
2791 | if (c->d & NoAccess) |
2792 | goto no_fetch; | |
1a6440ae | 2793 | rc = read_emulated(ctxt, ops, c->src.addr.mem, |
414e6277 | 2794 | c->src.valptr, c->src.bytes); |
b60d513c | 2795 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 2796 | goto done; |
16518d5a | 2797 | c->src.orig_val64 = c->src.val64; |
2dbd0dd7 AK |
2798 | no_fetch: |
2799 | ; | |
8b4caf66 LV |
2800 | } |
2801 | ||
e35b7b9c | 2802 | if (c->src2.type == OP_MEM) { |
1a6440ae | 2803 | rc = read_emulated(ctxt, ops, c->src2.addr.mem, |
9de41573 | 2804 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
2805 | if (rc != X86EMUL_CONTINUE) |
2806 | goto done; | |
2807 | } | |
2808 | ||
8b4caf66 LV |
2809 | if ((c->d & DstMask) == ImplicitOps) |
2810 | goto special_insn; | |
2811 | ||
2812 | ||
69f55cb1 GN |
2813 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2814 | /* optimisation - avoid slow emulated read if Mov */ | |
1a6440ae | 2815 | rc = read_emulated(ctxt, ops, c->dst.addr.mem, |
9de41573 | 2816 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
2817 | if (rc != X86EMUL_CONTINUE) |
2818 | goto done; | |
038e51de | 2819 | } |
e4e03ded | 2820 | c->dst.orig_val = c->dst.val; |
038e51de | 2821 | |
018a98db AK |
2822 | special_insn: |
2823 | ||
ef65c889 AK |
2824 | if (c->execute) { |
2825 | rc = c->execute(ctxt); | |
2826 | if (rc != X86EMUL_CONTINUE) | |
2827 | goto done; | |
2828 | goto writeback; | |
2829 | } | |
2830 | ||
e4e03ded | 2831 | if (c->twobyte) |
6aa8b732 AK |
2832 | goto twobyte_insn; |
2833 | ||
e4e03ded | 2834 | switch (c->b) { |
6aa8b732 AK |
2835 | case 0x00 ... 0x05: |
2836 | add: /* add */ | |
05f086f8 | 2837 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2838 | break; |
0934ac9d | 2839 | case 0x06: /* push es */ |
79168fd1 | 2840 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
2841 | break; |
2842 | case 0x07: /* pop es */ | |
0934ac9d | 2843 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2844 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2845 | goto done; |
2846 | break; | |
6aa8b732 AK |
2847 | case 0x08 ... 0x0d: |
2848 | or: /* or */ | |
05f086f8 | 2849 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2850 | break; |
0934ac9d | 2851 | case 0x0e: /* push cs */ |
79168fd1 | 2852 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 2853 | break; |
6aa8b732 AK |
2854 | case 0x10 ... 0x15: |
2855 | adc: /* adc */ | |
05f086f8 | 2856 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2857 | break; |
0934ac9d | 2858 | case 0x16: /* push ss */ |
79168fd1 | 2859 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
2860 | break; |
2861 | case 0x17: /* pop ss */ | |
0934ac9d | 2862 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2863 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2864 | goto done; |
2865 | break; | |
6aa8b732 AK |
2866 | case 0x18 ... 0x1d: |
2867 | sbb: /* sbb */ | |
05f086f8 | 2868 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2869 | break; |
0934ac9d | 2870 | case 0x1e: /* push ds */ |
79168fd1 | 2871 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
2872 | break; |
2873 | case 0x1f: /* pop ds */ | |
0934ac9d | 2874 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2875 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2876 | goto done; |
2877 | break; | |
aa3a816b | 2878 | case 0x20 ... 0x25: |
6aa8b732 | 2879 | and: /* and */ |
05f086f8 | 2880 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2881 | break; |
2882 | case 0x28 ... 0x2d: | |
2883 | sub: /* sub */ | |
05f086f8 | 2884 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2885 | break; |
2886 | case 0x30 ... 0x35: | |
2887 | xor: /* xor */ | |
05f086f8 | 2888 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2889 | break; |
2890 | case 0x38 ... 0x3d: | |
2891 | cmp: /* cmp */ | |
05f086f8 | 2892 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2893 | break; |
33615aa9 AK |
2894 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2895 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2896 | break; | |
2897 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2898 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2899 | break; | |
33615aa9 AK |
2900 | case 0x58 ... 0x5f: /* pop reg */ |
2901 | pop_instruction: | |
350f69dc | 2902 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2903 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2904 | goto done; |
33615aa9 | 2905 | break; |
abcf14b5 | 2906 | case 0x60: /* pusha */ |
c37eda13 WY |
2907 | rc = emulate_pusha(ctxt, ops); |
2908 | if (rc != X86EMUL_CONTINUE) | |
2909 | goto done; | |
abcf14b5 MG |
2910 | break; |
2911 | case 0x61: /* popa */ | |
2912 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2913 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2914 | goto done; |
2915 | break; | |
6aa8b732 | 2916 | case 0x63: /* movsxd */ |
8b4caf66 | 2917 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2918 | goto cannot_emulate; |
e4e03ded | 2919 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2920 | break; |
018a98db AK |
2921 | case 0x6c: /* insb */ |
2922 | case 0x6d: /* insw/insd */ | |
7972995b | 2923 | c->dst.bytes = min(c->dst.bytes, 4u); |
f850e2e6 | 2924 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2925 | c->dst.bytes)) { |
54b8486f | 2926 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2927 | goto done; |
2928 | } | |
7b262e90 GN |
2929 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, |
2930 | c->regs[VCPU_REGS_RDX], &c->dst.val)) | |
7972995b GN |
2931 | goto done; /* IO is needed, skip writeback */ |
2932 | break; | |
018a98db AK |
2933 | case 0x6e: /* outsb */ |
2934 | case 0x6f: /* outsw/outsd */ | |
7972995b | 2935 | c->src.bytes = min(c->src.bytes, 4u); |
f850e2e6 | 2936 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2937 | c->src.bytes)) { |
54b8486f | 2938 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2939 | goto done; |
2940 | } | |
7972995b GN |
2941 | ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], |
2942 | &c->src.val, 1, ctxt->vcpu); | |
2943 | ||
2944 | c->dst.type = OP_NONE; /* nothing to writeback */ | |
2945 | break; | |
b2833e3c | 2946 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2947 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2948 | jmp_rel(c, c->src.val); |
018a98db | 2949 | break; |
6aa8b732 | 2950 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2951 | switch (c->modrm_reg) { |
6aa8b732 AK |
2952 | case 0: |
2953 | goto add; | |
2954 | case 1: | |
2955 | goto or; | |
2956 | case 2: | |
2957 | goto adc; | |
2958 | case 3: | |
2959 | goto sbb; | |
2960 | case 4: | |
2961 | goto and; | |
2962 | case 5: | |
2963 | goto sub; | |
2964 | case 6: | |
2965 | goto xor; | |
2966 | case 7: | |
2967 | goto cmp; | |
2968 | } | |
2969 | break; | |
2970 | case 0x84 ... 0x85: | |
dfb507c4 | 2971 | test: |
05f086f8 | 2972 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2973 | break; |
2974 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2975 | xchg: |
6aa8b732 | 2976 | /* Write back the register source. */ |
31be40b3 WY |
2977 | c->src.val = c->dst.val; |
2978 | write_register_operand(&c->src); | |
6aa8b732 AK |
2979 | /* |
2980 | * Write back the memory destination with implicit LOCK | |
2981 | * prefix. | |
2982 | */ | |
31be40b3 | 2983 | c->dst.val = c->src.orig_val; |
e4e03ded | 2984 | c->lock_prefix = 1; |
6aa8b732 | 2985 | break; |
6aa8b732 | 2986 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2987 | goto mov; |
79168fd1 GN |
2988 | case 0x8c: /* mov r/m, sreg */ |
2989 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 2990 | emulate_ud(ctxt); |
5e3ae6c5 | 2991 | goto done; |
38d5bc6d | 2992 | } |
79168fd1 | 2993 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 2994 | break; |
7e0b54b1 | 2995 | case 0x8d: /* lea r16/r32, m */ |
342fc630 | 2996 | c->dst.val = c->src.addr.mem; |
7e0b54b1 | 2997 | break; |
4257198a GT |
2998 | case 0x8e: { /* mov seg, r/m16 */ |
2999 | uint16_t sel; | |
4257198a GT |
3000 | |
3001 | sel = c->src.val; | |
8b9f4414 | 3002 | |
c697518a GN |
3003 | if (c->modrm_reg == VCPU_SREG_CS || |
3004 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3005 | emulate_ud(ctxt); |
8b9f4414 GN |
3006 | goto done; |
3007 | } | |
3008 | ||
310b5d30 | 3009 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3010 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3011 | |
2e873022 | 3012 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3013 | |
3014 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3015 | break; | |
3016 | } | |
6aa8b732 | 3017 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3018 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 3019 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 3020 | goto done; |
6aa8b732 | 3021 | break; |
3d9e77df AK |
3022 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3023 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3024 | break; |
b13354f8 | 3025 | goto xchg; |
fd2a7608 | 3026 | case 0x9c: /* pushf */ |
05f086f8 | 3027 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3028 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3029 | break; |
535eabcf | 3030 | case 0x9d: /* popf */ |
2b48cc75 | 3031 | c->dst.type = OP_REG; |
1a6440ae | 3032 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3033 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
3034 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
3035 | if (rc != X86EMUL_CONTINUE) | |
3036 | goto done; | |
3037 | break; | |
5d55f299 | 3038 | case 0xa0 ... 0xa3: /* mov */ |
6aa8b732 | 3039 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 3040 | goto mov; |
6aa8b732 | 3041 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3042 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a6440ae | 3043 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem); |
a682e354 | 3044 | goto cmp; |
dfb507c4 MG |
3045 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3046 | goto test; | |
6aa8b732 | 3047 | case 0xaa ... 0xab: /* stos */ |
6aa8b732 | 3048 | case 0xac ... 0xad: /* lods */ |
a682e354 | 3049 | goto mov; |
6aa8b732 AK |
3050 | case 0xae ... 0xaf: /* scas */ |
3051 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
3052 | goto cannot_emulate; | |
a5e2e82b | 3053 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 3054 | goto mov; |
018a98db AK |
3055 | case 0xc0 ... 0xc1: |
3056 | emulate_grp2(ctxt); | |
3057 | break; | |
111de5d6 | 3058 | case 0xc3: /* ret */ |
cf5de4f8 | 3059 | c->dst.type = OP_REG; |
1a6440ae | 3060 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3061 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3062 | goto pop_instruction; |
018a98db AK |
3063 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
3064 | mov: | |
3065 | c->dst.val = c->src.val; | |
3066 | break; | |
a77ab5ea AK |
3067 | case 0xcb: /* ret far */ |
3068 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e MG |
3069 | if (rc != X86EMUL_CONTINUE) |
3070 | goto done; | |
3071 | break; | |
6e154e56 MG |
3072 | case 0xcc: /* int3 */ |
3073 | irq = 3; | |
3074 | goto do_interrupt; | |
3075 | case 0xcd: /* int n */ | |
3076 | irq = c->src.val; | |
3077 | do_interrupt: | |
3078 | rc = emulate_int(ctxt, ops, irq); | |
3079 | if (rc != X86EMUL_CONTINUE) | |
3080 | goto done; | |
3081 | break; | |
3082 | case 0xce: /* into */ | |
3083 | if (ctxt->eflags & EFLG_OF) { | |
3084 | irq = 4; | |
3085 | goto do_interrupt; | |
3086 | } | |
3087 | break; | |
62bd430e MG |
3088 | case 0xcf: /* iret */ |
3089 | rc = emulate_iret(ctxt, ops); | |
3090 | ||
1b30eaa8 | 3091 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
3092 | goto done; |
3093 | break; | |
018a98db | 3094 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3095 | emulate_grp2(ctxt); |
3096 | break; | |
3097 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3098 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3099 | emulate_grp2(ctxt); | |
3100 | break; | |
a6a3034c MG |
3101 | case 0xe4: /* inb */ |
3102 | case 0xe5: /* in */ | |
cf8f70bf | 3103 | goto do_io_in; |
a6a3034c MG |
3104 | case 0xe6: /* outb */ |
3105 | case 0xe7: /* out */ | |
cf8f70bf | 3106 | goto do_io_out; |
1a52e051 | 3107 | case 0xe8: /* call (near) */ { |
d53c4777 | 3108 | long int rel = c->src.val; |
e4e03ded | 3109 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3110 | jmp_rel(c, rel); |
79168fd1 | 3111 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3112 | break; |
1a52e051 NK |
3113 | } |
3114 | case 0xe9: /* jmp rel */ | |
954cd36f | 3115 | goto jmp; |
414e6277 GN |
3116 | case 0xea: { /* jmp far */ |
3117 | unsigned short sel; | |
ea79849d | 3118 | jump_far: |
414e6277 GN |
3119 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3120 | ||
3121 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3122 | goto done; |
954cd36f | 3123 | |
414e6277 GN |
3124 | c->eip = 0; |
3125 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3126 | break; |
414e6277 | 3127 | } |
954cd36f GT |
3128 | case 0xeb: |
3129 | jmp: /* jmp rel short */ | |
7a957275 | 3130 | jmp_rel(c, c->src.val); |
a01af5ec | 3131 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3132 | break; |
a6a3034c MG |
3133 | case 0xec: /* in al,dx */ |
3134 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3135 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3136 | do_io_in: | |
3137 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3138 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3139 | emulate_gp(ctxt, 0); |
cf8f70bf GN |
3140 | goto done; |
3141 | } | |
7b262e90 GN |
3142 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3143 | &c->dst.val)) | |
cf8f70bf GN |
3144 | goto done; /* IO is needed */ |
3145 | break; | |
ce7a0ad3 WY |
3146 | case 0xee: /* out dx,al */ |
3147 | case 0xef: /* out dx,(e/r)ax */ | |
cf8f70bf GN |
3148 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3149 | do_io_out: | |
3150 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3151 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3152 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
3153 | goto done; |
3154 | } | |
cf8f70bf GN |
3155 | ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, |
3156 | ctxt->vcpu); | |
3157 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 3158 | break; |
111de5d6 | 3159 | case 0xf4: /* hlt */ |
ad312c7c | 3160 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3161 | break; |
111de5d6 AK |
3162 | case 0xf5: /* cmc */ |
3163 | /* complement carry flag from eflags reg */ | |
3164 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3165 | break; |
018a98db | 3166 | case 0xf6 ... 0xf7: /* Grp3 */ |
8c5eee30 | 3167 | if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE) |
aca06a83 | 3168 | goto cannot_emulate; |
018a98db | 3169 | break; |
111de5d6 AK |
3170 | case 0xf8: /* clc */ |
3171 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3172 | break; |
8744aa9a MG |
3173 | case 0xf9: /* stc */ |
3174 | ctxt->eflags |= EFLG_CF; | |
3175 | break; | |
111de5d6 | 3176 | case 0xfa: /* cli */ |
07cbc6c1 | 3177 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3178 | emulate_gp(ctxt, 0); |
07cbc6c1 | 3179 | goto done; |
36089fed | 3180 | } else |
f850e2e6 | 3181 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3182 | break; |
3183 | case 0xfb: /* sti */ | |
07cbc6c1 | 3184 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3185 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3186 | goto done; |
3187 | } else { | |
95cb2295 | 3188 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3189 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3190 | } |
111de5d6 | 3191 | break; |
fb4616f4 MG |
3192 | case 0xfc: /* cld */ |
3193 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3194 | break; |
3195 | case 0xfd: /* std */ | |
3196 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3197 | break; |
ea79849d GN |
3198 | case 0xfe: /* Grp4 */ |
3199 | grp45: | |
018a98db | 3200 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 3201 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3202 | goto done; |
3203 | break; | |
ea79849d GN |
3204 | case 0xff: /* Grp5 */ |
3205 | if (c->modrm_reg == 5) | |
3206 | goto jump_far; | |
3207 | goto grp45; | |
91269b8f AK |
3208 | default: |
3209 | goto cannot_emulate; | |
6aa8b732 | 3210 | } |
018a98db AK |
3211 | |
3212 | writeback: | |
3213 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3214 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3215 | goto done; |
3216 | ||
5cd21917 GN |
3217 | /* |
3218 | * restore dst type in case the decoding will be reused | |
3219 | * (happens for string instruction ) | |
3220 | */ | |
3221 | c->dst.type = saved_dst_type; | |
3222 | ||
a682e354 | 3223 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3224 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3225 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3226 | |
3227 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3228 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3229 | &c->dst); | |
d9271123 | 3230 | |
5cd21917 | 3231 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3232 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3233 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
7b262e90 GN |
3234 | /* |
3235 | * Re-enter guest when pio read ahead buffer is empty or, | |
3236 | * if it is not used, after each 1024 iteration. | |
3237 | */ | |
3238 | if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || | |
3239 | (rc->end != 0 && rc->end == rc->pos)) | |
5cd21917 GN |
3240 | ctxt->restart = false; |
3241 | } | |
9de41573 GN |
3242 | /* |
3243 | * reset read cache here in case string instruction is restared | |
3244 | * without decoding | |
3245 | */ | |
3246 | ctxt->decode.mem_read.end = 0; | |
95c55886 | 3247 | ctxt->eip = c->eip; |
018a98db AK |
3248 | |
3249 | done: | |
cb404fe0 | 3250 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3251 | |
3252 | twobyte_insn: | |
e4e03ded | 3253 | switch (c->b) { |
6aa8b732 | 3254 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3255 | switch (c->modrm_reg) { |
6aa8b732 AK |
3256 | u16 size; |
3257 | unsigned long address; | |
3258 | ||
aca7f966 | 3259 | case 0: /* vmcall */ |
e4e03ded | 3260 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3261 | goto cannot_emulate; |
3262 | ||
7aa81cc0 | 3263 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3264 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3265 | goto done; |
3266 | ||
33e3885d | 3267 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3268 | c->eip = ctxt->eip; |
16286d08 AK |
3269 | /* Disable writeback. */ |
3270 | c->dst.type = OP_NONE; | |
aca7f966 | 3271 | break; |
6aa8b732 | 3272 | case 2: /* lgdt */ |
1a6440ae | 3273 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3274 | &size, &address, c->op_bytes); |
1b30eaa8 | 3275 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3276 | goto done; |
3277 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3278 | /* Disable writeback. */ |
3279 | c->dst.type = OP_NONE; | |
6aa8b732 | 3280 | break; |
aca7f966 | 3281 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3282 | if (c->modrm_mod == 3) { |
3283 | switch (c->modrm_rm) { | |
3284 | case 1: | |
3285 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3286 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3287 | goto done; |
3288 | break; | |
3289 | default: | |
3290 | goto cannot_emulate; | |
3291 | } | |
aca7f966 | 3292 | } else { |
1a6440ae | 3293 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3294 | &size, &address, |
e4e03ded | 3295 | c->op_bytes); |
1b30eaa8 | 3296 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3297 | goto done; |
3298 | realmode_lidt(ctxt->vcpu, size, address); | |
3299 | } | |
16286d08 AK |
3300 | /* Disable writeback. */ |
3301 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3302 | break; |
3303 | case 4: /* smsw */ | |
16286d08 | 3304 | c->dst.bytes = 2; |
52a46617 | 3305 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3306 | break; |
3307 | case 6: /* lmsw */ | |
9928ff60 | 3308 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3309 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3310 | c->dst.type = OP_NONE; |
6aa8b732 | 3311 | break; |
6e1e5ffe | 3312 | case 5: /* not defined */ |
54b8486f | 3313 | emulate_ud(ctxt); |
6e1e5ffe | 3314 | goto done; |
6aa8b732 | 3315 | case 7: /* invlpg*/ |
1f6f0580 | 3316 | emulate_invlpg(ctxt->vcpu, c->src.addr.mem); |
16286d08 AK |
3317 | /* Disable writeback. */ |
3318 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3319 | break; |
3320 | default: | |
3321 | goto cannot_emulate; | |
3322 | } | |
3323 | break; | |
e99f0507 | 3324 | case 0x05: /* syscall */ |
3fb1b5db | 3325 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3326 | if (rc != X86EMUL_CONTINUE) |
3327 | goto done; | |
e66bb2cc AP |
3328 | else |
3329 | goto writeback; | |
e99f0507 | 3330 | break; |
018a98db AK |
3331 | case 0x06: |
3332 | emulate_clts(ctxt->vcpu); | |
018a98db | 3333 | break; |
018a98db | 3334 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3335 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3336 | break; |
3337 | case 0x08: /* invd */ | |
018a98db AK |
3338 | case 0x0d: /* GrpP (prefetch) */ |
3339 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3340 | break; |
3341 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3342 | switch (c->modrm_reg) { |
3343 | case 1: | |
3344 | case 5 ... 7: | |
3345 | case 9 ... 15: | |
54b8486f | 3346 | emulate_ud(ctxt); |
6aebfa6e GN |
3347 | goto done; |
3348 | } | |
1a0c7d44 | 3349 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3350 | break; |
6aa8b732 | 3351 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3352 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3353 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3354 | emulate_ud(ctxt); |
1e470be5 GN |
3355 | goto done; |
3356 | } | |
b27f3856 | 3357 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3358 | break; |
018a98db | 3359 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3360 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3361 | emulate_gp(ctxt, 0); |
0f12244f GN |
3362 | goto done; |
3363 | } | |
018a98db AK |
3364 | c->dst.type = OP_NONE; |
3365 | break; | |
6aa8b732 | 3366 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3367 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3368 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3369 | emulate_ud(ctxt); |
1e470be5 GN |
3370 | goto done; |
3371 | } | |
35aa5375 | 3372 | |
b27f3856 | 3373 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3374 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3375 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3376 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3377 | emulate_gp(ctxt, 0); |
338dbc97 GN |
3378 | goto done; |
3379 | } | |
3380 | ||
a01af5ec | 3381 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3382 | break; |
018a98db AK |
3383 | case 0x30: |
3384 | /* wrmsr */ | |
3385 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3386 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3387 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3388 | emulate_gp(ctxt, 0); |
fd525365 | 3389 | goto done; |
018a98db AK |
3390 | } |
3391 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3392 | break; |
3393 | case 0x32: | |
3394 | /* rdmsr */ | |
3fb1b5db | 3395 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3396 | emulate_gp(ctxt, 0); |
fd525365 | 3397 | goto done; |
018a98db AK |
3398 | } else { |
3399 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3400 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3401 | } | |
3402 | rc = X86EMUL_CONTINUE; | |
018a98db | 3403 | break; |
e99f0507 | 3404 | case 0x34: /* sysenter */ |
3fb1b5db | 3405 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3406 | if (rc != X86EMUL_CONTINUE) |
3407 | goto done; | |
8c604352 AP |
3408 | else |
3409 | goto writeback; | |
e99f0507 AP |
3410 | break; |
3411 | case 0x35: /* sysexit */ | |
3fb1b5db | 3412 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3413 | if (rc != X86EMUL_CONTINUE) |
3414 | goto done; | |
4668f050 AP |
3415 | else |
3416 | goto writeback; | |
e99f0507 | 3417 | break; |
6aa8b732 | 3418 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3419 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3420 | if (!test_cc(c->b, ctxt->eflags)) |
3421 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3422 | break; |
b2833e3c | 3423 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3424 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3425 | jmp_rel(c, c->src.val); |
018a98db | 3426 | break; |
0934ac9d | 3427 | case 0xa0: /* push fs */ |
79168fd1 | 3428 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3429 | break; |
3430 | case 0xa1: /* pop fs */ | |
3431 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3432 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3433 | goto done; |
3434 | break; | |
7de75248 NK |
3435 | case 0xa3: |
3436 | bt: /* bt */ | |
e4f8e039 | 3437 | c->dst.type = OP_NONE; |
e4e03ded LV |
3438 | /* only subword offset */ |
3439 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3440 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3441 | break; |
9bf8ea42 GT |
3442 | case 0xa4: /* shld imm8, r, r/m */ |
3443 | case 0xa5: /* shld cl, r, r/m */ | |
3444 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3445 | break; | |
0934ac9d | 3446 | case 0xa8: /* push gs */ |
79168fd1 | 3447 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3448 | break; |
3449 | case 0xa9: /* pop gs */ | |
3450 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3451 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3452 | goto done; |
3453 | break; | |
7de75248 NK |
3454 | case 0xab: |
3455 | bts: /* bts */ | |
05f086f8 | 3456 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3457 | break; |
9bf8ea42 GT |
3458 | case 0xac: /* shrd imm8, r, r/m */ |
3459 | case 0xad: /* shrd cl, r, r/m */ | |
3460 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3461 | break; | |
2a7c5b8b GC |
3462 | case 0xae: /* clflush */ |
3463 | break; | |
6aa8b732 AK |
3464 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3465 | /* | |
3466 | * Save real source value, then compare EAX against | |
3467 | * destination. | |
3468 | */ | |
e4e03ded LV |
3469 | c->src.orig_val = c->src.val; |
3470 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3471 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3472 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3473 | /* Success: write back to memory. */ |
e4e03ded | 3474 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3475 | } else { |
3476 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3477 | c->dst.type = OP_REG; |
1a6440ae | 3478 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3479 | } |
3480 | break; | |
6aa8b732 AK |
3481 | case 0xb3: |
3482 | btr: /* btr */ | |
05f086f8 | 3483 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3484 | break; |
6aa8b732 | 3485 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3486 | c->dst.bytes = c->op_bytes; |
3487 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3488 | : (u16) c->src.val; | |
6aa8b732 | 3489 | break; |
6aa8b732 | 3490 | case 0xba: /* Grp8 */ |
e4e03ded | 3491 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3492 | case 0: |
3493 | goto bt; | |
3494 | case 1: | |
3495 | goto bts; | |
3496 | case 2: | |
3497 | goto btr; | |
3498 | case 3: | |
3499 | goto btc; | |
3500 | } | |
3501 | break; | |
7de75248 NK |
3502 | case 0xbb: |
3503 | btc: /* btc */ | |
05f086f8 | 3504 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3505 | break; |
d9574a25 WY |
3506 | case 0xbc: { /* bsf */ |
3507 | u8 zf; | |
3508 | __asm__ ("bsf %2, %0; setz %1" | |
3509 | : "=r"(c->dst.val), "=q"(zf) | |
3510 | : "r"(c->src.val)); | |
3511 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3512 | if (zf) { | |
3513 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3514 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3515 | } | |
3516 | break; | |
3517 | } | |
3518 | case 0xbd: { /* bsr */ | |
3519 | u8 zf; | |
3520 | __asm__ ("bsr %2, %0; setz %1" | |
3521 | : "=r"(c->dst.val), "=q"(zf) | |
3522 | : "r"(c->src.val)); | |
3523 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3524 | if (zf) { | |
3525 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3526 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3527 | } | |
3528 | break; | |
3529 | } | |
6aa8b732 | 3530 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3531 | c->dst.bytes = c->op_bytes; |
3532 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3533 | (s16) c->src.val; | |
6aa8b732 | 3534 | break; |
92f738a5 WY |
3535 | case 0xc0 ... 0xc1: /* xadd */ |
3536 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
3537 | /* Write back the register source. */ | |
3538 | c->src.val = c->dst.orig_val; | |
3539 | write_register_operand(&c->src); | |
3540 | break; | |
a012e65a | 3541 | case 0xc3: /* movnti */ |
e4e03ded LV |
3542 | c->dst.bytes = c->op_bytes; |
3543 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3544 | (u64) c->src.val; | |
a012e65a | 3545 | break; |
6aa8b732 | 3546 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3547 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3548 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3549 | goto done; |
3550 | break; | |
91269b8f AK |
3551 | default: |
3552 | goto cannot_emulate; | |
6aa8b732 AK |
3553 | } |
3554 | goto writeback; | |
3555 | ||
3556 | cannot_emulate: | |
e4e03ded | 3557 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3558 | return -1; |
3559 | } |