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KVM: add missing void __user * cast to access_ok() call
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
46561646 76#define GroupMask (7<<14) /* Opcode uses one of the group mechanisms */
e09d082c 77#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
46561646
AK		 78#define GroupDual (2<<14) /* Alternate decoding of mod == 3 */
79#define Prefix (3<<14) /* Instruction varies with 66/f2/f3 prefix */
80#define RMExt (4<<14) /* Opcode extension in ModRM r/m if mod == 3 */
1253791d 81#define Sse (1<<17) /* SSE Vector instruction */
d8769fed 82/* Misc flags */
8ea7d6ae 83#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 84#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 85#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 86#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
7db41eb7 96#define Src2Imm (4<<29)
0dc8d10f 97#define Src2Mask (7<<29)
6aa8b732 98
d0e53325
AK		 99#define X2(x...) x, x
100#define X3(x...) X2(x), x
101#define X4(x...) X2(x), X2(x)
102#define X5(x...) X4(x), x
103#define X6(x...) X4(x), X2(x)
104#define X7(x...) X4(x), X3(x)
105#define X8(x...) X4(x), X4(x)
106#define X16(x...) X8(x), X8(x)
83babbca 107
d65b1dee
AK		 108struct opcode {
109 u32 flags;
c4f035c6 110 u8 intercept;
120df890 111 union {
ef65c889 112 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 113 struct opcode *group;
114 struct group_dual *gdual;
0d7cdee8 115 struct gprefix *gprefix;
120df890 116 } u;
d09beabd 117 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 118};
119
120struct group_dual {
121 struct opcode mod012[8];
122 struct opcode mod3[8];
d65b1dee
AK		 123};
124
0d7cdee8
AK		 125struct gprefix {
126 struct opcode pfx_no;
127 struct opcode pfx_66;
128 struct opcode pfx_f2;
129 struct opcode pfx_f3;
130};
131
6aa8b732 132/* EFLAGS bit definitions. */
d4c6a154
GN		 133#define EFLG_ID (1<<21)
134#define EFLG_VIP (1<<20)
135#define EFLG_VIF (1<<19)
136#define EFLG_AC (1<<18)
b1d86143
AP		 137#define EFLG_VM (1<<17)
138#define EFLG_RF (1<<16)
d4c6a154
GN		 139#define EFLG_IOPL (3<<12)
140#define EFLG_NT (1<<14)
6aa8b732
AK		 141#define EFLG_OF (1<<11)
142#define EFLG_DF (1<<10)
b1d86143 143#define EFLG_IF (1<<9)
d4c6a154 144#define EFLG_TF (1<<8)
6aa8b732
AK		 145#define EFLG_SF (1<<7)
146#define EFLG_ZF (1<<6)
147#define EFLG_AF (1<<4)
148#define EFLG_PF (1<<2)
149#define EFLG_CF (1<<0)
150
62bd430e
MG		 151#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
152#define EFLG_RESERVED_ONE_MASK 2
153
6aa8b732
AK		 154/*
155 * Instruction emulation:
156 * Most instructions are emulated directly via a fragment of inline assembly
157 * code. This allows us to save/restore EFLAGS and thus very easily pick up
158 * any modified flags.
159 */
160
05b3e0c2 161#if defined(CONFIG_X86_64)
6aa8b732
AK		 162#define _LO32 "k" /* force 32-bit operand */
163#define _STK "%%rsp" /* stack pointer */
164#elif defined(__i386__)
165#define _LO32 "" /* force 32-bit operand */
166#define _STK "%%esp" /* stack pointer */
167#endif
168
169/*
170 * These EFLAGS bits are restored from saved value during emulation, and
171 * any changes are written back to the saved value after emulation.
172 */
173#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
174
175/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 176#define _PRE_EFLAGS(_sav, _msk, _tmp) \
177 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
178 "movl %"_sav",%"_LO32 _tmp"; " \
179 "push %"_tmp"; " \
180 "push %"_tmp"; " \
181 "movl %"_msk",%"_LO32 _tmp"; " \
182 "andl %"_LO32 _tmp",("_STK"); " \
183 "pushf; " \
184 "notl %"_LO32 _tmp"; " \
185 "andl %"_LO32 _tmp",("_STK"); " \
186 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
187 "pop %"_tmp"; " \
188 "orl %"_LO32 _tmp",("_STK"); " \
189 "popf; " \
190 "pop %"_sav"; "
6aa8b732
AK		 191
192/* After executing instruction: write-back necessary bits in EFLAGS. */
193#define _POST_EFLAGS(_sav, _msk, _tmp) \
194 /* _sav |= EFLAGS & _msk; */ \
195 "pushf; " \
196 "pop %"_tmp"; " \
197 "andl %"_msk",%"_LO32 _tmp"; " \
198 "orl %"_LO32 _tmp",%"_sav"; "
199
dda96d8f
AK		 200#ifdef CONFIG_X86_64
201#define ON64(x) x
202#else
203#define ON64(x)
204#endif
205
b3b3d25a 206#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 207 do { \
208 __asm__ __volatile__ ( \
209 _PRE_EFLAGS("0", "4", "2") \
210 _op _suffix " %"_x"3,%1; " \
211 _POST_EFLAGS("0", "4", "2") \
fb2c2641 212 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 213 "=&r" (_tmp) \
214 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 215 } while (0)
6b7ad61f
AK		 216
217
6aa8b732
AK		 218/* Raw emulation: instruction has two explicit operands. */
219#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 220 do { \
221 unsigned long _tmp; \
222 \
223 switch ((_dst).bytes) { \
224 case 2: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 226 break; \
227 case 4: \
b3b3d25a 228 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 229 break; \
230 case 8: \
b3b3d25a 231 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 232 break; \
233 } \
6aa8b732
AK		 234 } while (0)
235
236#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
237 do { \
6b7ad61f 238 unsigned long _tmp; \
d77c26fc 239 switch ((_dst).bytes) { \
6aa8b732 240 case 1: \
b3b3d25a 241 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 242 break; \
243 default: \
244 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
245 _wx, _wy, _lx, _ly, _qx, _qy); \
246 break; \
247 } \
248 } while (0)
249
250/* Source operand is byte-sized and may be restricted to just %cl. */
251#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
252 __emulate_2op(_op, _src, _dst, _eflags, \
253 "b", "c", "b", "c", "b", "c", "b", "c")
254
255/* Source operand is byte, word, long or quad sized. */
256#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
257 __emulate_2op(_op, _src, _dst, _eflags, \
258 "b", "q", "w", "r", _LO32, "r", "", "r")
259
260/* Source operand is word, long or quad sized. */
261#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
262 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
263 "w", "r", _LO32, "r", "", "r")
264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 266#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
267 do { \
268 unsigned long _tmp; \
269 _type _clv = (_cl).val; \
270 _type _srcv = (_src).val; \
271 _type _dstv = (_dst).val; \
272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
277 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
281 (_cl).val = (unsigned long) _clv; \
282 (_src).val = (unsigned long) _srcv; \
283 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
7295261c
AK		 286#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
287 do { \
288 switch ((_dst).bytes) { \
289 case 2: \
290 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "w", unsigned short); \
292 break; \
293 case 4: \
294 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
295 "l", unsigned int); \
296 break; \
297 case 8: \
298 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
299 "q", unsigned long)); \
300 break; \
301 } \
d175226a
GT		 302 } while (0)
303
dda96d8f 304#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 305 do { \
306 unsigned long _tmp; \
307 \
dda96d8f
AK		 308 __asm__ __volatile__ ( \
309 _PRE_EFLAGS("0", "3", "2") \
310 _op _suffix " %1; " \
311 _POST_EFLAGS("0", "3", "2") \
312 : "=m" (_eflags), "+m" ((_dst).val), \
313 "=&r" (_tmp) \
314 : "i" (EFLAGS_MASK)); \
315 } while (0)
316
317/* Instruction has only one explicit operand (no source operand). */
318#define emulate_1op(_op, _dst, _eflags) \
319 do { \
d77c26fc 320 switch ((_dst).bytes) { \
dda96d8f
AK		 321 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
322 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
323 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
324 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 325 } \
326 } while (0)
327
3f9f53b0
MG		 328#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
329 do { \
330 unsigned long _tmp; \
331 \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "1") \
334 _op _suffix " %5; " \
335 _POST_EFLAGS("0", "4", "1") \
336 : "=m" (_eflags), "=&r" (_tmp), \
337 "+a" (_rax), "+d" (_rdx) \
338 : "i" (EFLAGS_MASK), "m" ((_src).val), \
339 "a" (_rax), "d" (_rdx)); \
340 } while (0)
341
f6b3597b
AK		 342#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
343 do { \
344 unsigned long _tmp; \
345 \
346 __asm__ __volatile__ ( \
347 _PRE_EFLAGS("0", "5", "1") \
348 "1: \n\t" \
349 _op _suffix " %6; " \
350 "2: \n\t" \
351 _POST_EFLAGS("0", "5", "1") \
352 ".pushsection .fixup,\"ax\" \n\t" \
353 "3: movb $1, %4 \n\t" \
354 "jmp 2b \n\t" \
355 ".popsection \n\t" \
356 _ASM_EXTABLE(1b, 3b) \
357 : "=m" (_eflags), "=&r" (_tmp), \
358 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
359 : "i" (EFLAGS_MASK), "m" ((_src).val), \
360 "a" (_rax), "d" (_rdx)); \
361 } while (0)
362
3f9f53b0 363/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 364#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
365 do { \
366 switch((_src).bytes) { \
367 case 1: \
368 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
369 _eflags, "b"); \
370 break; \
371 case 2: \
372 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
373 _eflags, "w"); \
374 break; \
375 case 4: \
376 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
377 _eflags, "l"); \
378 break; \
379 case 8: \
380 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
381 _eflags, "q")); \
382 break; \
3f9f53b0
MG		 383 } \
384 } while (0)
385
f6b3597b
AK		 386#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
387 do { \
388 switch((_src).bytes) { \
389 case 1: \
390 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
391 _eflags, "b", _ex); \
392 break; \
393 case 2: \
394 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
395 _eflags, "w", _ex); \
396 break; \
397 case 4: \
398 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
399 _eflags, "l", _ex); \
400 break; \
401 case 8: ON64( \
402 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
403 _eflags, "q", _ex)); \
404 break; \
405 } \
406 } while (0)
407
6aa8b732
AK		 408/* Fetch next part of the instruction being emulated. */
409#define insn_fetch(_type, _size, _eip) \
410({ unsigned long _x; \
62266869 411 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 412 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 413 goto done; \
414 (_eip) += (_size); \
415 (_type)_x; \
416})
417
7295261c 418#define insn_fetch_arr(_arr, _size, _eip) \
414e6277
GN		 419({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
420 if (rc != X86EMUL_CONTINUE) \
421 goto done; \
422 (_eip) += (_size); \
423})
424
8a76d7f2
JR		 425static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
426 enum x86_intercept intercept,
427 enum x86_intercept_stage stage)
428{
429 struct x86_instruction_info info = {
430 .intercept = intercept,
431 .rep_prefix = ctxt->decode.rep_prefix,
432 .modrm_mod = ctxt->decode.modrm_mod,
433 .modrm_reg = ctxt->decode.modrm_reg,
434 .modrm_rm = ctxt->decode.modrm_rm,
435 .src_val = ctxt->decode.src.val64,
436 .src_bytes = ctxt->decode.src.bytes,
437 .dst_bytes = ctxt->decode.dst.bytes,
438 .ad_bytes = ctxt->decode.ad_bytes,
439 .next_rip = ctxt->eip,
440 };
441
2953538e 442 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 443}
444
ddcb2885
HH		 445static inline unsigned long ad_mask(struct decode_cache *c)
446{
447 return (1UL << (c->ad_bytes << 3)) - 1;
448}
449
6aa8b732 450/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 451static inline unsigned long
452address_mask(struct decode_cache *c, unsigned long reg)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 return reg;
456 else
457 return reg & ad_mask(c);
458}
459
460static inline unsigned long
90de84f5 461register_address(struct decode_cache *c, unsigned long reg)
e4706772 462{
90de84f5 463 return address_mask(c, reg);
e4706772
HH		 464}
465
7a957275
HH		 466static inline void
467register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
468{
469 if (c->ad_bytes == sizeof(unsigned long))
470 *reg += inc;
471 else
472 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
473}
6aa8b732 474
7a957275
HH		 475static inline void jmp_rel(struct decode_cache *c, int rel)
476{
477 register_address_increment(c, &c->eip, rel);
478}
098c937b 479
56697687
AK		 480static u32 desc_limit_scaled(struct desc_struct *desc)
481{
482 u32 limit = get_desc_limit(desc);
483
484 return desc->g ? (limit << 12) | 0xfff : limit;
485}
486
7a5b56df
AK		 487static void set_seg_override(struct decode_cache *c, int seg)
488{
489 c->has_seg_override = true;
490 c->seg_override = seg;
491}
492
79168fd1
GN		 493static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
494 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 495{
496 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
497 return 0;
498
4bff1e86 499 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 500}
501
90de84f5 502static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
90de84f5 503 struct decode_cache *c)
7a5b56df
AK		 504{
505 if (!c->has_seg_override)
506 return 0;
507
90de84f5 508 return c->seg_override;
7a5b56df
AK		 509}
510
35d3d4a1
AK		 511static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
54b8486f 513{
da9cb575
AK		 514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
35d3d4a1 517 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 518}
519
3b88e41a
JR		 520static int emulate_db(struct x86_emulate_ctxt *ctxt)
521{
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523}
524
35d3d4a1 525static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 528}
529
618ff15d
AK		 530static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531{
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533}
534
35d3d4a1 535static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 536{
35d3d4a1 537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 538}
539
35d3d4a1 540static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 543}
544
34d1f490
AK		 545static int emulate_de(struct x86_emulate_ctxt *ctxt)
546{
35d3d4a1 547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 548}
549
1253791d
AK		 550static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553}
554
1aa36616
AK		 555static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
556{
557 u16 selector;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
561 return selector;
562}
563
564static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
565 unsigned seg)
566{
567 u16 dummy;
568 u32 base3;
569 struct desc_struct desc;
570
571 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
572 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
573}
574
3d9b938e 575static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 576 struct segmented_address addr,
3d9b938e 577 unsigned size, bool write, bool fetch,
52fd8b44
AK		 578 ulong *linear)
579{
580 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 581 struct desc_struct desc;
582 bool usable;
52fd8b44 583 ulong la;
618ff15d 584 u32 lim;
1aa36616 585 u16 sel;
618ff15d 586 unsigned cpl, rpl;
52fd8b44
AK		 587
588 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 589 switch (ctxt->mode) {
590 case X86EMUL_MODE_REAL:
591 break;
592 case X86EMUL_MODE_PROT64:
593 if (((signed long)la << 16) >> 16 != la)
594 return emulate_gp(ctxt, 0);
595 break;
596 default:
1aa36616
AK		 597 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
598 addr.seg);
618ff15d
AK		 599 if (!usable)
600 goto bad;
601 /* code segment or read-only data segment */
602 if (((desc.type & 8) || !(desc.type & 2)) && write)
603 goto bad;
604 /* unreadable code segment */
3d9b938e 605 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 606 goto bad;
607 lim = desc_limit_scaled(&desc);
608 if ((desc.type & 8) || !(desc.type & 4)) {
609 /* expand-up segment */
610 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
611 goto bad;
612 } else {
613 /* exapand-down segment */
614 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
615 goto bad;
616 lim = desc.d ? 0xffffffff : 0xffff;
617 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
618 goto bad;
619 }
717746e3 620 cpl = ctxt->ops->cpl(ctxt);
1aa36616 621 rpl = sel & 3;
618ff15d
AK		 622 cpl = max(cpl, rpl);
623 if (!(desc.type & 8)) {
624 /* data segment */
625 if (cpl > desc.dpl)
626 goto bad;
627 } else if ((desc.type & 8) && !(desc.type & 4)) {
628 /* nonconforming code segment */
629 if (cpl != desc.dpl)
630 goto bad;
631 } else if ((desc.type & 8) && (desc.type & 4)) {
632 /* conforming code segment */
633 if (cpl < desc.dpl)
634 goto bad;
635 }
636 break;
637 }
3d9b938e 638 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 639 la &= (u32)-1;
640 *linear = la;
641 return X86EMUL_CONTINUE;
618ff15d
AK		 642bad:
643 if (addr.seg == VCPU_SREG_SS)
644 return emulate_ss(ctxt, addr.seg);
645 else
646 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 647}
648
3d9b938e
NE		 649static int linearize(struct x86_emulate_ctxt *ctxt,
650 struct segmented_address addr,
651 unsigned size, bool write,
652 ulong *linear)
653{
654 return __linearize(ctxt, addr, size, write, false, linear);
655}
656
657
3ca3ac4d
AK		 658static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
659 struct segmented_address addr,
660 void *data,
661 unsigned size)
662{
9fa088f4
AK		 663 int rc;
664 ulong linear;
665
83b8795a 666 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 667 if (rc != X86EMUL_CONTINUE)
668 return rc;
0f65dd70 669 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 670}
671
62266869
AK		 672static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
2fb53ad8 674 unsigned long eip, u8 *dest)
62266869
AK		 675{
676 struct fetch_cache *fc = &ctxt->decode.fetch;
677 int rc;
2fb53ad8 678 int size, cur_size;
62266869 679
2fb53ad8 680 if (eip == fc->end) {
3d9b938e
NE		 681 unsigned long linear;
682 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 683 cur_size = fc->end - fc->start;
684 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 685 rc = __linearize(ctxt, addr, size, false, true, &linear);
686 if (rc != X86EMUL_CONTINUE)
687 return rc;
0f65dd70
AK		 688 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
689 size, &ctxt->exception);
3e2815e9 690 if (rc != X86EMUL_CONTINUE)
62266869 691 return rc;
2fb53ad8 692 fc->end += size;
62266869 693 }
2fb53ad8 694 *dest = fc->data[eip - fc->start];
3e2815e9 695 return X86EMUL_CONTINUE;
62266869
AK		 696}
697
698static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
699 struct x86_emulate_ops *ops,
700 unsigned long eip, void *dest, unsigned size)
701{
3e2815e9 702 int rc;
62266869 703
eb3c79e6 704 /* x86 instructions are limited to 15 bytes. */
063db061 705 if (eip + size - ctxt->eip > 15)
eb3c79e6 706 return X86EMUL_UNHANDLEABLE;
62266869
AK		 707 while (size--) {
708 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 709 if (rc != X86EMUL_CONTINUE)
62266869
AK		 710 return rc;
711 }
3e2815e9 712 return X86EMUL_CONTINUE;
62266869
AK		 713}
714
1e3c5cb0
RR		 715/*
716 * Given the 'reg' portion of a ModRM byte, and a register block, return a
717 * pointer into the block that addresses the relevant register.
718 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
719 */
720static void *decode_register(u8 modrm_reg, unsigned long *regs,
721 int highbyte_regs)
6aa8b732
AK		 722{
723 void *p;
724
725 p = &regs[modrm_reg];
726 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
727 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
728 return p;
729}
730
731static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 732 struct segmented_address addr,
6aa8b732
AK		 733 u16 *size, unsigned long *address, int op_bytes)
734{
735 int rc;
736
737 if (op_bytes == 2)
738 op_bytes = 3;
739 *address = 0;
3ca3ac4d 740 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 741 if (rc != X86EMUL_CONTINUE)
6aa8b732 742 return rc;
30b31ab6 743 addr.ea += 2;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 745 return rc;
746}
747
bbe9abbd
NK		 748static int test_cc(unsigned int condition, unsigned int flags)
749{
750 int rc = 0;
751
752 switch ((condition & 15) >> 1) {
753 case 0: /* o */
754 rc |= (flags & EFLG_OF);
755 break;
756 case 1: /* b/c/nae */
757 rc |= (flags & EFLG_CF);
758 break;
759 case 2: /* z/e */
760 rc |= (flags & EFLG_ZF);
761 break;
762 case 3: /* be/na */
763 rc |= (flags & (EFLG_CF|EFLG_ZF));
764 break;
765 case 4: /* s */
766 rc |= (flags & EFLG_SF);
767 break;
768 case 5: /* p/pe */
769 rc |= (flags & EFLG_PF);
770 break;
771 case 7: /* le/ng */
772 rc |= (flags & EFLG_ZF);
773 /* fall through */
774 case 6: /* l/nge */
775 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
776 break;
777 }
778
779 /* Odd condition identifiers (lsb == 1) have inverted sense. */
780 return (!!rc ^ (condition & 1));
781}
782
91ff3cb4
AK		 783static void fetch_register_operand(struct operand *op)
784{
785 switch (op->bytes) {
786 case 1:
787 op->val = *(u8 *)op->addr.reg;
788 break;
789 case 2:
790 op->val = *(u16 *)op->addr.reg;
791 break;
792 case 4:
793 op->val = *(u32 *)op->addr.reg;
794 break;
795 case 8:
796 op->val = *(u64 *)op->addr.reg;
797 break;
798 }
799}
800
1253791d
AK		 801static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
802{
803 ctxt->ops->get_fpu(ctxt);
804 switch (reg) {
805 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
806 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
807 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
808 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
809 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
810 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
811 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
812 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
813#ifdef CONFIG_X86_64
814 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
815 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
816 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
817 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
818 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
819 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
820 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
821 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
822#endif
823 default: BUG();
824 }
825 ctxt->ops->put_fpu(ctxt);
826}
827
828static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
829 int reg)
830{
831 ctxt->ops->get_fpu(ctxt);
832 switch (reg) {
833 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
834 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
835 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
836 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
837 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
838 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
839 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
840 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
841#ifdef CONFIG_X86_64
842 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
843 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
844 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
845 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
846 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
847 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
848 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
849 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
850#endif
851 default: BUG();
852 }
853 ctxt->ops->put_fpu(ctxt);
854}
855
856static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
857 struct operand *op,
3c118e24 858 struct decode_cache *c,
3c118e24
AK		 859 int inhibit_bytereg)
860{
33615aa9 861 unsigned reg = c->modrm_reg;
9f1ef3f8 862 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 863
864 if (!(c->d & ModRM))
865 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 866
867 if (c->d & Sse) {
868 op->type = OP_XMM;
869 op->bytes = 16;
870 op->addr.xmm = reg;
871 read_sse_reg(ctxt, &op->vec_val, reg);
872 return;
873 }
874
3c118e24
AK		 875 op->type = OP_REG;
876 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 877 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 878 op->bytes = 1;
879 } else {
1a6440ae 880 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 881 op->bytes = c->op_bytes;
3c118e24 882 }
91ff3cb4 883 fetch_register_operand(op);
3c118e24
AK		 884 op->orig_val = op->val;
885}
886
1c73ef66 887static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 888 struct x86_emulate_ops *ops,
889 struct operand *op)
1c73ef66
AK		 890{
891 struct decode_cache *c = &ctxt->decode;
892 u8 sib;
f5b4edcd 893 int index_reg = 0, base_reg = 0, scale;
3e2815e9 894 int rc = X86EMUL_CONTINUE;
2dbd0dd7 895 ulong modrm_ea = 0;
1c73ef66
AK		 896
897 if (c->rex_prefix) {
898 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
899 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
900 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
901 }
902
903 c->modrm = insn_fetch(u8, 1, c->eip);
904 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
905 c->modrm_reg |= (c->modrm & 0x38) >> 3;
906 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 907 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 908
909 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 910 op->type = OP_REG;
911 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
912 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 913 c->regs, c->d & ByteOp);
1253791d
AK		 914 if (c->d & Sse) {
915 op->type = OP_XMM;
916 op->bytes = 16;
917 op->addr.xmm = c->modrm_rm;
918 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
919 return rc;
920 }
2dbd0dd7 921 fetch_register_operand(op);
1c73ef66
AK		 922 return rc;
923 }
924
2dbd0dd7
AK		 925 op->type = OP_MEM;
926
1c73ef66
AK		 927 if (c->ad_bytes == 2) {
928 unsigned bx = c->regs[VCPU_REGS_RBX];
929 unsigned bp = c->regs[VCPU_REGS_RBP];
930 unsigned si = c->regs[VCPU_REGS_RSI];
931 unsigned di = c->regs[VCPU_REGS_RDI];
932
933 /* 16-bit ModR/M decode. */
934 switch (c->modrm_mod) {
935 case 0:
936 if (c->modrm_rm == 6)
2dbd0dd7 937 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 938 break;
939 case 1:
2dbd0dd7 940 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 941 break;
942 case 2:
2dbd0dd7 943 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 944 break;
945 }
946 switch (c->modrm_rm) {
947 case 0:
2dbd0dd7 948 modrm_ea += bx + si;
1c73ef66
AK		 949 break;
950 case 1:
2dbd0dd7 951 modrm_ea += bx + di;
1c73ef66
AK		 952 break;
953 case 2:
2dbd0dd7 954 modrm_ea += bp + si;
1c73ef66
AK		 955 break;
956 case 3:
2dbd0dd7 957 modrm_ea += bp + di;
1c73ef66
AK		 958 break;
959 case 4:
2dbd0dd7 960 modrm_ea += si;
1c73ef66
AK		 961 break;
962 case 5:
2dbd0dd7 963 modrm_ea += di;
1c73ef66
AK		 964 break;
965 case 6:
966 if (c->modrm_mod != 0)
2dbd0dd7 967 modrm_ea += bp;
1c73ef66
AK		 968 break;
969 case 7:
2dbd0dd7 970 modrm_ea += bx;
1c73ef66
AK		 971 break;
972 }
973 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
974 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 975 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 976 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 977 } else {
978 /* 32/64-bit ModR/M decode. */
84411d85 979 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 980 sib = insn_fetch(u8, 1, c->eip);
981 index_reg |= (sib >> 3) & 7;
982 base_reg |= sib & 7;
983 scale = sib >> 6;
984
dc71d0f1 985 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 986 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 987 else
2dbd0dd7 988 modrm_ea += c->regs[base_reg];
dc71d0f1 989 if (index_reg != 4)
2dbd0dd7 990 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 991 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
992 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 993 c->rip_relative = 1;
84411d85 994 } else
2dbd0dd7 995 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 996 switch (c->modrm_mod) {
997 case 0:
998 if (c->modrm_rm == 5)
2dbd0dd7 999 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1000 break;
1001 case 1:
2dbd0dd7 1002 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 1003 break;
1004 case 2:
2dbd0dd7 1005 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1006 break;
1007 }
1008 }
90de84f5 1009 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1010done:
1011 return rc;
1012}
1013
1014static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 1015 struct x86_emulate_ops *ops,
1016 struct operand *op)
1c73ef66
AK		 1017{
1018 struct decode_cache *c = &ctxt->decode;
3e2815e9 1019 int rc = X86EMUL_CONTINUE;
1c73ef66 1020
2dbd0dd7 1021 op->type = OP_MEM;
1c73ef66
AK		 1022 switch (c->ad_bytes) {
1023 case 2:
90de84f5 1024 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1025 break;
1026 case 4:
90de84f5 1027 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1028 break;
1029 case 8:
90de84f5 1030 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1031 break;
1032 }
1033done:
1034 return rc;
1035}
1036
35c843c4
WY		 1037static void fetch_bit_operand(struct decode_cache *c)
1038{
7129eeca 1039 long sv = 0, mask;
35c843c4 1040
3885f18f 1041 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1042 mask = ~(c->dst.bytes * 8 - 1);
1043
1044 if (c->src.bytes == 2)
1045 sv = (s16)c->src.val & (s16)mask;
1046 else if (c->src.bytes == 4)
1047 sv = (s32)c->src.val & (s32)mask;
1048
90de84f5 1049 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1050 }
ba7ff2b7
WY		 1051
1052 /* only subword offset */
1053 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1054}
1055
dde7e6d1
AK		 1056static int read_emulated(struct x86_emulate_ctxt *ctxt,
1057 struct x86_emulate_ops *ops,
1058 unsigned long addr, void *dest, unsigned size)
6aa8b732 1059{
dde7e6d1
AK		 1060 int rc;
1061 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1062
dde7e6d1
AK		 1063 while (size) {
1064 int n = min(size, 8u);
1065 size -= n;
1066 if (mc->pos < mc->end)
1067 goto read_cached;
5cd21917 1068
0f65dd70
AK		 1069 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1070 &ctxt->exception);
dde7e6d1
AK		 1071 if (rc != X86EMUL_CONTINUE)
1072 return rc;
1073 mc->end += n;
6aa8b732 1074
dde7e6d1
AK		 1075 read_cached:
1076 memcpy(dest, mc->data + mc->pos, n);
1077 mc->pos += n;
1078 dest += n;
1079 addr += n;
6aa8b732 1080 }
dde7e6d1
AK		 1081 return X86EMUL_CONTINUE;
1082}
6aa8b732 1083
3ca3ac4d
AK		 1084static int segmented_read(struct x86_emulate_ctxt *ctxt,
1085 struct segmented_address addr,
1086 void *data,
1087 unsigned size)
1088{
9fa088f4
AK		 1089 int rc;
1090 ulong linear;
1091
83b8795a 1092 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1093 if (rc != X86EMUL_CONTINUE)
1094 return rc;
1095 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1096}
1097
1098static int segmented_write(struct x86_emulate_ctxt *ctxt,
1099 struct segmented_address addr,
1100 const void *data,
1101 unsigned size)
1102{
9fa088f4
AK		 1103 int rc;
1104 ulong linear;
1105
83b8795a 1106 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1107 if (rc != X86EMUL_CONTINUE)
1108 return rc;
0f65dd70
AK		 1109 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1110 &ctxt->exception);
3ca3ac4d
AK		 1111}
1112
1113static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1114 struct segmented_address addr,
1115 const void *orig_data, const void *data,
1116 unsigned size)
1117{
9fa088f4
AK		 1118 int rc;
1119 ulong linear;
1120
83b8795a 1121 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1122 if (rc != X86EMUL_CONTINUE)
1123 return rc;
0f65dd70
AK		 1124 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1125 size, &ctxt->exception);
3ca3ac4d
AK		 1126}
1127
dde7e6d1
AK		 1128static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1129 struct x86_emulate_ops *ops,
1130 unsigned int size, unsigned short port,
1131 void *dest)
1132{
1133 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1134
dde7e6d1
AK		 1135 if (rc->pos == rc->end) { /* refill pio read ahead */
1136 struct decode_cache *c = &ctxt->decode;
1137 unsigned int in_page, n;
1138 unsigned int count = c->rep_prefix ?
1139 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1140 in_page = (ctxt->eflags & EFLG_DF) ?
1141 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1142 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1143 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1144 count);
1145 if (n == 0)
1146 n = 1;
1147 rc->pos = rc->end = 0;
ca1d4a9e 1148 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1149 return 0;
1150 rc->end = n * size;
6aa8b732
AK		 1151 }
1152
dde7e6d1
AK		 1153 memcpy(dest, rc->data + rc->pos, size);
1154 rc->pos += size;
1155 return 1;
1156}
6aa8b732 1157
dde7e6d1
AK		 1158static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1159 struct x86_emulate_ops *ops,
1160 u16 selector, struct desc_ptr *dt)
1161{
1162 if (selector & 1 << 2) {
1163 struct desc_struct desc;
1aa36616
AK		 1164 u16 sel;
1165
dde7e6d1 1166 memset (dt, 0, sizeof *dt);
1aa36616 1167 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1168 return;
e09d082c 1169
dde7e6d1
AK		 1170 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1171 dt->address = get_desc_base(&desc);
1172 } else
4bff1e86 1173 ops->get_gdt(ctxt, dt);
dde7e6d1 1174}
120df890 1175
dde7e6d1
AK		 1176/* allowed just for 8 bytes segments */
1177static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1178 struct x86_emulate_ops *ops,
1179 u16 selector, struct desc_struct *desc)
1180{
1181 struct desc_ptr dt;
1182 u16 index = selector >> 3;
1183 int ret;
dde7e6d1 1184 ulong addr;
120df890 1185
dde7e6d1 1186 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1187
35d3d4a1
AK		 1188 if (dt.size < index * 8 + 7)
1189 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1190 addr = dt.address + index * 8;
0f65dd70 1191 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1192
dde7e6d1
AK		 1193 return ret;
1194}
ef65c889 1195
dde7e6d1
AK		 1196/* allowed just for 8 bytes segments */
1197static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, struct desc_struct *desc)
1200{
1201 struct desc_ptr dt;
1202 u16 index = selector >> 3;
dde7e6d1
AK		 1203 ulong addr;
1204 int ret;
6aa8b732 1205
dde7e6d1 1206 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1207
35d3d4a1
AK		 1208 if (dt.size < index * 8 + 7)
1209 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1210
dde7e6d1 1211 addr = dt.address + index * 8;
0f65dd70 1212 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1213
dde7e6d1
AK		 1214 return ret;
1215}
c7e75a3d 1216
5601d05b 1217/* Does not support long mode */
dde7e6d1
AK		 1218static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1219 struct x86_emulate_ops *ops,
1220 u16 selector, int seg)
1221{
1222 struct desc_struct seg_desc;
1223 u8 dpl, rpl, cpl;
1224 unsigned err_vec = GP_VECTOR;
1225 u32 err_code = 0;
1226 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1227 int ret;
69f55cb1 1228
dde7e6d1 1229 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1230
dde7e6d1
AK		 1231 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1232 || ctxt->mode == X86EMUL_MODE_REAL) {
1233 /* set real mode segment descriptor */
1234 set_desc_base(&seg_desc, selector << 4);
1235 set_desc_limit(&seg_desc, 0xffff);
1236 seg_desc.type = 3;
1237 seg_desc.p = 1;
1238 seg_desc.s = 1;
1239 goto load;
1240 }
1241
1242 /* NULL selector is not valid for TR, CS and SS */
1243 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1244 && null_selector)
1245 goto exception;
1246
1247 /* TR should be in GDT only */
1248 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1249 goto exception;
1250
1251 if (null_selector) /* for NULL selector skip all following checks */
1252 goto load;
1253
1254 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1255 if (ret != X86EMUL_CONTINUE)
1256 return ret;
1257
1258 err_code = selector & 0xfffc;
1259 err_vec = GP_VECTOR;
1260
1261 /* can't load system descriptor into segment selecor */
1262 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1263 goto exception;
1264
1265 if (!seg_desc.p) {
1266 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1267 goto exception;
1268 }
1269
1270 rpl = selector & 3;
1271 dpl = seg_desc.dpl;
717746e3 1272 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1273
1274 switch (seg) {
1275 case VCPU_SREG_SS:
1276 /*
1277 * segment is not a writable data segment or segment
1278 * selector's RPL != CPL or segment selector's RPL != CPL
1279 */
1280 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1281 goto exception;
6aa8b732 1282 break;
dde7e6d1
AK		 1283 case VCPU_SREG_CS:
1284 if (!(seg_desc.type & 8))
1285 goto exception;
1286
1287 if (seg_desc.type & 4) {
1288 /* conforming */
1289 if (dpl > cpl)
1290 goto exception;
1291 } else {
1292 /* nonconforming */
1293 if (rpl > cpl || dpl != cpl)
1294 goto exception;
1295 }
1296 /* CS(RPL) <- CPL */
1297 selector = (selector & 0xfffc) | cpl;
6aa8b732 1298 break;
dde7e6d1
AK		 1299 case VCPU_SREG_TR:
1300 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1301 goto exception;
1302 break;
1303 case VCPU_SREG_LDTR:
1304 if (seg_desc.s || seg_desc.type != 2)
1305 goto exception;
1306 break;
1307 default: /* DS, ES, FS, or GS */
4e62417b 1308 /*
dde7e6d1
AK		 1309 * segment is not a data or readable code segment or
1310 * ((segment is a data or nonconforming code segment)
1311 * and (both RPL and CPL > DPL))
4e62417b 1312 */
dde7e6d1
AK		 1313 if ((seg_desc.type & 0xa) == 0x8 ||
1314 (((seg_desc.type & 0xc) != 0xc) &&
1315 (rpl > dpl && cpl > dpl)))
1316 goto exception;
6aa8b732 1317 break;
dde7e6d1
AK		 1318 }
1319
1320 if (seg_desc.s) {
1321 /* mark segment as accessed */
1322 seg_desc.type |= 1;
1323 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1324 if (ret != X86EMUL_CONTINUE)
1325 return ret;
1326 }
1327load:
1aa36616 1328 ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1329 return X86EMUL_CONTINUE;
1330exception:
1331 emulate_exception(ctxt, err_vec, err_code, true);
1332 return X86EMUL_PROPAGATE_FAULT;
1333}
1334
31be40b3
WY		 1335static void write_register_operand(struct operand *op)
1336{
1337 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1338 switch (op->bytes) {
1339 case 1:
1340 *(u8 *)op->addr.reg = (u8)op->val;
1341 break;
1342 case 2:
1343 *(u16 *)op->addr.reg = (u16)op->val;
1344 break;
1345 case 4:
1346 *op->addr.reg = (u32)op->val;
1347 break; /* 64b: zero-extend */
1348 case 8:
1349 *op->addr.reg = op->val;
1350 break;
1351 }
1352}
1353
adddcecf 1354static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1355{
1356 int rc;
1357 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1358
1359 switch (c->dst.type) {
1360 case OP_REG:
31be40b3 1361 write_register_operand(&c->dst);
6aa8b732 1362 break;
dde7e6d1
AK		 1363 case OP_MEM:
1364 if (c->lock_prefix)
3ca3ac4d
AK		 1365 rc = segmented_cmpxchg(ctxt,
1366 c->dst.addr.mem,
1367 &c->dst.orig_val,
1368 &c->dst.val,
1369 c->dst.bytes);
341de7e3 1370 else
3ca3ac4d
AK		 1371 rc = segmented_write(ctxt,
1372 c->dst.addr.mem,
1373 &c->dst.val,
1374 c->dst.bytes);
dde7e6d1
AK		 1375 if (rc != X86EMUL_CONTINUE)
1376 return rc;
a682e354 1377 break;
1253791d
AK		 1378 case OP_XMM:
1379 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1380 break;
dde7e6d1
AK		 1381 case OP_NONE:
1382 /* no writeback */
414e6277 1383 break;
dde7e6d1 1384 default:
414e6277 1385 break;
6aa8b732 1386 }
dde7e6d1
AK		 1387 return X86EMUL_CONTINUE;
1388}
6aa8b732 1389
4487b3b4 1390static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1391{
1392 struct decode_cache *c = &ctxt->decode;
4179bb02 1393 struct segmented_address addr;
0dc8d10f 1394
dde7e6d1 1395 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1396 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1397 addr.seg = VCPU_SREG_SS;
1398
1399 /* Disable writeback. */
1400 c->dst.type = OP_NONE;
1401 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1402}
69f55cb1 1403
dde7e6d1 1404static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1405 void *dest, int len)
1406{
1407 struct decode_cache *c = &ctxt->decode;
1408 int rc;
90de84f5 1409 struct segmented_address addr;
8b4caf66 1410
90de84f5
AK		 1411 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1412 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1413 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1414 if (rc != X86EMUL_CONTINUE)
1415 return rc;
1416
1417 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1418 return rc;
8b4caf66
LV		 1419}
1420
c54fe504
TY		 1421static int em_pop(struct x86_emulate_ctxt *ctxt)
1422{
1423 struct decode_cache *c = &ctxt->decode;
1424
3b9be3bf 1425 return emulate_pop(ctxt, &c->dst.val, c->op_bytes);
c54fe504
TY		 1426}
1427
dde7e6d1
AK		 1428static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1429 struct x86_emulate_ops *ops,
1430 void *dest, int len)
9de41573
GN		 1431{
1432 int rc;
dde7e6d1
AK		 1433 unsigned long val, change_mask;
1434 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1435 int cpl = ops->cpl(ctxt);
9de41573 1436
3b9be3bf 1437 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
9de41573 1440
dde7e6d1
AK		 1441 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1442 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1443
dde7e6d1
AK		 1444 switch(ctxt->mode) {
1445 case X86EMUL_MODE_PROT64:
1446 case X86EMUL_MODE_PROT32:
1447 case X86EMUL_MODE_PROT16:
1448 if (cpl == 0)
1449 change_mask |= EFLG_IOPL;
1450 if (cpl <= iopl)
1451 change_mask |= EFLG_IF;
1452 break;
1453 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1454 if (iopl < 3)
1455 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1456 change_mask |= EFLG_IF;
1457 break;
1458 default: /* real mode */
1459 change_mask |= (EFLG_IOPL | EFLG_IF);
1460 break;
9de41573 1461 }
dde7e6d1
AK		 1462
1463 *(unsigned long *)dest =
1464 (ctxt->eflags & ~change_mask) | (val & change_mask);
1465
1466 return rc;
9de41573
GN		 1467}
1468
62aaa2f0
TY		 1469static int em_popf(struct x86_emulate_ctxt *ctxt)
1470{
1471 struct decode_cache *c = &ctxt->decode;
1472
1473 c->dst.type = OP_REG;
1474 c->dst.addr.reg = &ctxt->eflags;
1475 c->dst.bytes = c->op_bytes;
1476 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1477}
1478
4179bb02
TY		 1479static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1480 struct x86_emulate_ops *ops, int seg)
7b262e90 1481{
dde7e6d1 1482 struct decode_cache *c = &ctxt->decode;
7b262e90 1483
1aa36616 1484 c->src.val = get_segment_selector(ctxt, seg);
7b262e90 1485
4487b3b4 1486 return em_push(ctxt);
7b262e90
GN		 1487}
1488
dde7e6d1
AK		 1489static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1490 struct x86_emulate_ops *ops, int seg)
38ba30ba 1491{
dde7e6d1
AK		 1492 struct decode_cache *c = &ctxt->decode;
1493 unsigned long selector;
1494 int rc;
38ba30ba 1495
3b9be3bf 1496 rc = emulate_pop(ctxt, &selector, c->op_bytes);
dde7e6d1
AK		 1497 if (rc != X86EMUL_CONTINUE)
1498 return rc;
1499
1500 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1501 return rc;
38ba30ba
GN		 1502}
1503
b96a7fad 1504static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1505{
dde7e6d1
AK		 1506 struct decode_cache *c = &ctxt->decode;
1507 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1508 int rc = X86EMUL_CONTINUE;
1509 int reg = VCPU_REGS_RAX;
38ba30ba 1510
dde7e6d1
AK		 1511 while (reg <= VCPU_REGS_RDI) {
1512 (reg == VCPU_REGS_RSP) ?
1513 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1514
4487b3b4 1515 rc = em_push(ctxt);
dde7e6d1
AK		 1516 if (rc != X86EMUL_CONTINUE)
1517 return rc;
38ba30ba 1518
dde7e6d1 1519 ++reg;
38ba30ba 1520 }
38ba30ba 1521
dde7e6d1 1522 return rc;
38ba30ba
GN		 1523}
1524
62aaa2f0
TY		 1525static int em_pushf(struct x86_emulate_ctxt *ctxt)
1526{
1527 struct decode_cache *c = &ctxt->decode;
1528
1529 c->src.val = (unsigned long)ctxt->eflags;
1530 return em_push(ctxt);
1531}
1532
b96a7fad 1533static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1534{
dde7e6d1
AK		 1535 struct decode_cache *c = &ctxt->decode;
1536 int rc = X86EMUL_CONTINUE;
1537 int reg = VCPU_REGS_RDI;
38ba30ba 1538
dde7e6d1
AK		 1539 while (reg >= VCPU_REGS_RAX) {
1540 if (reg == VCPU_REGS_RSP) {
1541 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1542 c->op_bytes);
1543 --reg;
1544 }
38ba30ba 1545
3b9be3bf 1546 rc = emulate_pop(ctxt, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1547 if (rc != X86EMUL_CONTINUE)
1548 break;
1549 --reg;
38ba30ba 1550 }
dde7e6d1 1551 return rc;
38ba30ba
GN		 1552}
1553
6e154e56
MG		 1554int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1555 struct x86_emulate_ops *ops, int irq)
1556{
1557 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1558 int rc;
6e154e56
MG		 1559 struct desc_ptr dt;
1560 gva_t cs_addr;
1561 gva_t eip_addr;
1562 u16 cs, eip;
6e154e56
MG		 1563
1564 /* TODO: Add limit checks */
1565 c->src.val = ctxt->eflags;
4487b3b4 1566 rc = em_push(ctxt);
5c56e1cf
AK		 1567 if (rc != X86EMUL_CONTINUE)
1568 return rc;
6e154e56
MG		 1569
1570 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1571
1aa36616 1572 c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1573 rc = em_push(ctxt);
5c56e1cf
AK		 1574 if (rc != X86EMUL_CONTINUE)
1575 return rc;
6e154e56
MG		 1576
1577 c->src.val = c->eip;
4487b3b4 1578 rc = em_push(ctxt);
5c56e1cf
AK		 1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
1581
4bff1e86 1582 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1583
1584 eip_addr = dt.address + (irq << 2);
1585 cs_addr = dt.address + (irq << 2) + 2;
1586
0f65dd70 1587 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1588 if (rc != X86EMUL_CONTINUE)
1589 return rc;
1590
0f65dd70 1591 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1592 if (rc != X86EMUL_CONTINUE)
1593 return rc;
1594
1595 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1596 if (rc != X86EMUL_CONTINUE)
1597 return rc;
1598
1599 c->eip = eip;
1600
1601 return rc;
1602}
1603
1604static int emulate_int(struct x86_emulate_ctxt *ctxt,
1605 struct x86_emulate_ops *ops, int irq)
1606{
1607 switch(ctxt->mode) {
1608 case X86EMUL_MODE_REAL:
1609 return emulate_int_real(ctxt, ops, irq);
1610 case X86EMUL_MODE_VM86:
1611 case X86EMUL_MODE_PROT16:
1612 case X86EMUL_MODE_PROT32:
1613 case X86EMUL_MODE_PROT64:
1614 default:
1615 /* Protected mode interrupts unimplemented yet */
1616 return X86EMUL_UNHANDLEABLE;
1617 }
1618}
1619
dde7e6d1
AK		 1620static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1621 struct x86_emulate_ops *ops)
38ba30ba 1622{
dde7e6d1
AK		 1623 struct decode_cache *c = &ctxt->decode;
1624 int rc = X86EMUL_CONTINUE;
1625 unsigned long temp_eip = 0;
1626 unsigned long temp_eflags = 0;
1627 unsigned long cs = 0;
1628 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1629 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1630 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1631 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1632
dde7e6d1 1633 /* TODO: Add stack limit check */
38ba30ba 1634
3b9be3bf 1635 rc = emulate_pop(ctxt, &temp_eip, c->op_bytes);
38ba30ba 1636
dde7e6d1
AK		 1637 if (rc != X86EMUL_CONTINUE)
1638 return rc;
38ba30ba 1639
35d3d4a1
AK		 1640 if (temp_eip & ~0xffff)
1641 return emulate_gp(ctxt, 0);
38ba30ba 1642
3b9be3bf 1643 rc = emulate_pop(ctxt, &cs, c->op_bytes);
38ba30ba 1644
dde7e6d1
AK		 1645 if (rc != X86EMUL_CONTINUE)
1646 return rc;
38ba30ba 1647
3b9be3bf 1648 rc = emulate_pop(ctxt, &temp_eflags, c->op_bytes);
38ba30ba 1649
dde7e6d1
AK		 1650 if (rc != X86EMUL_CONTINUE)
1651 return rc;
38ba30ba 1652
dde7e6d1 1653 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1654
dde7e6d1
AK		 1655 if (rc != X86EMUL_CONTINUE)
1656 return rc;
38ba30ba 1657
dde7e6d1 1658 c->eip = temp_eip;
38ba30ba 1659
38ba30ba 1660
dde7e6d1
AK		 1661 if (c->op_bytes == 4)
1662 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1663 else if (c->op_bytes == 2) {
1664 ctxt->eflags &= ~0xffff;
1665 ctxt->eflags |= temp_eflags;
38ba30ba 1666 }
dde7e6d1
AK		 1667
1668 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1669 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1670
1671 return rc;
38ba30ba
GN		 1672}
1673
dde7e6d1
AK		 1674static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1675 struct x86_emulate_ops* ops)
c37eda13 1676{
dde7e6d1
AK		 1677 switch(ctxt->mode) {
1678 case X86EMUL_MODE_REAL:
1679 return emulate_iret_real(ctxt, ops);
1680 case X86EMUL_MODE_VM86:
1681 case X86EMUL_MODE_PROT16:
1682 case X86EMUL_MODE_PROT32:
1683 case X86EMUL_MODE_PROT64:
c37eda13 1684 default:
dde7e6d1
AK		 1685 /* iret from protected mode unimplemented yet */
1686 return X86EMUL_UNHANDLEABLE;
c37eda13 1687 }
c37eda13
WY		 1688}
1689
d2f62766
TY		 1690static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1691{
1692 struct decode_cache *c = &ctxt->decode;
1693 int rc;
1694 unsigned short sel;
1695
1696 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1697
1698 rc = load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS);
1699 if (rc != X86EMUL_CONTINUE)
1700 return rc;
1701
1702 c->eip = 0;
1703 memcpy(&c->eip, c->src.valptr, c->op_bytes);
1704 return X86EMUL_CONTINUE;
1705}
1706
51187683 1707static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1708{
1709 struct decode_cache *c = &ctxt->decode;
1710
3b9be3bf 1711 return emulate_pop(ctxt, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1712}
1713
51187683 1714static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1715{
05f086f8 1716 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1717 switch (c->modrm_reg) {
1718 case 0: /* rol */
05f086f8 1719 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1720 break;
1721 case 1: /* ror */
05f086f8 1722 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1723 break;
1724 case 2: /* rcl */
05f086f8 1725 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1726 break;
1727 case 3: /* rcr */
05f086f8 1728 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1729 break;
1730 case 4: /* sal/shl */
1731 case 6: /* sal/shl */
05f086f8 1732 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1733 break;
1734 case 5: /* shr */
05f086f8 1735 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1736 break;
1737 case 7: /* sar */
05f086f8 1738 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1739 break;
1740 }
51187683 1741 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1742}
1743
51187683 1744static int em_grp3(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1745{
1746 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1747 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1748 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1749 u8 de = 0;
8cdbd2c9
LV		 1750
1751 switch (c->modrm_reg) {
1752 case 0 ... 1: /* test */
05f086f8 1753 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1754 break;
1755 case 2: /* not */
1756 c->dst.val = ~c->dst.val;
1757 break;
1758 case 3: /* neg */
05f086f8 1759 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1760 break;
3f9f53b0
MG		 1761 case 4: /* mul */
1762 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1763 break;
1764 case 5: /* imul */
1765 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1766 break;
1767 case 6: /* div */
34d1f490
AK		 1768 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1769 ctxt->eflags, de);
3f9f53b0
MG		 1770 break;
1771 case 7: /* idiv */
34d1f490
AK		 1772 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1773 ctxt->eflags, de);
3f9f53b0 1774 break;
8cdbd2c9 1775 default:
8c5eee30 1776 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1777 }
34d1f490
AK		 1778 if (de)
1779 return emulate_de(ctxt);
8c5eee30 1780 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1781}
1782
51187683 1783static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1784{
1785 struct decode_cache *c = &ctxt->decode;
4179bb02 1786 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1787
1788 switch (c->modrm_reg) {
1789 case 0: /* inc */
05f086f8 1790 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1791 break;
1792 case 1: /* dec */
05f086f8 1793 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1794 break;
d19292e4
MG		 1795 case 2: /* call near abs */ {
1796 long int old_eip;
1797 old_eip = c->eip;
1798 c->eip = c->src.val;
1799 c->src.val = old_eip;
4487b3b4 1800 rc = em_push(ctxt);
d19292e4
MG		 1801 break;
1802 }
8cdbd2c9 1803 case 4: /* jmp abs */
fd60754e 1804 c->eip = c->src.val;
8cdbd2c9 1805 break;
d2f62766
TY		 1806 case 5: /* jmp far */
1807 rc = em_jmp_far(ctxt);
1808 break;
8cdbd2c9 1809 case 6: /* push */
4487b3b4 1810 rc = em_push(ctxt);
8cdbd2c9 1811 break;
8cdbd2c9 1812 }
4179bb02 1813 return rc;
8cdbd2c9
LV		 1814}
1815
51187683 1816static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1817{
1818 struct decode_cache *c = &ctxt->decode;
16518d5a 1819 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1820
1821 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1822 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1823 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1824 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1825 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1826 } else {
16518d5a
AK		 1827 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1828 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1829
05f086f8 1830 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1831 }
1b30eaa8 1832 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1833}
1834
a77ab5ea
AK		 1835static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1836 struct x86_emulate_ops *ops)
1837{
1838 struct decode_cache *c = &ctxt->decode;
1839 int rc;
1840 unsigned long cs;
1841
3b9be3bf 1842 rc = emulate_pop(ctxt, &c->eip, c->op_bytes);
1b30eaa8 1843 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1844 return rc;
1845 if (c->op_bytes == 4)
1846 c->eip = (u32)c->eip;
3b9be3bf 1847 rc = emulate_pop(ctxt, &cs, c->op_bytes);
1b30eaa8 1848 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1849 return rc;
2e873022 1850 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1851 return rc;
1852}
1853
09b5f4d3
WY		 1854static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1855 struct x86_emulate_ops *ops, int seg)
1856{
1857 struct decode_cache *c = &ctxt->decode;
1858 unsigned short sel;
1859 int rc;
1860
1861 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1862
1863 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1864 if (rc != X86EMUL_CONTINUE)
1865 return rc;
1866
1867 c->dst.val = c->src.val;
1868 return rc;
1869}
1870
e66bb2cc
AP		 1871static inline void
1872setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1873 struct x86_emulate_ops *ops, struct desc_struct *cs,
1874 struct desc_struct *ss)
e66bb2cc 1875{
1aa36616
AK		 1876 u16 selector;
1877
79168fd1 1878 memset(cs, 0, sizeof(struct desc_struct));
1aa36616 1879 ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1880 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1881
1882 cs->l = 0; /* will be adjusted later */
79168fd1 1883 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1884 cs->g = 1; /* 4kb granularity */
79168fd1 1885 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1886 cs->type = 0x0b; /* Read, Execute, Accessed */
1887 cs->s = 1;
1888 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1889 cs->p = 1;
1890 cs->d = 1;
e66bb2cc 1891
79168fd1
GN		 1892 set_desc_base(ss, 0); /* flat segment */
1893 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1894 ss->g = 1; /* 4kb granularity */
1895 ss->s = 1;
1896 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1897 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1898 ss->dpl = 0;
79168fd1 1899 ss->p = 1;
e66bb2cc
AP		 1900}
1901
1902static int
3fb1b5db 1903emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1904{
1905 struct decode_cache *c = &ctxt->decode;
79168fd1 1906 struct desc_struct cs, ss;
e66bb2cc 1907 u64 msr_data;
79168fd1 1908 u16 cs_sel, ss_sel;
c2ad2bb3 1909 u64 efer = 0;
e66bb2cc
AP		 1910
1911 /* syscall is not available in real mode */
2e901c4c 1912 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1913 ctxt->mode == X86EMUL_MODE_VM86)
1914 return emulate_ud(ctxt);
e66bb2cc 1915
c2ad2bb3 1916 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1917 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1918
717746e3 1919 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1920 msr_data >>= 32;
79168fd1
GN		 1921 cs_sel = (u16)(msr_data & 0xfffc);
1922 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1923
c2ad2bb3 1924 if (efer & EFER_LMA) {
79168fd1 1925 cs.d = 0;
e66bb2cc
AP		 1926 cs.l = 1;
1927 }
1aa36616
AK		 1928 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1929 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc
AP		 1930
1931 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1932 if (efer & EFER_LMA) {
e66bb2cc
AP		 1933#ifdef CONFIG_X86_64
1934 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1935
717746e3 1936 ops->get_msr(ctxt,
3fb1b5db
GN		 1937 ctxt->mode == X86EMUL_MODE_PROT64 ?
1938 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1939 c->eip = msr_data;
1940
717746e3 1941 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1942 ctxt->eflags &= ~(msr_data | EFLG_RF);
1943#endif
1944 } else {
1945 /* legacy mode */
717746e3 1946 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1947 c->eip = (u32)msr_data;
1948
1949 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1950 }
1951
e54cfa97 1952 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1953}
1954
8c604352 1955static int
3fb1b5db 1956emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1957{
1958 struct decode_cache *c = &ctxt->decode;
79168fd1 1959 struct desc_struct cs, ss;
8c604352 1960 u64 msr_data;
79168fd1 1961 u16 cs_sel, ss_sel;
c2ad2bb3 1962 u64 efer = 0;
8c604352 1963
c2ad2bb3 1964 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1965 /* inject #GP if in real mode */
35d3d4a1
AK		 1966 if (ctxt->mode == X86EMUL_MODE_REAL)
1967 return emulate_gp(ctxt, 0);
8c604352
AP		 1968
1969 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1970 * Therefore, we inject an #UD.
1971 */
35d3d4a1
AK		 1972 if (ctxt->mode == X86EMUL_MODE_PROT64)
1973 return emulate_ud(ctxt);
8c604352 1974
79168fd1 1975 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1976
717746e3 1977 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1978 switch (ctxt->mode) {
1979 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1980 if ((msr_data & 0xfffc) == 0x0)
1981 return emulate_gp(ctxt, 0);
8c604352
AP		 1982 break;
1983 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1984 if (msr_data == 0x0)
1985 return emulate_gp(ctxt, 0);
8c604352
AP		 1986 break;
1987 }
1988
1989 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1990 cs_sel = (u16)msr_data;
1991 cs_sel &= ~SELECTOR_RPL_MASK;
1992 ss_sel = cs_sel + 8;
1993 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1994 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1995 cs.d = 0;
8c604352
AP		 1996 cs.l = 1;
1997 }
1998
1aa36616
AK		 1999 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2000 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2001
717746e3 2002 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2003 c->eip = msr_data;
2004
717746e3 2005 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2006 c->regs[VCPU_REGS_RSP] = msr_data;
2007
e54cfa97 2008 return X86EMUL_CONTINUE;
8c604352
AP		 2009}
2010
4668f050 2011static int
3fb1b5db 2012emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2013{
2014 struct decode_cache *c = &ctxt->decode;
79168fd1 2015 struct desc_struct cs, ss;
4668f050
AP		 2016 u64 msr_data;
2017 int usermode;
79168fd1 2018 u16 cs_sel, ss_sel;
4668f050 2019
a0044755
GN		 2020 /* inject #GP if in real mode or Virtual 8086 mode */
2021 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2022 ctxt->mode == X86EMUL_MODE_VM86)
2023 return emulate_gp(ctxt, 0);
4668f050 2024
79168fd1 2025 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2026
2027 if ((c->rex_prefix & 0x8) != 0x0)
2028 usermode = X86EMUL_MODE_PROT64;
2029 else
2030 usermode = X86EMUL_MODE_PROT32;
2031
2032 cs.dpl = 3;
2033 ss.dpl = 3;
717746e3 2034 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2035 switch (usermode) {
2036 case X86EMUL_MODE_PROT32:
79168fd1 2037 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2038 if ((msr_data & 0xfffc) == 0x0)
2039 return emulate_gp(ctxt, 0);
79168fd1 2040 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2041 break;
2042 case X86EMUL_MODE_PROT64:
79168fd1 2043 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2044 if (msr_data == 0x0)
2045 return emulate_gp(ctxt, 0);
79168fd1
GN		 2046 ss_sel = cs_sel + 8;
2047 cs.d = 0;
4668f050
AP		 2048 cs.l = 1;
2049 break;
2050 }
79168fd1
GN		 2051 cs_sel |= SELECTOR_RPL_MASK;
2052 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2053
1aa36616
AK		 2054 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2055 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2056
bdb475a3
GN		 2057 c->eip = c->regs[VCPU_REGS_RDX];
2058 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2059
e54cfa97 2060 return X86EMUL_CONTINUE;
4668f050
AP		 2061}
2062
9c537244
GN		 2063static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2064 struct x86_emulate_ops *ops)
f850e2e6
GN		 2065{
2066 int iopl;
2067 if (ctxt->mode == X86EMUL_MODE_REAL)
2068 return false;
2069 if (ctxt->mode == X86EMUL_MODE_VM86)
2070 return true;
2071 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2072 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2073}
2074
2075static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2076 struct x86_emulate_ops *ops,
2077 u16 port, u16 len)
2078{
79168fd1 2079 struct desc_struct tr_seg;
5601d05b 2080 u32 base3;
f850e2e6 2081 int r;
1aa36616 2082 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2083 unsigned mask = (1 << len) - 1;
5601d05b 2084 unsigned long base;
f850e2e6 2085
1aa36616 2086 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2087 if (!tr_seg.p)
f850e2e6 2088 return false;
79168fd1 2089 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2090 return false;
5601d05b
GN		 2091 base = get_desc_base(&tr_seg);
2092#ifdef CONFIG_X86_64
2093 base |= ((u64)base3) << 32;
2094#endif
0f65dd70 2095 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2096 if (r != X86EMUL_CONTINUE)
2097 return false;
79168fd1 2098 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2099 return false;
0f65dd70 2100 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2101 if (r != X86EMUL_CONTINUE)
2102 return false;
2103 if ((perm >> bit_idx) & mask)
2104 return false;
2105 return true;
2106}
2107
2108static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2109 struct x86_emulate_ops *ops,
2110 u16 port, u16 len)
2111{
4fc40f07
GN		 2112 if (ctxt->perm_ok)
2113 return true;
2114
9c537244 2115 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2116 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2117 return false;
4fc40f07
GN		 2118
2119 ctxt->perm_ok = true;
2120
f850e2e6
GN		 2121 return true;
2122}
2123
38ba30ba
GN		 2124static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2125 struct x86_emulate_ops *ops,
2126 struct tss_segment_16 *tss)
2127{
2128 struct decode_cache *c = &ctxt->decode;
2129
2130 tss->ip = c->eip;
2131 tss->flag = ctxt->eflags;
2132 tss->ax = c->regs[VCPU_REGS_RAX];
2133 tss->cx = c->regs[VCPU_REGS_RCX];
2134 tss->dx = c->regs[VCPU_REGS_RDX];
2135 tss->bx = c->regs[VCPU_REGS_RBX];
2136 tss->sp = c->regs[VCPU_REGS_RSP];
2137 tss->bp = c->regs[VCPU_REGS_RBP];
2138 tss->si = c->regs[VCPU_REGS_RSI];
2139 tss->di = c->regs[VCPU_REGS_RDI];
2140
1aa36616
AK		 2141 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2142 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2143 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2144 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2145 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2146}
2147
2148static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2149 struct x86_emulate_ops *ops,
2150 struct tss_segment_16 *tss)
2151{
2152 struct decode_cache *c = &ctxt->decode;
2153 int ret;
2154
2155 c->eip = tss->ip;
2156 ctxt->eflags = tss->flag | 2;
2157 c->regs[VCPU_REGS_RAX] = tss->ax;
2158 c->regs[VCPU_REGS_RCX] = tss->cx;
2159 c->regs[VCPU_REGS_RDX] = tss->dx;
2160 c->regs[VCPU_REGS_RBX] = tss->bx;
2161 c->regs[VCPU_REGS_RSP] = tss->sp;
2162 c->regs[VCPU_REGS_RBP] = tss->bp;
2163 c->regs[VCPU_REGS_RSI] = tss->si;
2164 c->regs[VCPU_REGS_RDI] = tss->di;
2165
2166 /*
2167 * SDM says that segment selectors are loaded before segment
2168 * descriptors
2169 */
1aa36616
AK		 2170 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2171 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2172 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2173 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2174 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2175
2176 /*
2177 * Now load segment descriptors. If fault happenes at this stage
2178 * it is handled in a context of new task
2179 */
2180 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2181 if (ret != X86EMUL_CONTINUE)
2182 return ret;
2183 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2184 if (ret != X86EMUL_CONTINUE)
2185 return ret;
2186 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2187 if (ret != X86EMUL_CONTINUE)
2188 return ret;
2189 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2190 if (ret != X86EMUL_CONTINUE)
2191 return ret;
2192 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2193 if (ret != X86EMUL_CONTINUE)
2194 return ret;
2195
2196 return X86EMUL_CONTINUE;
2197}
2198
2199static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2200 struct x86_emulate_ops *ops,
2201 u16 tss_selector, u16 old_tss_sel,
2202 ulong old_tss_base, struct desc_struct *new_desc)
2203{
2204 struct tss_segment_16 tss_seg;
2205 int ret;
bcc55cba 2206 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2207
0f65dd70 2208 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2209 &ctxt->exception);
db297e3d 2210 if (ret != X86EMUL_CONTINUE)
38ba30ba 2211 /* FIXME: need to provide precise fault address */
38ba30ba 2212 return ret;
38ba30ba
GN		 2213
2214 save_state_to_tss16(ctxt, ops, &tss_seg);
2215
0f65dd70 2216 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2217 &ctxt->exception);
db297e3d 2218 if (ret != X86EMUL_CONTINUE)
38ba30ba 2219 /* FIXME: need to provide precise fault address */
38ba30ba 2220 return ret;
38ba30ba 2221
0f65dd70 2222 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2223 &ctxt->exception);
db297e3d 2224 if (ret != X86EMUL_CONTINUE)
38ba30ba 2225 /* FIXME: need to provide precise fault address */
38ba30ba 2226 return ret;
38ba30ba
GN		 2227
2228 if (old_tss_sel != 0xffff) {
2229 tss_seg.prev_task_link = old_tss_sel;
2230
0f65dd70 2231 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2232 &tss_seg.prev_task_link,
2233 sizeof tss_seg.prev_task_link,
0f65dd70 2234 &ctxt->exception);
db297e3d 2235 if (ret != X86EMUL_CONTINUE)
38ba30ba 2236 /* FIXME: need to provide precise fault address */
38ba30ba 2237 return ret;
38ba30ba
GN		 2238 }
2239
2240 return load_state_from_tss16(ctxt, ops, &tss_seg);
2241}
2242
2243static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2244 struct x86_emulate_ops *ops,
2245 struct tss_segment_32 *tss)
2246{
2247 struct decode_cache *c = &ctxt->decode;
2248
717746e3 2249 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2250 tss->eip = c->eip;
2251 tss->eflags = ctxt->eflags;
2252 tss->eax = c->regs[VCPU_REGS_RAX];
2253 tss->ecx = c->regs[VCPU_REGS_RCX];
2254 tss->edx = c->regs[VCPU_REGS_RDX];
2255 tss->ebx = c->regs[VCPU_REGS_RBX];
2256 tss->esp = c->regs[VCPU_REGS_RSP];
2257 tss->ebp = c->regs[VCPU_REGS_RBP];
2258 tss->esi = c->regs[VCPU_REGS_RSI];
2259 tss->edi = c->regs[VCPU_REGS_RDI];
2260
1aa36616
AK		 2261 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2262 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2263 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2264 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2265 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2266 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2267 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2268}
2269
2270static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2271 struct x86_emulate_ops *ops,
2272 struct tss_segment_32 *tss)
2273{
2274 struct decode_cache *c = &ctxt->decode;
2275 int ret;
2276
717746e3 2277 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2278 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2279 c->eip = tss->eip;
2280 ctxt->eflags = tss->eflags | 2;
2281 c->regs[VCPU_REGS_RAX] = tss->eax;
2282 c->regs[VCPU_REGS_RCX] = tss->ecx;
2283 c->regs[VCPU_REGS_RDX] = tss->edx;
2284 c->regs[VCPU_REGS_RBX] = tss->ebx;
2285 c->regs[VCPU_REGS_RSP] = tss->esp;
2286 c->regs[VCPU_REGS_RBP] = tss->ebp;
2287 c->regs[VCPU_REGS_RSI] = tss->esi;
2288 c->regs[VCPU_REGS_RDI] = tss->edi;
2289
2290 /*
2291 * SDM says that segment selectors are loaded before segment
2292 * descriptors
2293 */
1aa36616
AK		 2294 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2295 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2296 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2297 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2298 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2299 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2300 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2301
2302 /*
2303 * Now load segment descriptors. If fault happenes at this stage
2304 * it is handled in a context of new task
2305 */
2306 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2307 if (ret != X86EMUL_CONTINUE)
2308 return ret;
2309 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2310 if (ret != X86EMUL_CONTINUE)
2311 return ret;
2312 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2313 if (ret != X86EMUL_CONTINUE)
2314 return ret;
2315 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2316 if (ret != X86EMUL_CONTINUE)
2317 return ret;
2318 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2319 if (ret != X86EMUL_CONTINUE)
2320 return ret;
2321 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2322 if (ret != X86EMUL_CONTINUE)
2323 return ret;
2324 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2325 if (ret != X86EMUL_CONTINUE)
2326 return ret;
2327
2328 return X86EMUL_CONTINUE;
2329}
2330
2331static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2332 struct x86_emulate_ops *ops,
2333 u16 tss_selector, u16 old_tss_sel,
2334 ulong old_tss_base, struct desc_struct *new_desc)
2335{
2336 struct tss_segment_32 tss_seg;
2337 int ret;
bcc55cba 2338 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2339
0f65dd70 2340 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2341 &ctxt->exception);
db297e3d 2342 if (ret != X86EMUL_CONTINUE)
38ba30ba 2343 /* FIXME: need to provide precise fault address */
38ba30ba 2344 return ret;
38ba30ba
GN		 2345
2346 save_state_to_tss32(ctxt, ops, &tss_seg);
2347
0f65dd70 2348 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2349 &ctxt->exception);
db297e3d 2350 if (ret != X86EMUL_CONTINUE)
38ba30ba 2351 /* FIXME: need to provide precise fault address */
38ba30ba 2352 return ret;
38ba30ba 2353
0f65dd70 2354 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2355 &ctxt->exception);
db297e3d 2356 if (ret != X86EMUL_CONTINUE)
38ba30ba 2357 /* FIXME: need to provide precise fault address */
38ba30ba 2358 return ret;
38ba30ba
GN		 2359
2360 if (old_tss_sel != 0xffff) {
2361 tss_seg.prev_task_link = old_tss_sel;
2362
0f65dd70 2363 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2364 &tss_seg.prev_task_link,
2365 sizeof tss_seg.prev_task_link,
0f65dd70 2366 &ctxt->exception);
db297e3d 2367 if (ret != X86EMUL_CONTINUE)
38ba30ba 2368 /* FIXME: need to provide precise fault address */
38ba30ba 2369 return ret;
38ba30ba
GN		 2370 }
2371
2372 return load_state_from_tss32(ctxt, ops, &tss_seg);
2373}
2374
2375static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2376 struct x86_emulate_ops *ops,
2377 u16 tss_selector, int reason,
2378 bool has_error_code, u32 error_code)
38ba30ba
GN		 2379{
2380 struct desc_struct curr_tss_desc, next_tss_desc;
2381 int ret;
1aa36616 2382 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2383 ulong old_tss_base =
4bff1e86 2384 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2385 u32 desc_limit;
38ba30ba
GN		 2386
2387 /* FIXME: old_tss_base == ~0 ? */
2388
2389 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2390 if (ret != X86EMUL_CONTINUE)
2391 return ret;
2392 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2393 if (ret != X86EMUL_CONTINUE)
2394 return ret;
2395
2396 /* FIXME: check that next_tss_desc is tss */
2397
2398 if (reason != TASK_SWITCH_IRET) {
2399 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2400 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2401 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2402 }
2403
ceffb459
GN		 2404 desc_limit = desc_limit_scaled(&next_tss_desc);
2405 if (!next_tss_desc.p ||
2406 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2407 desc_limit < 0x2b)) {
54b8486f 2408 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2409 return X86EMUL_PROPAGATE_FAULT;
2410 }
2411
2412 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2413 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2414 write_segment_descriptor(ctxt, ops, old_tss_sel,
2415 &curr_tss_desc);
2416 }
2417
2418 if (reason == TASK_SWITCH_IRET)
2419 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2420
2421 /* set back link to prev task only if NT bit is set in eflags
2422 note that old_tss_sel is not used afetr this point */
2423 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2424 old_tss_sel = 0xffff;
2425
2426 if (next_tss_desc.type & 8)
2427 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2428 old_tss_base, &next_tss_desc);
2429 else
2430 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2431 old_tss_base, &next_tss_desc);
0760d448
JK		 2432 if (ret != X86EMUL_CONTINUE)
2433 return ret;
38ba30ba
GN		 2434
2435 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2436 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2437
2438 if (reason != TASK_SWITCH_IRET) {
2439 next_tss_desc.type |= (1 << 1); /* set busy flag */
2440 write_segment_descriptor(ctxt, ops, tss_selector,
2441 &next_tss_desc);
2442 }
2443
717746e3 2444 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2445 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2446
e269fb21
JK		 2447 if (has_error_code) {
2448 struct decode_cache *c = &ctxt->decode;
2449
2450 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2451 c->lock_prefix = 0;
2452 c->src.val = (unsigned long) error_code;
4487b3b4 2453 ret = em_push(ctxt);
e269fb21
JK		 2454 }
2455
38ba30ba
GN		 2456 return ret;
2457}
2458
2459int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2460 u16 tss_selector, int reason,
2461 bool has_error_code, u32 error_code)
38ba30ba 2462{
9aabc88f 2463 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2464 struct decode_cache *c = &ctxt->decode;
2465 int rc;
2466
38ba30ba 2467 c->eip = ctxt->eip;
e269fb21 2468 c->dst.type = OP_NONE;
38ba30ba 2469
e269fb21
JK		 2470 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2471 has_error_code, error_code);
38ba30ba 2472
4179bb02
TY		 2473 if (rc == X86EMUL_CONTINUE)
2474 ctxt->eip = c->eip;
38ba30ba 2475
a0c0ab2f 2476 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2477}
2478
90de84f5 2479static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2480 int reg, struct operand *op)
a682e354
GN		 2481{
2482 struct decode_cache *c = &ctxt->decode;
2483 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2484
d9271123 2485 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2486 op->addr.mem.ea = register_address(c, c->regs[reg]);
2487 op->addr.mem.seg = seg;
a682e354
GN		 2488}
2489
7af04fc0
AK		 2490static int em_das(struct x86_emulate_ctxt *ctxt)
2491{
2492 struct decode_cache *c = &ctxt->decode;
2493 u8 al, old_al;
2494 bool af, cf, old_cf;
2495
2496 cf = ctxt->eflags & X86_EFLAGS_CF;
2497 al = c->dst.val;
2498
2499 old_al = al;
2500 old_cf = cf;
2501 cf = false;
2502 af = ctxt->eflags & X86_EFLAGS_AF;
2503 if ((al & 0x0f) > 9 || af) {
2504 al -= 6;
2505 cf = old_cf | (al >= 250);
2506 af = true;
2507 } else {
2508 af = false;
2509 }
2510 if (old_al > 0x99 || old_cf) {
2511 al -= 0x60;
2512 cf = true;
2513 }
2514
2515 c->dst.val = al;
2516 /* Set PF, ZF, SF */
2517 c->src.type = OP_IMM;
2518 c->src.val = 0;
2519 c->src.bytes = 1;
2520 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2521 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2522 if (cf)
2523 ctxt->eflags |= X86_EFLAGS_CF;
2524 if (af)
2525 ctxt->eflags |= X86_EFLAGS_AF;
2526 return X86EMUL_CONTINUE;
2527}
2528
0ef753b8
AK		 2529static int em_call_far(struct x86_emulate_ctxt *ctxt)
2530{
2531 struct decode_cache *c = &ctxt->decode;
2532 u16 sel, old_cs;
2533 ulong old_eip;
2534 int rc;
2535
1aa36616 2536 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2537 old_eip = c->eip;
2538
2539 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2540 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2541 return X86EMUL_CONTINUE;
2542
2543 c->eip = 0;
2544 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2545
2546 c->src.val = old_cs;
4487b3b4 2547 rc = em_push(ctxt);
0ef753b8
AK		 2548 if (rc != X86EMUL_CONTINUE)
2549 return rc;
2550
2551 c->src.val = old_eip;
4487b3b4 2552 return em_push(ctxt);
0ef753b8
AK		 2553}
2554
40ece7c7
AK		 2555static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2556{
2557 struct decode_cache *c = &ctxt->decode;
2558 int rc;
2559
2560 c->dst.type = OP_REG;
2561 c->dst.addr.reg = &c->eip;
2562 c->dst.bytes = c->op_bytes;
3b9be3bf 2563 rc = emulate_pop(ctxt, &c->dst.val, c->op_bytes);
40ece7c7
AK		 2564 if (rc != X86EMUL_CONTINUE)
2565 return rc;
2566 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2567 return X86EMUL_CONTINUE;
2568}
2569
d67fc27a
TY		 2570static int em_add(struct x86_emulate_ctxt *ctxt)
2571{
2572 struct decode_cache *c = &ctxt->decode;
2573
2574 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2575 return X86EMUL_CONTINUE;
2576}
2577
2578static int em_or(struct x86_emulate_ctxt *ctxt)
2579{
2580 struct decode_cache *c = &ctxt->decode;
2581
2582 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2583 return X86EMUL_CONTINUE;
2584}
2585
2586static int em_adc(struct x86_emulate_ctxt *ctxt)
2587{
2588 struct decode_cache *c = &ctxt->decode;
2589
2590 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2591 return X86EMUL_CONTINUE;
2592}
2593
2594static int em_sbb(struct x86_emulate_ctxt *ctxt)
2595{
2596 struct decode_cache *c = &ctxt->decode;
2597
2598 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2599 return X86EMUL_CONTINUE;
2600}
2601
2602static int em_and(struct x86_emulate_ctxt *ctxt)
2603{
2604 struct decode_cache *c = &ctxt->decode;
2605
2606 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2607 return X86EMUL_CONTINUE;
2608}
2609
2610static int em_sub(struct x86_emulate_ctxt *ctxt)
2611{
2612 struct decode_cache *c = &ctxt->decode;
2613
2614 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2615 return X86EMUL_CONTINUE;
2616}
2617
2618static int em_xor(struct x86_emulate_ctxt *ctxt)
2619{
2620 struct decode_cache *c = &ctxt->decode;
2621
2622 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2623 return X86EMUL_CONTINUE;
2624}
2625
2626static int em_cmp(struct x86_emulate_ctxt *ctxt)
2627{
2628 struct decode_cache *c = &ctxt->decode;
2629
2630 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2631 /* Disable writeback. */
2632 c->dst.type = OP_NONE;
2633 return X86EMUL_CONTINUE;
2634}
2635
5c82aa29 2636static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2637{
2638 struct decode_cache *c = &ctxt->decode;
2639
f3a1b9f4
AK		 2640 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2641 return X86EMUL_CONTINUE;
2642}
2643
5c82aa29
AK		 2644static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2645{
2646 struct decode_cache *c = &ctxt->decode;
2647
2648 c->dst.val = c->src2.val;
2649 return em_imul(ctxt);
2650}
2651
61429142
AK		 2652static int em_cwd(struct x86_emulate_ctxt *ctxt)
2653{
2654 struct decode_cache *c = &ctxt->decode;
2655
2656 c->dst.type = OP_REG;
2657 c->dst.bytes = c->src.bytes;
2658 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2659 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2660
2661 return X86EMUL_CONTINUE;
2662}
2663
48bb5d3c
AK		 2664static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2665{
48bb5d3c
AK		 2666 struct decode_cache *c = &ctxt->decode;
2667 u64 tsc = 0;
2668
717746e3 2669 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2670 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2671 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2672 return X86EMUL_CONTINUE;
2673}
2674
b9eac5f4
AK		 2675static int em_mov(struct x86_emulate_ctxt *ctxt)
2676{
2677 struct decode_cache *c = &ctxt->decode;
2678 c->dst.val = c->src.val;
2679 return X86EMUL_CONTINUE;
2680}
2681
aa97bb48
AK		 2682static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2683{
2684 struct decode_cache *c = &ctxt->decode;
2685 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2686 return X86EMUL_CONTINUE;
2687}
2688
38503911
AK		 2689static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2690{
2691 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2692 int rc;
2693 ulong linear;
2694
83b8795a 2695 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2696 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2697 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2698 /* Disable writeback. */
2699 c->dst.type = OP_NONE;
2700 return X86EMUL_CONTINUE;
2701}
2702
2d04a05b
AK		 2703static int em_clts(struct x86_emulate_ctxt *ctxt)
2704{
2705 ulong cr0;
2706
2707 cr0 = ctxt->ops->get_cr(ctxt, 0);
2708 cr0 &= ~X86_CR0_TS;
2709 ctxt->ops->set_cr(ctxt, 0, cr0);
2710 return X86EMUL_CONTINUE;
2711}
2712
26d05cc7
AK		 2713static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2714{
2715 struct decode_cache *c = &ctxt->decode;
2716 int rc;
2717
2718 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2719 return X86EMUL_UNHANDLEABLE;
2720
2721 rc = ctxt->ops->fix_hypercall(ctxt);
2722 if (rc != X86EMUL_CONTINUE)
2723 return rc;
2724
2725 /* Let the processor re-execute the fixed hypercall */
2726 c->eip = ctxt->eip;
2727 /* Disable writeback. */
2728 c->dst.type = OP_NONE;
2729 return X86EMUL_CONTINUE;
2730}
2731
2732static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2733{
2734 struct decode_cache *c = &ctxt->decode;
2735 struct desc_ptr desc_ptr;
2736 int rc;
2737
509cf9fe 2738 rc = read_descriptor(ctxt, c->src.addr.mem,
26d05cc7
AK		 2739 &desc_ptr.size, &desc_ptr.address,
2740 c->op_bytes);
2741 if (rc != X86EMUL_CONTINUE)
2742 return rc;
2743 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2744 /* Disable writeback. */
2745 c->dst.type = OP_NONE;
2746 return X86EMUL_CONTINUE;
2747}
2748
5ef39c71 2749static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2750{
2751 struct decode_cache *c = &ctxt->decode;
2752 int rc;
2753
5ef39c71
AK		 2754 rc = ctxt->ops->fix_hypercall(ctxt);
2755
26d05cc7
AK		 2756 /* Disable writeback. */
2757 c->dst.type = OP_NONE;
2758 return rc;
2759}
2760
2761static int em_lidt(struct x86_emulate_ctxt *ctxt)
2762{
2763 struct decode_cache *c = &ctxt->decode;
2764 struct desc_ptr desc_ptr;
2765 int rc;
2766
509cf9fe
TY		 2767 rc = read_descriptor(ctxt, c->src.addr.mem,
2768 &desc_ptr.size, &desc_ptr.address,
26d05cc7
AK		 2769 c->op_bytes);
2770 if (rc != X86EMUL_CONTINUE)
2771 return rc;
2772 ctxt->ops->set_idt(ctxt, &desc_ptr);
2773 /* Disable writeback. */
2774 c->dst.type = OP_NONE;
2775 return X86EMUL_CONTINUE;
2776}
2777
2778static int em_smsw(struct x86_emulate_ctxt *ctxt)
2779{
2780 struct decode_cache *c = &ctxt->decode;
2781
2782 c->dst.bytes = 2;
2783 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2784 return X86EMUL_CONTINUE;
2785}
2786
2787static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2788{
2789 struct decode_cache *c = &ctxt->decode;
2790 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2791 | (c->src.val & 0x0f));
2792 c->dst.type = OP_NONE;
2793 return X86EMUL_CONTINUE;
2794}
2795
cfec82cb
JR		 2796static bool valid_cr(int nr)
2797{
2798 switch (nr) {
2799 case 0:
2800 case 2 ... 4:
2801 case 8:
2802 return true;
2803 default:
2804 return false;
2805 }
2806}
2807
2808static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2809{
2810 struct decode_cache *c = &ctxt->decode;
2811
2812 if (!valid_cr(c->modrm_reg))
2813 return emulate_ud(ctxt);
2814
2815 return X86EMUL_CONTINUE;
2816}
2817
2818static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2819{
2820 struct decode_cache *c = &ctxt->decode;
2821 u64 new_val = c->src.val64;
2822 int cr = c->modrm_reg;
c2ad2bb3 2823 u64 efer = 0;
cfec82cb
JR		 2824
2825 static u64 cr_reserved_bits[] = {
2826 0xffffffff00000000ULL,
2827 0, 0, 0, /* CR3 checked later */
2828 CR4_RESERVED_BITS,
2829 0, 0, 0,
2830 CR8_RESERVED_BITS,
2831 };
2832
2833 if (!valid_cr(cr))
2834 return emulate_ud(ctxt);
2835
2836 if (new_val & cr_reserved_bits[cr])
2837 return emulate_gp(ctxt, 0);
2838
2839 switch (cr) {
2840 case 0: {
c2ad2bb3 2841 u64 cr4;
cfec82cb
JR		 2842 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2843 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2844 return emulate_gp(ctxt, 0);
2845
717746e3
AK		 2846 cr4 = ctxt->ops->get_cr(ctxt, 4);
2847 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2848
2849 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2850 !(cr4 & X86_CR4_PAE))
2851 return emulate_gp(ctxt, 0);
2852
2853 break;
2854 }
2855 case 3: {
2856 u64 rsvd = 0;
2857
c2ad2bb3
AK		 2858 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2859 if (efer & EFER_LMA)
cfec82cb 2860 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2861 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2862 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2863 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2864 rsvd = CR3_NONPAE_RESERVED_BITS;
2865
2866 if (new_val & rsvd)
2867 return emulate_gp(ctxt, 0);
2868
2869 break;
2870 }
2871 case 4: {
c2ad2bb3 2872 u64 cr4;
cfec82cb 2873
717746e3
AK		 2874 cr4 = ctxt->ops->get_cr(ctxt, 4);
2875 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2876
2877 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2878 return emulate_gp(ctxt, 0);
2879
2880 break;
2881 }
2882 }
2883
2884 return X86EMUL_CONTINUE;
2885}
2886
3b88e41a
JR		 2887static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2888{
2889 unsigned long dr7;
2890
717746e3 2891 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2892
2893 /* Check if DR7.Global_Enable is set */
2894 return dr7 & (1 << 13);
2895}
2896
2897static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2898{
2899 struct decode_cache *c = &ctxt->decode;
2900 int dr = c->modrm_reg;
2901 u64 cr4;
2902
2903 if (dr > 7)
2904 return emulate_ud(ctxt);
2905
717746e3 2906 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2907 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2908 return emulate_ud(ctxt);
2909
2910 if (check_dr7_gd(ctxt))
2911 return emulate_db(ctxt);
2912
2913 return X86EMUL_CONTINUE;
2914}
2915
2916static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2917{
2918 struct decode_cache *c = &ctxt->decode;
2919 u64 new_val = c->src.val64;
2920 int dr = c->modrm_reg;
2921
2922 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2923 return emulate_gp(ctxt, 0);
2924
2925 return check_dr_read(ctxt);
2926}
2927
01de8b09
JR		 2928static int check_svme(struct x86_emulate_ctxt *ctxt)
2929{
2930 u64 efer;
2931
717746e3 2932 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2933
2934 if (!(efer & EFER_SVME))
2935 return emulate_ud(ctxt);
2936
2937 return X86EMUL_CONTINUE;
2938}
2939
2940static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2941{
fe870ab9 2942 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2943
2944 /* Valid physical address? */
d4224449 2945 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2946 return emulate_gp(ctxt, 0);
2947
2948 return check_svme(ctxt);
2949}
2950
d7eb8203
JR		 2951static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2952{
717746e3 2953 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2954
717746e3 2955 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2956 return emulate_ud(ctxt);
2957
2958 return X86EMUL_CONTINUE;
2959}
2960
8061252e
JR		 2961static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2962{
717746e3 2963 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2964 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2965
717746e3 2966 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2967 (rcx > 3))
2968 return emulate_gp(ctxt, 0);
2969
2970 return X86EMUL_CONTINUE;
2971}
2972
f6511935
JR		 2973static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2974{
2975 struct decode_cache *c = &ctxt->decode;
2976
2977 c->dst.bytes = min(c->dst.bytes, 4u);
2978 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2979 return emulate_gp(ctxt, 0);
2980
2981 return X86EMUL_CONTINUE;
2982}
2983
2984static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2985{
2986 struct decode_cache *c = &ctxt->decode;
2987
2988 c->src.bytes = min(c->src.bytes, 4u);
2989 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2990 return emulate_gp(ctxt, 0);
2991
2992 return X86EMUL_CONTINUE;
2993}
2994
73fba5f4 2995#define D(_y) { .flags = (_y) }
c4f035c6 2996#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2997#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2998 .check_perm = (_p) }
73fba5f4 2999#define N D(0)
01de8b09 3000#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 3001#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3002#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3003#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3004#define II(_f, _e, _i) \
3005 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3006#define IIP(_f, _e, _i, _p) \
3007 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3008 .check_perm = (_p) }
aa97bb48 3009#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3010
8d8f4e9f 3011#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3012#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 3013#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3014
d67fc27a
TY		 3015#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3016 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3017 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3018
d7eb8203
JR		 3019static struct opcode group7_rm1[] = {
3020 DI(SrcNone | ModRM | Priv, monitor),
3021 DI(SrcNone | ModRM | Priv, mwait),
3022 N, N, N, N, N, N,
3023};
3024
01de8b09
JR		 3025static struct opcode group7_rm3[] = {
3026 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3027 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3028 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3029 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3030 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3031 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3032 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3033 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3034};
6230f7fc 3035
d7eb8203
JR		 3036static struct opcode group7_rm7[] = {
3037 N,
3038 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3039 N, N, N, N, N, N,
3040};
d67fc27a 3041
73fba5f4 3042static struct opcode group1[] = {
d67fc27a
TY		 3043 I(Lock, em_add),
3044 I(Lock, em_or),
3045 I(Lock, em_adc),
3046 I(Lock, em_sbb),
3047 I(Lock, em_and),
3048 I(Lock, em_sub),
3049 I(Lock, em_xor),
3050 I(0, em_cmp),
73fba5f4
AK		 3051};
3052
3053static struct opcode group1A[] = {
3054 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3055};
3056
3057static struct opcode group3[] = {
3058 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3059 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3060 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3061};
3062
3063static struct opcode group4[] = {
3064 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3065 N, N, N, N, N, N,
3066};
3067
3068static struct opcode group5[] = {
3069 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3070 D(SrcMem | ModRM | Stack),
3071 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3072 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3073 D(SrcMem | ModRM | Stack), N,
3074};
3075
dee6bb70
JR		 3076static struct opcode group6[] = {
3077 DI(ModRM | Prot, sldt),
3078 DI(ModRM | Prot, str),
3079 DI(ModRM | Prot | Priv, lldt),
3080 DI(ModRM | Prot | Priv, ltr),
3081 N, N, N, N,
3082};
3083
73fba5f4 3084static struct group_dual group7 = { {
dee6bb70
JR		 3085 DI(ModRM | Mov | DstMem | Priv, sgdt),
3086 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3087 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3088 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3089 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3090 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3091 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3092}, {
5ef39c71
AK		 3093 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3094 EXT(0, group7_rm1),
01de8b09 3095 N, EXT(0, group7_rm3),
5ef39c71
AK		 3096 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3097 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3098} };
3099
3100static struct opcode group8[] = {
3101 N, N, N, N,
3102 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3103 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3104};
3105
3106static struct group_dual group9 = { {
3107 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3108}, {
3109 N, N, N, N, N, N, N, N,
3110} };
3111
a4d4a7c1
AK		 3112static struct opcode group11[] = {
3113 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3114};
3115
aa97bb48
AK		 3116static struct gprefix pfx_0f_6f_0f_7f = {
3117 N, N, N, I(Sse, em_movdqu),
3118};
3119
73fba5f4
AK		 3120static struct opcode opcode_table[256] = {
3121 /* 0x00 - 0x07 */
d67fc27a 3122 I6ALU(Lock, em_add),
73fba5f4
AK		 3123 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3124 /* 0x08 - 0x0F */
d67fc27a 3125 I6ALU(Lock, em_or),
73fba5f4
AK		 3126 D(ImplicitOps | Stack | No64), N,
3127 /* 0x10 - 0x17 */
d67fc27a 3128 I6ALU(Lock, em_adc),
73fba5f4
AK		 3129 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3130 /* 0x18 - 0x1F */
d67fc27a 3131 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3132 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3133 /* 0x20 - 0x27 */
d67fc27a 3134 I6ALU(Lock, em_and), N, N,
73fba5f4 3135 /* 0x28 - 0x2F */
d67fc27a 3136 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3137 /* 0x30 - 0x37 */
d67fc27a 3138 I6ALU(Lock, em_xor), N, N,
73fba5f4 3139 /* 0x38 - 0x3F */
d67fc27a 3140 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3141 /* 0x40 - 0x4F */
3142 X16(D(DstReg)),
3143 /* 0x50 - 0x57 */
63540382 3144 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3145 /* 0x58 - 0x5F */
c54fe504 3146 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3147 /* 0x60 - 0x67 */
b96a7fad
TY		 3148 I(ImplicitOps | Stack | No64, em_pusha),
3149 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3150 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3151 N, N, N, N,
3152 /* 0x68 - 0x6F */
d46164db
AK		 3153 I(SrcImm | Mov | Stack, em_push),
3154 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3155 I(SrcImmByte | Mov | Stack, em_push),
3156 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 3157 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3158 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3159 /* 0x70 - 0x7F */
3160 X16(D(SrcImmByte)),
3161 /* 0x80 - 0x87 */
3162 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3163 G(DstMem | SrcImm | ModRM | Group, group1),
3164 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3165 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3166 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3167 /* 0x88 - 0x8F */
b9eac5f4
AK		 3168 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3169 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3170 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3171 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3172 /* 0x90 - 0x97 */
bf608f88 3173 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3174 /* 0x98 - 0x9F */
61429142 3175 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3176 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3177 II(ImplicitOps | Stack, em_pushf, pushf),
3178 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3179 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3180 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3181 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3182 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3183 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3184 /* 0xA8 - 0xAF */
50748613 3185 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3186 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3187 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3188 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3189 /* 0xB0 - 0xB7 */
b9eac5f4 3190 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3191 /* 0xB8 - 0xBF */
b9eac5f4 3192 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3193 /* 0xC0 - 0xC7 */
d2c6c7ad 3194 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3195 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3196 D(ImplicitOps | Stack),
09b5f4d3 3197 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3198 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3199 /* 0xC8 - 0xCF */
3200 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3201 D(ImplicitOps), DI(SrcImmByte, intn),
3202 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3203 /* 0xD0 - 0xD7 */
d2c6c7ad 3204 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3205 N, N, N, N,
3206 /* 0xD8 - 0xDF */
3207 N, N, N, N, N, N, N, N,
3208 /* 0xE0 - 0xE7 */
e4abac67 3209 X4(D(SrcImmByte)),
f6511935
JR		 3210 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3211 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3212 /* 0xE8 - 0xEF */
3213 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3214 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 3215 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3216 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 3217 /* 0xF0 - 0xF7 */
bf608f88 3218 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3219 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3220 G(ByteOp, group3), G(0, group3),
73fba5f4 3221 /* 0xF8 - 0xFF */
8744aa9a 3222 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3223 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3224};
3225
3226static struct opcode twobyte_table[256] = {
3227 /* 0x00 - 0x0F */
dee6bb70 3228 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3229 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3230 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3231 N, D(ImplicitOps | ModRM), N, N,
3232 /* 0x10 - 0x1F */
3233 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3234 /* 0x20 - 0x2F */
cfec82cb 3235 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3236 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3237 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3238 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3239 N, N, N, N,
3240 N, N, N, N, N, N, N, N,
3241 /* 0x30 - 0x3F */
8061252e
JR		 3242 DI(ImplicitOps | Priv, wrmsr),
3243 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3244 DI(ImplicitOps | Priv, rdmsr),
3245 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3246 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3247 N, N,
73fba5f4
AK		 3248 N, N, N, N, N, N, N, N,
3249 /* 0x40 - 0x4F */
3250 X16(D(DstReg | SrcMem | ModRM | Mov)),
3251 /* 0x50 - 0x5F */
3252 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3253 /* 0x60 - 0x6F */
aa97bb48
AK		 3254 N, N, N, N,
3255 N, N, N, N,
3256 N, N, N, N,
3257 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3258 /* 0x70 - 0x7F */
aa97bb48
AK		 3259 N, N, N, N,
3260 N, N, N, N,
3261 N, N, N, N,
3262 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3263 /* 0x80 - 0x8F */
3264 X16(D(SrcImm)),
3265 /* 0x90 - 0x9F */
ee45b58e 3266 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3267 /* 0xA0 - 0xA7 */
3268 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3269 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3270 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3271 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3272 /* 0xA8 - 0xAF */
3273 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3274 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3275 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3276 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3277 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3278 /* 0xB0 - 0xB7 */
739ae406 3279 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3280 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3281 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3282 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3283 /* 0xB8 - 0xBF */
3284 N, N,
ba7ff2b7 3285 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3286 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3287 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3288 /* 0xC0 - 0xCF */
739ae406 3289 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3290 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3291 N, N, N, GD(0, &group9),
3292 N, N, N, N, N, N, N, N,
3293 /* 0xD0 - 0xDF */
3294 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3295 /* 0xE0 - 0xEF */
3296 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3297 /* 0xF0 - 0xFF */
3298 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3299};
3300
3301#undef D
3302#undef N
3303#undef G
3304#undef GD
3305#undef I
aa97bb48 3306#undef GP
01de8b09 3307#undef EXT
73fba5f4 3308
8d8f4e9f 3309#undef D2bv
f6511935 3310#undef D2bvIP
8d8f4e9f 3311#undef I2bv
d67fc27a 3312#undef I6ALU
8d8f4e9f 3313
39f21ee5
AK		 3314static unsigned imm_size(struct decode_cache *c)
3315{
3316 unsigned size;
3317
3318 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3319 if (size == 8)
3320 size = 4;
3321 return size;
3322}
3323
3324static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3325 unsigned size, bool sign_extension)
3326{
3327 struct decode_cache *c = &ctxt->decode;
3328 struct x86_emulate_ops *ops = ctxt->ops;
3329 int rc = X86EMUL_CONTINUE;
3330
3331 op->type = OP_IMM;
3332 op->bytes = size;
90de84f5 3333 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3334 /* NB. Immediates are sign-extended as necessary. */
3335 switch (op->bytes) {
3336 case 1:
3337 op->val = insn_fetch(s8, 1, c->eip);
3338 break;
3339 case 2:
3340 op->val = insn_fetch(s16, 2, c->eip);
3341 break;
3342 case 4:
3343 op->val = insn_fetch(s32, 4, c->eip);
3344 break;
3345 }
3346 if (!sign_extension) {
3347 switch (op->bytes) {
3348 case 1:
3349 op->val &= 0xff;
3350 break;
3351 case 2:
3352 op->val &= 0xffff;
3353 break;
3354 case 4:
3355 op->val &= 0xffffffff;
3356 break;
3357 }
3358 }
3359done:
3360 return rc;
3361}
3362
dde7e6d1 3363int
dc25e89e 3364x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3365{
3366 struct x86_emulate_ops *ops = ctxt->ops;
3367 struct decode_cache *c = &ctxt->decode;
3368 int rc = X86EMUL_CONTINUE;
3369 int mode = ctxt->mode;
46561646 3370 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3371 bool op_prefix = false;
46561646 3372 struct opcode opcode;
2dbd0dd7 3373 struct operand memop = { .type = OP_NONE };
dde7e6d1 3374
dde7e6d1 3375 c->eip = ctxt->eip;
dc25e89e
AP		 3376 c->fetch.start = c->eip;
3377 c->fetch.end = c->fetch.start + insn_len;
3378 if (insn_len > 0)
3379 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3380
3381 switch (mode) {
3382 case X86EMUL_MODE_REAL:
3383 case X86EMUL_MODE_VM86:
3384 case X86EMUL_MODE_PROT16:
3385 def_op_bytes = def_ad_bytes = 2;
3386 break;
3387 case X86EMUL_MODE_PROT32:
3388 def_op_bytes = def_ad_bytes = 4;
3389 break;
3390#ifdef CONFIG_X86_64
3391 case X86EMUL_MODE_PROT64:
3392 def_op_bytes = 4;
3393 def_ad_bytes = 8;
3394 break;
3395#endif
3396 default:
3397 return -1;
3398 }
3399
3400 c->op_bytes = def_op_bytes;
3401 c->ad_bytes = def_ad_bytes;
3402
3403 /* Legacy prefixes. */
3404 for (;;) {
3405 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3406 case 0x66: /* operand-size override */
0d7cdee8 3407 op_prefix = true;
dde7e6d1
AK		 3408 /* switch between 2/4 bytes */
3409 c->op_bytes = def_op_bytes ^ 6;
3410 break;
3411 case 0x67: /* address-size override */
3412 if (mode == X86EMUL_MODE_PROT64)
3413 /* switch between 4/8 bytes */
3414 c->ad_bytes = def_ad_bytes ^ 12;
3415 else
3416 /* switch between 2/4 bytes */
3417 c->ad_bytes = def_ad_bytes ^ 6;
3418 break;
3419 case 0x26: /* ES override */
3420 case 0x2e: /* CS override */
3421 case 0x36: /* SS override */
3422 case 0x3e: /* DS override */
3423 set_seg_override(c, (c->b >> 3) & 3);
3424 break;
3425 case 0x64: /* FS override */
3426 case 0x65: /* GS override */
3427 set_seg_override(c, c->b & 7);
3428 break;
3429 case 0x40 ... 0x4f: /* REX */
3430 if (mode != X86EMUL_MODE_PROT64)
3431 goto done_prefixes;
3432 c->rex_prefix = c->b;
3433 continue;
3434 case 0xf0: /* LOCK */
3435 c->lock_prefix = 1;
3436 break;
3437 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3438 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3439 c->rep_prefix = c->b;
dde7e6d1
AK		 3440 break;
3441 default:
3442 goto done_prefixes;
3443 }
3444
3445 /* Any legacy prefix after a REX prefix nullifies its effect. */
3446
3447 c->rex_prefix = 0;
3448 }
3449
3450done_prefixes:
3451
3452 /* REX prefix. */
1e87e3ef
AK		 3453 if (c->rex_prefix & 8)
3454 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3455
3456 /* Opcode byte(s). */
3457 opcode = opcode_table[c->b];
d3ad6243
WY		 3458 /* Two-byte opcode? */
3459 if (c->b == 0x0f) {
3460 c->twobyte = 1;
3461 c->b = insn_fetch(u8, 1, c->eip);
3462 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3463 }
3464 c->d = opcode.flags;
3465
46561646
AK		 3466 while (c->d & GroupMask) {
3467 switch (c->d & GroupMask) {
3468 case Group:
3469 c->modrm = insn_fetch(u8, 1, c->eip);
3470 --c->eip;
3471 goffset = (c->modrm >> 3) & 7;
3472 opcode = opcode.u.group[goffset];
3473 break;
3474 case GroupDual:
3475 c->modrm = insn_fetch(u8, 1, c->eip);
3476 --c->eip;
3477 goffset = (c->modrm >> 3) & 7;
3478 if ((c->modrm >> 6) == 3)
3479 opcode = opcode.u.gdual->mod3[goffset];
3480 else
3481 opcode = opcode.u.gdual->mod012[goffset];
3482 break;
3483 case RMExt:
01de8b09
JR		 3484 goffset = c->modrm & 7;
3485 opcode = opcode.u.group[goffset];
46561646
AK		 3486 break;
3487 case Prefix:
3488 if (c->rep_prefix && op_prefix)
3489 return X86EMUL_UNHANDLEABLE;
3490 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3491 switch (simd_prefix) {
3492 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3493 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3494 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3495 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3496 }
3497 break;
3498 default:
0d7cdee8 3499 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3500 }
46561646
AK		 3501
3502 c->d &= ~GroupMask;
0d7cdee8
AK		 3503 c->d |= opcode.flags;
3504 }
3505
dde7e6d1 3506 c->execute = opcode.u.execute;
d09beabd 3507 c->check_perm = opcode.check_perm;
c4f035c6 3508 c->intercept = opcode.intercept;
dde7e6d1
AK		 3509
3510 /* Unrecognised? */
d53db5ef 3511 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3512 return -1;
dde7e6d1 3513
d867162c
AK		 3514 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3515 return -1;
3516
dde7e6d1
AK		 3517 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3518 c->op_bytes = 8;
3519
7f9b4b75
AK		 3520 if (c->d & Op3264) {
3521 if (mode == X86EMUL_MODE_PROT64)
3522 c->op_bytes = 8;
3523 else
3524 c->op_bytes = 4;
3525 }
3526
1253791d
AK		 3527 if (c->d & Sse)
3528 c->op_bytes = 16;
3529
dde7e6d1 3530 /* ModRM and SIB bytes. */
09ee57cd 3531 if (c->d & ModRM) {
2dbd0dd7 3532 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3533 if (!c->has_seg_override)
3534 set_seg_override(c, c->modrm_seg);
3535 } else if (c->d & MemAbs)
2dbd0dd7 3536 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3537 if (rc != X86EMUL_CONTINUE)
3538 goto done;
3539
3540 if (!c->has_seg_override)
3541 set_seg_override(c, VCPU_SREG_DS);
3542
c1ed6dea 3543 memop.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1 3544
2dbd0dd7 3545 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3546 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3547
2dbd0dd7 3548 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3549 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3550
3551 /*
3552 * Decode and fetch the source operand: register, memory
3553 * or immediate.
3554 */
3555 switch (c->d & SrcMask) {
3556 case SrcNone:
3557 break;
3558 case SrcReg:
1253791d 3559 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3560 break;
3561 case SrcMem16:
2dbd0dd7 3562 memop.bytes = 2;
dde7e6d1
AK		 3563 goto srcmem_common;
3564 case SrcMem32:
2dbd0dd7 3565 memop.bytes = 4;
dde7e6d1
AK		 3566 goto srcmem_common;
3567 case SrcMem:
2dbd0dd7 3568 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3569 c->op_bytes;
dde7e6d1 3570 srcmem_common:
2dbd0dd7 3571 c->src = memop;
dde7e6d1 3572 break;
b250e605 3573 case SrcImmU16:
39f21ee5
AK		 3574 rc = decode_imm(ctxt, &c->src, 2, false);
3575 break;
dde7e6d1 3576 case SrcImm:
39f21ee5
AK		 3577 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3578 break;
dde7e6d1 3579 case SrcImmU:
39f21ee5 3580 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3581 break;
3582 case SrcImmByte:
39f21ee5
AK		 3583 rc = decode_imm(ctxt, &c->src, 1, true);
3584 break;
dde7e6d1 3585 case SrcImmUByte:
39f21ee5 3586 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3587 break;
3588 case SrcAcc:
3589 c->src.type = OP_REG;
3590 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3591 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3592 fetch_register_operand(&c->src);
dde7e6d1
AK		 3593 break;
3594 case SrcOne:
3595 c->src.bytes = 1;
3596 c->src.val = 1;
3597 break;
3598 case SrcSI:
3599 c->src.type = OP_MEM;
3600 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3601 c->src.addr.mem.ea =
3602 register_address(c, c->regs[VCPU_REGS_RSI]);
c1ed6dea 3603 c->src.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1
AK		 3604 c->src.val = 0;
3605 break;
3606 case SrcImmFAddr:
3607 c->src.type = OP_IMM;
90de84f5 3608 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3609 c->src.bytes = c->op_bytes + 2;
3610 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3611 break;
3612 case SrcMemFAddr:
2dbd0dd7
AK		 3613 memop.bytes = c->op_bytes + 2;
3614 goto srcmem_common;
dde7e6d1
AK		 3615 break;
3616 }
3617
39f21ee5
AK		 3618 if (rc != X86EMUL_CONTINUE)
3619 goto done;
3620
dde7e6d1
AK		 3621 /*
3622 * Decode and fetch the second source operand: register, memory
3623 * or immediate.
3624 */
3625 switch (c->d & Src2Mask) {
3626 case Src2None:
3627 break;
3628 case Src2CL:
3629 c->src2.bytes = 1;
3630 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3631 break;
3632 case Src2ImmByte:
39f21ee5 3633 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3634 break;
3635 case Src2One:
3636 c->src2.bytes = 1;
3637 c->src2.val = 1;
3638 break;
7db41eb7
AK		 3639 case Src2Imm:
3640 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3641 break;
dde7e6d1
AK		 3642 }
3643
39f21ee5
AK		 3644 if (rc != X86EMUL_CONTINUE)
3645 goto done;
3646
dde7e6d1
AK		 3647 /* Decode and fetch the destination operand: register or memory. */
3648 switch (c->d & DstMask) {
dde7e6d1 3649 case DstReg:
1253791d 3650 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3651 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3652 break;
943858e2
WY		 3653 case DstImmUByte:
3654 c->dst.type = OP_IMM;
90de84f5 3655 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3656 c->dst.bytes = 1;
3657 c->dst.val = insn_fetch(u8, 1, c->eip);
3658 break;
dde7e6d1
AK		 3659 case DstMem:
3660 case DstMem64:
2dbd0dd7 3661 c->dst = memop;
dde7e6d1
AK		 3662 if ((c->d & DstMask) == DstMem64)
3663 c->dst.bytes = 8;
3664 else
3665 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3666 if (c->d & BitOp)
3667 fetch_bit_operand(c);
2dbd0dd7 3668 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3669 break;
3670 case DstAcc:
3671 c->dst.type = OP_REG;
3672 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3673 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3674 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3675 c->dst.orig_val = c->dst.val;
3676 break;
3677 case DstDI:
3678 c->dst.type = OP_MEM;
3679 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3680 c->dst.addr.mem.ea =
3681 register_address(c, c->regs[VCPU_REGS_RDI]);
3682 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3683 c->dst.val = 0;
3684 break;
36089fed
WY		 3685 case ImplicitOps:
3686 /* Special instructions do their own operand decoding. */
3687 default:
3688 c->dst.type = OP_NONE; /* Disable writeback. */
3689 return 0;
dde7e6d1
AK		 3690 }
3691
3692done:
a0c0ab2f 3693 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3694}
3695
3e2f65d5
GN		 3696static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3697{
3698 struct decode_cache *c = &ctxt->decode;
3699
3700 /* The second termination condition only applies for REPE
3701 * and REPNE. Test if the repeat string operation prefix is
3702 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3703 * corresponding termination condition according to:
3704 * - if REPE/REPZ and ZF = 0 then done
3705 * - if REPNE/REPNZ and ZF = 1 then done
3706 */
3707 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3708 (c->b == 0xae) || (c->b == 0xaf))
3709 && (((c->rep_prefix == REPE_PREFIX) &&
3710 ((ctxt->eflags & EFLG_ZF) == 0))
3711 || ((c->rep_prefix == REPNE_PREFIX) &&
3712 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3713 return true;
3714
3715 return false;
3716}
3717
8b4caf66 3718int
9aabc88f 3719x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3720{
9aabc88f 3721 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3722 u64 msr_data;
8b4caf66 3723 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3724 int rc = X86EMUL_CONTINUE;
5cd21917 3725 int saved_dst_type = c->dst.type;
6e154e56 3726 int irq; /* Used for int 3, int, and into */
8b4caf66 3727
9de41573 3728 ctxt->decode.mem_read.pos = 0;
310b5d30 3729
1161624f 3730 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3731 rc = emulate_ud(ctxt);
1161624f
GN		 3732 goto done;
3733 }
3734
d380a5e4 3735 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3736 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3737 rc = emulate_ud(ctxt);
d380a5e4
GN		 3738 goto done;
3739 }
3740
081bca0e 3741 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3742 rc = emulate_ud(ctxt);
081bca0e
AK		 3743 goto done;
3744 }
3745
1253791d 3746 if ((c->d & Sse)
717746e3
AK		 3747 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3748 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3749 rc = emulate_ud(ctxt);
3750 goto done;
3751 }
3752
717746e3 3753 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3754 rc = emulate_nm(ctxt);
3755 goto done;
3756 }
3757
c4f035c6 3758 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3759 rc = emulator_check_intercept(ctxt, c->intercept,
3760 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3761 if (rc != X86EMUL_CONTINUE)
3762 goto done;
3763 }
3764
e92805ac 3765 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3766 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3767 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3768 goto done;
3769 }
3770
8ea7d6ae
JR		 3771 /* Instruction can only be executed in protected mode */
3772 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3773 rc = emulate_ud(ctxt);
3774 goto done;
3775 }
3776
d09beabd
JR		 3777 /* Do instruction specific permission checks */
3778 if (c->check_perm) {
3779 rc = c->check_perm(ctxt);
3780 if (rc != X86EMUL_CONTINUE)
3781 goto done;
3782 }
3783
c4f035c6 3784 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3785 rc = emulator_check_intercept(ctxt, c->intercept,
3786 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3787 if (rc != X86EMUL_CONTINUE)
3788 goto done;
3789 }
3790
b9fa9d6b
AK		 3791 if (c->rep_prefix && (c->d & String)) {
3792 /* All REP prefixes have the same first termination condition */
c73e197b 3793 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3794 ctxt->eip = c->eip;
b9fa9d6b
AK		 3795 goto done;
3796 }
b9fa9d6b
AK		 3797 }
3798
c483c02a 3799 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3800 rc = segmented_read(ctxt, c->src.addr.mem,
3801 c->src.valptr, c->src.bytes);
b60d513c 3802 if (rc != X86EMUL_CONTINUE)
8b4caf66 3803 goto done;
16518d5a 3804 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3805 }
3806
e35b7b9c 3807 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3808 rc = segmented_read(ctxt, c->src2.addr.mem,
3809 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3810 if (rc != X86EMUL_CONTINUE)
3811 goto done;
3812 }
3813
8b4caf66
LV		 3814 if ((c->d & DstMask) == ImplicitOps)
3815 goto special_insn;
3816
3817
69f55cb1
GN		 3818 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3819 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3820 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3821 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3822 if (rc != X86EMUL_CONTINUE)
3823 goto done;
038e51de 3824 }
e4e03ded 3825 c->dst.orig_val = c->dst.val;
038e51de 3826
018a98db
AK		 3827special_insn:
3828
c4f035c6 3829 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3830 rc = emulator_check_intercept(ctxt, c->intercept,
3831 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3832 if (rc != X86EMUL_CONTINUE)
3833 goto done;
3834 }
3835
ef65c889
AK		 3836 if (c->execute) {
3837 rc = c->execute(ctxt);
3838 if (rc != X86EMUL_CONTINUE)
3839 goto done;
3840 goto writeback;
3841 }
3842
e4e03ded 3843 if (c->twobyte)
6aa8b732
AK		 3844 goto twobyte_insn;
3845
e4e03ded 3846 switch (c->b) {
0934ac9d 3847 case 0x06: /* push es */
4179bb02 3848 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3849 break;
3850 case 0x07: /* pop es */
0934ac9d 3851 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3852 break;
0934ac9d 3853 case 0x0e: /* push cs */
4179bb02 3854 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3855 break;
0934ac9d 3856 case 0x16: /* push ss */
4179bb02 3857 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3858 break;
3859 case 0x17: /* pop ss */
0934ac9d 3860 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3861 break;
0934ac9d 3862 case 0x1e: /* push ds */
4179bb02 3863 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3864 break;
3865 case 0x1f: /* pop ds */
0934ac9d 3866 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3867 break;
33615aa9
AK		 3868 case 0x40 ... 0x47: /* inc r16/r32 */
3869 emulate_1op("inc", c->dst, ctxt->eflags);
3870 break;
3871 case 0x48 ... 0x4f: /* dec r16/r32 */
3872 emulate_1op("dec", c->dst, ctxt->eflags);
3873 break;
6aa8b732 3874 case 0x63: /* movsxd */
8b4caf66 3875 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3876 goto cannot_emulate;
e4e03ded 3877 c->dst.val = (s32) c->src.val;
6aa8b732 3878 break;
018a98db
AK		 3879 case 0x6c: /* insb */
3880 case 0x6d: /* insw/insd */
a13a63fa
WY		 3881 c->src.val = c->regs[VCPU_REGS_RDX];
3882 goto do_io_in;
018a98db
AK		 3883 case 0x6e: /* outsb */
3884 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3885 c->dst.val = c->regs[VCPU_REGS_RDX];
3886 goto do_io_out;
7972995b 3887 break;
b2833e3c 3888 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3889 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3890 jmp_rel(c, c->src.val);
018a98db 3891 break;
6aa8b732 3892 case 0x84 ... 0x85:
dfb507c4 3893 test:
05f086f8 3894 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3895 break;
3896 case 0x86 ... 0x87: /* xchg */
b13354f8 3897 xchg:
6aa8b732 3898 /* Write back the register source. */
31be40b3
WY		 3899 c->src.val = c->dst.val;
3900 write_register_operand(&c->src);
6aa8b732
AK		 3901 /*
3902 * Write back the memory destination with implicit LOCK
3903 * prefix.
3904 */
31be40b3 3905 c->dst.val = c->src.orig_val;
e4e03ded 3906 c->lock_prefix = 1;
6aa8b732 3907 break;
79168fd1
GN		 3908 case 0x8c: /* mov r/m, sreg */
3909 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3910 rc = emulate_ud(ctxt);
5e3ae6c5 3911 goto done;
38d5bc6d 3912 }
1aa36616 3913 c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3914 break;
7e0b54b1 3915 case 0x8d: /* lea r16/r32, m */
90de84f5 3916 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3917 break;
4257198a
GT		 3918 case 0x8e: { /* mov seg, r/m16 */
3919 uint16_t sel;
4257198a
GT		 3920
3921 sel = c->src.val;
8b9f4414 3922
c697518a
GN		 3923 if (c->modrm_reg == VCPU_SREG_CS ||
3924 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3925 rc = emulate_ud(ctxt);
8b9f4414
GN		 3926 goto done;
3927 }
3928
310b5d30 3929 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3930 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3931
2e873022 3932 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3933
3934 c->dst.type = OP_NONE; /* Disable writeback. */
3935 break;
3936 }
6aa8b732 3937 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3938 rc = em_grp1a(ctxt);
6aa8b732 3939 break;
3d9e77df
AK		 3940 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3941 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3942 break;
b13354f8 3943 goto xchg;
e8b6fa70
WY		 3944 case 0x98: /* cbw/cwde/cdqe */
3945 switch (c->op_bytes) {
3946 case 2: c->dst.val = (s8)c->dst.val; break;
3947 case 4: c->dst.val = (s16)c->dst.val; break;
3948 case 8: c->dst.val = (s32)c->dst.val; break;
3949 }
3950 break;
dfb507c4
MG		 3951 case 0xa8 ... 0xa9: /* test ax, imm */
3952 goto test;
018a98db 3953 case 0xc0 ... 0xc1:
51187683 3954 rc = em_grp2(ctxt);
018a98db 3955 break;
111de5d6 3956 case 0xc3: /* ret */
cf5de4f8 3957 c->dst.type = OP_REG;
1a6440ae 3958 c->dst.addr.reg = &c->eip;
cf5de4f8 3959 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3960 rc = em_pop(ctxt);
3961 break;
09b5f4d3
WY		 3962 case 0xc4: /* les */
3963 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3964 break;
3965 case 0xc5: /* lds */
3966 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3967 break;
a77ab5ea
AK		 3968 case 0xcb: /* ret far */
3969 rc = emulate_ret_far(ctxt, ops);
62bd430e 3970 break;
6e154e56
MG		 3971 case 0xcc: /* int3 */
3972 irq = 3;
3973 goto do_interrupt;
3974 case 0xcd: /* int n */
3975 irq = c->src.val;
3976 do_interrupt:
3977 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3978 break;
3979 case 0xce: /* into */
3980 if (ctxt->eflags & EFLG_OF) {
3981 irq = 4;
3982 goto do_interrupt;
3983 }
3984 break;
62bd430e
MG		 3985 case 0xcf: /* iret */
3986 rc = emulate_iret(ctxt, ops);
a77ab5ea 3987 break;
018a98db 3988 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3989 rc = em_grp2(ctxt);
018a98db
AK		 3990 break;
3991 case 0xd2 ... 0xd3: /* Grp2 */
3992 c->src.val = c->regs[VCPU_REGS_RCX];
51187683 3993 rc = em_grp2(ctxt);
018a98db 3994 break;
f2f31845
WY		 3995 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3996 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3997 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3998 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3999 jmp_rel(c, c->src.val);
4000 break;
e4abac67
WY		 4001 case 0xe3: /* jcxz/jecxz/jrcxz */
4002 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
4003 jmp_rel(c, c->src.val);
4004 break;
a6a3034c
MG		 4005 case 0xe4: /* inb */
4006 case 0xe5: /* in */
cf8f70bf 4007 goto do_io_in;
a6a3034c
MG		 4008 case 0xe6: /* outb */
4009 case 0xe7: /* out */
cf8f70bf 4010 goto do_io_out;
1a52e051 4011 case 0xe8: /* call (near) */ {
d53c4777 4012 long int rel = c->src.val;
e4e03ded 4013 c->src.val = (unsigned long) c->eip;
7a957275 4014 jmp_rel(c, rel);
4487b3b4 4015 rc = em_push(ctxt);
8cdbd2c9 4016 break;
1a52e051
NK		 4017 }
4018 case 0xe9: /* jmp rel */
954cd36f 4019 goto jmp;
d2f62766
TY		 4020 case 0xea: /* jmp far */
4021 rc = em_jmp_far(ctxt);
954cd36f 4022 break;
954cd36f
GT		 4023 case 0xeb:
4024 jmp: /* jmp rel short */
7a957275 4025 jmp_rel(c, c->src.val);
a01af5ec 4026 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4027 break;
a6a3034c
MG		 4028 case 0xec: /* in al,dx */
4029 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 4030 c->src.val = c->regs[VCPU_REGS_RDX];
4031 do_io_in:
7b262e90
GN		 4032 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4033 &c->dst.val))
cf8f70bf
GN		 4034 goto done; /* IO is needed */
4035 break;
ce7a0ad3
WY		 4036 case 0xee: /* out dx,al */
4037 case 0xef: /* out dx,(e/r)ax */
41167be5 4038 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 4039 do_io_out:
ca1d4a9e
AK		 4040 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4041 &c->src.val, 1);
cf8f70bf 4042 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4043 break;
111de5d6 4044 case 0xf4: /* hlt */
6c3287f7 4045 ctxt->ops->halt(ctxt);
19fdfa0d 4046 break;
111de5d6
AK		 4047 case 0xf5: /* cmc */
4048 /* complement carry flag from eflags reg */
4049 ctxt->eflags ^= EFLG_CF;
111de5d6 4050 break;
018a98db 4051 case 0xf6 ... 0xf7: /* Grp3 */
51187683 4052 rc = em_grp3(ctxt);
018a98db 4053 break;
111de5d6
AK		 4054 case 0xf8: /* clc */
4055 ctxt->eflags &= ~EFLG_CF;
111de5d6 4056 break;
8744aa9a
MG		 4057 case 0xf9: /* stc */
4058 ctxt->eflags |= EFLG_CF;
4059 break;
111de5d6 4060 case 0xfa: /* cli */
07cbc6c1 4061 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4062 rc = emulate_gp(ctxt, 0);
07cbc6c1 4063 goto done;
36089fed 4064 } else
f850e2e6 4065 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4066 break;
4067 case 0xfb: /* sti */
07cbc6c1 4068 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4069 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4070 goto done;
4071 } else {
95cb2295 4072 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4073 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4074 }
111de5d6 4075 break;
fb4616f4
MG		 4076 case 0xfc: /* cld */
4077 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4078 break;
4079 case 0xfd: /* std */
4080 ctxt->eflags |= EFLG_DF;
fb4616f4 4081 break;
ea79849d 4082 case 0xfe: /* Grp4 */
51187683 4083 rc = em_grp45(ctxt);
018a98db 4084 break;
ea79849d 4085 case 0xff: /* Grp5 */
51187683
TY		 4086 rc = em_grp45(ctxt);
4087 break;
91269b8f
AK		 4088 default:
4089 goto cannot_emulate;
6aa8b732 4090 }
018a98db 4091
7d9ddaed
AK		 4092 if (rc != X86EMUL_CONTINUE)
4093 goto done;
4094
018a98db 4095writeback:
adddcecf 4096 rc = writeback(ctxt);
1b30eaa8 4097 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4098 goto done;
4099
5cd21917
GN		 4100 /*
4101 * restore dst type in case the decoding will be reused
4102 * (happens for string instruction )
4103 */
4104 c->dst.type = saved_dst_type;
4105
a682e354 4106 if ((c->d & SrcMask) == SrcSI)
c1ed6dea 4107 string_addr_inc(ctxt, seg_override(ctxt, c),
79168fd1 4108 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4109
4110 if ((c->d & DstMask) == DstDI)
90de84f5 4111 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4112 &c->dst);
d9271123 4113
5cd21917 4114 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4115 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4116 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4117
d2ddd1c4
GN		 4118 if (!string_insn_completed(ctxt)) {
4119 /*
4120 * Re-enter guest when pio read ahead buffer is empty
4121 * or, if it is not used, after each 1024 iteration.
4122 */
4123 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4124 (r->end == 0 || r->end != r->pos)) {
4125 /*
4126 * Reset read cache. Usually happens before
4127 * decode, but since instruction is restarted
4128 * we have to do it here.
4129 */
4130 ctxt->decode.mem_read.end = 0;
4131 return EMULATION_RESTART;
4132 }
4133 goto done; /* skip rip writeback */
0fa6ccbd 4134 }
5cd21917 4135 }
d2ddd1c4
GN		 4136
4137 ctxt->eip = c->eip;
018a98db
AK		 4138
4139done:
da9cb575
AK		 4140 if (rc == X86EMUL_PROPAGATE_FAULT)
4141 ctxt->have_exception = true;
775fde86
JR		 4142 if (rc == X86EMUL_INTERCEPTED)
4143 return EMULATION_INTERCEPTED;
4144
d2ddd1c4 4145 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4146
4147twobyte_insn:
e4e03ded 4148 switch (c->b) {
e99f0507 4149 case 0x05: /* syscall */
3fb1b5db 4150 rc = emulate_syscall(ctxt, ops);
e99f0507 4151 break;
018a98db 4152 case 0x06:
2d04a05b 4153 rc = em_clts(ctxt);
018a98db 4154 break;
018a98db 4155 case 0x09: /* wbinvd */
cfb22375 4156 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4157 break;
4158 case 0x08: /* invd */
018a98db
AK		 4159 case 0x0d: /* GrpP (prefetch) */
4160 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4161 break;
4162 case 0x20: /* mov cr, reg */
717746e3 4163 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4164 break;
6aa8b732 4165 case 0x21: /* mov from dr to reg */
717746e3 4166 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4167 break;
018a98db 4168 case 0x22: /* mov reg, cr */
717746e3 4169 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4170 emulate_gp(ctxt, 0);
da9cb575 4171 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4172 goto done;
4173 }
018a98db
AK		 4174 c->dst.type = OP_NONE;
4175 break;
6aa8b732 4176 case 0x23: /* mov from reg to dr */
717746e3 4177 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4178 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4179 ~0ULL : ~0U)) < 0) {
338dbc97 4180 /* #UD condition is already handled by the code above */
54b8486f 4181 emulate_gp(ctxt, 0);
da9cb575 4182 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4183 goto done;
4184 }
4185
a01af5ec 4186 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4187 break;
018a98db
AK		 4188 case 0x30:
4189 /* wrmsr */
4190 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4191 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4192 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4193 emulate_gp(ctxt, 0);
da9cb575 4194 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4195 goto done;
018a98db
AK		 4196 }
4197 rc = X86EMUL_CONTINUE;
018a98db
AK		 4198 break;
4199 case 0x32:
4200 /* rdmsr */
717746e3 4201 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4202 emulate_gp(ctxt, 0);
da9cb575 4203 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4204 goto done;
018a98db
AK		 4205 } else {
4206 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4207 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4208 }
4209 rc = X86EMUL_CONTINUE;
018a98db 4210 break;
e99f0507 4211 case 0x34: /* sysenter */
3fb1b5db 4212 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4213 break;
4214 case 0x35: /* sysexit */
3fb1b5db 4215 rc = emulate_sysexit(ctxt, ops);
e99f0507 4216 break;
6aa8b732 4217 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4218 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4219 if (!test_cc(c->b, ctxt->eflags))
4220 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4221 break;
b2833e3c 4222 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4223 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4224 jmp_rel(c, c->src.val);
018a98db 4225 break;
ee45b58e
WY		 4226 case 0x90 ... 0x9f: /* setcc r/m8 */
4227 c->dst.val = test_cc(c->b, ctxt->eflags);
4228 break;
0934ac9d 4229 case 0xa0: /* push fs */
4179bb02 4230 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4231 break;
4232 case 0xa1: /* pop fs */
4233 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4234 break;
7de75248
NK		 4235 case 0xa3:
4236 bt: /* bt */
e4f8e039 4237 c->dst.type = OP_NONE;
e4e03ded
LV		 4238 /* only subword offset */
4239 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4240 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4241 break;
9bf8ea42
GT		 4242 case 0xa4: /* shld imm8, r, r/m */
4243 case 0xa5: /* shld cl, r, r/m */
4244 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4245 break;
0934ac9d 4246 case 0xa8: /* push gs */
4179bb02 4247 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4248 break;
4249 case 0xa9: /* pop gs */
4250 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4251 break;
7de75248
NK		 4252 case 0xab:
4253 bts: /* bts */
05f086f8 4254 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4255 break;
9bf8ea42
GT		 4256 case 0xac: /* shrd imm8, r, r/m */
4257 case 0xad: /* shrd cl, r, r/m */
4258 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4259 break;
2a7c5b8b
GC		 4260 case 0xae: /* clflush */
4261 break;
6aa8b732
AK		 4262 case 0xb0 ... 0xb1: /* cmpxchg */
4263 /*
4264 * Save real source value, then compare EAX against
4265 * destination.
4266 */
e4e03ded
LV		 4267 c->src.orig_val = c->src.val;
4268 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4269 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4270 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4271 /* Success: write back to memory. */
e4e03ded 4272 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4273 } else {
4274 /* Failure: write the value we saw to EAX. */
e4e03ded 4275 c->dst.type = OP_REG;
1a6440ae 4276 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4277 }
4278 break;
09b5f4d3
WY		 4279 case 0xb2: /* lss */
4280 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4281 break;
6aa8b732
AK		 4282 case 0xb3:
4283 btr: /* btr */
05f086f8 4284 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4285 break;
09b5f4d3
WY		 4286 case 0xb4: /* lfs */
4287 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4288 break;
4289 case 0xb5: /* lgs */
4290 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4291 break;
6aa8b732 4292 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4293 c->dst.bytes = c->op_bytes;
4294 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4295 : (u16) c->src.val;
6aa8b732 4296 break;
6aa8b732 4297 case 0xba: /* Grp8 */
e4e03ded 4298 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4299 case 0:
4300 goto bt;
4301 case 1:
4302 goto bts;
4303 case 2:
4304 goto btr;
4305 case 3:
4306 goto btc;
4307 }
4308 break;
7de75248
NK		 4309 case 0xbb:
4310 btc: /* btc */
05f086f8 4311 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4312 break;
d9574a25
WY		 4313 case 0xbc: { /* bsf */
4314 u8 zf;
4315 __asm__ ("bsf %2, %0; setz %1"
4316 : "=r"(c->dst.val), "=q"(zf)
4317 : "r"(c->src.val));
4318 ctxt->eflags &= ~X86_EFLAGS_ZF;
4319 if (zf) {
4320 ctxt->eflags |= X86_EFLAGS_ZF;
4321 c->dst.type = OP_NONE; /* Disable writeback. */
4322 }
4323 break;
4324 }
4325 case 0xbd: { /* bsr */
4326 u8 zf;
4327 __asm__ ("bsr %2, %0; setz %1"
4328 : "=r"(c->dst.val), "=q"(zf)
4329 : "r"(c->src.val));
4330 ctxt->eflags &= ~X86_EFLAGS_ZF;
4331 if (zf) {
4332 ctxt->eflags |= X86_EFLAGS_ZF;
4333 c->dst.type = OP_NONE; /* Disable writeback. */
4334 }
4335 break;
4336 }
6aa8b732 4337 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4338 c->dst.bytes = c->op_bytes;
4339 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4340 (s16) c->src.val;
6aa8b732 4341 break;
92f738a5
WY		 4342 case 0xc0 ... 0xc1: /* xadd */
4343 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4344 /* Write back the register source. */
4345 c->src.val = c->dst.orig_val;
4346 write_register_operand(&c->src);
4347 break;
a012e65a 4348 case 0xc3: /* movnti */
e4e03ded
LV		 4349 c->dst.bytes = c->op_bytes;
4350 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4351 (u64) c->src.val;
a012e65a 4352 break;
6aa8b732 4353 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4354 rc = em_grp9(ctxt);
8cdbd2c9 4355 break;
91269b8f
AK		 4356 default:
4357 goto cannot_emulate;
6aa8b732 4358 }
7d9ddaed
AK		 4359
4360 if (rc != X86EMUL_CONTINUE)
4361 goto done;
4362
6aa8b732
AK		 4363 goto writeback;
4364
4365cannot_emulate:
a0c0ab2f 4366 return EMULATION_FAILED;
6aa8b732 4367}
Linux kernel - Deliverables
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