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KVM: x86 emulator: merge the two emulate_1op_rax_rdx implementations
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
221192bd
MT		 50#define DstDX (8<<1) /* Destination is in DX register */
51#define DstMask (0xf<<1)
6aa8b732 52/* Source operand type. */
221192bd
MT		 53#define SrcNone (0<<5) /* No source operand. */
54#define SrcReg (1<<5) /* Register operand. */
55#define SrcMem (2<<5) /* Memory operand. */
56#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
58#define SrcImm (5<<5) /* Immediate operand. */
59#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
60#define SrcOne (7<<5) /* Implied '1' */
61#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
62#define SrcImmU (9<<5) /* Immediate operand, unsigned */
63#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
64#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
65#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
66#define SrcAcc (0xd<<5) /* Source Accumulator */
67#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
68#define SrcDX (0xf<<5) /* Source is in DX register */
69#define SrcMask (0xf<<5)
6aa8b732 70/* Generic ModRM decode. */
221192bd 71#define ModRM (1<<9)
6aa8b732 72/* Destination is only written; never read. */
221192bd
MT		 73#define Mov (1<<10)
74#define BitOp (1<<11)
75#define MemAbs (1<<12) /* Memory operand is absolute displacement */
76#define String (1<<13) /* String instruction (rep capable) */
77#define Stack (1<<14) /* Stack instruction (push/pop) */
78#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
79#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
81#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
82#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
83#define Sse (1<<18) /* SSE Vector instruction */
d8769fed 84/* Misc flags */
8ea7d6ae 85#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 86#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
c4f035c6 112 u8 intercept;
120df890 113 union {
ef65c889 114 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 115 struct opcode *group;
116 struct group_dual *gdual;
0d7cdee8 117 struct gprefix *gprefix;
120df890 118 } u;
d09beabd 119 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 120};
121
122struct group_dual {
123 struct opcode mod012[8];
124 struct opcode mod3[8];
d65b1dee
AK		 125};
126
0d7cdee8
AK		 127struct gprefix {
128 struct opcode pfx_no;
129 struct opcode pfx_66;
130 struct opcode pfx_f2;
131 struct opcode pfx_f3;
132};
133
6aa8b732 134/* EFLAGS bit definitions. */
d4c6a154
GN		 135#define EFLG_ID (1<<21)
136#define EFLG_VIP (1<<20)
137#define EFLG_VIF (1<<19)
138#define EFLG_AC (1<<18)
b1d86143
AP		 139#define EFLG_VM (1<<17)
140#define EFLG_RF (1<<16)
d4c6a154
GN		 141#define EFLG_IOPL (3<<12)
142#define EFLG_NT (1<<14)
6aa8b732
AK		 143#define EFLG_OF (1<<11)
144#define EFLG_DF (1<<10)
b1d86143 145#define EFLG_IF (1<<9)
d4c6a154 146#define EFLG_TF (1<<8)
6aa8b732
AK		 147#define EFLG_SF (1<<7)
148#define EFLG_ZF (1<<6)
149#define EFLG_AF (1<<4)
150#define EFLG_PF (1<<2)
151#define EFLG_CF (1<<0)
152
62bd430e
MG		 153#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
154#define EFLG_RESERVED_ONE_MASK 2
155
6aa8b732
AK		 156/*
157 * Instruction emulation:
158 * Most instructions are emulated directly via a fragment of inline assembly
159 * code. This allows us to save/restore EFLAGS and thus very easily pick up
160 * any modified flags.
161 */
162
05b3e0c2 163#if defined(CONFIG_X86_64)
6aa8b732
AK		 164#define _LO32 "k" /* force 32-bit operand */
165#define _STK "%%rsp" /* stack pointer */
166#elif defined(__i386__)
167#define _LO32 "" /* force 32-bit operand */
168#define _STK "%%esp" /* stack pointer */
169#endif
170
171/*
172 * These EFLAGS bits are restored from saved value during emulation, and
173 * any changes are written back to the saved value after emulation.
174 */
175#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
176
177/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 178#define _PRE_EFLAGS(_sav, _msk, _tmp) \
179 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
180 "movl %"_sav",%"_LO32 _tmp"; " \
181 "push %"_tmp"; " \
182 "push %"_tmp"; " \
183 "movl %"_msk",%"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "pushf; " \
186 "notl %"_LO32 _tmp"; " \
187 "andl %"_LO32 _tmp",("_STK"); " \
188 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
189 "pop %"_tmp"; " \
190 "orl %"_LO32 _tmp",("_STK"); " \
191 "popf; " \
192 "pop %"_sav"; "
6aa8b732
AK		 193
194/* After executing instruction: write-back necessary bits in EFLAGS. */
195#define _POST_EFLAGS(_sav, _msk, _tmp) \
196 /* _sav |= EFLAGS & _msk; */ \
197 "pushf; " \
198 "pop %"_tmp"; " \
199 "andl %"_msk",%"_LO32 _tmp"; " \
200 "orl %"_LO32 _tmp",%"_sav"; "
201
dda96d8f
AK		 202#ifdef CONFIG_X86_64
203#define ON64(x) x
204#else
205#define ON64(x)
206#endif
207
a31b9cea 208#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 209 do { \
210 __asm__ __volatile__ ( \
211 _PRE_EFLAGS("0", "4", "2") \
212 _op _suffix " %"_x"3,%1; " \
213 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 214 : "=m" ((ctxt)->eflags), \
215 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 216 "=&r" (_tmp) \
a31b9cea 217 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 218 } while (0)
6b7ad61f
AK		 219
220
6aa8b732 221/* Raw emulation: instruction has two explicit operands. */
a31b9cea 222#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 223 do { \
224 unsigned long _tmp; \
225 \
a31b9cea 226 switch ((ctxt)->dst.bytes) { \
6b7ad61f 227 case 2: \
a31b9cea 228 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 229 break; \
230 case 4: \
a31b9cea 231 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 232 break; \
233 case 8: \
a31b9cea 234 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 235 break; \
236 } \
6aa8b732
AK		 237 } while (0)
238
a31b9cea 239#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 240 do { \
6b7ad61f 241 unsigned long _tmp; \
a31b9cea 242 switch ((ctxt)->dst.bytes) { \
6aa8b732 243 case 1: \
a31b9cea 244 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 245 break; \
246 default: \
a31b9cea 247 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 248 _wx, _wy, _lx, _ly, _qx, _qy); \
249 break; \
250 } \
251 } while (0)
252
253/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 254#define emulate_2op_SrcB(ctxt, _op) \
255 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 256
257/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 258#define emulate_2op_SrcV(ctxt, _op) \
259 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 260
261/* Source operand is word, long or quad sized. */
a31b9cea
AK		 262#define emulate_2op_SrcV_nobyte(ctxt, _op) \
263 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
29053a60 266#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 267 do { \
268 unsigned long _tmp; \
761441b9
AK		 269 _type _clv = (ctxt)->src2.val; \
270 _type _srcv = (ctxt)->src.val; \
271 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
761441b9 277 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
761441b9
AK		 281 (ctxt)->src2.val = (unsigned long) _clv; \
282 (ctxt)->src2.val = (unsigned long) _srcv; \
283 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
761441b9 286#define emulate_2op_cl(ctxt, _op) \
7295261c 287 do { \
761441b9 288 switch ((ctxt)->dst.bytes) { \
7295261c 289 case 2: \
29053a60 290 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 291 break; \
292 case 4: \
29053a60 293 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 294 break; \
295 case 8: \
29053a60 296 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 297 break; \
298 } \
d175226a
GT		 299 } while (0)
300
d1eef45d 301#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 302 do { \
303 unsigned long _tmp; \
304 \
dda96d8f
AK		 305 __asm__ __volatile__ ( \
306 _PRE_EFLAGS("0", "3", "2") \
307 _op _suffix " %1; " \
308 _POST_EFLAGS("0", "3", "2") \
d1eef45d 309 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 310 "=&r" (_tmp) \
311 : "i" (EFLAGS_MASK)); \
312 } while (0)
313
314/* Instruction has only one explicit operand (no source operand). */
d1eef45d 315#define emulate_1op(ctxt, _op) \
dda96d8f 316 do { \
d1eef45d
AK		 317 switch ((ctxt)->dst.bytes) { \
318 case 1: __emulate_1op(ctxt, _op, "b"); break; \
319 case 2: __emulate_1op(ctxt, _op, "w"); break; \
320 case 4: __emulate_1op(ctxt, _op, "l"); break; \
321 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 322 } \
323 } while (0)
324
9fef72ce 325#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
f6b3597b
AK		 326 do { \
327 unsigned long _tmp; \
328 \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "5", "1") \
331 "1: \n\t" \
332 _op _suffix " %6; " \
333 "2: \n\t" \
334 _POST_EFLAGS("0", "5", "1") \
335 ".pushsection .fixup,\"ax\" \n\t" \
336 "3: movb $1, %4 \n\t" \
337 "jmp 2b \n\t" \
338 ".popsection \n\t" \
339 _ASM_EXTABLE(1b, 3b) \
340 : "=m" (_eflags), "=&r" (_tmp), \
341 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
342 : "i" (EFLAGS_MASK), "m" ((_src).val), \
343 "a" (_rax), "d" (_rdx)); \
344 } while (0)
345
3f9f53b0 346/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
9fef72ce 347#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _ex) \
7295261c
AK		 348 do { \
349 switch((_src).bytes) { \
350 case 1: \
351 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
9fef72ce 352 _eflags, "b", _ex); \
7295261c
AK		 353 break; \
354 case 2: \
355 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
9fef72ce 356 _eflags, "w", _ex); \
7295261c
AK		 357 break; \
358 case 4: \
359 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
9fef72ce 360 _eflags, "l", _ex); \
f6b3597b
AK		 361 break; \
362 case 8: ON64( \
9fef72ce
AK		 363 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
364 _eflags, "q", _ex)); \
f6b3597b
AK		 365 break; \
366 } \
367 } while (0)
368
8a76d7f2
JR		 369static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
370 enum x86_intercept intercept,
371 enum x86_intercept_stage stage)
372{
373 struct x86_instruction_info info = {
374 .intercept = intercept,
9dac77fa
AK		 375 .rep_prefix = ctxt->rep_prefix,
376 .modrm_mod = ctxt->modrm_mod,
377 .modrm_reg = ctxt->modrm_reg,
378 .modrm_rm = ctxt->modrm_rm,
379 .src_val = ctxt->src.val64,
380 .src_bytes = ctxt->src.bytes,
381 .dst_bytes = ctxt->dst.bytes,
382 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 383 .next_rip = ctxt->eip,
384 };
385
2953538e 386 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 387}
388
9dac77fa 389static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 390{
9dac77fa 391 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 392}
393
6aa8b732 394/* Access/update address held in a register, based on addressing mode. */
e4706772 395static inline unsigned long
9dac77fa 396address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 397{
9dac77fa 398 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 399 return reg;
400 else
9dac77fa 401 return reg & ad_mask(ctxt);
e4706772
HH		 402}
403
404static inline unsigned long
9dac77fa 405register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 406{
9dac77fa 407 return address_mask(ctxt, reg);
e4706772
HH		 408}
409
7a957275 410static inline void
9dac77fa 411register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 412{
9dac77fa 413 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 414 *reg += inc;
415 else
9dac77fa 416 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 417}
6aa8b732 418
9dac77fa 419static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 420{
9dac77fa 421 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 422}
098c937b 423
56697687
AK		 424static u32 desc_limit_scaled(struct desc_struct *desc)
425{
426 u32 limit = get_desc_limit(desc);
427
428 return desc->g ? (limit << 12) | 0xfff : limit;
429}
430
9dac77fa 431static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 432{
9dac77fa
AK		 433 ctxt->has_seg_override = true;
434 ctxt->seg_override = seg;
7a5b56df
AK		 435}
436
7b105ca2 437static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 438{
439 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
440 return 0;
441
7b105ca2 442 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 443}
444
9dac77fa 445static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 446{
9dac77fa 447 if (!ctxt->has_seg_override)
7a5b56df
AK		 448 return 0;
449
9dac77fa 450 return ctxt->seg_override;
7a5b56df
AK		 451}
452
35d3d4a1
AK		 453static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
454 u32 error, bool valid)
54b8486f 455{
da9cb575
AK		 456 ctxt->exception.vector = vec;
457 ctxt->exception.error_code = error;
458 ctxt->exception.error_code_valid = valid;
35d3d4a1 459 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 460}
461
3b88e41a
JR		 462static int emulate_db(struct x86_emulate_ctxt *ctxt)
463{
464 return emulate_exception(ctxt, DB_VECTOR, 0, false);
465}
466
35d3d4a1 467static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 468{
35d3d4a1 469 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 470}
471
618ff15d
AK		 472static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
473{
474 return emulate_exception(ctxt, SS_VECTOR, err, true);
475}
476
35d3d4a1 477static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 478{
35d3d4a1 479 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 480}
481
35d3d4a1 482static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 483{
35d3d4a1 484 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 485}
486
34d1f490
AK		 487static int emulate_de(struct x86_emulate_ctxt *ctxt)
488{
35d3d4a1 489 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 490}
491
1253791d
AK		 492static int emulate_nm(struct x86_emulate_ctxt *ctxt)
493{
494 return emulate_exception(ctxt, NM_VECTOR, 0, false);
495}
496
1aa36616
AK		 497static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
498{
499 u16 selector;
500 struct desc_struct desc;
501
502 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
503 return selector;
504}
505
506static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
507 unsigned seg)
508{
509 u16 dummy;
510 u32 base3;
511 struct desc_struct desc;
512
513 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
514 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
515}
516
3d9b938e 517static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 518 struct segmented_address addr,
3d9b938e 519 unsigned size, bool write, bool fetch,
52fd8b44
AK		 520 ulong *linear)
521{
618ff15d
AK		 522 struct desc_struct desc;
523 bool usable;
52fd8b44 524 ulong la;
618ff15d 525 u32 lim;
1aa36616 526 u16 sel;
618ff15d 527 unsigned cpl, rpl;
52fd8b44 528
7b105ca2 529 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 530 switch (ctxt->mode) {
531 case X86EMUL_MODE_REAL:
532 break;
533 case X86EMUL_MODE_PROT64:
534 if (((signed long)la << 16) >> 16 != la)
535 return emulate_gp(ctxt, 0);
536 break;
537 default:
1aa36616
AK		 538 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
539 addr.seg);
618ff15d
AK		 540 if (!usable)
541 goto bad;
542 /* code segment or read-only data segment */
543 if (((desc.type & 8) || !(desc.type & 2)) && write)
544 goto bad;
545 /* unreadable code segment */
3d9b938e 546 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 547 goto bad;
548 lim = desc_limit_scaled(&desc);
549 if ((desc.type & 8) || !(desc.type & 4)) {
550 /* expand-up segment */
551 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
552 goto bad;
553 } else {
554 /* exapand-down segment */
555 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
556 goto bad;
557 lim = desc.d ? 0xffffffff : 0xffff;
558 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
559 goto bad;
560 }
717746e3 561 cpl = ctxt->ops->cpl(ctxt);
1aa36616 562 rpl = sel & 3;
618ff15d
AK		 563 cpl = max(cpl, rpl);
564 if (!(desc.type & 8)) {
565 /* data segment */
566 if (cpl > desc.dpl)
567 goto bad;
568 } else if ((desc.type & 8) && !(desc.type & 4)) {
569 /* nonconforming code segment */
570 if (cpl != desc.dpl)
571 goto bad;
572 } else if ((desc.type & 8) && (desc.type & 4)) {
573 /* conforming code segment */
574 if (cpl < desc.dpl)
575 goto bad;
576 }
577 break;
578 }
9dac77fa 579 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 580 la &= (u32)-1;
581 *linear = la;
582 return X86EMUL_CONTINUE;
618ff15d
AK		 583bad:
584 if (addr.seg == VCPU_SREG_SS)
585 return emulate_ss(ctxt, addr.seg);
586 else
587 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 588}
589
3d9b938e
NE		 590static int linearize(struct x86_emulate_ctxt *ctxt,
591 struct segmented_address addr,
592 unsigned size, bool write,
593 ulong *linear)
594{
595 return __linearize(ctxt, addr, size, write, false, linear);
596}
597
598
3ca3ac4d
AK		 599static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
600 struct segmented_address addr,
601 void *data,
602 unsigned size)
603{
9fa088f4
AK		 604 int rc;
605 ulong linear;
606
83b8795a 607 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 608 if (rc != X86EMUL_CONTINUE)
609 return rc;
0f65dd70 610 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 611}
612
807941b1
TY		 613/*
614 * Fetch the next byte of the instruction being emulated which is pointed to
615 * by ctxt->_eip, then increment ctxt->_eip.
616 *
617 * Also prefetch the remaining bytes of the instruction without crossing page
618 * boundary if they are not in fetch_cache yet.
619 */
620static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 621{
9dac77fa 622 struct fetch_cache *fc = &ctxt->fetch;
62266869 623 int rc;
2fb53ad8 624 int size, cur_size;
62266869 625
807941b1 626 if (ctxt->_eip == fc->end) {
3d9b938e 627 unsigned long linear;
807941b1
TY		 628 struct segmented_address addr = { .seg = VCPU_SREG_CS,
629 .ea = ctxt->_eip };
2fb53ad8 630 cur_size = fc->end - fc->start;
807941b1
TY		 631 size = min(15UL - cur_size,
632 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 633 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 634 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 635 return rc;
ef5d75cc
TY		 636 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
637 size, &ctxt->exception);
7d88bb48 638 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 639 return rc;
2fb53ad8 640 fc->end += size;
62266869 641 }
807941b1
TY		 642 *dest = fc->data[ctxt->_eip - fc->start];
643 ctxt->_eip++;
3e2815e9 644 return X86EMUL_CONTINUE;
62266869
AK		 645}
646
647static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 648 void *dest, unsigned size)
62266869 649{
3e2815e9 650 int rc;
62266869 651
eb3c79e6 652 /* x86 instructions are limited to 15 bytes. */
7d88bb48 653 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 654 return X86EMUL_UNHANDLEABLE;
62266869 655 while (size--) {
807941b1 656 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 657 if (rc != X86EMUL_CONTINUE)
62266869
AK		 658 return rc;
659 }
3e2815e9 660 return X86EMUL_CONTINUE;
62266869
AK		 661}
662
67cbc90d 663/* Fetch next part of the instruction being emulated. */
e85a1085 664#define insn_fetch(_type, _ctxt) \
67cbc90d 665({ unsigned long _x; \
e85a1085 666 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 667 if (rc != X86EMUL_CONTINUE) \
668 goto done; \
67cbc90d
TY		 669 (_type)_x; \
670})
671
807941b1
TY		 672#define insn_fetch_arr(_arr, _size, _ctxt) \
673({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 674 if (rc != X86EMUL_CONTINUE) \
675 goto done; \
67cbc90d
TY		 676})
677
1e3c5cb0
RR		 678/*
679 * Given the 'reg' portion of a ModRM byte, and a register block, return a
680 * pointer into the block that addresses the relevant register.
681 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
682 */
683static void *decode_register(u8 modrm_reg, unsigned long *regs,
684 int highbyte_regs)
6aa8b732
AK		 685{
686 void *p;
687
688 p = &regs[modrm_reg];
689 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
690 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
691 return p;
692}
693
694static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 695 struct segmented_address addr,
6aa8b732
AK		 696 u16 *size, unsigned long *address, int op_bytes)
697{
698 int rc;
699
700 if (op_bytes == 2)
701 op_bytes = 3;
702 *address = 0;
3ca3ac4d 703 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 704 if (rc != X86EMUL_CONTINUE)
6aa8b732 705 return rc;
30b31ab6 706 addr.ea += 2;
3ca3ac4d 707 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 708 return rc;
709}
710
bbe9abbd
NK		 711static int test_cc(unsigned int condition, unsigned int flags)
712{
713 int rc = 0;
714
715 switch ((condition & 15) >> 1) {
716 case 0: /* o */
717 rc |= (flags & EFLG_OF);
718 break;
719 case 1: /* b/c/nae */
720 rc |= (flags & EFLG_CF);
721 break;
722 case 2: /* z/e */
723 rc |= (flags & EFLG_ZF);
724 break;
725 case 3: /* be/na */
726 rc |= (flags & (EFLG_CF|EFLG_ZF));
727 break;
728 case 4: /* s */
729 rc |= (flags & EFLG_SF);
730 break;
731 case 5: /* p/pe */
732 rc |= (flags & EFLG_PF);
733 break;
734 case 7: /* le/ng */
735 rc |= (flags & EFLG_ZF);
736 /* fall through */
737 case 6: /* l/nge */
738 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
739 break;
740 }
741
742 /* Odd condition identifiers (lsb == 1) have inverted sense. */
743 return (!!rc ^ (condition & 1));
744}
745
91ff3cb4
AK		 746static void fetch_register_operand(struct operand *op)
747{
748 switch (op->bytes) {
749 case 1:
750 op->val = *(u8 *)op->addr.reg;
751 break;
752 case 2:
753 op->val = *(u16 *)op->addr.reg;
754 break;
755 case 4:
756 op->val = *(u32 *)op->addr.reg;
757 break;
758 case 8:
759 op->val = *(u64 *)op->addr.reg;
760 break;
761 }
762}
763
1253791d
AK		 764static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
765{
766 ctxt->ops->get_fpu(ctxt);
767 switch (reg) {
768 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
769 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
770 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
771 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
772 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
773 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
774 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
775 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
776#ifdef CONFIG_X86_64
777 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
778 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
779 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
780 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
781 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
782 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
783 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
784 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
785#endif
786 default: BUG();
787 }
788 ctxt->ops->put_fpu(ctxt);
789}
790
791static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
792 int reg)
793{
794 ctxt->ops->get_fpu(ctxt);
795 switch (reg) {
796 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
797 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
798 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
799 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
800 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
801 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
802 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
803 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
804#ifdef CONFIG_X86_64
805 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
806 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
807 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
808 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
809 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
810 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
811 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
812 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
813#endif
814 default: BUG();
815 }
816 ctxt->ops->put_fpu(ctxt);
817}
818
819static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
820 struct operand *op,
3c118e24
AK		 821 int inhibit_bytereg)
822{
9dac77fa
AK		 823 unsigned reg = ctxt->modrm_reg;
824 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 825
9dac77fa
AK		 826 if (!(ctxt->d & ModRM))
827 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 828
9dac77fa 829 if (ctxt->d & Sse) {
1253791d
AK		 830 op->type = OP_XMM;
831 op->bytes = 16;
832 op->addr.xmm = reg;
833 read_sse_reg(ctxt, &op->vec_val, reg);
834 return;
835 }
836
3c118e24 837 op->type = OP_REG;
9dac77fa
AK		 838 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
839 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 840 op->bytes = 1;
841 } else {
9dac77fa
AK		 842 op->addr.reg = decode_register(reg, ctxt->regs, 0);
843 op->bytes = ctxt->op_bytes;
3c118e24 844 }
91ff3cb4 845 fetch_register_operand(op);
3c118e24
AK		 846 op->orig_val = op->val;
847}
848
1c73ef66 849static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 850 struct operand *op)
1c73ef66 851{
1c73ef66 852 u8 sib;
f5b4edcd 853 int index_reg = 0, base_reg = 0, scale;
3e2815e9 854 int rc = X86EMUL_CONTINUE;
2dbd0dd7 855 ulong modrm_ea = 0;
1c73ef66 856
9dac77fa
AK		 857 if (ctxt->rex_prefix) {
858 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
859 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
860 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 861 }
862
e85a1085 863 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 864 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
865 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
866 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
867 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 868
9dac77fa 869 if (ctxt->modrm_mod == 3) {
2dbd0dd7 870 op->type = OP_REG;
9dac77fa
AK		 871 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
872 op->addr.reg = decode_register(ctxt->modrm_rm,
873 ctxt->regs, ctxt->d & ByteOp);
874 if (ctxt->d & Sse) {
1253791d
AK		 875 op->type = OP_XMM;
876 op->bytes = 16;
9dac77fa
AK		 877 op->addr.xmm = ctxt->modrm_rm;
878 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 879 return rc;
880 }
2dbd0dd7 881 fetch_register_operand(op);
1c73ef66
AK		 882 return rc;
883 }
884
2dbd0dd7
AK		 885 op->type = OP_MEM;
886
9dac77fa
AK		 887 if (ctxt->ad_bytes == 2) {
888 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
889 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
890 unsigned si = ctxt->regs[VCPU_REGS_RSI];
891 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 892
893 /* 16-bit ModR/M decode. */
9dac77fa 894 switch (ctxt->modrm_mod) {
1c73ef66 895 case 0:
9dac77fa 896 if (ctxt->modrm_rm == 6)
e85a1085 897 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 898 break;
899 case 1:
e85a1085 900 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 901 break;
902 case 2:
e85a1085 903 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 904 break;
905 }
9dac77fa 906 switch (ctxt->modrm_rm) {
1c73ef66 907 case 0:
2dbd0dd7 908 modrm_ea += bx + si;
1c73ef66
AK		 909 break;
910 case 1:
2dbd0dd7 911 modrm_ea += bx + di;
1c73ef66
AK		 912 break;
913 case 2:
2dbd0dd7 914 modrm_ea += bp + si;
1c73ef66
AK		 915 break;
916 case 3:
2dbd0dd7 917 modrm_ea += bp + di;
1c73ef66
AK		 918 break;
919 case 4:
2dbd0dd7 920 modrm_ea += si;
1c73ef66
AK		 921 break;
922 case 5:
2dbd0dd7 923 modrm_ea += di;
1c73ef66
AK		 924 break;
925 case 6:
9dac77fa 926 if (ctxt->modrm_mod != 0)
2dbd0dd7 927 modrm_ea += bp;
1c73ef66
AK		 928 break;
929 case 7:
2dbd0dd7 930 modrm_ea += bx;
1c73ef66
AK		 931 break;
932 }
9dac77fa
AK		 933 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
934 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
935 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 936 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 937 } else {
938 /* 32/64-bit ModR/M decode. */
9dac77fa 939 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 940 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 941 index_reg |= (sib >> 3) & 7;
942 base_reg |= sib & 7;
943 scale = sib >> 6;
944
9dac77fa 945 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 946 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 947 else
9dac77fa 948 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 949 if (index_reg != 4)
9dac77fa
AK		 950 modrm_ea += ctxt->regs[index_reg] << scale;
951 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 952 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 953 ctxt->rip_relative = 1;
84411d85 954 } else
9dac77fa
AK		 955 modrm_ea += ctxt->regs[ctxt->modrm_rm];
956 switch (ctxt->modrm_mod) {
1c73ef66 957 case 0:
9dac77fa 958 if (ctxt->modrm_rm == 5)
e85a1085 959 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 960 break;
961 case 1:
e85a1085 962 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 963 break;
964 case 2:
e85a1085 965 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 966 break;
967 }
968 }
90de84f5 969 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 970done:
971 return rc;
972}
973
974static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 975 struct operand *op)
1c73ef66 976{
3e2815e9 977 int rc = X86EMUL_CONTINUE;
1c73ef66 978
2dbd0dd7 979 op->type = OP_MEM;
9dac77fa 980 switch (ctxt->ad_bytes) {
1c73ef66 981 case 2:
e85a1085 982 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 983 break;
984 case 4:
e85a1085 985 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 986 break;
987 case 8:
e85a1085 988 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 989 break;
990 }
991done:
992 return rc;
993}
994
9dac77fa 995static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 996{
7129eeca 997 long sv = 0, mask;
35c843c4 998
9dac77fa
AK		 999 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1000 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1001
9dac77fa
AK		 1002 if (ctxt->src.bytes == 2)
1003 sv = (s16)ctxt->src.val & (s16)mask;
1004 else if (ctxt->src.bytes == 4)
1005 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1006
9dac77fa 1007 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1008 }
ba7ff2b7
WY		 1009
1010 /* only subword offset */
9dac77fa 1011 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1012}
1013
dde7e6d1 1014static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1015 unsigned long addr, void *dest, unsigned size)
6aa8b732 1016{
dde7e6d1 1017 int rc;
9dac77fa 1018 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1019
dde7e6d1
AK		 1020 while (size) {
1021 int n = min(size, 8u);
1022 size -= n;
1023 if (mc->pos < mc->end)
1024 goto read_cached;
5cd21917 1025
7b105ca2
TY		 1026 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1027 &ctxt->exception);
dde7e6d1
AK		 1028 if (rc != X86EMUL_CONTINUE)
1029 return rc;
1030 mc->end += n;
6aa8b732 1031
dde7e6d1
AK		 1032 read_cached:
1033 memcpy(dest, mc->data + mc->pos, n);
1034 mc->pos += n;
1035 dest += n;
1036 addr += n;
6aa8b732 1037 }
dde7e6d1
AK		 1038 return X86EMUL_CONTINUE;
1039}
6aa8b732 1040
3ca3ac4d
AK		 1041static int segmented_read(struct x86_emulate_ctxt *ctxt,
1042 struct segmented_address addr,
1043 void *data,
1044 unsigned size)
1045{
9fa088f4
AK		 1046 int rc;
1047 ulong linear;
1048
83b8795a 1049 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1050 if (rc != X86EMUL_CONTINUE)
1051 return rc;
7b105ca2 1052 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1053}
1054
1055static int segmented_write(struct x86_emulate_ctxt *ctxt,
1056 struct segmented_address addr,
1057 const void *data,
1058 unsigned size)
1059{
9fa088f4
AK		 1060 int rc;
1061 ulong linear;
1062
83b8795a 1063 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1064 if (rc != X86EMUL_CONTINUE)
1065 return rc;
0f65dd70
AK		 1066 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1067 &ctxt->exception);
3ca3ac4d
AK		 1068}
1069
1070static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1071 struct segmented_address addr,
1072 const void *orig_data, const void *data,
1073 unsigned size)
1074{
9fa088f4
AK		 1075 int rc;
1076 ulong linear;
1077
83b8795a 1078 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1079 if (rc != X86EMUL_CONTINUE)
1080 return rc;
0f65dd70
AK		 1081 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1082 size, &ctxt->exception);
3ca3ac4d
AK		 1083}
1084
dde7e6d1 1085static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1086 unsigned int size, unsigned short port,
1087 void *dest)
1088{
9dac77fa 1089 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1090
dde7e6d1 1091 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1092 unsigned int in_page, n;
9dac77fa
AK		 1093 unsigned int count = ctxt->rep_prefix ?
1094 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1095 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1096 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1097 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1098 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1099 count);
1100 if (n == 0)
1101 n = 1;
1102 rc->pos = rc->end = 0;
7b105ca2 1103 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1104 return 0;
1105 rc->end = n * size;
6aa8b732
AK		 1106 }
1107
dde7e6d1
AK		 1108 memcpy(dest, rc->data + rc->pos, size);
1109 rc->pos += size;
1110 return 1;
1111}
6aa8b732 1112
dde7e6d1 1113static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1114 u16 selector, struct desc_ptr *dt)
1115{
7b105ca2
TY		 1116 struct x86_emulate_ops *ops = ctxt->ops;
1117
dde7e6d1
AK		 1118 if (selector & 1 << 2) {
1119 struct desc_struct desc;
1aa36616
AK		 1120 u16 sel;
1121
dde7e6d1 1122 memset (dt, 0, sizeof *dt);
1aa36616 1123 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1124 return;
e09d082c 1125
dde7e6d1
AK		 1126 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1127 dt->address = get_desc_base(&desc);
1128 } else
4bff1e86 1129 ops->get_gdt(ctxt, dt);
dde7e6d1 1130}
120df890 1131
dde7e6d1
AK		 1132/* allowed just for 8 bytes segments */
1133static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1134 u16 selector, struct desc_struct *desc)
1135{
1136 struct desc_ptr dt;
1137 u16 index = selector >> 3;
dde7e6d1 1138 ulong addr;
120df890 1139
7b105ca2 1140 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1141
35d3d4a1
AK		 1142 if (dt.size < index * 8 + 7)
1143 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1144
7b105ca2
TY		 1145 addr = dt.address + index * 8;
1146 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1147 &ctxt->exception);
dde7e6d1 1148}
ef65c889 1149
dde7e6d1
AK		 1150/* allowed just for 8 bytes segments */
1151static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1152 u16 selector, struct desc_struct *desc)
1153{
1154 struct desc_ptr dt;
1155 u16 index = selector >> 3;
dde7e6d1 1156 ulong addr;
6aa8b732 1157
7b105ca2 1158 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1159
35d3d4a1
AK		 1160 if (dt.size < index * 8 + 7)
1161 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1162
dde7e6d1 1163 addr = dt.address + index * 8;
7b105ca2
TY		 1164 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1165 &ctxt->exception);
dde7e6d1 1166}
c7e75a3d 1167
5601d05b 1168/* Does not support long mode */
dde7e6d1 1169static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1170 u16 selector, int seg)
1171{
1172 struct desc_struct seg_desc;
1173 u8 dpl, rpl, cpl;
1174 unsigned err_vec = GP_VECTOR;
1175 u32 err_code = 0;
1176 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1177 int ret;
69f55cb1 1178
dde7e6d1 1179 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1180
dde7e6d1
AK		 1181 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1182 || ctxt->mode == X86EMUL_MODE_REAL) {
1183 /* set real mode segment descriptor */
1184 set_desc_base(&seg_desc, selector << 4);
1185 set_desc_limit(&seg_desc, 0xffff);
1186 seg_desc.type = 3;
1187 seg_desc.p = 1;
1188 seg_desc.s = 1;
1189 goto load;
1190 }
1191
1192 /* NULL selector is not valid for TR, CS and SS */
1193 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1194 && null_selector)
1195 goto exception;
1196
1197 /* TR should be in GDT only */
1198 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1199 goto exception;
1200
1201 if (null_selector) /* for NULL selector skip all following checks */
1202 goto load;
1203
7b105ca2 1204 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1205 if (ret != X86EMUL_CONTINUE)
1206 return ret;
1207
1208 err_code = selector & 0xfffc;
1209 err_vec = GP_VECTOR;
1210
1211 /* can't load system descriptor into segment selecor */
1212 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1213 goto exception;
1214
1215 if (!seg_desc.p) {
1216 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1217 goto exception;
1218 }
1219
1220 rpl = selector & 3;
1221 dpl = seg_desc.dpl;
7b105ca2 1222 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1223
1224 switch (seg) {
1225 case VCPU_SREG_SS:
1226 /*
1227 * segment is not a writable data segment or segment
1228 * selector's RPL != CPL or segment selector's RPL != CPL
1229 */
1230 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1231 goto exception;
6aa8b732 1232 break;
dde7e6d1
AK		 1233 case VCPU_SREG_CS:
1234 if (!(seg_desc.type & 8))
1235 goto exception;
1236
1237 if (seg_desc.type & 4) {
1238 /* conforming */
1239 if (dpl > cpl)
1240 goto exception;
1241 } else {
1242 /* nonconforming */
1243 if (rpl > cpl || dpl != cpl)
1244 goto exception;
1245 }
1246 /* CS(RPL) <- CPL */
1247 selector = (selector & 0xfffc) | cpl;
6aa8b732 1248 break;
dde7e6d1
AK		 1249 case VCPU_SREG_TR:
1250 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1251 goto exception;
1252 break;
1253 case VCPU_SREG_LDTR:
1254 if (seg_desc.s || seg_desc.type != 2)
1255 goto exception;
1256 break;
1257 default: /* DS, ES, FS, or GS */
4e62417b 1258 /*
dde7e6d1
AK		 1259 * segment is not a data or readable code segment or
1260 * ((segment is a data or nonconforming code segment)
1261 * and (both RPL and CPL > DPL))
4e62417b 1262 */
dde7e6d1
AK		 1263 if ((seg_desc.type & 0xa) == 0x8 ||
1264 (((seg_desc.type & 0xc) != 0xc) &&
1265 (rpl > dpl && cpl > dpl)))
1266 goto exception;
6aa8b732 1267 break;
dde7e6d1
AK		 1268 }
1269
1270 if (seg_desc.s) {
1271 /* mark segment as accessed */
1272 seg_desc.type |= 1;
7b105ca2 1273 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1274 if (ret != X86EMUL_CONTINUE)
1275 return ret;
1276 }
1277load:
7b105ca2 1278 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1279 return X86EMUL_CONTINUE;
1280exception:
1281 emulate_exception(ctxt, err_vec, err_code, true);
1282 return X86EMUL_PROPAGATE_FAULT;
1283}
1284
31be40b3
WY		 1285static void write_register_operand(struct operand *op)
1286{
1287 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1288 switch (op->bytes) {
1289 case 1:
1290 *(u8 *)op->addr.reg = (u8)op->val;
1291 break;
1292 case 2:
1293 *(u16 *)op->addr.reg = (u16)op->val;
1294 break;
1295 case 4:
1296 *op->addr.reg = (u32)op->val;
1297 break; /* 64b: zero-extend */
1298 case 8:
1299 *op->addr.reg = op->val;
1300 break;
1301 }
1302}
1303
adddcecf 1304static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1305{
1306 int rc;
dde7e6d1 1307
9dac77fa 1308 switch (ctxt->dst.type) {
dde7e6d1 1309 case OP_REG:
9dac77fa 1310 write_register_operand(&ctxt->dst);
6aa8b732 1311 break;
dde7e6d1 1312 case OP_MEM:
9dac77fa 1313 if (ctxt->lock_prefix)
3ca3ac4d 1314 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1315 ctxt->dst.addr.mem,
1316 &ctxt->dst.orig_val,
1317 &ctxt->dst.val,
1318 ctxt->dst.bytes);
341de7e3 1319 else
3ca3ac4d 1320 rc = segmented_write(ctxt,
9dac77fa
AK		 1321 ctxt->dst.addr.mem,
1322 &ctxt->dst.val,
1323 ctxt->dst.bytes);
dde7e6d1
AK		 1324 if (rc != X86EMUL_CONTINUE)
1325 return rc;
a682e354 1326 break;
1253791d 1327 case OP_XMM:
9dac77fa 1328 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1329 break;
dde7e6d1
AK		 1330 case OP_NONE:
1331 /* no writeback */
414e6277 1332 break;
dde7e6d1 1333 default:
414e6277 1334 break;
6aa8b732 1335 }
dde7e6d1
AK		 1336 return X86EMUL_CONTINUE;
1337}
6aa8b732 1338
4487b3b4 1339static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1340{
4179bb02 1341 struct segmented_address addr;
0dc8d10f 1342
9dac77fa
AK		 1343 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1344 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1345 addr.seg = VCPU_SREG_SS;
1346
1347 /* Disable writeback. */
9dac77fa
AK		 1348 ctxt->dst.type = OP_NONE;
1349 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1350}
69f55cb1 1351
dde7e6d1 1352static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1353 void *dest, int len)
1354{
dde7e6d1 1355 int rc;
90de84f5 1356 struct segmented_address addr;
8b4caf66 1357
9dac77fa 1358 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1359 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1360 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1361 if (rc != X86EMUL_CONTINUE)
1362 return rc;
1363
9dac77fa 1364 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1365 return rc;
8b4caf66
LV		 1366}
1367
c54fe504
TY		 1368static int em_pop(struct x86_emulate_ctxt *ctxt)
1369{
9dac77fa 1370 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1371}
1372
dde7e6d1 1373static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1374 void *dest, int len)
9de41573
GN		 1375{
1376 int rc;
dde7e6d1
AK		 1377 unsigned long val, change_mask;
1378 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1379 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1380
3b9be3bf 1381 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1382 if (rc != X86EMUL_CONTINUE)
1383 return rc;
9de41573 1384
dde7e6d1
AK		 1385 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1386 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1387
dde7e6d1
AK		 1388 switch(ctxt->mode) {
1389 case X86EMUL_MODE_PROT64:
1390 case X86EMUL_MODE_PROT32:
1391 case X86EMUL_MODE_PROT16:
1392 if (cpl == 0)
1393 change_mask |= EFLG_IOPL;
1394 if (cpl <= iopl)
1395 change_mask |= EFLG_IF;
1396 break;
1397 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1398 if (iopl < 3)
1399 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1400 change_mask |= EFLG_IF;
1401 break;
1402 default: /* real mode */
1403 change_mask |= (EFLG_IOPL | EFLG_IF);
1404 break;
9de41573 1405 }
dde7e6d1
AK		 1406
1407 *(unsigned long *)dest =
1408 (ctxt->eflags & ~change_mask) | (val & change_mask);
1409
1410 return rc;
9de41573
GN		 1411}
1412
62aaa2f0
TY		 1413static int em_popf(struct x86_emulate_ctxt *ctxt)
1414{
9dac77fa
AK		 1415 ctxt->dst.type = OP_REG;
1416 ctxt->dst.addr.reg = &ctxt->eflags;
1417 ctxt->dst.bytes = ctxt->op_bytes;
1418 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1419}
1420
7b105ca2 1421static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1422{
9dac77fa 1423 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1424
4487b3b4 1425 return em_push(ctxt);
7b262e90
GN		 1426}
1427
7b105ca2 1428static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1429{
dde7e6d1
AK		 1430 unsigned long selector;
1431 int rc;
38ba30ba 1432
9dac77fa 1433 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1434 if (rc != X86EMUL_CONTINUE)
1435 return rc;
1436
7b105ca2 1437 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1438 return rc;
38ba30ba
GN		 1439}
1440
b96a7fad 1441static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1442{
9dac77fa 1443 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1444 int rc = X86EMUL_CONTINUE;
1445 int reg = VCPU_REGS_RAX;
38ba30ba 1446
dde7e6d1
AK		 1447 while (reg <= VCPU_REGS_RDI) {
1448 (reg == VCPU_REGS_RSP) ?
9dac77fa 1449 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1450
4487b3b4 1451 rc = em_push(ctxt);
dde7e6d1
AK		 1452 if (rc != X86EMUL_CONTINUE)
1453 return rc;
38ba30ba 1454
dde7e6d1 1455 ++reg;
38ba30ba 1456 }
38ba30ba 1457
dde7e6d1 1458 return rc;
38ba30ba
GN		 1459}
1460
62aaa2f0
TY		 1461static int em_pushf(struct x86_emulate_ctxt *ctxt)
1462{
9dac77fa 1463 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1464 return em_push(ctxt);
1465}
1466
b96a7fad 1467static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1468{
dde7e6d1
AK		 1469 int rc = X86EMUL_CONTINUE;
1470 int reg = VCPU_REGS_RDI;
38ba30ba 1471
dde7e6d1
AK		 1472 while (reg >= VCPU_REGS_RAX) {
1473 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1474 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1475 ctxt->op_bytes);
dde7e6d1
AK		 1476 --reg;
1477 }
38ba30ba 1478
9dac77fa 1479 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1480 if (rc != X86EMUL_CONTINUE)
1481 break;
1482 --reg;
38ba30ba 1483 }
dde7e6d1 1484 return rc;
38ba30ba
GN		 1485}
1486
7b105ca2 1487int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1488{
7b105ca2 1489 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1490 int rc;
6e154e56
MG		 1491 struct desc_ptr dt;
1492 gva_t cs_addr;
1493 gva_t eip_addr;
1494 u16 cs, eip;
6e154e56
MG		 1495
1496 /* TODO: Add limit checks */
9dac77fa 1497 ctxt->src.val = ctxt->eflags;
4487b3b4 1498 rc = em_push(ctxt);
5c56e1cf
AK		 1499 if (rc != X86EMUL_CONTINUE)
1500 return rc;
6e154e56
MG		 1501
1502 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1503
9dac77fa 1504 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1505 rc = em_push(ctxt);
5c56e1cf
AK		 1506 if (rc != X86EMUL_CONTINUE)
1507 return rc;
6e154e56 1508
9dac77fa 1509 ctxt->src.val = ctxt->_eip;
4487b3b4 1510 rc = em_push(ctxt);
5c56e1cf
AK		 1511 if (rc != X86EMUL_CONTINUE)
1512 return rc;
1513
4bff1e86 1514 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1515
1516 eip_addr = dt.address + (irq << 2);
1517 cs_addr = dt.address + (irq << 2) + 2;
1518
0f65dd70 1519 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1520 if (rc != X86EMUL_CONTINUE)
1521 return rc;
1522
0f65dd70 1523 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1524 if (rc != X86EMUL_CONTINUE)
1525 return rc;
1526
7b105ca2 1527 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1528 if (rc != X86EMUL_CONTINUE)
1529 return rc;
1530
9dac77fa 1531 ctxt->_eip = eip;
6e154e56
MG		 1532
1533 return rc;
1534}
1535
7b105ca2 1536static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1537{
1538 switch(ctxt->mode) {
1539 case X86EMUL_MODE_REAL:
7b105ca2 1540 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1541 case X86EMUL_MODE_VM86:
1542 case X86EMUL_MODE_PROT16:
1543 case X86EMUL_MODE_PROT32:
1544 case X86EMUL_MODE_PROT64:
1545 default:
1546 /* Protected mode interrupts unimplemented yet */
1547 return X86EMUL_UNHANDLEABLE;
1548 }
1549}
1550
7b105ca2 1551static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1552{
dde7e6d1
AK		 1553 int rc = X86EMUL_CONTINUE;
1554 unsigned long temp_eip = 0;
1555 unsigned long temp_eflags = 0;
1556 unsigned long cs = 0;
1557 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1558 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1559 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1560 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1561
dde7e6d1 1562 /* TODO: Add stack limit check */
38ba30ba 1563
9dac77fa 1564 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1565
dde7e6d1
AK		 1566 if (rc != X86EMUL_CONTINUE)
1567 return rc;
38ba30ba 1568
35d3d4a1
AK		 1569 if (temp_eip & ~0xffff)
1570 return emulate_gp(ctxt, 0);
38ba30ba 1571
9dac77fa 1572 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1573
dde7e6d1
AK		 1574 if (rc != X86EMUL_CONTINUE)
1575 return rc;
38ba30ba 1576
9dac77fa 1577 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1578
dde7e6d1
AK		 1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
38ba30ba 1581
7b105ca2 1582 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1583
dde7e6d1
AK		 1584 if (rc != X86EMUL_CONTINUE)
1585 return rc;
38ba30ba 1586
9dac77fa 1587 ctxt->_eip = temp_eip;
38ba30ba 1588
38ba30ba 1589
9dac77fa 1590 if (ctxt->op_bytes == 4)
dde7e6d1 1591 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1592 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1593 ctxt->eflags &= ~0xffff;
1594 ctxt->eflags |= temp_eflags;
38ba30ba 1595 }
dde7e6d1
AK		 1596
1597 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1598 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1599
1600 return rc;
38ba30ba
GN		 1601}
1602
e01991e7 1603static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1604{
dde7e6d1
AK		 1605 switch(ctxt->mode) {
1606 case X86EMUL_MODE_REAL:
7b105ca2 1607 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1608 case X86EMUL_MODE_VM86:
1609 case X86EMUL_MODE_PROT16:
1610 case X86EMUL_MODE_PROT32:
1611 case X86EMUL_MODE_PROT64:
c37eda13 1612 default:
dde7e6d1
AK		 1613 /* iret from protected mode unimplemented yet */
1614 return X86EMUL_UNHANDLEABLE;
c37eda13 1615 }
c37eda13
WY		 1616}
1617
d2f62766
TY		 1618static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1619{
d2f62766
TY		 1620 int rc;
1621 unsigned short sel;
1622
9dac77fa 1623 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1624
7b105ca2 1625 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1626 if (rc != X86EMUL_CONTINUE)
1627 return rc;
1628
9dac77fa
AK		 1629 ctxt->_eip = 0;
1630 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1631 return X86EMUL_CONTINUE;
1632}
1633
51187683 1634static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1635{
9dac77fa 1636 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1637}
1638
51187683 1639static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1640{
9dac77fa 1641 switch (ctxt->modrm_reg) {
8cdbd2c9 1642 case 0: /* rol */
a31b9cea 1643 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1644 break;
1645 case 1: /* ror */
a31b9cea 1646 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1647 break;
1648 case 2: /* rcl */
a31b9cea 1649 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1650 break;
1651 case 3: /* rcr */
a31b9cea 1652 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1653 break;
1654 case 4: /* sal/shl */
1655 case 6: /* sal/shl */
a31b9cea 1656 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1657 break;
1658 case 5: /* shr */
a31b9cea 1659 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1660 break;
1661 case 7: /* sar */
a31b9cea 1662 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1663 break;
1664 }
51187683 1665 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1666}
1667
51187683 1668static int em_grp3(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1669{
9dac77fa
AK		 1670 unsigned long *rax = &ctxt->regs[VCPU_REGS_RAX];
1671 unsigned long *rdx = &ctxt->regs[VCPU_REGS_RDX];
34d1f490 1672 u8 de = 0;
8cdbd2c9 1673
9dac77fa 1674 switch (ctxt->modrm_reg) {
8cdbd2c9 1675 case 0 ... 1: /* test */
a31b9cea 1676 emulate_2op_SrcV(ctxt, "test");
8cdbd2c9
LV		 1677 break;
1678 case 2: /* not */
9dac77fa 1679 ctxt->dst.val = ~ctxt->dst.val;
8cdbd2c9
LV		 1680 break;
1681 case 3: /* neg */
d1eef45d 1682 emulate_1op(ctxt, "neg");
8cdbd2c9 1683 break;
3f9f53b0 1684 case 4: /* mul */
9fef72ce
AK		 1685 emulate_1op_rax_rdx("mul", ctxt->src, *rax, *rdx,
1686 ctxt->eflags, de);
3f9f53b0
MG		 1687 break;
1688 case 5: /* imul */
9fef72ce
AK		 1689 emulate_1op_rax_rdx("imul", ctxt->src, *rax, *rdx,
1690 ctxt->eflags, de);
3f9f53b0
MG		 1691 break;
1692 case 6: /* div */
9fef72ce
AK		 1693 emulate_1op_rax_rdx("div", ctxt->src, *rax, *rdx,
1694 ctxt->eflags, de);
3f9f53b0
MG		 1695 break;
1696 case 7: /* idiv */
9fef72ce
AK		 1697 emulate_1op_rax_rdx("idiv", ctxt->src, *rax, *rdx,
1698 ctxt->eflags, de);
3f9f53b0 1699 break;
8cdbd2c9 1700 default:
8c5eee30 1701 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1702 }
34d1f490
AK		 1703 if (de)
1704 return emulate_de(ctxt);
8c5eee30 1705 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1706}
1707
51187683 1708static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1709{
4179bb02 1710 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1711
9dac77fa 1712 switch (ctxt->modrm_reg) {
8cdbd2c9 1713 case 0: /* inc */
d1eef45d 1714 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1715 break;
1716 case 1: /* dec */
d1eef45d 1717 emulate_1op(ctxt, "dec");
8cdbd2c9 1718 break;
d19292e4
MG		 1719 case 2: /* call near abs */ {
1720 long int old_eip;
9dac77fa
AK		 1721 old_eip = ctxt->_eip;
1722 ctxt->_eip = ctxt->src.val;
1723 ctxt->src.val = old_eip;
4487b3b4 1724 rc = em_push(ctxt);
d19292e4
MG		 1725 break;
1726 }
8cdbd2c9 1727 case 4: /* jmp abs */
9dac77fa 1728 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1729 break;
d2f62766
TY		 1730 case 5: /* jmp far */
1731 rc = em_jmp_far(ctxt);
1732 break;
8cdbd2c9 1733 case 6: /* push */
4487b3b4 1734 rc = em_push(ctxt);
8cdbd2c9 1735 break;
8cdbd2c9 1736 }
4179bb02 1737 return rc;
8cdbd2c9
LV		 1738}
1739
51187683 1740static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1741{
9dac77fa 1742 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1743
9dac77fa
AK		 1744 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1745 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1746 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1747 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1748 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1749 } else {
9dac77fa
AK		 1750 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1751 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1752
05f086f8 1753 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1754 }
1b30eaa8 1755 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1756}
1757
ebda02c2
TY		 1758static int em_ret(struct x86_emulate_ctxt *ctxt)
1759{
9dac77fa
AK		 1760 ctxt->dst.type = OP_REG;
1761 ctxt->dst.addr.reg = &ctxt->_eip;
1762 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1763 return em_pop(ctxt);
1764}
1765
e01991e7 1766static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1767{
a77ab5ea
AK		 1768 int rc;
1769 unsigned long cs;
1770
9dac77fa 1771 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1772 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1773 return rc;
9dac77fa
AK		 1774 if (ctxt->op_bytes == 4)
1775 ctxt->_eip = (u32)ctxt->_eip;
1776 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1777 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1778 return rc;
7b105ca2 1779 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1780 return rc;
1781}
1782
7b105ca2 1783static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
09b5f4d3 1784{
09b5f4d3
WY		 1785 unsigned short sel;
1786 int rc;
1787
9dac77fa 1788 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1789
7b105ca2 1790 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1791 if (rc != X86EMUL_CONTINUE)
1792 return rc;
1793
9dac77fa 1794 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1795 return rc;
1796}
1797
7b105ca2 1798static void
e66bb2cc 1799setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1800 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1801{
1aa36616
AK		 1802 u16 selector;
1803
79168fd1 1804 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1805 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1806 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1807
1808 cs->l = 0; /* will be adjusted later */
79168fd1 1809 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1810 cs->g = 1; /* 4kb granularity */
79168fd1 1811 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1812 cs->type = 0x0b; /* Read, Execute, Accessed */
1813 cs->s = 1;
1814 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1815 cs->p = 1;
1816 cs->d = 1;
e66bb2cc 1817
79168fd1
GN		 1818 set_desc_base(ss, 0); /* flat segment */
1819 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1820 ss->g = 1; /* 4kb granularity */
1821 ss->s = 1;
1822 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1823 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1824 ss->dpl = 0;
79168fd1 1825 ss->p = 1;
e66bb2cc
AP		 1826}
1827
e01991e7 1828static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1829{
7b105ca2 1830 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1831 struct desc_struct cs, ss;
e66bb2cc 1832 u64 msr_data;
79168fd1 1833 u16 cs_sel, ss_sel;
c2ad2bb3 1834 u64 efer = 0;
e66bb2cc
AP		 1835
1836 /* syscall is not available in real mode */
2e901c4c 1837 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1838 ctxt->mode == X86EMUL_MODE_VM86)
1839 return emulate_ud(ctxt);
e66bb2cc 1840
c2ad2bb3 1841 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1842 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1843
717746e3 1844 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1845 msr_data >>= 32;
79168fd1
GN		 1846 cs_sel = (u16)(msr_data & 0xfffc);
1847 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1848
c2ad2bb3 1849 if (efer & EFER_LMA) {
79168fd1 1850 cs.d = 0;
e66bb2cc
AP		 1851 cs.l = 1;
1852 }
1aa36616
AK		 1853 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1854 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1855
9dac77fa 1856 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1857 if (efer & EFER_LMA) {
e66bb2cc 1858#ifdef CONFIG_X86_64
9dac77fa 1859 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1860
717746e3 1861 ops->get_msr(ctxt,
3fb1b5db
GN		 1862 ctxt->mode == X86EMUL_MODE_PROT64 ?
1863 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1864 ctxt->_eip = msr_data;
e66bb2cc 1865
717746e3 1866 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1867 ctxt->eflags &= ~(msr_data | EFLG_RF);
1868#endif
1869 } else {
1870 /* legacy mode */
717746e3 1871 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1872 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1873
1874 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1875 }
1876
e54cfa97 1877 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1878}
1879
e01991e7 1880static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1881{
7b105ca2 1882 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1883 struct desc_struct cs, ss;
8c604352 1884 u64 msr_data;
79168fd1 1885 u16 cs_sel, ss_sel;
c2ad2bb3 1886 u64 efer = 0;
8c604352 1887
7b105ca2 1888 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1889 /* inject #GP if in real mode */
35d3d4a1
AK		 1890 if (ctxt->mode == X86EMUL_MODE_REAL)
1891 return emulate_gp(ctxt, 0);
8c604352
AP		 1892
1893 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1894 * Therefore, we inject an #UD.
1895 */
35d3d4a1
AK		 1896 if (ctxt->mode == X86EMUL_MODE_PROT64)
1897 return emulate_ud(ctxt);
8c604352 1898
7b105ca2 1899 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1900
717746e3 1901 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1902 switch (ctxt->mode) {
1903 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1904 if ((msr_data & 0xfffc) == 0x0)
1905 return emulate_gp(ctxt, 0);
8c604352
AP		 1906 break;
1907 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1908 if (msr_data == 0x0)
1909 return emulate_gp(ctxt, 0);
8c604352
AP		 1910 break;
1911 }
1912
1913 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1914 cs_sel = (u16)msr_data;
1915 cs_sel &= ~SELECTOR_RPL_MASK;
1916 ss_sel = cs_sel + 8;
1917 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1918 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1919 cs.d = 0;
8c604352
AP		 1920 cs.l = 1;
1921 }
1922
1aa36616
AK		 1923 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1924 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1925
717746e3 1926 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1927 ctxt->_eip = msr_data;
8c604352 1928
717746e3 1929 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1930 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1931
e54cfa97 1932 return X86EMUL_CONTINUE;
8c604352
AP		 1933}
1934
e01991e7 1935static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1936{
7b105ca2 1937 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1938 struct desc_struct cs, ss;
4668f050
AP		 1939 u64 msr_data;
1940 int usermode;
1249b96e 1941 u16 cs_sel = 0, ss_sel = 0;
4668f050 1942
a0044755
GN		 1943 /* inject #GP if in real mode or Virtual 8086 mode */
1944 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1945 ctxt->mode == X86EMUL_MODE_VM86)
1946 return emulate_gp(ctxt, 0);
4668f050 1947
7b105ca2 1948 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 1949
9dac77fa 1950 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 1951 usermode = X86EMUL_MODE_PROT64;
1952 else
1953 usermode = X86EMUL_MODE_PROT32;
1954
1955 cs.dpl = 3;
1956 ss.dpl = 3;
717746e3 1957 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1958 switch (usermode) {
1959 case X86EMUL_MODE_PROT32:
79168fd1 1960 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1961 if ((msr_data & 0xfffc) == 0x0)
1962 return emulate_gp(ctxt, 0);
79168fd1 1963 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1964 break;
1965 case X86EMUL_MODE_PROT64:
79168fd1 1966 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1967 if (msr_data == 0x0)
1968 return emulate_gp(ctxt, 0);
79168fd1
GN		 1969 ss_sel = cs_sel + 8;
1970 cs.d = 0;
4668f050
AP		 1971 cs.l = 1;
1972 break;
1973 }
79168fd1
GN		 1974 cs_sel |= SELECTOR_RPL_MASK;
1975 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1976
1aa36616
AK		 1977 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1978 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 1979
9dac77fa
AK		 1980 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
1981 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 1982
e54cfa97 1983 return X86EMUL_CONTINUE;
4668f050
AP		 1984}
1985
7b105ca2 1986static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 1987{
1988 int iopl;
1989 if (ctxt->mode == X86EMUL_MODE_REAL)
1990 return false;
1991 if (ctxt->mode == X86EMUL_MODE_VM86)
1992 return true;
1993 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1994 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 1995}
1996
1997static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 1998 u16 port, u16 len)
1999{
7b105ca2 2000 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2001 struct desc_struct tr_seg;
5601d05b 2002 u32 base3;
f850e2e6 2003 int r;
1aa36616 2004 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2005 unsigned mask = (1 << len) - 1;
5601d05b 2006 unsigned long base;
f850e2e6 2007
1aa36616 2008 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2009 if (!tr_seg.p)
f850e2e6 2010 return false;
79168fd1 2011 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2012 return false;
5601d05b
GN		 2013 base = get_desc_base(&tr_seg);
2014#ifdef CONFIG_X86_64
2015 base |= ((u64)base3) << 32;
2016#endif
0f65dd70 2017 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2018 if (r != X86EMUL_CONTINUE)
2019 return false;
79168fd1 2020 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2021 return false;
0f65dd70 2022 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2023 if (r != X86EMUL_CONTINUE)
2024 return false;
2025 if ((perm >> bit_idx) & mask)
2026 return false;
2027 return true;
2028}
2029
2030static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2031 u16 port, u16 len)
2032{
4fc40f07
GN		 2033 if (ctxt->perm_ok)
2034 return true;
2035
7b105ca2
TY		 2036 if (emulator_bad_iopl(ctxt))
2037 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2038 return false;
4fc40f07
GN		 2039
2040 ctxt->perm_ok = true;
2041
f850e2e6
GN		 2042 return true;
2043}
2044
38ba30ba 2045static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2046 struct tss_segment_16 *tss)
2047{
9dac77fa 2048 tss->ip = ctxt->_eip;
38ba30ba 2049 tss->flag = ctxt->eflags;
9dac77fa
AK		 2050 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2051 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2052 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2053 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2054 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2055 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2056 tss->si = ctxt->regs[VCPU_REGS_RSI];
2057 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2058
1aa36616
AK		 2059 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2060 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2061 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2062 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2063 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2064}
2065
2066static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2067 struct tss_segment_16 *tss)
2068{
38ba30ba
GN		 2069 int ret;
2070
9dac77fa 2071 ctxt->_eip = tss->ip;
38ba30ba 2072 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2073 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2074 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2075 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2076 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2077 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2078 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2079 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2080 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2081
2082 /*
2083 * SDM says that segment selectors are loaded before segment
2084 * descriptors
2085 */
1aa36616
AK		 2086 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2087 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2088 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2089 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2090 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2091
2092 /*
2093 * Now load segment descriptors. If fault happenes at this stage
2094 * it is handled in a context of new task
2095 */
7b105ca2 2096 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2097 if (ret != X86EMUL_CONTINUE)
2098 return ret;
7b105ca2 2099 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2100 if (ret != X86EMUL_CONTINUE)
2101 return ret;
7b105ca2 2102 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2103 if (ret != X86EMUL_CONTINUE)
2104 return ret;
7b105ca2 2105 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2106 if (ret != X86EMUL_CONTINUE)
2107 return ret;
7b105ca2 2108 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2109 if (ret != X86EMUL_CONTINUE)
2110 return ret;
2111
2112 return X86EMUL_CONTINUE;
2113}
2114
2115static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2116 u16 tss_selector, u16 old_tss_sel,
2117 ulong old_tss_base, struct desc_struct *new_desc)
2118{
7b105ca2 2119 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2120 struct tss_segment_16 tss_seg;
2121 int ret;
bcc55cba 2122 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2123
0f65dd70 2124 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2125 &ctxt->exception);
db297e3d 2126 if (ret != X86EMUL_CONTINUE)
38ba30ba 2127 /* FIXME: need to provide precise fault address */
38ba30ba 2128 return ret;
38ba30ba 2129
7b105ca2 2130 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2131
0f65dd70 2132 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2133 &ctxt->exception);
db297e3d 2134 if (ret != X86EMUL_CONTINUE)
38ba30ba 2135 /* FIXME: need to provide precise fault address */
38ba30ba 2136 return ret;
38ba30ba 2137
0f65dd70 2138 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2139 &ctxt->exception);
db297e3d 2140 if (ret != X86EMUL_CONTINUE)
38ba30ba 2141 /* FIXME: need to provide precise fault address */
38ba30ba 2142 return ret;
38ba30ba
GN		 2143
2144 if (old_tss_sel != 0xffff) {
2145 tss_seg.prev_task_link = old_tss_sel;
2146
0f65dd70 2147 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2148 &tss_seg.prev_task_link,
2149 sizeof tss_seg.prev_task_link,
0f65dd70 2150 &ctxt->exception);
db297e3d 2151 if (ret != X86EMUL_CONTINUE)
38ba30ba 2152 /* FIXME: need to provide precise fault address */
38ba30ba 2153 return ret;
38ba30ba
GN		 2154 }
2155
7b105ca2 2156 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2157}
2158
2159static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2160 struct tss_segment_32 *tss)
2161{
7b105ca2 2162 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2163 tss->eip = ctxt->_eip;
38ba30ba 2164 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2165 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2166 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2167 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2168 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2169 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2170 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2171 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2172 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2173
1aa36616
AK		 2174 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2175 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2176 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2177 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2178 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2179 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2180 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2181}
2182
2183static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2184 struct tss_segment_32 *tss)
2185{
38ba30ba
GN		 2186 int ret;
2187
7b105ca2 2188 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2189 return emulate_gp(ctxt, 0);
9dac77fa 2190 ctxt->_eip = tss->eip;
38ba30ba 2191 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2192 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2193 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2194 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2195 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2196 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2197 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2198 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2199 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2200
2201 /*
2202 * SDM says that segment selectors are loaded before segment
2203 * descriptors
2204 */
1aa36616
AK		 2205 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2206 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2207 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2208 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2209 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2210 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2211 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2212
2213 /*
2214 * Now load segment descriptors. If fault happenes at this stage
2215 * it is handled in a context of new task
2216 */
7b105ca2 2217 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2218 if (ret != X86EMUL_CONTINUE)
2219 return ret;
7b105ca2 2220 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2221 if (ret != X86EMUL_CONTINUE)
2222 return ret;
7b105ca2 2223 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2224 if (ret != X86EMUL_CONTINUE)
2225 return ret;
7b105ca2 2226 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2227 if (ret != X86EMUL_CONTINUE)
2228 return ret;
7b105ca2 2229 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2230 if (ret != X86EMUL_CONTINUE)
2231 return ret;
7b105ca2 2232 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2233 if (ret != X86EMUL_CONTINUE)
2234 return ret;
7b105ca2 2235 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2236 if (ret != X86EMUL_CONTINUE)
2237 return ret;
2238
2239 return X86EMUL_CONTINUE;
2240}
2241
2242static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2243 u16 tss_selector, u16 old_tss_sel,
2244 ulong old_tss_base, struct desc_struct *new_desc)
2245{
7b105ca2 2246 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2247 struct tss_segment_32 tss_seg;
2248 int ret;
bcc55cba 2249 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2250
0f65dd70 2251 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2252 &ctxt->exception);
db297e3d 2253 if (ret != X86EMUL_CONTINUE)
38ba30ba 2254 /* FIXME: need to provide precise fault address */
38ba30ba 2255 return ret;
38ba30ba 2256
7b105ca2 2257 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2258
0f65dd70 2259 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2260 &ctxt->exception);
db297e3d 2261 if (ret != X86EMUL_CONTINUE)
38ba30ba 2262 /* FIXME: need to provide precise fault address */
38ba30ba 2263 return ret;
38ba30ba 2264
0f65dd70 2265 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2266 &ctxt->exception);
db297e3d 2267 if (ret != X86EMUL_CONTINUE)
38ba30ba 2268 /* FIXME: need to provide precise fault address */
38ba30ba 2269 return ret;
38ba30ba
GN		 2270
2271 if (old_tss_sel != 0xffff) {
2272 tss_seg.prev_task_link = old_tss_sel;
2273
0f65dd70 2274 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2275 &tss_seg.prev_task_link,
2276 sizeof tss_seg.prev_task_link,
0f65dd70 2277 &ctxt->exception);
db297e3d 2278 if (ret != X86EMUL_CONTINUE)
38ba30ba 2279 /* FIXME: need to provide precise fault address */
38ba30ba 2280 return ret;
38ba30ba
GN		 2281 }
2282
7b105ca2 2283 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2284}
2285
2286static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2287 u16 tss_selector, int reason,
2288 bool has_error_code, u32 error_code)
38ba30ba 2289{
7b105ca2 2290 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2291 struct desc_struct curr_tss_desc, next_tss_desc;
2292 int ret;
1aa36616 2293 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2294 ulong old_tss_base =
4bff1e86 2295 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2296 u32 desc_limit;
38ba30ba
GN		 2297
2298 /* FIXME: old_tss_base == ~0 ? */
2299
7b105ca2 2300 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2301 if (ret != X86EMUL_CONTINUE)
2302 return ret;
7b105ca2 2303 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2304 if (ret != X86EMUL_CONTINUE)
2305 return ret;
2306
2307 /* FIXME: check that next_tss_desc is tss */
2308
2309 if (reason != TASK_SWITCH_IRET) {
2310 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2311 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2312 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2313 }
2314
ceffb459
GN		 2315 desc_limit = desc_limit_scaled(&next_tss_desc);
2316 if (!next_tss_desc.p ||
2317 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2318 desc_limit < 0x2b)) {
54b8486f 2319 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2320 return X86EMUL_PROPAGATE_FAULT;
2321 }
2322
2323 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2324 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2325 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2326 }
2327
2328 if (reason == TASK_SWITCH_IRET)
2329 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2330
2331 /* set back link to prev task only if NT bit is set in eflags
2332 note that old_tss_sel is not used afetr this point */
2333 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2334 old_tss_sel = 0xffff;
2335
2336 if (next_tss_desc.type & 8)
7b105ca2 2337 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2338 old_tss_base, &next_tss_desc);
2339 else
7b105ca2 2340 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2341 old_tss_base, &next_tss_desc);
0760d448
JK		 2342 if (ret != X86EMUL_CONTINUE)
2343 return ret;
38ba30ba
GN		 2344
2345 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2346 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2347
2348 if (reason != TASK_SWITCH_IRET) {
2349 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2350 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2351 }
2352
717746e3 2353 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2354 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2355
e269fb21 2356 if (has_error_code) {
9dac77fa
AK		 2357 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2358 ctxt->lock_prefix = 0;
2359 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2360 ret = em_push(ctxt);
e269fb21
JK		 2361 }
2362
38ba30ba
GN		 2363 return ret;
2364}
2365
2366int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2367 u16 tss_selector, int reason,
2368 bool has_error_code, u32 error_code)
38ba30ba 2369{
38ba30ba
GN		 2370 int rc;
2371
9dac77fa
AK		 2372 ctxt->_eip = ctxt->eip;
2373 ctxt->dst.type = OP_NONE;
38ba30ba 2374
7b105ca2 2375 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2376 has_error_code, error_code);
38ba30ba 2377
4179bb02 2378 if (rc == X86EMUL_CONTINUE)
9dac77fa 2379 ctxt->eip = ctxt->_eip;
38ba30ba 2380
a0c0ab2f 2381 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2382}
2383
90de84f5 2384static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2385 int reg, struct operand *op)
a682e354 2386{
a682e354
GN		 2387 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2388
9dac77fa
AK		 2389 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2390 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2391 op->addr.mem.seg = seg;
a682e354
GN		 2392}
2393
7af04fc0
AK		 2394static int em_das(struct x86_emulate_ctxt *ctxt)
2395{
7af04fc0
AK		 2396 u8 al, old_al;
2397 bool af, cf, old_cf;
2398
2399 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2400 al = ctxt->dst.val;
7af04fc0
AK		 2401
2402 old_al = al;
2403 old_cf = cf;
2404 cf = false;
2405 af = ctxt->eflags & X86_EFLAGS_AF;
2406 if ((al & 0x0f) > 9 || af) {
2407 al -= 6;
2408 cf = old_cf | (al >= 250);
2409 af = true;
2410 } else {
2411 af = false;
2412 }
2413 if (old_al > 0x99 || old_cf) {
2414 al -= 0x60;
2415 cf = true;
2416 }
2417
9dac77fa 2418 ctxt->dst.val = al;
7af04fc0 2419 /* Set PF, ZF, SF */
9dac77fa
AK		 2420 ctxt->src.type = OP_IMM;
2421 ctxt->src.val = 0;
2422 ctxt->src.bytes = 1;
a31b9cea 2423 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2424 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2425 if (cf)
2426 ctxt->eflags |= X86_EFLAGS_CF;
2427 if (af)
2428 ctxt->eflags |= X86_EFLAGS_AF;
2429 return X86EMUL_CONTINUE;
2430}
2431
0ef753b8
AK		 2432static int em_call_far(struct x86_emulate_ctxt *ctxt)
2433{
0ef753b8
AK		 2434 u16 sel, old_cs;
2435 ulong old_eip;
2436 int rc;
2437
1aa36616 2438 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2439 old_eip = ctxt->_eip;
0ef753b8 2440
9dac77fa 2441 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2442 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2443 return X86EMUL_CONTINUE;
2444
9dac77fa
AK		 2445 ctxt->_eip = 0;
2446 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2447
9dac77fa 2448 ctxt->src.val = old_cs;
4487b3b4 2449 rc = em_push(ctxt);
0ef753b8
AK		 2450 if (rc != X86EMUL_CONTINUE)
2451 return rc;
2452
9dac77fa 2453 ctxt->src.val = old_eip;
4487b3b4 2454 return em_push(ctxt);
0ef753b8
AK		 2455}
2456
40ece7c7
AK		 2457static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2458{
40ece7c7
AK		 2459 int rc;
2460
9dac77fa
AK		 2461 ctxt->dst.type = OP_REG;
2462 ctxt->dst.addr.reg = &ctxt->_eip;
2463 ctxt->dst.bytes = ctxt->op_bytes;
2464 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2465 if (rc != X86EMUL_CONTINUE)
2466 return rc;
9dac77fa 2467 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2468 return X86EMUL_CONTINUE;
2469}
2470
d67fc27a
TY		 2471static int em_add(struct x86_emulate_ctxt *ctxt)
2472{
a31b9cea 2473 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2474 return X86EMUL_CONTINUE;
2475}
2476
2477static int em_or(struct x86_emulate_ctxt *ctxt)
2478{
a31b9cea 2479 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2480 return X86EMUL_CONTINUE;
2481}
2482
2483static int em_adc(struct x86_emulate_ctxt *ctxt)
2484{
a31b9cea 2485 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2486 return X86EMUL_CONTINUE;
2487}
2488
2489static int em_sbb(struct x86_emulate_ctxt *ctxt)
2490{
a31b9cea 2491 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2492 return X86EMUL_CONTINUE;
2493}
2494
2495static int em_and(struct x86_emulate_ctxt *ctxt)
2496{
a31b9cea 2497 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2498 return X86EMUL_CONTINUE;
2499}
2500
2501static int em_sub(struct x86_emulate_ctxt *ctxt)
2502{
a31b9cea 2503 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2504 return X86EMUL_CONTINUE;
2505}
2506
2507static int em_xor(struct x86_emulate_ctxt *ctxt)
2508{
a31b9cea 2509 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2510 return X86EMUL_CONTINUE;
2511}
2512
2513static int em_cmp(struct x86_emulate_ctxt *ctxt)
2514{
a31b9cea 2515 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2516 /* Disable writeback. */
9dac77fa 2517 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2518 return X86EMUL_CONTINUE;
2519}
2520
9f21ca59
TY		 2521static int em_test(struct x86_emulate_ctxt *ctxt)
2522{
a31b9cea 2523 emulate_2op_SrcV(ctxt, "test");
9f21ca59
TY		 2524 return X86EMUL_CONTINUE;
2525}
2526
e4f973ae
TY		 2527static int em_xchg(struct x86_emulate_ctxt *ctxt)
2528{
e4f973ae 2529 /* Write back the register source. */
9dac77fa
AK		 2530 ctxt->src.val = ctxt->dst.val;
2531 write_register_operand(&ctxt->src);
e4f973ae
TY		 2532
2533 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2534 ctxt->dst.val = ctxt->src.orig_val;
2535 ctxt->lock_prefix = 1;
e4f973ae
TY		 2536 return X86EMUL_CONTINUE;
2537}
2538
5c82aa29 2539static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2540{
a31b9cea 2541 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2542 return X86EMUL_CONTINUE;
2543}
2544
5c82aa29
AK		 2545static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2546{
9dac77fa 2547 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2548 return em_imul(ctxt);
2549}
2550
61429142
AK		 2551static int em_cwd(struct x86_emulate_ctxt *ctxt)
2552{
9dac77fa
AK		 2553 ctxt->dst.type = OP_REG;
2554 ctxt->dst.bytes = ctxt->src.bytes;
2555 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2556 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2557
2558 return X86EMUL_CONTINUE;
2559}
2560
48bb5d3c
AK		 2561static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2562{
48bb5d3c
AK		 2563 u64 tsc = 0;
2564
717746e3 2565 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2566 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2567 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2568 return X86EMUL_CONTINUE;
2569}
2570
b9eac5f4
AK		 2571static int em_mov(struct x86_emulate_ctxt *ctxt)
2572{
9dac77fa 2573 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2574 return X86EMUL_CONTINUE;
2575}
2576
1bd5f469
TY		 2577static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2578{
9dac77fa 2579 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2580 return emulate_ud(ctxt);
2581
9dac77fa 2582 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2583 return X86EMUL_CONTINUE;
2584}
2585
2586static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2587{
9dac77fa 2588 u16 sel = ctxt->src.val;
1bd5f469 2589
9dac77fa 2590 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2591 return emulate_ud(ctxt);
2592
9dac77fa 2593 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2594 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2595
2596 /* Disable writeback. */
9dac77fa
AK		 2597 ctxt->dst.type = OP_NONE;
2598 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2599}
2600
aa97bb48
AK		 2601static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2602{
9dac77fa 2603 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2604 return X86EMUL_CONTINUE;
2605}
2606
38503911
AK		 2607static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2608{
9fa088f4
AK		 2609 int rc;
2610 ulong linear;
2611
9dac77fa 2612 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2613 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2614 ctxt->ops->invlpg(ctxt, linear);
38503911 2615 /* Disable writeback. */
9dac77fa 2616 ctxt->dst.type = OP_NONE;
38503911
AK		 2617 return X86EMUL_CONTINUE;
2618}
2619
2d04a05b
AK		 2620static int em_clts(struct x86_emulate_ctxt *ctxt)
2621{
2622 ulong cr0;
2623
2624 cr0 = ctxt->ops->get_cr(ctxt, 0);
2625 cr0 &= ~X86_CR0_TS;
2626 ctxt->ops->set_cr(ctxt, 0, cr0);
2627 return X86EMUL_CONTINUE;
2628}
2629
26d05cc7
AK		 2630static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2631{
26d05cc7
AK		 2632 int rc;
2633
9dac77fa 2634 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2635 return X86EMUL_UNHANDLEABLE;
2636
2637 rc = ctxt->ops->fix_hypercall(ctxt);
2638 if (rc != X86EMUL_CONTINUE)
2639 return rc;
2640
2641 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2642 ctxt->_eip = ctxt->eip;
26d05cc7 2643 /* Disable writeback. */
9dac77fa 2644 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2645 return X86EMUL_CONTINUE;
2646}
2647
2648static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2649{
26d05cc7
AK		 2650 struct desc_ptr desc_ptr;
2651 int rc;
2652
9dac77fa 2653 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2654 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2655 ctxt->op_bytes);
26d05cc7
AK		 2656 if (rc != X86EMUL_CONTINUE)
2657 return rc;
2658 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2659 /* Disable writeback. */
9dac77fa 2660 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2661 return X86EMUL_CONTINUE;
2662}
2663
5ef39c71 2664static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2665{
26d05cc7
AK		 2666 int rc;
2667
5ef39c71
AK		 2668 rc = ctxt->ops->fix_hypercall(ctxt);
2669
26d05cc7 2670 /* Disable writeback. */
9dac77fa 2671 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2672 return rc;
2673}
2674
2675static int em_lidt(struct x86_emulate_ctxt *ctxt)
2676{
26d05cc7
AK		 2677 struct desc_ptr desc_ptr;
2678 int rc;
2679
9dac77fa 2680 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2681 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2682 ctxt->op_bytes);
26d05cc7
AK		 2683 if (rc != X86EMUL_CONTINUE)
2684 return rc;
2685 ctxt->ops->set_idt(ctxt, &desc_ptr);
2686 /* Disable writeback. */
9dac77fa 2687 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2688 return X86EMUL_CONTINUE;
2689}
2690
2691static int em_smsw(struct x86_emulate_ctxt *ctxt)
2692{
9dac77fa
AK		 2693 ctxt->dst.bytes = 2;
2694 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2695 return X86EMUL_CONTINUE;
2696}
2697
2698static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2699{
26d05cc7 2700 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2701 | (ctxt->src.val & 0x0f));
2702 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2703 return X86EMUL_CONTINUE;
2704}
2705
d06e03ad
TY		 2706static int em_loop(struct x86_emulate_ctxt *ctxt)
2707{
9dac77fa
AK		 2708 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2709 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2710 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2711 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2712
2713 return X86EMUL_CONTINUE;
2714}
2715
2716static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2717{
9dac77fa
AK		 2718 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2719 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2720
2721 return X86EMUL_CONTINUE;
2722}
2723
f411e6cd
TY		 2724static int em_cli(struct x86_emulate_ctxt *ctxt)
2725{
2726 if (emulator_bad_iopl(ctxt))
2727 return emulate_gp(ctxt, 0);
2728
2729 ctxt->eflags &= ~X86_EFLAGS_IF;
2730 return X86EMUL_CONTINUE;
2731}
2732
2733static int em_sti(struct x86_emulate_ctxt *ctxt)
2734{
2735 if (emulator_bad_iopl(ctxt))
2736 return emulate_gp(ctxt, 0);
2737
2738 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2739 ctxt->eflags |= X86_EFLAGS_IF;
2740 return X86EMUL_CONTINUE;
2741}
2742
cfec82cb
JR		 2743static bool valid_cr(int nr)
2744{
2745 switch (nr) {
2746 case 0:
2747 case 2 ... 4:
2748 case 8:
2749 return true;
2750 default:
2751 return false;
2752 }
2753}
2754
2755static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2756{
9dac77fa 2757 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2758 return emulate_ud(ctxt);
2759
2760 return X86EMUL_CONTINUE;
2761}
2762
2763static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2764{
9dac77fa
AK		 2765 u64 new_val = ctxt->src.val64;
2766 int cr = ctxt->modrm_reg;
c2ad2bb3 2767 u64 efer = 0;
cfec82cb
JR		 2768
2769 static u64 cr_reserved_bits[] = {
2770 0xffffffff00000000ULL,
2771 0, 0, 0, /* CR3 checked later */
2772 CR4_RESERVED_BITS,
2773 0, 0, 0,
2774 CR8_RESERVED_BITS,
2775 };
2776
2777 if (!valid_cr(cr))
2778 return emulate_ud(ctxt);
2779
2780 if (new_val & cr_reserved_bits[cr])
2781 return emulate_gp(ctxt, 0);
2782
2783 switch (cr) {
2784 case 0: {
c2ad2bb3 2785 u64 cr4;
cfec82cb
JR		 2786 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2787 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2788 return emulate_gp(ctxt, 0);
2789
717746e3
AK		 2790 cr4 = ctxt->ops->get_cr(ctxt, 4);
2791 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2792
2793 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2794 !(cr4 & X86_CR4_PAE))
2795 return emulate_gp(ctxt, 0);
2796
2797 break;
2798 }
2799 case 3: {
2800 u64 rsvd = 0;
2801
c2ad2bb3
AK		 2802 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2803 if (efer & EFER_LMA)
cfec82cb 2804 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2805 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2806 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2807 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2808 rsvd = CR3_NONPAE_RESERVED_BITS;
2809
2810 if (new_val & rsvd)
2811 return emulate_gp(ctxt, 0);
2812
2813 break;
2814 }
2815 case 4: {
c2ad2bb3 2816 u64 cr4;
cfec82cb 2817
717746e3
AK		 2818 cr4 = ctxt->ops->get_cr(ctxt, 4);
2819 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2820
2821 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2822 return emulate_gp(ctxt, 0);
2823
2824 break;
2825 }
2826 }
2827
2828 return X86EMUL_CONTINUE;
2829}
2830
3b88e41a
JR		 2831static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2832{
2833 unsigned long dr7;
2834
717746e3 2835 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2836
2837 /* Check if DR7.Global_Enable is set */
2838 return dr7 & (1 << 13);
2839}
2840
2841static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2842{
9dac77fa 2843 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2844 u64 cr4;
2845
2846 if (dr > 7)
2847 return emulate_ud(ctxt);
2848
717746e3 2849 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2850 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2851 return emulate_ud(ctxt);
2852
2853 if (check_dr7_gd(ctxt))
2854 return emulate_db(ctxt);
2855
2856 return X86EMUL_CONTINUE;
2857}
2858
2859static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2860{
9dac77fa
AK		 2861 u64 new_val = ctxt->src.val64;
2862 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2863
2864 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2865 return emulate_gp(ctxt, 0);
2866
2867 return check_dr_read(ctxt);
2868}
2869
01de8b09
JR		 2870static int check_svme(struct x86_emulate_ctxt *ctxt)
2871{
2872 u64 efer;
2873
717746e3 2874 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2875
2876 if (!(efer & EFER_SVME))
2877 return emulate_ud(ctxt);
2878
2879 return X86EMUL_CONTINUE;
2880}
2881
2882static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2883{
9dac77fa 2884 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2885
2886 /* Valid physical address? */
d4224449 2887 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2888 return emulate_gp(ctxt, 0);
2889
2890 return check_svme(ctxt);
2891}
2892
d7eb8203
JR		 2893static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2894{
717746e3 2895 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2896
717746e3 2897 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2898 return emulate_ud(ctxt);
2899
2900 return X86EMUL_CONTINUE;
2901}
2902
8061252e
JR		 2903static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2904{
717746e3 2905 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2906 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2907
717746e3 2908 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2909 (rcx > 3))
2910 return emulate_gp(ctxt, 0);
2911
2912 return X86EMUL_CONTINUE;
2913}
2914
f6511935
JR		 2915static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2916{
9dac77fa
AK		 2917 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2918 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2919 return emulate_gp(ctxt, 0);
2920
2921 return X86EMUL_CONTINUE;
2922}
2923
2924static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2925{
9dac77fa
AK		 2926 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2927 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2928 return emulate_gp(ctxt, 0);
2929
2930 return X86EMUL_CONTINUE;
2931}
2932
73fba5f4 2933#define D(_y) { .flags = (_y) }
c4f035c6 2934#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2935#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2936 .check_perm = (_p) }
73fba5f4 2937#define N D(0)
01de8b09 2938#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2939#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2940#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2941#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2942#define II(_f, _e, _i) \
2943 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2944#define IIP(_f, _e, _i, _p) \
2945 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2946 .check_perm = (_p) }
aa97bb48 2947#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2948
8d8f4e9f 2949#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2950#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2951#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2952
d67fc27a
TY		 2953#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2954 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2955 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 2956
d7eb8203
JR		 2957static struct opcode group7_rm1[] = {
2958 DI(SrcNone | ModRM | Priv, monitor),
2959 DI(SrcNone | ModRM | Priv, mwait),
2960 N, N, N, N, N, N,
2961};
2962
01de8b09
JR		 2963static struct opcode group7_rm3[] = {
2964 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 2965 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 2966 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2967 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2968 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2969 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2970 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2971 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2972};
6230f7fc 2973
d7eb8203
JR		 2974static struct opcode group7_rm7[] = {
2975 N,
2976 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2977 N, N, N, N, N, N,
2978};
d67fc27a 2979
73fba5f4 2980static struct opcode group1[] = {
d67fc27a
TY		 2981 I(Lock, em_add),
2982 I(Lock, em_or),
2983 I(Lock, em_adc),
2984 I(Lock, em_sbb),
2985 I(Lock, em_and),
2986 I(Lock, em_sub),
2987 I(Lock, em_xor),
2988 I(0, em_cmp),
73fba5f4
AK		 2989};
2990
2991static struct opcode group1A[] = {
2992 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2993};
2994
2995static struct opcode group3[] = {
2996 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2997 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2998 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2999};
3000
3001static struct opcode group4[] = {
3002 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3003 N, N, N, N, N, N,
3004};
3005
3006static struct opcode group5[] = {
3007 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3008 D(SrcMem | ModRM | Stack),
3009 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3010 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3011 D(SrcMem | ModRM | Stack), N,
3012};
3013
dee6bb70
JR		 3014static struct opcode group6[] = {
3015 DI(ModRM | Prot, sldt),
3016 DI(ModRM | Prot, str),
3017 DI(ModRM | Prot | Priv, lldt),
3018 DI(ModRM | Prot | Priv, ltr),
3019 N, N, N, N,
3020};
3021
73fba5f4 3022static struct group_dual group7 = { {
dee6bb70
JR		 3023 DI(ModRM | Mov | DstMem | Priv, sgdt),
3024 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3025 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3026 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3027 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3028 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3029 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3030}, {
5ef39c71
AK		 3031 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3032 EXT(0, group7_rm1),
01de8b09 3033 N, EXT(0, group7_rm3),
5ef39c71
AK		 3034 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3035 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3036} };
3037
3038static struct opcode group8[] = {
3039 N, N, N, N,
3040 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3041 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3042};
3043
3044static struct group_dual group9 = { {
3045 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3046}, {
3047 N, N, N, N, N, N, N, N,
3048} };
3049
a4d4a7c1
AK		 3050static struct opcode group11[] = {
3051 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3052};
3053
aa97bb48
AK		 3054static struct gprefix pfx_0f_6f_0f_7f = {
3055 N, N, N, I(Sse, em_movdqu),
3056};
3057
73fba5f4
AK		 3058static struct opcode opcode_table[256] = {
3059 /* 0x00 - 0x07 */
d67fc27a 3060 I6ALU(Lock, em_add),
73fba5f4
AK		 3061 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3062 /* 0x08 - 0x0F */
d67fc27a 3063 I6ALU(Lock, em_or),
73fba5f4
AK		 3064 D(ImplicitOps | Stack | No64), N,
3065 /* 0x10 - 0x17 */
d67fc27a 3066 I6ALU(Lock, em_adc),
73fba5f4
AK		 3067 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3068 /* 0x18 - 0x1F */
d67fc27a 3069 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3070 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3071 /* 0x20 - 0x27 */
d67fc27a 3072 I6ALU(Lock, em_and), N, N,
73fba5f4 3073 /* 0x28 - 0x2F */
d67fc27a 3074 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3075 /* 0x30 - 0x37 */
d67fc27a 3076 I6ALU(Lock, em_xor), N, N,
73fba5f4 3077 /* 0x38 - 0x3F */
d67fc27a 3078 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3079 /* 0x40 - 0x4F */
3080 X16(D(DstReg)),
3081 /* 0x50 - 0x57 */
63540382 3082 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3083 /* 0x58 - 0x5F */
c54fe504 3084 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3085 /* 0x60 - 0x67 */
b96a7fad
TY		 3086 I(ImplicitOps | Stack | No64, em_pusha),
3087 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3088 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3089 N, N, N, N,
3090 /* 0x68 - 0x6F */
d46164db
AK		 3091 I(SrcImm | Mov | Stack, em_push),
3092 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3093 I(SrcImmByte | Mov | Stack, em_push),
3094 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3095 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3096 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3097 /* 0x70 - 0x7F */
3098 X16(D(SrcImmByte)),
3099 /* 0x80 - 0x87 */
3100 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3101 G(DstMem | SrcImm | ModRM | Group, group1),
3102 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3103 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3104 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3105 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3106 /* 0x88 - 0x8F */
b9eac5f4
AK		 3107 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3108 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3109 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3110 D(ModRM | SrcMem | NoAccess | DstReg),
3111 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3112 G(0, group1A),
73fba5f4 3113 /* 0x90 - 0x97 */
bf608f88 3114 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3115 /* 0x98 - 0x9F */
61429142 3116 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3117 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3118 II(ImplicitOps | Stack, em_pushf, pushf),
3119 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3120 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3121 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3122 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3123 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3124 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3125 /* 0xA8 - 0xAF */
9f21ca59 3126 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3127 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3128 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3129 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3130 /* 0xB0 - 0xB7 */
b9eac5f4 3131 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3132 /* 0xB8 - 0xBF */
b9eac5f4 3133 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3134 /* 0xC0 - 0xC7 */
d2c6c7ad 3135 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3136 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3137 I(ImplicitOps | Stack, em_ret),
09b5f4d3 3138 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3139 G(ByteOp, group11), G(0, group11),
73fba5f4 3140 /* 0xC8 - 0xCF */
db5b0762 3141 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3142 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3143 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3144 /* 0xD0 - 0xD7 */
d2c6c7ad 3145 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3146 N, N, N, N,
3147 /* 0xD8 - 0xDF */
3148 N, N, N, N, N, N, N, N,
3149 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3150 X3(I(SrcImmByte, em_loop)),
3151 I(SrcImmByte, em_jcxz),
f6511935
JR		 3152 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3153 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3154 /* 0xE8 - 0xEF */
3155 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3156 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3157 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3158 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3159 /* 0xF0 - 0xF7 */
bf608f88 3160 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3161 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3162 G(ByteOp, group3), G(0, group3),
73fba5f4 3163 /* 0xF8 - 0xFF */
f411e6cd
TY		 3164 D(ImplicitOps), D(ImplicitOps),
3165 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3166 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3167};
3168
3169static struct opcode twobyte_table[256] = {
3170 /* 0x00 - 0x0F */
dee6bb70 3171 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3172 N, I(ImplicitOps | VendorSpecific, em_syscall),
3173 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3174 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3175 N, D(ImplicitOps | ModRM), N, N,
3176 /* 0x10 - 0x1F */
3177 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3178 /* 0x20 - 0x2F */
cfec82cb 3179 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3180 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3181 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3182 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3183 N, N, N, N,
3184 N, N, N, N, N, N, N, N,
3185 /* 0x30 - 0x3F */
8061252e
JR		 3186 DI(ImplicitOps | Priv, wrmsr),
3187 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3188 DI(ImplicitOps | Priv, rdmsr),
3189 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3190 I(ImplicitOps | VendorSpecific, em_sysenter),
3191 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3192 N, N,
73fba5f4
AK		 3193 N, N, N, N, N, N, N, N,
3194 /* 0x40 - 0x4F */
3195 X16(D(DstReg | SrcMem | ModRM | Mov)),
3196 /* 0x50 - 0x5F */
3197 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3198 /* 0x60 - 0x6F */
aa97bb48
AK		 3199 N, N, N, N,
3200 N, N, N, N,
3201 N, N, N, N,
3202 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3203 /* 0x70 - 0x7F */
aa97bb48
AK		 3204 N, N, N, N,
3205 N, N, N, N,
3206 N, N, N, N,
3207 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3208 /* 0x80 - 0x8F */
3209 X16(D(SrcImm)),
3210 /* 0x90 - 0x9F */
ee45b58e 3211 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3212 /* 0xA0 - 0xA7 */
3213 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3214 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3215 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3216 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3217 /* 0xA8 - 0xAF */
3218 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3219 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3220 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3221 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3222 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3223 /* 0xB0 - 0xB7 */
739ae406 3224 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3225 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3226 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3227 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3228 /* 0xB8 - 0xBF */
3229 N, N,
ba7ff2b7 3230 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3231 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3232 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3233 /* 0xC0 - 0xCF */
739ae406 3234 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3235 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3236 N, N, N, GD(0, &group9),
3237 N, N, N, N, N, N, N, N,
3238 /* 0xD0 - 0xDF */
3239 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3240 /* 0xE0 - 0xEF */
3241 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3242 /* 0xF0 - 0xFF */
3243 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3244};
3245
3246#undef D
3247#undef N
3248#undef G
3249#undef GD
3250#undef I
aa97bb48 3251#undef GP
01de8b09 3252#undef EXT
73fba5f4 3253
8d8f4e9f 3254#undef D2bv
f6511935 3255#undef D2bvIP
8d8f4e9f 3256#undef I2bv
d67fc27a 3257#undef I6ALU
8d8f4e9f 3258
9dac77fa 3259static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3260{
3261 unsigned size;
3262
9dac77fa 3263 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3264 if (size == 8)
3265 size = 4;
3266 return size;
3267}
3268
3269static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3270 unsigned size, bool sign_extension)
3271{
39f21ee5
AK		 3272 int rc = X86EMUL_CONTINUE;
3273
3274 op->type = OP_IMM;
3275 op->bytes = size;
9dac77fa 3276 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3277 /* NB. Immediates are sign-extended as necessary. */
3278 switch (op->bytes) {
3279 case 1:
e85a1085 3280 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3281 break;
3282 case 2:
e85a1085 3283 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3284 break;
3285 case 4:
e85a1085 3286 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3287 break;
3288 }
3289 if (!sign_extension) {
3290 switch (op->bytes) {
3291 case 1:
3292 op->val &= 0xff;
3293 break;
3294 case 2:
3295 op->val &= 0xffff;
3296 break;
3297 case 4:
3298 op->val &= 0xffffffff;
3299 break;
3300 }
3301 }
3302done:
3303 return rc;
3304}
3305
ef5d75cc 3306int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3307{
dde7e6d1
AK		 3308 int rc = X86EMUL_CONTINUE;
3309 int mode = ctxt->mode;
46561646 3310 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3311 bool op_prefix = false;
46561646 3312 struct opcode opcode;
cb16c348 3313 struct operand memop = { .type = OP_NONE }, *memopp = NULL;
dde7e6d1 3314
9dac77fa
AK		 3315 ctxt->_eip = ctxt->eip;
3316 ctxt->fetch.start = ctxt->_eip;
3317 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3318 if (insn_len > 0)
9dac77fa 3319 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3320
3321 switch (mode) {
3322 case X86EMUL_MODE_REAL:
3323 case X86EMUL_MODE_VM86:
3324 case X86EMUL_MODE_PROT16:
3325 def_op_bytes = def_ad_bytes = 2;
3326 break;
3327 case X86EMUL_MODE_PROT32:
3328 def_op_bytes = def_ad_bytes = 4;
3329 break;
3330#ifdef CONFIG_X86_64
3331 case X86EMUL_MODE_PROT64:
3332 def_op_bytes = 4;
3333 def_ad_bytes = 8;
3334 break;
3335#endif
3336 default:
1d2887e2 3337 return EMULATION_FAILED;
dde7e6d1
AK		 3338 }
3339
9dac77fa
AK		 3340 ctxt->op_bytes = def_op_bytes;
3341 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3342
3343 /* Legacy prefixes. */
3344 for (;;) {
e85a1085 3345 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3346 case 0x66: /* operand-size override */
0d7cdee8 3347 op_prefix = true;
dde7e6d1 3348 /* switch between 2/4 bytes */
9dac77fa 3349 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3350 break;
3351 case 0x67: /* address-size override */
3352 if (mode == X86EMUL_MODE_PROT64)
3353 /* switch between 4/8 bytes */
9dac77fa 3354 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3355 else
3356 /* switch between 2/4 bytes */
9dac77fa 3357 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3358 break;
3359 case 0x26: /* ES override */
3360 case 0x2e: /* CS override */
3361 case 0x36: /* SS override */
3362 case 0x3e: /* DS override */
9dac77fa 3363 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3364 break;
3365 case 0x64: /* FS override */
3366 case 0x65: /* GS override */
9dac77fa 3367 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3368 break;
3369 case 0x40 ... 0x4f: /* REX */
3370 if (mode != X86EMUL_MODE_PROT64)
3371 goto done_prefixes;
9dac77fa 3372 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3373 continue;
3374 case 0xf0: /* LOCK */
9dac77fa 3375 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3376 break;
3377 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3378 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3379 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3380 break;
3381 default:
3382 goto done_prefixes;
3383 }
3384
3385 /* Any legacy prefix after a REX prefix nullifies its effect. */
3386
9dac77fa 3387 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3388 }
3389
3390done_prefixes:
3391
3392 /* REX prefix. */
9dac77fa
AK		 3393 if (ctxt->rex_prefix & 8)
3394 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3395
3396 /* Opcode byte(s). */
9dac77fa 3397 opcode = opcode_table[ctxt->b];
d3ad6243 3398 /* Two-byte opcode? */
9dac77fa
AK		 3399 if (ctxt->b == 0x0f) {
3400 ctxt->twobyte = 1;
e85a1085 3401 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3402 opcode = twobyte_table[ctxt->b];
dde7e6d1 3403 }
9dac77fa 3404 ctxt->d = opcode.flags;
dde7e6d1 3405
9dac77fa
AK		 3406 while (ctxt->d & GroupMask) {
3407 switch (ctxt->d & GroupMask) {
46561646 3408 case Group:
e85a1085 3409 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3410 --ctxt->_eip;
3411 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3412 opcode = opcode.u.group[goffset];
3413 break;
3414 case GroupDual:
e85a1085 3415 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3416 --ctxt->_eip;
3417 goffset = (ctxt->modrm >> 3) & 7;
3418 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3419 opcode = opcode.u.gdual->mod3[goffset];
3420 else
3421 opcode = opcode.u.gdual->mod012[goffset];
3422 break;
3423 case RMExt:
9dac77fa 3424 goffset = ctxt->modrm & 7;
01de8b09 3425 opcode = opcode.u.group[goffset];
46561646
AK		 3426 break;
3427 case Prefix:
9dac77fa 3428 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3429 return EMULATION_FAILED;
9dac77fa 3430 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3431 switch (simd_prefix) {
3432 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3433 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3434 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3435 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3436 }
3437 break;
3438 default:
1d2887e2 3439 return EMULATION_FAILED;
0d7cdee8 3440 }
46561646 3441
9dac77fa
AK		 3442 ctxt->d &= ~GroupMask;
3443 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3444 }
3445
9dac77fa
AK		 3446 ctxt->execute = opcode.u.execute;
3447 ctxt->check_perm = opcode.check_perm;
3448 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3449
3450 /* Unrecognised? */
9dac77fa 3451 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3452 return EMULATION_FAILED;
dde7e6d1 3453
9dac77fa 3454 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3455 return EMULATION_FAILED;
d867162c 3456
9dac77fa
AK		 3457 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3458 ctxt->op_bytes = 8;
dde7e6d1 3459
9dac77fa 3460 if (ctxt->d & Op3264) {
7f9b4b75 3461 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3462 ctxt->op_bytes = 8;
7f9b4b75 3463 else
9dac77fa 3464 ctxt->op_bytes = 4;
7f9b4b75
AK		 3465 }
3466
9dac77fa
AK		 3467 if (ctxt->d & Sse)
3468 ctxt->op_bytes = 16;
1253791d 3469
dde7e6d1 3470 /* ModRM and SIB bytes. */
9dac77fa 3471 if (ctxt->d & ModRM) {
ef5d75cc 3472 rc = decode_modrm(ctxt, &memop);
9dac77fa
AK		 3473 if (!ctxt->has_seg_override)
3474 set_seg_override(ctxt, ctxt->modrm_seg);
3475 } else if (ctxt->d & MemAbs)
ef5d75cc 3476 rc = decode_abs(ctxt, &memop);
dde7e6d1
AK		 3477 if (rc != X86EMUL_CONTINUE)
3478 goto done;
3479
9dac77fa
AK		 3480 if (!ctxt->has_seg_override)
3481 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3482
9dac77fa 3483 memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3484
9dac77fa 3485 if (memop.type == OP_MEM && ctxt->ad_bytes != 8)
90de84f5 3486 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3487
dde7e6d1
AK		 3488 /*
3489 * Decode and fetch the source operand: register, memory
3490 * or immediate.
3491 */
9dac77fa 3492 switch (ctxt->d & SrcMask) {
dde7e6d1
AK		 3493 case SrcNone:
3494 break;
3495 case SrcReg:
9dac77fa 3496 decode_register_operand(ctxt, &ctxt->src, 0);
dde7e6d1
AK		 3497 break;
3498 case SrcMem16:
2dbd0dd7 3499 memop.bytes = 2;
dde7e6d1
AK		 3500 goto srcmem_common;
3501 case SrcMem32:
2dbd0dd7 3502 memop.bytes = 4;
dde7e6d1
AK		 3503 goto srcmem_common;
3504 case SrcMem:
9dac77fa
AK		 3505 memop.bytes = (ctxt->d & ByteOp) ? 1 :
3506 ctxt->op_bytes;
dde7e6d1 3507 srcmem_common:
9dac77fa
AK		 3508 ctxt->src = memop;
3509 memopp = &ctxt->src;
dde7e6d1 3510 break;
b250e605 3511 case SrcImmU16:
9dac77fa 3512 rc = decode_imm(ctxt, &ctxt->src, 2, false);
39f21ee5 3513 break;
dde7e6d1 3514 case SrcImm:
9dac77fa 3515 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
39f21ee5 3516 break;
dde7e6d1 3517 case SrcImmU:
9dac77fa 3518 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
dde7e6d1
AK		 3519 break;
3520 case SrcImmByte:
9dac77fa 3521 rc = decode_imm(ctxt, &ctxt->src, 1, true);
39f21ee5 3522 break;
dde7e6d1 3523 case SrcImmUByte:
9dac77fa 3524 rc = decode_imm(ctxt, &ctxt->src, 1, false);
dde7e6d1
AK		 3525 break;
3526 case SrcAcc:
9dac77fa
AK		 3527 ctxt->src.type = OP_REG;
3528 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3529 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3530 fetch_register_operand(&ctxt->src);
dde7e6d1
AK		 3531 break;
3532 case SrcOne:
9dac77fa
AK		 3533 ctxt->src.bytes = 1;
3534 ctxt->src.val = 1;
dde7e6d1
AK		 3535 break;
3536 case SrcSI:
9dac77fa
AK		 3537 ctxt->src.type = OP_MEM;
3538 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3539 ctxt->src.addr.mem.ea =
3540 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3541 ctxt->src.addr.mem.seg = seg_override(ctxt);
3542 ctxt->src.val = 0;
dde7e6d1
AK		 3543 break;
3544 case SrcImmFAddr:
9dac77fa
AK		 3545 ctxt->src.type = OP_IMM;
3546 ctxt->src.addr.mem.ea = ctxt->_eip;
3547 ctxt->src.bytes = ctxt->op_bytes + 2;
807941b1 3548 insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
dde7e6d1
AK		 3549 break;
3550 case SrcMemFAddr:
9dac77fa 3551 memop.bytes = ctxt->op_bytes + 2;
2dbd0dd7 3552 goto srcmem_common;
dde7e6d1 3553 break;
221192bd 3554 case SrcDX:
9dac77fa
AK		 3555 ctxt->src.type = OP_REG;
3556 ctxt->src.bytes = 2;
3557 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3558 fetch_register_operand(&ctxt->src);
221192bd 3559 break;
dde7e6d1
AK		 3560 }
3561
39f21ee5
AK		 3562 if (rc != X86EMUL_CONTINUE)
3563 goto done;
3564
dde7e6d1
AK		 3565 /*
3566 * Decode and fetch the second source operand: register, memory
3567 * or immediate.
3568 */
9dac77fa 3569 switch (ctxt->d & Src2Mask) {
dde7e6d1
AK		 3570 case Src2None:
3571 break;
3572 case Src2CL:
9dac77fa 3573 ctxt->src2.bytes = 1;
9be3be1f 3574 ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
dde7e6d1
AK		 3575 break;
3576 case Src2ImmByte:
9dac77fa 3577 rc = decode_imm(ctxt, &ctxt->src2, 1, true);
dde7e6d1
AK		 3578 break;
3579 case Src2One:
9dac77fa
AK		 3580 ctxt->src2.bytes = 1;
3581 ctxt->src2.val = 1;
dde7e6d1 3582 break;
7db41eb7 3583 case Src2Imm:
9dac77fa 3584 rc = decode_imm(ctxt, &ctxt->src2, imm_size(ctxt), true);
7db41eb7 3585 break;
dde7e6d1
AK		 3586 }
3587
39f21ee5
AK		 3588 if (rc != X86EMUL_CONTINUE)
3589 goto done;
3590
dde7e6d1 3591 /* Decode and fetch the destination operand: register or memory. */
9dac77fa 3592 switch (ctxt->d & DstMask) {
dde7e6d1 3593 case DstReg:
9dac77fa
AK		 3594 decode_register_operand(ctxt, &ctxt->dst,
3595 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
dde7e6d1 3596 break;
943858e2 3597 case DstImmUByte:
9dac77fa
AK		 3598 ctxt->dst.type = OP_IMM;
3599 ctxt->dst.addr.mem.ea = ctxt->_eip;
3600 ctxt->dst.bytes = 1;
e85a1085 3601 ctxt->dst.val = insn_fetch(u8, ctxt);
943858e2 3602 break;
dde7e6d1
AK		 3603 case DstMem:
3604 case DstMem64:
9dac77fa
AK		 3605 ctxt->dst = memop;
3606 memopp = &ctxt->dst;
3607 if ((ctxt->d & DstMask) == DstMem64)
3608 ctxt->dst.bytes = 8;
dde7e6d1 3609 else
9dac77fa
AK		 3610 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3611 if (ctxt->d & BitOp)
3612 fetch_bit_operand(ctxt);
3613 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3614 break;
3615 case DstAcc:
9dac77fa
AK		 3616 ctxt->dst.type = OP_REG;
3617 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3618 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3619 fetch_register_operand(&ctxt->dst);
3620 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3621 break;
3622 case DstDI:
9dac77fa
AK		 3623 ctxt->dst.type = OP_MEM;
3624 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3625 ctxt->dst.addr.mem.ea =
3626 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3627 ctxt->dst.addr.mem.seg = VCPU_SREG_ES;
3628 ctxt->dst.val = 0;
dde7e6d1 3629 break;
221192bd 3630 case DstDX:
9dac77fa
AK		 3631 ctxt->dst.type = OP_REG;
3632 ctxt->dst.bytes = 2;
3633 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3634 fetch_register_operand(&ctxt->dst);
221192bd 3635 break;
36089fed
WY		 3636 case ImplicitOps:
3637 /* Special instructions do their own operand decoding. */
3638 default:
9dac77fa 3639 ctxt->dst.type = OP_NONE; /* Disable writeback. */
cb16c348 3640 break;
dde7e6d1
AK		 3641 }
3642
3643done:
9dac77fa
AK		 3644 if (memopp && memopp->type == OP_MEM && ctxt->rip_relative)
3645 memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3646
1d2887e2 3647 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3648}
3649
3e2f65d5
GN		 3650static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3651{
3e2f65d5
GN		 3652 /* The second termination condition only applies for REPE
3653 * and REPNE. Test if the repeat string operation prefix is
3654 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3655 * corresponding termination condition according to:
3656 * - if REPE/REPZ and ZF = 0 then done
3657 * - if REPNE/REPNZ and ZF = 1 then done
3658 */
9dac77fa
AK		 3659 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3660 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3661 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3662 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3663 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3664 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3665 return true;
3666
3667 return false;
3668}
3669
7b105ca2 3670int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3671{
9aabc88f 3672 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3673 u64 msr_data;
1b30eaa8 3674 int rc = X86EMUL_CONTINUE;
9dac77fa 3675 int saved_dst_type = ctxt->dst.type;
8b4caf66 3676
9dac77fa 3677 ctxt->mem_read.pos = 0;
310b5d30 3678
9dac77fa 3679 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3680 rc = emulate_ud(ctxt);
1161624f
GN		 3681 goto done;
3682 }
3683
d380a5e4 3684 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3685 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3686 rc = emulate_ud(ctxt);
d380a5e4
GN		 3687 goto done;
3688 }
3689
9dac77fa 3690 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3691 rc = emulate_ud(ctxt);
081bca0e
AK		 3692 goto done;
3693 }
3694
9dac77fa 3695 if ((ctxt->d & Sse)
717746e3
AK		 3696 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3697 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3698 rc = emulate_ud(ctxt);
3699 goto done;
3700 }
3701
9dac77fa 3702 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3703 rc = emulate_nm(ctxt);
3704 goto done;
3705 }
3706
9dac77fa
AK		 3707 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3708 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3709 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3710 if (rc != X86EMUL_CONTINUE)
3711 goto done;
3712 }
3713
e92805ac 3714 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3715 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3716 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3717 goto done;
3718 }
3719
8ea7d6ae 3720 /* Instruction can only be executed in protected mode */
9dac77fa 3721 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3722 rc = emulate_ud(ctxt);
3723 goto done;
3724 }
3725
d09beabd 3726 /* Do instruction specific permission checks */
9dac77fa
AK		 3727 if (ctxt->check_perm) {
3728 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3729 if (rc != X86EMUL_CONTINUE)
3730 goto done;
3731 }
3732
9dac77fa
AK		 3733 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3734 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3735 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3736 if (rc != X86EMUL_CONTINUE)
3737 goto done;
3738 }
3739
9dac77fa 3740 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3741 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3742 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3743 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3744 goto done;
3745 }
b9fa9d6b
AK		 3746 }
3747
9dac77fa
AK		 3748 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3749 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3750 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3751 if (rc != X86EMUL_CONTINUE)
8b4caf66 3752 goto done;
9dac77fa 3753 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3754 }
3755
9dac77fa
AK		 3756 if (ctxt->src2.type == OP_MEM) {
3757 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3758 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3759 if (rc != X86EMUL_CONTINUE)
3760 goto done;
3761 }
3762
9dac77fa 3763 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3764 goto special_insn;
3765
3766
9dac77fa 3767 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3768 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3769 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3770 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3771 if (rc != X86EMUL_CONTINUE)
3772 goto done;
038e51de 3773 }
9dac77fa 3774 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3775
018a98db
AK		 3776special_insn:
3777
9dac77fa
AK		 3778 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3779 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3780 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3781 if (rc != X86EMUL_CONTINUE)
3782 goto done;
3783 }
3784
9dac77fa
AK		 3785 if (ctxt->execute) {
3786 rc = ctxt->execute(ctxt);
ef65c889
AK		 3787 if (rc != X86EMUL_CONTINUE)
3788 goto done;
3789 goto writeback;
3790 }
3791
9dac77fa 3792 if (ctxt->twobyte)
6aa8b732
AK		 3793 goto twobyte_insn;
3794
9dac77fa 3795 switch (ctxt->b) {
0934ac9d 3796 case 0x06: /* push es */
7b105ca2 3797 rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
0934ac9d
MG		 3798 break;
3799 case 0x07: /* pop es */
7b105ca2 3800 rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
0934ac9d 3801 break;
0934ac9d 3802 case 0x0e: /* push cs */
7b105ca2 3803 rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
0934ac9d 3804 break;
0934ac9d 3805 case 0x16: /* push ss */
7b105ca2 3806 rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
0934ac9d
MG		 3807 break;
3808 case 0x17: /* pop ss */
7b105ca2 3809 rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
0934ac9d 3810 break;
0934ac9d 3811 case 0x1e: /* push ds */
7b105ca2 3812 rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
0934ac9d
MG		 3813 break;
3814 case 0x1f: /* pop ds */
7b105ca2 3815 rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
0934ac9d 3816 break;
33615aa9 3817 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3818 emulate_1op(ctxt, "inc");
33615aa9
AK		 3819 break;
3820 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3821 emulate_1op(ctxt, "dec");
33615aa9 3822 break;
6aa8b732 3823 case 0x63: /* movsxd */
8b4caf66 3824 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3825 goto cannot_emulate;
9dac77fa 3826 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3827 break;
018a98db
AK		 3828 case 0x6c: /* insb */
3829 case 0x6d: /* insw/insd */
9dac77fa 3830 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3831 goto do_io_in;
018a98db
AK		 3832 case 0x6e: /* outsb */
3833 case 0x6f: /* outsw/outsd */
9dac77fa 3834 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3835 goto do_io_out;
7972995b 3836 break;
b2833e3c 3837 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3838 if (test_cc(ctxt->b, ctxt->eflags))
3839 jmp_rel(ctxt, ctxt->src.val);
018a98db 3840 break;
7e0b54b1 3841 case 0x8d: /* lea r16/r32, m */
9dac77fa 3842 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3843 break;
6aa8b732 3844 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3845 rc = em_grp1a(ctxt);
6aa8b732 3846 break;
3d9e77df 3847 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3848 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3849 break;
e4f973ae
TY		 3850 rc = em_xchg(ctxt);
3851 break;
e8b6fa70 3852 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3853 switch (ctxt->op_bytes) {
3854 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3855 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3856 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3857 }
3858 break;
018a98db 3859 case 0xc0 ... 0xc1:
51187683 3860 rc = em_grp2(ctxt);
018a98db 3861 break;
09b5f4d3 3862 case 0xc4: /* les */
7b105ca2 3863 rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
09b5f4d3
WY		 3864 break;
3865 case 0xc5: /* lds */
7b105ca2 3866 rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
09b5f4d3 3867 break;
6e154e56 3868 case 0xcc: /* int3 */
5c5df76b
TY		 3869 rc = emulate_int(ctxt, 3);
3870 break;
6e154e56 3871 case 0xcd: /* int n */
9dac77fa 3872 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3873 break;
3874 case 0xce: /* into */
5c5df76b
TY		 3875 if (ctxt->eflags & EFLG_OF)
3876 rc = emulate_int(ctxt, 4);
6e154e56 3877 break;
018a98db 3878 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3879 rc = em_grp2(ctxt);
018a98db
AK		 3880 break;
3881 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3882 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3883 rc = em_grp2(ctxt);
018a98db 3884 break;
a6a3034c
MG		 3885 case 0xe4: /* inb */
3886 case 0xe5: /* in */
cf8f70bf 3887 goto do_io_in;
a6a3034c
MG		 3888 case 0xe6: /* outb */
3889 case 0xe7: /* out */
cf8f70bf 3890 goto do_io_out;
1a52e051 3891 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3892 long int rel = ctxt->src.val;
3893 ctxt->src.val = (unsigned long) ctxt->_eip;
3894 jmp_rel(ctxt, rel);
4487b3b4 3895 rc = em_push(ctxt);
8cdbd2c9 3896 break;
1a52e051
NK		 3897 }
3898 case 0xe9: /* jmp rel */
db5b0762 3899 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3900 jmp_rel(ctxt, ctxt->src.val);
3901 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3902 break;
a6a3034c
MG		 3903 case 0xec: /* in al,dx */
3904 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3905 do_io_in:
9dac77fa
AK		 3906 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3907 &ctxt->dst.val))
cf8f70bf
GN		 3908 goto done; /* IO is needed */
3909 break;
ce7a0ad3
WY		 3910 case 0xee: /* out dx,al */
3911 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3912 do_io_out:
9dac77fa
AK		 3913 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3914 &ctxt->src.val, 1);
3915 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3916 break;
111de5d6 3917 case 0xf4: /* hlt */
6c3287f7 3918 ctxt->ops->halt(ctxt);
19fdfa0d 3919 break;
111de5d6
AK		 3920 case 0xf5: /* cmc */
3921 /* complement carry flag from eflags reg */
3922 ctxt->eflags ^= EFLG_CF;
111de5d6 3923 break;
018a98db 3924 case 0xf6 ... 0xf7: /* Grp3 */
51187683 3925 rc = em_grp3(ctxt);
018a98db 3926 break;
111de5d6
AK		 3927 case 0xf8: /* clc */
3928 ctxt->eflags &= ~EFLG_CF;
111de5d6 3929 break;
8744aa9a
MG		 3930 case 0xf9: /* stc */
3931 ctxt->eflags |= EFLG_CF;
3932 break;
fb4616f4
MG		 3933 case 0xfc: /* cld */
3934 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3935 break;
3936 case 0xfd: /* std */
3937 ctxt->eflags |= EFLG_DF;
fb4616f4 3938 break;
ea79849d 3939 case 0xfe: /* Grp4 */
51187683 3940 rc = em_grp45(ctxt);
018a98db 3941 break;
ea79849d 3942 case 0xff: /* Grp5 */
51187683
TY		 3943 rc = em_grp45(ctxt);
3944 break;
91269b8f
AK		 3945 default:
3946 goto cannot_emulate;
6aa8b732 3947 }
018a98db 3948
7d9ddaed
AK		 3949 if (rc != X86EMUL_CONTINUE)
3950 goto done;
3951
018a98db 3952writeback:
adddcecf 3953 rc = writeback(ctxt);
1b30eaa8 3954 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3955 goto done;
3956
5cd21917
GN		 3957 /*
3958 * restore dst type in case the decoding will be reused
3959 * (happens for string instruction )
3960 */
9dac77fa 3961 ctxt->dst.type = saved_dst_type;
5cd21917 3962
9dac77fa
AK		 3963 if ((ctxt->d & SrcMask) == SrcSI)
3964 string_addr_inc(ctxt, seg_override(ctxt),
3965 VCPU_REGS_RSI, &ctxt->src);
a682e354 3966
9dac77fa 3967 if ((ctxt->d & DstMask) == DstDI)
90de84f5 3968 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 3969 &ctxt->dst);
d9271123 3970
9dac77fa
AK		 3971 if (ctxt->rep_prefix && (ctxt->d & String)) {
3972 struct read_cache *r = &ctxt->io_read;
3973 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3974
d2ddd1c4
GN		 3975 if (!string_insn_completed(ctxt)) {
3976 /*
3977 * Re-enter guest when pio read ahead buffer is empty
3978 * or, if it is not used, after each 1024 iteration.
3979 */
9dac77fa 3980 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 3981 (r->end == 0 || r->end != r->pos)) {
3982 /*
3983 * Reset read cache. Usually happens before
3984 * decode, but since instruction is restarted
3985 * we have to do it here.
3986 */
9dac77fa 3987 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 3988 return EMULATION_RESTART;
3989 }
3990 goto done; /* skip rip writeback */
0fa6ccbd 3991 }
5cd21917 3992 }
d2ddd1c4 3993
9dac77fa 3994 ctxt->eip = ctxt->_eip;
018a98db
AK		 3995
3996done:
da9cb575
AK		 3997 if (rc == X86EMUL_PROPAGATE_FAULT)
3998 ctxt->have_exception = true;
775fde86
JR		 3999 if (rc == X86EMUL_INTERCEPTED)
4000 return EMULATION_INTERCEPTED;
4001
d2ddd1c4 4002 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4003
4004twobyte_insn:
9dac77fa 4005 switch (ctxt->b) {
018a98db 4006 case 0x09: /* wbinvd */
cfb22375 4007 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4008 break;
4009 case 0x08: /* invd */
018a98db
AK		 4010 case 0x0d: /* GrpP (prefetch) */
4011 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4012 break;
4013 case 0x20: /* mov cr, reg */
9dac77fa 4014 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4015 break;
6aa8b732 4016 case 0x21: /* mov from dr to reg */
9dac77fa 4017 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4018 break;
018a98db 4019 case 0x22: /* mov reg, cr */
9dac77fa 4020 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4021 emulate_gp(ctxt, 0);
da9cb575 4022 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4023 goto done;
4024 }
9dac77fa 4025 ctxt->dst.type = OP_NONE;
018a98db 4026 break;
6aa8b732 4027 case 0x23: /* mov from reg to dr */
9dac77fa 4028 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4029 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4030 ~0ULL : ~0U)) < 0) {
338dbc97 4031 /* #UD condition is already handled by the code above */
54b8486f 4032 emulate_gp(ctxt, 0);
da9cb575 4033 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4034 goto done;
4035 }
4036
9dac77fa 4037 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4038 break;
018a98db
AK		 4039 case 0x30:
4040 /* wrmsr */
9dac77fa
AK		 4041 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4042 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4043 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4044 emulate_gp(ctxt, 0);
da9cb575 4045 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4046 goto done;
018a98db
AK		 4047 }
4048 rc = X86EMUL_CONTINUE;
018a98db
AK		 4049 break;
4050 case 0x32:
4051 /* rdmsr */
9dac77fa 4052 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4053 emulate_gp(ctxt, 0);
da9cb575 4054 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4055 goto done;
018a98db 4056 } else {
9dac77fa
AK		 4057 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4058 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4059 }
4060 rc = X86EMUL_CONTINUE;
018a98db 4061 break;
6aa8b732 4062 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4063 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4064 if (!test_cc(ctxt->b, ctxt->eflags))
4065 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4066 break;
b2833e3c 4067 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4068 if (test_cc(ctxt->b, ctxt->eflags))
4069 jmp_rel(ctxt, ctxt->src.val);
018a98db 4070 break;
ee45b58e 4071 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4072 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4073 break;
0934ac9d 4074 case 0xa0: /* push fs */
7b105ca2 4075 rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
0934ac9d
MG		 4076 break;
4077 case 0xa1: /* pop fs */
7b105ca2 4078 rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
0934ac9d 4079 break;
7de75248
NK		 4080 case 0xa3:
4081 bt: /* bt */
9dac77fa 4082 ctxt->dst.type = OP_NONE;
e4e03ded 4083 /* only subword offset */
9dac77fa 4084 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4085 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4086 break;
9bf8ea42
GT		 4087 case 0xa4: /* shld imm8, r, r/m */
4088 case 0xa5: /* shld cl, r, r/m */
761441b9 4089 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4090 break;
0934ac9d 4091 case 0xa8: /* push gs */
7b105ca2 4092 rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
0934ac9d
MG		 4093 break;
4094 case 0xa9: /* pop gs */
7b105ca2 4095 rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
0934ac9d 4096 break;
7de75248
NK		 4097 case 0xab:
4098 bts: /* bts */
a31b9cea 4099 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4100 break;
9bf8ea42
GT		 4101 case 0xac: /* shrd imm8, r, r/m */
4102 case 0xad: /* shrd cl, r, r/m */
761441b9 4103 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4104 break;
2a7c5b8b
GC		 4105 case 0xae: /* clflush */
4106 break;
6aa8b732
AK		 4107 case 0xb0 ... 0xb1: /* cmpxchg */
4108 /*
4109 * Save real source value, then compare EAX against
4110 * destination.
4111 */
9dac77fa
AK		 4112 ctxt->src.orig_val = ctxt->src.val;
4113 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4114 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4115 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4116 /* Success: write back to memory. */
9dac77fa 4117 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4118 } else {
4119 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4120 ctxt->dst.type = OP_REG;
4121 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4122 }
4123 break;
09b5f4d3 4124 case 0xb2: /* lss */
7b105ca2 4125 rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
09b5f4d3 4126 break;
6aa8b732
AK		 4127 case 0xb3:
4128 btr: /* btr */
a31b9cea 4129 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4130 break;
09b5f4d3 4131 case 0xb4: /* lfs */
7b105ca2 4132 rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
09b5f4d3
WY		 4133 break;
4134 case 0xb5: /* lgs */
7b105ca2 4135 rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
09b5f4d3 4136 break;
6aa8b732 4137 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4138 ctxt->dst.bytes = ctxt->op_bytes;
4139 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4140 : (u16) ctxt->src.val;
6aa8b732 4141 break;
6aa8b732 4142 case 0xba: /* Grp8 */
9dac77fa 4143 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4144 case 0:
4145 goto bt;
4146 case 1:
4147 goto bts;
4148 case 2:
4149 goto btr;
4150 case 3:
4151 goto btc;
4152 }
4153 break;
7de75248
NK		 4154 case 0xbb:
4155 btc: /* btc */
a31b9cea 4156 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4157 break;
d9574a25
WY		 4158 case 0xbc: { /* bsf */
4159 u8 zf;
4160 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4161 : "=r"(ctxt->dst.val), "=q"(zf)
4162 : "r"(ctxt->src.val));
d9574a25
WY		 4163 ctxt->eflags &= ~X86_EFLAGS_ZF;
4164 if (zf) {
4165 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4166 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4167 }
4168 break;
4169 }
4170 case 0xbd: { /* bsr */
4171 u8 zf;
4172 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4173 : "=r"(ctxt->dst.val), "=q"(zf)
4174 : "r"(ctxt->src.val));
d9574a25
WY		 4175 ctxt->eflags &= ~X86_EFLAGS_ZF;
4176 if (zf) {
4177 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4178 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4179 }
4180 break;
4181 }
6aa8b732 4182 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4183 ctxt->dst.bytes = ctxt->op_bytes;
4184 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4185 (s16) ctxt->src.val;
6aa8b732 4186 break;
92f738a5 4187 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4188 emulate_2op_SrcV(ctxt, "add");
92f738a5 4189 /* Write back the register source. */
9dac77fa
AK		 4190 ctxt->src.val = ctxt->dst.orig_val;
4191 write_register_operand(&ctxt->src);
92f738a5 4192 break;
a012e65a 4193 case 0xc3: /* movnti */
9dac77fa
AK		 4194 ctxt->dst.bytes = ctxt->op_bytes;
4195 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4196 (u64) ctxt->src.val;
a012e65a 4197 break;
6aa8b732 4198 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4199 rc = em_grp9(ctxt);
8cdbd2c9 4200 break;
91269b8f
AK		 4201 default:
4202 goto cannot_emulate;
6aa8b732 4203 }
7d9ddaed
AK		 4204
4205 if (rc != X86EMUL_CONTINUE)
4206 goto done;
4207
6aa8b732
AK		 4208 goto writeback;
4209
4210cannot_emulate:
a0c0ab2f 4211 return EMULATION_FAILED;
6aa8b732 4212}
Linux kernel - Deliverables
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