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KVM: emulator: emulate AAM
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 135#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 136/* Source 2 operand type */
0b789eee 137#define Src2Shift (31)
4dd6a57d
AK		 138#define Src2None (OpNone << Src2Shift)
139#define Src2CL (OpCL << Src2Shift)
140#define Src2ImmByte (OpImmByte << Src2Shift)
141#define Src2One (OpOne << Src2Shift)
142#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 143#define Src2ES (OpES << Src2Shift)
144#define Src2CS (OpCS << Src2Shift)
145#define Src2SS (OpSS << Src2Shift)
146#define Src2DS (OpDS << Src2Shift)
147#define Src2FS (OpFS << Src2Shift)
148#define Src2GS (OpGS << Src2Shift)
4dd6a57d 149#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 150#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 151#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
152#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
153#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 154#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 155#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 156
d0e53325
AK		 157#define X2(x...) x, x
158#define X3(x...) X2(x), x
159#define X4(x...) X2(x), X2(x)
160#define X5(x...) X4(x), x
161#define X6(x...) X4(x), X2(x)
162#define X7(x...) X4(x), X3(x)
163#define X8(x...) X4(x), X4(x)
164#define X16(x...) X8(x), X8(x)
83babbca 165
e28bbd44
AK		 166#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
167#define FASTOP_SIZE 8
168
169/*
170 * fastop functions have a special calling convention:
171 *
172 * dst: [rdx]:rax (in/out)
173 * src: rbx (in/out)
174 * src2: rcx (in)
175 * flags: rflags (in/out)
176 *
177 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
178 * different operand sizes can be reached by calculation, rather than a jump
179 * table (which would be bigger than the code).
180 *
181 * fastop functions are declared as taking a never-defined fastop parameter,
182 * so they can't be called from C directly.
183 */
184
185struct fastop;
186
d65b1dee 187struct opcode {
b1ea50b2
AK		 188 u64 flags : 56;
189 u64 intercept : 8;
120df890 190 union {
ef65c889 191 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 192 const struct opcode *group;
193 const struct group_dual *gdual;
194 const struct gprefix *gprefix;
045a282c 195 const struct escape *esc;
e28bbd44 196 void (*fastop)(struct fastop *fake);
120df890 197 } u;
d09beabd 198 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 199};
200
201struct group_dual {
202 struct opcode mod012[8];
203 struct opcode mod3[8];
d65b1dee
AK		 204};
205
0d7cdee8
AK		 206struct gprefix {
207 struct opcode pfx_no;
208 struct opcode pfx_66;
209 struct opcode pfx_f2;
210 struct opcode pfx_f3;
211};
212
045a282c
GN		 213struct escape {
214 struct opcode op[8];
215 struct opcode high[64];
216};
217
6aa8b732 218/* EFLAGS bit definitions. */
d4c6a154
GN		 219#define EFLG_ID (1<<21)
220#define EFLG_VIP (1<<20)
221#define EFLG_VIF (1<<19)
222#define EFLG_AC (1<<18)
b1d86143
AP		 223#define EFLG_VM (1<<17)
224#define EFLG_RF (1<<16)
d4c6a154
GN		 225#define EFLG_IOPL (3<<12)
226#define EFLG_NT (1<<14)
6aa8b732
AK		 227#define EFLG_OF (1<<11)
228#define EFLG_DF (1<<10)
b1d86143 229#define EFLG_IF (1<<9)
d4c6a154 230#define EFLG_TF (1<<8)
6aa8b732
AK		 231#define EFLG_SF (1<<7)
232#define EFLG_ZF (1<<6)
233#define EFLG_AF (1<<4)
234#define EFLG_PF (1<<2)
235#define EFLG_CF (1<<0)
236
62bd430e
MG		 237#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
238#define EFLG_RESERVED_ONE_MASK 2
239
dd856efa
AK		 240static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
241{
242 if (!(ctxt->regs_valid & (1 << nr))) {
243 ctxt->regs_valid |= 1 << nr;
244 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
245 }
246 return ctxt->_regs[nr];
247}
248
249static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
250{
251 ctxt->regs_valid |= 1 << nr;
252 ctxt->regs_dirty |= 1 << nr;
253 return &ctxt->_regs[nr];
254}
255
256static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 reg_read(ctxt, nr);
259 return reg_write(ctxt, nr);
260}
261
262static void writeback_registers(struct x86_emulate_ctxt *ctxt)
263{
264 unsigned reg;
265
266 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
267 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
268}
269
270static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
271{
272 ctxt->regs_dirty = 0;
273 ctxt->regs_valid = 0;
274}
275
6aa8b732
AK		 276/*
277 * Instruction emulation:
278 * Most instructions are emulated directly via a fragment of inline assembly
279 * code. This allows us to save/restore EFLAGS and thus very easily pick up
280 * any modified flags.
281 */
282
05b3e0c2 283#if defined(CONFIG_X86_64)
6aa8b732
AK		 284#define _LO32 "k" /* force 32-bit operand */
285#define _STK "%%rsp" /* stack pointer */
286#elif defined(__i386__)
287#define _LO32 "" /* force 32-bit operand */
288#define _STK "%%esp" /* stack pointer */
289#endif
290
291/*
292 * These EFLAGS bits are restored from saved value during emulation, and
293 * any changes are written back to the saved value after emulation.
294 */
295#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
296
297/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 298#define _PRE_EFLAGS(_sav, _msk, _tmp) \
299 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
300 "movl %"_sav",%"_LO32 _tmp"; " \
301 "push %"_tmp"; " \
302 "push %"_tmp"; " \
303 "movl %"_msk",%"_LO32 _tmp"; " \
304 "andl %"_LO32 _tmp",("_STK"); " \
305 "pushf; " \
306 "notl %"_LO32 _tmp"; " \
307 "andl %"_LO32 _tmp",("_STK"); " \
308 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
309 "pop %"_tmp"; " \
310 "orl %"_LO32 _tmp",("_STK"); " \
311 "popf; " \
312 "pop %"_sav"; "
6aa8b732
AK		 313
314/* After executing instruction: write-back necessary bits in EFLAGS. */
315#define _POST_EFLAGS(_sav, _msk, _tmp) \
316 /* _sav |= EFLAGS & _msk; */ \
317 "pushf; " \
318 "pop %"_tmp"; " \
319 "andl %"_msk",%"_LO32 _tmp"; " \
320 "orl %"_LO32 _tmp",%"_sav"; "
321
dda96d8f
AK		 322#ifdef CONFIG_X86_64
323#define ON64(x) x
324#else
325#define ON64(x)
326#endif
327
a31b9cea 328#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 329 do { \
330 __asm__ __volatile__ ( \
331 _PRE_EFLAGS("0", "4", "2") \
332 _op _suffix " %"_x"3,%1; " \
333 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 334 : "=m" ((ctxt)->eflags), \
335 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 336 "=&r" (_tmp) \
a31b9cea 337 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 338 } while (0)
6b7ad61f
AK		 339
340
6aa8b732 341/* Raw emulation: instruction has two explicit operands. */
a31b9cea 342#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 343 do { \
344 unsigned long _tmp; \
345 \
a31b9cea 346 switch ((ctxt)->dst.bytes) { \
6b7ad61f 347 case 2: \
a31b9cea 348 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 349 break; \
350 case 4: \
a31b9cea 351 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 352 break; \
353 case 8: \
a31b9cea 354 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 355 break; \
356 } \
6aa8b732
AK		 357 } while (0)
358
a31b9cea 359#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 360 do { \
6b7ad61f 361 unsigned long _tmp; \
a31b9cea 362 switch ((ctxt)->dst.bytes) { \
6aa8b732 363 case 1: \
a31b9cea 364 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 365 break; \
366 default: \
a31b9cea 367 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 368 _wx, _wy, _lx, _ly, _qx, _qy); \
369 break; \
370 } \
371 } while (0)
372
373/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 374#define emulate_2op_SrcB(ctxt, _op) \
375 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 376
377/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 378#define emulate_2op_SrcV(ctxt, _op) \
379 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 380
381/* Source operand is word, long or quad sized. */
a31b9cea
AK		 382#define emulate_2op_SrcV_nobyte(ctxt, _op) \
383 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 384
d175226a 385/* Instruction has three operands and one operand is stored in ECX register */
29053a60 386#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 387 do { \
388 unsigned long _tmp; \
761441b9
AK		 389 _type _clv = (ctxt)->src2.val; \
390 _type _srcv = (ctxt)->src.val; \
391 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 392 \
393 __asm__ __volatile__ ( \
394 _PRE_EFLAGS("0", "5", "2") \
395 _op _suffix " %4,%1 \n" \
396 _POST_EFLAGS("0", "5", "2") \
761441b9 397 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 398 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
399 ); \
400 \
761441b9
AK		 401 (ctxt)->src2.val = (unsigned long) _clv; \
402 (ctxt)->src2.val = (unsigned long) _srcv; \
403 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 404 } while (0)
405
761441b9 406#define emulate_2op_cl(ctxt, _op) \
7295261c 407 do { \
761441b9 408 switch ((ctxt)->dst.bytes) { \
7295261c 409 case 2: \
29053a60 410 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 411 break; \
412 case 4: \
29053a60 413 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 414 break; \
415 case 8: \
29053a60 416 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 417 break; \
418 } \
d175226a
GT		 419 } while (0)
420
d1eef45d 421#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 422 do { \
423 unsigned long _tmp; \
424 \
dda96d8f
AK		 425 __asm__ __volatile__ ( \
426 _PRE_EFLAGS("0", "3", "2") \
427 _op _suffix " %1; " \
428 _POST_EFLAGS("0", "3", "2") \
d1eef45d 429 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 430 "=&r" (_tmp) \
431 : "i" (EFLAGS_MASK)); \
432 } while (0)
433
434/* Instruction has only one explicit operand (no source operand). */
d1eef45d 435#define emulate_1op(ctxt, _op) \
dda96d8f 436 do { \
d1eef45d
AK		 437 switch ((ctxt)->dst.bytes) { \
438 case 1: __emulate_1op(ctxt, _op, "b"); break; \
439 case 2: __emulate_1op(ctxt, _op, "w"); break; \
440 case 4: __emulate_1op(ctxt, _op, "l"); break; \
441 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 442 } \
443 } while (0)
444
4d758349
AK		 445static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
446
b7d491e7
AK		 447#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
448#define FOP_RET "ret \n\t"
449
450#define FOP_START(op) \
451 extern void em_##op(struct fastop *fake); \
452 asm(".pushsection .text, \"ax\" \n\t" \
453 ".global em_" #op " \n\t" \
454 FOP_ALIGN \
455 "em_" #op ": \n\t"
456
457#define FOP_END \
458 ".popsection")
459
0bdea068
AK		 460#define FOPNOP() FOP_ALIGN FOP_RET
461
b7d491e7
AK		 462#define FOP1E(op, dst) \
463 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
464
465#define FASTOP1(op) \
466 FOP_START(op) \
467 FOP1E(op##b, al) \
468 FOP1E(op##w, ax) \
469 FOP1E(op##l, eax) \
470 ON64(FOP1E(op##q, rax)) \
471 FOP_END
472
f7857f35
AK		 473#define FOP2E(op, dst, src) \
474 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
475
476#define FASTOP2(op) \
477 FOP_START(op) \
478 FOP2E(op##b, al, bl) \
479 FOP2E(op##w, ax, bx) \
480 FOP2E(op##l, eax, ebx) \
481 ON64(FOP2E(op##q, rax, rbx)) \
482 FOP_END
483
11c363ba
AK		 484/* 2 operand, word only */
485#define FASTOP2W(op) \
486 FOP_START(op) \
487 FOPNOP() \
488 FOP2E(op##w, ax, bx) \
489 FOP2E(op##l, eax, ebx) \
490 ON64(FOP2E(op##q, rax, rbx)) \
491 FOP_END
492
007a3b54
AK		 493/* 2 operand, src is CL */
494#define FASTOP2CL(op) \
495 FOP_START(op) \
496 FOP2E(op##b, al, cl) \
497 FOP2E(op##w, ax, cl) \
498 FOP2E(op##l, eax, cl) \
499 ON64(FOP2E(op##q, rax, cl)) \
500 FOP_END
501
0bdea068
AK		 502#define FOP3E(op, dst, src, src2) \
503 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
504
505/* 3-operand, word-only, src2=cl */
506#define FASTOP3WCL(op) \
507 FOP_START(op) \
508 FOPNOP() \
509 FOP3E(op##w, ax, bx, cl) \
510 FOP3E(op##l, eax, ebx, cl) \
511 ON64(FOP3E(op##q, rax, rbx, cl)) \
512 FOP_END
513
9ae9feba
AK		 514/* Special case for SETcc - 1 instruction per cc */
515#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
516
517FOP_START(setcc)
518FOP_SETCC(seto)
519FOP_SETCC(setno)
520FOP_SETCC(setc)
521FOP_SETCC(setnc)
522FOP_SETCC(setz)
523FOP_SETCC(setnz)
524FOP_SETCC(setbe)
525FOP_SETCC(setnbe)
526FOP_SETCC(sets)
527FOP_SETCC(setns)
528FOP_SETCC(setp)
529FOP_SETCC(setnp)
530FOP_SETCC(setl)
531FOP_SETCC(setnl)
532FOP_SETCC(setle)
533FOP_SETCC(setnle)
534FOP_END;
535
e8f2b1d6 536#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 537 do { \
538 unsigned long _tmp; \
dd856efa
AK		 539 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
540 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 541 \
542 __asm__ __volatile__ ( \
543 _PRE_EFLAGS("0", "5", "1") \
544 "1: \n\t" \
545 _op _suffix " %6; " \
546 "2: \n\t" \
547 _POST_EFLAGS("0", "5", "1") \
548 ".pushsection .fixup,\"ax\" \n\t" \
549 "3: movb $1, %4 \n\t" \
550 "jmp 2b \n\t" \
551 ".popsection \n\t" \
552 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 553 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
554 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 555 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 556 } while (0)
557
3f9f53b0 558/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 559#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 560 do { \
e8f2b1d6 561 switch((ctxt)->src.bytes) { \
7295261c 562 case 1: \
e8f2b1d6 563 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 564 break; \
565 case 2: \
e8f2b1d6 566 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 567 break; \
568 case 4: \
e8f2b1d6 569 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 570 break; \
571 case 8: ON64( \
e8f2b1d6 572 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 573 break; \
574 } \
575 } while (0)
576
8a76d7f2
JR		 577static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
578 enum x86_intercept intercept,
579 enum x86_intercept_stage stage)
580{
581 struct x86_instruction_info info = {
582 .intercept = intercept,
9dac77fa
AK		 583 .rep_prefix = ctxt->rep_prefix,
584 .modrm_mod = ctxt->modrm_mod,
585 .modrm_reg = ctxt->modrm_reg,
586 .modrm_rm = ctxt->modrm_rm,
587 .src_val = ctxt->src.val64,
588 .src_bytes = ctxt->src.bytes,
589 .dst_bytes = ctxt->dst.bytes,
590 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 591 .next_rip = ctxt->eip,
592 };
593
2953538e 594 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 595}
596
f47cfa31
AK		 597static void assign_masked(ulong *dest, ulong src, ulong mask)
598{
599 *dest = (*dest & ~mask) | (src & mask);
600}
601
9dac77fa 602static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 603{
9dac77fa 604 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 605}
606
f47cfa31
AK		 607static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
608{
609 u16 sel;
610 struct desc_struct ss;
611
612 if (ctxt->mode == X86EMUL_MODE_PROT64)
613 return ~0UL;
614 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
615 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
616}
617
612e89f0
AK		 618static int stack_size(struct x86_emulate_ctxt *ctxt)
619{
620 return (__fls(stack_mask(ctxt)) + 1) >> 3;
621}
622
6aa8b732 623/* Access/update address held in a register, based on addressing mode. */
e4706772 624static inline unsigned long
9dac77fa 625address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 626{
9dac77fa 627 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 628 return reg;
629 else
9dac77fa 630 return reg & ad_mask(ctxt);
e4706772
HH		 631}
632
633static inline unsigned long
9dac77fa 634register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 635{
9dac77fa 636 return address_mask(ctxt, reg);
e4706772
HH		 637}
638
5ad105e5
AK		 639static void masked_increment(ulong *reg, ulong mask, int inc)
640{
641 assign_masked(reg, *reg + inc, mask);
642}
643
7a957275 644static inline void
9dac77fa 645register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 646{
5ad105e5
AK		 647 ulong mask;
648
9dac77fa 649 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 650 mask = ~0UL;
7a957275 651 else
5ad105e5
AK		 652 mask = ad_mask(ctxt);
653 masked_increment(reg, mask, inc);
654}
655
656static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
657{
dd856efa 658 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 659}
6aa8b732 660
9dac77fa 661static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 662{
9dac77fa 663 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 664}
098c937b 665
56697687
AK		 666static u32 desc_limit_scaled(struct desc_struct *desc)
667{
668 u32 limit = get_desc_limit(desc);
669
670 return desc->g ? (limit << 12) | 0xfff : limit;
671}
672
9dac77fa 673static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 674{
9dac77fa
AK		 675 ctxt->has_seg_override = true;
676 ctxt->seg_override = seg;
7a5b56df
AK		 677}
678
7b105ca2 679static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 680{
681 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
682 return 0;
683
7b105ca2 684 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 685}
686
9dac77fa 687static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 688{
9dac77fa 689 if (!ctxt->has_seg_override)
7a5b56df
AK		 690 return 0;
691
9dac77fa 692 return ctxt->seg_override;
7a5b56df
AK		 693}
694
35d3d4a1
AK		 695static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
696 u32 error, bool valid)
54b8486f 697{
da9cb575
AK		 698 ctxt->exception.vector = vec;
699 ctxt->exception.error_code = error;
700 ctxt->exception.error_code_valid = valid;
35d3d4a1 701 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 702}
703
3b88e41a
JR		 704static int emulate_db(struct x86_emulate_ctxt *ctxt)
705{
706 return emulate_exception(ctxt, DB_VECTOR, 0, false);
707}
708
35d3d4a1 709static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 710{
35d3d4a1 711 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 712}
713
618ff15d
AK		 714static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
715{
716 return emulate_exception(ctxt, SS_VECTOR, err, true);
717}
718
35d3d4a1 719static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 720{
35d3d4a1 721 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 722}
723
35d3d4a1 724static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 725{
35d3d4a1 726 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 727}
728
34d1f490
AK		 729static int emulate_de(struct x86_emulate_ctxt *ctxt)
730{
35d3d4a1 731 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 732}
733
1253791d
AK		 734static int emulate_nm(struct x86_emulate_ctxt *ctxt)
735{
736 return emulate_exception(ctxt, NM_VECTOR, 0, false);
737}
738
1aa36616
AK		 739static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
740{
741 u16 selector;
742 struct desc_struct desc;
743
744 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
745 return selector;
746}
747
748static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
749 unsigned seg)
750{
751 u16 dummy;
752 u32 base3;
753 struct desc_struct desc;
754
755 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
756 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
757}
758
1c11b376
AK		 759/*
760 * x86 defines three classes of vector instructions: explicitly
761 * aligned, explicitly unaligned, and the rest, which change behaviour
762 * depending on whether they're AVX encoded or not.
763 *
764 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
765 * subject to the same check.
766 */
767static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
768{
769 if (likely(size < 16))
770 return false;
771
772 if (ctxt->d & Aligned)
773 return true;
774 else if (ctxt->d & Unaligned)
775 return false;
776 else if (ctxt->d & Avx)
777 return false;
778 else
779 return true;
780}
781
3d9b938e 782static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 783 struct segmented_address addr,
3d9b938e 784 unsigned size, bool write, bool fetch,
52fd8b44
AK		 785 ulong *linear)
786{
618ff15d
AK		 787 struct desc_struct desc;
788 bool usable;
52fd8b44 789 ulong la;
618ff15d 790 u32 lim;
1aa36616 791 u16 sel;
3a78a4f4 792 unsigned cpl;
52fd8b44 793
7b105ca2 794 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 795 switch (ctxt->mode) {
618ff15d
AK		 796 case X86EMUL_MODE_PROT64:
797 if (((signed long)la << 16) >> 16 != la)
798 return emulate_gp(ctxt, 0);
799 break;
800 default:
1aa36616
AK		 801 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
802 addr.seg);
618ff15d
AK		 803 if (!usable)
804 goto bad;
58b7825b
GN		 805 /* code segment in protected mode or read-only data segment */
806 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
807 || !(desc.type & 2)) && write)
618ff15d
AK		 808 goto bad;
809 /* unreadable code segment */
3d9b938e 810 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 811 goto bad;
812 lim = desc_limit_scaled(&desc);
813 if ((desc.type & 8) || !(desc.type & 4)) {
814 /* expand-up segment */
815 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
816 goto bad;
817 } else {
fc058680 818 /* expand-down segment */
618ff15d
AK		 819 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
820 goto bad;
821 lim = desc.d ? 0xffffffff : 0xffff;
822 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
823 goto bad;
824 }
717746e3 825 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 826 if (!(desc.type & 8)) {
827 /* data segment */
828 if (cpl > desc.dpl)
829 goto bad;
830 } else if ((desc.type & 8) && !(desc.type & 4)) {
831 /* nonconforming code segment */
832 if (cpl != desc.dpl)
833 goto bad;
834 } else if ((desc.type & 8) && (desc.type & 4)) {
835 /* conforming code segment */
836 if (cpl < desc.dpl)
837 goto bad;
838 }
839 break;
840 }
9dac77fa 841 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 842 la &= (u32)-1;
1c11b376
AK		 843 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
844 return emulate_gp(ctxt, 0);
52fd8b44
AK		 845 *linear = la;
846 return X86EMUL_CONTINUE;
618ff15d
AK		 847bad:
848 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 849 return emulate_ss(ctxt, sel);
618ff15d 850 else
0afbe2f8 851 return emulate_gp(ctxt, sel);
52fd8b44
AK		 852}
853
3d9b938e
NE		 854static int linearize(struct x86_emulate_ctxt *ctxt,
855 struct segmented_address addr,
856 unsigned size, bool write,
857 ulong *linear)
858{
859 return __linearize(ctxt, addr, size, write, false, linear);
860}
861
862
3ca3ac4d
AK		 863static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
864 struct segmented_address addr,
865 void *data,
866 unsigned size)
867{
9fa088f4
AK		 868 int rc;
869 ulong linear;
870
83b8795a 871 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 872 if (rc != X86EMUL_CONTINUE)
873 return rc;
0f65dd70 874 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 875}
876
807941b1
TY		 877/*
878 * Fetch the next byte of the instruction being emulated which is pointed to
879 * by ctxt->_eip, then increment ctxt->_eip.
880 *
881 * Also prefetch the remaining bytes of the instruction without crossing page
882 * boundary if they are not in fetch_cache yet.
883 */
884static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 885{
9dac77fa 886 struct fetch_cache *fc = &ctxt->fetch;
62266869 887 int rc;
2fb53ad8 888 int size, cur_size;
62266869 889
807941b1 890 if (ctxt->_eip == fc->end) {
3d9b938e 891 unsigned long linear;
807941b1
TY		 892 struct segmented_address addr = { .seg = VCPU_SREG_CS,
893 .ea = ctxt->_eip };
2fb53ad8 894 cur_size = fc->end - fc->start;
807941b1
TY		 895 size = min(15UL - cur_size,
896 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 897 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 898 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 899 return rc;
ef5d75cc
TY		 900 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
901 size, &ctxt->exception);
7d88bb48 902 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 903 return rc;
2fb53ad8 904 fc->end += size;
62266869 905 }
807941b1
TY		 906 *dest = fc->data[ctxt->_eip - fc->start];
907 ctxt->_eip++;
3e2815e9 908 return X86EMUL_CONTINUE;
62266869
AK		 909}
910
911static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 912 void *dest, unsigned size)
62266869 913{
3e2815e9 914 int rc;
62266869 915
eb3c79e6 916 /* x86 instructions are limited to 15 bytes. */
7d88bb48 917 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 918 return X86EMUL_UNHANDLEABLE;
62266869 919 while (size--) {
807941b1 920 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 921 if (rc != X86EMUL_CONTINUE)
62266869
AK		 922 return rc;
923 }
3e2815e9 924 return X86EMUL_CONTINUE;
62266869
AK		 925}
926
67cbc90d 927/* Fetch next part of the instruction being emulated. */
e85a1085 928#define insn_fetch(_type, _ctxt) \
67cbc90d 929({ unsigned long _x; \
e85a1085 930 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 931 if (rc != X86EMUL_CONTINUE) \
932 goto done; \
67cbc90d
TY		 933 (_type)_x; \
934})
935
807941b1
TY		 936#define insn_fetch_arr(_arr, _size, _ctxt) \
937({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 938 if (rc != X86EMUL_CONTINUE) \
939 goto done; \
67cbc90d
TY		 940})
941
1e3c5cb0
RR		 942/*
943 * Given the 'reg' portion of a ModRM byte, and a register block, return a
944 * pointer into the block that addresses the relevant register.
945 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
946 */
dd856efa 947static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 948 int highbyte_regs)
6aa8b732
AK		 949{
950 void *p;
951
6aa8b732 952 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 953 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
954 else
955 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 956 return p;
957}
958
959static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 960 struct segmented_address addr,
6aa8b732
AK		 961 u16 *size, unsigned long *address, int op_bytes)
962{
963 int rc;
964
965 if (op_bytes == 2)
966 op_bytes = 3;
967 *address = 0;
3ca3ac4d 968 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 969 if (rc != X86EMUL_CONTINUE)
6aa8b732 970 return rc;
30b31ab6 971 addr.ea += 2;
3ca3ac4d 972 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 973 return rc;
974}
975
34b77652
AK		 976FASTOP2(add);
977FASTOP2(or);
978FASTOP2(adc);
979FASTOP2(sbb);
980FASTOP2(and);
981FASTOP2(sub);
982FASTOP2(xor);
983FASTOP2(cmp);
984FASTOP2(test);
985
986FASTOP3WCL(shld);
987FASTOP3WCL(shrd);
988
989FASTOP2W(imul);
990
991FASTOP1(not);
992FASTOP1(neg);
993FASTOP1(inc);
994FASTOP1(dec);
995
996FASTOP2CL(rol);
997FASTOP2CL(ror);
998FASTOP2CL(rcl);
999FASTOP2CL(rcr);
1000FASTOP2CL(shl);
1001FASTOP2CL(shr);
1002FASTOP2CL(sar);
1003
1004FASTOP2W(bsf);
1005FASTOP2W(bsr);
1006FASTOP2W(bt);
1007FASTOP2W(bts);
1008FASTOP2W(btr);
1009FASTOP2W(btc);
1010
9ae9feba 1011static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1012{
9ae9feba
AK		 1013 u8 rc;
1014 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1015
9ae9feba 1016 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1017 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1018 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1019 return rc;
bbe9abbd
NK		 1020}
1021
91ff3cb4
AK		 1022static void fetch_register_operand(struct operand *op)
1023{
1024 switch (op->bytes) {
1025 case 1:
1026 op->val = *(u8 *)op->addr.reg;
1027 break;
1028 case 2:
1029 op->val = *(u16 *)op->addr.reg;
1030 break;
1031 case 4:
1032 op->val = *(u32 *)op->addr.reg;
1033 break;
1034 case 8:
1035 op->val = *(u64 *)op->addr.reg;
1036 break;
1037 }
1038}
1039
1253791d
AK		 1040static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1041{
1042 ctxt->ops->get_fpu(ctxt);
1043 switch (reg) {
89a87c67
MK		 1044 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1045 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1046 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1047 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1048 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1049 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1050 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1051 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1052#ifdef CONFIG_X86_64
89a87c67
MK		 1053 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1054 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1055 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1056 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1057 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1058 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1059 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1060 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1061#endif
1062 default: BUG();
1063 }
1064 ctxt->ops->put_fpu(ctxt);
1065}
1066
1067static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1068 int reg)
1069{
1070 ctxt->ops->get_fpu(ctxt);
1071 switch (reg) {
89a87c67
MK		 1072 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1073 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1074 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1075 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1076 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1077 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1078 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1079 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1080#ifdef CONFIG_X86_64
89a87c67
MK		 1081 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1082 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1083 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1084 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1085 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1086 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1087 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1088 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1089#endif
1090 default: BUG();
1091 }
1092 ctxt->ops->put_fpu(ctxt);
1093}
1094
cbe2c9d3
AK		 1095static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1096{
1097 ctxt->ops->get_fpu(ctxt);
1098 switch (reg) {
1099 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1100 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1101 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1102 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1103 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1104 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1105 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1106 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1107 default: BUG();
1108 }
1109 ctxt->ops->put_fpu(ctxt);
1110}
1111
1112static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1113{
1114 ctxt->ops->get_fpu(ctxt);
1115 switch (reg) {
1116 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1117 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1118 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1119 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1120 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1121 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1122 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1123 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1124 default: BUG();
1125 }
1126 ctxt->ops->put_fpu(ctxt);
1127}
1128
045a282c
GN		 1129static int em_fninit(struct x86_emulate_ctxt *ctxt)
1130{
1131 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1132 return emulate_nm(ctxt);
1133
1134 ctxt->ops->get_fpu(ctxt);
1135 asm volatile("fninit");
1136 ctxt->ops->put_fpu(ctxt);
1137 return X86EMUL_CONTINUE;
1138}
1139
1140static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1141{
1142 u16 fcw;
1143
1144 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1145 return emulate_nm(ctxt);
1146
1147 ctxt->ops->get_fpu(ctxt);
1148 asm volatile("fnstcw %0": "+m"(fcw));
1149 ctxt->ops->put_fpu(ctxt);
1150
1151 /* force 2 byte destination */
1152 ctxt->dst.bytes = 2;
1153 ctxt->dst.val = fcw;
1154
1155 return X86EMUL_CONTINUE;
1156}
1157
1158static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1159{
1160 u16 fsw;
1161
1162 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1163 return emulate_nm(ctxt);
1164
1165 ctxt->ops->get_fpu(ctxt);
1166 asm volatile("fnstsw %0": "+m"(fsw));
1167 ctxt->ops->put_fpu(ctxt);
1168
1169 /* force 2 byte destination */
1170 ctxt->dst.bytes = 2;
1171 ctxt->dst.val = fsw;
1172
1173 return X86EMUL_CONTINUE;
1174}
1175
1253791d 1176static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1177 struct operand *op)
3c118e24 1178{
9dac77fa
AK		 1179 unsigned reg = ctxt->modrm_reg;
1180 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1181
9dac77fa
AK		 1182 if (!(ctxt->d & ModRM))
1183 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1184
9dac77fa 1185 if (ctxt->d & Sse) {
1253791d
AK		 1186 op->type = OP_XMM;
1187 op->bytes = 16;
1188 op->addr.xmm = reg;
1189 read_sse_reg(ctxt, &op->vec_val, reg);
1190 return;
1191 }
cbe2c9d3
AK		 1192 if (ctxt->d & Mmx) {
1193 reg &= 7;
1194 op->type = OP_MM;
1195 op->bytes = 8;
1196 op->addr.mm = reg;
1197 return;
1198 }
1253791d 1199
3c118e24 1200 op->type = OP_REG;
2adb5ad9 1201 if (ctxt->d & ByteOp) {
dd856efa 1202 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1203 op->bytes = 1;
1204 } else {
dd856efa 1205 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1206 op->bytes = ctxt->op_bytes;
3c118e24 1207 }
91ff3cb4 1208 fetch_register_operand(op);
3c118e24
AK		 1209 op->orig_val = op->val;
1210}
1211
a6e3407b
AK		 1212static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1213{
1214 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1215 ctxt->modrm_seg = VCPU_SREG_SS;
1216}
1217
1c73ef66 1218static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1219 struct operand *op)
1c73ef66 1220{
1c73ef66 1221 u8 sib;
f5b4edcd 1222 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1223 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1224 ulong modrm_ea = 0;
1c73ef66 1225
9dac77fa
AK		 1226 if (ctxt->rex_prefix) {
1227 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1228 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1229 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1230 }
1231
9dac77fa
AK		 1232 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1233 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1234 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1235 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1236
9dac77fa 1237 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1238 op->type = OP_REG;
9dac77fa 1239 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1240 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1241 if (ctxt->d & Sse) {
1253791d
AK		 1242 op->type = OP_XMM;
1243 op->bytes = 16;
9dac77fa
AK		 1244 op->addr.xmm = ctxt->modrm_rm;
1245 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1246 return rc;
1247 }
cbe2c9d3
AK		 1248 if (ctxt->d & Mmx) {
1249 op->type = OP_MM;
1250 op->bytes = 8;
1251 op->addr.xmm = ctxt->modrm_rm & 7;
1252 return rc;
1253 }
2dbd0dd7 1254 fetch_register_operand(op);
1c73ef66
AK		 1255 return rc;
1256 }
1257
2dbd0dd7
AK		 1258 op->type = OP_MEM;
1259
9dac77fa 1260 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1261 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1262 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1263 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1264 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1265
1266 /* 16-bit ModR/M decode. */
9dac77fa 1267 switch (ctxt->modrm_mod) {
1c73ef66 1268 case 0:
9dac77fa 1269 if (ctxt->modrm_rm == 6)
e85a1085 1270 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1271 break;
1272 case 1:
e85a1085 1273 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1274 break;
1275 case 2:
e85a1085 1276 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1277 break;
1278 }
9dac77fa 1279 switch (ctxt->modrm_rm) {
1c73ef66 1280 case 0:
2dbd0dd7 1281 modrm_ea += bx + si;
1c73ef66
AK		 1282 break;
1283 case 1:
2dbd0dd7 1284 modrm_ea += bx + di;
1c73ef66
AK		 1285 break;
1286 case 2:
2dbd0dd7 1287 modrm_ea += bp + si;
1c73ef66
AK		 1288 break;
1289 case 3:
2dbd0dd7 1290 modrm_ea += bp + di;
1c73ef66
AK		 1291 break;
1292 case 4:
2dbd0dd7 1293 modrm_ea += si;
1c73ef66
AK		 1294 break;
1295 case 5:
2dbd0dd7 1296 modrm_ea += di;
1c73ef66
AK		 1297 break;
1298 case 6:
9dac77fa 1299 if (ctxt->modrm_mod != 0)
2dbd0dd7 1300 modrm_ea += bp;
1c73ef66
AK		 1301 break;
1302 case 7:
2dbd0dd7 1303 modrm_ea += bx;
1c73ef66
AK		 1304 break;
1305 }
9dac77fa
AK		 1306 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1307 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1308 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1309 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1310 } else {
1311 /* 32/64-bit ModR/M decode. */
9dac77fa 1312 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1313 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1314 index_reg |= (sib >> 3) & 7;
1315 base_reg |= sib & 7;
1316 scale = sib >> 6;
1317
9dac77fa 1318 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1319 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1320 else {
dd856efa 1321 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1322 adjust_modrm_seg(ctxt, base_reg);
1323 }
dc71d0f1 1324 if (index_reg != 4)
dd856efa 1325 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1326 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1327 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1328 ctxt->rip_relative = 1;
a6e3407b
AK		 1329 } else {
1330 base_reg = ctxt->modrm_rm;
dd856efa 1331 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1332 adjust_modrm_seg(ctxt, base_reg);
1333 }
9dac77fa 1334 switch (ctxt->modrm_mod) {
1c73ef66 1335 case 0:
9dac77fa 1336 if (ctxt->modrm_rm == 5)
e85a1085 1337 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1338 break;
1339 case 1:
e85a1085 1340 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1341 break;
1342 case 2:
e85a1085 1343 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1344 break;
1345 }
1346 }
90de84f5 1347 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1348done:
1349 return rc;
1350}
1351
1352static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1353 struct operand *op)
1c73ef66 1354{
3e2815e9 1355 int rc = X86EMUL_CONTINUE;
1c73ef66 1356
2dbd0dd7 1357 op->type = OP_MEM;
9dac77fa 1358 switch (ctxt->ad_bytes) {
1c73ef66 1359 case 2:
e85a1085 1360 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1361 break;
1362 case 4:
e85a1085 1363 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1364 break;
1365 case 8:
e85a1085 1366 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1367 break;
1368 }
1369done:
1370 return rc;
1371}
1372
9dac77fa 1373static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1374{
7129eeca 1375 long sv = 0, mask;
35c843c4 1376
9dac77fa
AK		 1377 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1378 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1379
9dac77fa
AK		 1380 if (ctxt->src.bytes == 2)
1381 sv = (s16)ctxt->src.val & (s16)mask;
1382 else if (ctxt->src.bytes == 4)
1383 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1384
9dac77fa 1385 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1386 }
ba7ff2b7
WY		 1387
1388 /* only subword offset */
9dac77fa 1389 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1390}
1391
dde7e6d1 1392static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1393 unsigned long addr, void *dest, unsigned size)
6aa8b732 1394{
dde7e6d1 1395 int rc;
9dac77fa 1396 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1397
f23b070e
XG		 1398 if (mc->pos < mc->end)
1399 goto read_cached;
6aa8b732 1400
f23b070e
XG		 1401 WARN_ON((mc->end + size) >= sizeof(mc->data));
1402
1403 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1404 &ctxt->exception);
1405 if (rc != X86EMUL_CONTINUE)
1406 return rc;
1407
1408 mc->end += size;
1409
1410read_cached:
1411 memcpy(dest, mc->data + mc->pos, size);
1412 mc->pos += size;
dde7e6d1
AK		 1413 return X86EMUL_CONTINUE;
1414}
6aa8b732 1415
3ca3ac4d
AK		 1416static int segmented_read(struct x86_emulate_ctxt *ctxt,
1417 struct segmented_address addr,
1418 void *data,
1419 unsigned size)
1420{
9fa088f4
AK		 1421 int rc;
1422 ulong linear;
1423
83b8795a 1424 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1425 if (rc != X86EMUL_CONTINUE)
1426 return rc;
7b105ca2 1427 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1428}
1429
1430static int segmented_write(struct x86_emulate_ctxt *ctxt,
1431 struct segmented_address addr,
1432 const void *data,
1433 unsigned size)
1434{
9fa088f4
AK		 1435 int rc;
1436 ulong linear;
1437
83b8795a 1438 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1439 if (rc != X86EMUL_CONTINUE)
1440 return rc;
0f65dd70
AK		 1441 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1442 &ctxt->exception);
3ca3ac4d
AK		 1443}
1444
1445static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1446 struct segmented_address addr,
1447 const void *orig_data, const void *data,
1448 unsigned size)
1449{
9fa088f4
AK		 1450 int rc;
1451 ulong linear;
1452
83b8795a 1453 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1454 if (rc != X86EMUL_CONTINUE)
1455 return rc;
0f65dd70
AK		 1456 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1457 size, &ctxt->exception);
3ca3ac4d
AK		 1458}
1459
dde7e6d1 1460static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1461 unsigned int size, unsigned short port,
1462 void *dest)
1463{
9dac77fa 1464 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1465
dde7e6d1 1466 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1467 unsigned int in_page, n;
9dac77fa 1468 unsigned int count = ctxt->rep_prefix ?
dd856efa 1469 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1470 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1471 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1472 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1473 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1474 count);
1475 if (n == 0)
1476 n = 1;
1477 rc->pos = rc->end = 0;
7b105ca2 1478 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1479 return 0;
1480 rc->end = n * size;
6aa8b732
AK		 1481 }
1482
b3356bf0
GN		 1483 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1484 ctxt->dst.data = rc->data + rc->pos;
1485 ctxt->dst.type = OP_MEM_STR;
1486 ctxt->dst.count = (rc->end - rc->pos) / size;
1487 rc->pos = rc->end;
1488 } else {
1489 memcpy(dest, rc->data + rc->pos, size);
1490 rc->pos += size;
1491 }
dde7e6d1
AK		 1492 return 1;
1493}
6aa8b732 1494
7f3d35fd
KW		 1495static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1496 u16 index, struct desc_struct *desc)
1497{
1498 struct desc_ptr dt;
1499 ulong addr;
1500
1501 ctxt->ops->get_idt(ctxt, &dt);
1502
1503 if (dt.size < index * 8 + 7)
1504 return emulate_gp(ctxt, index << 3 | 0x2);
1505
1506 addr = dt.address + index * 8;
1507 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1508 &ctxt->exception);
1509}
1510
dde7e6d1 1511static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1512 u16 selector, struct desc_ptr *dt)
1513{
0225fb50 1514 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1515
dde7e6d1
AK		 1516 if (selector & 1 << 2) {
1517 struct desc_struct desc;
1aa36616
AK		 1518 u16 sel;
1519
dde7e6d1 1520 memset (dt, 0, sizeof *dt);
1aa36616 1521 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1522 return;
e09d082c 1523
dde7e6d1
AK		 1524 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1525 dt->address = get_desc_base(&desc);
1526 } else
4bff1e86 1527 ops->get_gdt(ctxt, dt);
dde7e6d1 1528}
120df890 1529
dde7e6d1
AK		 1530/* allowed just for 8 bytes segments */
1531static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1532 u16 selector, struct desc_struct *desc,
1533 ulong *desc_addr_p)
dde7e6d1
AK		 1534{
1535 struct desc_ptr dt;
1536 u16 index = selector >> 3;
dde7e6d1 1537 ulong addr;
120df890 1538
7b105ca2 1539 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1540
35d3d4a1
AK		 1541 if (dt.size < index * 8 + 7)
1542 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1543
e919464b 1544 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1545 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1546 &ctxt->exception);
dde7e6d1 1547}
ef65c889 1548
dde7e6d1
AK		 1549/* allowed just for 8 bytes segments */
1550static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1551 u16 selector, struct desc_struct *desc)
1552{
1553 struct desc_ptr dt;
1554 u16 index = selector >> 3;
dde7e6d1 1555 ulong addr;
6aa8b732 1556
7b105ca2 1557 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1558
35d3d4a1
AK		 1559 if (dt.size < index * 8 + 7)
1560 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1561
dde7e6d1 1562 addr = dt.address + index * 8;
7b105ca2
TY		 1563 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1564 &ctxt->exception);
dde7e6d1 1565}
c7e75a3d 1566
5601d05b 1567/* Does not support long mode */
dde7e6d1 1568static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1569 u16 selector, int seg)
1570{
869be99c 1571 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1572 u8 dpl, rpl, cpl;
1573 unsigned err_vec = GP_VECTOR;
1574 u32 err_code = 0;
1575 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1576 ulong desc_addr;
dde7e6d1 1577 int ret;
03ebebeb 1578 u16 dummy;
69f55cb1 1579
dde7e6d1 1580 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1581
f8da94e9
KW		 1582 if (ctxt->mode == X86EMUL_MODE_REAL) {
1583 /* set real mode segment descriptor (keep limit etc. for
1584 * unreal mode) */
03ebebeb 1585 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1586 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1587 goto load;
f8da94e9
KW		 1588 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1589 /* VM86 needs a clean new segment descriptor */
1590 set_desc_base(&seg_desc, selector << 4);
1591 set_desc_limit(&seg_desc, 0xffff);
1592 seg_desc.type = 3;
1593 seg_desc.p = 1;
1594 seg_desc.s = 1;
1595 seg_desc.dpl = 3;
1596 goto load;
dde7e6d1
AK		 1597 }
1598
79d5b4c3
AK		 1599 rpl = selector & 3;
1600 cpl = ctxt->ops->cpl(ctxt);
1601
1602 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1603 if ((seg == VCPU_SREG_CS
1604 || (seg == VCPU_SREG_SS
1605 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1606 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1607 && null_selector)
1608 goto exception;
1609
1610 /* TR should be in GDT only */
1611 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1612 goto exception;
1613
1614 if (null_selector) /* for NULL selector skip all following checks */
1615 goto load;
1616
e919464b 1617 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1618 if (ret != X86EMUL_CONTINUE)
1619 return ret;
1620
1621 err_code = selector & 0xfffc;
1622 err_vec = GP_VECTOR;
1623
fc058680 1624 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1625 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1626 goto exception;
1627
1628 if (!seg_desc.p) {
1629 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1630 goto exception;
1631 }
1632
dde7e6d1 1633 dpl = seg_desc.dpl;
dde7e6d1
AK		 1634
1635 switch (seg) {
1636 case VCPU_SREG_SS:
1637 /*
1638 * segment is not a writable data segment or segment
1639 * selector's RPL != CPL or segment selector's RPL != CPL
1640 */
1641 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1642 goto exception;
6aa8b732 1643 break;
dde7e6d1
AK		 1644 case VCPU_SREG_CS:
1645 if (!(seg_desc.type & 8))
1646 goto exception;
1647
1648 if (seg_desc.type & 4) {
1649 /* conforming */
1650 if (dpl > cpl)
1651 goto exception;
1652 } else {
1653 /* nonconforming */
1654 if (rpl > cpl || dpl != cpl)
1655 goto exception;
1656 }
1657 /* CS(RPL) <- CPL */
1658 selector = (selector & 0xfffc) | cpl;
6aa8b732 1659 break;
dde7e6d1
AK		 1660 case VCPU_SREG_TR:
1661 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1662 goto exception;
869be99c
AK		 1663 old_desc = seg_desc;
1664 seg_desc.type |= 2; /* busy */
1665 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1666 sizeof(seg_desc), &ctxt->exception);
1667 if (ret != X86EMUL_CONTINUE)
1668 return ret;
dde7e6d1
AK		 1669 break;
1670 case VCPU_SREG_LDTR:
1671 if (seg_desc.s || seg_desc.type != 2)
1672 goto exception;
1673 break;
1674 default: /* DS, ES, FS, or GS */
4e62417b 1675 /*
dde7e6d1
AK		 1676 * segment is not a data or readable code segment or
1677 * ((segment is a data or nonconforming code segment)
1678 * and (both RPL and CPL > DPL))
4e62417b 1679 */
dde7e6d1
AK		 1680 if ((seg_desc.type & 0xa) == 0x8 ||
1681 (((seg_desc.type & 0xc) != 0xc) &&
1682 (rpl > dpl && cpl > dpl)))
1683 goto exception;
6aa8b732 1684 break;
dde7e6d1
AK		 1685 }
1686
1687 if (seg_desc.s) {
1688 /* mark segment as accessed */
1689 seg_desc.type |= 1;
7b105ca2 1690 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1691 if (ret != X86EMUL_CONTINUE)
1692 return ret;
1693 }
1694load:
7b105ca2 1695 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1696 return X86EMUL_CONTINUE;
1697exception:
1698 emulate_exception(ctxt, err_vec, err_code, true);
1699 return X86EMUL_PROPAGATE_FAULT;
1700}
1701
31be40b3
WY		 1702static void write_register_operand(struct operand *op)
1703{
1704 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1705 switch (op->bytes) {
1706 case 1:
1707 *(u8 *)op->addr.reg = (u8)op->val;
1708 break;
1709 case 2:
1710 *(u16 *)op->addr.reg = (u16)op->val;
1711 break;
1712 case 4:
1713 *op->addr.reg = (u32)op->val;
1714 break; /* 64b: zero-extend */
1715 case 8:
1716 *op->addr.reg = op->val;
1717 break;
1718 }
1719}
1720
adddcecf 1721static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1722{
1723 int rc;
dde7e6d1 1724
b6744dc3
AK		 1725 if (ctxt->d & NoWrite)
1726 return X86EMUL_CONTINUE;
1727
9dac77fa 1728 switch (ctxt->dst.type) {
dde7e6d1 1729 case OP_REG:
9dac77fa 1730 write_register_operand(&ctxt->dst);
6aa8b732 1731 break;
dde7e6d1 1732 case OP_MEM:
9dac77fa 1733 if (ctxt->lock_prefix)
3ca3ac4d 1734 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1735 ctxt->dst.addr.mem,
1736 &ctxt->dst.orig_val,
1737 &ctxt->dst.val,
1738 ctxt->dst.bytes);
341de7e3 1739 else
3ca3ac4d 1740 rc = segmented_write(ctxt,
9dac77fa
AK		 1741 ctxt->dst.addr.mem,
1742 &ctxt->dst.val,
1743 ctxt->dst.bytes);
dde7e6d1
AK		 1744 if (rc != X86EMUL_CONTINUE)
1745 return rc;
a682e354 1746 break;
b3356bf0
GN		 1747 case OP_MEM_STR:
1748 rc = segmented_write(ctxt,
1749 ctxt->dst.addr.mem,
1750 ctxt->dst.data,
1751 ctxt->dst.bytes * ctxt->dst.count);
1752 if (rc != X86EMUL_CONTINUE)
1753 return rc;
1754 break;
1253791d 1755 case OP_XMM:
9dac77fa 1756 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1757 break;
cbe2c9d3
AK		 1758 case OP_MM:
1759 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1760 break;
dde7e6d1
AK		 1761 case OP_NONE:
1762 /* no writeback */
414e6277 1763 break;
dde7e6d1 1764 default:
414e6277 1765 break;
6aa8b732 1766 }
dde7e6d1
AK		 1767 return X86EMUL_CONTINUE;
1768}
6aa8b732 1769
51ddff50 1770static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1771{
4179bb02 1772 struct segmented_address addr;
0dc8d10f 1773
5ad105e5 1774 rsp_increment(ctxt, -bytes);
dd856efa 1775 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1776 addr.seg = VCPU_SREG_SS;
1777
51ddff50
AK		 1778 return segmented_write(ctxt, addr, data, bytes);
1779}
1780
1781static int em_push(struct x86_emulate_ctxt *ctxt)
1782{
4179bb02 1783 /* Disable writeback. */
9dac77fa 1784 ctxt->dst.type = OP_NONE;
51ddff50 1785 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1786}
69f55cb1 1787
dde7e6d1 1788static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1789 void *dest, int len)
1790{
dde7e6d1 1791 int rc;
90de84f5 1792 struct segmented_address addr;
8b4caf66 1793
dd856efa 1794 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1795 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1796 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1797 if (rc != X86EMUL_CONTINUE)
1798 return rc;
1799
5ad105e5 1800 rsp_increment(ctxt, len);
dde7e6d1 1801 return rc;
8b4caf66
LV		 1802}
1803
c54fe504
TY		 1804static int em_pop(struct x86_emulate_ctxt *ctxt)
1805{
9dac77fa 1806 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1807}
1808
dde7e6d1 1809static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1810 void *dest, int len)
9de41573
GN		 1811{
1812 int rc;
dde7e6d1
AK		 1813 unsigned long val, change_mask;
1814 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1815 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1816
3b9be3bf 1817 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1818 if (rc != X86EMUL_CONTINUE)
1819 return rc;
9de41573 1820
dde7e6d1
AK		 1821 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1822 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1823
dde7e6d1
AK		 1824 switch(ctxt->mode) {
1825 case X86EMUL_MODE_PROT64:
1826 case X86EMUL_MODE_PROT32:
1827 case X86EMUL_MODE_PROT16:
1828 if (cpl == 0)
1829 change_mask |= EFLG_IOPL;
1830 if (cpl <= iopl)
1831 change_mask |= EFLG_IF;
1832 break;
1833 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1834 if (iopl < 3)
1835 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1836 change_mask |= EFLG_IF;
1837 break;
1838 default: /* real mode */
1839 change_mask |= (EFLG_IOPL | EFLG_IF);
1840 break;
9de41573 1841 }
dde7e6d1
AK		 1842
1843 *(unsigned long *)dest =
1844 (ctxt->eflags & ~change_mask) | (val & change_mask);
1845
1846 return rc;
9de41573
GN		 1847}
1848
62aaa2f0
TY		 1849static int em_popf(struct x86_emulate_ctxt *ctxt)
1850{
9dac77fa
AK		 1851 ctxt->dst.type = OP_REG;
1852 ctxt->dst.addr.reg = &ctxt->eflags;
1853 ctxt->dst.bytes = ctxt->op_bytes;
1854 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1855}
1856
612e89f0
AK		 1857static int em_enter(struct x86_emulate_ctxt *ctxt)
1858{
1859 int rc;
1860 unsigned frame_size = ctxt->src.val;
1861 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1862 ulong rbp;
612e89f0
AK		 1863
1864 if (nesting_level)
1865 return X86EMUL_UNHANDLEABLE;
1866
dd856efa
AK		 1867 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1868 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1869 if (rc != X86EMUL_CONTINUE)
1870 return rc;
dd856efa 1871 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1872 stack_mask(ctxt));
dd856efa
AK		 1873 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1874 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1875 stack_mask(ctxt));
1876 return X86EMUL_CONTINUE;
1877}
1878
f47cfa31
AK		 1879static int em_leave(struct x86_emulate_ctxt *ctxt)
1880{
dd856efa 1881 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1882 stack_mask(ctxt));
dd856efa 1883 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1884}
1885
1cd196ea 1886static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1887{
1cd196ea
AK		 1888 int seg = ctxt->src2.val;
1889
9dac77fa 1890 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1891
4487b3b4 1892 return em_push(ctxt);
7b262e90
GN		 1893}
1894
1cd196ea 1895static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1896{
1cd196ea 1897 int seg = ctxt->src2.val;
dde7e6d1
AK		 1898 unsigned long selector;
1899 int rc;
38ba30ba 1900
9dac77fa 1901 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1902 if (rc != X86EMUL_CONTINUE)
1903 return rc;
1904
7b105ca2 1905 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1906 return rc;
38ba30ba
GN		 1907}
1908
b96a7fad 1909static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1910{
dd856efa 1911 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1912 int rc = X86EMUL_CONTINUE;
1913 int reg = VCPU_REGS_RAX;
38ba30ba 1914
dde7e6d1
AK		 1915 while (reg <= VCPU_REGS_RDI) {
1916 (reg == VCPU_REGS_RSP) ?
dd856efa 1917 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1918
4487b3b4 1919 rc = em_push(ctxt);
dde7e6d1
AK		 1920 if (rc != X86EMUL_CONTINUE)
1921 return rc;
38ba30ba 1922
dde7e6d1 1923 ++reg;
38ba30ba 1924 }
38ba30ba 1925
dde7e6d1 1926 return rc;
38ba30ba
GN		 1927}
1928
62aaa2f0
TY		 1929static int em_pushf(struct x86_emulate_ctxt *ctxt)
1930{
9dac77fa 1931 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1932 return em_push(ctxt);
1933}
1934
b96a7fad 1935static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1936{
dde7e6d1
AK		 1937 int rc = X86EMUL_CONTINUE;
1938 int reg = VCPU_REGS_RDI;
38ba30ba 1939
dde7e6d1
AK		 1940 while (reg >= VCPU_REGS_RAX) {
1941 if (reg == VCPU_REGS_RSP) {
5ad105e5 1942 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1943 --reg;
1944 }
38ba30ba 1945
dd856efa 1946 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1947 if (rc != X86EMUL_CONTINUE)
1948 break;
1949 --reg;
38ba30ba 1950 }
dde7e6d1 1951 return rc;
38ba30ba
GN		 1952}
1953
dd856efa 1954static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1955{
0225fb50 1956 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1957 int rc;
6e154e56
MG		 1958 struct desc_ptr dt;
1959 gva_t cs_addr;
1960 gva_t eip_addr;
1961 u16 cs, eip;
6e154e56
MG		 1962
1963 /* TODO: Add limit checks */
9dac77fa 1964 ctxt->src.val = ctxt->eflags;
4487b3b4 1965 rc = em_push(ctxt);
5c56e1cf
AK		 1966 if (rc != X86EMUL_CONTINUE)
1967 return rc;
6e154e56
MG		 1968
1969 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1970
9dac77fa 1971 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1972 rc = em_push(ctxt);
5c56e1cf
AK		 1973 if (rc != X86EMUL_CONTINUE)
1974 return rc;
6e154e56 1975
9dac77fa 1976 ctxt->src.val = ctxt->_eip;
4487b3b4 1977 rc = em_push(ctxt);
5c56e1cf
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 return rc;
1980
4bff1e86 1981 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1982
1983 eip_addr = dt.address + (irq << 2);
1984 cs_addr = dt.address + (irq << 2) + 2;
1985
0f65dd70 1986 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1987 if (rc != X86EMUL_CONTINUE)
1988 return rc;
1989
0f65dd70 1990 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1991 if (rc != X86EMUL_CONTINUE)
1992 return rc;
1993
7b105ca2 1994 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1995 if (rc != X86EMUL_CONTINUE)
1996 return rc;
1997
9dac77fa 1998 ctxt->_eip = eip;
6e154e56
MG		 1999
2000 return rc;
2001}
2002
dd856efa
AK		 2003int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2004{
2005 int rc;
2006
2007 invalidate_registers(ctxt);
2008 rc = __emulate_int_real(ctxt, irq);
2009 if (rc == X86EMUL_CONTINUE)
2010 writeback_registers(ctxt);
2011 return rc;
2012}
2013
7b105ca2 2014static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2015{
2016 switch(ctxt->mode) {
2017 case X86EMUL_MODE_REAL:
dd856efa 2018 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2019 case X86EMUL_MODE_VM86:
2020 case X86EMUL_MODE_PROT16:
2021 case X86EMUL_MODE_PROT32:
2022 case X86EMUL_MODE_PROT64:
2023 default:
2024 /* Protected mode interrupts unimplemented yet */
2025 return X86EMUL_UNHANDLEABLE;
2026 }
2027}
2028
7b105ca2 2029static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2030{
dde7e6d1
AK		 2031 int rc = X86EMUL_CONTINUE;
2032 unsigned long temp_eip = 0;
2033 unsigned long temp_eflags = 0;
2034 unsigned long cs = 0;
2035 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2036 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2037 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2038 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2039
dde7e6d1 2040 /* TODO: Add stack limit check */
38ba30ba 2041
9dac77fa 2042 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2043
dde7e6d1
AK		 2044 if (rc != X86EMUL_CONTINUE)
2045 return rc;
38ba30ba 2046
35d3d4a1
AK		 2047 if (temp_eip & ~0xffff)
2048 return emulate_gp(ctxt, 0);
38ba30ba 2049
9dac77fa 2050 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2051
dde7e6d1
AK		 2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
38ba30ba 2054
9dac77fa 2055 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2056
dde7e6d1
AK		 2057 if (rc != X86EMUL_CONTINUE)
2058 return rc;
38ba30ba 2059
7b105ca2 2060 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2061
dde7e6d1
AK		 2062 if (rc != X86EMUL_CONTINUE)
2063 return rc;
38ba30ba 2064
9dac77fa 2065 ctxt->_eip = temp_eip;
38ba30ba 2066
38ba30ba 2067
9dac77fa 2068 if (ctxt->op_bytes == 4)
dde7e6d1 2069 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2070 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2071 ctxt->eflags &= ~0xffff;
2072 ctxt->eflags |= temp_eflags;
38ba30ba 2073 }
dde7e6d1
AK		 2074
2075 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2076 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2077
2078 return rc;
38ba30ba
GN		 2079}
2080
e01991e7 2081static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2082{
dde7e6d1
AK		 2083 switch(ctxt->mode) {
2084 case X86EMUL_MODE_REAL:
7b105ca2 2085 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2086 case X86EMUL_MODE_VM86:
2087 case X86EMUL_MODE_PROT16:
2088 case X86EMUL_MODE_PROT32:
2089 case X86EMUL_MODE_PROT64:
c37eda13 2090 default:
dde7e6d1
AK		 2091 /* iret from protected mode unimplemented yet */
2092 return X86EMUL_UNHANDLEABLE;
c37eda13 2093 }
c37eda13
WY		 2094}
2095
d2f62766
TY		 2096static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2097{
d2f62766
TY		 2098 int rc;
2099 unsigned short sel;
2100
9dac77fa 2101 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2102
7b105ca2 2103 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2104 if (rc != X86EMUL_CONTINUE)
2105 return rc;
2106
9dac77fa
AK		 2107 ctxt->_eip = 0;
2108 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2109 return X86EMUL_CONTINUE;
2110}
2111
3329ece1
AK		 2112static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2113{
2114 u8 ex = 0;
2115
2116 emulate_1op_rax_rdx(ctxt, "mul", ex);
2117 return X86EMUL_CONTINUE;
2118}
2119
2120static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2121{
2122 u8 ex = 0;
2123
2124 emulate_1op_rax_rdx(ctxt, "imul", ex);
2125 return X86EMUL_CONTINUE;
2126}
2127
2128static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2129{
34d1f490 2130 u8 de = 0;
8cdbd2c9 2131
3329ece1
AK		 2132 emulate_1op_rax_rdx(ctxt, "div", de);
2133 if (de)
2134 return emulate_de(ctxt);
2135 return X86EMUL_CONTINUE;
2136}
2137
2138static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2139{
2140 u8 de = 0;
2141
2142 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2143 if (de)
2144 return emulate_de(ctxt);
8c5eee30 2145 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2146}
2147
51187683 2148static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2149{
4179bb02 2150 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2151
9dac77fa 2152 switch (ctxt->modrm_reg) {
d19292e4
MG		 2153 case 2: /* call near abs */ {
2154 long int old_eip;
9dac77fa
AK		 2155 old_eip = ctxt->_eip;
2156 ctxt->_eip = ctxt->src.val;
2157 ctxt->src.val = old_eip;
4487b3b4 2158 rc = em_push(ctxt);
d19292e4
MG		 2159 break;
2160 }
8cdbd2c9 2161 case 4: /* jmp abs */
9dac77fa 2162 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2163 break;
d2f62766
TY		 2164 case 5: /* jmp far */
2165 rc = em_jmp_far(ctxt);
2166 break;
8cdbd2c9 2167 case 6: /* push */
4487b3b4 2168 rc = em_push(ctxt);
8cdbd2c9 2169 break;
8cdbd2c9 2170 }
4179bb02 2171 return rc;
8cdbd2c9
LV		 2172}
2173
e0dac408 2174static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2175{
9dac77fa 2176 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2177
dd856efa
AK		 2178 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2179 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2180 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2181 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2182 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2183 } else {
dd856efa
AK		 2184 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2185 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2186
05f086f8 2187 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2188 }
1b30eaa8 2189 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2190}
2191
ebda02c2
TY		 2192static int em_ret(struct x86_emulate_ctxt *ctxt)
2193{
9dac77fa
AK		 2194 ctxt->dst.type = OP_REG;
2195 ctxt->dst.addr.reg = &ctxt->_eip;
2196 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2197 return em_pop(ctxt);
2198}
2199
e01991e7 2200static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2201{
a77ab5ea
AK		 2202 int rc;
2203 unsigned long cs;
2204
9dac77fa 2205 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2206 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2207 return rc;
9dac77fa
AK		 2208 if (ctxt->op_bytes == 4)
2209 ctxt->_eip = (u32)ctxt->_eip;
2210 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2211 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2212 return rc;
7b105ca2 2213 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2214 return rc;
2215}
2216
e940b5c2
TY		 2217static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2218{
2219 /* Save real source value, then compare EAX against destination. */
2220 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2221 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2222 fastop(ctxt, em_cmp);
e940b5c2
TY		 2223
2224 if (ctxt->eflags & EFLG_ZF) {
2225 /* Success: write back to memory. */
2226 ctxt->dst.val = ctxt->src.orig_val;
2227 } else {
2228 /* Failure: write the value we saw to EAX. */
2229 ctxt->dst.type = OP_REG;
dd856efa 2230 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2231 }
2232 return X86EMUL_CONTINUE;
2233}
2234
d4b4325f 2235static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2236{
d4b4325f 2237 int seg = ctxt->src2.val;
09b5f4d3
WY		 2238 unsigned short sel;
2239 int rc;
2240
9dac77fa 2241 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2242
7b105ca2 2243 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2244 if (rc != X86EMUL_CONTINUE)
2245 return rc;
2246
9dac77fa 2247 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2248 return rc;
2249}
2250
7b105ca2 2251static void
e66bb2cc 2252setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2253 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2254{
e66bb2cc 2255 cs->l = 0; /* will be adjusted later */
79168fd1 2256 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2257 cs->g = 1; /* 4kb granularity */
79168fd1 2258 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2259 cs->type = 0x0b; /* Read, Execute, Accessed */
2260 cs->s = 1;
2261 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2262 cs->p = 1;
2263 cs->d = 1;
99245b50 2264 cs->avl = 0;
e66bb2cc 2265
79168fd1
GN		 2266 set_desc_base(ss, 0); /* flat segment */
2267 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2268 ss->g = 1; /* 4kb granularity */
2269 ss->s = 1;
2270 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2271 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2272 ss->dpl = 0;
79168fd1 2273 ss->p = 1;
99245b50
GN		 2274 ss->l = 0;
2275 ss->avl = 0;
e66bb2cc
AP		 2276}
2277
1a18a69b
AK		 2278static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2279{
2280 u32 eax, ebx, ecx, edx;
2281
2282 eax = ecx = 0;
0017f93a
AK		 2283 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2284 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2285 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2286 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2287}
2288
c2226fc9
SB		 2289static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2290{
0225fb50 2291 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2292 u32 eax, ebx, ecx, edx;
2293
2294 /*
2295 * syscall should always be enabled in longmode - so only become
2296 * vendor specific (cpuid) if other modes are active...
2297 */
2298 if (ctxt->mode == X86EMUL_MODE_PROT64)
2299 return true;
2300
2301 eax = 0x00000000;
2302 ecx = 0x00000000;
0017f93a
AK		 2303 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2304 /*
2305 * Intel ("GenuineIntel")
2306 * remark: Intel CPUs only support "syscall" in 64bit
2307 * longmode. Also an 64bit guest with a
2308 * 32bit compat-app running will #UD !! While this
2309 * behaviour can be fixed (by emulating) into AMD
2310 * response - CPUs of AMD can't behave like Intel.
2311 */
2312 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2313 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2314 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2315 return false;
2316
2317 /* AMD ("AuthenticAMD") */
2318 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2319 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2320 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2321 return true;
2322
2323 /* AMD ("AMDisbetter!") */
2324 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2325 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2326 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2327 return true;
c2226fc9
SB		 2328
2329 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2330 return false;
2331}
2332
e01991e7 2333static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2334{
0225fb50 2335 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2336 struct desc_struct cs, ss;
e66bb2cc 2337 u64 msr_data;
79168fd1 2338 u16 cs_sel, ss_sel;
c2ad2bb3 2339 u64 efer = 0;
e66bb2cc
AP		 2340
2341 /* syscall is not available in real mode */
2e901c4c 2342 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2343 ctxt->mode == X86EMUL_MODE_VM86)
2344 return emulate_ud(ctxt);
e66bb2cc 2345
c2226fc9
SB		 2346 if (!(em_syscall_is_enabled(ctxt)))
2347 return emulate_ud(ctxt);
2348
c2ad2bb3 2349 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2350 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2351
c2226fc9
SB		 2352 if (!(efer & EFER_SCE))
2353 return emulate_ud(ctxt);
2354
717746e3 2355 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2356 msr_data >>= 32;
79168fd1
GN		 2357 cs_sel = (u16)(msr_data & 0xfffc);
2358 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2359
c2ad2bb3 2360 if (efer & EFER_LMA) {
79168fd1 2361 cs.d = 0;
e66bb2cc
AP		 2362 cs.l = 1;
2363 }
1aa36616
AK		 2364 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2365 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2366
dd856efa 2367 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2368 if (efer & EFER_LMA) {
e66bb2cc 2369#ifdef CONFIG_X86_64
dd856efa 2370 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2371
717746e3 2372 ops->get_msr(ctxt,
3fb1b5db
GN		 2373 ctxt->mode == X86EMUL_MODE_PROT64 ?
2374 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2375 ctxt->_eip = msr_data;
e66bb2cc 2376
717746e3 2377 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2378 ctxt->eflags &= ~(msr_data | EFLG_RF);
2379#endif
2380 } else {
2381 /* legacy mode */
717746e3 2382 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2383 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2384
2385 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2386 }
2387
e54cfa97 2388 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2389}
2390
e01991e7 2391static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2392{
0225fb50 2393 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2394 struct desc_struct cs, ss;
8c604352 2395 u64 msr_data;
79168fd1 2396 u16 cs_sel, ss_sel;
c2ad2bb3 2397 u64 efer = 0;
8c604352 2398
7b105ca2 2399 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2400 /* inject #GP if in real mode */
35d3d4a1
AK		 2401 if (ctxt->mode == X86EMUL_MODE_REAL)
2402 return emulate_gp(ctxt, 0);
8c604352 2403
1a18a69b
AK		 2404 /*
2405 * Not recognized on AMD in compat mode (but is recognized in legacy
2406 * mode).
2407 */
2408 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2409 && !vendor_intel(ctxt))
2410 return emulate_ud(ctxt);
2411
8c604352
AP		 2412 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2413 * Therefore, we inject an #UD.
2414 */
35d3d4a1
AK		 2415 if (ctxt->mode == X86EMUL_MODE_PROT64)
2416 return emulate_ud(ctxt);
8c604352 2417
7b105ca2 2418 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2419
717746e3 2420 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2421 switch (ctxt->mode) {
2422 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2423 if ((msr_data & 0xfffc) == 0x0)
2424 return emulate_gp(ctxt, 0);
8c604352
AP		 2425 break;
2426 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2427 if (msr_data == 0x0)
2428 return emulate_gp(ctxt, 0);
8c604352 2429 break;
9d1b39a9
GN		 2430 default:
2431 break;
8c604352
AP		 2432 }
2433
2434 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2435 cs_sel = (u16)msr_data;
2436 cs_sel &= ~SELECTOR_RPL_MASK;
2437 ss_sel = cs_sel + 8;
2438 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2439 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2440 cs.d = 0;
8c604352
AP		 2441 cs.l = 1;
2442 }
2443
1aa36616
AK		 2444 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2445 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2446
717746e3 2447 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2448 ctxt->_eip = msr_data;
8c604352 2449
717746e3 2450 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2451 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2452
e54cfa97 2453 return X86EMUL_CONTINUE;
8c604352
AP		 2454}
2455
e01991e7 2456static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2457{
0225fb50 2458 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2459 struct desc_struct cs, ss;
4668f050
AP		 2460 u64 msr_data;
2461 int usermode;
1249b96e 2462 u16 cs_sel = 0, ss_sel = 0;
4668f050 2463
a0044755
GN		 2464 /* inject #GP if in real mode or Virtual 8086 mode */
2465 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2466 ctxt->mode == X86EMUL_MODE_VM86)
2467 return emulate_gp(ctxt, 0);
4668f050 2468
7b105ca2 2469 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2470
9dac77fa 2471 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2472 usermode = X86EMUL_MODE_PROT64;
2473 else
2474 usermode = X86EMUL_MODE_PROT32;
2475
2476 cs.dpl = 3;
2477 ss.dpl = 3;
717746e3 2478 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2479 switch (usermode) {
2480 case X86EMUL_MODE_PROT32:
79168fd1 2481 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2482 if ((msr_data & 0xfffc) == 0x0)
2483 return emulate_gp(ctxt, 0);
79168fd1 2484 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2485 break;
2486 case X86EMUL_MODE_PROT64:
79168fd1 2487 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2488 if (msr_data == 0x0)
2489 return emulate_gp(ctxt, 0);
79168fd1
GN		 2490 ss_sel = cs_sel + 8;
2491 cs.d = 0;
4668f050
AP		 2492 cs.l = 1;
2493 break;
2494 }
79168fd1
GN		 2495 cs_sel |= SELECTOR_RPL_MASK;
2496 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2497
1aa36616
AK		 2498 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2499 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2500
dd856efa
AK		 2501 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2502 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2503
e54cfa97 2504 return X86EMUL_CONTINUE;
4668f050
AP		 2505}
2506
7b105ca2 2507static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2508{
2509 int iopl;
2510 if (ctxt->mode == X86EMUL_MODE_REAL)
2511 return false;
2512 if (ctxt->mode == X86EMUL_MODE_VM86)
2513 return true;
2514 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2515 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2516}
2517
2518static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2519 u16 port, u16 len)
2520{
0225fb50 2521 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2522 struct desc_struct tr_seg;
5601d05b 2523 u32 base3;
f850e2e6 2524 int r;
1aa36616 2525 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2526 unsigned mask = (1 << len) - 1;
5601d05b 2527 unsigned long base;
f850e2e6 2528
1aa36616 2529 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2530 if (!tr_seg.p)
f850e2e6 2531 return false;
79168fd1 2532 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2533 return false;
5601d05b
GN		 2534 base = get_desc_base(&tr_seg);
2535#ifdef CONFIG_X86_64
2536 base |= ((u64)base3) << 32;
2537#endif
0f65dd70 2538 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2539 if (r != X86EMUL_CONTINUE)
2540 return false;
79168fd1 2541 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2542 return false;
0f65dd70 2543 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2544 if (r != X86EMUL_CONTINUE)
2545 return false;
2546 if ((perm >> bit_idx) & mask)
2547 return false;
2548 return true;
2549}
2550
2551static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2552 u16 port, u16 len)
2553{
4fc40f07
GN		 2554 if (ctxt->perm_ok)
2555 return true;
2556
7b105ca2
TY		 2557 if (emulator_bad_iopl(ctxt))
2558 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2559 return false;
4fc40f07
GN		 2560
2561 ctxt->perm_ok = true;
2562
f850e2e6
GN		 2563 return true;
2564}
2565
38ba30ba 2566static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2567 struct tss_segment_16 *tss)
2568{
9dac77fa 2569 tss->ip = ctxt->_eip;
38ba30ba 2570 tss->flag = ctxt->eflags;
dd856efa
AK		 2571 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2572 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2573 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2574 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2575 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2576 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2577 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2578 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2579
1aa36616
AK		 2580 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2581 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2582 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2583 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2584 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2585}
2586
2587static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2588 struct tss_segment_16 *tss)
2589{
38ba30ba
GN		 2590 int ret;
2591
9dac77fa 2592 ctxt->_eip = tss->ip;
38ba30ba 2593 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2594 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2595 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2596 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2597 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2598 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2599 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2600 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2601 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2602
2603 /*
2604 * SDM says that segment selectors are loaded before segment
2605 * descriptors
2606 */
1aa36616
AK		 2607 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2608 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2609 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2610 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2611 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2612
2613 /*
fc058680 2614 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2615 * it is handled in a context of new task
2616 */
7b105ca2 2617 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2618 if (ret != X86EMUL_CONTINUE)
2619 return ret;
7b105ca2 2620 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
7b105ca2 2623 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
7b105ca2 2626 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
7b105ca2 2629 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
2632
2633 return X86EMUL_CONTINUE;
2634}
2635
2636static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2637 u16 tss_selector, u16 old_tss_sel,
2638 ulong old_tss_base, struct desc_struct *new_desc)
2639{
0225fb50 2640 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2641 struct tss_segment_16 tss_seg;
2642 int ret;
bcc55cba 2643 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2644
0f65dd70 2645 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba 2650
7b105ca2 2651 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2652
0f65dd70 2653 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2654 &ctxt->exception);
db297e3d 2655 if (ret != X86EMUL_CONTINUE)
38ba30ba 2656 /* FIXME: need to provide precise fault address */
38ba30ba 2657 return ret;
38ba30ba 2658
0f65dd70 2659 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2660 &ctxt->exception);
db297e3d 2661 if (ret != X86EMUL_CONTINUE)
38ba30ba 2662 /* FIXME: need to provide precise fault address */
38ba30ba 2663 return ret;
38ba30ba
GN		 2664
2665 if (old_tss_sel != 0xffff) {
2666 tss_seg.prev_task_link = old_tss_sel;
2667
0f65dd70 2668 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2669 &tss_seg.prev_task_link,
2670 sizeof tss_seg.prev_task_link,
0f65dd70 2671 &ctxt->exception);
db297e3d 2672 if (ret != X86EMUL_CONTINUE)
38ba30ba 2673 /* FIXME: need to provide precise fault address */
38ba30ba 2674 return ret;
38ba30ba
GN		 2675 }
2676
7b105ca2 2677 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2678}
2679
2680static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2681 struct tss_segment_32 *tss)
2682{
7b105ca2 2683 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2684 tss->eip = ctxt->_eip;
38ba30ba 2685 tss->eflags = ctxt->eflags;
dd856efa
AK		 2686 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2687 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2688 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2689 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2690 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2691 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2692 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2693 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2694
1aa36616
AK		 2695 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2696 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2697 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2698 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2699 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2700 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2701 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2702}
2703
2704static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2705 struct tss_segment_32 *tss)
2706{
38ba30ba
GN		 2707 int ret;
2708
7b105ca2 2709 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2710 return emulate_gp(ctxt, 0);
9dac77fa 2711 ctxt->_eip = tss->eip;
38ba30ba 2712 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2713
2714 /* General purpose registers */
dd856efa
AK		 2715 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2716 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2717 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2718 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2719 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2720 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2721 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2722 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2723
2724 /*
2725 * SDM says that segment selectors are loaded before segment
2726 * descriptors
2727 */
1aa36616
AK		 2728 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2729 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2730 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2731 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2732 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2733 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2734 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2735
4cee4798
KW		 2736 /*
2737 * If we're switching between Protected Mode and VM86, we need to make
2738 * sure to update the mode before loading the segment descriptors so
2739 * that the selectors are interpreted correctly.
2740 *
2741 * Need to get rflags to the vcpu struct immediately because it
2742 * influences the CPL which is checked at least when loading the segment
2743 * descriptors and when pushing an error code to the new kernel stack.
2744 *
2745 * TODO Introduce a separate ctxt->ops->set_cpl callback
2746 */
2747 if (ctxt->eflags & X86_EFLAGS_VM)
2748 ctxt->mode = X86EMUL_MODE_VM86;
2749 else
2750 ctxt->mode = X86EMUL_MODE_PROT32;
2751
2752 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2753
38ba30ba
GN		 2754 /*
2755 * Now load segment descriptors. If fault happenes at this stage
2756 * it is handled in a context of new task
2757 */
7b105ca2 2758 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2759 if (ret != X86EMUL_CONTINUE)
2760 return ret;
7b105ca2 2761 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2762 if (ret != X86EMUL_CONTINUE)
2763 return ret;
7b105ca2 2764 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2765 if (ret != X86EMUL_CONTINUE)
2766 return ret;
7b105ca2 2767 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2768 if (ret != X86EMUL_CONTINUE)
2769 return ret;
7b105ca2 2770 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2771 if (ret != X86EMUL_CONTINUE)
2772 return ret;
7b105ca2 2773 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2774 if (ret != X86EMUL_CONTINUE)
2775 return ret;
7b105ca2 2776 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2777 if (ret != X86EMUL_CONTINUE)
2778 return ret;
2779
2780 return X86EMUL_CONTINUE;
2781}
2782
2783static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2784 u16 tss_selector, u16 old_tss_sel,
2785 ulong old_tss_base, struct desc_struct *new_desc)
2786{
0225fb50 2787 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2788 struct tss_segment_32 tss_seg;
2789 int ret;
bcc55cba 2790 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2791
0f65dd70 2792 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2793 &ctxt->exception);
db297e3d 2794 if (ret != X86EMUL_CONTINUE)
38ba30ba 2795 /* FIXME: need to provide precise fault address */
38ba30ba 2796 return ret;
38ba30ba 2797
7b105ca2 2798 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2799
0f65dd70 2800 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2801 &ctxt->exception);
db297e3d 2802 if (ret != X86EMUL_CONTINUE)
38ba30ba 2803 /* FIXME: need to provide precise fault address */
38ba30ba 2804 return ret;
38ba30ba 2805
0f65dd70 2806 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2807 &ctxt->exception);
db297e3d 2808 if (ret != X86EMUL_CONTINUE)
38ba30ba 2809 /* FIXME: need to provide precise fault address */
38ba30ba 2810 return ret;
38ba30ba
GN		 2811
2812 if (old_tss_sel != 0xffff) {
2813 tss_seg.prev_task_link = old_tss_sel;
2814
0f65dd70 2815 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2816 &tss_seg.prev_task_link,
2817 sizeof tss_seg.prev_task_link,
0f65dd70 2818 &ctxt->exception);
db297e3d 2819 if (ret != X86EMUL_CONTINUE)
38ba30ba 2820 /* FIXME: need to provide precise fault address */
38ba30ba 2821 return ret;
38ba30ba
GN		 2822 }
2823
7b105ca2 2824 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2825}
2826
2827static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2828 u16 tss_selector, int idt_index, int reason,
e269fb21 2829 bool has_error_code, u32 error_code)
38ba30ba 2830{
0225fb50 2831 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2832 struct desc_struct curr_tss_desc, next_tss_desc;
2833 int ret;
1aa36616 2834 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2835 ulong old_tss_base =
4bff1e86 2836 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2837 u32 desc_limit;
e919464b 2838 ulong desc_addr;
38ba30ba
GN		 2839
2840 /* FIXME: old_tss_base == ~0 ? */
2841
e919464b 2842 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2843 if (ret != X86EMUL_CONTINUE)
2844 return ret;
e919464b 2845 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2846 if (ret != X86EMUL_CONTINUE)
2847 return ret;
2848
2849 /* FIXME: check that next_tss_desc is tss */
2850
7f3d35fd
KW		 2851 /*
2852 * Check privileges. The three cases are task switch caused by...
2853 *
2854 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2855 * 2. Exception/IRQ/iret: No check is performed
fc058680 2856 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2857 */
2858 if (reason == TASK_SWITCH_GATE) {
2859 if (idt_index != -1) {
2860 /* Software interrupts */
2861 struct desc_struct task_gate_desc;
2862 int dpl;
2863
2864 ret = read_interrupt_descriptor(ctxt, idt_index,
2865 &task_gate_desc);
2866 if (ret != X86EMUL_CONTINUE)
2867 return ret;
2868
2869 dpl = task_gate_desc.dpl;
2870 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2871 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2872 }
2873 } else if (reason != TASK_SWITCH_IRET) {
2874 int dpl = next_tss_desc.dpl;
2875 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2876 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2877 }
2878
7f3d35fd 2879
ceffb459
GN		 2880 desc_limit = desc_limit_scaled(&next_tss_desc);
2881 if (!next_tss_desc.p ||
2882 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2883 desc_limit < 0x2b)) {
54b8486f 2884 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2885 return X86EMUL_PROPAGATE_FAULT;
2886 }
2887
2888 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2889 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2890 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2891 }
2892
2893 if (reason == TASK_SWITCH_IRET)
2894 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2895
2896 /* set back link to prev task only if NT bit is set in eflags
fc058680 2897 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2898 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2899 old_tss_sel = 0xffff;
2900
2901 if (next_tss_desc.type & 8)
7b105ca2 2902 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2903 old_tss_base, &next_tss_desc);
2904 else
7b105ca2 2905 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2906 old_tss_base, &next_tss_desc);
0760d448
JK		 2907 if (ret != X86EMUL_CONTINUE)
2908 return ret;
38ba30ba
GN		 2909
2910 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2911 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2912
2913 if (reason != TASK_SWITCH_IRET) {
2914 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2915 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2916 }
2917
717746e3 2918 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2919 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2920
e269fb21 2921 if (has_error_code) {
9dac77fa
AK		 2922 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2923 ctxt->lock_prefix = 0;
2924 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2925 ret = em_push(ctxt);
e269fb21
JK		 2926 }
2927
38ba30ba
GN		 2928 return ret;
2929}
2930
2931int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2932 u16 tss_selector, int idt_index, int reason,
e269fb21 2933 bool has_error_code, u32 error_code)
38ba30ba 2934{
38ba30ba
GN		 2935 int rc;
2936
dd856efa 2937 invalidate_registers(ctxt);
9dac77fa
AK		 2938 ctxt->_eip = ctxt->eip;
2939 ctxt->dst.type = OP_NONE;
38ba30ba 2940
7f3d35fd 2941 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2942 has_error_code, error_code);
38ba30ba 2943
dd856efa 2944 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2945 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2946 writeback_registers(ctxt);
2947 }
38ba30ba 2948
a0c0ab2f 2949 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2950}
2951
f3bd64c6
GN		 2952static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2953 struct operand *op)
a682e354 2954{
b3356bf0 2955 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2956
dd856efa
AK		 2957 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2958 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2959}
2960
7af04fc0
AK		 2961static int em_das(struct x86_emulate_ctxt *ctxt)
2962{
7af04fc0
AK		 2963 u8 al, old_al;
2964 bool af, cf, old_cf;
2965
2966 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2967 al = ctxt->dst.val;
7af04fc0
AK		 2968
2969 old_al = al;
2970 old_cf = cf;
2971 cf = false;
2972 af = ctxt->eflags & X86_EFLAGS_AF;
2973 if ((al & 0x0f) > 9 || af) {
2974 al -= 6;
2975 cf = old_cf | (al >= 250);
2976 af = true;
2977 } else {
2978 af = false;
2979 }
2980 if (old_al > 0x99 || old_cf) {
2981 al -= 0x60;
2982 cf = true;
2983 }
2984
9dac77fa 2985 ctxt->dst.val = al;
7af04fc0 2986 /* Set PF, ZF, SF */
9dac77fa
AK		 2987 ctxt->src.type = OP_IMM;
2988 ctxt->src.val = 0;
2989 ctxt->src.bytes = 1;
158de57f 2990 fastop(ctxt, em_or);
7af04fc0
AK		 2991 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2992 if (cf)
2993 ctxt->eflags |= X86_EFLAGS_CF;
2994 if (af)
2995 ctxt->eflags |= X86_EFLAGS_AF;
2996 return X86EMUL_CONTINUE;
2997}
2998
a035d5c6
PB		 2999static int em_aam(struct x86_emulate_ctxt *ctxt)
3000{
3001 u8 al, ah;
3002
3003 if (ctxt->src.val == 0)
3004 return emulate_de(ctxt);
3005
3006 al = ctxt->dst.val & 0xff;
3007 ah = al / ctxt->src.val;
3008 al %= ctxt->src.val;
3009
3010 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3011
3012 /* Set PF, ZF, SF */
3013 ctxt->src.type = OP_IMM;
3014 ctxt->src.val = 0;
3015 ctxt->src.bytes = 1;
3016 fastop(ctxt, em_or);
3017
3018 return X86EMUL_CONTINUE;
3019}
3020
7f662273
GN		 3021static int em_aad(struct x86_emulate_ctxt *ctxt)
3022{
3023 u8 al = ctxt->dst.val & 0xff;
3024 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3025
3026 al = (al + (ah * ctxt->src.val)) & 0xff;
3027
3028 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3029
f583c29b
GN		 3030 /* Set PF, ZF, SF */
3031 ctxt->src.type = OP_IMM;
3032 ctxt->src.val = 0;
3033 ctxt->src.bytes = 1;
3034 fastop(ctxt, em_or);
7f662273
GN		 3035
3036 return X86EMUL_CONTINUE;
3037}
3038
d4ddafcd
TY		 3039static int em_call(struct x86_emulate_ctxt *ctxt)
3040{
3041 long rel = ctxt->src.val;
3042
3043 ctxt->src.val = (unsigned long)ctxt->_eip;
3044 jmp_rel(ctxt, rel);
3045 return em_push(ctxt);
3046}
3047
0ef753b8
AK		 3048static int em_call_far(struct x86_emulate_ctxt *ctxt)
3049{
0ef753b8
AK		 3050 u16 sel, old_cs;
3051 ulong old_eip;
3052 int rc;
3053
1aa36616 3054 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3055 old_eip = ctxt->_eip;
0ef753b8 3056
9dac77fa 3057 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3058 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3059 return X86EMUL_CONTINUE;
3060
9dac77fa
AK		 3061 ctxt->_eip = 0;
3062 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3063
9dac77fa 3064 ctxt->src.val = old_cs;
4487b3b4 3065 rc = em_push(ctxt);
0ef753b8
AK		 3066 if (rc != X86EMUL_CONTINUE)
3067 return rc;
3068
9dac77fa 3069 ctxt->src.val = old_eip;
4487b3b4 3070 return em_push(ctxt);
0ef753b8
AK		 3071}
3072
40ece7c7
AK		 3073static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3074{
40ece7c7
AK		 3075 int rc;
3076
9dac77fa
AK		 3077 ctxt->dst.type = OP_REG;
3078 ctxt->dst.addr.reg = &ctxt->_eip;
3079 ctxt->dst.bytes = ctxt->op_bytes;
3080 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3081 if (rc != X86EMUL_CONTINUE)
3082 return rc;
5ad105e5 3083 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3084 return X86EMUL_CONTINUE;
3085}
3086
e4f973ae
TY		 3087static int em_xchg(struct x86_emulate_ctxt *ctxt)
3088{
e4f973ae 3089 /* Write back the register source. */
9dac77fa
AK		 3090 ctxt->src.val = ctxt->dst.val;
3091 write_register_operand(&ctxt->src);
e4f973ae
TY		 3092
3093 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3094 ctxt->dst.val = ctxt->src.orig_val;
3095 ctxt->lock_prefix = 1;
e4f973ae
TY		 3096 return X86EMUL_CONTINUE;
3097}
3098
5c82aa29
AK		 3099static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3100{
9dac77fa 3101 ctxt->dst.val = ctxt->src2.val;
4d758349 3102 return fastop(ctxt, em_imul);
5c82aa29
AK		 3103}
3104
61429142
AK		 3105static int em_cwd(struct x86_emulate_ctxt *ctxt)
3106{
9dac77fa
AK		 3107 ctxt->dst.type = OP_REG;
3108 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3109 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3110 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3111
3112 return X86EMUL_CONTINUE;
3113}
3114
48bb5d3c
AK		 3115static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3116{
48bb5d3c
AK		 3117 u64 tsc = 0;
3118
717746e3 3119 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3120 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3121 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3122 return X86EMUL_CONTINUE;
3123}
3124
222d21aa
AK		 3125static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3126{
3127 u64 pmc;
3128
dd856efa 3129 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3130 return emulate_gp(ctxt, 0);
dd856efa
AK		 3131 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3132 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3133 return X86EMUL_CONTINUE;
3134}
3135
b9eac5f4
AK		 3136static int em_mov(struct x86_emulate_ctxt *ctxt)
3137{
49597d81 3138 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3139 return X86EMUL_CONTINUE;
3140}
3141
bc00f8d2
TY		 3142static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3143{
3144 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3145 return emulate_gp(ctxt, 0);
3146
3147 /* Disable writeback. */
3148 ctxt->dst.type = OP_NONE;
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3153{
3154 unsigned long val;
3155
3156 if (ctxt->mode == X86EMUL_MODE_PROT64)
3157 val = ctxt->src.val & ~0ULL;
3158 else
3159 val = ctxt->src.val & ~0U;
3160
3161 /* #UD condition is already handled. */
3162 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3163 return emulate_gp(ctxt, 0);
3164
3165 /* Disable writeback. */
3166 ctxt->dst.type = OP_NONE;
3167 return X86EMUL_CONTINUE;
3168}
3169
e1e210b0
TY		 3170static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3171{
3172 u64 msr_data;
3173
dd856efa
AK		 3174 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3175 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3176 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3177 return emulate_gp(ctxt, 0);
3178
3179 return X86EMUL_CONTINUE;
3180}
3181
3182static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3183{
3184 u64 msr_data;
3185
dd856efa 3186 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3187 return emulate_gp(ctxt, 0);
3188
dd856efa
AK		 3189 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3190 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3191 return X86EMUL_CONTINUE;
3192}
3193
1bd5f469
TY		 3194static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3195{
9dac77fa 3196 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3197 return emulate_ud(ctxt);
3198
9dac77fa 3199 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3200 return X86EMUL_CONTINUE;
3201}
3202
3203static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3204{
9dac77fa 3205 u16 sel = ctxt->src.val;
1bd5f469 3206
9dac77fa 3207 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3208 return emulate_ud(ctxt);
3209
9dac77fa 3210 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3211 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3212
3213 /* Disable writeback. */
9dac77fa
AK		 3214 ctxt->dst.type = OP_NONE;
3215 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3216}
3217
a14e579f
AK		 3218static int em_lldt(struct x86_emulate_ctxt *ctxt)
3219{
3220 u16 sel = ctxt->src.val;
3221
3222 /* Disable writeback. */
3223 ctxt->dst.type = OP_NONE;
3224 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3225}
3226
80890006
AK		 3227static int em_ltr(struct x86_emulate_ctxt *ctxt)
3228{
3229 u16 sel = ctxt->src.val;
3230
3231 /* Disable writeback. */
3232 ctxt->dst.type = OP_NONE;
3233 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3234}
3235
38503911
AK		 3236static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3237{
9fa088f4
AK		 3238 int rc;
3239 ulong linear;
3240
9dac77fa 3241 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3242 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3243 ctxt->ops->invlpg(ctxt, linear);
38503911 3244 /* Disable writeback. */
9dac77fa 3245 ctxt->dst.type = OP_NONE;
38503911
AK		 3246 return X86EMUL_CONTINUE;
3247}
3248
2d04a05b
AK		 3249static int em_clts(struct x86_emulate_ctxt *ctxt)
3250{
3251 ulong cr0;
3252
3253 cr0 = ctxt->ops->get_cr(ctxt, 0);
3254 cr0 &= ~X86_CR0_TS;
3255 ctxt->ops->set_cr(ctxt, 0, cr0);
3256 return X86EMUL_CONTINUE;
3257}
3258
26d05cc7
AK		 3259static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3260{
26d05cc7
AK		 3261 int rc;
3262
9dac77fa 3263 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3264 return X86EMUL_UNHANDLEABLE;
3265
3266 rc = ctxt->ops->fix_hypercall(ctxt);
3267 if (rc != X86EMUL_CONTINUE)
3268 return rc;
3269
3270 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3271 ctxt->_eip = ctxt->eip;
26d05cc7 3272 /* Disable writeback. */
9dac77fa 3273 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3274 return X86EMUL_CONTINUE;
3275}
3276
96051572
AK		 3277static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3278 void (*get)(struct x86_emulate_ctxt *ctxt,
3279 struct desc_ptr *ptr))
3280{
3281 struct desc_ptr desc_ptr;
3282
3283 if (ctxt->mode == X86EMUL_MODE_PROT64)
3284 ctxt->op_bytes = 8;
3285 get(ctxt, &desc_ptr);
3286 if (ctxt->op_bytes == 2) {
3287 ctxt->op_bytes = 4;
3288 desc_ptr.address &= 0x00ffffff;
3289 }
3290 /* Disable writeback. */
3291 ctxt->dst.type = OP_NONE;
3292 return segmented_write(ctxt, ctxt->dst.addr.mem,
3293 &desc_ptr, 2 + ctxt->op_bytes);
3294}
3295
3296static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3297{
3298 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3299}
3300
3301static int em_sidt(struct x86_emulate_ctxt *ctxt)
3302{
3303 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3304}
3305
26d05cc7
AK		 3306static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3307{
26d05cc7
AK		 3308 struct desc_ptr desc_ptr;
3309 int rc;
3310
510425ff
AK		 3311 if (ctxt->mode == X86EMUL_MODE_PROT64)
3312 ctxt->op_bytes = 8;
9dac77fa 3313 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3314 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3315 ctxt->op_bytes);
26d05cc7
AK		 3316 if (rc != X86EMUL_CONTINUE)
3317 return rc;
3318 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3319 /* Disable writeback. */
9dac77fa 3320 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3321 return X86EMUL_CONTINUE;
3322}
3323
5ef39c71 3324static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3325{
26d05cc7
AK		 3326 int rc;
3327
5ef39c71
AK		 3328 rc = ctxt->ops->fix_hypercall(ctxt);
3329
26d05cc7 3330 /* Disable writeback. */
9dac77fa 3331 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3332 return rc;
3333}
3334
3335static int em_lidt(struct x86_emulate_ctxt *ctxt)
3336{
26d05cc7
AK		 3337 struct desc_ptr desc_ptr;
3338 int rc;
3339
510425ff
AK		 3340 if (ctxt->mode == X86EMUL_MODE_PROT64)
3341 ctxt->op_bytes = 8;
9dac77fa 3342 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3343 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3344 ctxt->op_bytes);
26d05cc7
AK		 3345 if (rc != X86EMUL_CONTINUE)
3346 return rc;
3347 ctxt->ops->set_idt(ctxt, &desc_ptr);
3348 /* Disable writeback. */
9dac77fa 3349 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3350 return X86EMUL_CONTINUE;
3351}
3352
3353static int em_smsw(struct x86_emulate_ctxt *ctxt)
3354{
9dac77fa
AK		 3355 ctxt->dst.bytes = 2;
3356 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3357 return X86EMUL_CONTINUE;
3358}
3359
3360static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3361{
26d05cc7 3362 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3363 | (ctxt->src.val & 0x0f));
3364 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3365 return X86EMUL_CONTINUE;
3366}
3367
d06e03ad
TY		 3368static int em_loop(struct x86_emulate_ctxt *ctxt)
3369{
dd856efa
AK		 3370 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3371 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3372 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3373 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3374
3375 return X86EMUL_CONTINUE;
3376}
3377
3378static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3379{
dd856efa 3380 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3381 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3382
3383 return X86EMUL_CONTINUE;
3384}
3385
d7841a4b
TY		 3386static int em_in(struct x86_emulate_ctxt *ctxt)
3387{
3388 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3389 &ctxt->dst.val))
3390 return X86EMUL_IO_NEEDED;
3391
3392 return X86EMUL_CONTINUE;
3393}
3394
3395static int em_out(struct x86_emulate_ctxt *ctxt)
3396{
3397 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3398 &ctxt->src.val, 1);
3399 /* Disable writeback. */
3400 ctxt->dst.type = OP_NONE;
3401 return X86EMUL_CONTINUE;
3402}
3403
f411e6cd
TY		 3404static int em_cli(struct x86_emulate_ctxt *ctxt)
3405{
3406 if (emulator_bad_iopl(ctxt))
3407 return emulate_gp(ctxt, 0);
3408
3409 ctxt->eflags &= ~X86_EFLAGS_IF;
3410 return X86EMUL_CONTINUE;
3411}
3412
3413static int em_sti(struct x86_emulate_ctxt *ctxt)
3414{
3415 if (emulator_bad_iopl(ctxt))
3416 return emulate_gp(ctxt, 0);
3417
3418 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3419 ctxt->eflags |= X86_EFLAGS_IF;
3420 return X86EMUL_CONTINUE;
3421}
3422
6d6eede4
AK		 3423static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3424{
3425 u32 eax, ebx, ecx, edx;
3426
dd856efa
AK		 3427 eax = reg_read(ctxt, VCPU_REGS_RAX);
3428 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3429 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3430 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3431 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3432 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3433 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3434 return X86EMUL_CONTINUE;
3435}
3436
2dd7caa0
AK		 3437static int em_lahf(struct x86_emulate_ctxt *ctxt)
3438{
dd856efa
AK		 3439 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3440 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3441 return X86EMUL_CONTINUE;
3442}
3443
9299836e
AK		 3444static int em_bswap(struct x86_emulate_ctxt *ctxt)
3445{
3446 switch (ctxt->op_bytes) {
3447#ifdef CONFIG_X86_64
3448 case 8:
3449 asm("bswap %0" : "+r"(ctxt->dst.val));
3450 break;
3451#endif
3452 default:
3453 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3454 break;
3455 }
3456 return X86EMUL_CONTINUE;
3457}
3458
cfec82cb
JR		 3459static bool valid_cr(int nr)
3460{
3461 switch (nr) {
3462 case 0:
3463 case 2 ... 4:
3464 case 8:
3465 return true;
3466 default:
3467 return false;
3468 }
3469}
3470
3471static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3472{
9dac77fa 3473 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3474 return emulate_ud(ctxt);
3475
3476 return X86EMUL_CONTINUE;
3477}
3478
3479static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3480{
9dac77fa
AK		 3481 u64 new_val = ctxt->src.val64;
3482 int cr = ctxt->modrm_reg;
c2ad2bb3 3483 u64 efer = 0;
cfec82cb
JR		 3484
3485 static u64 cr_reserved_bits[] = {
3486 0xffffffff00000000ULL,
3487 0, 0, 0, /* CR3 checked later */
3488 CR4_RESERVED_BITS,
3489 0, 0, 0,
3490 CR8_RESERVED_BITS,
3491 };
3492
3493 if (!valid_cr(cr))
3494 return emulate_ud(ctxt);
3495
3496 if (new_val & cr_reserved_bits[cr])
3497 return emulate_gp(ctxt, 0);
3498
3499 switch (cr) {
3500 case 0: {
c2ad2bb3 3501 u64 cr4;
cfec82cb
JR		 3502 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3503 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3504 return emulate_gp(ctxt, 0);
3505
717746e3
AK		 3506 cr4 = ctxt->ops->get_cr(ctxt, 4);
3507 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3508
3509 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3510 !(cr4 & X86_CR4_PAE))
3511 return emulate_gp(ctxt, 0);
3512
3513 break;
3514 }
3515 case 3: {
3516 u64 rsvd = 0;
3517
c2ad2bb3
AK		 3518 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3519 if (efer & EFER_LMA)
cfec82cb 3520 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3521 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3522 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3523 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3524 rsvd = CR3_NONPAE_RESERVED_BITS;
3525
3526 if (new_val & rsvd)
3527 return emulate_gp(ctxt, 0);
3528
3529 break;
3530 }
3531 case 4: {
717746e3 3532 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3533
3534 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3535 return emulate_gp(ctxt, 0);
3536
3537 break;
3538 }
3539 }
3540
3541 return X86EMUL_CONTINUE;
3542}
3543
3b88e41a
JR		 3544static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3545{
3546 unsigned long dr7;
3547
717746e3 3548 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3549
3550 /* Check if DR7.Global_Enable is set */
3551 return dr7 & (1 << 13);
3552}
3553
3554static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3555{
9dac77fa 3556 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3557 u64 cr4;
3558
3559 if (dr > 7)
3560 return emulate_ud(ctxt);
3561
717746e3 3562 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3563 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3564 return emulate_ud(ctxt);
3565
3566 if (check_dr7_gd(ctxt))
3567 return emulate_db(ctxt);
3568
3569 return X86EMUL_CONTINUE;
3570}
3571
3572static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3573{
9dac77fa
AK		 3574 u64 new_val = ctxt->src.val64;
3575 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3576
3577 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3578 return emulate_gp(ctxt, 0);
3579
3580 return check_dr_read(ctxt);
3581}
3582
01de8b09
JR		 3583static int check_svme(struct x86_emulate_ctxt *ctxt)
3584{
3585 u64 efer;
3586
717746e3 3587 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3588
3589 if (!(efer & EFER_SVME))
3590 return emulate_ud(ctxt);
3591
3592 return X86EMUL_CONTINUE;
3593}
3594
3595static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3596{
dd856efa 3597 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3598
3599 /* Valid physical address? */
d4224449 3600 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3601 return emulate_gp(ctxt, 0);
3602
3603 return check_svme(ctxt);
3604}
3605
d7eb8203
JR		 3606static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3607{
717746e3 3608 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3609
717746e3 3610 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3611 return emulate_ud(ctxt);
3612
3613 return X86EMUL_CONTINUE;
3614}
3615
8061252e
JR		 3616static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3617{
717746e3 3618 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3619 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3620
717746e3 3621 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3622 (rcx > 3))
3623 return emulate_gp(ctxt, 0);
3624
3625 return X86EMUL_CONTINUE;
3626}
3627
f6511935
JR		 3628static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3629{
9dac77fa
AK		 3630 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3631 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3632 return emulate_gp(ctxt, 0);
3633
3634 return X86EMUL_CONTINUE;
3635}
3636
3637static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3638{
9dac77fa
AK		 3639 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3640 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3641 return emulate_gp(ctxt, 0);
3642
3643 return X86EMUL_CONTINUE;
3644}
3645
73fba5f4 3646#define D(_y) { .flags = (_y) }
c4f035c6 3647#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3648#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3649 .check_perm = (_p) }
0b789eee 3650#define N D(NotImpl)
01de8b09 3651#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3652#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3653#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3654#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3655#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3656#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3657#define II(_f, _e, _i) \
3658 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3659#define IIP(_f, _e, _i, _p) \
3660 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3661 .check_perm = (_p) }
aa97bb48 3662#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3663
8d8f4e9f 3664#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3665#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3666#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3667#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3668#define I2bvIP(_f, _e, _i, _p) \
3669 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3670
fb864fbc
AK		 3671#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3672 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3673 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3674
fd0a0d82 3675static const struct opcode group7_rm1[] = {
1c2545be
TY		 3676 DI(SrcNone | Priv, monitor),
3677 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3678 N, N, N, N, N, N,
3679};
3680
fd0a0d82 3681static const struct opcode group7_rm3[] = {
1c2545be
TY		 3682 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3683 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3684 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3685 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3686 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3687 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3688 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3689 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3690};
6230f7fc 3691
fd0a0d82 3692static const struct opcode group7_rm7[] = {
d7eb8203 3693 N,
1c2545be 3694 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3695 N, N, N, N, N, N,
3696};
d67fc27a 3697
fd0a0d82 3698static const struct opcode group1[] = {
fb864fbc
AK		 3699 F(Lock, em_add),
3700 F(Lock | PageTable, em_or),
3701 F(Lock, em_adc),
3702 F(Lock, em_sbb),
3703 F(Lock | PageTable, em_and),
3704 F(Lock, em_sub),
3705 F(Lock, em_xor),
3706 F(NoWrite, em_cmp),
73fba5f4
AK		 3707};
3708
fd0a0d82 3709static const struct opcode group1A[] = {
1c2545be 3710 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3711};
3712
007a3b54
AK		 3713static const struct opcode group2[] = {
3714 F(DstMem | ModRM, em_rol),
3715 F(DstMem | ModRM, em_ror),
3716 F(DstMem | ModRM, em_rcl),
3717 F(DstMem | ModRM, em_rcr),
3718 F(DstMem | ModRM, em_shl),
3719 F(DstMem | ModRM, em_shr),
3720 F(DstMem | ModRM, em_shl),
3721 F(DstMem | ModRM, em_sar),
3722};
3723
fd0a0d82 3724static const struct opcode group3[] = {
fb864fbc
AK		 3725 F(DstMem | SrcImm | NoWrite, em_test),
3726 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3727 F(DstMem | SrcNone | Lock, em_not),
3728 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3729 I(SrcMem, em_mul_ex),
3730 I(SrcMem, em_imul_ex),
3731 I(SrcMem, em_div_ex),
3732 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3733};
3734
fd0a0d82 3735static const struct opcode group4[] = {
95413dc4
AK		 3736 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3737 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3738 N, N, N, N, N, N,
3739};
3740
fd0a0d82 3741static const struct opcode group5[] = {
95413dc4
AK		 3742 F(DstMem | SrcNone | Lock, em_inc),
3743 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3744 I(SrcMem | Stack, em_grp45),
3745 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3746 I(SrcMem | Stack, em_grp45),
3747 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3748 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3749};
3750
fd0a0d82 3751static const struct opcode group6[] = {
1c2545be
TY		 3752 DI(Prot, sldt),
3753 DI(Prot, str),
a14e579f 3754 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3755 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3756 N, N, N, N,
3757};
3758
fd0a0d82 3759static const struct group_dual group7 = { {
96051572
AK		 3760 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3761 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3762 II(SrcMem | Priv, em_lgdt, lgdt),
3763 II(SrcMem | Priv, em_lidt, lidt),
3764 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3765 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3766 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3767}, {
1c2545be 3768 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3769 EXT(0, group7_rm1),
01de8b09 3770 N, EXT(0, group7_rm3),
1c2545be
TY		 3771 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3772 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3773 EXT(0, group7_rm7),
73fba5f4
AK		 3774} };
3775
fd0a0d82 3776static const struct opcode group8[] = {
73fba5f4 3777 N, N, N, N,
11c363ba
AK		 3778 F(DstMem | SrcImmByte | NoWrite, em_bt),
3779 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3780 F(DstMem | SrcImmByte | Lock, em_btr),
3781 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3782};
3783
fd0a0d82 3784static const struct group_dual group9 = { {
1c2545be 3785 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3786}, {
3787 N, N, N, N, N, N, N, N,
3788} };
3789
fd0a0d82 3790static const struct opcode group11[] = {
1c2545be 3791 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3792 X7(D(Undefined)),
a4d4a7c1
AK		 3793};
3794
fd0a0d82 3795static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3796 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3797};
3798
fd0a0d82 3799static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3800 I(0, em_mov), N, N, N,
3801};
3802
045a282c
GN		 3803static const struct escape escape_d9 = { {
3804 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3805}, {
3806 /* 0xC0 - 0xC7 */
3807 N, N, N, N, N, N, N, N,
3808 /* 0xC8 - 0xCF */
3809 N, N, N, N, N, N, N, N,
3810 /* 0xD0 - 0xC7 */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xD8 - 0xDF */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xE0 - 0xE7 */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xE8 - 0xEF */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xF0 - 0xF7 */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xF8 - 0xFF */
3821 N, N, N, N, N, N, N, N,
3822} };
3823
3824static const struct escape escape_db = { {
3825 N, N, N, N, N, N, N, N,
3826}, {
3827 /* 0xC0 - 0xC7 */
3828 N, N, N, N, N, N, N, N,
3829 /* 0xC8 - 0xCF */
3830 N, N, N, N, N, N, N, N,
3831 /* 0xD0 - 0xC7 */
3832 N, N, N, N, N, N, N, N,
3833 /* 0xD8 - 0xDF */
3834 N, N, N, N, N, N, N, N,
3835 /* 0xE0 - 0xE7 */
3836 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3837 /* 0xE8 - 0xEF */
3838 N, N, N, N, N, N, N, N,
3839 /* 0xF0 - 0xF7 */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xF8 - 0xFF */
3842 N, N, N, N, N, N, N, N,
3843} };
3844
3845static const struct escape escape_dd = { {
3846 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3847}, {
3848 /* 0xC0 - 0xC7 */
3849 N, N, N, N, N, N, N, N,
3850 /* 0xC8 - 0xCF */
3851 N, N, N, N, N, N, N, N,
3852 /* 0xD0 - 0xC7 */
3853 N, N, N, N, N, N, N, N,
3854 /* 0xD8 - 0xDF */
3855 N, N, N, N, N, N, N, N,
3856 /* 0xE0 - 0xE7 */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xE8 - 0xEF */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xF0 - 0xF7 */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xF8 - 0xFF */
3863 N, N, N, N, N, N, N, N,
3864} };
3865
fd0a0d82 3866static const struct opcode opcode_table[256] = {
73fba5f4 3867 /* 0x00 - 0x07 */
fb864fbc 3868 F6ALU(Lock, em_add),
1cd196ea
AK		 3869 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3870 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3871 /* 0x08 - 0x0F */
fb864fbc 3872 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3873 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3874 N,
73fba5f4 3875 /* 0x10 - 0x17 */
fb864fbc 3876 F6ALU(Lock, em_adc),
1cd196ea
AK		 3877 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3878 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3879 /* 0x18 - 0x1F */
fb864fbc 3880 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3881 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3882 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3883 /* 0x20 - 0x27 */
fb864fbc 3884 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3885 /* 0x28 - 0x2F */
fb864fbc 3886 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3887 /* 0x30 - 0x37 */
fb864fbc 3888 F6ALU(Lock, em_xor), N, N,
73fba5f4 3889 /* 0x38 - 0x3F */
fb864fbc 3890 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3891 /* 0x40 - 0x4F */
95413dc4 3892 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3893 /* 0x50 - 0x57 */
63540382 3894 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3895 /* 0x58 - 0x5F */
c54fe504 3896 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3897 /* 0x60 - 0x67 */
b96a7fad
TY		 3898 I(ImplicitOps | Stack | No64, em_pusha),
3899 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3900 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3901 N, N, N, N,
3902 /* 0x68 - 0x6F */
d46164db
AK		 3903 I(SrcImm | Mov | Stack, em_push),
3904 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3905 I(SrcImmByte | Mov | Stack, em_push),
3906 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3907 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3908 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3909 /* 0x70 - 0x7F */
3910 X16(D(SrcImmByte)),
3911 /* 0x80 - 0x87 */
1c2545be
TY		 3912 G(ByteOp | DstMem | SrcImm, group1),
3913 G(DstMem | SrcImm, group1),
3914 G(ByteOp | DstMem | SrcImm | No64, group1),
3915 G(DstMem | SrcImmByte, group1),
fb864fbc 3916 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3917 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3918 /* 0x88 - 0x8F */
d5ae7ce8 3919 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3920 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3921 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3922 D(ModRM | SrcMem | NoAccess | DstReg),
3923 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3924 G(0, group1A),
73fba5f4 3925 /* 0x90 - 0x97 */
bf608f88 3926 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3927 /* 0x98 - 0x9F */
61429142 3928 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3929 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3930 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3931 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3932 /* 0xA0 - 0xA7 */
b9eac5f4 3933 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3934 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3935 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3936 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3937 /* 0xA8 - 0xAF */
fb864fbc 3938 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3939 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3940 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3941 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3942 /* 0xB0 - 0xB7 */
b9eac5f4 3943 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3944 /* 0xB8 - 0xBF */
5e2c6883 3945 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3946 /* 0xC0 - 0xC7 */
007a3b54 3947 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3948 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3949 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3950 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3951 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3952 G(ByteOp, group11), G(0, group11),
73fba5f4 3953 /* 0xC8 - 0xCF */
612e89f0
AK		 3954 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3955 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3956 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3957 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3958 /* 0xD0 - 0xD7 */
007a3b54
AK		 3959 G(Src2One | ByteOp, group2), G(Src2One, group2),
3960 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6
PB		 3961 I(DstAcc | SrcImmUByte | No64, em_aam),
3962 I(DstAcc | SrcImmUByte | No64, em_aad), N, N,
73fba5f4 3963 /* 0xD8 - 0xDF */
045a282c 3964 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3965 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3966 X3(I(SrcImmByte, em_loop)),
3967 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3968 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3969 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3970 /* 0xE8 - 0xEF */
d4ddafcd 3971 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3972 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3973 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3974 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3975 /* 0xF0 - 0xF7 */
bf608f88 3976 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3977 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3978 G(ByteOp, group3), G(0, group3),
73fba5f4 3979 /* 0xF8 - 0xFF */
f411e6cd
TY		 3980 D(ImplicitOps), D(ImplicitOps),
3981 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3982 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3983};
3984
fd0a0d82 3985static const struct opcode twobyte_table[256] = {
73fba5f4 3986 /* 0x00 - 0x0F */
dee6bb70 3987 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3988 N, I(ImplicitOps | VendorSpecific, em_syscall),
3989 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3990 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3991 N, D(ImplicitOps | ModRM), N, N,
3992 /* 0x10 - 0x1F */
3993 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3994 /* 0x20 - 0x2F */
cfec82cb 3995 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3996 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3997 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3998 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3999 N, N, N, N,
3e114eb4
AK		 4000 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4001 N, N, N, N,
73fba5f4 4002 /* 0x30 - 0x3F */
e1e210b0 4003 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4004 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4005 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4006 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4007 I(ImplicitOps | VendorSpecific, em_sysenter),
4008 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4009 N, N,
73fba5f4
AK		 4010 N, N, N, N, N, N, N, N,
4011 /* 0x40 - 0x4F */
4012 X16(D(DstReg | SrcMem | ModRM | Mov)),
4013 /* 0x50 - 0x5F */
4014 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4015 /* 0x60 - 0x6F */
aa97bb48
AK		 4016 N, N, N, N,
4017 N, N, N, N,
4018 N, N, N, N,
4019 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4020 /* 0x70 - 0x7F */
aa97bb48
AK		 4021 N, N, N, N,
4022 N, N, N, N,
4023 N, N, N, N,
4024 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4025 /* 0x80 - 0x8F */
4026 X16(D(SrcImm)),
4027 /* 0x90 - 0x9F */
ee45b58e 4028 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4029 /* 0xA0 - 0xA7 */
1cd196ea 4030 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4031 II(ImplicitOps, em_cpuid, cpuid),
4032 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4033 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4034 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4035 /* 0xA8 - 0xAF */
1cd196ea 4036 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4037 DI(ImplicitOps, rsm),
11c363ba 4038 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4039 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4040 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4041 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4042 /* 0xB0 - 0xB7 */
e940b5c2 4043 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4044 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4045 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4046 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4047 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4048 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4049 /* 0xB8 - 0xBF */
4050 N, N,
ce7faab2 4051 G(BitOp, group8),
11c363ba
AK		 4052 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4053 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4054 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4055 /* 0xC0 - 0xC7 */
739ae406 4056 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4057 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4058 N, N, N, GD(0, &group9),
9299836e
AK		 4059 /* 0xC8 - 0xCF */
4060 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4061 /* 0xD0 - 0xDF */
4062 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4063 /* 0xE0 - 0xEF */
4064 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4065 /* 0xF0 - 0xFF */
4066 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4067};
4068
4069#undef D
4070#undef N
4071#undef G
4072#undef GD
4073#undef I
aa97bb48 4074#undef GP
01de8b09 4075#undef EXT
73fba5f4 4076
8d8f4e9f 4077#undef D2bv
f6511935 4078#undef D2bvIP
8d8f4e9f 4079#undef I2bv
d7841a4b 4080#undef I2bvIP
d67fc27a 4081#undef I6ALU
8d8f4e9f 4082
9dac77fa 4083static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4084{
4085 unsigned size;
4086
9dac77fa 4087 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4088 if (size == 8)
4089 size = 4;
4090 return size;
4091}
4092
4093static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4094 unsigned size, bool sign_extension)
4095{
39f21ee5
AK		 4096 int rc = X86EMUL_CONTINUE;
4097
4098 op->type = OP_IMM;
4099 op->bytes = size;
9dac77fa 4100 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4101 /* NB. Immediates are sign-extended as necessary. */
4102 switch (op->bytes) {
4103 case 1:
e85a1085 4104 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4105 break;
4106 case 2:
e85a1085 4107 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4108 break;
4109 case 4:
e85a1085 4110 op->val = insn_fetch(s32, ctxt);
39f21ee5 4111 break;
5e2c6883
NA		 4112 case 8:
4113 op->val = insn_fetch(s64, ctxt);
4114 break;
39f21ee5
AK		 4115 }
4116 if (!sign_extension) {
4117 switch (op->bytes) {
4118 case 1:
4119 op->val &= 0xff;
4120 break;
4121 case 2:
4122 op->val &= 0xffff;
4123 break;
4124 case 4:
4125 op->val &= 0xffffffff;
4126 break;
4127 }
4128 }
4129done:
4130 return rc;
4131}
4132
a9945549
AK		 4133static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4134 unsigned d)
4135{
4136 int rc = X86EMUL_CONTINUE;
4137
4138 switch (d) {
4139 case OpReg:
2adb5ad9 4140 decode_register_operand(ctxt, op);
a9945549
AK		 4141 break;
4142 case OpImmUByte:
608aabe3 4143 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4144 break;
4145 case OpMem:
41ddf978 4146 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4147 mem_common:
4148 *op = ctxt->memop;
4149 ctxt->memopp = op;
4150 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4151 fetch_bit_operand(ctxt);
4152 op->orig_val = op->val;
4153 break;
41ddf978
AK		 4154 case OpMem64:
4155 ctxt->memop.bytes = 8;
4156 goto mem_common;
a9945549
AK		 4157 case OpAcc:
4158 op->type = OP_REG;
4159 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4160 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4161 fetch_register_operand(op);
4162 op->orig_val = op->val;
4163 break;
4164 case OpDI:
4165 op->type = OP_MEM;
4166 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4167 op->addr.mem.ea =
dd856efa 4168 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4169 op->addr.mem.seg = VCPU_SREG_ES;
4170 op->val = 0;
b3356bf0 4171 op->count = 1;
a9945549
AK		 4172 break;
4173 case OpDX:
4174 op->type = OP_REG;
4175 op->bytes = 2;
dd856efa 4176 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4177 fetch_register_operand(op);
4178 break;
4dd6a57d
AK		 4179 case OpCL:
4180 op->bytes = 1;
dd856efa 4181 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4182 break;
4183 case OpImmByte:
4184 rc = decode_imm(ctxt, op, 1, true);
4185 break;
4186 case OpOne:
4187 op->bytes = 1;
4188 op->val = 1;
4189 break;
4190 case OpImm:
4191 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4192 break;
5e2c6883
NA		 4193 case OpImm64:
4194 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4195 break;
28867cee
AK		 4196 case OpMem8:
4197 ctxt->memop.bytes = 1;
660696d1
GN		 4198 if (ctxt->memop.type == OP_REG) {
4199 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4200 fetch_register_operand(&ctxt->memop);
4201 }
28867cee 4202 goto mem_common;
0fe59128
AK		 4203 case OpMem16:
4204 ctxt->memop.bytes = 2;
4205 goto mem_common;
4206 case OpMem32:
4207 ctxt->memop.bytes = 4;
4208 goto mem_common;
4209 case OpImmU16:
4210 rc = decode_imm(ctxt, op, 2, false);
4211 break;
4212 case OpImmU:
4213 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4214 break;
4215 case OpSI:
4216 op->type = OP_MEM;
4217 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4218 op->addr.mem.ea =
dd856efa 4219 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4220 op->addr.mem.seg = seg_override(ctxt);
4221 op->val = 0;
b3356bf0 4222 op->count = 1;
0fe59128
AK		 4223 break;
4224 case OpImmFAddr:
4225 op->type = OP_IMM;
4226 op->addr.mem.ea = ctxt->_eip;
4227 op->bytes = ctxt->op_bytes + 2;
4228 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4229 break;
4230 case OpMemFAddr:
4231 ctxt->memop.bytes = ctxt->op_bytes + 2;
4232 goto mem_common;
c191a7a0
AK		 4233 case OpES:
4234 op->val = VCPU_SREG_ES;
4235 break;
4236 case OpCS:
4237 op->val = VCPU_SREG_CS;
4238 break;
4239 case OpSS:
4240 op->val = VCPU_SREG_SS;
4241 break;
4242 case OpDS:
4243 op->val = VCPU_SREG_DS;
4244 break;
4245 case OpFS:
4246 op->val = VCPU_SREG_FS;
4247 break;
4248 case OpGS:
4249 op->val = VCPU_SREG_GS;
4250 break;
a9945549
AK		 4251 case OpImplicit:
4252 /* Special instructions do their own operand decoding. */
4253 default:
4254 op->type = OP_NONE; /* Disable writeback. */
4255 break;
4256 }
4257
4258done:
4259 return rc;
4260}
4261
ef5d75cc 4262int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4263{
dde7e6d1
AK		 4264 int rc = X86EMUL_CONTINUE;
4265 int mode = ctxt->mode;
46561646 4266 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4267 bool op_prefix = false;
46561646 4268 struct opcode opcode;
dde7e6d1 4269
f09ed83e
AK		 4270 ctxt->memop.type = OP_NONE;
4271 ctxt->memopp = NULL;
9dac77fa
AK		 4272 ctxt->_eip = ctxt->eip;
4273 ctxt->fetch.start = ctxt->_eip;
4274 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4275 if (insn_len > 0)
9dac77fa 4276 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4277
4278 switch (mode) {
4279 case X86EMUL_MODE_REAL:
4280 case X86EMUL_MODE_VM86:
4281 case X86EMUL_MODE_PROT16:
4282 def_op_bytes = def_ad_bytes = 2;
4283 break;
4284 case X86EMUL_MODE_PROT32:
4285 def_op_bytes = def_ad_bytes = 4;
4286 break;
4287#ifdef CONFIG_X86_64
4288 case X86EMUL_MODE_PROT64:
4289 def_op_bytes = 4;
4290 def_ad_bytes = 8;
4291 break;
4292#endif
4293 default:
1d2887e2 4294 return EMULATION_FAILED;
dde7e6d1
AK		 4295 }
4296
9dac77fa
AK		 4297 ctxt->op_bytes = def_op_bytes;
4298 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4299
4300 /* Legacy prefixes. */
4301 for (;;) {
e85a1085 4302 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4303 case 0x66: /* operand-size override */
0d7cdee8 4304 op_prefix = true;
dde7e6d1 4305 /* switch between 2/4 bytes */
9dac77fa 4306 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4307 break;
4308 case 0x67: /* address-size override */
4309 if (mode == X86EMUL_MODE_PROT64)
4310 /* switch between 4/8 bytes */
9dac77fa 4311 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4312 else
4313 /* switch between 2/4 bytes */
9dac77fa 4314 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4315 break;
4316 case 0x26: /* ES override */
4317 case 0x2e: /* CS override */
4318 case 0x36: /* SS override */
4319 case 0x3e: /* DS override */
9dac77fa 4320 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4321 break;
4322 case 0x64: /* FS override */
4323 case 0x65: /* GS override */
9dac77fa 4324 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4325 break;
4326 case 0x40 ... 0x4f: /* REX */
4327 if (mode != X86EMUL_MODE_PROT64)
4328 goto done_prefixes;
9dac77fa 4329 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4330 continue;
4331 case 0xf0: /* LOCK */
9dac77fa 4332 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4333 break;
4334 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4335 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4336 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4337 break;
4338 default:
4339 goto done_prefixes;
4340 }
4341
4342 /* Any legacy prefix after a REX prefix nullifies its effect. */
4343
9dac77fa 4344 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4345 }
4346
4347done_prefixes:
4348
4349 /* REX prefix. */
9dac77fa
AK		 4350 if (ctxt->rex_prefix & 8)
4351 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4352
4353 /* Opcode byte(s). */
9dac77fa 4354 opcode = opcode_table[ctxt->b];
d3ad6243 4355 /* Two-byte opcode? */
9dac77fa
AK		 4356 if (ctxt->b == 0x0f) {
4357 ctxt->twobyte = 1;
e85a1085 4358 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4359 opcode = twobyte_table[ctxt->b];
dde7e6d1 4360 }
9dac77fa 4361 ctxt->d = opcode.flags;
dde7e6d1 4362
9f4260e7
TY		 4363 if (ctxt->d & ModRM)
4364 ctxt->modrm = insn_fetch(u8, ctxt);
4365
9dac77fa
AK		 4366 while (ctxt->d & GroupMask) {
4367 switch (ctxt->d & GroupMask) {
46561646 4368 case Group:
9dac77fa 4369 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4370 opcode = opcode.u.group[goffset];
4371 break;
4372 case GroupDual:
9dac77fa
AK		 4373 goffset = (ctxt->modrm >> 3) & 7;
4374 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4375 opcode = opcode.u.gdual->mod3[goffset];
4376 else
4377 opcode = opcode.u.gdual->mod012[goffset];
4378 break;
4379 case RMExt:
9dac77fa 4380 goffset = ctxt->modrm & 7;
01de8b09 4381 opcode = opcode.u.group[goffset];
46561646
AK		 4382 break;
4383 case Prefix:
9dac77fa 4384 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4385 return EMULATION_FAILED;
9dac77fa 4386 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4387 switch (simd_prefix) {
4388 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4389 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4390 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4391 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4392 }
4393 break;
045a282c
GN		 4394 case Escape:
4395 if (ctxt->modrm > 0xbf)
4396 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4397 else
4398 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4399 break;
46561646 4400 default:
1d2887e2 4401 return EMULATION_FAILED;
0d7cdee8 4402 }
46561646 4403
b1ea50b2 4404 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4405 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4406 }
4407
9dac77fa
AK		 4408 ctxt->execute = opcode.u.execute;
4409 ctxt->check_perm = opcode.check_perm;
4410 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4411
4412 /* Unrecognised? */
1146a78b 4413 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4414 return EMULATION_FAILED;
dde7e6d1 4415
9dac77fa 4416 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4417 return EMULATION_FAILED;
d867162c 4418
9dac77fa
AK		 4419 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4420 ctxt->op_bytes = 8;
dde7e6d1 4421
9dac77fa 4422 if (ctxt->d & Op3264) {
7f9b4b75 4423 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4424 ctxt->op_bytes = 8;
7f9b4b75 4425 else
9dac77fa 4426 ctxt->op_bytes = 4;
7f9b4b75
AK		 4427 }
4428
9dac77fa
AK		 4429 if (ctxt->d & Sse)
4430 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4431 else if (ctxt->d & Mmx)
4432 ctxt->op_bytes = 8;
1253791d 4433
dde7e6d1 4434 /* ModRM and SIB bytes. */
9dac77fa 4435 if (ctxt->d & ModRM) {
f09ed83e 4436 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4437 if (!ctxt->has_seg_override)
4438 set_seg_override(ctxt, ctxt->modrm_seg);
4439 } else if (ctxt->d & MemAbs)
f09ed83e 4440 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4441 if (rc != X86EMUL_CONTINUE)
4442 goto done;
4443
9dac77fa
AK		 4444 if (!ctxt->has_seg_override)
4445 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4446
f09ed83e 4447 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4448
f09ed83e
AK		 4449 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4450 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4451
dde7e6d1
AK		 4452 /*
4453 * Decode and fetch the source operand: register, memory
4454 * or immediate.
4455 */
0fe59128 4456 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4457 if (rc != X86EMUL_CONTINUE)
4458 goto done;
4459
dde7e6d1
AK		 4460 /*
4461 * Decode and fetch the second source operand: register, memory
4462 * or immediate.
4463 */
4dd6a57d 4464 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4465 if (rc != X86EMUL_CONTINUE)
4466 goto done;
4467
dde7e6d1 4468 /* Decode and fetch the destination operand: register or memory. */
a9945549 4469 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4470
4471done:
f09ed83e
AK		 4472 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4473 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4474
1d2887e2 4475 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4476}
4477
1cb3f3ae
XG		 4478bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4479{
4480 return ctxt->d & PageTable;
4481}
4482
3e2f65d5
GN		 4483static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4484{
3e2f65d5
GN		 4485 /* The second termination condition only applies for REPE
4486 * and REPNE. Test if the repeat string operation prefix is
4487 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4488 * corresponding termination condition according to:
4489 * - if REPE/REPZ and ZF = 0 then done
4490 * - if REPNE/REPNZ and ZF = 1 then done
4491 */
9dac77fa
AK		 4492 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4493 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4494 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4495 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4496 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4497 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4498 return true;
4499
4500 return false;
4501}
4502
cbe2c9d3
AK		 4503static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4504{
4505 bool fault = false;
4506
4507 ctxt->ops->get_fpu(ctxt);
4508 asm volatile("1: fwait \n\t"
4509 "2: \n\t"
4510 ".pushsection .fixup,\"ax\" \n\t"
4511 "3: \n\t"
4512 "movb $1, %[fault] \n\t"
4513 "jmp 2b \n\t"
4514 ".popsection \n\t"
4515 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4516 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4517 ctxt->ops->put_fpu(ctxt);
4518
4519 if (unlikely(fault))
4520 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4521
4522 return X86EMUL_CONTINUE;
4523}
4524
4525static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4526 struct operand *op)
4527{
4528 if (op->type == OP_MM)
4529 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4530}
4531
e28bbd44
AK		 4532static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4533{
4534 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4535 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4536 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4537 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4538 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4539 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4540 return X86EMUL_CONTINUE;
4541}
dd856efa 4542
7b105ca2 4543int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4544{
0225fb50 4545 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4546 int rc = X86EMUL_CONTINUE;
9dac77fa 4547 int saved_dst_type = ctxt->dst.type;
8b4caf66 4548
9dac77fa 4549 ctxt->mem_read.pos = 0;
310b5d30 4550
1146a78b
GN		 4551 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4552 (ctxt->d & Undefined)) {
35d3d4a1 4553 rc = emulate_ud(ctxt);
1161624f
GN		 4554 goto done;
4555 }
4556
d380a5e4 4557 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4558 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4559 rc = emulate_ud(ctxt);
d380a5e4
GN		 4560 goto done;
4561 }
4562
9dac77fa 4563 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4564 rc = emulate_ud(ctxt);
081bca0e
AK		 4565 goto done;
4566 }
4567
cbe2c9d3
AK		 4568 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4569 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4570 rc = emulate_ud(ctxt);
4571 goto done;
4572 }
4573
cbe2c9d3 4574 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4575 rc = emulate_nm(ctxt);
4576 goto done;
4577 }
4578
cbe2c9d3
AK		 4579 if (ctxt->d & Mmx) {
4580 rc = flush_pending_x87_faults(ctxt);
4581 if (rc != X86EMUL_CONTINUE)
4582 goto done;
4583 /*
4584 * Now that we know the fpu is exception safe, we can fetch
4585 * operands from it.
4586 */
4587 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4588 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4589 if (!(ctxt->d & Mov))
4590 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4591 }
4592
9dac77fa
AK		 4593 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4594 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4595 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4596 if (rc != X86EMUL_CONTINUE)
4597 goto done;
4598 }
4599
e92805ac 4600 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4601 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4602 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4603 goto done;
4604 }
4605
8ea7d6ae 4606 /* Instruction can only be executed in protected mode */
9d1b39a9 4607 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4608 rc = emulate_ud(ctxt);
4609 goto done;
4610 }
4611
d09beabd 4612 /* Do instruction specific permission checks */
9dac77fa
AK		 4613 if (ctxt->check_perm) {
4614 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4615 if (rc != X86EMUL_CONTINUE)
4616 goto done;
4617 }
4618
9dac77fa
AK		 4619 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4620 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4621 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4622 if (rc != X86EMUL_CONTINUE)
4623 goto done;
4624 }
4625
9dac77fa 4626 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4627 /* All REP prefixes have the same first termination condition */
dd856efa 4628 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4629 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4630 goto done;
4631 }
b9fa9d6b
AK		 4632 }
4633
9dac77fa
AK		 4634 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4635 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4636 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4637 if (rc != X86EMUL_CONTINUE)
8b4caf66 4638 goto done;
9dac77fa 4639 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4640 }
4641
9dac77fa
AK		 4642 if (ctxt->src2.type == OP_MEM) {
4643 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4644 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4645 if (rc != X86EMUL_CONTINUE)
4646 goto done;
4647 }
4648
9dac77fa 4649 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4650 goto special_insn;
4651
4652
9dac77fa 4653 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4654 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4655 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4656 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4657 if (rc != X86EMUL_CONTINUE)
4658 goto done;
038e51de 4659 }
9dac77fa 4660 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4661
018a98db
AK		 4662special_insn:
4663
9dac77fa
AK		 4664 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4665 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4666 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4667 if (rc != X86EMUL_CONTINUE)
4668 goto done;
4669 }
4670
9dac77fa 4671 if (ctxt->execute) {
e28bbd44
AK		 4672 if (ctxt->d & Fastop) {
4673 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4674 rc = fastop(ctxt, fop);
4675 if (rc != X86EMUL_CONTINUE)
4676 goto done;
4677 goto writeback;
4678 }
9dac77fa 4679 rc = ctxt->execute(ctxt);
ef65c889
AK		 4680 if (rc != X86EMUL_CONTINUE)
4681 goto done;
4682 goto writeback;
4683 }
4684
9dac77fa 4685 if (ctxt->twobyte)
6aa8b732
AK		 4686 goto twobyte_insn;
4687
9dac77fa 4688 switch (ctxt->b) {
6aa8b732 4689 case 0x63: /* movsxd */
8b4caf66 4690 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4691 goto cannot_emulate;
9dac77fa 4692 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4693 break;
b2833e3c 4694 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4695 if (test_cc(ctxt->b, ctxt->eflags))
4696 jmp_rel(ctxt, ctxt->src.val);
018a98db 4697 break;
7e0b54b1 4698 case 0x8d: /* lea r16/r32, m */
9dac77fa 4699 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4700 break;
3d9e77df 4701 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4702 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4703 break;
e4f973ae
TY		 4704 rc = em_xchg(ctxt);
4705 break;
e8b6fa70 4706 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4707 switch (ctxt->op_bytes) {
4708 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4709 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4710 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4711 }
4712 break;
6e154e56 4713 case 0xcc: /* int3 */
5c5df76b
TY		 4714 rc = emulate_int(ctxt, 3);
4715 break;
6e154e56 4716 case 0xcd: /* int n */
9dac77fa 4717 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4718 break;
4719 case 0xce: /* into */
5c5df76b
TY		 4720 if (ctxt->eflags & EFLG_OF)
4721 rc = emulate_int(ctxt, 4);
6e154e56 4722 break;
1a52e051 4723 case 0xe9: /* jmp rel */
db5b0762 4724 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4725 jmp_rel(ctxt, ctxt->src.val);
4726 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4727 break;
111de5d6 4728 case 0xf4: /* hlt */
6c3287f7 4729 ctxt->ops->halt(ctxt);
19fdfa0d 4730 break;
111de5d6
AK		 4731 case 0xf5: /* cmc */
4732 /* complement carry flag from eflags reg */
4733 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4734 break;
4735 case 0xf8: /* clc */
4736 ctxt->eflags &= ~EFLG_CF;
111de5d6 4737 break;
8744aa9a
MG		 4738 case 0xf9: /* stc */
4739 ctxt->eflags |= EFLG_CF;
4740 break;
fb4616f4
MG		 4741 case 0xfc: /* cld */
4742 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4743 break;
4744 case 0xfd: /* std */
4745 ctxt->eflags |= EFLG_DF;
fb4616f4 4746 break;
91269b8f
AK		 4747 default:
4748 goto cannot_emulate;
6aa8b732 4749 }
018a98db 4750
7d9ddaed
AK		 4751 if (rc != X86EMUL_CONTINUE)
4752 goto done;
4753
018a98db 4754writeback:
adddcecf 4755 rc = writeback(ctxt);
1b30eaa8 4756 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4757 goto done;
4758
5cd21917
GN		 4759 /*
4760 * restore dst type in case the decoding will be reused
4761 * (happens for string instruction )
4762 */
9dac77fa 4763 ctxt->dst.type = saved_dst_type;
5cd21917 4764
9dac77fa 4765 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4766 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4767
9dac77fa 4768 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4769 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4770
9dac77fa 4771 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4772 unsigned int count;
9dac77fa 4773 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4774 if ((ctxt->d & SrcMask) == SrcSI)
4775 count = ctxt->src.count;
4776 else
4777 count = ctxt->dst.count;
4778 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4779 -count);
3e2f65d5 4780
d2ddd1c4
GN		 4781 if (!string_insn_completed(ctxt)) {
4782 /*
4783 * Re-enter guest when pio read ahead buffer is empty
4784 * or, if it is not used, after each 1024 iteration.
4785 */
dd856efa 4786 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4787 (r->end == 0 || r->end != r->pos)) {
4788 /*
4789 * Reset read cache. Usually happens before
4790 * decode, but since instruction is restarted
4791 * we have to do it here.
4792 */
9dac77fa 4793 ctxt->mem_read.end = 0;
dd856efa 4794 writeback_registers(ctxt);
d2ddd1c4
GN		 4795 return EMULATION_RESTART;
4796 }
4797 goto done; /* skip rip writeback */
0fa6ccbd 4798 }
5cd21917 4799 }
d2ddd1c4 4800
9dac77fa 4801 ctxt->eip = ctxt->_eip;
018a98db
AK		 4802
4803done:
da9cb575
AK		 4804 if (rc == X86EMUL_PROPAGATE_FAULT)
4805 ctxt->have_exception = true;
775fde86
JR		 4806 if (rc == X86EMUL_INTERCEPTED)
4807 return EMULATION_INTERCEPTED;
4808
dd856efa
AK		 4809 if (rc == X86EMUL_CONTINUE)
4810 writeback_registers(ctxt);
4811
d2ddd1c4 4812 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4813
4814twobyte_insn:
9dac77fa 4815 switch (ctxt->b) {
018a98db 4816 case 0x09: /* wbinvd */
cfb22375 4817 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4818 break;
4819 case 0x08: /* invd */
018a98db
AK		 4820 case 0x0d: /* GrpP (prefetch) */
4821 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4822 break;
4823 case 0x20: /* mov cr, reg */
9dac77fa 4824 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4825 break;
6aa8b732 4826 case 0x21: /* mov from dr to reg */
9dac77fa 4827 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4828 break;
6aa8b732 4829 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4830 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4831 if (!test_cc(ctxt->b, ctxt->eflags))
4832 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4833 break;
b2833e3c 4834 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4835 if (test_cc(ctxt->b, ctxt->eflags))
4836 jmp_rel(ctxt, ctxt->src.val);
018a98db 4837 break;
ee45b58e 4838 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4839 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4840 break;
2a7c5b8b
GC		 4841 case 0xae: /* clflush */
4842 break;
6aa8b732 4843 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4844 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4845 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4846 : (u16) ctxt->src.val;
6aa8b732 4847 break;
6aa8b732 4848 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4849 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4850 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4851 (s16) ctxt->src.val;
6aa8b732 4852 break;
92f738a5 4853 case 0xc0 ... 0xc1: /* xadd */
158de57f 4854 fastop(ctxt, em_add);
92f738a5 4855 /* Write back the register source. */
9dac77fa
AK		 4856 ctxt->src.val = ctxt->dst.orig_val;
4857 write_register_operand(&ctxt->src);
92f738a5 4858 break;
a012e65a 4859 case 0xc3: /* movnti */
9dac77fa
AK		 4860 ctxt->dst.bytes = ctxt->op_bytes;
4861 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4862 (u64) ctxt->src.val;
a012e65a 4863 break;
91269b8f
AK		 4864 default:
4865 goto cannot_emulate;
6aa8b732 4866 }
7d9ddaed
AK		 4867
4868 if (rc != X86EMUL_CONTINUE)
4869 goto done;
4870
6aa8b732
AK		 4871 goto writeback;
4872
4873cannot_emulate:
a0c0ab2f 4874 return EMULATION_FAILED;
6aa8b732 4875}
dd856efa
AK		 4876
4877void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4878{
4879 invalidate_registers(ctxt);
4880}
4881
4882void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4883{
4884 writeback_registers(ctxt);
4885}
Linux kernel - Deliverables
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