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KVM: x86 emulator: fix group 11 decoding for reg != 0
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 57#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 58#define DstMask (7<<1)
6aa8b732 59/* Source operand type. */
9c9fddd0 60#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 74#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 75#define SrcMask (0xf<<4)
6aa8b732 76/* Generic ModRM decode. */
341de7e3 77#define ModRM (1<<8)
6aa8b732 78/* Destination is only written; never read. */
341de7e3
GN		 79#define Mov (1<<9)
80#define BitOp (1<<10)
81#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 82#define String (1<<12) /* String instruction (rep capable) */
83#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 84#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 86/* Misc flags */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
120df890 112 union {
ef65c889 113 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
6aa8b732 124/* EFLAGS bit definitions. */
d4c6a154
GN		 125#define EFLG_ID (1<<21)
126#define EFLG_VIP (1<<20)
127#define EFLG_VIF (1<<19)
128#define EFLG_AC (1<<18)
b1d86143
AP		 129#define EFLG_VM (1<<17)
130#define EFLG_RF (1<<16)
d4c6a154
GN		 131#define EFLG_IOPL (3<<12)
132#define EFLG_NT (1<<14)
6aa8b732
AK		 133#define EFLG_OF (1<<11)
134#define EFLG_DF (1<<10)
b1d86143 135#define EFLG_IF (1<<9)
d4c6a154 136#define EFLG_TF (1<<8)
6aa8b732
AK		 137#define EFLG_SF (1<<7)
138#define EFLG_ZF (1<<6)
139#define EFLG_AF (1<<4)
140#define EFLG_PF (1<<2)
141#define EFLG_CF (1<<0)
142
62bd430e
MG		 143#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144#define EFLG_RESERVED_ONE_MASK 2
145
6aa8b732
AK		 146/*
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
151 */
152
05b3e0c2 153#if defined(CONFIG_X86_64)
6aa8b732
AK		 154#define _LO32 "k" /* force 32-bit operand */
155#define _STK "%%rsp" /* stack pointer */
156#elif defined(__i386__)
157#define _LO32 "" /* force 32-bit operand */
158#define _STK "%%esp" /* stack pointer */
159#endif
160
161/*
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
164 */
165#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
166
167/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 168#define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
171 "push %"_tmp"; " \
172 "push %"_tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
175 "pushf; " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
179 "pop %"_tmp"; " \
180 "orl %"_LO32 _tmp",("_STK"); " \
181 "popf; " \
182 "pop %"_sav"; "
6aa8b732
AK		 183
184/* After executing instruction: write-back necessary bits in EFLAGS. */
185#define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
187 "pushf; " \
188 "pop %"_tmp"; " \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
191
dda96d8f
AK		 192#ifdef CONFIG_X86_64
193#define ON64(x) x
194#else
195#define ON64(x)
196#endif
197
b3b3d25a 198#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 199 do { \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
fb2c2641 204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 205 "=&r" (_tmp) \
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 207 } while (0)
6b7ad61f
AK		 208
209
6aa8b732
AK		 210/* Raw emulation: instruction has two explicit operands. */
211#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 212 do { \
213 unsigned long _tmp; \
214 \
215 switch ((_dst).bytes) { \
216 case 2: \
b3b3d25a 217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 218 break; \
219 case 4: \
b3b3d25a 220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 221 break; \
222 case 8: \
b3b3d25a 223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 224 break; \
225 } \
6aa8b732
AK		 226 } while (0)
227
228#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
229 do { \
6b7ad61f 230 unsigned long _tmp; \
d77c26fc 231 switch ((_dst).bytes) { \
6aa8b732 232 case 1: \
b3b3d25a 233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 234 break; \
235 default: \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
238 break; \
239 } \
240 } while (0)
241
242/* Source operand is byte-sized and may be restricted to just %cl. */
243#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
246
247/* Source operand is byte, word, long or quad sized. */
248#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
251
252/* Source operand is word, long or quad sized. */
253#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
256
d175226a
GT		 257/* Instruction has three operands and one operand is stored in ECX register */
258#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
259 do { \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
264 \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
271 ); \
272 \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
276 } while (0)
277
278#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
279 do { \
280 switch ((_dst).bytes) { \
281 case 2: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
284 break; \
285 case 4: \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
288 break; \
289 case 8: \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
292 break; \
293 } \
294 } while (0)
295
dda96d8f 296#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 297 do { \
298 unsigned long _tmp; \
299 \
dda96d8f
AK		 300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
305 "=&r" (_tmp) \
306 : "i" (EFLAGS_MASK)); \
307 } while (0)
308
309/* Instruction has only one explicit operand (no source operand). */
310#define emulate_1op(_op, _dst, _eflags) \
311 do { \
d77c26fc 312 switch ((_dst).bytes) { \
dda96d8f
AK		 313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 317 } \
318 } while (0)
319
3f9f53b0
MG		 320#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
321 do { \
322 unsigned long _tmp; \
323 \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
332 } while (0)
333
f6b3597b
AK		 334#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
335 do { \
336 unsigned long _tmp; \
337 \
338 __asm__ __volatile__ ( \
339 _PRE_EFLAGS("0", "5", "1") \
340 "1: \n\t" \
341 _op _suffix " %6; " \
342 "2: \n\t" \
343 _POST_EFLAGS("0", "5", "1") \
344 ".pushsection .fixup,\"ax\" \n\t" \
345 "3: movb $1, %4 \n\t" \
346 "jmp 2b \n\t" \
347 ".popsection \n\t" \
348 _ASM_EXTABLE(1b, 3b) \
349 : "=m" (_eflags), "=&r" (_tmp), \
350 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
351 : "i" (EFLAGS_MASK), "m" ((_src).val), \
352 "a" (_rax), "d" (_rdx)); \
353 } while (0)
354
3f9f53b0
MG		 355/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
356#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
357 do { \
358 switch((_src).bytes) { \
359 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
360 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
361 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
362 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
363 } \
364 } while (0)
365
f6b3597b
AK		 366#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
367 do { \
368 switch((_src).bytes) { \
369 case 1: \
370 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
371 _eflags, "b", _ex); \
372 break; \
373 case 2: \
374 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
375 _eflags, "w", _ex); \
376 break; \
377 case 4: \
378 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
379 _eflags, "l", _ex); \
380 break; \
381 case 8: ON64( \
382 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
383 _eflags, "q", _ex)); \
384 break; \
385 } \
386 } while (0)
387
6aa8b732
AK		 388/* Fetch next part of the instruction being emulated. */
389#define insn_fetch(_type, _size, _eip) \
390({ unsigned long _x; \
62266869 391 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 392 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 393 goto done; \
394 (_eip) += (_size); \
395 (_type)_x; \
396})
397
414e6277
GN		 398#define insn_fetch_arr(_arr, _size, _eip) \
399({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
400 if (rc != X86EMUL_CONTINUE) \
401 goto done; \
402 (_eip) += (_size); \
403})
404
ddcb2885
HH		 405static inline unsigned long ad_mask(struct decode_cache *c)
406{
407 return (1UL << (c->ad_bytes << 3)) - 1;
408}
409
6aa8b732 410/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 411static inline unsigned long
412address_mask(struct decode_cache *c, unsigned long reg)
413{
414 if (c->ad_bytes == sizeof(unsigned long))
415 return reg;
416 else
417 return reg & ad_mask(c);
418}
419
420static inline unsigned long
421register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
422{
423 return base + address_mask(c, reg);
424}
425
7a957275
HH		 426static inline void
427register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
428{
429 if (c->ad_bytes == sizeof(unsigned long))
430 *reg += inc;
431 else
432 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
433}
6aa8b732 434
7a957275
HH		 435static inline void jmp_rel(struct decode_cache *c, int rel)
436{
437 register_address_increment(c, &c->eip, rel);
438}
098c937b 439
7a5b56df
AK		 440static void set_seg_override(struct decode_cache *c, int seg)
441{
442 c->has_seg_override = true;
443 c->seg_override = seg;
444}
445
79168fd1
GN		 446static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
447 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 448{
449 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
450 return 0;
451
79168fd1 452 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 453}
454
455static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 456 struct x86_emulate_ops *ops,
7a5b56df
AK		 457 struct decode_cache *c)
458{
459 if (!c->has_seg_override)
460 return 0;
461
79168fd1 462 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 463}
464
79168fd1
GN		 465static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops)
7a5b56df 467{
79168fd1 468 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 469}
470
79168fd1
GN		 471static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
472 struct x86_emulate_ops *ops)
7a5b56df 473{
79168fd1 474 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 475}
476
54b8486f
GN		 477static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
478 u32 error, bool valid)
479{
480 ctxt->exception = vec;
481 ctxt->error_code = error;
482 ctxt->error_code_valid = valid;
54b8486f
GN		 483}
484
485static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
486{
487 emulate_exception(ctxt, GP_VECTOR, err, true);
488}
489
490static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
491 int err)
492{
493 ctxt->cr2 = addr;
494 emulate_exception(ctxt, PF_VECTOR, err, true);
495}
496
497static void emulate_ud(struct x86_emulate_ctxt *ctxt)
498{
499 emulate_exception(ctxt, UD_VECTOR, 0, false);
500}
501
502static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
503{
504 emulate_exception(ctxt, TS_VECTOR, err, true);
505}
506
34d1f490
AK		 507static int emulate_de(struct x86_emulate_ctxt *ctxt)
508{
509 emulate_exception(ctxt, DE_VECTOR, 0, false);
510 return X86EMUL_PROPAGATE_FAULT;
511}
512
62266869
AK		 513static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
514 struct x86_emulate_ops *ops,
2fb53ad8 515 unsigned long eip, u8 *dest)
62266869
AK		 516{
517 struct fetch_cache *fc = &ctxt->decode.fetch;
518 int rc;
2fb53ad8 519 int size, cur_size;
62266869 520
2fb53ad8
AK		 521 if (eip == fc->end) {
522 cur_size = fc->end - fc->start;
523 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
524 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
525 size, ctxt->vcpu, NULL);
3e2815e9 526 if (rc != X86EMUL_CONTINUE)
62266869 527 return rc;
2fb53ad8 528 fc->end += size;
62266869 529 }
2fb53ad8 530 *dest = fc->data[eip - fc->start];
3e2815e9 531 return X86EMUL_CONTINUE;
62266869
AK		 532}
533
534static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
535 struct x86_emulate_ops *ops,
536 unsigned long eip, void *dest, unsigned size)
537{
3e2815e9 538 int rc;
62266869 539
eb3c79e6 540 /* x86 instructions are limited to 15 bytes. */
063db061 541 if (eip + size - ctxt->eip > 15)
eb3c79e6 542 return X86EMUL_UNHANDLEABLE;
62266869
AK		 543 while (size--) {
544 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 545 if (rc != X86EMUL_CONTINUE)
62266869
AK		 546 return rc;
547 }
3e2815e9 548 return X86EMUL_CONTINUE;
62266869
AK		 549}
550
1e3c5cb0
RR		 551/*
552 * Given the 'reg' portion of a ModRM byte, and a register block, return a
553 * pointer into the block that addresses the relevant register.
554 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
555 */
556static void *decode_register(u8 modrm_reg, unsigned long *regs,
557 int highbyte_regs)
6aa8b732
AK		 558{
559 void *p;
560
561 p = &regs[modrm_reg];
562 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
563 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
564 return p;
565}
566
567static int read_descriptor(struct x86_emulate_ctxt *ctxt,
568 struct x86_emulate_ops *ops,
1a6440ae 569 ulong addr,
6aa8b732
AK		 570 u16 *size, unsigned long *address, int op_bytes)
571{
572 int rc;
573
574 if (op_bytes == 2)
575 op_bytes = 3;
576 *address = 0;
1a6440ae 577 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 578 if (rc != X86EMUL_CONTINUE)
6aa8b732 579 return rc;
1a6440ae 580 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 581 return rc;
582}
583
bbe9abbd
NK		 584static int test_cc(unsigned int condition, unsigned int flags)
585{
586 int rc = 0;
587
588 switch ((condition & 15) >> 1) {
589 case 0: /* o */
590 rc |= (flags & EFLG_OF);
591 break;
592 case 1: /* b/c/nae */
593 rc |= (flags & EFLG_CF);
594 break;
595 case 2: /* z/e */
596 rc |= (flags & EFLG_ZF);
597 break;
598 case 3: /* be/na */
599 rc |= (flags & (EFLG_CF|EFLG_ZF));
600 break;
601 case 4: /* s */
602 rc |= (flags & EFLG_SF);
603 break;
604 case 5: /* p/pe */
605 rc |= (flags & EFLG_PF);
606 break;
607 case 7: /* le/ng */
608 rc |= (flags & EFLG_ZF);
609 /* fall through */
610 case 6: /* l/nge */
611 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
612 break;
613 }
614
615 /* Odd condition identifiers (lsb == 1) have inverted sense. */
616 return (!!rc ^ (condition & 1));
617}
618
91ff3cb4
AK		 619static void fetch_register_operand(struct operand *op)
620{
621 switch (op->bytes) {
622 case 1:
623 op->val = *(u8 *)op->addr.reg;
624 break;
625 case 2:
626 op->val = *(u16 *)op->addr.reg;
627 break;
628 case 4:
629 op->val = *(u32 *)op->addr.reg;
630 break;
631 case 8:
632 op->val = *(u64 *)op->addr.reg;
633 break;
634 }
635}
636
3c118e24
AK		 637static void decode_register_operand(struct operand *op,
638 struct decode_cache *c,
3c118e24
AK		 639 int inhibit_bytereg)
640{
33615aa9 641 unsigned reg = c->modrm_reg;
9f1ef3f8 642 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 643
644 if (!(c->d & ModRM))
645 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 646 op->type = OP_REG;
647 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 648 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 649 op->bytes = 1;
650 } else {
1a6440ae 651 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 652 op->bytes = c->op_bytes;
3c118e24 653 }
91ff3cb4 654 fetch_register_operand(op);
3c118e24
AK		 655 op->orig_val = op->val;
656}
657
1c73ef66 658static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 659 struct x86_emulate_ops *ops,
660 struct operand *op)
1c73ef66
AK		 661{
662 struct decode_cache *c = &ctxt->decode;
663 u8 sib;
f5b4edcd 664 int index_reg = 0, base_reg = 0, scale;
3e2815e9 665 int rc = X86EMUL_CONTINUE;
2dbd0dd7 666 ulong modrm_ea = 0;
1c73ef66
AK		 667
668 if (c->rex_prefix) {
669 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
670 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
671 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
672 }
673
674 c->modrm = insn_fetch(u8, 1, c->eip);
675 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
676 c->modrm_reg |= (c->modrm & 0x38) >> 3;
677 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 678 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 679
680 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 681 op->type = OP_REG;
682 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
683 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 684 c->regs, c->d & ByteOp);
2dbd0dd7 685 fetch_register_operand(op);
1c73ef66
AK		 686 return rc;
687 }
688
2dbd0dd7
AK		 689 op->type = OP_MEM;
690
1c73ef66
AK		 691 if (c->ad_bytes == 2) {
692 unsigned bx = c->regs[VCPU_REGS_RBX];
693 unsigned bp = c->regs[VCPU_REGS_RBP];
694 unsigned si = c->regs[VCPU_REGS_RSI];
695 unsigned di = c->regs[VCPU_REGS_RDI];
696
697 /* 16-bit ModR/M decode. */
698 switch (c->modrm_mod) {
699 case 0:
700 if (c->modrm_rm == 6)
2dbd0dd7 701 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 702 break;
703 case 1:
2dbd0dd7 704 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 705 break;
706 case 2:
2dbd0dd7 707 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 708 break;
709 }
710 switch (c->modrm_rm) {
711 case 0:
2dbd0dd7 712 modrm_ea += bx + si;
1c73ef66
AK		 713 break;
714 case 1:
2dbd0dd7 715 modrm_ea += bx + di;
1c73ef66
AK		 716 break;
717 case 2:
2dbd0dd7 718 modrm_ea += bp + si;
1c73ef66
AK		 719 break;
720 case 3:
2dbd0dd7 721 modrm_ea += bp + di;
1c73ef66
AK		 722 break;
723 case 4:
2dbd0dd7 724 modrm_ea += si;
1c73ef66
AK		 725 break;
726 case 5:
2dbd0dd7 727 modrm_ea += di;
1c73ef66
AK		 728 break;
729 case 6:
730 if (c->modrm_mod != 0)
2dbd0dd7 731 modrm_ea += bp;
1c73ef66
AK		 732 break;
733 case 7:
2dbd0dd7 734 modrm_ea += bx;
1c73ef66
AK		 735 break;
736 }
737 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
738 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 739 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 740 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 741 } else {
742 /* 32/64-bit ModR/M decode. */
84411d85 743 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 744 sib = insn_fetch(u8, 1, c->eip);
745 index_reg |= (sib >> 3) & 7;
746 base_reg |= sib & 7;
747 scale = sib >> 6;
748
dc71d0f1 749 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 750 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 751 else
2dbd0dd7 752 modrm_ea += c->regs[base_reg];
dc71d0f1 753 if (index_reg != 4)
2dbd0dd7 754 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 755 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
756 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 757 c->rip_relative = 1;
84411d85 758 } else
2dbd0dd7 759 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 760 switch (c->modrm_mod) {
761 case 0:
762 if (c->modrm_rm == 5)
2dbd0dd7 763 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 764 break;
765 case 1:
2dbd0dd7 766 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 767 break;
768 case 2:
2dbd0dd7 769 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 770 break;
771 }
772 }
2dbd0dd7 773 op->addr.mem = modrm_ea;
1c73ef66
AK		 774done:
775 return rc;
776}
777
778static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 779 struct x86_emulate_ops *ops,
780 struct operand *op)
1c73ef66
AK		 781{
782 struct decode_cache *c = &ctxt->decode;
3e2815e9 783 int rc = X86EMUL_CONTINUE;
1c73ef66 784
2dbd0dd7 785 op->type = OP_MEM;
1c73ef66
AK		 786 switch (c->ad_bytes) {
787 case 2:
2dbd0dd7 788 op->addr.mem = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 789 break;
790 case 4:
2dbd0dd7 791 op->addr.mem = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 792 break;
793 case 8:
2dbd0dd7 794 op->addr.mem = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 795 break;
796 }
797done:
798 return rc;
799}
800
35c843c4
WY		 801static void fetch_bit_operand(struct decode_cache *c)
802{
803 long sv, mask;
804
3885f18f 805 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 806 mask = ~(c->dst.bytes * 8 - 1);
807
808 if (c->src.bytes == 2)
809 sv = (s16)c->src.val & (s16)mask;
810 else if (c->src.bytes == 4)
811 sv = (s32)c->src.val & (s32)mask;
812
813 c->dst.addr.mem += (sv >> 3);
814 }
ba7ff2b7
WY		 815
816 /* only subword offset */
817 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 818}
819
dde7e6d1
AK		 820static int read_emulated(struct x86_emulate_ctxt *ctxt,
821 struct x86_emulate_ops *ops,
822 unsigned long addr, void *dest, unsigned size)
6aa8b732 823{
dde7e6d1
AK		 824 int rc;
825 struct read_cache *mc = &ctxt->decode.mem_read;
826 u32 err;
6aa8b732 827
dde7e6d1
AK		 828 while (size) {
829 int n = min(size, 8u);
830 size -= n;
831 if (mc->pos < mc->end)
832 goto read_cached;
5cd21917 833
dde7e6d1
AK		 834 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
835 ctxt->vcpu);
836 if (rc == X86EMUL_PROPAGATE_FAULT)
837 emulate_pf(ctxt, addr, err);
838 if (rc != X86EMUL_CONTINUE)
839 return rc;
840 mc->end += n;
6aa8b732 841
dde7e6d1
AK		 842 read_cached:
843 memcpy(dest, mc->data + mc->pos, n);
844 mc->pos += n;
845 dest += n;
846 addr += n;
6aa8b732 847 }
dde7e6d1
AK		 848 return X86EMUL_CONTINUE;
849}
6aa8b732 850
dde7e6d1
AK		 851static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
852 struct x86_emulate_ops *ops,
853 unsigned int size, unsigned short port,
854 void *dest)
855{
856 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 857
dde7e6d1
AK		 858 if (rc->pos == rc->end) { /* refill pio read ahead */
859 struct decode_cache *c = &ctxt->decode;
860 unsigned int in_page, n;
861 unsigned int count = c->rep_prefix ?
862 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
863 in_page = (ctxt->eflags & EFLG_DF) ?
864 offset_in_page(c->regs[VCPU_REGS_RDI]) :
865 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
866 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
867 count);
868 if (n == 0)
869 n = 1;
870 rc->pos = rc->end = 0;
871 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
872 return 0;
873 rc->end = n * size;
6aa8b732
AK		 874 }
875
dde7e6d1
AK		 876 memcpy(dest, rc->data + rc->pos, size);
877 rc->pos += size;
878 return 1;
879}
6aa8b732 880
dde7e6d1
AK		 881static u32 desc_limit_scaled(struct desc_struct *desc)
882{
883 u32 limit = get_desc_limit(desc);
6aa8b732 884
dde7e6d1
AK		 885 return desc->g ? (limit << 12) | 0xfff : limit;
886}
6aa8b732 887
dde7e6d1
AK		 888static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
889 struct x86_emulate_ops *ops,
890 u16 selector, struct desc_ptr *dt)
891{
892 if (selector & 1 << 2) {
893 struct desc_struct desc;
894 memset (dt, 0, sizeof *dt);
895 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
896 return;
e09d082c 897
dde7e6d1
AK		 898 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
899 dt->address = get_desc_base(&desc);
900 } else
901 ops->get_gdt(dt, ctxt->vcpu);
902}
120df890 903
dde7e6d1
AK		 904/* allowed just for 8 bytes segments */
905static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
906 struct x86_emulate_ops *ops,
907 u16 selector, struct desc_struct *desc)
908{
909 struct desc_ptr dt;
910 u16 index = selector >> 3;
911 int ret;
912 u32 err;
913 ulong addr;
120df890 914
dde7e6d1 915 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 916
dde7e6d1
AK		 917 if (dt.size < index * 8 + 7) {
918 emulate_gp(ctxt, selector & 0xfffc);
919 return X86EMUL_PROPAGATE_FAULT;
e09d082c 920 }
dde7e6d1
AK		 921 addr = dt.address + index * 8;
922 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
923 if (ret == X86EMUL_PROPAGATE_FAULT)
924 emulate_pf(ctxt, addr, err);
e09d082c 925
dde7e6d1
AK		 926 return ret;
927}
ef65c889 928
dde7e6d1
AK		 929/* allowed just for 8 bytes segments */
930static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
931 struct x86_emulate_ops *ops,
932 u16 selector, struct desc_struct *desc)
933{
934 struct desc_ptr dt;
935 u16 index = selector >> 3;
936 u32 err;
937 ulong addr;
938 int ret;
6aa8b732 939
dde7e6d1 940 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 941
dde7e6d1
AK		 942 if (dt.size < index * 8 + 7) {
943 emulate_gp(ctxt, selector & 0xfffc);
944 return X86EMUL_PROPAGATE_FAULT;
945 }
6aa8b732 946
dde7e6d1
AK		 947 addr = dt.address + index * 8;
948 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
949 if (ret == X86EMUL_PROPAGATE_FAULT)
950 emulate_pf(ctxt, addr, err);
c7e75a3d 951
dde7e6d1
AK		 952 return ret;
953}
c7e75a3d 954
dde7e6d1
AK		 955static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
956 struct x86_emulate_ops *ops,
957 u16 selector, int seg)
958{
959 struct desc_struct seg_desc;
960 u8 dpl, rpl, cpl;
961 unsigned err_vec = GP_VECTOR;
962 u32 err_code = 0;
963 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
964 int ret;
69f55cb1 965
dde7e6d1 966 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 967
dde7e6d1
AK		 968 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
969 || ctxt->mode == X86EMUL_MODE_REAL) {
970 /* set real mode segment descriptor */
971 set_desc_base(&seg_desc, selector << 4);
972 set_desc_limit(&seg_desc, 0xffff);
973 seg_desc.type = 3;
974 seg_desc.p = 1;
975 seg_desc.s = 1;
976 goto load;
977 }
978
979 /* NULL selector is not valid for TR, CS and SS */
980 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
981 && null_selector)
982 goto exception;
983
984 /* TR should be in GDT only */
985 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
986 goto exception;
987
988 if (null_selector) /* for NULL selector skip all following checks */
989 goto load;
990
991 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
992 if (ret != X86EMUL_CONTINUE)
993 return ret;
994
995 err_code = selector & 0xfffc;
996 err_vec = GP_VECTOR;
997
998 /* can't load system descriptor into segment selecor */
999 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1000 goto exception;
1001
1002 if (!seg_desc.p) {
1003 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1004 goto exception;
1005 }
1006
1007 rpl = selector & 3;
1008 dpl = seg_desc.dpl;
1009 cpl = ops->cpl(ctxt->vcpu);
1010
1011 switch (seg) {
1012 case VCPU_SREG_SS:
1013 /*
1014 * segment is not a writable data segment or segment
1015 * selector's RPL != CPL or segment selector's RPL != CPL
1016 */
1017 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1018 goto exception;
6aa8b732 1019 break;
dde7e6d1
AK		 1020 case VCPU_SREG_CS:
1021 if (!(seg_desc.type & 8))
1022 goto exception;
1023
1024 if (seg_desc.type & 4) {
1025 /* conforming */
1026 if (dpl > cpl)
1027 goto exception;
1028 } else {
1029 /* nonconforming */
1030 if (rpl > cpl || dpl != cpl)
1031 goto exception;
1032 }
1033 /* CS(RPL) <- CPL */
1034 selector = (selector & 0xfffc) | cpl;
6aa8b732 1035 break;
dde7e6d1
AK		 1036 case VCPU_SREG_TR:
1037 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1038 goto exception;
1039 break;
1040 case VCPU_SREG_LDTR:
1041 if (seg_desc.s || seg_desc.type != 2)
1042 goto exception;
1043 break;
1044 default: /* DS, ES, FS, or GS */
4e62417b 1045 /*
dde7e6d1
AK		 1046 * segment is not a data or readable code segment or
1047 * ((segment is a data or nonconforming code segment)
1048 * and (both RPL and CPL > DPL))
4e62417b 1049 */
dde7e6d1
AK		 1050 if ((seg_desc.type & 0xa) == 0x8 ||
1051 (((seg_desc.type & 0xc) != 0xc) &&
1052 (rpl > dpl && cpl > dpl)))
1053 goto exception;
6aa8b732 1054 break;
dde7e6d1
AK		 1055 }
1056
1057 if (seg_desc.s) {
1058 /* mark segment as accessed */
1059 seg_desc.type |= 1;
1060 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1061 if (ret != X86EMUL_CONTINUE)
1062 return ret;
1063 }
1064load:
1065 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1066 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1067 return X86EMUL_CONTINUE;
1068exception:
1069 emulate_exception(ctxt, err_vec, err_code, true);
1070 return X86EMUL_PROPAGATE_FAULT;
1071}
1072
31be40b3
WY		 1073static void write_register_operand(struct operand *op)
1074{
1075 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1076 switch (op->bytes) {
1077 case 1:
1078 *(u8 *)op->addr.reg = (u8)op->val;
1079 break;
1080 case 2:
1081 *(u16 *)op->addr.reg = (u16)op->val;
1082 break;
1083 case 4:
1084 *op->addr.reg = (u32)op->val;
1085 break; /* 64b: zero-extend */
1086 case 8:
1087 *op->addr.reg = op->val;
1088 break;
1089 }
1090}
1091
dde7e6d1
AK		 1092static inline int writeback(struct x86_emulate_ctxt *ctxt,
1093 struct x86_emulate_ops *ops)
1094{
1095 int rc;
1096 struct decode_cache *c = &ctxt->decode;
1097 u32 err;
1098
1099 switch (c->dst.type) {
1100 case OP_REG:
31be40b3 1101 write_register_operand(&c->dst);
6aa8b732 1102 break;
dde7e6d1
AK		 1103 case OP_MEM:
1104 if (c->lock_prefix)
1105 rc = ops->cmpxchg_emulated(
1a6440ae 1106 c->dst.addr.mem,
dde7e6d1
AK		 1107 &c->dst.orig_val,
1108 &c->dst.val,
1109 c->dst.bytes,
1110 &err,
1111 ctxt->vcpu);
341de7e3 1112 else
dde7e6d1 1113 rc = ops->write_emulated(
1a6440ae 1114 c->dst.addr.mem,
dde7e6d1
AK		 1115 &c->dst.val,
1116 c->dst.bytes,
1117 &err,
1118 ctxt->vcpu);
1119 if (rc == X86EMUL_PROPAGATE_FAULT)
1a6440ae 1120 emulate_pf(ctxt, c->dst.addr.mem, err);
dde7e6d1
AK		 1121 if (rc != X86EMUL_CONTINUE)
1122 return rc;
a682e354 1123 break;
dde7e6d1
AK		 1124 case OP_NONE:
1125 /* no writeback */
414e6277 1126 break;
dde7e6d1 1127 default:
414e6277 1128 break;
6aa8b732 1129 }
dde7e6d1
AK		 1130 return X86EMUL_CONTINUE;
1131}
6aa8b732 1132
dde7e6d1
AK		 1133static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1134 struct x86_emulate_ops *ops)
1135{
1136 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1137
dde7e6d1
AK		 1138 c->dst.type = OP_MEM;
1139 c->dst.bytes = c->op_bytes;
1140 c->dst.val = c->src.val;
1141 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1142 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1143 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1144}
69f55cb1 1145
dde7e6d1
AK		 1146static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1147 struct x86_emulate_ops *ops,
1148 void *dest, int len)
1149{
1150 struct decode_cache *c = &ctxt->decode;
1151 int rc;
8b4caf66 1152
dde7e6d1
AK		 1153 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1154 c->regs[VCPU_REGS_RSP]),
1155 dest, len);
1156 if (rc != X86EMUL_CONTINUE)
1157 return rc;
1158
1159 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1160 return rc;
8b4caf66
LV		 1161}
1162
dde7e6d1
AK		 1163static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1164 struct x86_emulate_ops *ops,
1165 void *dest, int len)
9de41573
GN		 1166{
1167 int rc;
dde7e6d1
AK		 1168 unsigned long val, change_mask;
1169 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1170 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1171
dde7e6d1
AK		 1172 rc = emulate_pop(ctxt, ops, &val, len);
1173 if (rc != X86EMUL_CONTINUE)
1174 return rc;
9de41573 1175
dde7e6d1
AK		 1176 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1177 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1178
dde7e6d1
AK		 1179 switch(ctxt->mode) {
1180 case X86EMUL_MODE_PROT64:
1181 case X86EMUL_MODE_PROT32:
1182 case X86EMUL_MODE_PROT16:
1183 if (cpl == 0)
1184 change_mask |= EFLG_IOPL;
1185 if (cpl <= iopl)
1186 change_mask |= EFLG_IF;
1187 break;
1188 case X86EMUL_MODE_VM86:
1189 if (iopl < 3) {
1190 emulate_gp(ctxt, 0);
1191 return X86EMUL_PROPAGATE_FAULT;
1192 }
1193 change_mask |= EFLG_IF;
1194 break;
1195 default: /* real mode */
1196 change_mask |= (EFLG_IOPL | EFLG_IF);
1197 break;
9de41573 1198 }
dde7e6d1
AK		 1199
1200 *(unsigned long *)dest =
1201 (ctxt->eflags & ~change_mask) | (val & change_mask);
1202
1203 return rc;
9de41573
GN		 1204}
1205
dde7e6d1
AK		 1206static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1207 struct x86_emulate_ops *ops, int seg)
7b262e90 1208{
dde7e6d1 1209 struct decode_cache *c = &ctxt->decode;
7b262e90 1210
dde7e6d1 1211 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1212
dde7e6d1 1213 emulate_push(ctxt, ops);
7b262e90
GN		 1214}
1215
dde7e6d1
AK		 1216static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1217 struct x86_emulate_ops *ops, int seg)
38ba30ba 1218{
dde7e6d1
AK		 1219 struct decode_cache *c = &ctxt->decode;
1220 unsigned long selector;
1221 int rc;
38ba30ba 1222
dde7e6d1
AK		 1223 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1224 if (rc != X86EMUL_CONTINUE)
1225 return rc;
1226
1227 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1228 return rc;
38ba30ba
GN		 1229}
1230
dde7e6d1
AK		 1231static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1232 struct x86_emulate_ops *ops)
38ba30ba 1233{
dde7e6d1
AK		 1234 struct decode_cache *c = &ctxt->decode;
1235 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1236 int rc = X86EMUL_CONTINUE;
1237 int reg = VCPU_REGS_RAX;
38ba30ba 1238
dde7e6d1
AK		 1239 while (reg <= VCPU_REGS_RDI) {
1240 (reg == VCPU_REGS_RSP) ?
1241 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1242
dde7e6d1 1243 emulate_push(ctxt, ops);
38ba30ba 1244
dde7e6d1
AK		 1245 rc = writeback(ctxt, ops);
1246 if (rc != X86EMUL_CONTINUE)
1247 return rc;
38ba30ba 1248
dde7e6d1 1249 ++reg;
38ba30ba 1250 }
38ba30ba 1251
dde7e6d1
AK		 1252 /* Disable writeback. */
1253 c->dst.type = OP_NONE;
1254
1255 return rc;
38ba30ba
GN		 1256}
1257
dde7e6d1
AK		 1258static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1259 struct x86_emulate_ops *ops)
38ba30ba 1260{
dde7e6d1
AK		 1261 struct decode_cache *c = &ctxt->decode;
1262 int rc = X86EMUL_CONTINUE;
1263 int reg = VCPU_REGS_RDI;
38ba30ba 1264
dde7e6d1
AK		 1265 while (reg >= VCPU_REGS_RAX) {
1266 if (reg == VCPU_REGS_RSP) {
1267 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1268 c->op_bytes);
1269 --reg;
1270 }
38ba30ba 1271
dde7e6d1
AK		 1272 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1273 if (rc != X86EMUL_CONTINUE)
1274 break;
1275 --reg;
38ba30ba 1276 }
dde7e6d1 1277 return rc;
38ba30ba
GN		 1278}
1279
6e154e56
MG		 1280int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1281 struct x86_emulate_ops *ops, int irq)
1282{
1283 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1284 int rc;
6e154e56
MG		 1285 struct desc_ptr dt;
1286 gva_t cs_addr;
1287 gva_t eip_addr;
1288 u16 cs, eip;
1289 u32 err;
1290
1291 /* TODO: Add limit checks */
1292 c->src.val = ctxt->eflags;
1293 emulate_push(ctxt, ops);
5c56e1cf
AK		 1294 rc = writeback(ctxt, ops);
1295 if (rc != X86EMUL_CONTINUE)
1296 return rc;
6e154e56
MG		 1297
1298 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1299
1300 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1301 emulate_push(ctxt, ops);
5c56e1cf
AK		 1302 rc = writeback(ctxt, ops);
1303 if (rc != X86EMUL_CONTINUE)
1304 return rc;
6e154e56
MG		 1305
1306 c->src.val = c->eip;
1307 emulate_push(ctxt, ops);
5c56e1cf
AK		 1308 rc = writeback(ctxt, ops);
1309 if (rc != X86EMUL_CONTINUE)
1310 return rc;
1311
1312 c->dst.type = OP_NONE;
6e154e56
MG		 1313
1314 ops->get_idt(&dt, ctxt->vcpu);
1315
1316 eip_addr = dt.address + (irq << 2);
1317 cs_addr = dt.address + (irq << 2) + 2;
1318
1319 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1324 if (rc != X86EMUL_CONTINUE)
1325 return rc;
1326
1327 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1328 if (rc != X86EMUL_CONTINUE)
1329 return rc;
1330
1331 c->eip = eip;
1332
1333 return rc;
1334}
1335
1336static int emulate_int(struct x86_emulate_ctxt *ctxt,
1337 struct x86_emulate_ops *ops, int irq)
1338{
1339 switch(ctxt->mode) {
1340 case X86EMUL_MODE_REAL:
1341 return emulate_int_real(ctxt, ops, irq);
1342 case X86EMUL_MODE_VM86:
1343 case X86EMUL_MODE_PROT16:
1344 case X86EMUL_MODE_PROT32:
1345 case X86EMUL_MODE_PROT64:
1346 default:
1347 /* Protected mode interrupts unimplemented yet */
1348 return X86EMUL_UNHANDLEABLE;
1349 }
1350}
1351
dde7e6d1
AK		 1352static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1353 struct x86_emulate_ops *ops)
38ba30ba 1354{
dde7e6d1
AK		 1355 struct decode_cache *c = &ctxt->decode;
1356 int rc = X86EMUL_CONTINUE;
1357 unsigned long temp_eip = 0;
1358 unsigned long temp_eflags = 0;
1359 unsigned long cs = 0;
1360 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1361 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1362 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1363 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1364
dde7e6d1 1365 /* TODO: Add stack limit check */
38ba30ba 1366
dde7e6d1 1367 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1368
dde7e6d1
AK		 1369 if (rc != X86EMUL_CONTINUE)
1370 return rc;
38ba30ba 1371
dde7e6d1
AK		 1372 if (temp_eip & ~0xffff) {
1373 emulate_gp(ctxt, 0);
1374 return X86EMUL_PROPAGATE_FAULT;
1375 }
38ba30ba 1376
dde7e6d1 1377 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1378
dde7e6d1
AK		 1379 if (rc != X86EMUL_CONTINUE)
1380 return rc;
38ba30ba 1381
dde7e6d1 1382 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1383
dde7e6d1
AK		 1384 if (rc != X86EMUL_CONTINUE)
1385 return rc;
38ba30ba 1386
dde7e6d1 1387 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1388
dde7e6d1
AK		 1389 if (rc != X86EMUL_CONTINUE)
1390 return rc;
38ba30ba 1391
dde7e6d1 1392 c->eip = temp_eip;
38ba30ba 1393
38ba30ba 1394
dde7e6d1
AK		 1395 if (c->op_bytes == 4)
1396 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1397 else if (c->op_bytes == 2) {
1398 ctxt->eflags &= ~0xffff;
1399 ctxt->eflags |= temp_eflags;
38ba30ba 1400 }
dde7e6d1
AK		 1401
1402 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1403 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1404
1405 return rc;
38ba30ba
GN		 1406}
1407
dde7e6d1
AK		 1408static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1409 struct x86_emulate_ops* ops)
c37eda13 1410{
dde7e6d1
AK		 1411 switch(ctxt->mode) {
1412 case X86EMUL_MODE_REAL:
1413 return emulate_iret_real(ctxt, ops);
1414 case X86EMUL_MODE_VM86:
1415 case X86EMUL_MODE_PROT16:
1416 case X86EMUL_MODE_PROT32:
1417 case X86EMUL_MODE_PROT64:
c37eda13 1418 default:
dde7e6d1
AK		 1419 /* iret from protected mode unimplemented yet */
1420 return X86EMUL_UNHANDLEABLE;
c37eda13 1421 }
c37eda13
WY		 1422}
1423
dde7e6d1 1424static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1425 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1426{
1427 struct decode_cache *c = &ctxt->decode;
1428
dde7e6d1 1429 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1430}
1431
dde7e6d1 1432static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1433{
05f086f8 1434 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1435 switch (c->modrm_reg) {
1436 case 0: /* rol */
05f086f8 1437 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1438 break;
1439 case 1: /* ror */
05f086f8 1440 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1441 break;
1442 case 2: /* rcl */
05f086f8 1443 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1444 break;
1445 case 3: /* rcr */
05f086f8 1446 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1447 break;
1448 case 4: /* sal/shl */
1449 case 6: /* sal/shl */
05f086f8 1450 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1451 break;
1452 case 5: /* shr */
05f086f8 1453 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1454 break;
1455 case 7: /* sar */
05f086f8 1456 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1457 break;
1458 }
1459}
1460
1461static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1462 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1463{
1464 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1465 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1466 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1467 u8 de = 0;
8cdbd2c9
LV		 1468
1469 switch (c->modrm_reg) {
1470 case 0 ... 1: /* test */
05f086f8 1471 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1472 break;
1473 case 2: /* not */
1474 c->dst.val = ~c->dst.val;
1475 break;
1476 case 3: /* neg */
05f086f8 1477 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1478 break;
3f9f53b0
MG		 1479 case 4: /* mul */
1480 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1481 break;
1482 case 5: /* imul */
1483 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1484 break;
1485 case 6: /* div */
34d1f490
AK		 1486 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1487 ctxt->eflags, de);
3f9f53b0
MG		 1488 break;
1489 case 7: /* idiv */
34d1f490
AK		 1490 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1491 ctxt->eflags, de);
3f9f53b0 1492 break;
8cdbd2c9 1493 default:
8c5eee30 1494 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1495 }
34d1f490
AK		 1496 if (de)
1497 return emulate_de(ctxt);
8c5eee30 1498 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1499}
1500
1501static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1502 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1503{
1504 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1505
1506 switch (c->modrm_reg) {
1507 case 0: /* inc */
05f086f8 1508 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1509 break;
1510 case 1: /* dec */
05f086f8 1511 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1512 break;
d19292e4
MG		 1513 case 2: /* call near abs */ {
1514 long int old_eip;
1515 old_eip = c->eip;
1516 c->eip = c->src.val;
1517 c->src.val = old_eip;
79168fd1 1518 emulate_push(ctxt, ops);
d19292e4
MG		 1519 break;
1520 }
8cdbd2c9 1521 case 4: /* jmp abs */
fd60754e 1522 c->eip = c->src.val;
8cdbd2c9
LV		 1523 break;
1524 case 6: /* push */
79168fd1 1525 emulate_push(ctxt, ops);
8cdbd2c9 1526 break;
8cdbd2c9 1527 }
1b30eaa8 1528 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1529}
1530
1531static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1532 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1533{
1534 struct decode_cache *c = &ctxt->decode;
16518d5a 1535 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1536
1537 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1538 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1539 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1540 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1541 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1542 } else {
16518d5a
AK		 1543 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1544 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1545
05f086f8 1546 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1547 }
1b30eaa8 1548 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1549}
1550
a77ab5ea
AK		 1551static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1552 struct x86_emulate_ops *ops)
1553{
1554 struct decode_cache *c = &ctxt->decode;
1555 int rc;
1556 unsigned long cs;
1557
1558 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1559 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1560 return rc;
1561 if (c->op_bytes == 4)
1562 c->eip = (u32)c->eip;
1563 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1564 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1565 return rc;
2e873022 1566 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1567 return rc;
1568}
1569
09b5f4d3
WY		 1570static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1571 struct x86_emulate_ops *ops, int seg)
1572{
1573 struct decode_cache *c = &ctxt->decode;
1574 unsigned short sel;
1575 int rc;
1576
1577 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1578
1579 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1580 if (rc != X86EMUL_CONTINUE)
1581 return rc;
1582
1583 c->dst.val = c->src.val;
1584 return rc;
1585}
1586
e66bb2cc
AP		 1587static inline void
1588setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1589 struct x86_emulate_ops *ops, struct desc_struct *cs,
1590 struct desc_struct *ss)
e66bb2cc 1591{
79168fd1
GN		 1592 memset(cs, 0, sizeof(struct desc_struct));
1593 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1594 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1595
1596 cs->l = 0; /* will be adjusted later */
79168fd1 1597 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1598 cs->g = 1; /* 4kb granularity */
79168fd1 1599 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1600 cs->type = 0x0b; /* Read, Execute, Accessed */
1601 cs->s = 1;
1602 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1603 cs->p = 1;
1604 cs->d = 1;
e66bb2cc 1605
79168fd1
GN		 1606 set_desc_base(ss, 0); /* flat segment */
1607 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1608 ss->g = 1; /* 4kb granularity */
1609 ss->s = 1;
1610 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1611 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1612 ss->dpl = 0;
79168fd1 1613 ss->p = 1;
e66bb2cc
AP		 1614}
1615
1616static int
3fb1b5db 1617emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1618{
1619 struct decode_cache *c = &ctxt->decode;
79168fd1 1620 struct desc_struct cs, ss;
e66bb2cc 1621 u64 msr_data;
79168fd1 1622 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1623
1624 /* syscall is not available in real mode */
2e901c4c
GN		 1625 if (ctxt->mode == X86EMUL_MODE_REAL ||
1626 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1627 emulate_ud(ctxt);
2e901c4c
GN		 1628 return X86EMUL_PROPAGATE_FAULT;
1629 }
e66bb2cc 1630
79168fd1 1631 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1632
3fb1b5db 1633 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1634 msr_data >>= 32;
79168fd1
GN		 1635 cs_sel = (u16)(msr_data & 0xfffc);
1636 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1637
1638 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1639 cs.d = 0;
e66bb2cc
AP		 1640 cs.l = 1;
1641 }
79168fd1
GN		 1642 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1643 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1644 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1645 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1646
1647 c->regs[VCPU_REGS_RCX] = c->eip;
1648 if (is_long_mode(ctxt->vcpu)) {
1649#ifdef CONFIG_X86_64
1650 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1651
3fb1b5db
GN		 1652 ops->get_msr(ctxt->vcpu,
1653 ctxt->mode == X86EMUL_MODE_PROT64 ?
1654 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1655 c->eip = msr_data;
1656
3fb1b5db 1657 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1658 ctxt->eflags &= ~(msr_data | EFLG_RF);
1659#endif
1660 } else {
1661 /* legacy mode */
3fb1b5db 1662 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1663 c->eip = (u32)msr_data;
1664
1665 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1666 }
1667
e54cfa97 1668 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1669}
1670
8c604352 1671static int
3fb1b5db 1672emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1673{
1674 struct decode_cache *c = &ctxt->decode;
79168fd1 1675 struct desc_struct cs, ss;
8c604352 1676 u64 msr_data;
79168fd1 1677 u16 cs_sel, ss_sel;
8c604352 1678
a0044755
GN		 1679 /* inject #GP if in real mode */
1680 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1681 emulate_gp(ctxt, 0);
2e901c4c 1682 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1683 }
1684
1685 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1686 * Therefore, we inject an #UD.
1687 */
2e901c4c 1688 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1689 emulate_ud(ctxt);
2e901c4c
GN		 1690 return X86EMUL_PROPAGATE_FAULT;
1691 }
8c604352 1692
79168fd1 1693 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1694
3fb1b5db 1695 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1696 switch (ctxt->mode) {
1697 case X86EMUL_MODE_PROT32:
1698 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1699 emulate_gp(ctxt, 0);
e54cfa97 1700 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1701 }
1702 break;
1703 case X86EMUL_MODE_PROT64:
1704 if (msr_data == 0x0) {
54b8486f 1705 emulate_gp(ctxt, 0);
e54cfa97 1706 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1707 }
1708 break;
1709 }
1710
1711 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1712 cs_sel = (u16)msr_data;
1713 cs_sel &= ~SELECTOR_RPL_MASK;
1714 ss_sel = cs_sel + 8;
1715 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1716 if (ctxt->mode == X86EMUL_MODE_PROT64
1717 || is_long_mode(ctxt->vcpu)) {
79168fd1 1718 cs.d = 0;
8c604352
AP		 1719 cs.l = 1;
1720 }
1721
79168fd1
GN		 1722 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1723 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1724 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1725 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1726
3fb1b5db 1727 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1728 c->eip = msr_data;
1729
3fb1b5db 1730 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1731 c->regs[VCPU_REGS_RSP] = msr_data;
1732
e54cfa97 1733 return X86EMUL_CONTINUE;
8c604352
AP		 1734}
1735
4668f050 1736static int
3fb1b5db 1737emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1738{
1739 struct decode_cache *c = &ctxt->decode;
79168fd1 1740 struct desc_struct cs, ss;
4668f050
AP		 1741 u64 msr_data;
1742 int usermode;
79168fd1 1743 u16 cs_sel, ss_sel;
4668f050 1744
a0044755
GN		 1745 /* inject #GP if in real mode or Virtual 8086 mode */
1746 if (ctxt->mode == X86EMUL_MODE_REAL ||
1747 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1748 emulate_gp(ctxt, 0);
2e901c4c 1749 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1750 }
1751
79168fd1 1752 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1753
1754 if ((c->rex_prefix & 0x8) != 0x0)
1755 usermode = X86EMUL_MODE_PROT64;
1756 else
1757 usermode = X86EMUL_MODE_PROT32;
1758
1759 cs.dpl = 3;
1760 ss.dpl = 3;
3fb1b5db 1761 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1762 switch (usermode) {
1763 case X86EMUL_MODE_PROT32:
79168fd1 1764 cs_sel = (u16)(msr_data + 16);
4668f050 1765 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1766 emulate_gp(ctxt, 0);
e54cfa97 1767 return X86EMUL_PROPAGATE_FAULT;
4668f050 1768 }
79168fd1 1769 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1770 break;
1771 case X86EMUL_MODE_PROT64:
79168fd1 1772 cs_sel = (u16)(msr_data + 32);
4668f050 1773 if (msr_data == 0x0) {
54b8486f 1774 emulate_gp(ctxt, 0);
e54cfa97 1775 return X86EMUL_PROPAGATE_FAULT;
4668f050 1776 }
79168fd1
GN		 1777 ss_sel = cs_sel + 8;
1778 cs.d = 0;
4668f050
AP		 1779 cs.l = 1;
1780 break;
1781 }
79168fd1
GN		 1782 cs_sel |= SELECTOR_RPL_MASK;
1783 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1784
79168fd1
GN		 1785 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1786 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1787 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1788 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1789
bdb475a3
GN		 1790 c->eip = c->regs[VCPU_REGS_RDX];
1791 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1792
e54cfa97 1793 return X86EMUL_CONTINUE;
4668f050
AP		 1794}
1795
9c537244
GN		 1796static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1797 struct x86_emulate_ops *ops)
f850e2e6
GN		 1798{
1799 int iopl;
1800 if (ctxt->mode == X86EMUL_MODE_REAL)
1801 return false;
1802 if (ctxt->mode == X86EMUL_MODE_VM86)
1803 return true;
1804 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1805 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1806}
1807
1808static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1809 struct x86_emulate_ops *ops,
1810 u16 port, u16 len)
1811{
79168fd1 1812 struct desc_struct tr_seg;
f850e2e6
GN		 1813 int r;
1814 u16 io_bitmap_ptr;
1815 u8 perm, bit_idx = port & 0x7;
1816 unsigned mask = (1 << len) - 1;
1817
79168fd1
GN		 1818 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1819 if (!tr_seg.p)
f850e2e6 1820 return false;
79168fd1 1821 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1822 return false;
79168fd1
GN		 1823 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1824 ctxt->vcpu, NULL);
f850e2e6
GN		 1825 if (r != X86EMUL_CONTINUE)
1826 return false;
79168fd1 1827 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1828 return false;
79168fd1
GN		 1829 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1830 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1831 if (r != X86EMUL_CONTINUE)
1832 return false;
1833 if ((perm >> bit_idx) & mask)
1834 return false;
1835 return true;
1836}
1837
1838static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1839 struct x86_emulate_ops *ops,
1840 u16 port, u16 len)
1841{
4fc40f07
GN		 1842 if (ctxt->perm_ok)
1843 return true;
1844
9c537244 1845 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1846 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1847 return false;
4fc40f07
GN		 1848
1849 ctxt->perm_ok = true;
1850
f850e2e6
GN		 1851 return true;
1852}
1853
38ba30ba
GN		 1854static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1855 struct x86_emulate_ops *ops,
1856 struct tss_segment_16 *tss)
1857{
1858 struct decode_cache *c = &ctxt->decode;
1859
1860 tss->ip = c->eip;
1861 tss->flag = ctxt->eflags;
1862 tss->ax = c->regs[VCPU_REGS_RAX];
1863 tss->cx = c->regs[VCPU_REGS_RCX];
1864 tss->dx = c->regs[VCPU_REGS_RDX];
1865 tss->bx = c->regs[VCPU_REGS_RBX];
1866 tss->sp = c->regs[VCPU_REGS_RSP];
1867 tss->bp = c->regs[VCPU_REGS_RBP];
1868 tss->si = c->regs[VCPU_REGS_RSI];
1869 tss->di = c->regs[VCPU_REGS_RDI];
1870
1871 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1872 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1873 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1874 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1875 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1876}
1877
1878static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1879 struct x86_emulate_ops *ops,
1880 struct tss_segment_16 *tss)
1881{
1882 struct decode_cache *c = &ctxt->decode;
1883 int ret;
1884
1885 c->eip = tss->ip;
1886 ctxt->eflags = tss->flag | 2;
1887 c->regs[VCPU_REGS_RAX] = tss->ax;
1888 c->regs[VCPU_REGS_RCX] = tss->cx;
1889 c->regs[VCPU_REGS_RDX] = tss->dx;
1890 c->regs[VCPU_REGS_RBX] = tss->bx;
1891 c->regs[VCPU_REGS_RSP] = tss->sp;
1892 c->regs[VCPU_REGS_RBP] = tss->bp;
1893 c->regs[VCPU_REGS_RSI] = tss->si;
1894 c->regs[VCPU_REGS_RDI] = tss->di;
1895
1896 /*
1897 * SDM says that segment selectors are loaded before segment
1898 * descriptors
1899 */
1900 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1901 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1902 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1903 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1904 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1905
1906 /*
1907 * Now load segment descriptors. If fault happenes at this stage
1908 * it is handled in a context of new task
1909 */
1910 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1911 if (ret != X86EMUL_CONTINUE)
1912 return ret;
1913 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1914 if (ret != X86EMUL_CONTINUE)
1915 return ret;
1916 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1917 if (ret != X86EMUL_CONTINUE)
1918 return ret;
1919 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1920 if (ret != X86EMUL_CONTINUE)
1921 return ret;
1922 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1923 if (ret != X86EMUL_CONTINUE)
1924 return ret;
1925
1926 return X86EMUL_CONTINUE;
1927}
1928
1929static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1930 struct x86_emulate_ops *ops,
1931 u16 tss_selector, u16 old_tss_sel,
1932 ulong old_tss_base, struct desc_struct *new_desc)
1933{
1934 struct tss_segment_16 tss_seg;
1935 int ret;
1936 u32 err, new_tss_base = get_desc_base(new_desc);
1937
1938 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1939 &err);
1940 if (ret == X86EMUL_PROPAGATE_FAULT) {
1941 /* FIXME: need to provide precise fault address */
54b8486f 1942 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1943 return ret;
1944 }
1945
1946 save_state_to_tss16(ctxt, ops, &tss_seg);
1947
1948 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1949 &err);
1950 if (ret == X86EMUL_PROPAGATE_FAULT) {
1951 /* FIXME: need to provide precise fault address */
54b8486f 1952 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1953 return ret;
1954 }
1955
1956 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1957 &err);
1958 if (ret == X86EMUL_PROPAGATE_FAULT) {
1959 /* FIXME: need to provide precise fault address */
54b8486f 1960 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1961 return ret;
1962 }
1963
1964 if (old_tss_sel != 0xffff) {
1965 tss_seg.prev_task_link = old_tss_sel;
1966
1967 ret = ops->write_std(new_tss_base,
1968 &tss_seg.prev_task_link,
1969 sizeof tss_seg.prev_task_link,
1970 ctxt->vcpu, &err);
1971 if (ret == X86EMUL_PROPAGATE_FAULT) {
1972 /* FIXME: need to provide precise fault address */
54b8486f 1973 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1974 return ret;
1975 }
1976 }
1977
1978 return load_state_from_tss16(ctxt, ops, &tss_seg);
1979}
1980
1981static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1982 struct x86_emulate_ops *ops,
1983 struct tss_segment_32 *tss)
1984{
1985 struct decode_cache *c = &ctxt->decode;
1986
1987 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1988 tss->eip = c->eip;
1989 tss->eflags = ctxt->eflags;
1990 tss->eax = c->regs[VCPU_REGS_RAX];
1991 tss->ecx = c->regs[VCPU_REGS_RCX];
1992 tss->edx = c->regs[VCPU_REGS_RDX];
1993 tss->ebx = c->regs[VCPU_REGS_RBX];
1994 tss->esp = c->regs[VCPU_REGS_RSP];
1995 tss->ebp = c->regs[VCPU_REGS_RBP];
1996 tss->esi = c->regs[VCPU_REGS_RSI];
1997 tss->edi = c->regs[VCPU_REGS_RDI];
1998
1999 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2000 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2001 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2002 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2003 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2004 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2005 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2006}
2007
2008static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2009 struct x86_emulate_ops *ops,
2010 struct tss_segment_32 *tss)
2011{
2012 struct decode_cache *c = &ctxt->decode;
2013 int ret;
2014
0f12244f 2015 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2016 emulate_gp(ctxt, 0);
0f12244f
GN		 2017 return X86EMUL_PROPAGATE_FAULT;
2018 }
38ba30ba
GN		 2019 c->eip = tss->eip;
2020 ctxt->eflags = tss->eflags | 2;
2021 c->regs[VCPU_REGS_RAX] = tss->eax;
2022 c->regs[VCPU_REGS_RCX] = tss->ecx;
2023 c->regs[VCPU_REGS_RDX] = tss->edx;
2024 c->regs[VCPU_REGS_RBX] = tss->ebx;
2025 c->regs[VCPU_REGS_RSP] = tss->esp;
2026 c->regs[VCPU_REGS_RBP] = tss->ebp;
2027 c->regs[VCPU_REGS_RSI] = tss->esi;
2028 c->regs[VCPU_REGS_RDI] = tss->edi;
2029
2030 /*
2031 * SDM says that segment selectors are loaded before segment
2032 * descriptors
2033 */
2034 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2035 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2036 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2037 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2038 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2039 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2040 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2041
2042 /*
2043 * Now load segment descriptors. If fault happenes at this stage
2044 * it is handled in a context of new task
2045 */
2046 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2047 if (ret != X86EMUL_CONTINUE)
2048 return ret;
2049 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2050 if (ret != X86EMUL_CONTINUE)
2051 return ret;
2052 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2053 if (ret != X86EMUL_CONTINUE)
2054 return ret;
2055 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2056 if (ret != X86EMUL_CONTINUE)
2057 return ret;
2058 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2059 if (ret != X86EMUL_CONTINUE)
2060 return ret;
2061 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2062 if (ret != X86EMUL_CONTINUE)
2063 return ret;
2064 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2065 if (ret != X86EMUL_CONTINUE)
2066 return ret;
2067
2068 return X86EMUL_CONTINUE;
2069}
2070
2071static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2072 struct x86_emulate_ops *ops,
2073 u16 tss_selector, u16 old_tss_sel,
2074 ulong old_tss_base, struct desc_struct *new_desc)
2075{
2076 struct tss_segment_32 tss_seg;
2077 int ret;
2078 u32 err, new_tss_base = get_desc_base(new_desc);
2079
2080 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2081 &err);
2082 if (ret == X86EMUL_PROPAGATE_FAULT) {
2083 /* FIXME: need to provide precise fault address */
54b8486f 2084 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2085 return ret;
2086 }
2087
2088 save_state_to_tss32(ctxt, ops, &tss_seg);
2089
2090 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2091 &err);
2092 if (ret == X86EMUL_PROPAGATE_FAULT) {
2093 /* FIXME: need to provide precise fault address */
54b8486f 2094 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2095 return ret;
2096 }
2097
2098 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2099 &err);
2100 if (ret == X86EMUL_PROPAGATE_FAULT) {
2101 /* FIXME: need to provide precise fault address */
54b8486f 2102 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2103 return ret;
2104 }
2105
2106 if (old_tss_sel != 0xffff) {
2107 tss_seg.prev_task_link = old_tss_sel;
2108
2109 ret = ops->write_std(new_tss_base,
2110 &tss_seg.prev_task_link,
2111 sizeof tss_seg.prev_task_link,
2112 ctxt->vcpu, &err);
2113 if (ret == X86EMUL_PROPAGATE_FAULT) {
2114 /* FIXME: need to provide precise fault address */
54b8486f 2115 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2116 return ret;
2117 }
2118 }
2119
2120 return load_state_from_tss32(ctxt, ops, &tss_seg);
2121}
2122
2123static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2124 struct x86_emulate_ops *ops,
2125 u16 tss_selector, int reason,
2126 bool has_error_code, u32 error_code)
38ba30ba
GN		 2127{
2128 struct desc_struct curr_tss_desc, next_tss_desc;
2129 int ret;
2130 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2131 ulong old_tss_base =
5951c442 2132 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2133 u32 desc_limit;
38ba30ba
GN		 2134
2135 /* FIXME: old_tss_base == ~0 ? */
2136
2137 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2138 if (ret != X86EMUL_CONTINUE)
2139 return ret;
2140 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2141 if (ret != X86EMUL_CONTINUE)
2142 return ret;
2143
2144 /* FIXME: check that next_tss_desc is tss */
2145
2146 if (reason != TASK_SWITCH_IRET) {
2147 if ((tss_selector & 3) > next_tss_desc.dpl ||
2148 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2149 emulate_gp(ctxt, 0);
38ba30ba
GN		 2150 return X86EMUL_PROPAGATE_FAULT;
2151 }
2152 }
2153
ceffb459
GN		 2154 desc_limit = desc_limit_scaled(&next_tss_desc);
2155 if (!next_tss_desc.p ||
2156 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2157 desc_limit < 0x2b)) {
54b8486f 2158 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2159 return X86EMUL_PROPAGATE_FAULT;
2160 }
2161
2162 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2163 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2164 write_segment_descriptor(ctxt, ops, old_tss_sel,
2165 &curr_tss_desc);
2166 }
2167
2168 if (reason == TASK_SWITCH_IRET)
2169 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2170
2171 /* set back link to prev task only if NT bit is set in eflags
2172 note that old_tss_sel is not used afetr this point */
2173 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2174 old_tss_sel = 0xffff;
2175
2176 if (next_tss_desc.type & 8)
2177 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2178 old_tss_base, &next_tss_desc);
2179 else
2180 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2181 old_tss_base, &next_tss_desc);
0760d448
JK		 2182 if (ret != X86EMUL_CONTINUE)
2183 return ret;
38ba30ba
GN		 2184
2185 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2186 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2187
2188 if (reason != TASK_SWITCH_IRET) {
2189 next_tss_desc.type |= (1 << 1); /* set busy flag */
2190 write_segment_descriptor(ctxt, ops, tss_selector,
2191 &next_tss_desc);
2192 }
2193
2194 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2195 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2196 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2197
e269fb21
JK		 2198 if (has_error_code) {
2199 struct decode_cache *c = &ctxt->decode;
2200
2201 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2202 c->lock_prefix = 0;
2203 c->src.val = (unsigned long) error_code;
79168fd1 2204 emulate_push(ctxt, ops);
e269fb21
JK		 2205 }
2206
38ba30ba
GN		 2207 return ret;
2208}
2209
2210int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2211 u16 tss_selector, int reason,
2212 bool has_error_code, u32 error_code)
38ba30ba 2213{
9aabc88f 2214 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2215 struct decode_cache *c = &ctxt->decode;
2216 int rc;
2217
38ba30ba 2218 c->eip = ctxt->eip;
e269fb21 2219 c->dst.type = OP_NONE;
38ba30ba 2220
e269fb21
JK		 2221 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2222 has_error_code, error_code);
38ba30ba
GN		 2223
2224 if (rc == X86EMUL_CONTINUE) {
e269fb21 2225 rc = writeback(ctxt, ops);
95c55886
GN		 2226 if (rc == X86EMUL_CONTINUE)
2227 ctxt->eip = c->eip;
38ba30ba
GN		 2228 }
2229
19d04437 2230 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2231}
2232
a682e354 2233static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2234 int reg, struct operand *op)
a682e354
GN		 2235{
2236 struct decode_cache *c = &ctxt->decode;
2237 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2238
d9271123 2239 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2240 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2241}
2242
63540382
AK		 2243static int em_push(struct x86_emulate_ctxt *ctxt)
2244{
2245 emulate_push(ctxt, ctxt->ops);
2246 return X86EMUL_CONTINUE;
2247}
2248
7af04fc0
AK		 2249static int em_das(struct x86_emulate_ctxt *ctxt)
2250{
2251 struct decode_cache *c = &ctxt->decode;
2252 u8 al, old_al;
2253 bool af, cf, old_cf;
2254
2255 cf = ctxt->eflags & X86_EFLAGS_CF;
2256 al = c->dst.val;
2257
2258 old_al = al;
2259 old_cf = cf;
2260 cf = false;
2261 af = ctxt->eflags & X86_EFLAGS_AF;
2262 if ((al & 0x0f) > 9 || af) {
2263 al -= 6;
2264 cf = old_cf | (al >= 250);
2265 af = true;
2266 } else {
2267 af = false;
2268 }
2269 if (old_al > 0x99 || old_cf) {
2270 al -= 0x60;
2271 cf = true;
2272 }
2273
2274 c->dst.val = al;
2275 /* Set PF, ZF, SF */
2276 c->src.type = OP_IMM;
2277 c->src.val = 0;
2278 c->src.bytes = 1;
2279 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2280 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2281 if (cf)
2282 ctxt->eflags |= X86_EFLAGS_CF;
2283 if (af)
2284 ctxt->eflags |= X86_EFLAGS_AF;
2285 return X86EMUL_CONTINUE;
2286}
2287
0ef753b8
AK		 2288static int em_call_far(struct x86_emulate_ctxt *ctxt)
2289{
2290 struct decode_cache *c = &ctxt->decode;
2291 u16 sel, old_cs;
2292 ulong old_eip;
2293 int rc;
2294
2295 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2296 old_eip = c->eip;
2297
2298 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2299 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2300 return X86EMUL_CONTINUE;
2301
2302 c->eip = 0;
2303 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2304
2305 c->src.val = old_cs;
2306 emulate_push(ctxt, ctxt->ops);
2307 rc = writeback(ctxt, ctxt->ops);
2308 if (rc != X86EMUL_CONTINUE)
2309 return rc;
2310
2311 c->src.val = old_eip;
2312 emulate_push(ctxt, ctxt->ops);
2313 rc = writeback(ctxt, ctxt->ops);
2314 if (rc != X86EMUL_CONTINUE)
2315 return rc;
2316
2317 c->dst.type = OP_NONE;
2318
2319 return X86EMUL_CONTINUE;
2320}
2321
40ece7c7
AK		 2322static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2323{
2324 struct decode_cache *c = &ctxt->decode;
2325 int rc;
2326
2327 c->dst.type = OP_REG;
2328 c->dst.addr.reg = &c->eip;
2329 c->dst.bytes = c->op_bytes;
2330 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2331 if (rc != X86EMUL_CONTINUE)
2332 return rc;
2333 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2334 return X86EMUL_CONTINUE;
2335}
2336
5c82aa29 2337static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2338{
2339 struct decode_cache *c = &ctxt->decode;
2340
f3a1b9f4
AK		 2341 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2342 return X86EMUL_CONTINUE;
2343}
2344
5c82aa29
AK		 2345static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2346{
2347 struct decode_cache *c = &ctxt->decode;
2348
2349 c->dst.val = c->src2.val;
2350 return em_imul(ctxt);
2351}
2352
61429142
AK		 2353static int em_cwd(struct x86_emulate_ctxt *ctxt)
2354{
2355 struct decode_cache *c = &ctxt->decode;
2356
2357 c->dst.type = OP_REG;
2358 c->dst.bytes = c->src.bytes;
2359 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2360 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2361
2362 return X86EMUL_CONTINUE;
2363}
2364
48bb5d3c
AK		 2365static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2366{
2367 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2368 struct decode_cache *c = &ctxt->decode;
2369 u64 tsc = 0;
2370
2371 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2372 emulate_gp(ctxt, 0);
2373 return X86EMUL_PROPAGATE_FAULT;
2374 }
2375 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2376 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2377 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2378 return X86EMUL_CONTINUE;
2379}
2380
b9eac5f4
AK		 2381static int em_mov(struct x86_emulate_ctxt *ctxt)
2382{
2383 struct decode_cache *c = &ctxt->decode;
2384 c->dst.val = c->src.val;
2385 return X86EMUL_CONTINUE;
2386}
2387
73fba5f4
AK		 2388#define D(_y) { .flags = (_y) }
2389#define N D(0)
2390#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2391#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2392#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2393
8d8f4e9f
AK		 2394#define D2bv(_f) D((_f) | ByteOp), D(_f)
2395#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2396
6230f7fc
AK		 2397#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2398 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2399 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2400
2401
73fba5f4
AK		 2402static struct opcode group1[] = {
2403 X7(D(Lock)), N
2404};
2405
2406static struct opcode group1A[] = {
2407 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2408};
2409
2410static struct opcode group3[] = {
2411 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2412 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2413 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2414};
2415
2416static struct opcode group4[] = {
2417 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2418 N, N, N, N, N, N,
2419};
2420
2421static struct opcode group5[] = {
2422 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2423 D(SrcMem | ModRM | Stack),
2424 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2425 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2426 D(SrcMem | ModRM | Stack), N,
2427};
2428
2429static struct group_dual group7 = { {
2430 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2431 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2432 D(SrcMem16 | ModRM | Mov | Priv),
2433 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4
AK		 2434}, {
2435 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2436 D(SrcNone | ModRM | DstMem | Mov), N,
2437 D(SrcMem16 | ModRM | Mov | Priv), N,
2438} };
2439
2440static struct opcode group8[] = {
2441 N, N, N, N,
2442 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2443 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2444};
2445
2446static struct group_dual group9 = { {
2447 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2448}, {
2449 N, N, N, N, N, N, N, N,
2450} };
2451
a4d4a7c1
AK		 2452static struct opcode group11[] = {
2453 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2454};
2455
73fba5f4
AK		 2456static struct opcode opcode_table[256] = {
2457 /* 0x00 - 0x07 */
6230f7fc 2458 D6ALU(Lock),
73fba5f4
AK		 2459 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2460 /* 0x08 - 0x0F */
6230f7fc 2461 D6ALU(Lock),
73fba5f4
AK		 2462 D(ImplicitOps | Stack | No64), N,
2463 /* 0x10 - 0x17 */
6230f7fc 2464 D6ALU(Lock),
73fba5f4
AK		 2465 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2466 /* 0x18 - 0x1F */
6230f7fc 2467 D6ALU(Lock),
73fba5f4
AK		 2468 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2469 /* 0x20 - 0x27 */
6230f7fc 2470 D6ALU(Lock), N, N,
73fba5f4 2471 /* 0x28 - 0x2F */
6230f7fc 2472 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2473 /* 0x30 - 0x37 */
6230f7fc 2474 D6ALU(Lock), N, N,
73fba5f4 2475 /* 0x38 - 0x3F */
6230f7fc 2476 D6ALU(0), N, N,
73fba5f4
AK		 2477 /* 0x40 - 0x4F */
2478 X16(D(DstReg)),
2479 /* 0x50 - 0x57 */
63540382 2480 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2481 /* 0x58 - 0x5F */
2482 X8(D(DstReg | Stack)),
2483 /* 0x60 - 0x67 */
2484 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2485 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2486 N, N, N, N,
2487 /* 0x68 - 0x6F */
d46164db
AK		 2488 I(SrcImm | Mov | Stack, em_push),
2489 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2490 I(SrcImmByte | Mov | Stack, em_push),
2491 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2492 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2493 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2494 /* 0x70 - 0x7F */
2495 X16(D(SrcImmByte)),
2496 /* 0x80 - 0x87 */
2497 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2498 G(DstMem | SrcImm | ModRM | Group, group1),
2499 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2500 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2501 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2502 /* 0x88 - 0x8F */
b9eac5f4
AK		 2503 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2504 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2505 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2506 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2507 /* 0x90 - 0x97 */
3d9e77df 2508 X8(D(SrcAcc | DstReg)),
73fba5f4 2509 /* 0x98 - 0x9F */
61429142 2510 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2511 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2512 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2513 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2514 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2515 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2516 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2517 D2bv(SrcSI | DstDI | String),
73fba5f4 2518 /* 0xA8 - 0xAF */
50748613 2519 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2520 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2521 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2522 D2bv(SrcAcc | DstDI | String),
73fba5f4 2523 /* 0xB0 - 0xB7 */
b9eac5f4 2524 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2525 /* 0xB8 - 0xBF */
b9eac5f4 2526 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2527 /* 0xC0 - 0xC7 */
d2c6c7ad 2528 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2529 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2530 D(ImplicitOps | Stack),
09b5f4d3 2531 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2532 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2533 /* 0xC8 - 0xCF */
2534 N, N, N, D(ImplicitOps | Stack),
2535 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2536 /* 0xD0 - 0xD7 */
d2c6c7ad 2537 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2538 N, N, N, N,
2539 /* 0xD8 - 0xDF */
2540 N, N, N, N, N, N, N, N,
2541 /* 0xE0 - 0xE7 */
e4abac67 2542 X4(D(SrcImmByte)),
d269e396 2543 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2544 /* 0xE8 - 0xEF */
2545 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2546 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2547 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2548 /* 0xF0 - 0xF7 */
2549 N, N, N, N,
2550 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2551 /* 0xF8 - 0xFF */
8744aa9a 2552 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2553 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2554};
2555
2556static struct opcode twobyte_table[256] = {
2557 /* 0x00 - 0x0F */
2558 N, GD(0, &group7), N, N,
2559 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2560 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2561 N, D(ImplicitOps | ModRM), N, N,
2562 /* 0x10 - 0x1F */
2563 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2564 /* 0x20 - 0x2F */
b27f3856
AK		 2565 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2566 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2567 N, N, N, N,
2568 N, N, N, N, N, N, N, N,
2569 /* 0x30 - 0x3F */
48bb5d3c
AK		 2570 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2571 D(ImplicitOps | Priv), N,
73fba5f4
AK		 2572 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2573 N, N, N, N, N, N, N, N,
2574 /* 0x40 - 0x4F */
2575 X16(D(DstReg | SrcMem | ModRM | Mov)),
2576 /* 0x50 - 0x5F */
2577 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2578 /* 0x60 - 0x6F */
2579 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2580 /* 0x70 - 0x7F */
2581 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2582 /* 0x80 - 0x8F */
2583 X16(D(SrcImm)),
2584 /* 0x90 - 0x9F */
ee45b58e 2585 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2586 /* 0xA0 - 0xA7 */
2587 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2588 N, D(DstMem | SrcReg | ModRM | BitOp),
2589 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2590 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2591 /* 0xA8 - 0xAF */
2592 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2593 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2594 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2595 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2596 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2597 /* 0xB0 - 0xB7 */
739ae406 2598 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2599 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2600 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2601 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2602 /* 0xB8 - 0xBF */
2603 N, N,
ba7ff2b7 2604 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2605 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2606 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2607 /* 0xC0 - 0xCF */
739ae406 2608 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2609 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2610 N, N, N, GD(0, &group9),
2611 N, N, N, N, N, N, N, N,
2612 /* 0xD0 - 0xDF */
2613 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2614 /* 0xE0 - 0xEF */
2615 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2616 /* 0xF0 - 0xFF */
2617 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2618};
2619
2620#undef D
2621#undef N
2622#undef G
2623#undef GD
2624#undef I
2625
8d8f4e9f
AK		 2626#undef D2bv
2627#undef I2bv
6230f7fc 2628#undef D6ALU
8d8f4e9f 2629
39f21ee5
AK		 2630static unsigned imm_size(struct decode_cache *c)
2631{
2632 unsigned size;
2633
2634 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2635 if (size == 8)
2636 size = 4;
2637 return size;
2638}
2639
2640static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2641 unsigned size, bool sign_extension)
2642{
2643 struct decode_cache *c = &ctxt->decode;
2644 struct x86_emulate_ops *ops = ctxt->ops;
2645 int rc = X86EMUL_CONTINUE;
2646
2647 op->type = OP_IMM;
2648 op->bytes = size;
2649 op->addr.mem = c->eip;
2650 /* NB. Immediates are sign-extended as necessary. */
2651 switch (op->bytes) {
2652 case 1:
2653 op->val = insn_fetch(s8, 1, c->eip);
2654 break;
2655 case 2:
2656 op->val = insn_fetch(s16, 2, c->eip);
2657 break;
2658 case 4:
2659 op->val = insn_fetch(s32, 4, c->eip);
2660 break;
2661 }
2662 if (!sign_extension) {
2663 switch (op->bytes) {
2664 case 1:
2665 op->val &= 0xff;
2666 break;
2667 case 2:
2668 op->val &= 0xffff;
2669 break;
2670 case 4:
2671 op->val &= 0xffffffff;
2672 break;
2673 }
2674 }
2675done:
2676 return rc;
2677}
2678
dde7e6d1
AK		 2679int
2680x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2681{
2682 struct x86_emulate_ops *ops = ctxt->ops;
2683 struct decode_cache *c = &ctxt->decode;
2684 int rc = X86EMUL_CONTINUE;
2685 int mode = ctxt->mode;
2686 int def_op_bytes, def_ad_bytes, dual, goffset;
2687 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2688 struct operand memop = { .type = OP_NONE };
dde7e6d1 2689
dde7e6d1
AK		 2690 c->eip = ctxt->eip;
2691 c->fetch.start = c->fetch.end = c->eip;
2692 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2693
2694 switch (mode) {
2695 case X86EMUL_MODE_REAL:
2696 case X86EMUL_MODE_VM86:
2697 case X86EMUL_MODE_PROT16:
2698 def_op_bytes = def_ad_bytes = 2;
2699 break;
2700 case X86EMUL_MODE_PROT32:
2701 def_op_bytes = def_ad_bytes = 4;
2702 break;
2703#ifdef CONFIG_X86_64
2704 case X86EMUL_MODE_PROT64:
2705 def_op_bytes = 4;
2706 def_ad_bytes = 8;
2707 break;
2708#endif
2709 default:
2710 return -1;
2711 }
2712
2713 c->op_bytes = def_op_bytes;
2714 c->ad_bytes = def_ad_bytes;
2715
2716 /* Legacy prefixes. */
2717 for (;;) {
2718 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2719 case 0x66: /* operand-size override */
2720 /* switch between 2/4 bytes */
2721 c->op_bytes = def_op_bytes ^ 6;
2722 break;
2723 case 0x67: /* address-size override */
2724 if (mode == X86EMUL_MODE_PROT64)
2725 /* switch between 4/8 bytes */
2726 c->ad_bytes = def_ad_bytes ^ 12;
2727 else
2728 /* switch between 2/4 bytes */
2729 c->ad_bytes = def_ad_bytes ^ 6;
2730 break;
2731 case 0x26: /* ES override */
2732 case 0x2e: /* CS override */
2733 case 0x36: /* SS override */
2734 case 0x3e: /* DS override */
2735 set_seg_override(c, (c->b >> 3) & 3);
2736 break;
2737 case 0x64: /* FS override */
2738 case 0x65: /* GS override */
2739 set_seg_override(c, c->b & 7);
2740 break;
2741 case 0x40 ... 0x4f: /* REX */
2742 if (mode != X86EMUL_MODE_PROT64)
2743 goto done_prefixes;
2744 c->rex_prefix = c->b;
2745 continue;
2746 case 0xf0: /* LOCK */
2747 c->lock_prefix = 1;
2748 break;
2749 case 0xf2: /* REPNE/REPNZ */
2750 c->rep_prefix = REPNE_PREFIX;
2751 break;
2752 case 0xf3: /* REP/REPE/REPZ */
2753 c->rep_prefix = REPE_PREFIX;
2754 break;
2755 default:
2756 goto done_prefixes;
2757 }
2758
2759 /* Any legacy prefix after a REX prefix nullifies its effect. */
2760
2761 c->rex_prefix = 0;
2762 }
2763
2764done_prefixes:
2765
2766 /* REX prefix. */
1e87e3ef
AK		 2767 if (c->rex_prefix & 8)
2768 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2769
2770 /* Opcode byte(s). */
2771 opcode = opcode_table[c->b];
d3ad6243
WY		 2772 /* Two-byte opcode? */
2773 if (c->b == 0x0f) {
2774 c->twobyte = 1;
2775 c->b = insn_fetch(u8, 1, c->eip);
2776 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2777 }
2778 c->d = opcode.flags;
2779
2780 if (c->d & Group) {
2781 dual = c->d & GroupDual;
2782 c->modrm = insn_fetch(u8, 1, c->eip);
2783 --c->eip;
2784
2785 if (c->d & GroupDual) {
2786 g_mod012 = opcode.u.gdual->mod012;
2787 g_mod3 = opcode.u.gdual->mod3;
2788 } else
2789 g_mod012 = g_mod3 = opcode.u.group;
2790
2791 c->d &= ~(Group | GroupDual);
2792
2793 goffset = (c->modrm >> 3) & 7;
2794
2795 if ((c->modrm >> 6) == 3)
2796 opcode = g_mod3[goffset];
2797 else
2798 opcode = g_mod012[goffset];
2799 c->d |= opcode.flags;
2800 }
2801
2802 c->execute = opcode.u.execute;
2803
2804 /* Unrecognised? */
2805 if (c->d == 0 || (c->d & Undefined)) {
2806 DPRINTF("Cannot emulate %02x\n", c->b);
2807 return -1;
2808 }
2809
2810 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2811 c->op_bytes = 8;
2812
7f9b4b75
AK		 2813 if (c->d & Op3264) {
2814 if (mode == X86EMUL_MODE_PROT64)
2815 c->op_bytes = 8;
2816 else
2817 c->op_bytes = 4;
2818 }
2819
dde7e6d1 2820 /* ModRM and SIB bytes. */
09ee57cd 2821 if (c->d & ModRM) {
2dbd0dd7 2822 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2823 if (!c->has_seg_override)
2824 set_seg_override(c, c->modrm_seg);
2825 } else if (c->d & MemAbs)
2dbd0dd7 2826 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2827 if (rc != X86EMUL_CONTINUE)
2828 goto done;
2829
2830 if (!c->has_seg_override)
2831 set_seg_override(c, VCPU_SREG_DS);
2832
2dbd0dd7
AK		 2833 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2834 memop.addr.mem += seg_override_base(ctxt, ops, c);
dde7e6d1 2835
2dbd0dd7
AK		 2836 if (memop.type == OP_MEM && c->ad_bytes != 8)
2837 memop.addr.mem = (u32)memop.addr.mem;
dde7e6d1 2838
2dbd0dd7
AK		 2839 if (memop.type == OP_MEM && c->rip_relative)
2840 memop.addr.mem += c->eip;
dde7e6d1
AK		 2841
2842 /*
2843 * Decode and fetch the source operand: register, memory
2844 * or immediate.
2845 */
2846 switch (c->d & SrcMask) {
2847 case SrcNone:
2848 break;
2849 case SrcReg:
2850 decode_register_operand(&c->src, c, 0);
2851 break;
2852 case SrcMem16:
2dbd0dd7 2853 memop.bytes = 2;
dde7e6d1
AK		 2854 goto srcmem_common;
2855 case SrcMem32:
2dbd0dd7 2856 memop.bytes = 4;
dde7e6d1
AK		 2857 goto srcmem_common;
2858 case SrcMem:
2dbd0dd7 2859 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2860 c->op_bytes;
dde7e6d1 2861 srcmem_common:
2dbd0dd7 2862 c->src = memop;
dde7e6d1 2863 break;
b250e605 2864 case SrcImmU16:
39f21ee5
AK		 2865 rc = decode_imm(ctxt, &c->src, 2, false);
2866 break;
dde7e6d1 2867 case SrcImm:
39f21ee5
AK		 2868 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2869 break;
dde7e6d1 2870 case SrcImmU:
39f21ee5 2871 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2872 break;
2873 case SrcImmByte:
39f21ee5
AK		 2874 rc = decode_imm(ctxt, &c->src, 1, true);
2875 break;
dde7e6d1 2876 case SrcImmUByte:
39f21ee5 2877 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2878 break;
2879 case SrcAcc:
2880 c->src.type = OP_REG;
2881 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2882 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2883 fetch_register_operand(&c->src);
dde7e6d1
AK		 2884 break;
2885 case SrcOne:
2886 c->src.bytes = 1;
2887 c->src.val = 1;
2888 break;
2889 case SrcSI:
2890 c->src.type = OP_MEM;
2891 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2892 c->src.addr.mem =
dde7e6d1
AK		 2893 register_address(c, seg_override_base(ctxt, ops, c),
2894 c->regs[VCPU_REGS_RSI]);
2895 c->src.val = 0;
2896 break;
2897 case SrcImmFAddr:
2898 c->src.type = OP_IMM;
1a6440ae 2899 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2900 c->src.bytes = c->op_bytes + 2;
2901 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2902 break;
2903 case SrcMemFAddr:
2dbd0dd7
AK		 2904 memop.bytes = c->op_bytes + 2;
2905 goto srcmem_common;
dde7e6d1
AK		 2906 break;
2907 }
2908
39f21ee5
AK		 2909 if (rc != X86EMUL_CONTINUE)
2910 goto done;
2911
dde7e6d1
AK		 2912 /*
2913 * Decode and fetch the second source operand: register, memory
2914 * or immediate.
2915 */
2916 switch (c->d & Src2Mask) {
2917 case Src2None:
2918 break;
2919 case Src2CL:
2920 c->src2.bytes = 1;
2921 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2922 break;
2923 case Src2ImmByte:
39f21ee5 2924 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2925 break;
2926 case Src2One:
2927 c->src2.bytes = 1;
2928 c->src2.val = 1;
2929 break;
7db41eb7
AK		 2930 case Src2Imm:
2931 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2932 break;
dde7e6d1
AK		 2933 }
2934
39f21ee5
AK		 2935 if (rc != X86EMUL_CONTINUE)
2936 goto done;
2937
dde7e6d1
AK		 2938 /* Decode and fetch the destination operand: register or memory. */
2939 switch (c->d & DstMask) {
dde7e6d1
AK		 2940 case DstReg:
2941 decode_register_operand(&c->dst, c,
2942 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2943 break;
943858e2
WY		 2944 case DstImmUByte:
2945 c->dst.type = OP_IMM;
2946 c->dst.addr.mem = c->eip;
2947 c->dst.bytes = 1;
2948 c->dst.val = insn_fetch(u8, 1, c->eip);
2949 break;
dde7e6d1
AK		 2950 case DstMem:
2951 case DstMem64:
2dbd0dd7 2952 c->dst = memop;
dde7e6d1
AK		 2953 if ((c->d & DstMask) == DstMem64)
2954 c->dst.bytes = 8;
2955 else
2956 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2957 if (c->d & BitOp)
2958 fetch_bit_operand(c);
2dbd0dd7 2959 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2960 break;
2961 case DstAcc:
2962 c->dst.type = OP_REG;
2963 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2964 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2965 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2966 c->dst.orig_val = c->dst.val;
2967 break;
2968 case DstDI:
2969 c->dst.type = OP_MEM;
2970 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2971 c->dst.addr.mem =
dde7e6d1
AK		 2972 register_address(c, es_base(ctxt, ops),
2973 c->regs[VCPU_REGS_RDI]);
2974 c->dst.val = 0;
2975 break;
36089fed
WY		 2976 case ImplicitOps:
2977 /* Special instructions do their own operand decoding. */
2978 default:
2979 c->dst.type = OP_NONE; /* Disable writeback. */
2980 return 0;
dde7e6d1
AK		 2981 }
2982
2983done:
2984 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2985}
2986
3e2f65d5
GN		 2987static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2988{
2989 struct decode_cache *c = &ctxt->decode;
2990
2991 /* The second termination condition only applies for REPE
2992 * and REPNE. Test if the repeat string operation prefix is
2993 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2994 * corresponding termination condition according to:
2995 * - if REPE/REPZ and ZF = 0 then done
2996 * - if REPNE/REPNZ and ZF = 1 then done
2997 */
2998 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2999 (c->b == 0xae) || (c->b == 0xaf))
3000 && (((c->rep_prefix == REPE_PREFIX) &&
3001 ((ctxt->eflags & EFLG_ZF) == 0))
3002 || ((c->rep_prefix == REPNE_PREFIX) &&
3003 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3004 return true;
3005
3006 return false;
3007}
3008
8b4caf66 3009int
9aabc88f 3010x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3011{
9aabc88f 3012 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3013 u64 msr_data;
8b4caf66 3014 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3015 int rc = X86EMUL_CONTINUE;
5cd21917 3016 int saved_dst_type = c->dst.type;
6e154e56 3017 int irq; /* Used for int 3, int, and into */
8b4caf66 3018
9de41573 3019 ctxt->decode.mem_read.pos = 0;
310b5d30 3020
1161624f 3021 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 3022 emulate_ud(ctxt);
1161624f
GN		 3023 goto done;
3024 }
3025
d380a5e4 3026 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3027 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 3028 emulate_ud(ctxt);
d380a5e4
GN		 3029 goto done;
3030 }
3031
081bca0e
AK		 3032 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3033 emulate_ud(ctxt);
3034 goto done;
3035 }
3036
e92805ac 3037 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3038 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 3039 emulate_gp(ctxt, 0);
e92805ac
GN		 3040 goto done;
3041 }
3042
b9fa9d6b
AK		 3043 if (c->rep_prefix && (c->d & String)) {
3044 /* All REP prefixes have the same first termination condition */
c73e197b 3045 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3046 ctxt->eip = c->eip;
b9fa9d6b
AK		 3047 goto done;
3048 }
b9fa9d6b
AK		 3049 }
3050
c483c02a 3051 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
1a6440ae 3052 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 3053 c->src.valptr, c->src.bytes);
b60d513c 3054 if (rc != X86EMUL_CONTINUE)
8b4caf66 3055 goto done;
16518d5a 3056 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3057 }
3058
e35b7b9c 3059 if (c->src2.type == OP_MEM) {
1a6440ae 3060 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 3061 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3062 if (rc != X86EMUL_CONTINUE)
3063 goto done;
3064 }
3065
8b4caf66
LV		 3066 if ((c->d & DstMask) == ImplicitOps)
3067 goto special_insn;
3068
3069
69f55cb1
GN		 3070 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3071 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 3072 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 3073 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3074 if (rc != X86EMUL_CONTINUE)
3075 goto done;
038e51de 3076 }
e4e03ded 3077 c->dst.orig_val = c->dst.val;
038e51de 3078
018a98db
AK		 3079special_insn:
3080
ef65c889
AK		 3081 if (c->execute) {
3082 rc = c->execute(ctxt);
3083 if (rc != X86EMUL_CONTINUE)
3084 goto done;
3085 goto writeback;
3086 }
3087
e4e03ded 3088 if (c->twobyte)
6aa8b732
AK		 3089 goto twobyte_insn;
3090
e4e03ded 3091 switch (c->b) {
6aa8b732
AK		 3092 case 0x00 ... 0x05:
3093 add: /* add */
05f086f8 3094 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3095 break;
0934ac9d 3096 case 0x06: /* push es */
79168fd1 3097 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3098 break;
3099 case 0x07: /* pop es */
0934ac9d 3100 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 3101 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3102 goto done;
3103 break;
6aa8b732
AK		 3104 case 0x08 ... 0x0d:
3105 or: /* or */
05f086f8 3106 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3107 break;
0934ac9d 3108 case 0x0e: /* push cs */
79168fd1 3109 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3110 break;
6aa8b732
AK		 3111 case 0x10 ... 0x15:
3112 adc: /* adc */
05f086f8 3113 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3114 break;
0934ac9d 3115 case 0x16: /* push ss */
79168fd1 3116 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3117 break;
3118 case 0x17: /* pop ss */
0934ac9d 3119 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 3120 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3121 goto done;
3122 break;
6aa8b732
AK		 3123 case 0x18 ... 0x1d:
3124 sbb: /* sbb */
05f086f8 3125 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3126 break;
0934ac9d 3127 case 0x1e: /* push ds */
79168fd1 3128 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3129 break;
3130 case 0x1f: /* pop ds */
0934ac9d 3131 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 3132 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3133 goto done;
3134 break;
aa3a816b 3135 case 0x20 ... 0x25:
6aa8b732 3136 and: /* and */
05f086f8 3137 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3138 break;
3139 case 0x28 ... 0x2d:
3140 sub: /* sub */
05f086f8 3141 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3142 break;
3143 case 0x30 ... 0x35:
3144 xor: /* xor */
05f086f8 3145 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3146 break;
3147 case 0x38 ... 0x3d:
3148 cmp: /* cmp */
05f086f8 3149 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3150 break;
33615aa9
AK		 3151 case 0x40 ... 0x47: /* inc r16/r32 */
3152 emulate_1op("inc", c->dst, ctxt->eflags);
3153 break;
3154 case 0x48 ... 0x4f: /* dec r16/r32 */
3155 emulate_1op("dec", c->dst, ctxt->eflags);
3156 break;
33615aa9
AK		 3157 case 0x58 ... 0x5f: /* pop reg */
3158 pop_instruction:
350f69dc 3159 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 3160 if (rc != X86EMUL_CONTINUE)
33615aa9 3161 goto done;
33615aa9 3162 break;
abcf14b5 3163 case 0x60: /* pusha */
c37eda13
WY		 3164 rc = emulate_pusha(ctxt, ops);
3165 if (rc != X86EMUL_CONTINUE)
3166 goto done;
abcf14b5
MG		 3167 break;
3168 case 0x61: /* popa */
3169 rc = emulate_popa(ctxt, ops);
1b30eaa8 3170 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 3171 goto done;
3172 break;
6aa8b732 3173 case 0x63: /* movsxd */
8b4caf66 3174 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3175 goto cannot_emulate;
e4e03ded 3176 c->dst.val = (s32) c->src.val;
6aa8b732 3177 break;
018a98db
AK		 3178 case 0x6c: /* insb */
3179 case 0x6d: /* insw/insd */
a13a63fa
WY		 3180 c->src.val = c->regs[VCPU_REGS_RDX];
3181 goto do_io_in;
018a98db
AK		 3182 case 0x6e: /* outsb */
3183 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3184 c->dst.val = c->regs[VCPU_REGS_RDX];
3185 goto do_io_out;
7972995b 3186 break;
b2833e3c 3187 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3188 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3189 jmp_rel(c, c->src.val);
018a98db 3190 break;
6aa8b732 3191 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3192 switch (c->modrm_reg) {
6aa8b732
AK		 3193 case 0:
3194 goto add;
3195 case 1:
3196 goto or;
3197 case 2:
3198 goto adc;
3199 case 3:
3200 goto sbb;
3201 case 4:
3202 goto and;
3203 case 5:
3204 goto sub;
3205 case 6:
3206 goto xor;
3207 case 7:
3208 goto cmp;
3209 }
3210 break;
3211 case 0x84 ... 0x85:
dfb507c4 3212 test:
05f086f8 3213 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3214 break;
3215 case 0x86 ... 0x87: /* xchg */
b13354f8 3216 xchg:
6aa8b732 3217 /* Write back the register source. */
31be40b3
WY		 3218 c->src.val = c->dst.val;
3219 write_register_operand(&c->src);
6aa8b732
AK		 3220 /*
3221 * Write back the memory destination with implicit LOCK
3222 * prefix.
3223 */
31be40b3 3224 c->dst.val = c->src.orig_val;
e4e03ded 3225 c->lock_prefix = 1;
6aa8b732 3226 break;
79168fd1
GN		 3227 case 0x8c: /* mov r/m, sreg */
3228 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3229 emulate_ud(ctxt);
5e3ae6c5 3230 goto done;
38d5bc6d 3231 }
79168fd1 3232 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3233 break;
7e0b54b1 3234 case 0x8d: /* lea r16/r32, m */
342fc630 3235 c->dst.val = c->src.addr.mem;
7e0b54b1 3236 break;
4257198a
GT		 3237 case 0x8e: { /* mov seg, r/m16 */
3238 uint16_t sel;
4257198a
GT		 3239
3240 sel = c->src.val;
8b9f4414 3241
c697518a
GN		 3242 if (c->modrm_reg == VCPU_SREG_CS ||
3243 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3244 emulate_ud(ctxt);
8b9f4414
GN		 3245 goto done;
3246 }
3247
310b5d30 3248 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3249 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3250
2e873022 3251 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3252
3253 c->dst.type = OP_NONE; /* Disable writeback. */
3254 break;
3255 }
6aa8b732 3256 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3257 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 3258 if (rc != X86EMUL_CONTINUE)
6aa8b732 3259 goto done;
6aa8b732 3260 break;
3d9e77df
AK		 3261 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3262 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3263 break;
b13354f8 3264 goto xchg;
e8b6fa70
WY		 3265 case 0x98: /* cbw/cwde/cdqe */
3266 switch (c->op_bytes) {
3267 case 2: c->dst.val = (s8)c->dst.val; break;
3268 case 4: c->dst.val = (s16)c->dst.val; break;
3269 case 8: c->dst.val = (s32)c->dst.val; break;
3270 }
3271 break;
fd2a7608 3272 case 0x9c: /* pushf */
05f086f8 3273 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3274 emulate_push(ctxt, ops);
8cdbd2c9 3275 break;
535eabcf 3276 case 0x9d: /* popf */
2b48cc75 3277 c->dst.type = OP_REG;
1a6440ae 3278 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3279 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 3280 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3281 if (rc != X86EMUL_CONTINUE)
3282 goto done;
3283 break;
6aa8b732 3284 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3285 c->dst.type = OP_NONE; /* Disable writeback. */
1a6440ae 3286 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
a682e354 3287 goto cmp;
dfb507c4
MG		 3288 case 0xa8 ... 0xa9: /* test ax, imm */
3289 goto test;
6aa8b732 3290 case 0xae ... 0xaf: /* scas */
f6b33fc5 3291 goto cmp;
018a98db
AK		 3292 case 0xc0 ... 0xc1:
3293 emulate_grp2(ctxt);
3294 break;
111de5d6 3295 case 0xc3: /* ret */
cf5de4f8 3296 c->dst.type = OP_REG;
1a6440ae 3297 c->dst.addr.reg = &c->eip;
cf5de4f8 3298 c->dst.bytes = c->op_bytes;
111de5d6 3299 goto pop_instruction;
09b5f4d3
WY		 3300 case 0xc4: /* les */
3301 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3302 if (rc != X86EMUL_CONTINUE)
3303 goto done;
3304 break;
3305 case 0xc5: /* lds */
3306 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3307 if (rc != X86EMUL_CONTINUE)
3308 goto done;
3309 break;
a77ab5ea
AK		 3310 case 0xcb: /* ret far */
3311 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 3312 if (rc != X86EMUL_CONTINUE)
3313 goto done;
3314 break;
6e154e56
MG		 3315 case 0xcc: /* int3 */
3316 irq = 3;
3317 goto do_interrupt;
3318 case 0xcd: /* int n */
3319 irq = c->src.val;
3320 do_interrupt:
3321 rc = emulate_int(ctxt, ops, irq);
3322 if (rc != X86EMUL_CONTINUE)
3323 goto done;
3324 break;
3325 case 0xce: /* into */
3326 if (ctxt->eflags & EFLG_OF) {
3327 irq = 4;
3328 goto do_interrupt;
3329 }
3330 break;
62bd430e
MG		 3331 case 0xcf: /* iret */
3332 rc = emulate_iret(ctxt, ops);
3333
1b30eaa8 3334 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 3335 goto done;
3336 break;
018a98db 3337 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3338 emulate_grp2(ctxt);
3339 break;
3340 case 0xd2 ... 0xd3: /* Grp2 */
3341 c->src.val = c->regs[VCPU_REGS_RCX];
3342 emulate_grp2(ctxt);
3343 break;
f2f31845
WY		 3344 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3345 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3346 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3347 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3348 jmp_rel(c, c->src.val);
3349 break;
e4abac67
WY		 3350 case 0xe3: /* jcxz/jecxz/jrcxz */
3351 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3352 jmp_rel(c, c->src.val);
3353 break;
a6a3034c
MG		 3354 case 0xe4: /* inb */
3355 case 0xe5: /* in */
cf8f70bf 3356 goto do_io_in;
a6a3034c
MG		 3357 case 0xe6: /* outb */
3358 case 0xe7: /* out */
cf8f70bf 3359 goto do_io_out;
1a52e051 3360 case 0xe8: /* call (near) */ {
d53c4777 3361 long int rel = c->src.val;
e4e03ded 3362 c->src.val = (unsigned long) c->eip;
7a957275 3363 jmp_rel(c, rel);
79168fd1 3364 emulate_push(ctxt, ops);
8cdbd2c9 3365 break;
1a52e051
NK		 3366 }
3367 case 0xe9: /* jmp rel */
954cd36f 3368 goto jmp;
414e6277
GN		 3369 case 0xea: { /* jmp far */
3370 unsigned short sel;
ea79849d 3371 jump_far:
414e6277
GN		 3372 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3373
3374 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3375 goto done;
954cd36f 3376
414e6277
GN		 3377 c->eip = 0;
3378 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3379 break;
414e6277 3380 }
954cd36f
GT		 3381 case 0xeb:
3382 jmp: /* jmp rel short */
7a957275 3383 jmp_rel(c, c->src.val);
a01af5ec 3384 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3385 break;
a6a3034c
MG		 3386 case 0xec: /* in al,dx */
3387 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3388 c->src.val = c->regs[VCPU_REGS_RDX];
3389 do_io_in:
3390 c->dst.bytes = min(c->dst.bytes, 4u);
3391 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3392 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3393 goto done;
3394 }
7b262e90
GN		 3395 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3396 &c->dst.val))
cf8f70bf
GN		 3397 goto done; /* IO is needed */
3398 break;
ce7a0ad3
WY		 3399 case 0xee: /* out dx,al */
3400 case 0xef: /* out dx,(e/r)ax */
41167be5 3401 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3402 do_io_out:
41167be5
WY		 3403 c->src.bytes = min(c->src.bytes, 4u);
3404 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3405 c->src.bytes)) {
54b8486f 3406 emulate_gp(ctxt, 0);
f850e2e6
GN		 3407 goto done;
3408 }
41167be5
WY		 3409 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3410 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3411 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3412 break;
111de5d6 3413 case 0xf4: /* hlt */
ad312c7c 3414 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3415 break;
111de5d6
AK		 3416 case 0xf5: /* cmc */
3417 /* complement carry flag from eflags reg */
3418 ctxt->eflags ^= EFLG_CF;
111de5d6 3419 break;
018a98db 3420 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490
AK		 3421 rc = emulate_grp3(ctxt, ops);
3422 if (rc != X86EMUL_CONTINUE)
3423 goto done;
018a98db 3424 break;
111de5d6
AK		 3425 case 0xf8: /* clc */
3426 ctxt->eflags &= ~EFLG_CF;
111de5d6 3427 break;
8744aa9a
MG		 3428 case 0xf9: /* stc */
3429 ctxt->eflags |= EFLG_CF;
3430 break;
111de5d6 3431 case 0xfa: /* cli */
07cbc6c1 3432 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3433 emulate_gp(ctxt, 0);
07cbc6c1 3434 goto done;
36089fed 3435 } else
f850e2e6 3436 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3437 break;
3438 case 0xfb: /* sti */
07cbc6c1 3439 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3440 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3441 goto done;
3442 } else {
95cb2295 3443 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3444 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3445 }
111de5d6 3446 break;
fb4616f4
MG		 3447 case 0xfc: /* cld */
3448 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3449 break;
3450 case 0xfd: /* std */
3451 ctxt->eflags |= EFLG_DF;
fb4616f4 3452 break;
ea79849d
GN		 3453 case 0xfe: /* Grp4 */
3454 grp45:
018a98db 3455 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3456 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3457 goto done;
3458 break;
ea79849d
GN		 3459 case 0xff: /* Grp5 */
3460 if (c->modrm_reg == 5)
3461 goto jump_far;
3462 goto grp45;
91269b8f
AK		 3463 default:
3464 goto cannot_emulate;
6aa8b732 3465 }
018a98db
AK		 3466
3467writeback:
3468 rc = writeback(ctxt, ops);
1b30eaa8 3469 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3470 goto done;
3471
5cd21917
GN		 3472 /*
3473 * restore dst type in case the decoding will be reused
3474 * (happens for string instruction )
3475 */
3476 c->dst.type = saved_dst_type;
3477
a682e354 3478 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3479 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3480 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3481
3482 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3483 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3484 &c->dst);
d9271123 3485
5cd21917 3486 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3487 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3488 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3489
d2ddd1c4
GN		 3490 if (!string_insn_completed(ctxt)) {
3491 /*
3492 * Re-enter guest when pio read ahead buffer is empty
3493 * or, if it is not used, after each 1024 iteration.
3494 */
3495 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3496 (r->end == 0 || r->end != r->pos)) {
3497 /*
3498 * Reset read cache. Usually happens before
3499 * decode, but since instruction is restarted
3500 * we have to do it here.
3501 */
3502 ctxt->decode.mem_read.end = 0;
3503 return EMULATION_RESTART;
3504 }
3505 goto done; /* skip rip writeback */
0fa6ccbd 3506 }
5cd21917 3507 }
d2ddd1c4
GN		 3508
3509 ctxt->eip = c->eip;
018a98db
AK		 3510
3511done:
d2ddd1c4 3512 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3513
3514twobyte_insn:
e4e03ded 3515 switch (c->b) {
6aa8b732 3516 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3517 switch (c->modrm_reg) {
6aa8b732
AK		 3518 u16 size;
3519 unsigned long address;
3520
aca7f966 3521 case 0: /* vmcall */
e4e03ded 3522 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3523 goto cannot_emulate;
3524
7aa81cc0 3525 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3526 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3527 goto done;
3528
33e3885d 3529 /* Let the processor re-execute the fixed hypercall */
063db061 3530 c->eip = ctxt->eip;
16286d08
AK		 3531 /* Disable writeback. */
3532 c->dst.type = OP_NONE;
aca7f966 3533 break;
6aa8b732 3534 case 2: /* lgdt */
1a6440ae 3535 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3536 &size, &address, c->op_bytes);
1b30eaa8 3537 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3538 goto done;
3539 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3540 /* Disable writeback. */
3541 c->dst.type = OP_NONE;
6aa8b732 3542 break;
aca7f966 3543 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3544 if (c->modrm_mod == 3) {
3545 switch (c->modrm_rm) {
3546 case 1:
3547 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3548 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3549 goto done;
3550 break;
3551 default:
3552 goto cannot_emulate;
3553 }
aca7f966 3554 } else {
1a6440ae 3555 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3556 &size, &address,
e4e03ded 3557 c->op_bytes);
1b30eaa8 3558 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3559 goto done;
3560 realmode_lidt(ctxt->vcpu, size, address);
3561 }
16286d08
AK		 3562 /* Disable writeback. */
3563 c->dst.type = OP_NONE;
6aa8b732
AK		 3564 break;
3565 case 4: /* smsw */
16286d08 3566 c->dst.bytes = 2;
52a46617 3567 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3568 break;
3569 case 6: /* lmsw */
9928ff60 3570 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3571 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3572 c->dst.type = OP_NONE;
6aa8b732 3573 break;
6e1e5ffe 3574 case 5: /* not defined */
54b8486f 3575 emulate_ud(ctxt);
6e1e5ffe 3576 goto done;
6aa8b732 3577 case 7: /* invlpg*/
1f6f0580 3578 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
16286d08
AK		 3579 /* Disable writeback. */
3580 c->dst.type = OP_NONE;
6aa8b732
AK		 3581 break;
3582 default:
3583 goto cannot_emulate;
3584 }
3585 break;
e99f0507 3586 case 0x05: /* syscall */
3fb1b5db 3587 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3588 if (rc != X86EMUL_CONTINUE)
3589 goto done;
e66bb2cc
AP		 3590 else
3591 goto writeback;
e99f0507 3592 break;
018a98db
AK		 3593 case 0x06:
3594 emulate_clts(ctxt->vcpu);
018a98db 3595 break;
018a98db 3596 case 0x09: /* wbinvd */
f5f48ee1 3597 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3598 break;
3599 case 0x08: /* invd */
018a98db
AK		 3600 case 0x0d: /* GrpP (prefetch) */
3601 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3602 break;
3603 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3604 switch (c->modrm_reg) {
3605 case 1:
3606 case 5 ... 7:
3607 case 9 ... 15:
54b8486f 3608 emulate_ud(ctxt);
6aebfa6e
GN		 3609 goto done;
3610 }
1a0c7d44 3611 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3612 break;
6aa8b732 3613 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3614 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3615 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3616 emulate_ud(ctxt);
1e470be5
GN		 3617 goto done;
3618 }
b27f3856 3619 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3620 break;
018a98db 3621 case 0x22: /* mov reg, cr */
1a0c7d44 3622 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3623 emulate_gp(ctxt, 0);
0f12244f
GN		 3624 goto done;
3625 }
018a98db
AK		 3626 c->dst.type = OP_NONE;
3627 break;
6aa8b732 3628 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3629 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3630 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3631 emulate_ud(ctxt);
1e470be5
GN		 3632 goto done;
3633 }
35aa5375 3634
b27f3856 3635 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3636 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3637 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3638 /* #UD condition is already handled by the code above */
54b8486f 3639 emulate_gp(ctxt, 0);
338dbc97
GN		 3640 goto done;
3641 }
3642
a01af5ec 3643 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3644 break;
018a98db
AK		 3645 case 0x30:
3646 /* wrmsr */
3647 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3648 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3649 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3650 emulate_gp(ctxt, 0);
fd525365 3651 goto done;
018a98db
AK		 3652 }
3653 rc = X86EMUL_CONTINUE;
018a98db
AK		 3654 break;
3655 case 0x32:
3656 /* rdmsr */
3fb1b5db 3657 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3658 emulate_gp(ctxt, 0);
fd525365 3659 goto done;
018a98db
AK		 3660 } else {
3661 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3662 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3663 }
3664 rc = X86EMUL_CONTINUE;
018a98db 3665 break;
e99f0507 3666 case 0x34: /* sysenter */
3fb1b5db 3667 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3668 if (rc != X86EMUL_CONTINUE)
3669 goto done;
8c604352
AP		 3670 else
3671 goto writeback;
e99f0507
AP		 3672 break;
3673 case 0x35: /* sysexit */
3fb1b5db 3674 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3675 if (rc != X86EMUL_CONTINUE)
3676 goto done;
4668f050
AP		 3677 else
3678 goto writeback;
e99f0507 3679 break;
6aa8b732 3680 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3681 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3682 if (!test_cc(c->b, ctxt->eflags))
3683 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3684 break;
b2833e3c 3685 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3686 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3687 jmp_rel(c, c->src.val);
018a98db 3688 break;
ee45b58e
WY		 3689 case 0x90 ... 0x9f: /* setcc r/m8 */
3690 c->dst.val = test_cc(c->b, ctxt->eflags);
3691 break;
0934ac9d 3692 case 0xa0: /* push fs */
79168fd1 3693 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3694 break;
3695 case 0xa1: /* pop fs */
3696 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3697 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3698 goto done;
3699 break;
7de75248
NK		 3700 case 0xa3:
3701 bt: /* bt */
e4f8e039 3702 c->dst.type = OP_NONE;
e4e03ded
LV		 3703 /* only subword offset */
3704 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3705 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3706 break;
9bf8ea42
GT		 3707 case 0xa4: /* shld imm8, r, r/m */
3708 case 0xa5: /* shld cl, r, r/m */
3709 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3710 break;
0934ac9d 3711 case 0xa8: /* push gs */
79168fd1 3712 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3713 break;
3714 case 0xa9: /* pop gs */
3715 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3716 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3717 goto done;
3718 break;
7de75248
NK		 3719 case 0xab:
3720 bts: /* bts */
05f086f8 3721 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3722 break;
9bf8ea42
GT		 3723 case 0xac: /* shrd imm8, r, r/m */
3724 case 0xad: /* shrd cl, r, r/m */
3725 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3726 break;
2a7c5b8b
GC		 3727 case 0xae: /* clflush */
3728 break;
6aa8b732
AK		 3729 case 0xb0 ... 0xb1: /* cmpxchg */
3730 /*
3731 * Save real source value, then compare EAX against
3732 * destination.
3733 */
e4e03ded
LV		 3734 c->src.orig_val = c->src.val;
3735 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3736 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3737 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3738 /* Success: write back to memory. */
e4e03ded 3739 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3740 } else {
3741 /* Failure: write the value we saw to EAX. */
e4e03ded 3742 c->dst.type = OP_REG;
1a6440ae 3743 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3744 }
3745 break;
09b5f4d3
WY		 3746 case 0xb2: /* lss */
3747 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
3748 if (rc != X86EMUL_CONTINUE)
3749 goto done;
3750 break;
6aa8b732
AK		 3751 case 0xb3:
3752 btr: /* btr */
05f086f8 3753 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3754 break;
09b5f4d3
WY		 3755 case 0xb4: /* lfs */
3756 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
3757 if (rc != X86EMUL_CONTINUE)
3758 goto done;
3759 break;
3760 case 0xb5: /* lgs */
3761 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
3762 if (rc != X86EMUL_CONTINUE)
3763 goto done;
3764 break;
6aa8b732 3765 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3766 c->dst.bytes = c->op_bytes;
3767 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3768 : (u16) c->src.val;
6aa8b732 3769 break;
6aa8b732 3770 case 0xba: /* Grp8 */
e4e03ded 3771 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3772 case 0:
3773 goto bt;
3774 case 1:
3775 goto bts;
3776 case 2:
3777 goto btr;
3778 case 3:
3779 goto btc;
3780 }
3781 break;
7de75248
NK		 3782 case 0xbb:
3783 btc: /* btc */
05f086f8 3784 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3785 break;
d9574a25
WY		 3786 case 0xbc: { /* bsf */
3787 u8 zf;
3788 __asm__ ("bsf %2, %0; setz %1"
3789 : "=r"(c->dst.val), "=q"(zf)
3790 : "r"(c->src.val));
3791 ctxt->eflags &= ~X86_EFLAGS_ZF;
3792 if (zf) {
3793 ctxt->eflags |= X86_EFLAGS_ZF;
3794 c->dst.type = OP_NONE; /* Disable writeback. */
3795 }
3796 break;
3797 }
3798 case 0xbd: { /* bsr */
3799 u8 zf;
3800 __asm__ ("bsr %2, %0; setz %1"
3801 : "=r"(c->dst.val), "=q"(zf)
3802 : "r"(c->src.val));
3803 ctxt->eflags &= ~X86_EFLAGS_ZF;
3804 if (zf) {
3805 ctxt->eflags |= X86_EFLAGS_ZF;
3806 c->dst.type = OP_NONE; /* Disable writeback. */
3807 }
3808 break;
3809 }
6aa8b732 3810 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3811 c->dst.bytes = c->op_bytes;
3812 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3813 (s16) c->src.val;
6aa8b732 3814 break;
92f738a5
WY		 3815 case 0xc0 ... 0xc1: /* xadd */
3816 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3817 /* Write back the register source. */
3818 c->src.val = c->dst.orig_val;
3819 write_register_operand(&c->src);
3820 break;
a012e65a 3821 case 0xc3: /* movnti */
e4e03ded
LV		 3822 c->dst.bytes = c->op_bytes;
3823 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3824 (u64) c->src.val;
a012e65a 3825 break;
6aa8b732 3826 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3827 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3828 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3829 goto done;
3830 break;
91269b8f
AK		 3831 default:
3832 goto cannot_emulate;
6aa8b732
AK		 3833 }
3834 goto writeback;
3835
3836cannot_emulate:
e4e03ded 3837 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3838 return -1;
3839}
Linux kernel - Deliverables
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