projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: switch MUL/DIV to DstXacc
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 133#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
6aa8b732 164
820207c8
AK		 165#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
166
d0e53325
AK		 167#define X2(x...) x, x
168#define X3(x...) X2(x), x
169#define X4(x...) X2(x), X2(x)
170#define X5(x...) X4(x), x
171#define X6(x...) X4(x), X2(x)
172#define X7(x...) X4(x), X3(x)
173#define X8(x...) X4(x), X4(x)
174#define X16(x...) X8(x), X8(x)
83babbca 175
e28bbd44
AK		 176#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177#define FASTOP_SIZE 8
178
179/*
180 * fastop functions have a special calling convention:
181 *
182 * dst: [rdx]:rax (in/out)
183 * src: rbx (in/out)
184 * src2: rcx (in)
185 * flags: rflags (in/out)
186 *
187 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
188 * different operand sizes can be reached by calculation, rather than a jump
189 * table (which would be bigger than the code).
190 *
191 * fastop functions are declared as taking a never-defined fastop parameter,
192 * so they can't be called from C directly.
193 */
194
195struct fastop;
196
d65b1dee 197struct opcode {
b1ea50b2
AK		 198 u64 flags : 56;
199 u64 intercept : 8;
120df890 200 union {
ef65c889 201 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 202 const struct opcode *group;
203 const struct group_dual *gdual;
204 const struct gprefix *gprefix;
045a282c 205 const struct escape *esc;
e28bbd44 206 void (*fastop)(struct fastop *fake);
120df890 207 } u;
d09beabd 208 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 209};
210
211struct group_dual {
212 struct opcode mod012[8];
213 struct opcode mod3[8];
d65b1dee
AK		 214};
215
0d7cdee8
AK		 216struct gprefix {
217 struct opcode pfx_no;
218 struct opcode pfx_66;
219 struct opcode pfx_f2;
220 struct opcode pfx_f3;
221};
222
045a282c
GN		 223struct escape {
224 struct opcode op[8];
225 struct opcode high[64];
226};
227
6aa8b732 228/* EFLAGS bit definitions. */
d4c6a154
GN		 229#define EFLG_ID (1<<21)
230#define EFLG_VIP (1<<20)
231#define EFLG_VIF (1<<19)
232#define EFLG_AC (1<<18)
b1d86143
AP		 233#define EFLG_VM (1<<17)
234#define EFLG_RF (1<<16)
d4c6a154
GN		 235#define EFLG_IOPL (3<<12)
236#define EFLG_NT (1<<14)
6aa8b732
AK		 237#define EFLG_OF (1<<11)
238#define EFLG_DF (1<<10)
b1d86143 239#define EFLG_IF (1<<9)
d4c6a154 240#define EFLG_TF (1<<8)
6aa8b732
AK		 241#define EFLG_SF (1<<7)
242#define EFLG_ZF (1<<6)
243#define EFLG_AF (1<<4)
244#define EFLG_PF (1<<2)
245#define EFLG_CF (1<<0)
246
62bd430e
MG		 247#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
248#define EFLG_RESERVED_ONE_MASK 2
249
dd856efa
AK		 250static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
251{
252 if (!(ctxt->regs_valid & (1 << nr))) {
253 ctxt->regs_valid |= 1 << nr;
254 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
255 }
256 return ctxt->_regs[nr];
257}
258
259static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
260{
261 ctxt->regs_valid |= 1 << nr;
262 ctxt->regs_dirty |= 1 << nr;
263 return &ctxt->_regs[nr];
264}
265
266static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 reg_read(ctxt, nr);
269 return reg_write(ctxt, nr);
270}
271
272static void writeback_registers(struct x86_emulate_ctxt *ctxt)
273{
274 unsigned reg;
275
276 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
277 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
278}
279
280static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
281{
282 ctxt->regs_dirty = 0;
283 ctxt->regs_valid = 0;
284}
285
6aa8b732
AK		 286/*
287 * Instruction emulation:
288 * Most instructions are emulated directly via a fragment of inline assembly
289 * code. This allows us to save/restore EFLAGS and thus very easily pick up
290 * any modified flags.
291 */
292
05b3e0c2 293#if defined(CONFIG_X86_64)
6aa8b732
AK		 294#define _LO32 "k" /* force 32-bit operand */
295#define _STK "%%rsp" /* stack pointer */
296#elif defined(__i386__)
297#define _LO32 "" /* force 32-bit operand */
298#define _STK "%%esp" /* stack pointer */
299#endif
300
301/*
302 * These EFLAGS bits are restored from saved value during emulation, and
303 * any changes are written back to the saved value after emulation.
304 */
305#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
306
307/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 308#define _PRE_EFLAGS(_sav, _msk, _tmp) \
309 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
310 "movl %"_sav",%"_LO32 _tmp"; " \
311 "push %"_tmp"; " \
312 "push %"_tmp"; " \
313 "movl %"_msk",%"_LO32 _tmp"; " \
314 "andl %"_LO32 _tmp",("_STK"); " \
315 "pushf; " \
316 "notl %"_LO32 _tmp"; " \
317 "andl %"_LO32 _tmp",("_STK"); " \
318 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
319 "pop %"_tmp"; " \
320 "orl %"_LO32 _tmp",("_STK"); " \
321 "popf; " \
322 "pop %"_sav"; "
6aa8b732
AK		 323
324/* After executing instruction: write-back necessary bits in EFLAGS. */
325#define _POST_EFLAGS(_sav, _msk, _tmp) \
326 /* _sav |= EFLAGS & _msk; */ \
327 "pushf; " \
328 "pop %"_tmp"; " \
329 "andl %"_msk",%"_LO32 _tmp"; " \
330 "orl %"_LO32 _tmp",%"_sav"; "
331
dda96d8f
AK		 332#ifdef CONFIG_X86_64
333#define ON64(x) x
334#else
335#define ON64(x)
336#endif
337
a31b9cea 338#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 339 do { \
340 __asm__ __volatile__ ( \
341 _PRE_EFLAGS("0", "4", "2") \
342 _op _suffix " %"_x"3,%1; " \
343 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 344 : "=m" ((ctxt)->eflags), \
345 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 346 "=&r" (_tmp) \
a31b9cea 347 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 348 } while (0)
6b7ad61f
AK		 349
350
6aa8b732 351/* Raw emulation: instruction has two explicit operands. */
a31b9cea 352#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 353 do { \
354 unsigned long _tmp; \
355 \
a31b9cea 356 switch ((ctxt)->dst.bytes) { \
6b7ad61f 357 case 2: \
a31b9cea 358 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 359 break; \
360 case 4: \
a31b9cea 361 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 362 break; \
363 case 8: \
a31b9cea 364 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 365 break; \
366 } \
6aa8b732
AK		 367 } while (0)
368
a31b9cea 369#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 370 do { \
6b7ad61f 371 unsigned long _tmp; \
a31b9cea 372 switch ((ctxt)->dst.bytes) { \
6aa8b732 373 case 1: \
a31b9cea 374 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 375 break; \
376 default: \
a31b9cea 377 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 378 _wx, _wy, _lx, _ly, _qx, _qy); \
379 break; \
380 } \
381 } while (0)
382
383/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 384#define emulate_2op_SrcB(ctxt, _op) \
385 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 386
387/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 388#define emulate_2op_SrcV(ctxt, _op) \
389 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 390
391/* Source operand is word, long or quad sized. */
a31b9cea
AK		 392#define emulate_2op_SrcV_nobyte(ctxt, _op) \
393 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 394
d175226a 395/* Instruction has three operands and one operand is stored in ECX register */
29053a60 396#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 397 do { \
398 unsigned long _tmp; \
761441b9
AK		 399 _type _clv = (ctxt)->src2.val; \
400 _type _srcv = (ctxt)->src.val; \
401 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 402 \
403 __asm__ __volatile__ ( \
404 _PRE_EFLAGS("0", "5", "2") \
405 _op _suffix " %4,%1 \n" \
406 _POST_EFLAGS("0", "5", "2") \
761441b9 407 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 408 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
409 ); \
410 \
761441b9
AK		 411 (ctxt)->src2.val = (unsigned long) _clv; \
412 (ctxt)->src2.val = (unsigned long) _srcv; \
413 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 414 } while (0)
415
761441b9 416#define emulate_2op_cl(ctxt, _op) \
7295261c 417 do { \
761441b9 418 switch ((ctxt)->dst.bytes) { \
7295261c 419 case 2: \
29053a60 420 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 421 break; \
422 case 4: \
29053a60 423 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 424 break; \
425 case 8: \
29053a60 426 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 427 break; \
428 } \
d175226a
GT		 429 } while (0)
430
d1eef45d 431#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 432 do { \
433 unsigned long _tmp; \
434 \
dda96d8f
AK		 435 __asm__ __volatile__ ( \
436 _PRE_EFLAGS("0", "3", "2") \
437 _op _suffix " %1; " \
438 _POST_EFLAGS("0", "3", "2") \
d1eef45d 439 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 440 "=&r" (_tmp) \
441 : "i" (EFLAGS_MASK)); \
442 } while (0)
443
444/* Instruction has only one explicit operand (no source operand). */
d1eef45d 445#define emulate_1op(ctxt, _op) \
dda96d8f 446 do { \
d1eef45d
AK		 447 switch ((ctxt)->dst.bytes) { \
448 case 1: __emulate_1op(ctxt, _op, "b"); break; \
449 case 2: __emulate_1op(ctxt, _op, "w"); break; \
450 case 4: __emulate_1op(ctxt, _op, "l"); break; \
451 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 452 } \
453 } while (0)
454
4d758349
AK		 455static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
456
b7d491e7
AK		 457#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
458#define FOP_RET "ret \n\t"
459
460#define FOP_START(op) \
461 extern void em_##op(struct fastop *fake); \
462 asm(".pushsection .text, \"ax\" \n\t" \
463 ".global em_" #op " \n\t" \
464 FOP_ALIGN \
465 "em_" #op ": \n\t"
466
467#define FOP_END \
468 ".popsection")
469
0bdea068
AK		 470#define FOPNOP() FOP_ALIGN FOP_RET
471
b7d491e7
AK		 472#define FOP1E(op, dst) \
473 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
474
475#define FASTOP1(op) \
476 FOP_START(op) \
477 FOP1E(op##b, al) \
478 FOP1E(op##w, ax) \
479 FOP1E(op##l, eax) \
480 ON64(FOP1E(op##q, rax)) \
481 FOP_END
482
f7857f35
AK		 483#define FOP2E(op, dst, src) \
484 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
485
486#define FASTOP2(op) \
487 FOP_START(op) \
488 FOP2E(op##b, al, bl) \
489 FOP2E(op##w, ax, bx) \
490 FOP2E(op##l, eax, ebx) \
491 ON64(FOP2E(op##q, rax, rbx)) \
492 FOP_END
493
11c363ba
AK		 494/* 2 operand, word only */
495#define FASTOP2W(op) \
496 FOP_START(op) \
497 FOPNOP() \
498 FOP2E(op##w, ax, bx) \
499 FOP2E(op##l, eax, ebx) \
500 ON64(FOP2E(op##q, rax, rbx)) \
501 FOP_END
502
007a3b54
AK		 503/* 2 operand, src is CL */
504#define FASTOP2CL(op) \
505 FOP_START(op) \
506 FOP2E(op##b, al, cl) \
507 FOP2E(op##w, ax, cl) \
508 FOP2E(op##l, eax, cl) \
509 ON64(FOP2E(op##q, rax, cl)) \
510 FOP_END
511
0bdea068
AK		 512#define FOP3E(op, dst, src, src2) \
513 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
514
515/* 3-operand, word-only, src2=cl */
516#define FASTOP3WCL(op) \
517 FOP_START(op) \
518 FOPNOP() \
519 FOP3E(op##w, ax, bx, cl) \
520 FOP3E(op##l, eax, ebx, cl) \
521 ON64(FOP3E(op##q, rax, rbx, cl)) \
522 FOP_END
523
9ae9feba
AK		 524/* Special case for SETcc - 1 instruction per cc */
525#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
526
527FOP_START(setcc)
528FOP_SETCC(seto)
529FOP_SETCC(setno)
530FOP_SETCC(setc)
531FOP_SETCC(setnc)
532FOP_SETCC(setz)
533FOP_SETCC(setnz)
534FOP_SETCC(setbe)
535FOP_SETCC(setnbe)
536FOP_SETCC(sets)
537FOP_SETCC(setns)
538FOP_SETCC(setp)
539FOP_SETCC(setnp)
540FOP_SETCC(setl)
541FOP_SETCC(setnl)
542FOP_SETCC(setle)
543FOP_SETCC(setnle)
544FOP_END;
545
326f578f
PB		 546FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
547FOP_END;
548
e8f2b1d6 549#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 550 do { \
551 unsigned long _tmp; \
ab2c5ce6
AK		 552 ulong *rax = &ctxt->dst.val; \
553 ulong *rdx = &ctxt->src.val; \
f6b3597b
AK		 554 \
555 __asm__ __volatile__ ( \
556 _PRE_EFLAGS("0", "5", "1") \
557 "1: \n\t" \
558 _op _suffix " %6; " \
559 "2: \n\t" \
560 _POST_EFLAGS("0", "5", "1") \
561 ".pushsection .fixup,\"ax\" \n\t" \
562 "3: movb $1, %4 \n\t" \
563 "jmp 2b \n\t" \
564 ".popsection \n\t" \
565 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 566 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
567 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
ab2c5ce6 568 : "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
f6b3597b
AK		 569 } while (0)
570
3f9f53b0 571/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 572#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 573 do { \
e8f2b1d6 574 switch((ctxt)->src.bytes) { \
7295261c 575 case 1: \
e8f2b1d6 576 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 577 break; \
578 case 2: \
e8f2b1d6 579 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 580 break; \
581 case 4: \
e8f2b1d6 582 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 583 break; \
584 case 8: ON64( \
e8f2b1d6 585 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 586 break; \
587 } \
588 } while (0)
589
8a76d7f2
JR		 590static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
591 enum x86_intercept intercept,
592 enum x86_intercept_stage stage)
593{
594 struct x86_instruction_info info = {
595 .intercept = intercept,
9dac77fa
AK		 596 .rep_prefix = ctxt->rep_prefix,
597 .modrm_mod = ctxt->modrm_mod,
598 .modrm_reg = ctxt->modrm_reg,
599 .modrm_rm = ctxt->modrm_rm,
600 .src_val = ctxt->src.val64,
601 .src_bytes = ctxt->src.bytes,
602 .dst_bytes = ctxt->dst.bytes,
603 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 604 .next_rip = ctxt->eip,
605 };
606
2953538e 607 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 608}
609
f47cfa31
AK		 610static void assign_masked(ulong *dest, ulong src, ulong mask)
611{
612 *dest = (*dest & ~mask) | (src & mask);
613}
614
9dac77fa 615static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 616{
9dac77fa 617 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 618}
619
f47cfa31
AK		 620static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
621{
622 u16 sel;
623 struct desc_struct ss;
624
625 if (ctxt->mode == X86EMUL_MODE_PROT64)
626 return ~0UL;
627 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
628 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
629}
630
612e89f0
AK		 631static int stack_size(struct x86_emulate_ctxt *ctxt)
632{
633 return (__fls(stack_mask(ctxt)) + 1) >> 3;
634}
635
6aa8b732 636/* Access/update address held in a register, based on addressing mode. */
e4706772 637static inline unsigned long
9dac77fa 638address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 639{
9dac77fa 640 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 641 return reg;
642 else
9dac77fa 643 return reg & ad_mask(ctxt);
e4706772
HH		 644}
645
646static inline unsigned long
9dac77fa 647register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 648{
9dac77fa 649 return address_mask(ctxt, reg);
e4706772
HH		 650}
651
5ad105e5
AK		 652static void masked_increment(ulong *reg, ulong mask, int inc)
653{
654 assign_masked(reg, *reg + inc, mask);
655}
656
7a957275 657static inline void
9dac77fa 658register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 659{
5ad105e5
AK		 660 ulong mask;
661
9dac77fa 662 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 663 mask = ~0UL;
7a957275 664 else
5ad105e5
AK		 665 mask = ad_mask(ctxt);
666 masked_increment(reg, mask, inc);
667}
668
669static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
670{
dd856efa 671 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 672}
6aa8b732 673
9dac77fa 674static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 675{
9dac77fa 676 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 677}
098c937b 678
56697687
AK		 679static u32 desc_limit_scaled(struct desc_struct *desc)
680{
681 u32 limit = get_desc_limit(desc);
682
683 return desc->g ? (limit << 12) | 0xfff : limit;
684}
685
9dac77fa 686static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 687{
9dac77fa
AK		 688 ctxt->has_seg_override = true;
689 ctxt->seg_override = seg;
7a5b56df
AK		 690}
691
7b105ca2 692static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 693{
694 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
695 return 0;
696
7b105ca2 697 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 698}
699
9dac77fa 700static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 701{
9dac77fa 702 if (!ctxt->has_seg_override)
7a5b56df
AK		 703 return 0;
704
9dac77fa 705 return ctxt->seg_override;
7a5b56df
AK		 706}
707
35d3d4a1
AK		 708static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
709 u32 error, bool valid)
54b8486f 710{
da9cb575
AK		 711 ctxt->exception.vector = vec;
712 ctxt->exception.error_code = error;
713 ctxt->exception.error_code_valid = valid;
35d3d4a1 714 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 715}
716
3b88e41a
JR		 717static int emulate_db(struct x86_emulate_ctxt *ctxt)
718{
719 return emulate_exception(ctxt, DB_VECTOR, 0, false);
720}
721
35d3d4a1 722static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 723{
35d3d4a1 724 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 725}
726
618ff15d
AK		 727static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
728{
729 return emulate_exception(ctxt, SS_VECTOR, err, true);
730}
731
35d3d4a1 732static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 733{
35d3d4a1 734 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 735}
736
35d3d4a1 737static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 738{
35d3d4a1 739 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 740}
741
34d1f490
AK		 742static int emulate_de(struct x86_emulate_ctxt *ctxt)
743{
35d3d4a1 744 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 745}
746
1253791d
AK		 747static int emulate_nm(struct x86_emulate_ctxt *ctxt)
748{
749 return emulate_exception(ctxt, NM_VECTOR, 0, false);
750}
751
1aa36616
AK		 752static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
753{
754 u16 selector;
755 struct desc_struct desc;
756
757 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
758 return selector;
759}
760
761static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
762 unsigned seg)
763{
764 u16 dummy;
765 u32 base3;
766 struct desc_struct desc;
767
768 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
769 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
770}
771
1c11b376
AK		 772/*
773 * x86 defines three classes of vector instructions: explicitly
774 * aligned, explicitly unaligned, and the rest, which change behaviour
775 * depending on whether they're AVX encoded or not.
776 *
777 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
778 * subject to the same check.
779 */
780static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
781{
782 if (likely(size < 16))
783 return false;
784
785 if (ctxt->d & Aligned)
786 return true;
787 else if (ctxt->d & Unaligned)
788 return false;
789 else if (ctxt->d & Avx)
790 return false;
791 else
792 return true;
793}
794
3d9b938e 795static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 796 struct segmented_address addr,
3d9b938e 797 unsigned size, bool write, bool fetch,
52fd8b44
AK		 798 ulong *linear)
799{
618ff15d
AK		 800 struct desc_struct desc;
801 bool usable;
52fd8b44 802 ulong la;
618ff15d 803 u32 lim;
1aa36616 804 u16 sel;
3a78a4f4 805 unsigned cpl;
52fd8b44 806
7b105ca2 807 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 808 switch (ctxt->mode) {
618ff15d
AK		 809 case X86EMUL_MODE_PROT64:
810 if (((signed long)la << 16) >> 16 != la)
811 return emulate_gp(ctxt, 0);
812 break;
813 default:
1aa36616
AK		 814 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
815 addr.seg);
618ff15d
AK		 816 if (!usable)
817 goto bad;
58b7825b
GN		 818 /* code segment in protected mode or read-only data segment */
819 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
820 || !(desc.type & 2)) && write)
618ff15d
AK		 821 goto bad;
822 /* unreadable code segment */
3d9b938e 823 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 824 goto bad;
825 lim = desc_limit_scaled(&desc);
826 if ((desc.type & 8) || !(desc.type & 4)) {
827 /* expand-up segment */
828 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
829 goto bad;
830 } else {
fc058680 831 /* expand-down segment */
618ff15d
AK		 832 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
833 goto bad;
834 lim = desc.d ? 0xffffffff : 0xffff;
835 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
836 goto bad;
837 }
717746e3 838 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 839 if (!(desc.type & 8)) {
840 /* data segment */
841 if (cpl > desc.dpl)
842 goto bad;
843 } else if ((desc.type & 8) && !(desc.type & 4)) {
844 /* nonconforming code segment */
845 if (cpl != desc.dpl)
846 goto bad;
847 } else if ((desc.type & 8) && (desc.type & 4)) {
848 /* conforming code segment */
849 if (cpl < desc.dpl)
850 goto bad;
851 }
852 break;
853 }
9dac77fa 854 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 855 la &= (u32)-1;
1c11b376
AK		 856 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
857 return emulate_gp(ctxt, 0);
52fd8b44
AK		 858 *linear = la;
859 return X86EMUL_CONTINUE;
618ff15d
AK		 860bad:
861 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 862 return emulate_ss(ctxt, sel);
618ff15d 863 else
0afbe2f8 864 return emulate_gp(ctxt, sel);
52fd8b44
AK		 865}
866
3d9b938e
NE		 867static int linearize(struct x86_emulate_ctxt *ctxt,
868 struct segmented_address addr,
869 unsigned size, bool write,
870 ulong *linear)
871{
872 return __linearize(ctxt, addr, size, write, false, linear);
873}
874
875
3ca3ac4d
AK		 876static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
877 struct segmented_address addr,
878 void *data,
879 unsigned size)
880{
9fa088f4
AK		 881 int rc;
882 ulong linear;
883
83b8795a 884 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 885 if (rc != X86EMUL_CONTINUE)
886 return rc;
0f65dd70 887 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 888}
889
807941b1
TY		 890/*
891 * Fetch the next byte of the instruction being emulated which is pointed to
892 * by ctxt->_eip, then increment ctxt->_eip.
893 *
894 * Also prefetch the remaining bytes of the instruction without crossing page
895 * boundary if they are not in fetch_cache yet.
896 */
897static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 898{
9dac77fa 899 struct fetch_cache *fc = &ctxt->fetch;
62266869 900 int rc;
2fb53ad8 901 int size, cur_size;
62266869 902
807941b1 903 if (ctxt->_eip == fc->end) {
3d9b938e 904 unsigned long linear;
807941b1
TY		 905 struct segmented_address addr = { .seg = VCPU_SREG_CS,
906 .ea = ctxt->_eip };
2fb53ad8 907 cur_size = fc->end - fc->start;
807941b1
TY		 908 size = min(15UL - cur_size,
909 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 910 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 911 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 912 return rc;
ef5d75cc
TY		 913 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
914 size, &ctxt->exception);
7d88bb48 915 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 916 return rc;
2fb53ad8 917 fc->end += size;
62266869 918 }
807941b1
TY		 919 *dest = fc->data[ctxt->_eip - fc->start];
920 ctxt->_eip++;
3e2815e9 921 return X86EMUL_CONTINUE;
62266869
AK		 922}
923
924static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 925 void *dest, unsigned size)
62266869 926{
3e2815e9 927 int rc;
62266869 928
eb3c79e6 929 /* x86 instructions are limited to 15 bytes. */
7d88bb48 930 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 931 return X86EMUL_UNHANDLEABLE;
62266869 932 while (size--) {
807941b1 933 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 934 if (rc != X86EMUL_CONTINUE)
62266869
AK		 935 return rc;
936 }
3e2815e9 937 return X86EMUL_CONTINUE;
62266869
AK		 938}
939
67cbc90d 940/* Fetch next part of the instruction being emulated. */
e85a1085 941#define insn_fetch(_type, _ctxt) \
67cbc90d 942({ unsigned long _x; \
e85a1085 943 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 944 if (rc != X86EMUL_CONTINUE) \
945 goto done; \
67cbc90d
TY		 946 (_type)_x; \
947})
948
807941b1
TY		 949#define insn_fetch_arr(_arr, _size, _ctxt) \
950({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 951 if (rc != X86EMUL_CONTINUE) \
952 goto done; \
67cbc90d
TY		 953})
954
1e3c5cb0
RR		 955/*
956 * Given the 'reg' portion of a ModRM byte, and a register block, return a
957 * pointer into the block that addresses the relevant register.
958 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
959 */
dd856efa 960static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 961 int highbyte_regs)
6aa8b732
AK		 962{
963 void *p;
964
6aa8b732 965 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 966 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
967 else
968 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 969 return p;
970}
971
972static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 973 struct segmented_address addr,
6aa8b732
AK		 974 u16 *size, unsigned long *address, int op_bytes)
975{
976 int rc;
977
978 if (op_bytes == 2)
979 op_bytes = 3;
980 *address = 0;
3ca3ac4d 981 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 982 if (rc != X86EMUL_CONTINUE)
6aa8b732 983 return rc;
30b31ab6 984 addr.ea += 2;
3ca3ac4d 985 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 986 return rc;
987}
988
34b77652
AK		 989FASTOP2(add);
990FASTOP2(or);
991FASTOP2(adc);
992FASTOP2(sbb);
993FASTOP2(and);
994FASTOP2(sub);
995FASTOP2(xor);
996FASTOP2(cmp);
997FASTOP2(test);
998
999FASTOP3WCL(shld);
1000FASTOP3WCL(shrd);
1001
1002FASTOP2W(imul);
1003
1004FASTOP1(not);
1005FASTOP1(neg);
1006FASTOP1(inc);
1007FASTOP1(dec);
1008
1009FASTOP2CL(rol);
1010FASTOP2CL(ror);
1011FASTOP2CL(rcl);
1012FASTOP2CL(rcr);
1013FASTOP2CL(shl);
1014FASTOP2CL(shr);
1015FASTOP2CL(sar);
1016
1017FASTOP2W(bsf);
1018FASTOP2W(bsr);
1019FASTOP2W(bt);
1020FASTOP2W(bts);
1021FASTOP2W(btr);
1022FASTOP2W(btc);
1023
9ae9feba 1024static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1025{
9ae9feba
AK		 1026 u8 rc;
1027 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1028
9ae9feba 1029 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1030 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1031 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1032 return rc;
bbe9abbd
NK		 1033}
1034
91ff3cb4
AK		 1035static void fetch_register_operand(struct operand *op)
1036{
1037 switch (op->bytes) {
1038 case 1:
1039 op->val = *(u8 *)op->addr.reg;
1040 break;
1041 case 2:
1042 op->val = *(u16 *)op->addr.reg;
1043 break;
1044 case 4:
1045 op->val = *(u32 *)op->addr.reg;
1046 break;
1047 case 8:
1048 op->val = *(u64 *)op->addr.reg;
1049 break;
1050 }
1051}
1052
1253791d
AK		 1053static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1054{
1055 ctxt->ops->get_fpu(ctxt);
1056 switch (reg) {
89a87c67
MK		 1057 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1058 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1059 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1060 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1061 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1062 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1063 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1064 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1065#ifdef CONFIG_X86_64
89a87c67
MK		 1066 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1067 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1068 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1069 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1070 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1071 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1072 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1073 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1074#endif
1075 default: BUG();
1076 }
1077 ctxt->ops->put_fpu(ctxt);
1078}
1079
1080static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1081 int reg)
1082{
1083 ctxt->ops->get_fpu(ctxt);
1084 switch (reg) {
89a87c67
MK		 1085 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1086 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1087 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1088 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1089 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1090 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1091 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1092 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1093#ifdef CONFIG_X86_64
89a87c67
MK		 1094 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1095 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1096 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1097 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1098 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1099 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1100 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1101 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1102#endif
1103 default: BUG();
1104 }
1105 ctxt->ops->put_fpu(ctxt);
1106}
1107
cbe2c9d3
AK		 1108static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1109{
1110 ctxt->ops->get_fpu(ctxt);
1111 switch (reg) {
1112 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1113 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1114 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1115 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1116 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1117 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1118 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1119 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1120 default: BUG();
1121 }
1122 ctxt->ops->put_fpu(ctxt);
1123}
1124
1125static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1126{
1127 ctxt->ops->get_fpu(ctxt);
1128 switch (reg) {
1129 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1130 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1131 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1132 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1133 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1134 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1135 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1136 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1137 default: BUG();
1138 }
1139 ctxt->ops->put_fpu(ctxt);
1140}
1141
045a282c
GN		 1142static int em_fninit(struct x86_emulate_ctxt *ctxt)
1143{
1144 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1145 return emulate_nm(ctxt);
1146
1147 ctxt->ops->get_fpu(ctxt);
1148 asm volatile("fninit");
1149 ctxt->ops->put_fpu(ctxt);
1150 return X86EMUL_CONTINUE;
1151}
1152
1153static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1154{
1155 u16 fcw;
1156
1157 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1158 return emulate_nm(ctxt);
1159
1160 ctxt->ops->get_fpu(ctxt);
1161 asm volatile("fnstcw %0": "+m"(fcw));
1162 ctxt->ops->put_fpu(ctxt);
1163
1164 /* force 2 byte destination */
1165 ctxt->dst.bytes = 2;
1166 ctxt->dst.val = fcw;
1167
1168 return X86EMUL_CONTINUE;
1169}
1170
1171static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1172{
1173 u16 fsw;
1174
1175 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1176 return emulate_nm(ctxt);
1177
1178 ctxt->ops->get_fpu(ctxt);
1179 asm volatile("fnstsw %0": "+m"(fsw));
1180 ctxt->ops->put_fpu(ctxt);
1181
1182 /* force 2 byte destination */
1183 ctxt->dst.bytes = 2;
1184 ctxt->dst.val = fsw;
1185
1186 return X86EMUL_CONTINUE;
1187}
1188
1253791d 1189static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1190 struct operand *op)
3c118e24 1191{
9dac77fa
AK		 1192 unsigned reg = ctxt->modrm_reg;
1193 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1194
9dac77fa
AK		 1195 if (!(ctxt->d & ModRM))
1196 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1197
9dac77fa 1198 if (ctxt->d & Sse) {
1253791d
AK		 1199 op->type = OP_XMM;
1200 op->bytes = 16;
1201 op->addr.xmm = reg;
1202 read_sse_reg(ctxt, &op->vec_val, reg);
1203 return;
1204 }
cbe2c9d3
AK		 1205 if (ctxt->d & Mmx) {
1206 reg &= 7;
1207 op->type = OP_MM;
1208 op->bytes = 8;
1209 op->addr.mm = reg;
1210 return;
1211 }
1253791d 1212
3c118e24 1213 op->type = OP_REG;
2adb5ad9 1214 if (ctxt->d & ByteOp) {
dd856efa 1215 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1216 op->bytes = 1;
1217 } else {
dd856efa 1218 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1219 op->bytes = ctxt->op_bytes;
3c118e24 1220 }
91ff3cb4 1221 fetch_register_operand(op);
3c118e24
AK		 1222 op->orig_val = op->val;
1223}
1224
a6e3407b
AK		 1225static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1226{
1227 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1228 ctxt->modrm_seg = VCPU_SREG_SS;
1229}
1230
1c73ef66 1231static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1232 struct operand *op)
1c73ef66 1233{
1c73ef66 1234 u8 sib;
f5b4edcd 1235 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1236 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1237 ulong modrm_ea = 0;
1c73ef66 1238
9dac77fa
AK		 1239 if (ctxt->rex_prefix) {
1240 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1241 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1242 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1243 }
1244
9dac77fa
AK		 1245 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1246 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1247 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1248 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1249
9dac77fa 1250 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1251 op->type = OP_REG;
9dac77fa 1252 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1253 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1254 if (ctxt->d & Sse) {
1253791d
AK		 1255 op->type = OP_XMM;
1256 op->bytes = 16;
9dac77fa
AK		 1257 op->addr.xmm = ctxt->modrm_rm;
1258 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1259 return rc;
1260 }
cbe2c9d3
AK		 1261 if (ctxt->d & Mmx) {
1262 op->type = OP_MM;
1263 op->bytes = 8;
1264 op->addr.xmm = ctxt->modrm_rm & 7;
1265 return rc;
1266 }
2dbd0dd7 1267 fetch_register_operand(op);
1c73ef66
AK		 1268 return rc;
1269 }
1270
2dbd0dd7
AK		 1271 op->type = OP_MEM;
1272
9dac77fa 1273 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1274 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1275 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1276 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1277 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1278
1279 /* 16-bit ModR/M decode. */
9dac77fa 1280 switch (ctxt->modrm_mod) {
1c73ef66 1281 case 0:
9dac77fa 1282 if (ctxt->modrm_rm == 6)
e85a1085 1283 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1284 break;
1285 case 1:
e85a1085 1286 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1287 break;
1288 case 2:
e85a1085 1289 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1290 break;
1291 }
9dac77fa 1292 switch (ctxt->modrm_rm) {
1c73ef66 1293 case 0:
2dbd0dd7 1294 modrm_ea += bx + si;
1c73ef66
AK		 1295 break;
1296 case 1:
2dbd0dd7 1297 modrm_ea += bx + di;
1c73ef66
AK		 1298 break;
1299 case 2:
2dbd0dd7 1300 modrm_ea += bp + si;
1c73ef66
AK		 1301 break;
1302 case 3:
2dbd0dd7 1303 modrm_ea += bp + di;
1c73ef66
AK		 1304 break;
1305 case 4:
2dbd0dd7 1306 modrm_ea += si;
1c73ef66
AK		 1307 break;
1308 case 5:
2dbd0dd7 1309 modrm_ea += di;
1c73ef66
AK		 1310 break;
1311 case 6:
9dac77fa 1312 if (ctxt->modrm_mod != 0)
2dbd0dd7 1313 modrm_ea += bp;
1c73ef66
AK		 1314 break;
1315 case 7:
2dbd0dd7 1316 modrm_ea += bx;
1c73ef66
AK		 1317 break;
1318 }
9dac77fa
AK		 1319 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1320 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1321 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1322 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1323 } else {
1324 /* 32/64-bit ModR/M decode. */
9dac77fa 1325 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1326 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1327 index_reg |= (sib >> 3) & 7;
1328 base_reg |= sib & 7;
1329 scale = sib >> 6;
1330
9dac77fa 1331 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1332 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1333 else {
dd856efa 1334 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1335 adjust_modrm_seg(ctxt, base_reg);
1336 }
dc71d0f1 1337 if (index_reg != 4)
dd856efa 1338 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1339 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1340 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1341 ctxt->rip_relative = 1;
a6e3407b
AK		 1342 } else {
1343 base_reg = ctxt->modrm_rm;
dd856efa 1344 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1345 adjust_modrm_seg(ctxt, base_reg);
1346 }
9dac77fa 1347 switch (ctxt->modrm_mod) {
1c73ef66 1348 case 0:
9dac77fa 1349 if (ctxt->modrm_rm == 5)
e85a1085 1350 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1351 break;
1352 case 1:
e85a1085 1353 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1354 break;
1355 case 2:
e85a1085 1356 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1357 break;
1358 }
1359 }
90de84f5 1360 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1361done:
1362 return rc;
1363}
1364
1365static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1366 struct operand *op)
1c73ef66 1367{
3e2815e9 1368 int rc = X86EMUL_CONTINUE;
1c73ef66 1369
2dbd0dd7 1370 op->type = OP_MEM;
9dac77fa 1371 switch (ctxt->ad_bytes) {
1c73ef66 1372 case 2:
e85a1085 1373 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1374 break;
1375 case 4:
e85a1085 1376 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1377 break;
1378 case 8:
e85a1085 1379 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1380 break;
1381 }
1382done:
1383 return rc;
1384}
1385
9dac77fa 1386static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1387{
7129eeca 1388 long sv = 0, mask;
35c843c4 1389
9dac77fa
AK		 1390 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1391 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1392
9dac77fa
AK		 1393 if (ctxt->src.bytes == 2)
1394 sv = (s16)ctxt->src.val & (s16)mask;
1395 else if (ctxt->src.bytes == 4)
1396 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1397
9dac77fa 1398 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1399 }
ba7ff2b7
WY		 1400
1401 /* only subword offset */
9dac77fa 1402 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1403}
1404
dde7e6d1 1405static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1406 unsigned long addr, void *dest, unsigned size)
6aa8b732 1407{
dde7e6d1 1408 int rc;
9dac77fa 1409 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1410
f23b070e
XG		 1411 if (mc->pos < mc->end)
1412 goto read_cached;
6aa8b732 1413
f23b070e
XG		 1414 WARN_ON((mc->end + size) >= sizeof(mc->data));
1415
1416 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1417 &ctxt->exception);
1418 if (rc != X86EMUL_CONTINUE)
1419 return rc;
1420
1421 mc->end += size;
1422
1423read_cached:
1424 memcpy(dest, mc->data + mc->pos, size);
1425 mc->pos += size;
dde7e6d1
AK		 1426 return X86EMUL_CONTINUE;
1427}
6aa8b732 1428
3ca3ac4d
AK		 1429static int segmented_read(struct x86_emulate_ctxt *ctxt,
1430 struct segmented_address addr,
1431 void *data,
1432 unsigned size)
1433{
9fa088f4
AK		 1434 int rc;
1435 ulong linear;
1436
83b8795a 1437 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
7b105ca2 1440 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1441}
1442
1443static int segmented_write(struct x86_emulate_ctxt *ctxt,
1444 struct segmented_address addr,
1445 const void *data,
1446 unsigned size)
1447{
9fa088f4
AK		 1448 int rc;
1449 ulong linear;
1450
83b8795a 1451 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1452 if (rc != X86EMUL_CONTINUE)
1453 return rc;
0f65dd70
AK		 1454 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1455 &ctxt->exception);
3ca3ac4d
AK		 1456}
1457
1458static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1459 struct segmented_address addr,
1460 const void *orig_data, const void *data,
1461 unsigned size)
1462{
9fa088f4
AK		 1463 int rc;
1464 ulong linear;
1465
83b8795a 1466 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1467 if (rc != X86EMUL_CONTINUE)
1468 return rc;
0f65dd70
AK		 1469 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1470 size, &ctxt->exception);
3ca3ac4d
AK		 1471}
1472
dde7e6d1 1473static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1474 unsigned int size, unsigned short port,
1475 void *dest)
1476{
9dac77fa 1477 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1478
dde7e6d1 1479 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1480 unsigned int in_page, n;
9dac77fa 1481 unsigned int count = ctxt->rep_prefix ?
dd856efa 1482 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1483 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1484 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1485 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1486 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1487 count);
1488 if (n == 0)
1489 n = 1;
1490 rc->pos = rc->end = 0;
7b105ca2 1491 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1492 return 0;
1493 rc->end = n * size;
6aa8b732
AK		 1494 }
1495
b3356bf0
GN		 1496 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1497 ctxt->dst.data = rc->data + rc->pos;
1498 ctxt->dst.type = OP_MEM_STR;
1499 ctxt->dst.count = (rc->end - rc->pos) / size;
1500 rc->pos = rc->end;
1501 } else {
1502 memcpy(dest, rc->data + rc->pos, size);
1503 rc->pos += size;
1504 }
dde7e6d1
AK		 1505 return 1;
1506}
6aa8b732 1507
7f3d35fd
KW		 1508static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1509 u16 index, struct desc_struct *desc)
1510{
1511 struct desc_ptr dt;
1512 ulong addr;
1513
1514 ctxt->ops->get_idt(ctxt, &dt);
1515
1516 if (dt.size < index * 8 + 7)
1517 return emulate_gp(ctxt, index << 3 | 0x2);
1518
1519 addr = dt.address + index * 8;
1520 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1521 &ctxt->exception);
1522}
1523
dde7e6d1 1524static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1525 u16 selector, struct desc_ptr *dt)
1526{
0225fb50 1527 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1528
dde7e6d1
AK		 1529 if (selector & 1 << 2) {
1530 struct desc_struct desc;
1aa36616
AK		 1531 u16 sel;
1532
dde7e6d1 1533 memset (dt, 0, sizeof *dt);
1aa36616 1534 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1535 return;
e09d082c 1536
dde7e6d1
AK		 1537 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1538 dt->address = get_desc_base(&desc);
1539 } else
4bff1e86 1540 ops->get_gdt(ctxt, dt);
dde7e6d1 1541}
120df890 1542
dde7e6d1
AK		 1543/* allowed just for 8 bytes segments */
1544static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1545 u16 selector, struct desc_struct *desc,
1546 ulong *desc_addr_p)
dde7e6d1
AK		 1547{
1548 struct desc_ptr dt;
1549 u16 index = selector >> 3;
dde7e6d1 1550 ulong addr;
120df890 1551
7b105ca2 1552 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1553
35d3d4a1
AK		 1554 if (dt.size < index * 8 + 7)
1555 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1556
e919464b 1557 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1558 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1559 &ctxt->exception);
dde7e6d1 1560}
ef65c889 1561
dde7e6d1
AK		 1562/* allowed just for 8 bytes segments */
1563static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1564 u16 selector, struct desc_struct *desc)
1565{
1566 struct desc_ptr dt;
1567 u16 index = selector >> 3;
dde7e6d1 1568 ulong addr;
6aa8b732 1569
7b105ca2 1570 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1571
35d3d4a1
AK		 1572 if (dt.size < index * 8 + 7)
1573 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1574
dde7e6d1 1575 addr = dt.address + index * 8;
7b105ca2
TY		 1576 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1577 &ctxt->exception);
dde7e6d1 1578}
c7e75a3d 1579
5601d05b 1580/* Does not support long mode */
dde7e6d1 1581static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1582 u16 selector, int seg)
1583{
869be99c 1584 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1585 u8 dpl, rpl, cpl;
1586 unsigned err_vec = GP_VECTOR;
1587 u32 err_code = 0;
1588 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1589 ulong desc_addr;
dde7e6d1 1590 int ret;
03ebebeb 1591 u16 dummy;
69f55cb1 1592
dde7e6d1 1593 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1594
f8da94e9
KW		 1595 if (ctxt->mode == X86EMUL_MODE_REAL) {
1596 /* set real mode segment descriptor (keep limit etc. for
1597 * unreal mode) */
03ebebeb 1598 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1599 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1600 goto load;
f8da94e9
KW		 1601 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1602 /* VM86 needs a clean new segment descriptor */
1603 set_desc_base(&seg_desc, selector << 4);
1604 set_desc_limit(&seg_desc, 0xffff);
1605 seg_desc.type = 3;
1606 seg_desc.p = 1;
1607 seg_desc.s = 1;
1608 seg_desc.dpl = 3;
1609 goto load;
dde7e6d1
AK		 1610 }
1611
79d5b4c3
AK		 1612 rpl = selector & 3;
1613 cpl = ctxt->ops->cpl(ctxt);
1614
1615 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1616 if ((seg == VCPU_SREG_CS
1617 || (seg == VCPU_SREG_SS
1618 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1619 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1620 && null_selector)
1621 goto exception;
1622
1623 /* TR should be in GDT only */
1624 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1625 goto exception;
1626
1627 if (null_selector) /* for NULL selector skip all following checks */
1628 goto load;
1629
e919464b 1630 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1631 if (ret != X86EMUL_CONTINUE)
1632 return ret;
1633
1634 err_code = selector & 0xfffc;
1635 err_vec = GP_VECTOR;
1636
fc058680 1637 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1638 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1639 goto exception;
1640
1641 if (!seg_desc.p) {
1642 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1643 goto exception;
1644 }
1645
dde7e6d1 1646 dpl = seg_desc.dpl;
dde7e6d1
AK		 1647
1648 switch (seg) {
1649 case VCPU_SREG_SS:
1650 /*
1651 * segment is not a writable data segment or segment
1652 * selector's RPL != CPL or segment selector's RPL != CPL
1653 */
1654 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1655 goto exception;
6aa8b732 1656 break;
dde7e6d1
AK		 1657 case VCPU_SREG_CS:
1658 if (!(seg_desc.type & 8))
1659 goto exception;
1660
1661 if (seg_desc.type & 4) {
1662 /* conforming */
1663 if (dpl > cpl)
1664 goto exception;
1665 } else {
1666 /* nonconforming */
1667 if (rpl > cpl || dpl != cpl)
1668 goto exception;
1669 }
1670 /* CS(RPL) <- CPL */
1671 selector = (selector & 0xfffc) | cpl;
6aa8b732 1672 break;
dde7e6d1
AK		 1673 case VCPU_SREG_TR:
1674 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1675 goto exception;
869be99c
AK		 1676 old_desc = seg_desc;
1677 seg_desc.type |= 2; /* busy */
1678 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1679 sizeof(seg_desc), &ctxt->exception);
1680 if (ret != X86EMUL_CONTINUE)
1681 return ret;
dde7e6d1
AK		 1682 break;
1683 case VCPU_SREG_LDTR:
1684 if (seg_desc.s || seg_desc.type != 2)
1685 goto exception;
1686 break;
1687 default: /* DS, ES, FS, or GS */
4e62417b 1688 /*
dde7e6d1
AK		 1689 * segment is not a data or readable code segment or
1690 * ((segment is a data or nonconforming code segment)
1691 * and (both RPL and CPL > DPL))
4e62417b 1692 */
dde7e6d1
AK		 1693 if ((seg_desc.type & 0xa) == 0x8 ||
1694 (((seg_desc.type & 0xc) != 0xc) &&
1695 (rpl > dpl && cpl > dpl)))
1696 goto exception;
6aa8b732 1697 break;
dde7e6d1
AK		 1698 }
1699
1700 if (seg_desc.s) {
1701 /* mark segment as accessed */
1702 seg_desc.type |= 1;
7b105ca2 1703 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1704 if (ret != X86EMUL_CONTINUE)
1705 return ret;
1706 }
1707load:
7b105ca2 1708 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1709 return X86EMUL_CONTINUE;
1710exception:
1711 emulate_exception(ctxt, err_vec, err_code, true);
1712 return X86EMUL_PROPAGATE_FAULT;
1713}
1714
31be40b3
WY		 1715static void write_register_operand(struct operand *op)
1716{
1717 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1718 switch (op->bytes) {
1719 case 1:
1720 *(u8 *)op->addr.reg = (u8)op->val;
1721 break;
1722 case 2:
1723 *(u16 *)op->addr.reg = (u16)op->val;
1724 break;
1725 case 4:
1726 *op->addr.reg = (u32)op->val;
1727 break; /* 64b: zero-extend */
1728 case 8:
1729 *op->addr.reg = op->val;
1730 break;
1731 }
1732}
1733
fb32b1ed 1734static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1735{
1736 int rc;
dde7e6d1 1737
fb32b1ed 1738 switch (op->type) {
dde7e6d1 1739 case OP_REG:
fb32b1ed 1740 write_register_operand(op);
6aa8b732 1741 break;
dde7e6d1 1742 case OP_MEM:
9dac77fa 1743 if (ctxt->lock_prefix)
3ca3ac4d 1744 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1745 op->addr.mem,
1746 &op->orig_val,
1747 &op->val,
1748 op->bytes);
341de7e3 1749 else
3ca3ac4d 1750 rc = segmented_write(ctxt,
fb32b1ed
AK		 1751 op->addr.mem,
1752 &op->val,
1753 op->bytes);
dde7e6d1
AK		 1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
a682e354 1756 break;
b3356bf0
GN		 1757 case OP_MEM_STR:
1758 rc = segmented_write(ctxt,
fb32b1ed
AK		 1759 op->addr.mem,
1760 op->data,
1761 op->bytes * op->count);
b3356bf0
GN		 1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
1764 break;
1253791d 1765 case OP_XMM:
fb32b1ed 1766 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1767 break;
cbe2c9d3 1768 case OP_MM:
fb32b1ed 1769 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1770 break;
dde7e6d1
AK		 1771 case OP_NONE:
1772 /* no writeback */
414e6277 1773 break;
dde7e6d1 1774 default:
414e6277 1775 break;
6aa8b732 1776 }
dde7e6d1
AK		 1777 return X86EMUL_CONTINUE;
1778}
6aa8b732 1779
51ddff50 1780static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1781{
4179bb02 1782 struct segmented_address addr;
0dc8d10f 1783
5ad105e5 1784 rsp_increment(ctxt, -bytes);
dd856efa 1785 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1786 addr.seg = VCPU_SREG_SS;
1787
51ddff50
AK		 1788 return segmented_write(ctxt, addr, data, bytes);
1789}
1790
1791static int em_push(struct x86_emulate_ctxt *ctxt)
1792{
4179bb02 1793 /* Disable writeback. */
9dac77fa 1794 ctxt->dst.type = OP_NONE;
51ddff50 1795 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1796}
69f55cb1 1797
dde7e6d1 1798static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1799 void *dest, int len)
1800{
dde7e6d1 1801 int rc;
90de84f5 1802 struct segmented_address addr;
8b4caf66 1803
dd856efa 1804 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1805 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1806 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1807 if (rc != X86EMUL_CONTINUE)
1808 return rc;
1809
5ad105e5 1810 rsp_increment(ctxt, len);
dde7e6d1 1811 return rc;
8b4caf66
LV		 1812}
1813
c54fe504
TY		 1814static int em_pop(struct x86_emulate_ctxt *ctxt)
1815{
9dac77fa 1816 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1817}
1818
dde7e6d1 1819static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1820 void *dest, int len)
9de41573
GN		 1821{
1822 int rc;
dde7e6d1
AK		 1823 unsigned long val, change_mask;
1824 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1825 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1826
3b9be3bf 1827 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1828 if (rc != X86EMUL_CONTINUE)
1829 return rc;
9de41573 1830
dde7e6d1
AK		 1831 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1832 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1833
dde7e6d1
AK		 1834 switch(ctxt->mode) {
1835 case X86EMUL_MODE_PROT64:
1836 case X86EMUL_MODE_PROT32:
1837 case X86EMUL_MODE_PROT16:
1838 if (cpl == 0)
1839 change_mask |= EFLG_IOPL;
1840 if (cpl <= iopl)
1841 change_mask |= EFLG_IF;
1842 break;
1843 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1844 if (iopl < 3)
1845 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1846 change_mask |= EFLG_IF;
1847 break;
1848 default: /* real mode */
1849 change_mask |= (EFLG_IOPL | EFLG_IF);
1850 break;
9de41573 1851 }
dde7e6d1
AK		 1852
1853 *(unsigned long *)dest =
1854 (ctxt->eflags & ~change_mask) | (val & change_mask);
1855
1856 return rc;
9de41573
GN		 1857}
1858
62aaa2f0
TY		 1859static int em_popf(struct x86_emulate_ctxt *ctxt)
1860{
9dac77fa
AK		 1861 ctxt->dst.type = OP_REG;
1862 ctxt->dst.addr.reg = &ctxt->eflags;
1863 ctxt->dst.bytes = ctxt->op_bytes;
1864 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1865}
1866
612e89f0
AK		 1867static int em_enter(struct x86_emulate_ctxt *ctxt)
1868{
1869 int rc;
1870 unsigned frame_size = ctxt->src.val;
1871 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1872 ulong rbp;
612e89f0
AK		 1873
1874 if (nesting_level)
1875 return X86EMUL_UNHANDLEABLE;
1876
dd856efa
AK		 1877 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1878 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1879 if (rc != X86EMUL_CONTINUE)
1880 return rc;
dd856efa 1881 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1882 stack_mask(ctxt));
dd856efa
AK		 1883 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1884 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1885 stack_mask(ctxt));
1886 return X86EMUL_CONTINUE;
1887}
1888
f47cfa31
AK		 1889static int em_leave(struct x86_emulate_ctxt *ctxt)
1890{
dd856efa 1891 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1892 stack_mask(ctxt));
dd856efa 1893 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1894}
1895
1cd196ea 1896static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1897{
1cd196ea
AK		 1898 int seg = ctxt->src2.val;
1899
9dac77fa 1900 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1901
4487b3b4 1902 return em_push(ctxt);
7b262e90
GN		 1903}
1904
1cd196ea 1905static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1906{
1cd196ea 1907 int seg = ctxt->src2.val;
dde7e6d1
AK		 1908 unsigned long selector;
1909 int rc;
38ba30ba 1910
9dac77fa 1911 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
1914
7b105ca2 1915 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1916 return rc;
38ba30ba
GN		 1917}
1918
b96a7fad 1919static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1920{
dd856efa 1921 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1922 int rc = X86EMUL_CONTINUE;
1923 int reg = VCPU_REGS_RAX;
38ba30ba 1924
dde7e6d1
AK		 1925 while (reg <= VCPU_REGS_RDI) {
1926 (reg == VCPU_REGS_RSP) ?
dd856efa 1927 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1928
4487b3b4 1929 rc = em_push(ctxt);
dde7e6d1
AK		 1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
38ba30ba 1932
dde7e6d1 1933 ++reg;
38ba30ba 1934 }
38ba30ba 1935
dde7e6d1 1936 return rc;
38ba30ba
GN		 1937}
1938
62aaa2f0
TY		 1939static int em_pushf(struct x86_emulate_ctxt *ctxt)
1940{
9dac77fa 1941 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1942 return em_push(ctxt);
1943}
1944
b96a7fad 1945static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1946{
dde7e6d1
AK		 1947 int rc = X86EMUL_CONTINUE;
1948 int reg = VCPU_REGS_RDI;
38ba30ba 1949
dde7e6d1
AK		 1950 while (reg >= VCPU_REGS_RAX) {
1951 if (reg == VCPU_REGS_RSP) {
5ad105e5 1952 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1953 --reg;
1954 }
38ba30ba 1955
dd856efa 1956 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1957 if (rc != X86EMUL_CONTINUE)
1958 break;
1959 --reg;
38ba30ba 1960 }
dde7e6d1 1961 return rc;
38ba30ba
GN		 1962}
1963
dd856efa 1964static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1965{
0225fb50 1966 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1967 int rc;
6e154e56
MG		 1968 struct desc_ptr dt;
1969 gva_t cs_addr;
1970 gva_t eip_addr;
1971 u16 cs, eip;
6e154e56
MG		 1972
1973 /* TODO: Add limit checks */
9dac77fa 1974 ctxt->src.val = ctxt->eflags;
4487b3b4 1975 rc = em_push(ctxt);
5c56e1cf
AK		 1976 if (rc != X86EMUL_CONTINUE)
1977 return rc;
6e154e56
MG		 1978
1979 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1980
9dac77fa 1981 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1982 rc = em_push(ctxt);
5c56e1cf
AK		 1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
6e154e56 1985
9dac77fa 1986 ctxt->src.val = ctxt->_eip;
4487b3b4 1987 rc = em_push(ctxt);
5c56e1cf
AK		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
1990
4bff1e86 1991 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1992
1993 eip_addr = dt.address + (irq << 2);
1994 cs_addr = dt.address + (irq << 2) + 2;
1995
0f65dd70 1996 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1997 if (rc != X86EMUL_CONTINUE)
1998 return rc;
1999
0f65dd70 2000 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 2001 if (rc != X86EMUL_CONTINUE)
2002 return rc;
2003
7b105ca2 2004 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2005 if (rc != X86EMUL_CONTINUE)
2006 return rc;
2007
9dac77fa 2008 ctxt->_eip = eip;
6e154e56
MG		 2009
2010 return rc;
2011}
2012
dd856efa
AK		 2013int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2014{
2015 int rc;
2016
2017 invalidate_registers(ctxt);
2018 rc = __emulate_int_real(ctxt, irq);
2019 if (rc == X86EMUL_CONTINUE)
2020 writeback_registers(ctxt);
2021 return rc;
2022}
2023
7b105ca2 2024static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2025{
2026 switch(ctxt->mode) {
2027 case X86EMUL_MODE_REAL:
dd856efa 2028 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2029 case X86EMUL_MODE_VM86:
2030 case X86EMUL_MODE_PROT16:
2031 case X86EMUL_MODE_PROT32:
2032 case X86EMUL_MODE_PROT64:
2033 default:
2034 /* Protected mode interrupts unimplemented yet */
2035 return X86EMUL_UNHANDLEABLE;
2036 }
2037}
2038
7b105ca2 2039static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2040{
dde7e6d1
AK		 2041 int rc = X86EMUL_CONTINUE;
2042 unsigned long temp_eip = 0;
2043 unsigned long temp_eflags = 0;
2044 unsigned long cs = 0;
2045 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2046 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2047 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2048 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2049
dde7e6d1 2050 /* TODO: Add stack limit check */
38ba30ba 2051
9dac77fa 2052 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2053
dde7e6d1
AK		 2054 if (rc != X86EMUL_CONTINUE)
2055 return rc;
38ba30ba 2056
35d3d4a1
AK		 2057 if (temp_eip & ~0xffff)
2058 return emulate_gp(ctxt, 0);
38ba30ba 2059
9dac77fa 2060 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2061
dde7e6d1
AK		 2062 if (rc != X86EMUL_CONTINUE)
2063 return rc;
38ba30ba 2064
9dac77fa 2065 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2066
dde7e6d1
AK		 2067 if (rc != X86EMUL_CONTINUE)
2068 return rc;
38ba30ba 2069
7b105ca2 2070 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2071
dde7e6d1
AK		 2072 if (rc != X86EMUL_CONTINUE)
2073 return rc;
38ba30ba 2074
9dac77fa 2075 ctxt->_eip = temp_eip;
38ba30ba 2076
38ba30ba 2077
9dac77fa 2078 if (ctxt->op_bytes == 4)
dde7e6d1 2079 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2080 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2081 ctxt->eflags &= ~0xffff;
2082 ctxt->eflags |= temp_eflags;
38ba30ba 2083 }
dde7e6d1
AK		 2084
2085 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2086 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2087
2088 return rc;
38ba30ba
GN		 2089}
2090
e01991e7 2091static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2092{
dde7e6d1
AK		 2093 switch(ctxt->mode) {
2094 case X86EMUL_MODE_REAL:
7b105ca2 2095 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2096 case X86EMUL_MODE_VM86:
2097 case X86EMUL_MODE_PROT16:
2098 case X86EMUL_MODE_PROT32:
2099 case X86EMUL_MODE_PROT64:
c37eda13 2100 default:
dde7e6d1
AK		 2101 /* iret from protected mode unimplemented yet */
2102 return X86EMUL_UNHANDLEABLE;
c37eda13 2103 }
c37eda13
WY		 2104}
2105
d2f62766
TY		 2106static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2107{
d2f62766
TY		 2108 int rc;
2109 unsigned short sel;
2110
9dac77fa 2111 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2112
7b105ca2 2113 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2114 if (rc != X86EMUL_CONTINUE)
2115 return rc;
2116
9dac77fa
AK		 2117 ctxt->_eip = 0;
2118 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2119 return X86EMUL_CONTINUE;
2120}
2121
3329ece1
AK		 2122static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2123{
2124 u8 ex = 0;
2125
2126 emulate_1op_rax_rdx(ctxt, "mul", ex);
2127 return X86EMUL_CONTINUE;
2128}
2129
2130static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2131{
2132 u8 ex = 0;
2133
2134 emulate_1op_rax_rdx(ctxt, "imul", ex);
2135 return X86EMUL_CONTINUE;
2136}
2137
2138static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2139{
34d1f490 2140 u8 de = 0;
8cdbd2c9 2141
3329ece1
AK		 2142 emulate_1op_rax_rdx(ctxt, "div", de);
2143 if (de)
2144 return emulate_de(ctxt);
2145 return X86EMUL_CONTINUE;
2146}
2147
2148static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2149{
2150 u8 de = 0;
2151
2152 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2153 if (de)
2154 return emulate_de(ctxt);
8c5eee30 2155 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2156}
2157
51187683 2158static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2159{
4179bb02 2160 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2161
9dac77fa 2162 switch (ctxt->modrm_reg) {
d19292e4
MG		 2163 case 2: /* call near abs */ {
2164 long int old_eip;
9dac77fa
AK		 2165 old_eip = ctxt->_eip;
2166 ctxt->_eip = ctxt->src.val;
2167 ctxt->src.val = old_eip;
4487b3b4 2168 rc = em_push(ctxt);
d19292e4
MG		 2169 break;
2170 }
8cdbd2c9 2171 case 4: /* jmp abs */
9dac77fa 2172 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2173 break;
d2f62766
TY		 2174 case 5: /* jmp far */
2175 rc = em_jmp_far(ctxt);
2176 break;
8cdbd2c9 2177 case 6: /* push */
4487b3b4 2178 rc = em_push(ctxt);
8cdbd2c9 2179 break;
8cdbd2c9 2180 }
4179bb02 2181 return rc;
8cdbd2c9
LV		 2182}
2183
e0dac408 2184static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2185{
9dac77fa 2186 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2187
dd856efa
AK		 2188 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2189 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2190 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2191 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2192 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2193 } else {
dd856efa
AK		 2194 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2195 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2196
05f086f8 2197 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2198 }
1b30eaa8 2199 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2200}
2201
ebda02c2
TY		 2202static int em_ret(struct x86_emulate_ctxt *ctxt)
2203{
9dac77fa
AK		 2204 ctxt->dst.type = OP_REG;
2205 ctxt->dst.addr.reg = &ctxt->_eip;
2206 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2207 return em_pop(ctxt);
2208}
2209
e01991e7 2210static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2211{
a77ab5ea
AK		 2212 int rc;
2213 unsigned long cs;
2214
9dac77fa 2215 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2216 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2217 return rc;
9dac77fa
AK		 2218 if (ctxt->op_bytes == 4)
2219 ctxt->_eip = (u32)ctxt->_eip;
2220 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2221 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2222 return rc;
7b105ca2 2223 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2224 return rc;
2225}
2226
e940b5c2
TY		 2227static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2228{
2229 /* Save real source value, then compare EAX against destination. */
2230 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2231 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2232 fastop(ctxt, em_cmp);
e940b5c2
TY		 2233
2234 if (ctxt->eflags & EFLG_ZF) {
2235 /* Success: write back to memory. */
2236 ctxt->dst.val = ctxt->src.orig_val;
2237 } else {
2238 /* Failure: write the value we saw to EAX. */
2239 ctxt->dst.type = OP_REG;
dd856efa 2240 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2241 }
2242 return X86EMUL_CONTINUE;
2243}
2244
d4b4325f 2245static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2246{
d4b4325f 2247 int seg = ctxt->src2.val;
09b5f4d3
WY		 2248 unsigned short sel;
2249 int rc;
2250
9dac77fa 2251 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2252
7b105ca2 2253 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2254 if (rc != X86EMUL_CONTINUE)
2255 return rc;
2256
9dac77fa 2257 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2258 return rc;
2259}
2260
7b105ca2 2261static void
e66bb2cc 2262setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2263 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2264{
e66bb2cc 2265 cs->l = 0; /* will be adjusted later */
79168fd1 2266 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2267 cs->g = 1; /* 4kb granularity */
79168fd1 2268 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2269 cs->type = 0x0b; /* Read, Execute, Accessed */
2270 cs->s = 1;
2271 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2272 cs->p = 1;
2273 cs->d = 1;
99245b50 2274 cs->avl = 0;
e66bb2cc 2275
79168fd1
GN		 2276 set_desc_base(ss, 0); /* flat segment */
2277 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2278 ss->g = 1; /* 4kb granularity */
2279 ss->s = 1;
2280 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2281 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2282 ss->dpl = 0;
79168fd1 2283 ss->p = 1;
99245b50
GN		 2284 ss->l = 0;
2285 ss->avl = 0;
e66bb2cc
AP		 2286}
2287
1a18a69b
AK		 2288static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2289{
2290 u32 eax, ebx, ecx, edx;
2291
2292 eax = ecx = 0;
0017f93a
AK		 2293 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2294 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2295 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2296 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2297}
2298
c2226fc9
SB		 2299static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2300{
0225fb50 2301 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2302 u32 eax, ebx, ecx, edx;
2303
2304 /*
2305 * syscall should always be enabled in longmode - so only become
2306 * vendor specific (cpuid) if other modes are active...
2307 */
2308 if (ctxt->mode == X86EMUL_MODE_PROT64)
2309 return true;
2310
2311 eax = 0x00000000;
2312 ecx = 0x00000000;
0017f93a
AK		 2313 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2314 /*
2315 * Intel ("GenuineIntel")
2316 * remark: Intel CPUs only support "syscall" in 64bit
2317 * longmode. Also an 64bit guest with a
2318 * 32bit compat-app running will #UD !! While this
2319 * behaviour can be fixed (by emulating) into AMD
2320 * response - CPUs of AMD can't behave like Intel.
2321 */
2322 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2323 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2324 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2325 return false;
2326
2327 /* AMD ("AuthenticAMD") */
2328 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2329 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2330 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2331 return true;
2332
2333 /* AMD ("AMDisbetter!") */
2334 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2335 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2336 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2337 return true;
c2226fc9
SB		 2338
2339 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2340 return false;
2341}
2342
e01991e7 2343static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2344{
0225fb50 2345 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2346 struct desc_struct cs, ss;
e66bb2cc 2347 u64 msr_data;
79168fd1 2348 u16 cs_sel, ss_sel;
c2ad2bb3 2349 u64 efer = 0;
e66bb2cc
AP		 2350
2351 /* syscall is not available in real mode */
2e901c4c 2352 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2353 ctxt->mode == X86EMUL_MODE_VM86)
2354 return emulate_ud(ctxt);
e66bb2cc 2355
c2226fc9
SB		 2356 if (!(em_syscall_is_enabled(ctxt)))
2357 return emulate_ud(ctxt);
2358
c2ad2bb3 2359 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2360 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2361
c2226fc9
SB		 2362 if (!(efer & EFER_SCE))
2363 return emulate_ud(ctxt);
2364
717746e3 2365 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2366 msr_data >>= 32;
79168fd1
GN		 2367 cs_sel = (u16)(msr_data & 0xfffc);
2368 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2369
c2ad2bb3 2370 if (efer & EFER_LMA) {
79168fd1 2371 cs.d = 0;
e66bb2cc
AP		 2372 cs.l = 1;
2373 }
1aa36616
AK		 2374 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2375 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2376
dd856efa 2377 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2378 if (efer & EFER_LMA) {
e66bb2cc 2379#ifdef CONFIG_X86_64
dd856efa 2380 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2381
717746e3 2382 ops->get_msr(ctxt,
3fb1b5db
GN		 2383 ctxt->mode == X86EMUL_MODE_PROT64 ?
2384 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2385 ctxt->_eip = msr_data;
e66bb2cc 2386
717746e3 2387 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2388 ctxt->eflags &= ~(msr_data | EFLG_RF);
2389#endif
2390 } else {
2391 /* legacy mode */
717746e3 2392 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2393 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2394
2395 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2396 }
2397
e54cfa97 2398 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2399}
2400
e01991e7 2401static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2402{
0225fb50 2403 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2404 struct desc_struct cs, ss;
8c604352 2405 u64 msr_data;
79168fd1 2406 u16 cs_sel, ss_sel;
c2ad2bb3 2407 u64 efer = 0;
8c604352 2408
7b105ca2 2409 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2410 /* inject #GP if in real mode */
35d3d4a1
AK		 2411 if (ctxt->mode == X86EMUL_MODE_REAL)
2412 return emulate_gp(ctxt, 0);
8c604352 2413
1a18a69b
AK		 2414 /*
2415 * Not recognized on AMD in compat mode (but is recognized in legacy
2416 * mode).
2417 */
2418 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2419 && !vendor_intel(ctxt))
2420 return emulate_ud(ctxt);
2421
8c604352
AP		 2422 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2423 * Therefore, we inject an #UD.
2424 */
35d3d4a1
AK		 2425 if (ctxt->mode == X86EMUL_MODE_PROT64)
2426 return emulate_ud(ctxt);
8c604352 2427
7b105ca2 2428 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2429
717746e3 2430 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2431 switch (ctxt->mode) {
2432 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2433 if ((msr_data & 0xfffc) == 0x0)
2434 return emulate_gp(ctxt, 0);
8c604352
AP		 2435 break;
2436 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2437 if (msr_data == 0x0)
2438 return emulate_gp(ctxt, 0);
8c604352 2439 break;
9d1b39a9
GN		 2440 default:
2441 break;
8c604352
AP		 2442 }
2443
2444 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2445 cs_sel = (u16)msr_data;
2446 cs_sel &= ~SELECTOR_RPL_MASK;
2447 ss_sel = cs_sel + 8;
2448 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2449 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2450 cs.d = 0;
8c604352
AP		 2451 cs.l = 1;
2452 }
2453
1aa36616
AK		 2454 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2455 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2456
717746e3 2457 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2458 ctxt->_eip = msr_data;
8c604352 2459
717746e3 2460 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2461 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2462
e54cfa97 2463 return X86EMUL_CONTINUE;
8c604352
AP		 2464}
2465
e01991e7 2466static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2467{
0225fb50 2468 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2469 struct desc_struct cs, ss;
4668f050
AP		 2470 u64 msr_data;
2471 int usermode;
1249b96e 2472 u16 cs_sel = 0, ss_sel = 0;
4668f050 2473
a0044755
GN		 2474 /* inject #GP if in real mode or Virtual 8086 mode */
2475 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2476 ctxt->mode == X86EMUL_MODE_VM86)
2477 return emulate_gp(ctxt, 0);
4668f050 2478
7b105ca2 2479 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2480
9dac77fa 2481 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2482 usermode = X86EMUL_MODE_PROT64;
2483 else
2484 usermode = X86EMUL_MODE_PROT32;
2485
2486 cs.dpl = 3;
2487 ss.dpl = 3;
717746e3 2488 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2489 switch (usermode) {
2490 case X86EMUL_MODE_PROT32:
79168fd1 2491 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2492 if ((msr_data & 0xfffc) == 0x0)
2493 return emulate_gp(ctxt, 0);
79168fd1 2494 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2495 break;
2496 case X86EMUL_MODE_PROT64:
79168fd1 2497 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2498 if (msr_data == 0x0)
2499 return emulate_gp(ctxt, 0);
79168fd1
GN		 2500 ss_sel = cs_sel + 8;
2501 cs.d = 0;
4668f050
AP		 2502 cs.l = 1;
2503 break;
2504 }
79168fd1
GN		 2505 cs_sel |= SELECTOR_RPL_MASK;
2506 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2507
1aa36616
AK		 2508 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2509 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2510
dd856efa
AK		 2511 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2512 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2513
e54cfa97 2514 return X86EMUL_CONTINUE;
4668f050
AP		 2515}
2516
7b105ca2 2517static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2518{
2519 int iopl;
2520 if (ctxt->mode == X86EMUL_MODE_REAL)
2521 return false;
2522 if (ctxt->mode == X86EMUL_MODE_VM86)
2523 return true;
2524 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2525 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2526}
2527
2528static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2529 u16 port, u16 len)
2530{
0225fb50 2531 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2532 struct desc_struct tr_seg;
5601d05b 2533 u32 base3;
f850e2e6 2534 int r;
1aa36616 2535 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2536 unsigned mask = (1 << len) - 1;
5601d05b 2537 unsigned long base;
f850e2e6 2538
1aa36616 2539 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2540 if (!tr_seg.p)
f850e2e6 2541 return false;
79168fd1 2542 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2543 return false;
5601d05b
GN		 2544 base = get_desc_base(&tr_seg);
2545#ifdef CONFIG_X86_64
2546 base |= ((u64)base3) << 32;
2547#endif
0f65dd70 2548 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2549 if (r != X86EMUL_CONTINUE)
2550 return false;
79168fd1 2551 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2552 return false;
0f65dd70 2553 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2554 if (r != X86EMUL_CONTINUE)
2555 return false;
2556 if ((perm >> bit_idx) & mask)
2557 return false;
2558 return true;
2559}
2560
2561static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2562 u16 port, u16 len)
2563{
4fc40f07
GN		 2564 if (ctxt->perm_ok)
2565 return true;
2566
7b105ca2
TY		 2567 if (emulator_bad_iopl(ctxt))
2568 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2569 return false;
4fc40f07
GN		 2570
2571 ctxt->perm_ok = true;
2572
f850e2e6
GN		 2573 return true;
2574}
2575
38ba30ba 2576static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2577 struct tss_segment_16 *tss)
2578{
9dac77fa 2579 tss->ip = ctxt->_eip;
38ba30ba 2580 tss->flag = ctxt->eflags;
dd856efa
AK		 2581 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2582 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2583 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2584 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2585 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2586 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2587 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2588 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2589
1aa36616
AK		 2590 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2591 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2592 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2593 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2594 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2595}
2596
2597static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2598 struct tss_segment_16 *tss)
2599{
38ba30ba
GN		 2600 int ret;
2601
9dac77fa 2602 ctxt->_eip = tss->ip;
38ba30ba 2603 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2604 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2605 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2606 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2607 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2608 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2609 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2610 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2611 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2612
2613 /*
2614 * SDM says that segment selectors are loaded before segment
2615 * descriptors
2616 */
1aa36616
AK		 2617 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2618 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2619 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2620 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2621 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2622
2623 /*
fc058680 2624 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2625 * it is handled in a context of new task
2626 */
7b105ca2 2627 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2628 if (ret != X86EMUL_CONTINUE)
2629 return ret;
7b105ca2 2630 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2631 if (ret != X86EMUL_CONTINUE)
2632 return ret;
7b105ca2 2633 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2634 if (ret != X86EMUL_CONTINUE)
2635 return ret;
7b105ca2 2636 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2637 if (ret != X86EMUL_CONTINUE)
2638 return ret;
7b105ca2 2639 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2640 if (ret != X86EMUL_CONTINUE)
2641 return ret;
2642
2643 return X86EMUL_CONTINUE;
2644}
2645
2646static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2647 u16 tss_selector, u16 old_tss_sel,
2648 ulong old_tss_base, struct desc_struct *new_desc)
2649{
0225fb50 2650 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2651 struct tss_segment_16 tss_seg;
2652 int ret;
bcc55cba 2653 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2654
0f65dd70 2655 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2656 &ctxt->exception);
db297e3d 2657 if (ret != X86EMUL_CONTINUE)
38ba30ba 2658 /* FIXME: need to provide precise fault address */
38ba30ba 2659 return ret;
38ba30ba 2660
7b105ca2 2661 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2662
0f65dd70 2663 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2664 &ctxt->exception);
db297e3d 2665 if (ret != X86EMUL_CONTINUE)
38ba30ba 2666 /* FIXME: need to provide precise fault address */
38ba30ba 2667 return ret;
38ba30ba 2668
0f65dd70 2669 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2670 &ctxt->exception);
db297e3d 2671 if (ret != X86EMUL_CONTINUE)
38ba30ba 2672 /* FIXME: need to provide precise fault address */
38ba30ba 2673 return ret;
38ba30ba
GN		 2674
2675 if (old_tss_sel != 0xffff) {
2676 tss_seg.prev_task_link = old_tss_sel;
2677
0f65dd70 2678 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2679 &tss_seg.prev_task_link,
2680 sizeof tss_seg.prev_task_link,
0f65dd70 2681 &ctxt->exception);
db297e3d 2682 if (ret != X86EMUL_CONTINUE)
38ba30ba 2683 /* FIXME: need to provide precise fault address */
38ba30ba 2684 return ret;
38ba30ba
GN		 2685 }
2686
7b105ca2 2687 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2688}
2689
2690static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2691 struct tss_segment_32 *tss)
2692{
7b105ca2 2693 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2694 tss->eip = ctxt->_eip;
38ba30ba 2695 tss->eflags = ctxt->eflags;
dd856efa
AK		 2696 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2697 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2698 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2699 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2700 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2701 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2702 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2703 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2704
1aa36616
AK		 2705 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2706 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2707 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2708 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2709 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2710 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2711 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2712}
2713
2714static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2715 struct tss_segment_32 *tss)
2716{
38ba30ba
GN		 2717 int ret;
2718
7b105ca2 2719 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2720 return emulate_gp(ctxt, 0);
9dac77fa 2721 ctxt->_eip = tss->eip;
38ba30ba 2722 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2723
2724 /* General purpose registers */
dd856efa
AK		 2725 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2726 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2727 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2728 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2729 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2730 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2731 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2732 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2733
2734 /*
2735 * SDM says that segment selectors are loaded before segment
2736 * descriptors
2737 */
1aa36616
AK		 2738 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2739 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2740 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2741 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2742 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2743 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2744 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2745
4cee4798
KW		 2746 /*
2747 * If we're switching between Protected Mode and VM86, we need to make
2748 * sure to update the mode before loading the segment descriptors so
2749 * that the selectors are interpreted correctly.
2750 *
2751 * Need to get rflags to the vcpu struct immediately because it
2752 * influences the CPL which is checked at least when loading the segment
2753 * descriptors and when pushing an error code to the new kernel stack.
2754 *
2755 * TODO Introduce a separate ctxt->ops->set_cpl callback
2756 */
2757 if (ctxt->eflags & X86_EFLAGS_VM)
2758 ctxt->mode = X86EMUL_MODE_VM86;
2759 else
2760 ctxt->mode = X86EMUL_MODE_PROT32;
2761
2762 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2763
38ba30ba
GN		 2764 /*
2765 * Now load segment descriptors. If fault happenes at this stage
2766 * it is handled in a context of new task
2767 */
7b105ca2 2768 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2769 if (ret != X86EMUL_CONTINUE)
2770 return ret;
7b105ca2 2771 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2772 if (ret != X86EMUL_CONTINUE)
2773 return ret;
7b105ca2 2774 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2775 if (ret != X86EMUL_CONTINUE)
2776 return ret;
7b105ca2 2777 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2778 if (ret != X86EMUL_CONTINUE)
2779 return ret;
7b105ca2 2780 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2781 if (ret != X86EMUL_CONTINUE)
2782 return ret;
7b105ca2 2783 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2784 if (ret != X86EMUL_CONTINUE)
2785 return ret;
7b105ca2 2786 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2787 if (ret != X86EMUL_CONTINUE)
2788 return ret;
2789
2790 return X86EMUL_CONTINUE;
2791}
2792
2793static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2794 u16 tss_selector, u16 old_tss_sel,
2795 ulong old_tss_base, struct desc_struct *new_desc)
2796{
0225fb50 2797 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2798 struct tss_segment_32 tss_seg;
2799 int ret;
bcc55cba 2800 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2801
0f65dd70 2802 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2803 &ctxt->exception);
db297e3d 2804 if (ret != X86EMUL_CONTINUE)
38ba30ba 2805 /* FIXME: need to provide precise fault address */
38ba30ba 2806 return ret;
38ba30ba 2807
7b105ca2 2808 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2809
0f65dd70 2810 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2811 &ctxt->exception);
db297e3d 2812 if (ret != X86EMUL_CONTINUE)
38ba30ba 2813 /* FIXME: need to provide precise fault address */
38ba30ba 2814 return ret;
38ba30ba 2815
0f65dd70 2816 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2817 &ctxt->exception);
db297e3d 2818 if (ret != X86EMUL_CONTINUE)
38ba30ba 2819 /* FIXME: need to provide precise fault address */
38ba30ba 2820 return ret;
38ba30ba
GN		 2821
2822 if (old_tss_sel != 0xffff) {
2823 tss_seg.prev_task_link = old_tss_sel;
2824
0f65dd70 2825 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2826 &tss_seg.prev_task_link,
2827 sizeof tss_seg.prev_task_link,
0f65dd70 2828 &ctxt->exception);
db297e3d 2829 if (ret != X86EMUL_CONTINUE)
38ba30ba 2830 /* FIXME: need to provide precise fault address */
38ba30ba 2831 return ret;
38ba30ba
GN		 2832 }
2833
7b105ca2 2834 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2835}
2836
2837static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2838 u16 tss_selector, int idt_index, int reason,
e269fb21 2839 bool has_error_code, u32 error_code)
38ba30ba 2840{
0225fb50 2841 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2842 struct desc_struct curr_tss_desc, next_tss_desc;
2843 int ret;
1aa36616 2844 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2845 ulong old_tss_base =
4bff1e86 2846 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2847 u32 desc_limit;
e919464b 2848 ulong desc_addr;
38ba30ba
GN		 2849
2850 /* FIXME: old_tss_base == ~0 ? */
2851
e919464b 2852 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2853 if (ret != X86EMUL_CONTINUE)
2854 return ret;
e919464b 2855 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2856 if (ret != X86EMUL_CONTINUE)
2857 return ret;
2858
2859 /* FIXME: check that next_tss_desc is tss */
2860
7f3d35fd
KW		 2861 /*
2862 * Check privileges. The three cases are task switch caused by...
2863 *
2864 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2865 * 2. Exception/IRQ/iret: No check is performed
fc058680 2866 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2867 */
2868 if (reason == TASK_SWITCH_GATE) {
2869 if (idt_index != -1) {
2870 /* Software interrupts */
2871 struct desc_struct task_gate_desc;
2872 int dpl;
2873
2874 ret = read_interrupt_descriptor(ctxt, idt_index,
2875 &task_gate_desc);
2876 if (ret != X86EMUL_CONTINUE)
2877 return ret;
2878
2879 dpl = task_gate_desc.dpl;
2880 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2881 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2882 }
2883 } else if (reason != TASK_SWITCH_IRET) {
2884 int dpl = next_tss_desc.dpl;
2885 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2886 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2887 }
2888
7f3d35fd 2889
ceffb459
GN		 2890 desc_limit = desc_limit_scaled(&next_tss_desc);
2891 if (!next_tss_desc.p ||
2892 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2893 desc_limit < 0x2b)) {
54b8486f 2894 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2895 return X86EMUL_PROPAGATE_FAULT;
2896 }
2897
2898 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2899 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2900 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2901 }
2902
2903 if (reason == TASK_SWITCH_IRET)
2904 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2905
2906 /* set back link to prev task only if NT bit is set in eflags
fc058680 2907 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2908 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2909 old_tss_sel = 0xffff;
2910
2911 if (next_tss_desc.type & 8)
7b105ca2 2912 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2913 old_tss_base, &next_tss_desc);
2914 else
7b105ca2 2915 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2916 old_tss_base, &next_tss_desc);
0760d448
JK		 2917 if (ret != X86EMUL_CONTINUE)
2918 return ret;
38ba30ba
GN		 2919
2920 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2921 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2922
2923 if (reason != TASK_SWITCH_IRET) {
2924 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2925 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2926 }
2927
717746e3 2928 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2929 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2930
e269fb21 2931 if (has_error_code) {
9dac77fa
AK		 2932 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2933 ctxt->lock_prefix = 0;
2934 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2935 ret = em_push(ctxt);
e269fb21
JK		 2936 }
2937
38ba30ba
GN		 2938 return ret;
2939}
2940
2941int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2942 u16 tss_selector, int idt_index, int reason,
e269fb21 2943 bool has_error_code, u32 error_code)
38ba30ba 2944{
38ba30ba
GN		 2945 int rc;
2946
dd856efa 2947 invalidate_registers(ctxt);
9dac77fa
AK		 2948 ctxt->_eip = ctxt->eip;
2949 ctxt->dst.type = OP_NONE;
38ba30ba 2950
7f3d35fd 2951 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2952 has_error_code, error_code);
38ba30ba 2953
dd856efa 2954 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2955 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2956 writeback_registers(ctxt);
2957 }
38ba30ba 2958
a0c0ab2f 2959 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2960}
2961
f3bd64c6
GN		 2962static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2963 struct operand *op)
a682e354 2964{
b3356bf0 2965 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2966
dd856efa
AK		 2967 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2968 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2969}
2970
7af04fc0
AK		 2971static int em_das(struct x86_emulate_ctxt *ctxt)
2972{
7af04fc0
AK		 2973 u8 al, old_al;
2974 bool af, cf, old_cf;
2975
2976 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2977 al = ctxt->dst.val;
7af04fc0
AK		 2978
2979 old_al = al;
2980 old_cf = cf;
2981 cf = false;
2982 af = ctxt->eflags & X86_EFLAGS_AF;
2983 if ((al & 0x0f) > 9 || af) {
2984 al -= 6;
2985 cf = old_cf | (al >= 250);
2986 af = true;
2987 } else {
2988 af = false;
2989 }
2990 if (old_al > 0x99 || old_cf) {
2991 al -= 0x60;
2992 cf = true;
2993 }
2994
9dac77fa 2995 ctxt->dst.val = al;
7af04fc0 2996 /* Set PF, ZF, SF */
9dac77fa
AK		 2997 ctxt->src.type = OP_IMM;
2998 ctxt->src.val = 0;
2999 ctxt->src.bytes = 1;
158de57f 3000 fastop(ctxt, em_or);
7af04fc0
AK		 3001 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3002 if (cf)
3003 ctxt->eflags |= X86_EFLAGS_CF;
3004 if (af)
3005 ctxt->eflags |= X86_EFLAGS_AF;
3006 return X86EMUL_CONTINUE;
3007}
3008
a035d5c6
PB		 3009static int em_aam(struct x86_emulate_ctxt *ctxt)
3010{
3011 u8 al, ah;
3012
3013 if (ctxt->src.val == 0)
3014 return emulate_de(ctxt);
3015
3016 al = ctxt->dst.val & 0xff;
3017 ah = al / ctxt->src.val;
3018 al %= ctxt->src.val;
3019
3020 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3021
3022 /* Set PF, ZF, SF */
3023 ctxt->src.type = OP_IMM;
3024 ctxt->src.val = 0;
3025 ctxt->src.bytes = 1;
3026 fastop(ctxt, em_or);
3027
3028 return X86EMUL_CONTINUE;
3029}
3030
7f662273
GN		 3031static int em_aad(struct x86_emulate_ctxt *ctxt)
3032{
3033 u8 al = ctxt->dst.val & 0xff;
3034 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3035
3036 al = (al + (ah * ctxt->src.val)) & 0xff;
3037
3038 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3039
f583c29b
GN		 3040 /* Set PF, ZF, SF */
3041 ctxt->src.type = OP_IMM;
3042 ctxt->src.val = 0;
3043 ctxt->src.bytes = 1;
3044 fastop(ctxt, em_or);
7f662273
GN		 3045
3046 return X86EMUL_CONTINUE;
3047}
3048
d4ddafcd
TY		 3049static int em_call(struct x86_emulate_ctxt *ctxt)
3050{
3051 long rel = ctxt->src.val;
3052
3053 ctxt->src.val = (unsigned long)ctxt->_eip;
3054 jmp_rel(ctxt, rel);
3055 return em_push(ctxt);
3056}
3057
0ef753b8
AK		 3058static int em_call_far(struct x86_emulate_ctxt *ctxt)
3059{
0ef753b8
AK		 3060 u16 sel, old_cs;
3061 ulong old_eip;
3062 int rc;
3063
1aa36616 3064 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3065 old_eip = ctxt->_eip;
0ef753b8 3066
9dac77fa 3067 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3068 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3069 return X86EMUL_CONTINUE;
3070
9dac77fa
AK		 3071 ctxt->_eip = 0;
3072 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3073
9dac77fa 3074 ctxt->src.val = old_cs;
4487b3b4 3075 rc = em_push(ctxt);
0ef753b8
AK		 3076 if (rc != X86EMUL_CONTINUE)
3077 return rc;
3078
9dac77fa 3079 ctxt->src.val = old_eip;
4487b3b4 3080 return em_push(ctxt);
0ef753b8
AK		 3081}
3082
40ece7c7
AK		 3083static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3084{
40ece7c7
AK		 3085 int rc;
3086
9dac77fa
AK		 3087 ctxt->dst.type = OP_REG;
3088 ctxt->dst.addr.reg = &ctxt->_eip;
3089 ctxt->dst.bytes = ctxt->op_bytes;
3090 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3091 if (rc != X86EMUL_CONTINUE)
3092 return rc;
5ad105e5 3093 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3094 return X86EMUL_CONTINUE;
3095}
3096
e4f973ae
TY		 3097static int em_xchg(struct x86_emulate_ctxt *ctxt)
3098{
e4f973ae 3099 /* Write back the register source. */
9dac77fa
AK		 3100 ctxt->src.val = ctxt->dst.val;
3101 write_register_operand(&ctxt->src);
e4f973ae
TY		 3102
3103 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3104 ctxt->dst.val = ctxt->src.orig_val;
3105 ctxt->lock_prefix = 1;
e4f973ae
TY		 3106 return X86EMUL_CONTINUE;
3107}
3108
5c82aa29
AK		 3109static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3110{
9dac77fa 3111 ctxt->dst.val = ctxt->src2.val;
4d758349 3112 return fastop(ctxt, em_imul);
5c82aa29
AK		 3113}
3114
61429142
AK		 3115static int em_cwd(struct x86_emulate_ctxt *ctxt)
3116{
9dac77fa
AK		 3117 ctxt->dst.type = OP_REG;
3118 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3119 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3120 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3121
3122 return X86EMUL_CONTINUE;
3123}
3124
48bb5d3c
AK		 3125static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3126{
48bb5d3c
AK		 3127 u64 tsc = 0;
3128
717746e3 3129 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3130 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3131 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3132 return X86EMUL_CONTINUE;
3133}
3134
222d21aa
AK		 3135static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3136{
3137 u64 pmc;
3138
dd856efa 3139 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3140 return emulate_gp(ctxt, 0);
dd856efa
AK		 3141 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3142 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3143 return X86EMUL_CONTINUE;
3144}
3145
b9eac5f4
AK		 3146static int em_mov(struct x86_emulate_ctxt *ctxt)
3147{
49597d81 3148 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3149 return X86EMUL_CONTINUE;
3150}
3151
bc00f8d2
TY		 3152static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3153{
3154 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3155 return emulate_gp(ctxt, 0);
3156
3157 /* Disable writeback. */
3158 ctxt->dst.type = OP_NONE;
3159 return X86EMUL_CONTINUE;
3160}
3161
3162static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3163{
3164 unsigned long val;
3165
3166 if (ctxt->mode == X86EMUL_MODE_PROT64)
3167 val = ctxt->src.val & ~0ULL;
3168 else
3169 val = ctxt->src.val & ~0U;
3170
3171 /* #UD condition is already handled. */
3172 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3173 return emulate_gp(ctxt, 0);
3174
3175 /* Disable writeback. */
3176 ctxt->dst.type = OP_NONE;
3177 return X86EMUL_CONTINUE;
3178}
3179
e1e210b0
TY		 3180static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3181{
3182 u64 msr_data;
3183
dd856efa
AK		 3184 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3185 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3186 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3187 return emulate_gp(ctxt, 0);
3188
3189 return X86EMUL_CONTINUE;
3190}
3191
3192static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3193{
3194 u64 msr_data;
3195
dd856efa 3196 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3197 return emulate_gp(ctxt, 0);
3198
dd856efa
AK		 3199 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3200 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3201 return X86EMUL_CONTINUE;
3202}
3203
1bd5f469
TY		 3204static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3205{
9dac77fa 3206 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3207 return emulate_ud(ctxt);
3208
9dac77fa 3209 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3210 return X86EMUL_CONTINUE;
3211}
3212
3213static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3214{
9dac77fa 3215 u16 sel = ctxt->src.val;
1bd5f469 3216
9dac77fa 3217 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3218 return emulate_ud(ctxt);
3219
9dac77fa 3220 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3221 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3222
3223 /* Disable writeback. */
9dac77fa
AK		 3224 ctxt->dst.type = OP_NONE;
3225 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3226}
3227
a14e579f
AK		 3228static int em_lldt(struct x86_emulate_ctxt *ctxt)
3229{
3230 u16 sel = ctxt->src.val;
3231
3232 /* Disable writeback. */
3233 ctxt->dst.type = OP_NONE;
3234 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3235}
3236
80890006
AK		 3237static int em_ltr(struct x86_emulate_ctxt *ctxt)
3238{
3239 u16 sel = ctxt->src.val;
3240
3241 /* Disable writeback. */
3242 ctxt->dst.type = OP_NONE;
3243 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3244}
3245
38503911
AK		 3246static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3247{
9fa088f4
AK		 3248 int rc;
3249 ulong linear;
3250
9dac77fa 3251 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3252 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3253 ctxt->ops->invlpg(ctxt, linear);
38503911 3254 /* Disable writeback. */
9dac77fa 3255 ctxt->dst.type = OP_NONE;
38503911
AK		 3256 return X86EMUL_CONTINUE;
3257}
3258
2d04a05b
AK		 3259static int em_clts(struct x86_emulate_ctxt *ctxt)
3260{
3261 ulong cr0;
3262
3263 cr0 = ctxt->ops->get_cr(ctxt, 0);
3264 cr0 &= ~X86_CR0_TS;
3265 ctxt->ops->set_cr(ctxt, 0, cr0);
3266 return X86EMUL_CONTINUE;
3267}
3268
26d05cc7
AK		 3269static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3270{
26d05cc7
AK		 3271 int rc;
3272
9dac77fa 3273 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3274 return X86EMUL_UNHANDLEABLE;
3275
3276 rc = ctxt->ops->fix_hypercall(ctxt);
3277 if (rc != X86EMUL_CONTINUE)
3278 return rc;
3279
3280 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3281 ctxt->_eip = ctxt->eip;
26d05cc7 3282 /* Disable writeback. */
9dac77fa 3283 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3284 return X86EMUL_CONTINUE;
3285}
3286
96051572
AK		 3287static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3288 void (*get)(struct x86_emulate_ctxt *ctxt,
3289 struct desc_ptr *ptr))
3290{
3291 struct desc_ptr desc_ptr;
3292
3293 if (ctxt->mode == X86EMUL_MODE_PROT64)
3294 ctxt->op_bytes = 8;
3295 get(ctxt, &desc_ptr);
3296 if (ctxt->op_bytes == 2) {
3297 ctxt->op_bytes = 4;
3298 desc_ptr.address &= 0x00ffffff;
3299 }
3300 /* Disable writeback. */
3301 ctxt->dst.type = OP_NONE;
3302 return segmented_write(ctxt, ctxt->dst.addr.mem,
3303 &desc_ptr, 2 + ctxt->op_bytes);
3304}
3305
3306static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3307{
3308 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3309}
3310
3311static int em_sidt(struct x86_emulate_ctxt *ctxt)
3312{
3313 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3314}
3315
26d05cc7
AK		 3316static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3317{
26d05cc7
AK		 3318 struct desc_ptr desc_ptr;
3319 int rc;
3320
510425ff
AK		 3321 if (ctxt->mode == X86EMUL_MODE_PROT64)
3322 ctxt->op_bytes = 8;
9dac77fa 3323 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3324 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3325 ctxt->op_bytes);
26d05cc7
AK		 3326 if (rc != X86EMUL_CONTINUE)
3327 return rc;
3328 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3329 /* Disable writeback. */
9dac77fa 3330 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3331 return X86EMUL_CONTINUE;
3332}
3333
5ef39c71 3334static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3335{
26d05cc7
AK		 3336 int rc;
3337
5ef39c71
AK		 3338 rc = ctxt->ops->fix_hypercall(ctxt);
3339
26d05cc7 3340 /* Disable writeback. */
9dac77fa 3341 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3342 return rc;
3343}
3344
3345static int em_lidt(struct x86_emulate_ctxt *ctxt)
3346{
26d05cc7
AK		 3347 struct desc_ptr desc_ptr;
3348 int rc;
3349
510425ff
AK		 3350 if (ctxt->mode == X86EMUL_MODE_PROT64)
3351 ctxt->op_bytes = 8;
9dac77fa 3352 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3353 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3354 ctxt->op_bytes);
26d05cc7
AK		 3355 if (rc != X86EMUL_CONTINUE)
3356 return rc;
3357 ctxt->ops->set_idt(ctxt, &desc_ptr);
3358 /* Disable writeback. */
9dac77fa 3359 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3360 return X86EMUL_CONTINUE;
3361}
3362
3363static int em_smsw(struct x86_emulate_ctxt *ctxt)
3364{
9dac77fa
AK		 3365 ctxt->dst.bytes = 2;
3366 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3367 return X86EMUL_CONTINUE;
3368}
3369
3370static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3371{
26d05cc7 3372 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3373 | (ctxt->src.val & 0x0f));
3374 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3375 return X86EMUL_CONTINUE;
3376}
3377
d06e03ad
TY		 3378static int em_loop(struct x86_emulate_ctxt *ctxt)
3379{
dd856efa
AK		 3380 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3381 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3382 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3383 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3384
3385 return X86EMUL_CONTINUE;
3386}
3387
3388static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3389{
dd856efa 3390 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3391 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3392
3393 return X86EMUL_CONTINUE;
3394}
3395
d7841a4b
TY		 3396static int em_in(struct x86_emulate_ctxt *ctxt)
3397{
3398 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3399 &ctxt->dst.val))
3400 return X86EMUL_IO_NEEDED;
3401
3402 return X86EMUL_CONTINUE;
3403}
3404
3405static int em_out(struct x86_emulate_ctxt *ctxt)
3406{
3407 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3408 &ctxt->src.val, 1);
3409 /* Disable writeback. */
3410 ctxt->dst.type = OP_NONE;
3411 return X86EMUL_CONTINUE;
3412}
3413
f411e6cd
TY		 3414static int em_cli(struct x86_emulate_ctxt *ctxt)
3415{
3416 if (emulator_bad_iopl(ctxt))
3417 return emulate_gp(ctxt, 0);
3418
3419 ctxt->eflags &= ~X86_EFLAGS_IF;
3420 return X86EMUL_CONTINUE;
3421}
3422
3423static int em_sti(struct x86_emulate_ctxt *ctxt)
3424{
3425 if (emulator_bad_iopl(ctxt))
3426 return emulate_gp(ctxt, 0);
3427
3428 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3429 ctxt->eflags |= X86_EFLAGS_IF;
3430 return X86EMUL_CONTINUE;
3431}
3432
6d6eede4
AK		 3433static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3434{
3435 u32 eax, ebx, ecx, edx;
3436
dd856efa
AK		 3437 eax = reg_read(ctxt, VCPU_REGS_RAX);
3438 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3439 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3440 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3441 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3442 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3443 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3444 return X86EMUL_CONTINUE;
3445}
3446
2dd7caa0
AK		 3447static int em_lahf(struct x86_emulate_ctxt *ctxt)
3448{
dd856efa
AK		 3449 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3450 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3451 return X86EMUL_CONTINUE;
3452}
3453
9299836e
AK		 3454static int em_bswap(struct x86_emulate_ctxt *ctxt)
3455{
3456 switch (ctxt->op_bytes) {
3457#ifdef CONFIG_X86_64
3458 case 8:
3459 asm("bswap %0" : "+r"(ctxt->dst.val));
3460 break;
3461#endif
3462 default:
3463 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3464 break;
3465 }
3466 return X86EMUL_CONTINUE;
3467}
3468
cfec82cb
JR		 3469static bool valid_cr(int nr)
3470{
3471 switch (nr) {
3472 case 0:
3473 case 2 ... 4:
3474 case 8:
3475 return true;
3476 default:
3477 return false;
3478 }
3479}
3480
3481static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3482{
9dac77fa 3483 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3484 return emulate_ud(ctxt);
3485
3486 return X86EMUL_CONTINUE;
3487}
3488
3489static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3490{
9dac77fa
AK		 3491 u64 new_val = ctxt->src.val64;
3492 int cr = ctxt->modrm_reg;
c2ad2bb3 3493 u64 efer = 0;
cfec82cb
JR		 3494
3495 static u64 cr_reserved_bits[] = {
3496 0xffffffff00000000ULL,
3497 0, 0, 0, /* CR3 checked later */
3498 CR4_RESERVED_BITS,
3499 0, 0, 0,
3500 CR8_RESERVED_BITS,
3501 };
3502
3503 if (!valid_cr(cr))
3504 return emulate_ud(ctxt);
3505
3506 if (new_val & cr_reserved_bits[cr])
3507 return emulate_gp(ctxt, 0);
3508
3509 switch (cr) {
3510 case 0: {
c2ad2bb3 3511 u64 cr4;
cfec82cb
JR		 3512 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3513 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3514 return emulate_gp(ctxt, 0);
3515
717746e3
AK		 3516 cr4 = ctxt->ops->get_cr(ctxt, 4);
3517 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3518
3519 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3520 !(cr4 & X86_CR4_PAE))
3521 return emulate_gp(ctxt, 0);
3522
3523 break;
3524 }
3525 case 3: {
3526 u64 rsvd = 0;
3527
c2ad2bb3
AK		 3528 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3529 if (efer & EFER_LMA)
cfec82cb 3530 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3531 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3532 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3533 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3534 rsvd = CR3_NONPAE_RESERVED_BITS;
3535
3536 if (new_val & rsvd)
3537 return emulate_gp(ctxt, 0);
3538
3539 break;
3540 }
3541 case 4: {
717746e3 3542 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3543
3544 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3545 return emulate_gp(ctxt, 0);
3546
3547 break;
3548 }
3549 }
3550
3551 return X86EMUL_CONTINUE;
3552}
3553
3b88e41a
JR		 3554static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3555{
3556 unsigned long dr7;
3557
717746e3 3558 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3559
3560 /* Check if DR7.Global_Enable is set */
3561 return dr7 & (1 << 13);
3562}
3563
3564static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3565{
9dac77fa 3566 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3567 u64 cr4;
3568
3569 if (dr > 7)
3570 return emulate_ud(ctxt);
3571
717746e3 3572 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3573 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3574 return emulate_ud(ctxt);
3575
3576 if (check_dr7_gd(ctxt))
3577 return emulate_db(ctxt);
3578
3579 return X86EMUL_CONTINUE;
3580}
3581
3582static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3583{
9dac77fa
AK		 3584 u64 new_val = ctxt->src.val64;
3585 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3586
3587 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3588 return emulate_gp(ctxt, 0);
3589
3590 return check_dr_read(ctxt);
3591}
3592
01de8b09
JR		 3593static int check_svme(struct x86_emulate_ctxt *ctxt)
3594{
3595 u64 efer;
3596
717746e3 3597 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3598
3599 if (!(efer & EFER_SVME))
3600 return emulate_ud(ctxt);
3601
3602 return X86EMUL_CONTINUE;
3603}
3604
3605static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3606{
dd856efa 3607 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3608
3609 /* Valid physical address? */
d4224449 3610 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3611 return emulate_gp(ctxt, 0);
3612
3613 return check_svme(ctxt);
3614}
3615
d7eb8203
JR		 3616static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3617{
717746e3 3618 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3619
717746e3 3620 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3621 return emulate_ud(ctxt);
3622
3623 return X86EMUL_CONTINUE;
3624}
3625
8061252e
JR		 3626static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3627{
717746e3 3628 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3629 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3630
717746e3 3631 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3632 (rcx > 3))
3633 return emulate_gp(ctxt, 0);
3634
3635 return X86EMUL_CONTINUE;
3636}
3637
f6511935
JR		 3638static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3639{
9dac77fa
AK		 3640 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3641 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3642 return emulate_gp(ctxt, 0);
3643
3644 return X86EMUL_CONTINUE;
3645}
3646
3647static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3648{
9dac77fa
AK		 3649 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3650 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3651 return emulate_gp(ctxt, 0);
3652
3653 return X86EMUL_CONTINUE;
3654}
3655
73fba5f4 3656#define D(_y) { .flags = (_y) }
c4f035c6 3657#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3658#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3659 .check_perm = (_p) }
0b789eee 3660#define N D(NotImpl)
01de8b09 3661#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3662#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3663#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3664#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3665#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3666#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3667#define II(_f, _e, _i) \
3668 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3669#define IIP(_f, _e, _i, _p) \
3670 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3671 .check_perm = (_p) }
aa97bb48 3672#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3673
8d8f4e9f 3674#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3675#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3676#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3677#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3678#define I2bvIP(_f, _e, _i, _p) \
3679 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3680
fb864fbc
AK		 3681#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3682 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3683 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3684
fd0a0d82 3685static const struct opcode group7_rm1[] = {
1c2545be
TY		 3686 DI(SrcNone | Priv, monitor),
3687 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3688 N, N, N, N, N, N,
3689};
3690
fd0a0d82 3691static const struct opcode group7_rm3[] = {
1c2545be
TY		 3692 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3693 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3694 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3695 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3696 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3697 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3698 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3699 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3700};
6230f7fc 3701
fd0a0d82 3702static const struct opcode group7_rm7[] = {
d7eb8203 3703 N,
1c2545be 3704 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3705 N, N, N, N, N, N,
3706};
d67fc27a 3707
fd0a0d82 3708static const struct opcode group1[] = {
fb864fbc
AK		 3709 F(Lock, em_add),
3710 F(Lock | PageTable, em_or),
3711 F(Lock, em_adc),
3712 F(Lock, em_sbb),
3713 F(Lock | PageTable, em_and),
3714 F(Lock, em_sub),
3715 F(Lock, em_xor),
3716 F(NoWrite, em_cmp),
73fba5f4
AK		 3717};
3718
fd0a0d82 3719static const struct opcode group1A[] = {
1c2545be 3720 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3721};
3722
007a3b54
AK		 3723static const struct opcode group2[] = {
3724 F(DstMem | ModRM, em_rol),
3725 F(DstMem | ModRM, em_ror),
3726 F(DstMem | ModRM, em_rcl),
3727 F(DstMem | ModRM, em_rcr),
3728 F(DstMem | ModRM, em_shl),
3729 F(DstMem | ModRM, em_shr),
3730 F(DstMem | ModRM, em_shl),
3731 F(DstMem | ModRM, em_sar),
3732};
3733
fd0a0d82 3734static const struct opcode group3[] = {
fb864fbc
AK		 3735 F(DstMem | SrcImm | NoWrite, em_test),
3736 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3737 F(DstMem | SrcNone | Lock, em_not),
3738 F(DstMem | SrcNone | Lock, em_neg),
ab2c5ce6
AK		 3739 I(DstXacc | Src2Mem, em_mul_ex),
3740 I(DstXacc | Src2Mem, em_imul_ex),
3741 I(DstXacc | Src2Mem, em_div_ex),
3742 I(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3743};
3744
fd0a0d82 3745static const struct opcode group4[] = {
95413dc4
AK		 3746 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3747 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3748 N, N, N, N, N, N,
3749};
3750
fd0a0d82 3751static const struct opcode group5[] = {
95413dc4
AK		 3752 F(DstMem | SrcNone | Lock, em_inc),
3753 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3754 I(SrcMem | Stack, em_grp45),
3755 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3756 I(SrcMem | Stack, em_grp45),
3757 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3758 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3759};
3760
fd0a0d82 3761static const struct opcode group6[] = {
1c2545be
TY		 3762 DI(Prot, sldt),
3763 DI(Prot, str),
a14e579f 3764 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3765 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3766 N, N, N, N,
3767};
3768
fd0a0d82 3769static const struct group_dual group7 = { {
96051572
AK		 3770 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3771 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3772 II(SrcMem | Priv, em_lgdt, lgdt),
3773 II(SrcMem | Priv, em_lidt, lidt),
3774 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3775 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3776 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3777}, {
1c2545be 3778 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3779 EXT(0, group7_rm1),
01de8b09 3780 N, EXT(0, group7_rm3),
1c2545be
TY		 3781 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3782 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3783 EXT(0, group7_rm7),
73fba5f4
AK		 3784} };
3785
fd0a0d82 3786static const struct opcode group8[] = {
73fba5f4 3787 N, N, N, N,
11c363ba
AK		 3788 F(DstMem | SrcImmByte | NoWrite, em_bt),
3789 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3790 F(DstMem | SrcImmByte | Lock, em_btr),
3791 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3792};
3793
fd0a0d82 3794static const struct group_dual group9 = { {
1c2545be 3795 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3796}, {
3797 N, N, N, N, N, N, N, N,
3798} };
3799
fd0a0d82 3800static const struct opcode group11[] = {
1c2545be 3801 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3802 X7(D(Undefined)),
a4d4a7c1
AK		 3803};
3804
fd0a0d82 3805static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3806 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3807};
3808
fd0a0d82 3809static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3810 I(0, em_mov), N, N, N,
3811};
3812
045a282c
GN		 3813static const struct escape escape_d9 = { {
3814 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3815}, {
3816 /* 0xC0 - 0xC7 */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xC8 - 0xCF */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xD0 - 0xC7 */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xD8 - 0xDF */
3823 N, N, N, N, N, N, N, N,
3824 /* 0xE0 - 0xE7 */
3825 N, N, N, N, N, N, N, N,
3826 /* 0xE8 - 0xEF */
3827 N, N, N, N, N, N, N, N,
3828 /* 0xF0 - 0xF7 */
3829 N, N, N, N, N, N, N, N,
3830 /* 0xF8 - 0xFF */
3831 N, N, N, N, N, N, N, N,
3832} };
3833
3834static const struct escape escape_db = { {
3835 N, N, N, N, N, N, N, N,
3836}, {
3837 /* 0xC0 - 0xC7 */
3838 N, N, N, N, N, N, N, N,
3839 /* 0xC8 - 0xCF */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xD0 - 0xC7 */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xD8 - 0xDF */
3844 N, N, N, N, N, N, N, N,
3845 /* 0xE0 - 0xE7 */
3846 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3847 /* 0xE8 - 0xEF */
3848 N, N, N, N, N, N, N, N,
3849 /* 0xF0 - 0xF7 */
3850 N, N, N, N, N, N, N, N,
3851 /* 0xF8 - 0xFF */
3852 N, N, N, N, N, N, N, N,
3853} };
3854
3855static const struct escape escape_dd = { {
3856 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3857}, {
3858 /* 0xC0 - 0xC7 */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xC8 - 0xCF */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xD0 - 0xC7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xD8 - 0xDF */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xE0 - 0xE7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xE8 - 0xEF */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xF0 - 0xF7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xF8 - 0xFF */
3873 N, N, N, N, N, N, N, N,
3874} };
3875
fd0a0d82 3876static const struct opcode opcode_table[256] = {
73fba5f4 3877 /* 0x00 - 0x07 */
fb864fbc 3878 F6ALU(Lock, em_add),
1cd196ea
AK		 3879 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3880 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3881 /* 0x08 - 0x0F */
fb864fbc 3882 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3883 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3884 N,
73fba5f4 3885 /* 0x10 - 0x17 */
fb864fbc 3886 F6ALU(Lock, em_adc),
1cd196ea
AK		 3887 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3888 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3889 /* 0x18 - 0x1F */
fb864fbc 3890 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3891 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3892 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3893 /* 0x20 - 0x27 */
fb864fbc 3894 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3895 /* 0x28 - 0x2F */
fb864fbc 3896 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3897 /* 0x30 - 0x37 */
fb864fbc 3898 F6ALU(Lock, em_xor), N, N,
73fba5f4 3899 /* 0x38 - 0x3F */
fb864fbc 3900 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3901 /* 0x40 - 0x4F */
95413dc4 3902 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3903 /* 0x50 - 0x57 */
63540382 3904 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3905 /* 0x58 - 0x5F */
c54fe504 3906 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3907 /* 0x60 - 0x67 */
b96a7fad
TY		 3908 I(ImplicitOps | Stack | No64, em_pusha),
3909 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3910 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3911 N, N, N, N,
3912 /* 0x68 - 0x6F */
d46164db
AK		 3913 I(SrcImm | Mov | Stack, em_push),
3914 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3915 I(SrcImmByte | Mov | Stack, em_push),
3916 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3917 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3918 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3919 /* 0x70 - 0x7F */
3920 X16(D(SrcImmByte)),
3921 /* 0x80 - 0x87 */
1c2545be
TY		 3922 G(ByteOp | DstMem | SrcImm, group1),
3923 G(DstMem | SrcImm, group1),
3924 G(ByteOp | DstMem | SrcImm | No64, group1),
3925 G(DstMem | SrcImmByte, group1),
fb864fbc 3926 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3927 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3928 /* 0x88 - 0x8F */
d5ae7ce8 3929 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3930 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3931 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3932 D(ModRM | SrcMem | NoAccess | DstReg),
3933 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3934 G(0, group1A),
73fba5f4 3935 /* 0x90 - 0x97 */
bf608f88 3936 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3937 /* 0x98 - 0x9F */
61429142 3938 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3939 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3940 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3941 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3942 /* 0xA0 - 0xA7 */
b9eac5f4 3943 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3944 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3945 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3946 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3947 /* 0xA8 - 0xAF */
fb864fbc 3948 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3949 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3950 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3951 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3952 /* 0xB0 - 0xB7 */
b9eac5f4 3953 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3954 /* 0xB8 - 0xBF */
5e2c6883 3955 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3956 /* 0xC0 - 0xC7 */
007a3b54 3957 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3958 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3959 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3960 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3961 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3962 G(ByteOp, group11), G(0, group11),
73fba5f4 3963 /* 0xC8 - 0xCF */
612e89f0
AK		 3964 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3965 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3966 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3967 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3968 /* 0xD0 - 0xD7 */
007a3b54
AK		 3969 G(Src2One | ByteOp, group2), G(Src2One, group2),
3970 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3971 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3972 I(DstAcc | SrcImmUByte | No64, em_aad),
3973 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3974 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3975 /* 0xD8 - 0xDF */
045a282c 3976 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3977 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3978 X3(I(SrcImmByte, em_loop)),
3979 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3980 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3981 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3982 /* 0xE8 - 0xEF */
d4ddafcd 3983 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3984 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3985 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3986 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3987 /* 0xF0 - 0xF7 */
bf608f88 3988 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3989 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3990 G(ByteOp, group3), G(0, group3),
73fba5f4 3991 /* 0xF8 - 0xFF */
f411e6cd
TY		 3992 D(ImplicitOps), D(ImplicitOps),
3993 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3994 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3995};
3996
fd0a0d82 3997static const struct opcode twobyte_table[256] = {
73fba5f4 3998 /* 0x00 - 0x0F */
dee6bb70 3999 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 4000 N, I(ImplicitOps | VendorSpecific, em_syscall),
4001 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4002 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 4003 N, D(ImplicitOps | ModRM), N, N,
4004 /* 0x10 - 0x1F */
4005 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
4006 /* 0x20 - 0x2F */
cfec82cb 4007 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 4008 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4009 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4010 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4011 N, N, N, N,
3e114eb4
AK		 4012 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4013 N, N, N, N,
73fba5f4 4014 /* 0x30 - 0x3F */
e1e210b0 4015 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4016 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4017 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4018 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4019 I(ImplicitOps | VendorSpecific, em_sysenter),
4020 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4021 N, N,
73fba5f4
AK		 4022 N, N, N, N, N, N, N, N,
4023 /* 0x40 - 0x4F */
4024 X16(D(DstReg | SrcMem | ModRM | Mov)),
4025 /* 0x50 - 0x5F */
4026 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4027 /* 0x60 - 0x6F */
aa97bb48
AK		 4028 N, N, N, N,
4029 N, N, N, N,
4030 N, N, N, N,
4031 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4032 /* 0x70 - 0x7F */
aa97bb48
AK		 4033 N, N, N, N,
4034 N, N, N, N,
4035 N, N, N, N,
4036 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4037 /* 0x80 - 0x8F */
4038 X16(D(SrcImm)),
4039 /* 0x90 - 0x9F */
ee45b58e 4040 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4041 /* 0xA0 - 0xA7 */
1cd196ea 4042 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4043 II(ImplicitOps, em_cpuid, cpuid),
4044 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4045 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4046 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4047 /* 0xA8 - 0xAF */
1cd196ea 4048 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4049 DI(ImplicitOps, rsm),
11c363ba 4050 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4051 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4052 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4053 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4054 /* 0xB0 - 0xB7 */
e940b5c2 4055 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4056 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4057 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4058 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4059 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4060 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4061 /* 0xB8 - 0xBF */
4062 N, N,
ce7faab2 4063 G(BitOp, group8),
11c363ba
AK		 4064 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4065 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4066 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4067 /* 0xC0 - 0xC7 */
739ae406 4068 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4069 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4070 N, N, N, GD(0, &group9),
9299836e
AK		 4071 /* 0xC8 - 0xCF */
4072 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4073 /* 0xD0 - 0xDF */
4074 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4075 /* 0xE0 - 0xEF */
4076 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4077 /* 0xF0 - 0xFF */
4078 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4079};
4080
4081#undef D
4082#undef N
4083#undef G
4084#undef GD
4085#undef I
aa97bb48 4086#undef GP
01de8b09 4087#undef EXT
73fba5f4 4088
8d8f4e9f 4089#undef D2bv
f6511935 4090#undef D2bvIP
8d8f4e9f 4091#undef I2bv
d7841a4b 4092#undef I2bvIP
d67fc27a 4093#undef I6ALU
8d8f4e9f 4094
9dac77fa 4095static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4096{
4097 unsigned size;
4098
9dac77fa 4099 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4100 if (size == 8)
4101 size = 4;
4102 return size;
4103}
4104
4105static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4106 unsigned size, bool sign_extension)
4107{
39f21ee5
AK		 4108 int rc = X86EMUL_CONTINUE;
4109
4110 op->type = OP_IMM;
4111 op->bytes = size;
9dac77fa 4112 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4113 /* NB. Immediates are sign-extended as necessary. */
4114 switch (op->bytes) {
4115 case 1:
e85a1085 4116 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4117 break;
4118 case 2:
e85a1085 4119 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4120 break;
4121 case 4:
e85a1085 4122 op->val = insn_fetch(s32, ctxt);
39f21ee5 4123 break;
5e2c6883
NA		 4124 case 8:
4125 op->val = insn_fetch(s64, ctxt);
4126 break;
39f21ee5
AK		 4127 }
4128 if (!sign_extension) {
4129 switch (op->bytes) {
4130 case 1:
4131 op->val &= 0xff;
4132 break;
4133 case 2:
4134 op->val &= 0xffff;
4135 break;
4136 case 4:
4137 op->val &= 0xffffffff;
4138 break;
4139 }
4140 }
4141done:
4142 return rc;
4143}
4144
a9945549
AK		 4145static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4146 unsigned d)
4147{
4148 int rc = X86EMUL_CONTINUE;
4149
4150 switch (d) {
4151 case OpReg:
2adb5ad9 4152 decode_register_operand(ctxt, op);
a9945549
AK		 4153 break;
4154 case OpImmUByte:
608aabe3 4155 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4156 break;
4157 case OpMem:
41ddf978 4158 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4159 mem_common:
4160 *op = ctxt->memop;
4161 ctxt->memopp = op;
4162 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4163 fetch_bit_operand(ctxt);
4164 op->orig_val = op->val;
4165 break;
41ddf978
AK		 4166 case OpMem64:
4167 ctxt->memop.bytes = 8;
4168 goto mem_common;
a9945549
AK		 4169 case OpAcc:
4170 op->type = OP_REG;
4171 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4172 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4173 fetch_register_operand(op);
4174 op->orig_val = op->val;
4175 break;
820207c8
AK		 4176 case OpAccLo:
4177 op->type = OP_REG;
4178 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4179 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4180 fetch_register_operand(op);
4181 op->orig_val = op->val;
4182 break;
4183 case OpAccHi:
4184 if (ctxt->d & ByteOp) {
4185 op->type = OP_NONE;
4186 break;
4187 }
4188 op->type = OP_REG;
4189 op->bytes = ctxt->op_bytes;
4190 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4191 fetch_register_operand(op);
4192 op->orig_val = op->val;
4193 break;
a9945549
AK		 4194 case OpDI:
4195 op->type = OP_MEM;
4196 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4197 op->addr.mem.ea =
dd856efa 4198 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4199 op->addr.mem.seg = VCPU_SREG_ES;
4200 op->val = 0;
b3356bf0 4201 op->count = 1;
a9945549
AK		 4202 break;
4203 case OpDX:
4204 op->type = OP_REG;
4205 op->bytes = 2;
dd856efa 4206 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4207 fetch_register_operand(op);
4208 break;
4dd6a57d
AK		 4209 case OpCL:
4210 op->bytes = 1;
dd856efa 4211 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4212 break;
4213 case OpImmByte:
4214 rc = decode_imm(ctxt, op, 1, true);
4215 break;
4216 case OpOne:
4217 op->bytes = 1;
4218 op->val = 1;
4219 break;
4220 case OpImm:
4221 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4222 break;
5e2c6883
NA		 4223 case OpImm64:
4224 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4225 break;
28867cee
AK		 4226 case OpMem8:
4227 ctxt->memop.bytes = 1;
660696d1
GN		 4228 if (ctxt->memop.type == OP_REG) {
4229 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4230 fetch_register_operand(&ctxt->memop);
4231 }
28867cee 4232 goto mem_common;
0fe59128
AK		 4233 case OpMem16:
4234 ctxt->memop.bytes = 2;
4235 goto mem_common;
4236 case OpMem32:
4237 ctxt->memop.bytes = 4;
4238 goto mem_common;
4239 case OpImmU16:
4240 rc = decode_imm(ctxt, op, 2, false);
4241 break;
4242 case OpImmU:
4243 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4244 break;
4245 case OpSI:
4246 op->type = OP_MEM;
4247 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4248 op->addr.mem.ea =
dd856efa 4249 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4250 op->addr.mem.seg = seg_override(ctxt);
4251 op->val = 0;
b3356bf0 4252 op->count = 1;
0fe59128 4253 break;
7fa57952
PB		 4254 case OpXLat:
4255 op->type = OP_MEM;
4256 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4257 op->addr.mem.ea =
4258 register_address(ctxt,
4259 reg_read(ctxt, VCPU_REGS_RBX) +
4260 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4261 op->addr.mem.seg = seg_override(ctxt);
4262 op->val = 0;
4263 break;
0fe59128
AK		 4264 case OpImmFAddr:
4265 op->type = OP_IMM;
4266 op->addr.mem.ea = ctxt->_eip;
4267 op->bytes = ctxt->op_bytes + 2;
4268 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4269 break;
4270 case OpMemFAddr:
4271 ctxt->memop.bytes = ctxt->op_bytes + 2;
4272 goto mem_common;
c191a7a0
AK		 4273 case OpES:
4274 op->val = VCPU_SREG_ES;
4275 break;
4276 case OpCS:
4277 op->val = VCPU_SREG_CS;
4278 break;
4279 case OpSS:
4280 op->val = VCPU_SREG_SS;
4281 break;
4282 case OpDS:
4283 op->val = VCPU_SREG_DS;
4284 break;
4285 case OpFS:
4286 op->val = VCPU_SREG_FS;
4287 break;
4288 case OpGS:
4289 op->val = VCPU_SREG_GS;
4290 break;
a9945549
AK		 4291 case OpImplicit:
4292 /* Special instructions do their own operand decoding. */
4293 default:
4294 op->type = OP_NONE; /* Disable writeback. */
4295 break;
4296 }
4297
4298done:
4299 return rc;
4300}
4301
ef5d75cc 4302int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4303{
dde7e6d1
AK		 4304 int rc = X86EMUL_CONTINUE;
4305 int mode = ctxt->mode;
46561646 4306 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4307 bool op_prefix = false;
46561646 4308 struct opcode opcode;
dde7e6d1 4309
f09ed83e
AK		 4310 ctxt->memop.type = OP_NONE;
4311 ctxt->memopp = NULL;
9dac77fa
AK		 4312 ctxt->_eip = ctxt->eip;
4313 ctxt->fetch.start = ctxt->_eip;
4314 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4315 if (insn_len > 0)
9dac77fa 4316 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4317
4318 switch (mode) {
4319 case X86EMUL_MODE_REAL:
4320 case X86EMUL_MODE_VM86:
4321 case X86EMUL_MODE_PROT16:
4322 def_op_bytes = def_ad_bytes = 2;
4323 break;
4324 case X86EMUL_MODE_PROT32:
4325 def_op_bytes = def_ad_bytes = 4;
4326 break;
4327#ifdef CONFIG_X86_64
4328 case X86EMUL_MODE_PROT64:
4329 def_op_bytes = 4;
4330 def_ad_bytes = 8;
4331 break;
4332#endif
4333 default:
1d2887e2 4334 return EMULATION_FAILED;
dde7e6d1
AK		 4335 }
4336
9dac77fa
AK		 4337 ctxt->op_bytes = def_op_bytes;
4338 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4339
4340 /* Legacy prefixes. */
4341 for (;;) {
e85a1085 4342 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4343 case 0x66: /* operand-size override */
0d7cdee8 4344 op_prefix = true;
dde7e6d1 4345 /* switch between 2/4 bytes */
9dac77fa 4346 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4347 break;
4348 case 0x67: /* address-size override */
4349 if (mode == X86EMUL_MODE_PROT64)
4350 /* switch between 4/8 bytes */
9dac77fa 4351 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4352 else
4353 /* switch between 2/4 bytes */
9dac77fa 4354 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4355 break;
4356 case 0x26: /* ES override */
4357 case 0x2e: /* CS override */
4358 case 0x36: /* SS override */
4359 case 0x3e: /* DS override */
9dac77fa 4360 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4361 break;
4362 case 0x64: /* FS override */
4363 case 0x65: /* GS override */
9dac77fa 4364 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4365 break;
4366 case 0x40 ... 0x4f: /* REX */
4367 if (mode != X86EMUL_MODE_PROT64)
4368 goto done_prefixes;
9dac77fa 4369 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4370 continue;
4371 case 0xf0: /* LOCK */
9dac77fa 4372 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4373 break;
4374 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4375 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4376 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4377 break;
4378 default:
4379 goto done_prefixes;
4380 }
4381
4382 /* Any legacy prefix after a REX prefix nullifies its effect. */
4383
9dac77fa 4384 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4385 }
4386
4387done_prefixes:
4388
4389 /* REX prefix. */
9dac77fa
AK		 4390 if (ctxt->rex_prefix & 8)
4391 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4392
4393 /* Opcode byte(s). */
9dac77fa 4394 opcode = opcode_table[ctxt->b];
d3ad6243 4395 /* Two-byte opcode? */
9dac77fa
AK		 4396 if (ctxt->b == 0x0f) {
4397 ctxt->twobyte = 1;
e85a1085 4398 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4399 opcode = twobyte_table[ctxt->b];
dde7e6d1 4400 }
9dac77fa 4401 ctxt->d = opcode.flags;
dde7e6d1 4402
9f4260e7
TY		 4403 if (ctxt->d & ModRM)
4404 ctxt->modrm = insn_fetch(u8, ctxt);
4405
9dac77fa
AK		 4406 while (ctxt->d & GroupMask) {
4407 switch (ctxt->d & GroupMask) {
46561646 4408 case Group:
9dac77fa 4409 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4410 opcode = opcode.u.group[goffset];
4411 break;
4412 case GroupDual:
9dac77fa
AK		 4413 goffset = (ctxt->modrm >> 3) & 7;
4414 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4415 opcode = opcode.u.gdual->mod3[goffset];
4416 else
4417 opcode = opcode.u.gdual->mod012[goffset];
4418 break;
4419 case RMExt:
9dac77fa 4420 goffset = ctxt->modrm & 7;
01de8b09 4421 opcode = opcode.u.group[goffset];
46561646
AK		 4422 break;
4423 case Prefix:
9dac77fa 4424 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4425 return EMULATION_FAILED;
9dac77fa 4426 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4427 switch (simd_prefix) {
4428 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4429 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4430 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4431 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4432 }
4433 break;
045a282c
GN		 4434 case Escape:
4435 if (ctxt->modrm > 0xbf)
4436 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4437 else
4438 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4439 break;
46561646 4440 default:
1d2887e2 4441 return EMULATION_FAILED;
0d7cdee8 4442 }
46561646 4443
b1ea50b2 4444 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4445 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4446 }
4447
9dac77fa
AK		 4448 ctxt->execute = opcode.u.execute;
4449 ctxt->check_perm = opcode.check_perm;
4450 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4451
4452 /* Unrecognised? */
1146a78b 4453 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4454 return EMULATION_FAILED;
dde7e6d1 4455
9dac77fa 4456 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4457 return EMULATION_FAILED;
d867162c 4458
9dac77fa
AK		 4459 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4460 ctxt->op_bytes = 8;
dde7e6d1 4461
9dac77fa 4462 if (ctxt->d & Op3264) {
7f9b4b75 4463 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4464 ctxt->op_bytes = 8;
7f9b4b75 4465 else
9dac77fa 4466 ctxt->op_bytes = 4;
7f9b4b75
AK		 4467 }
4468
9dac77fa
AK		 4469 if (ctxt->d & Sse)
4470 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4471 else if (ctxt->d & Mmx)
4472 ctxt->op_bytes = 8;
1253791d 4473
dde7e6d1 4474 /* ModRM and SIB bytes. */
9dac77fa 4475 if (ctxt->d & ModRM) {
f09ed83e 4476 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4477 if (!ctxt->has_seg_override)
4478 set_seg_override(ctxt, ctxt->modrm_seg);
4479 } else if (ctxt->d & MemAbs)
f09ed83e 4480 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4481 if (rc != X86EMUL_CONTINUE)
4482 goto done;
4483
9dac77fa
AK		 4484 if (!ctxt->has_seg_override)
4485 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4486
f09ed83e 4487 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4488
f09ed83e
AK		 4489 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4490 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4491
dde7e6d1
AK		 4492 /*
4493 * Decode and fetch the source operand: register, memory
4494 * or immediate.
4495 */
0fe59128 4496 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4497 if (rc != X86EMUL_CONTINUE)
4498 goto done;
4499
dde7e6d1
AK		 4500 /*
4501 * Decode and fetch the second source operand: register, memory
4502 * or immediate.
4503 */
4dd6a57d 4504 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4505 if (rc != X86EMUL_CONTINUE)
4506 goto done;
4507
dde7e6d1 4508 /* Decode and fetch the destination operand: register or memory. */
a9945549 4509 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4510
4511done:
f09ed83e
AK		 4512 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4513 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4514
1d2887e2 4515 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4516}
4517
1cb3f3ae
XG		 4518bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4519{
4520 return ctxt->d & PageTable;
4521}
4522
3e2f65d5
GN		 4523static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4524{
3e2f65d5
GN		 4525 /* The second termination condition only applies for REPE
4526 * and REPNE. Test if the repeat string operation prefix is
4527 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4528 * corresponding termination condition according to:
4529 * - if REPE/REPZ and ZF = 0 then done
4530 * - if REPNE/REPNZ and ZF = 1 then done
4531 */
9dac77fa
AK		 4532 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4533 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4534 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4535 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4536 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4537 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4538 return true;
4539
4540 return false;
4541}
4542
cbe2c9d3
AK		 4543static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4544{
4545 bool fault = false;
4546
4547 ctxt->ops->get_fpu(ctxt);
4548 asm volatile("1: fwait \n\t"
4549 "2: \n\t"
4550 ".pushsection .fixup,\"ax\" \n\t"
4551 "3: \n\t"
4552 "movb $1, %[fault] \n\t"
4553 "jmp 2b \n\t"
4554 ".popsection \n\t"
4555 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4556 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4557 ctxt->ops->put_fpu(ctxt);
4558
4559 if (unlikely(fault))
4560 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4561
4562 return X86EMUL_CONTINUE;
4563}
4564
4565static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4566 struct operand *op)
4567{
4568 if (op->type == OP_MM)
4569 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4570}
4571
e28bbd44
AK		 4572static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4573{
4574 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4575 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4576 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4577 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4578 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4579 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4580 return X86EMUL_CONTINUE;
4581}
dd856efa 4582
7b105ca2 4583int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4584{
0225fb50 4585 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4586 int rc = X86EMUL_CONTINUE;
9dac77fa 4587 int saved_dst_type = ctxt->dst.type;
8b4caf66 4588
9dac77fa 4589 ctxt->mem_read.pos = 0;
310b5d30 4590
1146a78b
GN		 4591 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4592 (ctxt->d & Undefined)) {
35d3d4a1 4593 rc = emulate_ud(ctxt);
1161624f
GN		 4594 goto done;
4595 }
4596
d380a5e4 4597 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4598 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4599 rc = emulate_ud(ctxt);
d380a5e4
GN		 4600 goto done;
4601 }
4602
9dac77fa 4603 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4604 rc = emulate_ud(ctxt);
081bca0e
AK		 4605 goto done;
4606 }
4607
cbe2c9d3
AK		 4608 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4609 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4610 rc = emulate_ud(ctxt);
4611 goto done;
4612 }
4613
cbe2c9d3 4614 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4615 rc = emulate_nm(ctxt);
4616 goto done;
4617 }
4618
cbe2c9d3
AK		 4619 if (ctxt->d & Mmx) {
4620 rc = flush_pending_x87_faults(ctxt);
4621 if (rc != X86EMUL_CONTINUE)
4622 goto done;
4623 /*
4624 * Now that we know the fpu is exception safe, we can fetch
4625 * operands from it.
4626 */
4627 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4628 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4629 if (!(ctxt->d & Mov))
4630 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4631 }
4632
9dac77fa
AK		 4633 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4634 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4635 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4636 if (rc != X86EMUL_CONTINUE)
4637 goto done;
4638 }
4639
e92805ac 4640 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4641 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4642 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4643 goto done;
4644 }
4645
8ea7d6ae 4646 /* Instruction can only be executed in protected mode */
9d1b39a9 4647 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4648 rc = emulate_ud(ctxt);
4649 goto done;
4650 }
4651
d09beabd 4652 /* Do instruction specific permission checks */
9dac77fa
AK		 4653 if (ctxt->check_perm) {
4654 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4655 if (rc != X86EMUL_CONTINUE)
4656 goto done;
4657 }
4658
9dac77fa
AK		 4659 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4660 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4661 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4662 if (rc != X86EMUL_CONTINUE)
4663 goto done;
4664 }
4665
9dac77fa 4666 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4667 /* All REP prefixes have the same first termination condition */
dd856efa 4668 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4669 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4670 goto done;
4671 }
b9fa9d6b
AK		 4672 }
4673
9dac77fa
AK		 4674 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4675 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4676 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4677 if (rc != X86EMUL_CONTINUE)
8b4caf66 4678 goto done;
9dac77fa 4679 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4680 }
4681
9dac77fa
AK		 4682 if (ctxt->src2.type == OP_MEM) {
4683 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4684 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4685 if (rc != X86EMUL_CONTINUE)
4686 goto done;
4687 }
4688
9dac77fa 4689 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4690 goto special_insn;
4691
4692
9dac77fa 4693 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4694 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4695 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4696 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4697 if (rc != X86EMUL_CONTINUE)
4698 goto done;
038e51de 4699 }
9dac77fa 4700 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4701
018a98db
AK		 4702special_insn:
4703
9dac77fa
AK		 4704 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4705 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4706 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4707 if (rc != X86EMUL_CONTINUE)
4708 goto done;
4709 }
4710
9dac77fa 4711 if (ctxt->execute) {
e28bbd44
AK		 4712 if (ctxt->d & Fastop) {
4713 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4714 rc = fastop(ctxt, fop);
4715 if (rc != X86EMUL_CONTINUE)
4716 goto done;
4717 goto writeback;
4718 }
9dac77fa 4719 rc = ctxt->execute(ctxt);
ef65c889
AK		 4720 if (rc != X86EMUL_CONTINUE)
4721 goto done;
4722 goto writeback;
4723 }
4724
9dac77fa 4725 if (ctxt->twobyte)
6aa8b732
AK		 4726 goto twobyte_insn;
4727
9dac77fa 4728 switch (ctxt->b) {
6aa8b732 4729 case 0x63: /* movsxd */
8b4caf66 4730 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4731 goto cannot_emulate;
9dac77fa 4732 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4733 break;
b2833e3c 4734 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4735 if (test_cc(ctxt->b, ctxt->eflags))
4736 jmp_rel(ctxt, ctxt->src.val);
018a98db 4737 break;
7e0b54b1 4738 case 0x8d: /* lea r16/r32, m */
9dac77fa 4739 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4740 break;
3d9e77df 4741 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4742 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4743 break;
e4f973ae
TY		 4744 rc = em_xchg(ctxt);
4745 break;
e8b6fa70 4746 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4747 switch (ctxt->op_bytes) {
4748 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4749 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4750 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4751 }
4752 break;
6e154e56 4753 case 0xcc: /* int3 */
5c5df76b
TY		 4754 rc = emulate_int(ctxt, 3);
4755 break;
6e154e56 4756 case 0xcd: /* int n */
9dac77fa 4757 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4758 break;
4759 case 0xce: /* into */
5c5df76b
TY		 4760 if (ctxt->eflags & EFLG_OF)
4761 rc = emulate_int(ctxt, 4);
6e154e56 4762 break;
1a52e051 4763 case 0xe9: /* jmp rel */
db5b0762 4764 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4765 jmp_rel(ctxt, ctxt->src.val);
4766 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4767 break;
111de5d6 4768 case 0xf4: /* hlt */
6c3287f7 4769 ctxt->ops->halt(ctxt);
19fdfa0d 4770 break;
111de5d6
AK		 4771 case 0xf5: /* cmc */
4772 /* complement carry flag from eflags reg */
4773 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4774 break;
4775 case 0xf8: /* clc */
4776 ctxt->eflags &= ~EFLG_CF;
111de5d6 4777 break;
8744aa9a
MG		 4778 case 0xf9: /* stc */
4779 ctxt->eflags |= EFLG_CF;
4780 break;
fb4616f4
MG		 4781 case 0xfc: /* cld */
4782 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4783 break;
4784 case 0xfd: /* std */
4785 ctxt->eflags |= EFLG_DF;
fb4616f4 4786 break;
91269b8f
AK		 4787 default:
4788 goto cannot_emulate;
6aa8b732 4789 }
018a98db 4790
7d9ddaed
AK		 4791 if (rc != X86EMUL_CONTINUE)
4792 goto done;
4793
018a98db 4794writeback:
fb32b1ed
AK		 4795 if (!(ctxt->d & NoWrite)) {
4796 rc = writeback(ctxt, &ctxt->dst);
4797 if (rc != X86EMUL_CONTINUE)
4798 goto done;
4799 }
4800 if (ctxt->d & SrcWrite) {
4801 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4802 rc = writeback(ctxt, &ctxt->src);
4803 if (rc != X86EMUL_CONTINUE)
4804 goto done;
4805 }
018a98db 4806
5cd21917
GN		 4807 /*
4808 * restore dst type in case the decoding will be reused
4809 * (happens for string instruction )
4810 */
9dac77fa 4811 ctxt->dst.type = saved_dst_type;
5cd21917 4812
9dac77fa 4813 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4814 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4815
9dac77fa 4816 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4817 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4818
9dac77fa 4819 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4820 unsigned int count;
9dac77fa 4821 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4822 if ((ctxt->d & SrcMask) == SrcSI)
4823 count = ctxt->src.count;
4824 else
4825 count = ctxt->dst.count;
4826 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4827 -count);
3e2f65d5 4828
d2ddd1c4
GN		 4829 if (!string_insn_completed(ctxt)) {
4830 /*
4831 * Re-enter guest when pio read ahead buffer is empty
4832 * or, if it is not used, after each 1024 iteration.
4833 */
dd856efa 4834 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4835 (r->end == 0 || r->end != r->pos)) {
4836 /*
4837 * Reset read cache. Usually happens before
4838 * decode, but since instruction is restarted
4839 * we have to do it here.
4840 */
9dac77fa 4841 ctxt->mem_read.end = 0;
dd856efa 4842 writeback_registers(ctxt);
d2ddd1c4
GN		 4843 return EMULATION_RESTART;
4844 }
4845 goto done; /* skip rip writeback */
0fa6ccbd 4846 }
5cd21917 4847 }
d2ddd1c4 4848
9dac77fa 4849 ctxt->eip = ctxt->_eip;
018a98db
AK		 4850
4851done:
da9cb575
AK		 4852 if (rc == X86EMUL_PROPAGATE_FAULT)
4853 ctxt->have_exception = true;
775fde86
JR		 4854 if (rc == X86EMUL_INTERCEPTED)
4855 return EMULATION_INTERCEPTED;
4856
dd856efa
AK		 4857 if (rc == X86EMUL_CONTINUE)
4858 writeback_registers(ctxt);
4859
d2ddd1c4 4860 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4861
4862twobyte_insn:
9dac77fa 4863 switch (ctxt->b) {
018a98db 4864 case 0x09: /* wbinvd */
cfb22375 4865 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4866 break;
4867 case 0x08: /* invd */
018a98db
AK		 4868 case 0x0d: /* GrpP (prefetch) */
4869 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4870 break;
4871 case 0x20: /* mov cr, reg */
9dac77fa 4872 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4873 break;
6aa8b732 4874 case 0x21: /* mov from dr to reg */
9dac77fa 4875 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4876 break;
6aa8b732 4877 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4878 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4879 if (!test_cc(ctxt->b, ctxt->eflags))
4880 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4881 break;
b2833e3c 4882 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4883 if (test_cc(ctxt->b, ctxt->eflags))
4884 jmp_rel(ctxt, ctxt->src.val);
018a98db 4885 break;
ee45b58e 4886 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4887 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4888 break;
2a7c5b8b
GC		 4889 case 0xae: /* clflush */
4890 break;
6aa8b732 4891 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4892 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4893 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4894 : (u16) ctxt->src.val;
6aa8b732 4895 break;
6aa8b732 4896 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4897 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4898 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4899 (s16) ctxt->src.val;
6aa8b732 4900 break;
92f738a5 4901 case 0xc0 ... 0xc1: /* xadd */
158de57f 4902 fastop(ctxt, em_add);
92f738a5 4903 /* Write back the register source. */
9dac77fa
AK		 4904 ctxt->src.val = ctxt->dst.orig_val;
4905 write_register_operand(&ctxt->src);
92f738a5 4906 break;
a012e65a 4907 case 0xc3: /* movnti */
9dac77fa
AK		 4908 ctxt->dst.bytes = ctxt->op_bytes;
4909 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4910 (u64) ctxt->src.val;
a012e65a 4911 break;
91269b8f
AK		 4912 default:
4913 goto cannot_emulate;
6aa8b732 4914 }
7d9ddaed
AK		 4915
4916 if (rc != X86EMUL_CONTINUE)
4917 goto done;
4918
6aa8b732
AK		 4919 goto writeback;
4920
4921cannot_emulate:
a0c0ab2f 4922 return EMULATION_FAILED;
6aa8b732 4923}
dd856efa
AK		 4924
4925void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4926{
4927 invalidate_registers(ctxt);
4928}
4929
4930void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4931{
4932 writeback_registers(ctxt);
4933}
Linux kernel - Deliverables
This page took 1.112116 seconds and 5 git commands to generate.