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KVM: x86: POP [ESP] is not emulated correctly
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 128#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 129/* Generic ModRM decode. */
130#define ModRM (1<<19)
131/* Destination is only written; never read. */
132#define Mov (1<<20)
d8769fed 133/* Misc flags */
8ea7d6ae 134#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 135#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 136#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 137#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 138#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 139#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 140#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 141#define No64 (1<<28)
d5ae7ce8 142#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 143#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 144/* Source 2 operand type */
0b789eee 145#define Src2Shift (31)
4dd6a57d 146#define Src2None (OpNone << Src2Shift)
ab2c5ce6 147#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 148#define Src2CL (OpCL << Src2Shift)
149#define Src2ImmByte (OpImmByte << Src2Shift)
150#define Src2One (OpOne << Src2Shift)
151#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 152#define Src2ES (OpES << Src2Shift)
153#define Src2CS (OpCS << Src2Shift)
154#define Src2SS (OpSS << Src2Shift)
155#define Src2DS (OpDS << Src2Shift)
156#define Src2FS (OpFS << Src2Shift)
157#define Src2GS (OpGS << Src2Shift)
4dd6a57d 158#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 159#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 160#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
161#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
162#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 163#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 164#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 165#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 166#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 167#define Intercept ((u64)1 << 48) /* Has valid intercept field */
168#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 169#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 170#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 171#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 172#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 173#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 174
820207c8 175#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 176
d0e53325
AK		 177#define X2(x...) x, x
178#define X3(x...) X2(x), x
179#define X4(x...) X2(x), X2(x)
180#define X5(x...) X4(x), x
181#define X6(x...) X4(x), X2(x)
182#define X7(x...) X4(x), X3(x)
183#define X8(x...) X4(x), X4(x)
184#define X16(x...) X8(x), X8(x)
83babbca 185
e28bbd44
AK		 186#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
187#define FASTOP_SIZE 8
188
189/*
190 * fastop functions have a special calling convention:
191 *
017da7b6
AK		 192 * dst: rax (in/out)
193 * src: rdx (in/out)
e28bbd44
AK		 194 * src2: rcx (in)
195 * flags: rflags (in/out)
b8c0b6ae 196 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 197 *
198 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
199 * different operand sizes can be reached by calculation, rather than a jump
200 * table (which would be bigger than the code).
201 *
202 * fastop functions are declared as taking a never-defined fastop parameter,
203 * so they can't be called from C directly.
204 */
205
206struct fastop;
207
d65b1dee 208struct opcode {
b1ea50b2
AK		 209 u64 flags : 56;
210 u64 intercept : 8;
120df890 211 union {
ef65c889 212 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 213 const struct opcode *group;
214 const struct group_dual *gdual;
215 const struct gprefix *gprefix;
045a282c 216 const struct escape *esc;
39f062ff 217 const struct instr_dual *idual;
e28bbd44 218 void (*fastop)(struct fastop *fake);
120df890 219 } u;
d09beabd 220 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 221};
222
223struct group_dual {
224 struct opcode mod012[8];
225 struct opcode mod3[8];
d65b1dee
AK		 226};
227
0d7cdee8
AK		 228struct gprefix {
229 struct opcode pfx_no;
230 struct opcode pfx_66;
231 struct opcode pfx_f2;
232 struct opcode pfx_f3;
233};
234
045a282c
GN		 235struct escape {
236 struct opcode op[8];
237 struct opcode high[64];
238};
239
39f062ff
NA		 240struct instr_dual {
241 struct opcode mod012;
242 struct opcode mod3;
243};
244
6aa8b732 245/* EFLAGS bit definitions. */
d4c6a154
GN		 246#define EFLG_ID (1<<21)
247#define EFLG_VIP (1<<20)
248#define EFLG_VIF (1<<19)
249#define EFLG_AC (1<<18)
b1d86143
AP		 250#define EFLG_VM (1<<17)
251#define EFLG_RF (1<<16)
d4c6a154
GN		 252#define EFLG_IOPL (3<<12)
253#define EFLG_NT (1<<14)
6aa8b732
AK		 254#define EFLG_OF (1<<11)
255#define EFLG_DF (1<<10)
b1d86143 256#define EFLG_IF (1<<9)
d4c6a154 257#define EFLG_TF (1<<8)
6aa8b732
AK		 258#define EFLG_SF (1<<7)
259#define EFLG_ZF (1<<6)
260#define EFLG_AF (1<<4)
261#define EFLG_PF (1<<2)
262#define EFLG_CF (1<<0)
263
62bd430e
MG		 264#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
265#define EFLG_RESERVED_ONE_MASK 2
266
3dc4bc4f
NA		 267enum x86_transfer_type {
268 X86_TRANSFER_NONE,
269 X86_TRANSFER_CALL_JMP,
270 X86_TRANSFER_RET,
271 X86_TRANSFER_TASK_SWITCH,
272};
273
dd856efa
AK		 274static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 if (!(ctxt->regs_valid & (1 << nr))) {
277 ctxt->regs_valid |= 1 << nr;
278 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
279 }
280 return ctxt->_regs[nr];
281}
282
283static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
284{
285 ctxt->regs_valid |= 1 << nr;
286 ctxt->regs_dirty |= 1 << nr;
287 return &ctxt->_regs[nr];
288}
289
290static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
291{
292 reg_read(ctxt, nr);
293 return reg_write(ctxt, nr);
294}
295
296static void writeback_registers(struct x86_emulate_ctxt *ctxt)
297{
298 unsigned reg;
299
300 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
301 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
302}
303
304static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
305{
306 ctxt->regs_dirty = 0;
307 ctxt->regs_valid = 0;
308}
309
6aa8b732
AK		 310/*
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
313 */
314#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
315
dda96d8f
AK		 316#ifdef CONFIG_X86_64
317#define ON64(x) x
318#else
319#define ON64(x)
320#endif
321
4d758349
AK		 322static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
323
b7d491e7
AK		 324#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
325#define FOP_RET "ret \n\t"
326
327#define FOP_START(op) \
328 extern void em_##op(struct fastop *fake); \
329 asm(".pushsection .text, \"ax\" \n\t" \
330 ".global em_" #op " \n\t" \
331 FOP_ALIGN \
332 "em_" #op ": \n\t"
333
334#define FOP_END \
335 ".popsection")
336
0bdea068
AK		 337#define FOPNOP() FOP_ALIGN FOP_RET
338
b7d491e7 339#define FOP1E(op, dst) \
b8c0b6ae
AK		 340 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
341
342#define FOP1EEX(op, dst) \
343 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 344
345#define FASTOP1(op) \
346 FOP_START(op) \
347 FOP1E(op##b, al) \
348 FOP1E(op##w, ax) \
349 FOP1E(op##l, eax) \
350 ON64(FOP1E(op##q, rax)) \
351 FOP_END
352
b9fa409b
AK		 353/* 1-operand, using src2 (for MUL/DIV r/m) */
354#define FASTOP1SRC2(op, name) \
355 FOP_START(name) \
356 FOP1E(op, cl) \
357 FOP1E(op, cx) \
358 FOP1E(op, ecx) \
359 ON64(FOP1E(op, rcx)) \
360 FOP_END
361
b8c0b6ae
AK		 362/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
363#define FASTOP1SRC2EX(op, name) \
364 FOP_START(name) \
365 FOP1EEX(op, cl) \
366 FOP1EEX(op, cx) \
367 FOP1EEX(op, ecx) \
368 ON64(FOP1EEX(op, rcx)) \
369 FOP_END
370
f7857f35
AK		 371#define FOP2E(op, dst, src) \
372 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
373
374#define FASTOP2(op) \
375 FOP_START(op) \
017da7b6
AK		 376 FOP2E(op##b, al, dl) \
377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 380 FOP_END
381
11c363ba
AK		 382/* 2 operand, word only */
383#define FASTOP2W(op) \
384 FOP_START(op) \
385 FOPNOP() \
017da7b6
AK		 386 FOP2E(op##w, ax, dx) \
387 FOP2E(op##l, eax, edx) \
388 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 389 FOP_END
390
007a3b54
AK		 391/* 2 operand, src is CL */
392#define FASTOP2CL(op) \
393 FOP_START(op) \
394 FOP2E(op##b, al, cl) \
395 FOP2E(op##w, ax, cl) \
396 FOP2E(op##l, eax, cl) \
397 ON64(FOP2E(op##q, rax, cl)) \
398 FOP_END
399
5aca3722
NA		 400/* 2 operand, src and dest are reversed */
401#define FASTOP2R(op, name) \
402 FOP_START(name) \
403 FOP2E(op##b, dl, al) \
404 FOP2E(op##w, dx, ax) \
405 FOP2E(op##l, edx, eax) \
406 ON64(FOP2E(op##q, rdx, rax)) \
407 FOP_END
408
0bdea068
AK		 409#define FOP3E(op, dst, src, src2) \
410 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
411
412/* 3-operand, word-only, src2=cl */
413#define FASTOP3WCL(op) \
414 FOP_START(op) \
415 FOPNOP() \
017da7b6
AK		 416 FOP3E(op##w, ax, dx, cl) \
417 FOP3E(op##l, eax, edx, cl) \
418 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 419 FOP_END
420
9ae9feba
AK		 421/* Special case for SETcc - 1 instruction per cc */
422#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
423
b8c0b6ae
AK		 424asm(".global kvm_fastop_exception \n"
425 "kvm_fastop_exception: xor %esi, %esi; ret");
426
9ae9feba
AK		 427FOP_START(setcc)
428FOP_SETCC(seto)
429FOP_SETCC(setno)
430FOP_SETCC(setc)
431FOP_SETCC(setnc)
432FOP_SETCC(setz)
433FOP_SETCC(setnz)
434FOP_SETCC(setbe)
435FOP_SETCC(setnbe)
436FOP_SETCC(sets)
437FOP_SETCC(setns)
438FOP_SETCC(setp)
439FOP_SETCC(setnp)
440FOP_SETCC(setl)
441FOP_SETCC(setnl)
442FOP_SETCC(setle)
443FOP_SETCC(setnle)
444FOP_END;
445
326f578f
PB		 446FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
447FOP_END;
448
8a76d7f2
JR		 449static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
450 enum x86_intercept intercept,
451 enum x86_intercept_stage stage)
452{
453 struct x86_instruction_info info = {
454 .intercept = intercept,
9dac77fa
AK		 455 .rep_prefix = ctxt->rep_prefix,
456 .modrm_mod = ctxt->modrm_mod,
457 .modrm_reg = ctxt->modrm_reg,
458 .modrm_rm = ctxt->modrm_rm,
459 .src_val = ctxt->src.val64,
6cbc5f5a 460 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 461 .src_bytes = ctxt->src.bytes,
462 .dst_bytes = ctxt->dst.bytes,
463 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 464 .next_rip = ctxt->eip,
465 };
466
2953538e 467 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 468}
469
f47cfa31
AK		 470static void assign_masked(ulong *dest, ulong src, ulong mask)
471{
472 *dest = (*dest & ~mask) | (src & mask);
473}
474
9dac77fa 475static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 476{
9dac77fa 477 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 478}
479
f47cfa31
AK		 480static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
481{
482 u16 sel;
483 struct desc_struct ss;
484
485 if (ctxt->mode == X86EMUL_MODE_PROT64)
486 return ~0UL;
487 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
488 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
489}
490
612e89f0
AK		 491static int stack_size(struct x86_emulate_ctxt *ctxt)
492{
493 return (__fls(stack_mask(ctxt)) + 1) >> 3;
494}
495
6aa8b732 496/* Access/update address held in a register, based on addressing mode. */
e4706772 497static inline unsigned long
9dac77fa 498address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 499{
9dac77fa 500 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 501 return reg;
502 else
9dac77fa 503 return reg & ad_mask(ctxt);
e4706772
HH		 504}
505
506static inline unsigned long
01485a22 507register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 508{
01485a22 509 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 510}
511
5ad105e5
AK		 512static void masked_increment(ulong *reg, ulong mask, int inc)
513{
514 assign_masked(reg, *reg + inc, mask);
515}
516
7a957275 517static inline void
01485a22 518register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 519{
5ad105e5
AK		 520 ulong mask;
521
9dac77fa 522 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 523 mask = ~0UL;
7a957275 524 else
5ad105e5 525 mask = ad_mask(ctxt);
01485a22 526 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 527}
528
529static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
530{
dd856efa 531 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 532}
6aa8b732 533
56697687
AK		 534static u32 desc_limit_scaled(struct desc_struct *desc)
535{
536 u32 limit = get_desc_limit(desc);
537
538 return desc->g ? (limit << 12) | 0xfff : limit;
539}
540
7b105ca2 541static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 542{
543 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
544 return 0;
545
7b105ca2 546 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 547}
548
35d3d4a1
AK		 549static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
550 u32 error, bool valid)
54b8486f 551{
e0ad0b47 552 WARN_ON(vec > 0x1f);
da9cb575
AK		 553 ctxt->exception.vector = vec;
554 ctxt->exception.error_code = error;
555 ctxt->exception.error_code_valid = valid;
35d3d4a1 556 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 557}
558
3b88e41a
JR		 559static int emulate_db(struct x86_emulate_ctxt *ctxt)
560{
561 return emulate_exception(ctxt, DB_VECTOR, 0, false);
562}
563
35d3d4a1 564static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 565{
35d3d4a1 566 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 567}
568
618ff15d
AK		 569static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
570{
571 return emulate_exception(ctxt, SS_VECTOR, err, true);
572}
573
35d3d4a1 574static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 575{
35d3d4a1 576 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 577}
578
35d3d4a1 579static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 580{
35d3d4a1 581 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 582}
583
34d1f490
AK		 584static int emulate_de(struct x86_emulate_ctxt *ctxt)
585{
35d3d4a1 586 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 587}
588
1253791d
AK		 589static int emulate_nm(struct x86_emulate_ctxt *ctxt)
590{
591 return emulate_exception(ctxt, NM_VECTOR, 0, false);
592}
593
1aa36616
AK		 594static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
595{
596 u16 selector;
597 struct desc_struct desc;
598
599 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
600 return selector;
601}
602
603static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
604 unsigned seg)
605{
606 u16 dummy;
607 u32 base3;
608 struct desc_struct desc;
609
610 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
611 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
612}
613
1c11b376
AK		 614/*
615 * x86 defines three classes of vector instructions: explicitly
616 * aligned, explicitly unaligned, and the rest, which change behaviour
617 * depending on whether they're AVX encoded or not.
618 *
619 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
620 * subject to the same check.
621 */
622static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
623{
624 if (likely(size < 16))
625 return false;
626
627 if (ctxt->d & Aligned)
628 return true;
629 else if (ctxt->d & Unaligned)
630 return false;
631 else if (ctxt->d & Avx)
632 return false;
633 else
634 return true;
635}
636
d09155d2
PB		 637static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 unsigned *max_size, unsigned size,
640 bool write, bool fetch,
d50eaa18 641 enum x86emul_mode mode, ulong *linear)
52fd8b44 642{
618ff15d
AK		 643 struct desc_struct desc;
644 bool usable;
52fd8b44 645 ulong la;
618ff15d 646 u32 lim;
1aa36616 647 u16 sel;
52fd8b44 648
7b105ca2 649 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 650 *max_size = 0;
d50eaa18 651 switch (mode) {
618ff15d 652 case X86EMUL_MODE_PROT64:
4be4de7e 653 if (is_noncanonical_address(la))
abc7d8a4 654 goto bad;
fd56e154
PB		 655
656 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
657 if (size > *max_size)
658 goto bad;
618ff15d
AK		 659 break;
660 default:
1aa36616
AK		 661 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
662 addr.seg);
618ff15d
AK		 663 if (!usable)
664 goto bad;
58b7825b
GN		 665 /* code segment in protected mode or read-only data segment */
666 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
667 || !(desc.type & 2)) && write)
618ff15d
AK		 668 goto bad;
669 /* unreadable code segment */
3d9b938e 670 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 671 goto bad;
672 lim = desc_limit_scaled(&desc);
997b0412 673 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 674 /* expand-down segment */
fd56e154 675 if (addr.ea <= lim)
618ff15d
AK		 676 goto bad;
677 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 678 }
997b0412
PB		 679 if (addr.ea > lim)
680 goto bad;
681 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 682 if (size > *max_size)
683 goto bad;
31ff6488 684 la &= (u32)-1;
618ff15d
AK		 685 break;
686 }
1c11b376
AK		 687 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
688 return emulate_gp(ctxt, 0);
52fd8b44
AK		 689 *linear = la;
690 return X86EMUL_CONTINUE;
618ff15d
AK		 691bad:
692 if (addr.seg == VCPU_SREG_SS)
3606189f 693 return emulate_ss(ctxt, 0);
618ff15d 694 else
3606189f 695 return emulate_gp(ctxt, 0);
52fd8b44
AK		 696}
697
3d9b938e
NE		 698static int linearize(struct x86_emulate_ctxt *ctxt,
699 struct segmented_address addr,
700 unsigned size, bool write,
701 ulong *linear)
702{
fd56e154 703 unsigned max_size;
d50eaa18
NA		 704 return __linearize(ctxt, addr, &max_size, size, write, false,
705 ctxt->mode, linear);
3d9b938e
NE		 706}
707
d50eaa18
NA		 708static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
709 enum x86emul_mode mode)
710{
711 ulong linear;
712 int rc;
713 unsigned max_size;
714 struct segmented_address addr = { .seg = VCPU_SREG_CS,
715 .ea = dst };
716
717 if (ctxt->op_bytes != sizeof(unsigned long))
718 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
719 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
720 if (rc == X86EMUL_CONTINUE)
721 ctxt->_eip = addr.ea;
722 return rc;
723}
724
725static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
726{
727 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 728}
729
d50eaa18
NA		 730static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
731 const struct desc_struct *cs_desc)
732{
733 enum x86emul_mode mode = ctxt->mode;
734
735#ifdef CONFIG_X86_64
736 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
737 u64 efer = 0;
738
739 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
740 if (efer & EFER_LMA)
741 mode = X86EMUL_MODE_PROT64;
742 }
743#endif
744 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
745 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
746 return assign_eip(ctxt, dst, mode);
747}
748
749static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
750{
751 return assign_eip_near(ctxt, ctxt->_eip + rel);
752}
3d9b938e 753
3ca3ac4d
AK		 754static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
755 struct segmented_address addr,
756 void *data,
757 unsigned size)
758{
9fa088f4
AK		 759 int rc;
760 ulong linear;
761
83b8795a 762 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 763 if (rc != X86EMUL_CONTINUE)
764 return rc;
0f65dd70 765 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 766}
767
807941b1 768/*
285ca9e9 769 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 770 * boundary if they are not in fetch_cache yet.
771 */
9506d57d 772static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 773{
62266869 774 int rc;
fd56e154 775 unsigned size, max_size;
285ca9e9 776 unsigned long linear;
17052f16 777 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 778 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 779 .ea = ctxt->eip + cur_size };
780
fd56e154
PB		 781 /*
782 * We do not know exactly how many bytes will be needed, and
783 * __linearize is expensive, so fetch as much as possible. We
784 * just have to avoid going beyond the 15 byte limit, the end
785 * of the segment, or the end of the page.
786 *
787 * __linearize is called with size 0 so that it does not do any
788 * boundary check itself. Instead, we use max_size to check
789 * against op_size.
790 */
d50eaa18
NA		 791 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
792 &linear);
719d5a9b
PB		 793 if (unlikely(rc != X86EMUL_CONTINUE))
794 return rc;
795
fd56e154 796 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 797 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 798
799 /*
800 * One instruction can only straddle two pages,
801 * and one has been loaded at the beginning of
802 * x86_decode_insn. So, if not enough bytes
803 * still, we must have hit the 15-byte boundary.
804 */
805 if (unlikely(size < op_size))
fd56e154
PB		 806 return emulate_gp(ctxt, 0);
807
17052f16 808 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 809 size, &ctxt->exception);
810 if (unlikely(rc != X86EMUL_CONTINUE))
811 return rc;
17052f16 812 ctxt->fetch.end += size;
3e2815e9 813 return X86EMUL_CONTINUE;
62266869
AK		 814}
815
9506d57d
PB		 816static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
817 unsigned size)
62266869 818{
08da44ae
NA		 819 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
820
821 if (unlikely(done_size < size))
822 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 823 else
824 return X86EMUL_CONTINUE;
62266869
AK		 825}
826
67cbc90d 827/* Fetch next part of the instruction being emulated. */
e85a1085 828#define insn_fetch(_type, _ctxt) \
9506d57d 829({ _type _x; \
9506d57d
PB		 830 \
831 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 832 if (rc != X86EMUL_CONTINUE) \
833 goto done; \
9506d57d 834 ctxt->_eip += sizeof(_type); \
17052f16
PB		 835 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
836 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 837 _x; \
67cbc90d
TY		 838})
839
807941b1 840#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 841({ \
9506d57d 842 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 843 if (rc != X86EMUL_CONTINUE) \
844 goto done; \
9506d57d 845 ctxt->_eip += (_size); \
17052f16
PB		 846 memcpy(_arr, ctxt->fetch.ptr, _size); \
847 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 848})
849
1e3c5cb0
RR		 850/*
851 * Given the 'reg' portion of a ModRM byte, and a register block, return a
852 * pointer into the block that addresses the relevant register.
853 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
854 */
dd856efa 855static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 856 int byteop)
6aa8b732
AK		 857{
858 void *p;
aa9ac1a6 859 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 860
6aa8b732 861 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 862 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
863 else
864 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 865 return p;
866}
867
868static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 869 struct segmented_address addr,
6aa8b732
AK		 870 u16 *size, unsigned long *address, int op_bytes)
871{
872 int rc;
873
874 if (op_bytes == 2)
875 op_bytes = 3;
876 *address = 0;
3ca3ac4d 877 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 878 if (rc != X86EMUL_CONTINUE)
6aa8b732 879 return rc;
30b31ab6 880 addr.ea += 2;
3ca3ac4d 881 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 882 return rc;
883}
884
34b77652
AK		 885FASTOP2(add);
886FASTOP2(or);
887FASTOP2(adc);
888FASTOP2(sbb);
889FASTOP2(and);
890FASTOP2(sub);
891FASTOP2(xor);
892FASTOP2(cmp);
893FASTOP2(test);
894
b9fa409b
AK		 895FASTOP1SRC2(mul, mul_ex);
896FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 897FASTOP1SRC2EX(div, div_ex);
898FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 899
34b77652
AK		 900FASTOP3WCL(shld);
901FASTOP3WCL(shrd);
902
903FASTOP2W(imul);
904
905FASTOP1(not);
906FASTOP1(neg);
907FASTOP1(inc);
908FASTOP1(dec);
909
910FASTOP2CL(rol);
911FASTOP2CL(ror);
912FASTOP2CL(rcl);
913FASTOP2CL(rcr);
914FASTOP2CL(shl);
915FASTOP2CL(shr);
916FASTOP2CL(sar);
917
918FASTOP2W(bsf);
919FASTOP2W(bsr);
920FASTOP2W(bt);
921FASTOP2W(bts);
922FASTOP2W(btr);
923FASTOP2W(btc);
924
e47a5f5f
AK		 925FASTOP2(xadd);
926
5aca3722
NA		 927FASTOP2R(cmp, cmp_r);
928
9ae9feba 929static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 930{
9ae9feba
AK		 931 u8 rc;
932 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 933
9ae9feba 934 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 935 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 936 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
937 return rc;
bbe9abbd
NK		 938}
939
91ff3cb4
AK		 940static void fetch_register_operand(struct operand *op)
941{
942 switch (op->bytes) {
943 case 1:
944 op->val = *(u8 *)op->addr.reg;
945 break;
946 case 2:
947 op->val = *(u16 *)op->addr.reg;
948 break;
949 case 4:
950 op->val = *(u32 *)op->addr.reg;
951 break;
952 case 8:
953 op->val = *(u64 *)op->addr.reg;
954 break;
955 }
956}
957
1253791d
AK		 958static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
959{
960 ctxt->ops->get_fpu(ctxt);
961 switch (reg) {
89a87c67
MK		 962 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
963 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
964 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
965 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
966 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
967 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
968 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
969 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 970#ifdef CONFIG_X86_64
89a87c67
MK		 971 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
972 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
973 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
974 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
975 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
976 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
977 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
978 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 979#endif
980 default: BUG();
981 }
982 ctxt->ops->put_fpu(ctxt);
983}
984
985static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
986 int reg)
987{
988 ctxt->ops->get_fpu(ctxt);
989 switch (reg) {
89a87c67
MK		 990 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
991 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
992 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
993 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
994 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
995 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
996 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
997 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 998#ifdef CONFIG_X86_64
89a87c67
MK		 999 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1000 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1001 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1002 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1003 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1004 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1005 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1006 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1007#endif
1008 default: BUG();
1009 }
1010 ctxt->ops->put_fpu(ctxt);
1011}
1012
cbe2c9d3
AK		 1013static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1014{
1015 ctxt->ops->get_fpu(ctxt);
1016 switch (reg) {
1017 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1018 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1019 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1020 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1021 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1022 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1023 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1024 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1025 default: BUG();
1026 }
1027 ctxt->ops->put_fpu(ctxt);
1028}
1029
1030static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1031{
1032 ctxt->ops->get_fpu(ctxt);
1033 switch (reg) {
1034 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1035 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1036 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1037 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1038 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1039 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1040 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1041 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1042 default: BUG();
1043 }
1044 ctxt->ops->put_fpu(ctxt);
1045}
1046
045a282c
GN		 1047static int em_fninit(struct x86_emulate_ctxt *ctxt)
1048{
1049 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1050 return emulate_nm(ctxt);
1051
1052 ctxt->ops->get_fpu(ctxt);
1053 asm volatile("fninit");
1054 ctxt->ops->put_fpu(ctxt);
1055 return X86EMUL_CONTINUE;
1056}
1057
1058static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1059{
1060 u16 fcw;
1061
1062 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1063 return emulate_nm(ctxt);
1064
1065 ctxt->ops->get_fpu(ctxt);
1066 asm volatile("fnstcw %0": "+m"(fcw));
1067 ctxt->ops->put_fpu(ctxt);
1068
045a282c
GN		 1069 ctxt->dst.val = fcw;
1070
1071 return X86EMUL_CONTINUE;
1072}
1073
1074static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1075{
1076 u16 fsw;
1077
1078 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1079 return emulate_nm(ctxt);
1080
1081 ctxt->ops->get_fpu(ctxt);
1082 asm volatile("fnstsw %0": "+m"(fsw));
1083 ctxt->ops->put_fpu(ctxt);
1084
045a282c
GN		 1085 ctxt->dst.val = fsw;
1086
1087 return X86EMUL_CONTINUE;
1088}
1089
1253791d 1090static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1091 struct operand *op)
3c118e24 1092{
9dac77fa 1093 unsigned reg = ctxt->modrm_reg;
33615aa9 1094
9dac77fa
AK		 1095 if (!(ctxt->d & ModRM))
1096 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1097
9dac77fa 1098 if (ctxt->d & Sse) {
1253791d
AK		 1099 op->type = OP_XMM;
1100 op->bytes = 16;
1101 op->addr.xmm = reg;
1102 read_sse_reg(ctxt, &op->vec_val, reg);
1103 return;
1104 }
cbe2c9d3
AK		 1105 if (ctxt->d & Mmx) {
1106 reg &= 7;
1107 op->type = OP_MM;
1108 op->bytes = 8;
1109 op->addr.mm = reg;
1110 return;
1111 }
1253791d 1112
3c118e24 1113 op->type = OP_REG;
6d4d85ec
GN		 1114 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1115 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1116
91ff3cb4 1117 fetch_register_operand(op);
3c118e24
AK		 1118 op->orig_val = op->val;
1119}
1120
a6e3407b
AK		 1121static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1122{
1123 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1124 ctxt->modrm_seg = VCPU_SREG_SS;
1125}
1126
1c73ef66 1127static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1128 struct operand *op)
1c73ef66 1129{
1c73ef66 1130 u8 sib;
02357bdc 1131 int index_reg, base_reg, scale;
3e2815e9 1132 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1133 ulong modrm_ea = 0;
1c73ef66 1134
02357bdc
BD		 1135 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1136 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1137 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1138
02357bdc 1139 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1140 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1141 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1142 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1143
9b88ae99 1144 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1145 op->type = OP_REG;
9dac77fa 1146 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1147 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1148 ctxt->d & ByteOp);
9dac77fa 1149 if (ctxt->d & Sse) {
1253791d
AK		 1150 op->type = OP_XMM;
1151 op->bytes = 16;
9dac77fa
AK		 1152 op->addr.xmm = ctxt->modrm_rm;
1153 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1154 return rc;
1155 }
cbe2c9d3
AK		 1156 if (ctxt->d & Mmx) {
1157 op->type = OP_MM;
1158 op->bytes = 8;
bdc90722 1159 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1160 return rc;
1161 }
2dbd0dd7 1162 fetch_register_operand(op);
1c73ef66
AK		 1163 return rc;
1164 }
1165
2dbd0dd7
AK		 1166 op->type = OP_MEM;
1167
9dac77fa 1168 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1169 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1170 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1171 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1172 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1173
1174 /* 16-bit ModR/M decode. */
9dac77fa 1175 switch (ctxt->modrm_mod) {
1c73ef66 1176 case 0:
9dac77fa 1177 if (ctxt->modrm_rm == 6)
e85a1085 1178 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1179 break;
1180 case 1:
e85a1085 1181 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1182 break;
1183 case 2:
e85a1085 1184 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1185 break;
1186 }
9dac77fa 1187 switch (ctxt->modrm_rm) {
1c73ef66 1188 case 0:
2dbd0dd7 1189 modrm_ea += bx + si;
1c73ef66
AK		 1190 break;
1191 case 1:
2dbd0dd7 1192 modrm_ea += bx + di;
1c73ef66
AK		 1193 break;
1194 case 2:
2dbd0dd7 1195 modrm_ea += bp + si;
1c73ef66
AK		 1196 break;
1197 case 3:
2dbd0dd7 1198 modrm_ea += bp + di;
1c73ef66
AK		 1199 break;
1200 case 4:
2dbd0dd7 1201 modrm_ea += si;
1c73ef66
AK		 1202 break;
1203 case 5:
2dbd0dd7 1204 modrm_ea += di;
1c73ef66
AK		 1205 break;
1206 case 6:
9dac77fa 1207 if (ctxt->modrm_mod != 0)
2dbd0dd7 1208 modrm_ea += bp;
1c73ef66
AK		 1209 break;
1210 case 7:
2dbd0dd7 1211 modrm_ea += bx;
1c73ef66
AK		 1212 break;
1213 }
9dac77fa
AK		 1214 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1215 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1216 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1217 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1218 } else {
1219 /* 32/64-bit ModR/M decode. */
9dac77fa 1220 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1221 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1222 index_reg |= (sib >> 3) & 7;
1223 base_reg |= sib & 7;
1224 scale = sib >> 6;
1225
9dac77fa 1226 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1227 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1228 else {
dd856efa 1229 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1230 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1231 /* Increment ESP on POP [ESP] */
1232 if ((ctxt->d & IncSP) &&
1233 base_reg == VCPU_REGS_RSP)
1234 modrm_ea += ctxt->op_bytes;
a6e3407b 1235 }
dc71d0f1 1236 if (index_reg != 4)
dd856efa 1237 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1238 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1239 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1240 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1241 ctxt->rip_relative = 1;
a6e3407b
AK		 1242 } else {
1243 base_reg = ctxt->modrm_rm;
dd856efa 1244 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1245 adjust_modrm_seg(ctxt, base_reg);
1246 }
9dac77fa 1247 switch (ctxt->modrm_mod) {
1c73ef66 1248 case 1:
e85a1085 1249 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1250 break;
1251 case 2:
e85a1085 1252 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1253 break;
1254 }
1255 }
90de84f5 1256 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1257 if (ctxt->ad_bytes != 8)
1258 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1259
1c73ef66
AK		 1260done:
1261 return rc;
1262}
1263
1264static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1265 struct operand *op)
1c73ef66 1266{
3e2815e9 1267 int rc = X86EMUL_CONTINUE;
1c73ef66 1268
2dbd0dd7 1269 op->type = OP_MEM;
9dac77fa 1270 switch (ctxt->ad_bytes) {
1c73ef66 1271 case 2:
e85a1085 1272 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1273 break;
1274 case 4:
e85a1085 1275 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1276 break;
1277 case 8:
e85a1085 1278 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1279 break;
1280 }
1281done:
1282 return rc;
1283}
1284
9dac77fa 1285static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1286{
7129eeca 1287 long sv = 0, mask;
35c843c4 1288
9dac77fa 1289 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1290 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1291
9dac77fa
AK		 1292 if (ctxt->src.bytes == 2)
1293 sv = (s16)ctxt->src.val & (s16)mask;
1294 else if (ctxt->src.bytes == 4)
1295 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1296 else
1297 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1298
1c1c35ae
NA		 1299 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1300 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1301 }
ba7ff2b7
WY		 1302
1303 /* only subword offset */
9dac77fa 1304 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1305}
1306
dde7e6d1 1307static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1308 unsigned long addr, void *dest, unsigned size)
6aa8b732 1309{
dde7e6d1 1310 int rc;
9dac77fa 1311 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1312
f23b070e
XG		 1313 if (mc->pos < mc->end)
1314 goto read_cached;
6aa8b732 1315
f23b070e
XG		 1316 WARN_ON((mc->end + size) >= sizeof(mc->data));
1317
1318 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1319 &ctxt->exception);
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 mc->end += size;
1324
1325read_cached:
1326 memcpy(dest, mc->data + mc->pos, size);
1327 mc->pos += size;
dde7e6d1
AK		 1328 return X86EMUL_CONTINUE;
1329}
6aa8b732 1330
3ca3ac4d
AK		 1331static int segmented_read(struct x86_emulate_ctxt *ctxt,
1332 struct segmented_address addr,
1333 void *data,
1334 unsigned size)
1335{
9fa088f4
AK		 1336 int rc;
1337 ulong linear;
1338
83b8795a 1339 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
7b105ca2 1342 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1343}
1344
1345static int segmented_write(struct x86_emulate_ctxt *ctxt,
1346 struct segmented_address addr,
1347 const void *data,
1348 unsigned size)
1349{
9fa088f4
AK		 1350 int rc;
1351 ulong linear;
1352
83b8795a 1353 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1354 if (rc != X86EMUL_CONTINUE)
1355 return rc;
0f65dd70
AK		 1356 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1357 &ctxt->exception);
3ca3ac4d
AK		 1358}
1359
1360static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1361 struct segmented_address addr,
1362 const void *orig_data, const void *data,
1363 unsigned size)
1364{
9fa088f4
AK		 1365 int rc;
1366 ulong linear;
1367
83b8795a 1368 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1369 if (rc != X86EMUL_CONTINUE)
1370 return rc;
0f65dd70
AK		 1371 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1372 size, &ctxt->exception);
3ca3ac4d
AK		 1373}
1374
dde7e6d1 1375static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1376 unsigned int size, unsigned short port,
1377 void *dest)
1378{
9dac77fa 1379 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1380
dde7e6d1 1381 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1382 unsigned int in_page, n;
9dac77fa 1383 unsigned int count = ctxt->rep_prefix ?
dd856efa 1384 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1385 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1386 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1387 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1388 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1389 if (n == 0)
1390 n = 1;
1391 rc->pos = rc->end = 0;
7b105ca2 1392 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1393 return 0;
1394 rc->end = n * size;
6aa8b732
AK		 1395 }
1396
e6e39f04
NA		 1397 if (ctxt->rep_prefix && (ctxt->d & String) &&
1398 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1399 ctxt->dst.data = rc->data + rc->pos;
1400 ctxt->dst.type = OP_MEM_STR;
1401 ctxt->dst.count = (rc->end - rc->pos) / size;
1402 rc->pos = rc->end;
1403 } else {
1404 memcpy(dest, rc->data + rc->pos, size);
1405 rc->pos += size;
1406 }
dde7e6d1
AK		 1407 return 1;
1408}
6aa8b732 1409
7f3d35fd
KW		 1410static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1411 u16 index, struct desc_struct *desc)
1412{
1413 struct desc_ptr dt;
1414 ulong addr;
1415
1416 ctxt->ops->get_idt(ctxt, &dt);
1417
1418 if (dt.size < index * 8 + 7)
1419 return emulate_gp(ctxt, index << 3 | 0x2);
1420
1421 addr = dt.address + index * 8;
1422 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1423 &ctxt->exception);
1424}
1425
dde7e6d1 1426static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1427 u16 selector, struct desc_ptr *dt)
1428{
0225fb50 1429 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1430 u32 base3 = 0;
7b105ca2 1431
dde7e6d1
AK		 1432 if (selector & 1 << 2) {
1433 struct desc_struct desc;
1aa36616
AK		 1434 u16 sel;
1435
dde7e6d1 1436 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1437 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1438 VCPU_SREG_LDTR))
dde7e6d1 1439 return;
e09d082c 1440
dde7e6d1 1441 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1442 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1443 } else
4bff1e86 1444 ops->get_gdt(ctxt, dt);
dde7e6d1 1445}
120df890 1446
dde7e6d1
AK		 1447/* allowed just for 8 bytes segments */
1448static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1449 u16 selector, struct desc_struct *desc,
1450 ulong *desc_addr_p)
dde7e6d1
AK		 1451{
1452 struct desc_ptr dt;
1453 u16 index = selector >> 3;
dde7e6d1 1454 ulong addr;
120df890 1455
7b105ca2 1456 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1457
35d3d4a1
AK		 1458 if (dt.size < index * 8 + 7)
1459 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1460
e919464b 1461 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1462 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1463 &ctxt->exception);
dde7e6d1 1464}
ef65c889 1465
dde7e6d1
AK		 1466/* allowed just for 8 bytes segments */
1467static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1468 u16 selector, struct desc_struct *desc)
1469{
1470 struct desc_ptr dt;
1471 u16 index = selector >> 3;
dde7e6d1 1472 ulong addr;
6aa8b732 1473
7b105ca2 1474 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1475
35d3d4a1
AK		 1476 if (dt.size < index * 8 + 7)
1477 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1478
dde7e6d1 1479 addr = dt.address + index * 8;
7b105ca2
TY		 1480 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1481 &ctxt->exception);
dde7e6d1 1482}
c7e75a3d 1483
5601d05b 1484/* Does not support long mode */
2356aaeb 1485static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1486 u16 selector, int seg, u8 cpl,
3dc4bc4f 1487 enum x86_transfer_type transfer,
d1442d85 1488 struct desc_struct *desc)
dde7e6d1 1489{
869be99c 1490 struct desc_struct seg_desc, old_desc;
2356aaeb 1491 u8 dpl, rpl;
dde7e6d1
AK		 1492 unsigned err_vec = GP_VECTOR;
1493 u32 err_code = 0;
1494 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1495 ulong desc_addr;
dde7e6d1 1496 int ret;
03ebebeb 1497 u16 dummy;
e37a75a1 1498 u32 base3 = 0;
69f55cb1 1499
dde7e6d1 1500 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1501
f8da94e9
KW		 1502 if (ctxt->mode == X86EMUL_MODE_REAL) {
1503 /* set real mode segment descriptor (keep limit etc. for
1504 * unreal mode) */
03ebebeb 1505 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1506 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1507 goto load;
f8da94e9
KW		 1508 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1509 /* VM86 needs a clean new segment descriptor */
1510 set_desc_base(&seg_desc, selector << 4);
1511 set_desc_limit(&seg_desc, 0xffff);
1512 seg_desc.type = 3;
1513 seg_desc.p = 1;
1514 seg_desc.s = 1;
1515 seg_desc.dpl = 3;
1516 goto load;
dde7e6d1
AK		 1517 }
1518
79d5b4c3 1519 rpl = selector & 3;
79d5b4c3
AK		 1520
1521 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1522 if ((seg == VCPU_SREG_CS
1523 || (seg == VCPU_SREG_SS
1524 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1525 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1526 && null_selector)
1527 goto exception;
1528
1529 /* TR should be in GDT only */
1530 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1531 goto exception;
1532
1533 if (null_selector) /* for NULL selector skip all following checks */
1534 goto load;
1535
e919464b 1536 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1537 if (ret != X86EMUL_CONTINUE)
1538 return ret;
1539
1540 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1541 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1542 GP_VECTOR;
dde7e6d1 1543
fc058680 1544 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1545 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1546 if (transfer == X86_TRANSFER_CALL_JMP)
1547 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1548 goto exception;
3dc4bc4f 1549 }
dde7e6d1
AK		 1550
1551 if (!seg_desc.p) {
1552 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1553 goto exception;
1554 }
1555
dde7e6d1 1556 dpl = seg_desc.dpl;
dde7e6d1
AK		 1557
1558 switch (seg) {
1559 case VCPU_SREG_SS:
1560 /*
1561 * segment is not a writable data segment or segment
1562 * selector's RPL != CPL or segment selector's RPL != CPL
1563 */
1564 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1565 goto exception;
6aa8b732 1566 break;
dde7e6d1
AK		 1567 case VCPU_SREG_CS:
1568 if (!(seg_desc.type & 8))
1569 goto exception;
1570
1571 if (seg_desc.type & 4) {
1572 /* conforming */
1573 if (dpl > cpl)
1574 goto exception;
1575 } else {
1576 /* nonconforming */
1577 if (rpl > cpl || dpl != cpl)
1578 goto exception;
1579 }
040c8dc8
NA		 1580 /* in long-mode d/b must be clear if l is set */
1581 if (seg_desc.d && seg_desc.l) {
1582 u64 efer = 0;
1583
1584 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1585 if (efer & EFER_LMA)
1586 goto exception;
1587 }
1588
dde7e6d1
AK		 1589 /* CS(RPL) <- CPL */
1590 selector = (selector & 0xfffc) | cpl;
6aa8b732 1591 break;
dde7e6d1
AK		 1592 case VCPU_SREG_TR:
1593 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1594 goto exception;
869be99c
AK		 1595 old_desc = seg_desc;
1596 seg_desc.type |= 2; /* busy */
1597 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1598 sizeof(seg_desc), &ctxt->exception);
1599 if (ret != X86EMUL_CONTINUE)
1600 return ret;
dde7e6d1
AK		 1601 break;
1602 case VCPU_SREG_LDTR:
1603 if (seg_desc.s || seg_desc.type != 2)
1604 goto exception;
1605 break;
1606 default: /* DS, ES, FS, or GS */
4e62417b 1607 /*
dde7e6d1
AK		 1608 * segment is not a data or readable code segment or
1609 * ((segment is a data or nonconforming code segment)
1610 * and (both RPL and CPL > DPL))
4e62417b 1611 */
dde7e6d1
AK		 1612 if ((seg_desc.type & 0xa) == 0x8 ||
1613 (((seg_desc.type & 0xc) != 0xc) &&
1614 (rpl > dpl && cpl > dpl)))
1615 goto exception;
6aa8b732 1616 break;
dde7e6d1
AK		 1617 }
1618
1619 if (seg_desc.s) {
1620 /* mark segment as accessed */
1621 seg_desc.type |= 1;
7b105ca2 1622 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1623 if (ret != X86EMUL_CONTINUE)
1624 return ret;
e37a75a1
NA		 1625 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1626 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1627 sizeof(base3), &ctxt->exception);
1628 if (ret != X86EMUL_CONTINUE)
1629 return ret;
9a9abf6b
NA		 1630 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1631 ((u64)base3 << 32)))
1632 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1633 }
1634load:
e37a75a1 1635 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1636 if (desc)
1637 *desc = seg_desc;
dde7e6d1
AK		 1638 return X86EMUL_CONTINUE;
1639exception:
592f0858 1640 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1641}
1642
2356aaeb
PB		 1643static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1644 u16 selector, int seg)
1645{
1646 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1647 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1648 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1649}
1650
31be40b3
WY		 1651static void write_register_operand(struct operand *op)
1652{
1653 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1654 switch (op->bytes) {
1655 case 1:
1656 *(u8 *)op->addr.reg = (u8)op->val;
1657 break;
1658 case 2:
1659 *(u16 *)op->addr.reg = (u16)op->val;
1660 break;
1661 case 4:
1662 *op->addr.reg = (u32)op->val;
1663 break; /* 64b: zero-extend */
1664 case 8:
1665 *op->addr.reg = op->val;
1666 break;
1667 }
1668}
1669
fb32b1ed 1670static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1671{
fb32b1ed 1672 switch (op->type) {
dde7e6d1 1673 case OP_REG:
fb32b1ed 1674 write_register_operand(op);
6aa8b732 1675 break;
dde7e6d1 1676 case OP_MEM:
9dac77fa 1677 if (ctxt->lock_prefix)
f5f87dfb
PB		 1678 return segmented_cmpxchg(ctxt,
1679 op->addr.mem,
1680 &op->orig_val,
1681 &op->val,
1682 op->bytes);
1683 else
1684 return segmented_write(ctxt,
fb32b1ed 1685 op->addr.mem,
fb32b1ed
AK		 1686 &op->val,
1687 op->bytes);
a682e354 1688 break;
b3356bf0 1689 case OP_MEM_STR:
f5f87dfb
PB		 1690 return segmented_write(ctxt,
1691 op->addr.mem,
1692 op->data,
1693 op->bytes * op->count);
b3356bf0 1694 break;
1253791d 1695 case OP_XMM:
fb32b1ed 1696 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1697 break;
cbe2c9d3 1698 case OP_MM:
fb32b1ed 1699 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1700 break;
dde7e6d1
AK		 1701 case OP_NONE:
1702 /* no writeback */
414e6277 1703 break;
dde7e6d1 1704 default:
414e6277 1705 break;
6aa8b732 1706 }
dde7e6d1
AK		 1707 return X86EMUL_CONTINUE;
1708}
6aa8b732 1709
51ddff50 1710static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1711{
4179bb02 1712 struct segmented_address addr;
0dc8d10f 1713
5ad105e5 1714 rsp_increment(ctxt, -bytes);
dd856efa 1715 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1716 addr.seg = VCPU_SREG_SS;
1717
51ddff50
AK		 1718 return segmented_write(ctxt, addr, data, bytes);
1719}
1720
1721static int em_push(struct x86_emulate_ctxt *ctxt)
1722{
4179bb02 1723 /* Disable writeback. */
9dac77fa 1724 ctxt->dst.type = OP_NONE;
51ddff50 1725 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1726}
69f55cb1 1727
dde7e6d1 1728static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1729 void *dest, int len)
1730{
dde7e6d1 1731 int rc;
90de84f5 1732 struct segmented_address addr;
8b4caf66 1733
dd856efa 1734 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1735 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1736 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1737 if (rc != X86EMUL_CONTINUE)
1738 return rc;
1739
5ad105e5 1740 rsp_increment(ctxt, len);
dde7e6d1 1741 return rc;
8b4caf66
LV		 1742}
1743
c54fe504
TY		 1744static int em_pop(struct x86_emulate_ctxt *ctxt)
1745{
9dac77fa 1746 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1747}
1748
dde7e6d1 1749static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1750 void *dest, int len)
9de41573
GN		 1751{
1752 int rc;
dde7e6d1
AK		 1753 unsigned long val, change_mask;
1754 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1755 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1756
3b9be3bf 1757 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
9de41573 1760
dde7e6d1 1761 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1762 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1763
dde7e6d1
AK		 1764 switch(ctxt->mode) {
1765 case X86EMUL_MODE_PROT64:
1766 case X86EMUL_MODE_PROT32:
1767 case X86EMUL_MODE_PROT16:
1768 if (cpl == 0)
1769 change_mask |= EFLG_IOPL;
1770 if (cpl <= iopl)
1771 change_mask |= EFLG_IF;
1772 break;
1773 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1774 if (iopl < 3)
1775 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1776 change_mask |= EFLG_IF;
1777 break;
1778 default: /* real mode */
1779 change_mask |= (EFLG_IOPL | EFLG_IF);
1780 break;
9de41573 1781 }
dde7e6d1
AK		 1782
1783 *(unsigned long *)dest =
1784 (ctxt->eflags & ~change_mask) | (val & change_mask);
1785
1786 return rc;
9de41573
GN		 1787}
1788
62aaa2f0
TY		 1789static int em_popf(struct x86_emulate_ctxt *ctxt)
1790{
9dac77fa
AK		 1791 ctxt->dst.type = OP_REG;
1792 ctxt->dst.addr.reg = &ctxt->eflags;
1793 ctxt->dst.bytes = ctxt->op_bytes;
1794 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1795}
1796
612e89f0
AK		 1797static int em_enter(struct x86_emulate_ctxt *ctxt)
1798{
1799 int rc;
1800 unsigned frame_size = ctxt->src.val;
1801 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1802 ulong rbp;
612e89f0
AK		 1803
1804 if (nesting_level)
1805 return X86EMUL_UNHANDLEABLE;
1806
dd856efa
AK		 1807 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1808 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1809 if (rc != X86EMUL_CONTINUE)
1810 return rc;
dd856efa 1811 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1812 stack_mask(ctxt));
dd856efa
AK		 1813 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1814 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1815 stack_mask(ctxt));
1816 return X86EMUL_CONTINUE;
1817}
1818
f47cfa31
AK		 1819static int em_leave(struct x86_emulate_ctxt *ctxt)
1820{
dd856efa 1821 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1822 stack_mask(ctxt));
dd856efa 1823 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1824}
1825
1cd196ea 1826static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1827{
1cd196ea
AK		 1828 int seg = ctxt->src2.val;
1829
9dac77fa 1830 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1831 if (ctxt->op_bytes == 4) {
1832 rsp_increment(ctxt, -2);
1833 ctxt->op_bytes = 2;
1834 }
7b262e90 1835
4487b3b4 1836 return em_push(ctxt);
7b262e90
GN		 1837}
1838
1cd196ea 1839static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1840{
1cd196ea 1841 int seg = ctxt->src2.val;
dde7e6d1
AK		 1842 unsigned long selector;
1843 int rc;
38ba30ba 1844
3313bc4e 1845 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
a5457e7b
PB		 1849 if (ctxt->modrm_reg == VCPU_SREG_SS)
1850 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1851 if (ctxt->op_bytes > 2)
1852 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1853
7b105ca2 1854 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1855 return rc;
38ba30ba
GN		 1856}
1857
b96a7fad 1858static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1859{
dd856efa 1860 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1861 int rc = X86EMUL_CONTINUE;
1862 int reg = VCPU_REGS_RAX;
38ba30ba 1863
dde7e6d1
AK		 1864 while (reg <= VCPU_REGS_RDI) {
1865 (reg == VCPU_REGS_RSP) ?
dd856efa 1866 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1867
4487b3b4 1868 rc = em_push(ctxt);
dde7e6d1
AK		 1869 if (rc != X86EMUL_CONTINUE)
1870 return rc;
38ba30ba 1871
dde7e6d1 1872 ++reg;
38ba30ba 1873 }
38ba30ba 1874
dde7e6d1 1875 return rc;
38ba30ba
GN		 1876}
1877
62aaa2f0
TY		 1878static int em_pushf(struct x86_emulate_ctxt *ctxt)
1879{
bc397a6c 1880 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1881 return em_push(ctxt);
1882}
1883
b96a7fad 1884static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1885{
dde7e6d1
AK		 1886 int rc = X86EMUL_CONTINUE;
1887 int reg = VCPU_REGS_RDI;
38ba30ba 1888
dde7e6d1
AK		 1889 while (reg >= VCPU_REGS_RAX) {
1890 if (reg == VCPU_REGS_RSP) {
5ad105e5 1891 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1892 --reg;
1893 }
38ba30ba 1894
dd856efa 1895 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1896 if (rc != X86EMUL_CONTINUE)
1897 break;
1898 --reg;
38ba30ba 1899 }
dde7e6d1 1900 return rc;
38ba30ba
GN		 1901}
1902
dd856efa 1903static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1904{
0225fb50 1905 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1906 int rc;
6e154e56
MG		 1907 struct desc_ptr dt;
1908 gva_t cs_addr;
1909 gva_t eip_addr;
1910 u16 cs, eip;
6e154e56
MG		 1911
1912 /* TODO: Add limit checks */
9dac77fa 1913 ctxt->src.val = ctxt->eflags;
4487b3b4 1914 rc = em_push(ctxt);
5c56e1cf
AK		 1915 if (rc != X86EMUL_CONTINUE)
1916 return rc;
6e154e56
MG		 1917
1918 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1919
9dac77fa 1920 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1921 rc = em_push(ctxt);
5c56e1cf
AK		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
6e154e56 1924
9dac77fa 1925 ctxt->src.val = ctxt->_eip;
4487b3b4 1926 rc = em_push(ctxt);
5c56e1cf
AK		 1927 if (rc != X86EMUL_CONTINUE)
1928 return rc;
1929
4bff1e86 1930 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1931
1932 eip_addr = dt.address + (irq << 2);
1933 cs_addr = dt.address + (irq << 2) + 2;
1934
0f65dd70 1935 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1936 if (rc != X86EMUL_CONTINUE)
1937 return rc;
1938
0f65dd70 1939 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1940 if (rc != X86EMUL_CONTINUE)
1941 return rc;
1942
7b105ca2 1943 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1944 if (rc != X86EMUL_CONTINUE)
1945 return rc;
1946
9dac77fa 1947 ctxt->_eip = eip;
6e154e56
MG		 1948
1949 return rc;
1950}
1951
dd856efa
AK		 1952int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1953{
1954 int rc;
1955
1956 invalidate_registers(ctxt);
1957 rc = __emulate_int_real(ctxt, irq);
1958 if (rc == X86EMUL_CONTINUE)
1959 writeback_registers(ctxt);
1960 return rc;
1961}
1962
7b105ca2 1963static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1964{
1965 switch(ctxt->mode) {
1966 case X86EMUL_MODE_REAL:
dd856efa 1967 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1968 case X86EMUL_MODE_VM86:
1969 case X86EMUL_MODE_PROT16:
1970 case X86EMUL_MODE_PROT32:
1971 case X86EMUL_MODE_PROT64:
1972 default:
1973 /* Protected mode interrupts unimplemented yet */
1974 return X86EMUL_UNHANDLEABLE;
1975 }
1976}
1977
7b105ca2 1978static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1979{
dde7e6d1
AK		 1980 int rc = X86EMUL_CONTINUE;
1981 unsigned long temp_eip = 0;
1982 unsigned long temp_eflags = 0;
1983 unsigned long cs = 0;
1984 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1985 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1986 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1987 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1988
dde7e6d1 1989 /* TODO: Add stack limit check */
38ba30ba 1990
9dac77fa 1991 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1992
dde7e6d1
AK		 1993 if (rc != X86EMUL_CONTINUE)
1994 return rc;
38ba30ba 1995
35d3d4a1
AK		 1996 if (temp_eip & ~0xffff)
1997 return emulate_gp(ctxt, 0);
38ba30ba 1998
9dac77fa 1999 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2000
dde7e6d1
AK		 2001 if (rc != X86EMUL_CONTINUE)
2002 return rc;
38ba30ba 2003
9dac77fa 2004 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2005
dde7e6d1
AK		 2006 if (rc != X86EMUL_CONTINUE)
2007 return rc;
38ba30ba 2008
7b105ca2 2009 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2010
dde7e6d1
AK		 2011 if (rc != X86EMUL_CONTINUE)
2012 return rc;
38ba30ba 2013
9dac77fa 2014 ctxt->_eip = temp_eip;
38ba30ba 2015
38ba30ba 2016
9dac77fa 2017 if (ctxt->op_bytes == 4)
dde7e6d1 2018 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2019 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2020 ctxt->eflags &= ~0xffff;
2021 ctxt->eflags |= temp_eflags;
38ba30ba 2022 }
dde7e6d1
AK		 2023
2024 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2025 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2026
2027 return rc;
38ba30ba
GN		 2028}
2029
e01991e7 2030static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2031{
dde7e6d1
AK		 2032 switch(ctxt->mode) {
2033 case X86EMUL_MODE_REAL:
7b105ca2 2034 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2035 case X86EMUL_MODE_VM86:
2036 case X86EMUL_MODE_PROT16:
2037 case X86EMUL_MODE_PROT32:
2038 case X86EMUL_MODE_PROT64:
c37eda13 2039 default:
dde7e6d1
AK		 2040 /* iret from protected mode unimplemented yet */
2041 return X86EMUL_UNHANDLEABLE;
c37eda13 2042 }
c37eda13
WY		 2043}
2044
d2f62766
TY		 2045static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2046{
d2f62766 2047 int rc;
d1442d85
NA		 2048 unsigned short sel, old_sel;
2049 struct desc_struct old_desc, new_desc;
2050 const struct x86_emulate_ops *ops = ctxt->ops;
2051 u8 cpl = ctxt->ops->cpl(ctxt);
2052
2053 /* Assignment of RIP may only fail in 64-bit mode */
2054 if (ctxt->mode == X86EMUL_MODE_PROT64)
2055 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2056 VCPU_SREG_CS);
d2f62766 2057
9dac77fa 2058 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2059
3dc4bc4f
NA		 2060 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2061 X86_TRANSFER_CALL_JMP,
d1442d85 2062 &new_desc);
d2f62766
TY		 2063 if (rc != X86EMUL_CONTINUE)
2064 return rc;
2065
d50eaa18 2066 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2067 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2068 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2069 /* assigning eip failed; restore the old cs */
2070 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2071 return rc;
2072 }
2073 return rc;
d2f62766
TY		 2074}
2075
f7784046 2076static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2077{
f7784046
NA		 2078 return assign_eip_near(ctxt, ctxt->src.val);
2079}
8cdbd2c9 2080
f7784046
NA		 2081static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2082{
2083 int rc;
2084 long int old_eip;
2085
2086 old_eip = ctxt->_eip;
2087 rc = assign_eip_near(ctxt, ctxt->src.val);
2088 if (rc != X86EMUL_CONTINUE)
2089 return rc;
2090 ctxt->src.val = old_eip;
2091 rc = em_push(ctxt);
4179bb02 2092 return rc;
8cdbd2c9
LV		 2093}
2094
e0dac408 2095static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2096{
9dac77fa 2097 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2098
aaa05f24
NA		 2099 if (ctxt->dst.bytes == 16)
2100 return X86EMUL_UNHANDLEABLE;
2101
dd856efa
AK		 2102 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2103 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2104 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2105 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2106 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2107 } else {
dd856efa
AK		 2108 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2109 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2110
05f086f8 2111 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2112 }
1b30eaa8 2113 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2114}
2115
ebda02c2
TY		 2116static int em_ret(struct x86_emulate_ctxt *ctxt)
2117{
234f3ce4
NA		 2118 int rc;
2119 unsigned long eip;
2120
2121 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2122 if (rc != X86EMUL_CONTINUE)
2123 return rc;
2124
2125 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2126}
2127
e01991e7 2128static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2129{
a77ab5ea 2130 int rc;
d1442d85
NA		 2131 unsigned long eip, cs;
2132 u16 old_cs;
9e8919ae 2133 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2134 struct desc_struct old_desc, new_desc;
2135 const struct x86_emulate_ops *ops = ctxt->ops;
2136
2137 if (ctxt->mode == X86EMUL_MODE_PROT64)
2138 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2139 VCPU_SREG_CS);
a77ab5ea 2140
d1442d85 2141 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2142 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2143 return rc;
9dac77fa 2144 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2145 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2146 return rc;
9e8919ae
NA		 2147 /* Outer-privilege level return is not implemented */
2148 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2149 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2150 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2151 X86_TRANSFER_RET,
d1442d85
NA		 2152 &new_desc);
2153 if (rc != X86EMUL_CONTINUE)
2154 return rc;
d50eaa18 2155 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2156 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2157 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2158 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2159 }
a77ab5ea
AK		 2160 return rc;
2161}
2162
3261107e
BR		 2163static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2164{
2165 int rc;
2166
2167 rc = em_ret_far(ctxt);
2168 if (rc != X86EMUL_CONTINUE)
2169 return rc;
2170 rsp_increment(ctxt, ctxt->src.val);
2171 return X86EMUL_CONTINUE;
2172}
2173
e940b5c2
TY		 2174static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2175{
2176 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2177 ctxt->dst.orig_val = ctxt->dst.val;
2178 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2179 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2180 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2181 fastop(ctxt, em_cmp);
e940b5c2
TY		 2182
2183 if (ctxt->eflags & EFLG_ZF) {
2184 /* Success: write back to memory. */
2185 ctxt->dst.val = ctxt->src.orig_val;
2186 } else {
2187 /* Failure: write the value we saw to EAX. */
2188 ctxt->dst.type = OP_REG;
dd856efa 2189 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2190 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2191 }
2192 return X86EMUL_CONTINUE;
2193}
2194
d4b4325f 2195static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2196{
d4b4325f 2197 int seg = ctxt->src2.val;
09b5f4d3
WY		 2198 unsigned short sel;
2199 int rc;
2200
9dac77fa 2201 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2202
7b105ca2 2203 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2204 if (rc != X86EMUL_CONTINUE)
2205 return rc;
2206
9dac77fa 2207 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2208 return rc;
2209}
2210
7b105ca2 2211static void
e66bb2cc 2212setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2213 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2214{
e66bb2cc 2215 cs->l = 0; /* will be adjusted later */
79168fd1 2216 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2217 cs->g = 1; /* 4kb granularity */
79168fd1 2218 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2219 cs->type = 0x0b; /* Read, Execute, Accessed */
2220 cs->s = 1;
2221 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2222 cs->p = 1;
2223 cs->d = 1;
99245b50 2224 cs->avl = 0;
e66bb2cc 2225
79168fd1
GN		 2226 set_desc_base(ss, 0); /* flat segment */
2227 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2228 ss->g = 1; /* 4kb granularity */
2229 ss->s = 1;
2230 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2231 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2232 ss->dpl = 0;
79168fd1 2233 ss->p = 1;
99245b50
GN		 2234 ss->l = 0;
2235 ss->avl = 0;
e66bb2cc
AP		 2236}
2237
1a18a69b
AK		 2238static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2239{
2240 u32 eax, ebx, ecx, edx;
2241
2242 eax = ecx = 0;
0017f93a
AK		 2243 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2244 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2245 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2246 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2247}
2248
c2226fc9
SB		 2249static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2250{
0225fb50 2251 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2252 u32 eax, ebx, ecx, edx;
2253
2254 /*
2255 * syscall should always be enabled in longmode - so only become
2256 * vendor specific (cpuid) if other modes are active...
2257 */
2258 if (ctxt->mode == X86EMUL_MODE_PROT64)
2259 return true;
2260
2261 eax = 0x00000000;
2262 ecx = 0x00000000;
0017f93a
AK		 2263 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2264 /*
2265 * Intel ("GenuineIntel")
2266 * remark: Intel CPUs only support "syscall" in 64bit
2267 * longmode. Also an 64bit guest with a
2268 * 32bit compat-app running will #UD !! While this
2269 * behaviour can be fixed (by emulating) into AMD
2270 * response - CPUs of AMD can't behave like Intel.
2271 */
2272 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2273 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2274 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2275 return false;
2276
2277 /* AMD ("AuthenticAMD") */
2278 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2279 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2280 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2281 return true;
2282
2283 /* AMD ("AMDisbetter!") */
2284 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2285 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2286 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2287 return true;
c2226fc9
SB		 2288
2289 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2290 return false;
2291}
2292
e01991e7 2293static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2294{
0225fb50 2295 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2296 struct desc_struct cs, ss;
e66bb2cc 2297 u64 msr_data;
79168fd1 2298 u16 cs_sel, ss_sel;
c2ad2bb3 2299 u64 efer = 0;
e66bb2cc
AP		 2300
2301 /* syscall is not available in real mode */
2e901c4c 2302 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2303 ctxt->mode == X86EMUL_MODE_VM86)
2304 return emulate_ud(ctxt);
e66bb2cc 2305
c2226fc9
SB		 2306 if (!(em_syscall_is_enabled(ctxt)))
2307 return emulate_ud(ctxt);
2308
c2ad2bb3 2309 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2310 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2311
c2226fc9
SB		 2312 if (!(efer & EFER_SCE))
2313 return emulate_ud(ctxt);
2314
717746e3 2315 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2316 msr_data >>= 32;
79168fd1
GN		 2317 cs_sel = (u16)(msr_data & 0xfffc);
2318 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2319
c2ad2bb3 2320 if (efer & EFER_LMA) {
79168fd1 2321 cs.d = 0;
e66bb2cc
AP		 2322 cs.l = 1;
2323 }
1aa36616
AK		 2324 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2325 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2326
dd856efa 2327 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2328 if (efer & EFER_LMA) {
e66bb2cc 2329#ifdef CONFIG_X86_64
6c6cb69b 2330 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2331
717746e3 2332 ops->get_msr(ctxt,
3fb1b5db
GN		 2333 ctxt->mode == X86EMUL_MODE_PROT64 ?
2334 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2335 ctxt->_eip = msr_data;
e66bb2cc 2336
717746e3 2337 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2338 ctxt->eflags &= ~msr_data;
807c1425 2339 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2340#endif
2341 } else {
2342 /* legacy mode */
717746e3 2343 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2344 ctxt->_eip = (u32)msr_data;
e66bb2cc 2345
6c6cb69b 2346 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2347 }
2348
e54cfa97 2349 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2350}
2351
e01991e7 2352static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2353{
0225fb50 2354 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2355 struct desc_struct cs, ss;
8c604352 2356 u64 msr_data;
79168fd1 2357 u16 cs_sel, ss_sel;
c2ad2bb3 2358 u64 efer = 0;
8c604352 2359
7b105ca2 2360 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2361 /* inject #GP if in real mode */
35d3d4a1
AK		 2362 if (ctxt->mode == X86EMUL_MODE_REAL)
2363 return emulate_gp(ctxt, 0);
8c604352 2364
1a18a69b
AK		 2365 /*
2366 * Not recognized on AMD in compat mode (but is recognized in legacy
2367 * mode).
2368 */
2369 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2370 && !vendor_intel(ctxt))
2371 return emulate_ud(ctxt);
2372
b2c9d43e 2373 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2374 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2375 return X86EMUL_UNHANDLEABLE;
8c604352 2376
7b105ca2 2377 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2378
717746e3 2379 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2380 switch (ctxt->mode) {
2381 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2382 if ((msr_data & 0xfffc) == 0x0)
2383 return emulate_gp(ctxt, 0);
8c604352
AP		 2384 break;
2385 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2386 if (msr_data == 0x0)
2387 return emulate_gp(ctxt, 0);
8c604352 2388 break;
9d1b39a9
GN		 2389 default:
2390 break;
8c604352
AP		 2391 }
2392
6c6cb69b 2393 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2394 cs_sel = (u16)msr_data;
2395 cs_sel &= ~SELECTOR_RPL_MASK;
2396 ss_sel = cs_sel + 8;
2397 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2398 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2399 cs.d = 0;
8c604352
AP		 2400 cs.l = 1;
2401 }
2402
1aa36616
AK		 2403 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2404 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2405
717746e3 2406 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2407 ctxt->_eip = msr_data;
8c604352 2408
717746e3 2409 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2410 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2411
e54cfa97 2412 return X86EMUL_CONTINUE;
8c604352
AP		 2413}
2414
e01991e7 2415static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2416{
0225fb50 2417 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2418 struct desc_struct cs, ss;
234f3ce4 2419 u64 msr_data, rcx, rdx;
4668f050 2420 int usermode;
1249b96e 2421 u16 cs_sel = 0, ss_sel = 0;
4668f050 2422
a0044755
GN		 2423 /* inject #GP if in real mode or Virtual 8086 mode */
2424 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2425 ctxt->mode == X86EMUL_MODE_VM86)
2426 return emulate_gp(ctxt, 0);
4668f050 2427
7b105ca2 2428 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2429
9dac77fa 2430 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2431 usermode = X86EMUL_MODE_PROT64;
2432 else
2433 usermode = X86EMUL_MODE_PROT32;
2434
234f3ce4
NA		 2435 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2436 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2437
4668f050
AP		 2438 cs.dpl = 3;
2439 ss.dpl = 3;
717746e3 2440 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2441 switch (usermode) {
2442 case X86EMUL_MODE_PROT32:
79168fd1 2443 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2444 if ((msr_data & 0xfffc) == 0x0)
2445 return emulate_gp(ctxt, 0);
79168fd1 2446 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2447 rcx = (u32)rcx;
2448 rdx = (u32)rdx;
4668f050
AP		 2449 break;
2450 case X86EMUL_MODE_PROT64:
79168fd1 2451 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2452 if (msr_data == 0x0)
2453 return emulate_gp(ctxt, 0);
79168fd1
GN		 2454 ss_sel = cs_sel + 8;
2455 cs.d = 0;
4668f050 2456 cs.l = 1;
234f3ce4
NA		 2457 if (is_noncanonical_address(rcx) ||
2458 is_noncanonical_address(rdx))
2459 return emulate_gp(ctxt, 0);
4668f050
AP		 2460 break;
2461 }
79168fd1
GN		 2462 cs_sel |= SELECTOR_RPL_MASK;
2463 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2464
1aa36616
AK		 2465 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2466 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2467
234f3ce4
NA		 2468 ctxt->_eip = rdx;
2469 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2470
e54cfa97 2471 return X86EMUL_CONTINUE;
4668f050
AP		 2472}
2473
7b105ca2 2474static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2475{
2476 int iopl;
2477 if (ctxt->mode == X86EMUL_MODE_REAL)
2478 return false;
2479 if (ctxt->mode == X86EMUL_MODE_VM86)
2480 return true;
2481 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2482 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2483}
2484
2485static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2486 u16 port, u16 len)
2487{
0225fb50 2488 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2489 struct desc_struct tr_seg;
5601d05b 2490 u32 base3;
f850e2e6 2491 int r;
1aa36616 2492 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2493 unsigned mask = (1 << len) - 1;
5601d05b 2494 unsigned long base;
f850e2e6 2495
1aa36616 2496 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2497 if (!tr_seg.p)
f850e2e6 2498 return false;
79168fd1 2499 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2500 return false;
5601d05b
GN		 2501 base = get_desc_base(&tr_seg);
2502#ifdef CONFIG_X86_64
2503 base |= ((u64)base3) << 32;
2504#endif
0f65dd70 2505 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2506 if (r != X86EMUL_CONTINUE)
2507 return false;
79168fd1 2508 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2509 return false;
0f65dd70 2510 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2511 if (r != X86EMUL_CONTINUE)
2512 return false;
2513 if ((perm >> bit_idx) & mask)
2514 return false;
2515 return true;
2516}
2517
2518static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2519 u16 port, u16 len)
2520{
4fc40f07
GN		 2521 if (ctxt->perm_ok)
2522 return true;
2523
7b105ca2
TY		 2524 if (emulator_bad_iopl(ctxt))
2525 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2526 return false;
4fc40f07
GN		 2527
2528 ctxt->perm_ok = true;
2529
f850e2e6
GN		 2530 return true;
2531}
2532
38ba30ba 2533static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2534 struct tss_segment_16 *tss)
2535{
9dac77fa 2536 tss->ip = ctxt->_eip;
38ba30ba 2537 tss->flag = ctxt->eflags;
dd856efa
AK		 2538 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2539 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2540 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2541 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2542 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2543 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2544 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2545 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2546
1aa36616
AK		 2547 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2548 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2549 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2550 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2551 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2552}
2553
2554static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2555 struct tss_segment_16 *tss)
2556{
38ba30ba 2557 int ret;
2356aaeb 2558 u8 cpl;
38ba30ba 2559
9dac77fa 2560 ctxt->_eip = tss->ip;
38ba30ba 2561 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2562 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2563 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2564 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2565 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2566 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2567 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2568 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2569 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2570
2571 /*
2572 * SDM says that segment selectors are loaded before segment
2573 * descriptors
2574 */
1aa36616
AK		 2575 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2576 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2577 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2578 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2579 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2580
2356aaeb
PB		 2581 cpl = tss->cs & 3;
2582
38ba30ba 2583 /*
fc058680 2584 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2585 * it is handled in a context of new task
2586 */
d1442d85 2587 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2588 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2589 if (ret != X86EMUL_CONTINUE)
2590 return ret;
d1442d85 2591 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2592 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2593 if (ret != X86EMUL_CONTINUE)
2594 return ret;
d1442d85 2595 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2596 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2597 if (ret != X86EMUL_CONTINUE)
2598 return ret;
d1442d85 2599 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2600 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
d1442d85 2603 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2604 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2605 if (ret != X86EMUL_CONTINUE)
2606 return ret;
2607
2608 return X86EMUL_CONTINUE;
2609}
2610
2611static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2612 u16 tss_selector, u16 old_tss_sel,
2613 ulong old_tss_base, struct desc_struct *new_desc)
2614{
0225fb50 2615 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2616 struct tss_segment_16 tss_seg;
2617 int ret;
bcc55cba 2618 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2619
0f65dd70 2620 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2621 &ctxt->exception);
db297e3d 2622 if (ret != X86EMUL_CONTINUE)
38ba30ba 2623 return ret;
38ba30ba 2624
7b105ca2 2625 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2626
0f65dd70 2627 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2628 &ctxt->exception);
db297e3d 2629 if (ret != X86EMUL_CONTINUE)
38ba30ba 2630 return ret;
38ba30ba 2631
0f65dd70 2632 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2633 &ctxt->exception);
db297e3d 2634 if (ret != X86EMUL_CONTINUE)
38ba30ba 2635 return ret;
38ba30ba
GN		 2636
2637 if (old_tss_sel != 0xffff) {
2638 tss_seg.prev_task_link = old_tss_sel;
2639
0f65dd70 2640 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2641 &tss_seg.prev_task_link,
2642 sizeof tss_seg.prev_task_link,
0f65dd70 2643 &ctxt->exception);
db297e3d 2644 if (ret != X86EMUL_CONTINUE)
38ba30ba 2645 return ret;
38ba30ba
GN		 2646 }
2647
7b105ca2 2648 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2649}
2650
2651static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2652 struct tss_segment_32 *tss)
2653{
5c7411e2 2654 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2655 tss->eip = ctxt->_eip;
38ba30ba 2656 tss->eflags = ctxt->eflags;
dd856efa
AK		 2657 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2658 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2659 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2660 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2661 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2662 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2663 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2664 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2665
1aa36616
AK		 2666 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2667 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2668 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2669 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2670 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2671 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2672}
2673
2674static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2675 struct tss_segment_32 *tss)
2676{
38ba30ba 2677 int ret;
2356aaeb 2678 u8 cpl;
38ba30ba 2679
7b105ca2 2680 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2681 return emulate_gp(ctxt, 0);
9dac77fa 2682 ctxt->_eip = tss->eip;
38ba30ba 2683 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2684
2685 /* General purpose registers */
dd856efa
AK		 2686 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2687 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2688 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2689 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2690 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2691 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2692 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2693 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2694
2695 /*
2696 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2697 * descriptors. This is important because CPL checks will
2698 * use CS.RPL.
38ba30ba 2699 */
1aa36616
AK		 2700 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2701 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2702 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2703 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2704 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2705 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2706 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2707
4cee4798
KW		 2708 /*
2709 * If we're switching between Protected Mode and VM86, we need to make
2710 * sure to update the mode before loading the segment descriptors so
2711 * that the selectors are interpreted correctly.
4cee4798 2712 */
2356aaeb 2713 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2714 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2715 cpl = 3;
2716 } else {
4cee4798 2717 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2718 cpl = tss->cs & 3;
2719 }
4cee4798 2720
38ba30ba
GN		 2721 /*
2722 * Now load segment descriptors. If fault happenes at this stage
2723 * it is handled in a context of new task
2724 */
d1442d85 2725 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2726 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2727 if (ret != X86EMUL_CONTINUE)
2728 return ret;
d1442d85 2729 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2730 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2731 if (ret != X86EMUL_CONTINUE)
2732 return ret;
d1442d85 2733 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2734 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
d1442d85 2737 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2738 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2739 if (ret != X86EMUL_CONTINUE)
2740 return ret;
d1442d85 2741 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2742 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2743 if (ret != X86EMUL_CONTINUE)
2744 return ret;
d1442d85 2745 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2746 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2747 if (ret != X86EMUL_CONTINUE)
2748 return ret;
d1442d85 2749 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2750 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2751 if (ret != X86EMUL_CONTINUE)
2752 return ret;
2753
2754 return X86EMUL_CONTINUE;
2755}
2756
2757static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2758 u16 tss_selector, u16 old_tss_sel,
2759 ulong old_tss_base, struct desc_struct *new_desc)
2760{
0225fb50 2761 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2762 struct tss_segment_32 tss_seg;
2763 int ret;
bcc55cba 2764 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2765 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2766 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2767
0f65dd70 2768 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2769 &ctxt->exception);
db297e3d 2770 if (ret != X86EMUL_CONTINUE)
38ba30ba 2771 return ret;
38ba30ba 2772
7b105ca2 2773 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2774
5c7411e2
NA		 2775 /* Only GP registers and segment selectors are saved */
2776 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2777 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2778 if (ret != X86EMUL_CONTINUE)
38ba30ba 2779 return ret;
38ba30ba 2780
0f65dd70 2781 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2782 &ctxt->exception);
db297e3d 2783 if (ret != X86EMUL_CONTINUE)
38ba30ba 2784 return ret;
38ba30ba
GN		 2785
2786 if (old_tss_sel != 0xffff) {
2787 tss_seg.prev_task_link = old_tss_sel;
2788
0f65dd70 2789 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2790 &tss_seg.prev_task_link,
2791 sizeof tss_seg.prev_task_link,
0f65dd70 2792 &ctxt->exception);
db297e3d 2793 if (ret != X86EMUL_CONTINUE)
38ba30ba 2794 return ret;
38ba30ba
GN		 2795 }
2796
7b105ca2 2797 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2798}
2799
2800static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2801 u16 tss_selector, int idt_index, int reason,
e269fb21 2802 bool has_error_code, u32 error_code)
38ba30ba 2803{
0225fb50 2804 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2805 struct desc_struct curr_tss_desc, next_tss_desc;
2806 int ret;
1aa36616 2807 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2808 ulong old_tss_base =
4bff1e86 2809 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2810 u32 desc_limit;
e919464b 2811 ulong desc_addr;
38ba30ba
GN		 2812
2813 /* FIXME: old_tss_base == ~0 ? */
2814
e919464b 2815 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2816 if (ret != X86EMUL_CONTINUE)
2817 return ret;
e919464b 2818 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2819 if (ret != X86EMUL_CONTINUE)
2820 return ret;
2821
2822 /* FIXME: check that next_tss_desc is tss */
2823
7f3d35fd
KW		 2824 /*
2825 * Check privileges. The three cases are task switch caused by...
2826 *
2827 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2828 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2829 * 3. jmp/call to TSS/task-gate: No check is performed since the
2830 * hardware checks it before exiting.
7f3d35fd
KW		 2831 */
2832 if (reason == TASK_SWITCH_GATE) {
2833 if (idt_index != -1) {
2834 /* Software interrupts */
2835 struct desc_struct task_gate_desc;
2836 int dpl;
2837
2838 ret = read_interrupt_descriptor(ctxt, idt_index,
2839 &task_gate_desc);
2840 if (ret != X86EMUL_CONTINUE)
2841 return ret;
2842
2843 dpl = task_gate_desc.dpl;
2844 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2845 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2846 }
38ba30ba
GN		 2847 }
2848
ceffb459
GN		 2849 desc_limit = desc_limit_scaled(&next_tss_desc);
2850 if (!next_tss_desc.p ||
2851 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2852 desc_limit < 0x2b)) {
592f0858 2853 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2854 }
2855
2856 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2857 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2858 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2859 }
2860
2861 if (reason == TASK_SWITCH_IRET)
2862 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2863
2864 /* set back link to prev task only if NT bit is set in eflags
fc058680 2865 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2866 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2867 old_tss_sel = 0xffff;
2868
2869 if (next_tss_desc.type & 8)
7b105ca2 2870 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2871 old_tss_base, &next_tss_desc);
2872 else
7b105ca2 2873 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2874 old_tss_base, &next_tss_desc);
0760d448
JK		 2875 if (ret != X86EMUL_CONTINUE)
2876 return ret;
38ba30ba
GN		 2877
2878 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2879 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2880
2881 if (reason != TASK_SWITCH_IRET) {
2882 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2883 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2884 }
2885
717746e3 2886 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2887 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2888
e269fb21 2889 if (has_error_code) {
9dac77fa
AK		 2890 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2891 ctxt->lock_prefix = 0;
2892 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2893 ret = em_push(ctxt);
e269fb21
JK		 2894 }
2895
38ba30ba
GN		 2896 return ret;
2897}
2898
2899int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2900 u16 tss_selector, int idt_index, int reason,
e269fb21 2901 bool has_error_code, u32 error_code)
38ba30ba 2902{
38ba30ba
GN		 2903 int rc;
2904
dd856efa 2905 invalidate_registers(ctxt);
9dac77fa
AK		 2906 ctxt->_eip = ctxt->eip;
2907 ctxt->dst.type = OP_NONE;
38ba30ba 2908
7f3d35fd 2909 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2910 has_error_code, error_code);
38ba30ba 2911
dd856efa 2912 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2913 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2914 writeback_registers(ctxt);
2915 }
38ba30ba 2916
a0c0ab2f 2917 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2918}
2919
f3bd64c6
GN		 2920static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2921 struct operand *op)
a682e354 2922{
b3356bf0 2923 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2924
01485a22
PB		 2925 register_address_increment(ctxt, reg, df * op->bytes);
2926 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2927}
2928
7af04fc0
AK		 2929static int em_das(struct x86_emulate_ctxt *ctxt)
2930{
7af04fc0
AK		 2931 u8 al, old_al;
2932 bool af, cf, old_cf;
2933
2934 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2935 al = ctxt->dst.val;
7af04fc0
AK		 2936
2937 old_al = al;
2938 old_cf = cf;
2939 cf = false;
2940 af = ctxt->eflags & X86_EFLAGS_AF;
2941 if ((al & 0x0f) > 9 || af) {
2942 al -= 6;
2943 cf = old_cf | (al >= 250);
2944 af = true;
2945 } else {
2946 af = false;
2947 }
2948 if (old_al > 0x99 || old_cf) {
2949 al -= 0x60;
2950 cf = true;
2951 }
2952
9dac77fa 2953 ctxt->dst.val = al;
7af04fc0 2954 /* Set PF, ZF, SF */
9dac77fa
AK		 2955 ctxt->src.type = OP_IMM;
2956 ctxt->src.val = 0;
2957 ctxt->src.bytes = 1;
158de57f 2958 fastop(ctxt, em_or);
7af04fc0
AK		 2959 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2960 if (cf)
2961 ctxt->eflags |= X86_EFLAGS_CF;
2962 if (af)
2963 ctxt->eflags |= X86_EFLAGS_AF;
2964 return X86EMUL_CONTINUE;
2965}
2966
a035d5c6
PB		 2967static int em_aam(struct x86_emulate_ctxt *ctxt)
2968{
2969 u8 al, ah;
2970
2971 if (ctxt->src.val == 0)
2972 return emulate_de(ctxt);
2973
2974 al = ctxt->dst.val & 0xff;
2975 ah = al / ctxt->src.val;
2976 al %= ctxt->src.val;
2977
2978 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2979
2980 /* Set PF, ZF, SF */
2981 ctxt->src.type = OP_IMM;
2982 ctxt->src.val = 0;
2983 ctxt->src.bytes = 1;
2984 fastop(ctxt, em_or);
2985
2986 return X86EMUL_CONTINUE;
2987}
2988
7f662273
GN		 2989static int em_aad(struct x86_emulate_ctxt *ctxt)
2990{
2991 u8 al = ctxt->dst.val & 0xff;
2992 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2993
2994 al = (al + (ah * ctxt->src.val)) & 0xff;
2995
2996 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2997
f583c29b
GN		 2998 /* Set PF, ZF, SF */
2999 ctxt->src.type = OP_IMM;
3000 ctxt->src.val = 0;
3001 ctxt->src.bytes = 1;
3002 fastop(ctxt, em_or);
7f662273
GN		 3003
3004 return X86EMUL_CONTINUE;
3005}
3006
d4ddafcd
TY		 3007static int em_call(struct x86_emulate_ctxt *ctxt)
3008{
234f3ce4 3009 int rc;
d4ddafcd
TY		 3010 long rel = ctxt->src.val;
3011
3012 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3013 rc = jmp_rel(ctxt, rel);
3014 if (rc != X86EMUL_CONTINUE)
3015 return rc;
d4ddafcd
TY		 3016 return em_push(ctxt);
3017}
3018
0ef753b8
AK		 3019static int em_call_far(struct x86_emulate_ctxt *ctxt)
3020{
0ef753b8
AK		 3021 u16 sel, old_cs;
3022 ulong old_eip;
3023 int rc;
d1442d85
NA		 3024 struct desc_struct old_desc, new_desc;
3025 const struct x86_emulate_ops *ops = ctxt->ops;
3026 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3027
9dac77fa 3028 old_eip = ctxt->_eip;
d1442d85 3029 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3030
9dac77fa 3031 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3032 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3033 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3034 if (rc != X86EMUL_CONTINUE)
80976dbb 3035 return rc;
0ef753b8 3036
d50eaa18 3037 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3038 if (rc != X86EMUL_CONTINUE)
3039 goto fail;
0ef753b8 3040
9dac77fa 3041 ctxt->src.val = old_cs;
4487b3b4 3042 rc = em_push(ctxt);
0ef753b8 3043 if (rc != X86EMUL_CONTINUE)
d1442d85 3044 goto fail;
0ef753b8 3045
9dac77fa 3046 ctxt->src.val = old_eip;
d1442d85
NA		 3047 rc = em_push(ctxt);
3048 /* If we failed, we tainted the memory, but the very least we should
3049 restore cs */
3050 if (rc != X86EMUL_CONTINUE)
3051 goto fail;
3052 return rc;
3053fail:
3054 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3055 return rc;
3056
0ef753b8
AK		 3057}
3058
40ece7c7
AK		 3059static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3060{
40ece7c7 3061 int rc;
234f3ce4 3062 unsigned long eip;
40ece7c7 3063
234f3ce4
NA		 3064 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3065 if (rc != X86EMUL_CONTINUE)
3066 return rc;
3067 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3068 if (rc != X86EMUL_CONTINUE)
3069 return rc;
5ad105e5 3070 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3071 return X86EMUL_CONTINUE;
3072}
3073
e4f973ae
TY		 3074static int em_xchg(struct x86_emulate_ctxt *ctxt)
3075{
e4f973ae 3076 /* Write back the register source. */
9dac77fa
AK		 3077 ctxt->src.val = ctxt->dst.val;
3078 write_register_operand(&ctxt->src);
e4f973ae
TY		 3079
3080 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3081 ctxt->dst.val = ctxt->src.orig_val;
3082 ctxt->lock_prefix = 1;
e4f973ae
TY		 3083 return X86EMUL_CONTINUE;
3084}
3085
5c82aa29
AK		 3086static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3087{
9dac77fa 3088 ctxt->dst.val = ctxt->src2.val;
4d758349 3089 return fastop(ctxt, em_imul);
5c82aa29
AK		 3090}
3091
61429142
AK		 3092static int em_cwd(struct x86_emulate_ctxt *ctxt)
3093{
9dac77fa
AK		 3094 ctxt->dst.type = OP_REG;
3095 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3096 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3097 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3098
3099 return X86EMUL_CONTINUE;
3100}
3101
48bb5d3c
AK		 3102static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3103{
48bb5d3c
AK		 3104 u64 tsc = 0;
3105
717746e3 3106 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3107 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3108 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3109 return X86EMUL_CONTINUE;
3110}
3111
222d21aa
AK		 3112static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3113{
3114 u64 pmc;
3115
dd856efa 3116 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3117 return emulate_gp(ctxt, 0);
dd856efa
AK		 3118 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3119 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3120 return X86EMUL_CONTINUE;
3121}
3122
b9eac5f4
AK		 3123static int em_mov(struct x86_emulate_ctxt *ctxt)
3124{
54cfdb3e 3125 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3126 return X86EMUL_CONTINUE;
3127}
3128
84cffe49
BP		 3129#define FFL(x) bit(X86_FEATURE_##x)
3130
3131static int em_movbe(struct x86_emulate_ctxt *ctxt)
3132{
3133 u32 ebx, ecx, edx, eax = 1;
3134 u16 tmp;
3135
3136 /*
3137 * Check MOVBE is set in the guest-visible CPUID leaf.
3138 */
3139 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3140 if (!(ecx & FFL(MOVBE)))
3141 return emulate_ud(ctxt);
3142
3143 switch (ctxt->op_bytes) {
3144 case 2:
3145 /*
3146 * From MOVBE definition: "...When the operand size is 16 bits,
3147 * the upper word of the destination register remains unchanged
3148 * ..."
3149 *
3150 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3151 * rules so we have to do the operation almost per hand.
3152 */
3153 tmp = (u16)ctxt->src.val;
3154 ctxt->dst.val &= ~0xffffUL;
3155 ctxt->dst.val |= (unsigned long)swab16(tmp);
3156 break;
3157 case 4:
3158 ctxt->dst.val = swab32((u32)ctxt->src.val);
3159 break;
3160 case 8:
3161 ctxt->dst.val = swab64(ctxt->src.val);
3162 break;
3163 default:
592f0858 3164 BUG();
84cffe49
BP		 3165 }
3166 return X86EMUL_CONTINUE;
3167}
3168
bc00f8d2
TY		 3169static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3170{
3171 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3172 return emulate_gp(ctxt, 0);
3173
3174 /* Disable writeback. */
3175 ctxt->dst.type = OP_NONE;
3176 return X86EMUL_CONTINUE;
3177}
3178
3179static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3180{
3181 unsigned long val;
3182
3183 if (ctxt->mode == X86EMUL_MODE_PROT64)
3184 val = ctxt->src.val & ~0ULL;
3185 else
3186 val = ctxt->src.val & ~0U;
3187
3188 /* #UD condition is already handled. */
3189 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3190 return emulate_gp(ctxt, 0);
3191
3192 /* Disable writeback. */
3193 ctxt->dst.type = OP_NONE;
3194 return X86EMUL_CONTINUE;
3195}
3196
e1e210b0
TY		 3197static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3198{
3199 u64 msr_data;
3200
dd856efa
AK		 3201 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3202 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3203 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3204 return emulate_gp(ctxt, 0);
3205
3206 return X86EMUL_CONTINUE;
3207}
3208
3209static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3210{
3211 u64 msr_data;
3212
dd856efa 3213 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3214 return emulate_gp(ctxt, 0);
3215
dd856efa
AK		 3216 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3217 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3218 return X86EMUL_CONTINUE;
3219}
3220
1bd5f469
TY		 3221static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3222{
9dac77fa 3223 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3224 return emulate_ud(ctxt);
3225
9dac77fa 3226 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3227 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3228 ctxt->dst.bytes = 2;
1bd5f469
TY		 3229 return X86EMUL_CONTINUE;
3230}
3231
3232static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3233{
9dac77fa 3234 u16 sel = ctxt->src.val;
1bd5f469 3235
9dac77fa 3236 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3237 return emulate_ud(ctxt);
3238
9dac77fa 3239 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3240 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3241
3242 /* Disable writeback. */
9dac77fa
AK		 3243 ctxt->dst.type = OP_NONE;
3244 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3245}
3246
a14e579f
AK		 3247static int em_lldt(struct x86_emulate_ctxt *ctxt)
3248{
3249 u16 sel = ctxt->src.val;
3250
3251 /* Disable writeback. */
3252 ctxt->dst.type = OP_NONE;
3253 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3254}
3255
80890006
AK		 3256static int em_ltr(struct x86_emulate_ctxt *ctxt)
3257{
3258 u16 sel = ctxt->src.val;
3259
3260 /* Disable writeback. */
3261 ctxt->dst.type = OP_NONE;
3262 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3263}
3264
38503911
AK		 3265static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3266{
9fa088f4
AK		 3267 int rc;
3268 ulong linear;
3269
9dac77fa 3270 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3271 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3272 ctxt->ops->invlpg(ctxt, linear);
38503911 3273 /* Disable writeback. */
9dac77fa 3274 ctxt->dst.type = OP_NONE;
38503911
AK		 3275 return X86EMUL_CONTINUE;
3276}
3277
2d04a05b
AK		 3278static int em_clts(struct x86_emulate_ctxt *ctxt)
3279{
3280 ulong cr0;
3281
3282 cr0 = ctxt->ops->get_cr(ctxt, 0);
3283 cr0 &= ~X86_CR0_TS;
3284 ctxt->ops->set_cr(ctxt, 0, cr0);
3285 return X86EMUL_CONTINUE;
3286}
3287
26d05cc7
AK		 3288static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3289{
0f54a321 3290 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3291
26d05cc7
AK		 3292 if (rc != X86EMUL_CONTINUE)
3293 return rc;
3294
3295 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3296 ctxt->_eip = ctxt->eip;
26d05cc7 3297 /* Disable writeback. */
9dac77fa 3298 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3299 return X86EMUL_CONTINUE;
3300}
3301
96051572
AK		 3302static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3303 void (*get)(struct x86_emulate_ctxt *ctxt,
3304 struct desc_ptr *ptr))
3305{
3306 struct desc_ptr desc_ptr;
3307
3308 if (ctxt->mode == X86EMUL_MODE_PROT64)
3309 ctxt->op_bytes = 8;
3310 get(ctxt, &desc_ptr);
3311 if (ctxt->op_bytes == 2) {
3312 ctxt->op_bytes = 4;
3313 desc_ptr.address &= 0x00ffffff;
3314 }
3315 /* Disable writeback. */
3316 ctxt->dst.type = OP_NONE;
3317 return segmented_write(ctxt, ctxt->dst.addr.mem,
3318 &desc_ptr, 2 + ctxt->op_bytes);
3319}
3320
3321static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3322{
3323 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3324}
3325
3326static int em_sidt(struct x86_emulate_ctxt *ctxt)
3327{
3328 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3329}
3330
5b7f6a1e 3331static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3332{
26d05cc7
AK		 3333 struct desc_ptr desc_ptr;
3334 int rc;
3335
510425ff
AK		 3336 if (ctxt->mode == X86EMUL_MODE_PROT64)
3337 ctxt->op_bytes = 8;
9dac77fa 3338 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3339 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3340 ctxt->op_bytes);
26d05cc7
AK		 3341 if (rc != X86EMUL_CONTINUE)
3342 return rc;
9a9abf6b
NA		 3343 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3344 is_noncanonical_address(desc_ptr.address))
3345 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3346 if (lgdt)
3347 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3348 else
3349 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3350 /* Disable writeback. */
9dac77fa 3351 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3352 return X86EMUL_CONTINUE;
3353}
3354
5b7f6a1e
NA		 3355static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3356{
3357 return em_lgdt_lidt(ctxt, true);
3358}
3359
5ef39c71 3360static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3361{
26d05cc7
AK		 3362 int rc;
3363
5ef39c71
AK		 3364 rc = ctxt->ops->fix_hypercall(ctxt);
3365
26d05cc7 3366 /* Disable writeback. */
9dac77fa 3367 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3368 return rc;
3369}
3370
3371static int em_lidt(struct x86_emulate_ctxt *ctxt)
3372{
5b7f6a1e 3373 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3374}
3375
3376static int em_smsw(struct x86_emulate_ctxt *ctxt)
3377{
32e94d06
NA		 3378 if (ctxt->dst.type == OP_MEM)
3379 ctxt->dst.bytes = 2;
9dac77fa 3380 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3381 return X86EMUL_CONTINUE;
3382}
3383
3384static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3385{
26d05cc7 3386 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3387 | (ctxt->src.val & 0x0f));
3388 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3389 return X86EMUL_CONTINUE;
3390}
3391
d06e03ad
TY		 3392static int em_loop(struct x86_emulate_ctxt *ctxt)
3393{
234f3ce4
NA		 3394 int rc = X86EMUL_CONTINUE;
3395
01485a22 3396 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3397 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3398 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3399 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3400
234f3ce4 3401 return rc;
d06e03ad
TY		 3402}
3403
3404static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3405{
234f3ce4
NA		 3406 int rc = X86EMUL_CONTINUE;
3407
dd856efa 3408 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3409 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3410
234f3ce4 3411 return rc;
d06e03ad
TY		 3412}
3413
d7841a4b
TY		 3414static int em_in(struct x86_emulate_ctxt *ctxt)
3415{
3416 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3417 &ctxt->dst.val))
3418 return X86EMUL_IO_NEEDED;
3419
3420 return X86EMUL_CONTINUE;
3421}
3422
3423static int em_out(struct x86_emulate_ctxt *ctxt)
3424{
3425 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3426 &ctxt->src.val, 1);
3427 /* Disable writeback. */
3428 ctxt->dst.type = OP_NONE;
3429 return X86EMUL_CONTINUE;
3430}
3431
f411e6cd
TY		 3432static int em_cli(struct x86_emulate_ctxt *ctxt)
3433{
3434 if (emulator_bad_iopl(ctxt))
3435 return emulate_gp(ctxt, 0);
3436
3437 ctxt->eflags &= ~X86_EFLAGS_IF;
3438 return X86EMUL_CONTINUE;
3439}
3440
3441static int em_sti(struct x86_emulate_ctxt *ctxt)
3442{
3443 if (emulator_bad_iopl(ctxt))
3444 return emulate_gp(ctxt, 0);
3445
3446 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3447 ctxt->eflags |= X86_EFLAGS_IF;
3448 return X86EMUL_CONTINUE;
3449}
3450
6d6eede4
AK		 3451static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3452{
3453 u32 eax, ebx, ecx, edx;
3454
dd856efa
AK		 3455 eax = reg_read(ctxt, VCPU_REGS_RAX);
3456 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3457 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3458 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3459 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3460 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3461 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3462 return X86EMUL_CONTINUE;
3463}
3464
98f73630
PB		 3465static int em_sahf(struct x86_emulate_ctxt *ctxt)
3466{
3467 u32 flags;
3468
3469 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3470 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3471
3472 ctxt->eflags &= ~0xffUL;
3473 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3474 return X86EMUL_CONTINUE;
3475}
3476
2dd7caa0
AK		 3477static int em_lahf(struct x86_emulate_ctxt *ctxt)
3478{
dd856efa
AK		 3479 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3480 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3481 return X86EMUL_CONTINUE;
3482}
3483
9299836e
AK		 3484static int em_bswap(struct x86_emulate_ctxt *ctxt)
3485{
3486 switch (ctxt->op_bytes) {
3487#ifdef CONFIG_X86_64
3488 case 8:
3489 asm("bswap %0" : "+r"(ctxt->dst.val));
3490 break;
3491#endif
3492 default:
3493 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3494 break;
3495 }
3496 return X86EMUL_CONTINUE;
3497}
3498
13e457e0
NA		 3499static int em_clflush(struct x86_emulate_ctxt *ctxt)
3500{
3501 /* emulating clflush regardless of cpuid */
3502 return X86EMUL_CONTINUE;
3503}
3504
cfec82cb
JR		 3505static bool valid_cr(int nr)
3506{
3507 switch (nr) {
3508 case 0:
3509 case 2 ... 4:
3510 case 8:
3511 return true;
3512 default:
3513 return false;
3514 }
3515}
3516
3517static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3518{
9dac77fa 3519 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3520 return emulate_ud(ctxt);
3521
3522 return X86EMUL_CONTINUE;
3523}
3524
3525static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3526{
9dac77fa
AK		 3527 u64 new_val = ctxt->src.val64;
3528 int cr = ctxt->modrm_reg;
c2ad2bb3 3529 u64 efer = 0;
cfec82cb
JR		 3530
3531 static u64 cr_reserved_bits[] = {
3532 0xffffffff00000000ULL,
3533 0, 0, 0, /* CR3 checked later */
3534 CR4_RESERVED_BITS,
3535 0, 0, 0,
3536 CR8_RESERVED_BITS,
3537 };
3538
3539 if (!valid_cr(cr))
3540 return emulate_ud(ctxt);
3541
3542 if (new_val & cr_reserved_bits[cr])
3543 return emulate_gp(ctxt, 0);
3544
3545 switch (cr) {
3546 case 0: {
c2ad2bb3 3547 u64 cr4;
cfec82cb
JR		 3548 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3549 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3550 return emulate_gp(ctxt, 0);
3551
717746e3
AK		 3552 cr4 = ctxt->ops->get_cr(ctxt, 4);
3553 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3554
3555 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3556 !(cr4 & X86_CR4_PAE))
3557 return emulate_gp(ctxt, 0);
3558
3559 break;
3560 }
3561 case 3: {
3562 u64 rsvd = 0;
3563
c2ad2bb3
AK		 3564 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3565 if (efer & EFER_LMA)
9d88fca7 3566 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3567
3568 if (new_val & rsvd)
3569 return emulate_gp(ctxt, 0);
3570
3571 break;
3572 }
3573 case 4: {
717746e3 3574 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3575
3576 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3577 return emulate_gp(ctxt, 0);
3578
3579 break;
3580 }
3581 }
3582
3583 return X86EMUL_CONTINUE;
3584}
3585
3b88e41a
JR		 3586static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3587{
3588 unsigned long dr7;
3589
717746e3 3590 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3591
3592 /* Check if DR7.Global_Enable is set */
3593 return dr7 & (1 << 13);
3594}
3595
3596static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3597{
9dac77fa 3598 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3599 u64 cr4;
3600
3601 if (dr > 7)
3602 return emulate_ud(ctxt);
3603
717746e3 3604 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3605 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3606 return emulate_ud(ctxt);
3607
6d2a0526
NA		 3608 if (check_dr7_gd(ctxt)) {
3609 ulong dr6;
3610
3611 ctxt->ops->get_dr(ctxt, 6, &dr6);
3612 dr6 &= ~15;
3613 dr6 |= DR6_BD | DR6_RTM;
3614 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3615 return emulate_db(ctxt);
6d2a0526 3616 }
3b88e41a
JR		 3617
3618 return X86EMUL_CONTINUE;
3619}
3620
3621static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3622{
9dac77fa
AK		 3623 u64 new_val = ctxt->src.val64;
3624 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3625
3626 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3627 return emulate_gp(ctxt, 0);
3628
3629 return check_dr_read(ctxt);
3630}
3631
01de8b09
JR		 3632static int check_svme(struct x86_emulate_ctxt *ctxt)
3633{
3634 u64 efer;
3635
717746e3 3636 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3637
3638 if (!(efer & EFER_SVME))
3639 return emulate_ud(ctxt);
3640
3641 return X86EMUL_CONTINUE;
3642}
3643
3644static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3645{
dd856efa 3646 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3647
3648 /* Valid physical address? */
d4224449 3649 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3650 return emulate_gp(ctxt, 0);
3651
3652 return check_svme(ctxt);
3653}
3654
d7eb8203
JR		 3655static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3656{
717746e3 3657 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3658
717746e3 3659 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3660 return emulate_ud(ctxt);
3661
3662 return X86EMUL_CONTINUE;
3663}
3664
8061252e
JR		 3665static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3666{
717746e3 3667 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3668 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3669
717746e3 3670 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3671 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3672 return emulate_gp(ctxt, 0);
3673
3674 return X86EMUL_CONTINUE;
3675}
3676
f6511935
JR		 3677static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3678{
9dac77fa
AK		 3679 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3680 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3681 return emulate_gp(ctxt, 0);
3682
3683 return X86EMUL_CONTINUE;
3684}
3685
3686static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3687{
9dac77fa
AK		 3688 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3689 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3690 return emulate_gp(ctxt, 0);
3691
3692 return X86EMUL_CONTINUE;
3693}
3694
73fba5f4 3695#define D(_y) { .flags = (_y) }
d40a6898
PB		 3696#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3697#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3698 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3699#define N D(NotImpl)
01de8b09 3700#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3701#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3702#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3703#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3704#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3705#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3706#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3707#define II(_f, _e, _i) \
d40a6898 3708 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3709#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3710 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3711 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3712#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3713
8d8f4e9f 3714#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3715#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3716#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3717#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3718#define I2bvIP(_f, _e, _i, _p) \
3719 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3720
fb864fbc
AK		 3721#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3722 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3723 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3724
0f54a321
NA		 3725static const struct opcode group7_rm0[] = {
3726 N,
3727 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3728 N, N, N, N, N, N,
3729};
3730
fd0a0d82 3731static const struct opcode group7_rm1[] = {
1c2545be
TY		 3732 DI(SrcNone | Priv, monitor),
3733 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3734 N, N, N, N, N, N,
3735};
3736
fd0a0d82 3737static const struct opcode group7_rm3[] = {
1c2545be 3738 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3739 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3740 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3741 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3742 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3743 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3744 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3745 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3746};
6230f7fc 3747
fd0a0d82 3748static const struct opcode group7_rm7[] = {
d7eb8203 3749 N,
1c2545be 3750 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3751 N, N, N, N, N, N,
3752};
d67fc27a 3753
fd0a0d82 3754static const struct opcode group1[] = {
fb864fbc
AK		 3755 F(Lock, em_add),
3756 F(Lock | PageTable, em_or),
3757 F(Lock, em_adc),
3758 F(Lock, em_sbb),
3759 F(Lock | PageTable, em_and),
3760 F(Lock, em_sub),
3761 F(Lock, em_xor),
3762 F(NoWrite, em_cmp),
73fba5f4
AK		 3763};
3764
fd0a0d82 3765static const struct opcode group1A[] = {
ab708099 3766 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3767};
3768
007a3b54
AK		 3769static const struct opcode group2[] = {
3770 F(DstMem | ModRM, em_rol),
3771 F(DstMem | ModRM, em_ror),
3772 F(DstMem | ModRM, em_rcl),
3773 F(DstMem | ModRM, em_rcr),
3774 F(DstMem | ModRM, em_shl),
3775 F(DstMem | ModRM, em_shr),
3776 F(DstMem | ModRM, em_shl),
3777 F(DstMem | ModRM, em_sar),
3778};
3779
fd0a0d82 3780static const struct opcode group3[] = {
fb864fbc
AK		 3781 F(DstMem | SrcImm | NoWrite, em_test),
3782 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3783 F(DstMem | SrcNone | Lock, em_not),
3784 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3785 F(DstXacc | Src2Mem, em_mul_ex),
3786 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3787 F(DstXacc | Src2Mem, em_div_ex),
3788 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3789};
3790
fd0a0d82 3791static const struct opcode group4[] = {
95413dc4
AK		 3792 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3793 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3794 N, N, N, N, N, N,
3795};
3796
fd0a0d82 3797static const struct opcode group5[] = {
95413dc4
AK		 3798 F(DstMem | SrcNone | Lock, em_inc),
3799 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3800 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3801 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3802 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3803 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3804 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3805};
3806
fd0a0d82 3807static const struct opcode group6[] = {
1c2545be
TY		 3808 DI(Prot, sldt),
3809 DI(Prot, str),
a14e579f 3810 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3811 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3812 N, N, N, N,
3813};
3814
fd0a0d82 3815static const struct group_dual group7 = { {
606b1c3e
NA		 3816 II(Mov | DstMem, em_sgdt, sgdt),
3817 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3818 II(SrcMem | Priv, em_lgdt, lgdt),
3819 II(SrcMem | Priv, em_lidt, lidt),
3820 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3821 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3822 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3823}, {
0f54a321 3824 EXT(0, group7_rm0),
5ef39c71 3825 EXT(0, group7_rm1),
01de8b09 3826 N, EXT(0, group7_rm3),
1c2545be
TY		 3827 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3828 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3829 EXT(0, group7_rm7),
73fba5f4
AK		 3830} };
3831
fd0a0d82 3832static const struct opcode group8[] = {
73fba5f4 3833 N, N, N, N,
11c363ba
AK		 3834 F(DstMem | SrcImmByte | NoWrite, em_bt),
3835 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3836 F(DstMem | SrcImmByte | Lock, em_btr),
3837 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3838};
3839
fd0a0d82 3840static const struct group_dual group9 = { {
1c2545be 3841 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3842}, {
3843 N, N, N, N, N, N, N, N,
3844} };
3845
fd0a0d82 3846static const struct opcode group11[] = {
1c2545be 3847 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3848 X7(D(Undefined)),
a4d4a7c1
AK		 3849};
3850
13e457e0 3851static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3852 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3853};
3854
3855static const struct group_dual group15 = { {
3856 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3857}, {
3858 N, N, N, N, N, N, N, N,
3859} };
3860
fd0a0d82 3861static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3862 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3863};
3864
39f062ff
NA		 3865static const struct instr_dual instr_dual_0f_2b = {
3866 I(0, em_mov), N
3867};
3868
d5b77069 3869static const struct gprefix pfx_0f_2b = {
39f062ff 3870 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3871};
3872
27ce8258 3873static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3874 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3875};
3876
0a37027e
AW		 3877static const struct gprefix pfx_0f_e7 = {
3878 N, I(Sse, em_mov), N, N,
3879};
3880
045a282c 3881static const struct escape escape_d9 = { {
16bebefe 3882 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3883}, {
3884 /* 0xC0 - 0xC7 */
3885 N, N, N, N, N, N, N, N,
3886 /* 0xC8 - 0xCF */
3887 N, N, N, N, N, N, N, N,
3888 /* 0xD0 - 0xC7 */
3889 N, N, N, N, N, N, N, N,
3890 /* 0xD8 - 0xDF */
3891 N, N, N, N, N, N, N, N,
3892 /* 0xE0 - 0xE7 */
3893 N, N, N, N, N, N, N, N,
3894 /* 0xE8 - 0xEF */
3895 N, N, N, N, N, N, N, N,
3896 /* 0xF0 - 0xF7 */
3897 N, N, N, N, N, N, N, N,
3898 /* 0xF8 - 0xFF */
3899 N, N, N, N, N, N, N, N,
3900} };
3901
3902static const struct escape escape_db = { {
3903 N, N, N, N, N, N, N, N,
3904}, {
3905 /* 0xC0 - 0xC7 */
3906 N, N, N, N, N, N, N, N,
3907 /* 0xC8 - 0xCF */
3908 N, N, N, N, N, N, N, N,
3909 /* 0xD0 - 0xC7 */
3910 N, N, N, N, N, N, N, N,
3911 /* 0xD8 - 0xDF */
3912 N, N, N, N, N, N, N, N,
3913 /* 0xE0 - 0xE7 */
3914 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3915 /* 0xE8 - 0xEF */
3916 N, N, N, N, N, N, N, N,
3917 /* 0xF0 - 0xF7 */
3918 N, N, N, N, N, N, N, N,
3919 /* 0xF8 - 0xFF */
3920 N, N, N, N, N, N, N, N,
3921} };
3922
3923static const struct escape escape_dd = { {
16bebefe 3924 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3925}, {
3926 /* 0xC0 - 0xC7 */
3927 N, N, N, N, N, N, N, N,
3928 /* 0xC8 - 0xCF */
3929 N, N, N, N, N, N, N, N,
3930 /* 0xD0 - 0xC7 */
3931 N, N, N, N, N, N, N, N,
3932 /* 0xD8 - 0xDF */
3933 N, N, N, N, N, N, N, N,
3934 /* 0xE0 - 0xE7 */
3935 N, N, N, N, N, N, N, N,
3936 /* 0xE8 - 0xEF */
3937 N, N, N, N, N, N, N, N,
3938 /* 0xF0 - 0xF7 */
3939 N, N, N, N, N, N, N, N,
3940 /* 0xF8 - 0xFF */
3941 N, N, N, N, N, N, N, N,
3942} };
3943
39f062ff
NA		 3944static const struct instr_dual instr_dual_0f_c3 = {
3945 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3946};
3947
fd0a0d82 3948static const struct opcode opcode_table[256] = {
73fba5f4 3949 /* 0x00 - 0x07 */
fb864fbc 3950 F6ALU(Lock, em_add),
1cd196ea
AK		 3951 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3952 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3953 /* 0x08 - 0x0F */
fb864fbc 3954 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3955 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3956 N,
73fba5f4 3957 /* 0x10 - 0x17 */
fb864fbc 3958 F6ALU(Lock, em_adc),
1cd196ea
AK		 3959 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3960 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3961 /* 0x18 - 0x1F */
fb864fbc 3962 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3963 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3964 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3965 /* 0x20 - 0x27 */
fb864fbc 3966 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3967 /* 0x28 - 0x2F */
fb864fbc 3968 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3969 /* 0x30 - 0x37 */
fb864fbc 3970 F6ALU(Lock, em_xor), N, N,
73fba5f4 3971 /* 0x38 - 0x3F */
fb864fbc 3972 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3973 /* 0x40 - 0x4F */
95413dc4 3974 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3975 /* 0x50 - 0x57 */
63540382 3976 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3977 /* 0x58 - 0x5F */
c54fe504 3978 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3979 /* 0x60 - 0x67 */
b96a7fad
TY		 3980 I(ImplicitOps | Stack | No64, em_pusha),
3981 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3982 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3983 N, N, N, N,
3984 /* 0x68 - 0x6F */
d46164db
AK		 3985 I(SrcImm | Mov | Stack, em_push),
3986 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3987 I(SrcImmByte | Mov | Stack, em_push),
3988 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3989 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3990 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3991 /* 0x70 - 0x7F */
58b7075d 3992 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3993 /* 0x80 - 0x87 */
1c2545be
TY		 3994 G(ByteOp | DstMem | SrcImm, group1),
3995 G(DstMem | SrcImm, group1),
3996 G(ByteOp | DstMem | SrcImm | No64, group1),
3997 G(DstMem | SrcImmByte, group1),
fb864fbc 3998 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3999 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4000 /* 0x88 - 0x8F */
d5ae7ce8 4001 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4002 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4003 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4004 D(ModRM | SrcMem | NoAccess | DstReg),
4005 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4006 G(0, group1A),
73fba5f4 4007 /* 0x90 - 0x97 */
bf608f88 4008 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4009 /* 0x98 - 0x9F */
61429142 4010 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4011 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4012 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4013 II(ImplicitOps | Stack, em_popf, popf),
4014 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4015 /* 0xA0 - 0xA7 */
b9eac5f4 4016 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4017 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4018 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4019 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4020 /* 0xA8 - 0xAF */
fb864fbc 4021 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4022 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4023 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4024 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4025 /* 0xB0 - 0xB7 */
b9eac5f4 4026 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4027 /* 0xB8 - 0xBF */
5e2c6883 4028 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4029 /* 0xC0 - 0xC7 */
007a3b54 4030 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4031 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4032 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4033 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4034 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4035 G(ByteOp, group11), G(0, group11),
73fba5f4 4036 /* 0xC8 - 0xCF */
612e89f0 4037 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4038 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4039 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4040 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4041 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4042 /* 0xD0 - 0xD7 */
007a3b54
AK		 4043 G(Src2One | ByteOp, group2), G(Src2One, group2),
4044 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4045 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4046 I(DstAcc | SrcImmUByte | No64, em_aad),
4047 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4048 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4049 /* 0xD8 - 0xDF */
045a282c 4050 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4051 /* 0xE0 - 0xE7 */
58b7075d
NA		 4052 X3(I(SrcImmByte | NearBranch, em_loop)),
4053 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4054 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4055 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4056 /* 0xE8 - 0xEF */
58b7075d
NA		 4057 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4058 I(SrcImmFAddr | No64, em_jmp_far),
4059 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4060 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4061 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4062 /* 0xF0 - 0xF7 */
bf608f88 4063 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4064 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4065 G(ByteOp, group3), G(0, group3),
73fba5f4 4066 /* 0xF8 - 0xFF */
f411e6cd
TY		 4067 D(ImplicitOps), D(ImplicitOps),
4068 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4069 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4070};
4071
fd0a0d82 4072static const struct opcode twobyte_table[256] = {
73fba5f4 4073 /* 0x00 - 0x0F */
dee6bb70 4074 G(0, group6), GD(0, &group7), N, N,
b51e974f 4075 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4076 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4077 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4078 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4079 /* 0x10 - 0x1F */
103f98ea 4080 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4081 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4082 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4083 /* 0x20 - 0x2F */
9b88ae99
NA		 4084 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4085 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4086 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4087 check_cr_write),
4088 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4089 check_dr_write),
73fba5f4 4090 N, N, N, N,
27ce8258
IM		 4091 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4092 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4093 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4094 N, N, N, N,
73fba5f4 4095 /* 0x30 - 0x3F */
e1e210b0 4096 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4097 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4098 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4099 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4100 I(ImplicitOps | EmulateOnUD, em_sysenter),
4101 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4102 N, N,
73fba5f4
AK		 4103 N, N, N, N, N, N, N, N,
4104 /* 0x40 - 0x4F */
140bad89 4105 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4106 /* 0x50 - 0x5F */
4107 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4108 /* 0x60 - 0x6F */
aa97bb48
AK		 4109 N, N, N, N,
4110 N, N, N, N,
4111 N, N, N, N,
4112 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4113 /* 0x70 - 0x7F */
aa97bb48
AK		 4114 N, N, N, N,
4115 N, N, N, N,
4116 N, N, N, N,
4117 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4118 /* 0x80 - 0x8F */
58b7075d 4119 X16(D(SrcImm | NearBranch)),
73fba5f4 4120 /* 0x90 - 0x9F */
ee45b58e 4121 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4122 /* 0xA0 - 0xA7 */
1cd196ea 4123 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4124 II(ImplicitOps, em_cpuid, cpuid),
4125 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4126 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4127 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4128 /* 0xA8 - 0xAF */
1cd196ea 4129 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4130 DI(ImplicitOps, rsm),
11c363ba 4131 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4132 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4133 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4134 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4135 /* 0xB0 - 0xB7 */
e940b5c2 4136 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4137 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4138 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4139 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4140 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4141 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4142 /* 0xB8 - 0xBF */
4143 N, N,
ce7faab2 4144 G(BitOp, group8),
11c363ba
AK		 4145 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4146 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4147 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4148 /* 0xC0 - 0xC7 */
e47a5f5f 4149 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4150 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4151 N, N, N, GD(0, &group9),
9299836e
AK		 4152 /* 0xC8 - 0xCF */
4153 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4154 /* 0xD0 - 0xDF */
4155 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4156 /* 0xE0 - 0xEF */
0a37027e
AW		 4157 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4158 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4159 /* 0xF0 - 0xFF */
4160 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4161};
4162
39f062ff
NA		 4163static const struct instr_dual instr_dual_0f_38_f0 = {
4164 I(DstReg | SrcMem | Mov, em_movbe), N
4165};
4166
4167static const struct instr_dual instr_dual_0f_38_f1 = {
4168 I(DstMem | SrcReg | Mov, em_movbe), N
4169};
4170
0bc5eedb 4171static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4172 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4173};
4174
4175static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4176 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4177};
4178
4179/*
4180 * Insns below are selected by the prefix which indexed by the third opcode
4181 * byte.
4182 */
4183static const struct opcode opcode_map_0f_38[256] = {
4184 /* 0x00 - 0x7f */
4185 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4186 /* 0x80 - 0xef */
4187 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4188 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4189 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4190 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4191 /* 0xf2 - 0xff */
4192 N, N, X4(N), X8(N)
0bc5eedb
BP		 4193};
4194
73fba5f4
AK		 4195#undef D
4196#undef N
4197#undef G
4198#undef GD
4199#undef I
aa97bb48 4200#undef GP
01de8b09 4201#undef EXT
73fba5f4 4202
8d8f4e9f 4203#undef D2bv
f6511935 4204#undef D2bvIP
8d8f4e9f 4205#undef I2bv
d7841a4b 4206#undef I2bvIP
d67fc27a 4207#undef I6ALU
8d8f4e9f 4208
9dac77fa 4209static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4210{
4211 unsigned size;
4212
9dac77fa 4213 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4214 if (size == 8)
4215 size = 4;
4216 return size;
4217}
4218
4219static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4220 unsigned size, bool sign_extension)
4221{
39f21ee5
AK		 4222 int rc = X86EMUL_CONTINUE;
4223
4224 op->type = OP_IMM;
4225 op->bytes = size;
9dac77fa 4226 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4227 /* NB. Immediates are sign-extended as necessary. */
4228 switch (op->bytes) {
4229 case 1:
e85a1085 4230 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4231 break;
4232 case 2:
e85a1085 4233 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4234 break;
4235 case 4:
e85a1085 4236 op->val = insn_fetch(s32, ctxt);
39f21ee5 4237 break;
5e2c6883
NA		 4238 case 8:
4239 op->val = insn_fetch(s64, ctxt);
4240 break;
39f21ee5
AK		 4241 }
4242 if (!sign_extension) {
4243 switch (op->bytes) {
4244 case 1:
4245 op->val &= 0xff;
4246 break;
4247 case 2:
4248 op->val &= 0xffff;
4249 break;
4250 case 4:
4251 op->val &= 0xffffffff;
4252 break;
4253 }
4254 }
4255done:
4256 return rc;
4257}
4258
a9945549
AK		 4259static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4260 unsigned d)
4261{
4262 int rc = X86EMUL_CONTINUE;
4263
4264 switch (d) {
4265 case OpReg:
2adb5ad9 4266 decode_register_operand(ctxt, op);
a9945549
AK		 4267 break;
4268 case OpImmUByte:
608aabe3 4269 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4270 break;
4271 case OpMem:
41ddf978 4272 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4273 mem_common:
4274 *op = ctxt->memop;
4275 ctxt->memopp = op;
96888977 4276 if (ctxt->d & BitOp)
a9945549
AK		 4277 fetch_bit_operand(ctxt);
4278 op->orig_val = op->val;
4279 break;
41ddf978 4280 case OpMem64:
aaa05f24 4281 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4282 goto mem_common;
a9945549
AK		 4283 case OpAcc:
4284 op->type = OP_REG;
4285 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4286 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4287 fetch_register_operand(op);
4288 op->orig_val = op->val;
4289 break;
820207c8
AK		 4290 case OpAccLo:
4291 op->type = OP_REG;
4292 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4293 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4294 fetch_register_operand(op);
4295 op->orig_val = op->val;
4296 break;
4297 case OpAccHi:
4298 if (ctxt->d & ByteOp) {
4299 op->type = OP_NONE;
4300 break;
4301 }
4302 op->type = OP_REG;
4303 op->bytes = ctxt->op_bytes;
4304 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4305 fetch_register_operand(op);
4306 op->orig_val = op->val;
4307 break;
a9945549
AK		 4308 case OpDI:
4309 op->type = OP_MEM;
4310 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4311 op->addr.mem.ea =
01485a22 4312 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4313 op->addr.mem.seg = VCPU_SREG_ES;
4314 op->val = 0;
b3356bf0 4315 op->count = 1;
a9945549
AK		 4316 break;
4317 case OpDX:
4318 op->type = OP_REG;
4319 op->bytes = 2;
dd856efa 4320 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4321 fetch_register_operand(op);
4322 break;
4dd6a57d 4323 case OpCL:
d29b9d7e 4324 op->type = OP_IMM;
4dd6a57d 4325 op->bytes = 1;
dd856efa 4326 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4327 break;
4328 case OpImmByte:
4329 rc = decode_imm(ctxt, op, 1, true);
4330 break;
4331 case OpOne:
d29b9d7e 4332 op->type = OP_IMM;
4dd6a57d
AK		 4333 op->bytes = 1;
4334 op->val = 1;
4335 break;
4336 case OpImm:
4337 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4338 break;
5e2c6883
NA		 4339 case OpImm64:
4340 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4341 break;
28867cee
AK		 4342 case OpMem8:
4343 ctxt->memop.bytes = 1;
660696d1 4344 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4345 ctxt->memop.addr.reg = decode_register(ctxt,
4346 ctxt->modrm_rm, true);
660696d1
GN		 4347 fetch_register_operand(&ctxt->memop);
4348 }
28867cee 4349 goto mem_common;
0fe59128
AK		 4350 case OpMem16:
4351 ctxt->memop.bytes = 2;
4352 goto mem_common;
4353 case OpMem32:
4354 ctxt->memop.bytes = 4;
4355 goto mem_common;
4356 case OpImmU16:
4357 rc = decode_imm(ctxt, op, 2, false);
4358 break;
4359 case OpImmU:
4360 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4361 break;
4362 case OpSI:
4363 op->type = OP_MEM;
4364 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4365 op->addr.mem.ea =
01485a22 4366 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4367 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4368 op->val = 0;
b3356bf0 4369 op->count = 1;
0fe59128 4370 break;
7fa57952
PB		 4371 case OpXLat:
4372 op->type = OP_MEM;
4373 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4374 op->addr.mem.ea =
01485a22 4375 address_mask(ctxt,
7fa57952
PB		 4376 reg_read(ctxt, VCPU_REGS_RBX) +
4377 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4378 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4379 op->val = 0;
4380 break;
0fe59128
AK		 4381 case OpImmFAddr:
4382 op->type = OP_IMM;
4383 op->addr.mem.ea = ctxt->_eip;
4384 op->bytes = ctxt->op_bytes + 2;
4385 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4386 break;
4387 case OpMemFAddr:
4388 ctxt->memop.bytes = ctxt->op_bytes + 2;
4389 goto mem_common;
c191a7a0 4390 case OpES:
d29b9d7e 4391 op->type = OP_IMM;
c191a7a0
AK		 4392 op->val = VCPU_SREG_ES;
4393 break;
4394 case OpCS:
d29b9d7e 4395 op->type = OP_IMM;
c191a7a0
AK		 4396 op->val = VCPU_SREG_CS;
4397 break;
4398 case OpSS:
d29b9d7e 4399 op->type = OP_IMM;
c191a7a0
AK		 4400 op->val = VCPU_SREG_SS;
4401 break;
4402 case OpDS:
d29b9d7e 4403 op->type = OP_IMM;
c191a7a0
AK		 4404 op->val = VCPU_SREG_DS;
4405 break;
4406 case OpFS:
d29b9d7e 4407 op->type = OP_IMM;
c191a7a0
AK		 4408 op->val = VCPU_SREG_FS;
4409 break;
4410 case OpGS:
d29b9d7e 4411 op->type = OP_IMM;
c191a7a0
AK		 4412 op->val = VCPU_SREG_GS;
4413 break;
a9945549
AK		 4414 case OpImplicit:
4415 /* Special instructions do their own operand decoding. */
4416 default:
4417 op->type = OP_NONE; /* Disable writeback. */
4418 break;
4419 }
4420
4421done:
4422 return rc;
4423}
4424
ef5d75cc 4425int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4426{
dde7e6d1
AK		 4427 int rc = X86EMUL_CONTINUE;
4428 int mode = ctxt->mode;
46561646 4429 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4430 bool op_prefix = false;
573e80fe 4431 bool has_seg_override = false;
46561646 4432 struct opcode opcode;
dde7e6d1 4433
f09ed83e
AK		 4434 ctxt->memop.type = OP_NONE;
4435 ctxt->memopp = NULL;
9dac77fa 4436 ctxt->_eip = ctxt->eip;
17052f16
PB		 4437 ctxt->fetch.ptr = ctxt->fetch.data;
4438 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4439 ctxt->opcode_len = 1;
dc25e89e 4440 if (insn_len > 0)
9dac77fa 4441 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4442 else {
9506d57d 4443 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4444 if (rc != X86EMUL_CONTINUE)
4445 return rc;
4446 }
dde7e6d1
AK		 4447
4448 switch (mode) {
4449 case X86EMUL_MODE_REAL:
4450 case X86EMUL_MODE_VM86:
4451 case X86EMUL_MODE_PROT16:
4452 def_op_bytes = def_ad_bytes = 2;
4453 break;
4454 case X86EMUL_MODE_PROT32:
4455 def_op_bytes = def_ad_bytes = 4;
4456 break;
4457#ifdef CONFIG_X86_64
4458 case X86EMUL_MODE_PROT64:
4459 def_op_bytes = 4;
4460 def_ad_bytes = 8;
4461 break;
4462#endif
4463 default:
1d2887e2 4464 return EMULATION_FAILED;
dde7e6d1
AK		 4465 }
4466
9dac77fa
AK		 4467 ctxt->op_bytes = def_op_bytes;
4468 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4469
4470 /* Legacy prefixes. */
4471 for (;;) {
e85a1085 4472 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4473 case 0x66: /* operand-size override */
0d7cdee8 4474 op_prefix = true;
dde7e6d1 4475 /* switch between 2/4 bytes */
9dac77fa 4476 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4477 break;
4478 case 0x67: /* address-size override */
4479 if (mode == X86EMUL_MODE_PROT64)
4480 /* switch between 4/8 bytes */
9dac77fa 4481 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4482 else
4483 /* switch between 2/4 bytes */
9dac77fa 4484 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4485 break;
4486 case 0x26: /* ES override */
4487 case 0x2e: /* CS override */
4488 case 0x36: /* SS override */
4489 case 0x3e: /* DS override */
573e80fe
BD		 4490 has_seg_override = true;
4491 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4492 break;
4493 case 0x64: /* FS override */
4494 case 0x65: /* GS override */
573e80fe
BD		 4495 has_seg_override = true;
4496 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4497 break;
4498 case 0x40 ... 0x4f: /* REX */
4499 if (mode != X86EMUL_MODE_PROT64)
4500 goto done_prefixes;
9dac77fa 4501 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4502 continue;
4503 case 0xf0: /* LOCK */
9dac77fa 4504 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4505 break;
4506 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4507 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4508 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4509 break;
4510 default:
4511 goto done_prefixes;
4512 }
4513
4514 /* Any legacy prefix after a REX prefix nullifies its effect. */
4515
9dac77fa 4516 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4517 }
4518
4519done_prefixes:
4520
4521 /* REX prefix. */
9dac77fa
AK		 4522 if (ctxt->rex_prefix & 8)
4523 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4524
4525 /* Opcode byte(s). */
9dac77fa 4526 opcode = opcode_table[ctxt->b];
d3ad6243 4527 /* Two-byte opcode? */
9dac77fa 4528 if (ctxt->b == 0x0f) {
1ce19dc1 4529 ctxt->opcode_len = 2;
e85a1085 4530 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4531 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4532
4533 /* 0F_38 opcode map */
4534 if (ctxt->b == 0x38) {
4535 ctxt->opcode_len = 3;
4536 ctxt->b = insn_fetch(u8, ctxt);
4537 opcode = opcode_map_0f_38[ctxt->b];
4538 }
dde7e6d1 4539 }
9dac77fa 4540 ctxt->d = opcode.flags;
dde7e6d1 4541
9f4260e7
TY		 4542 if (ctxt->d & ModRM)
4543 ctxt->modrm = insn_fetch(u8, ctxt);
4544
7fe864dc
NA		 4545 /* vex-prefix instructions are not implemented */
4546 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4547 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4548 ctxt->d = NotImpl;
4549 }
4550
9dac77fa
AK		 4551 while (ctxt->d & GroupMask) {
4552 switch (ctxt->d & GroupMask) {
46561646 4553 case Group:
9dac77fa 4554 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4555 opcode = opcode.u.group[goffset];
4556 break;
4557 case GroupDual:
9dac77fa
AK		 4558 goffset = (ctxt->modrm >> 3) & 7;
4559 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4560 opcode = opcode.u.gdual->mod3[goffset];
4561 else
4562 opcode = opcode.u.gdual->mod012[goffset];
4563 break;
4564 case RMExt:
9dac77fa 4565 goffset = ctxt->modrm & 7;
01de8b09 4566 opcode = opcode.u.group[goffset];
46561646
AK		 4567 break;
4568 case Prefix:
9dac77fa 4569 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4570 return EMULATION_FAILED;
9dac77fa 4571 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4572 switch (simd_prefix) {
4573 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4574 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4575 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4576 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4577 }
4578 break;
045a282c
GN		 4579 case Escape:
4580 if (ctxt->modrm > 0xbf)
4581 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4582 else
4583 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4584 break;
39f062ff
NA		 4585 case InstrDual:
4586 if ((ctxt->modrm >> 6) == 3)
4587 opcode = opcode.u.idual->mod3;
4588 else
4589 opcode = opcode.u.idual->mod012;
4590 break;
46561646 4591 default:
1d2887e2 4592 return EMULATION_FAILED;
0d7cdee8 4593 }
46561646 4594
b1ea50b2 4595 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4596 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4597 }
4598
e24186e0
PB		 4599 /* Unrecognised? */
4600 if (ctxt->d == 0)
4601 return EMULATION_FAILED;
4602
9dac77fa 4603 ctxt->execute = opcode.u.execute;
dde7e6d1 4604
3a6095a0
NA		 4605 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4606 return EMULATION_FAILED;
4607
d40a6898 4608 if (unlikely(ctxt->d &
ed9aad21
NA		 4609 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4610 No16))) {
d40a6898
PB		 4611 /*
4612 * These are copied unconditionally here, and checked unconditionally
4613 * in x86_emulate_insn.
4614 */
4615 ctxt->check_perm = opcode.check_perm;
4616 ctxt->intercept = opcode.intercept;
dde7e6d1 4617
d40a6898
PB		 4618 if (ctxt->d & NotImpl)
4619 return EMULATION_FAILED;
d867162c 4620
58b7075d
NA		 4621 if (mode == X86EMUL_MODE_PROT64) {
4622 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4623 ctxt->op_bytes = 8;
4624 else if (ctxt->d & NearBranch)
4625 ctxt->op_bytes = 8;
4626 }
7f9b4b75 4627
d40a6898
PB		 4628 if (ctxt->d & Op3264) {
4629 if (mode == X86EMUL_MODE_PROT64)
4630 ctxt->op_bytes = 8;
4631 else
4632 ctxt->op_bytes = 4;
4633 }
4634
ed9aad21
NA		 4635 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4636 ctxt->op_bytes = 4;
4637
d40a6898
PB		 4638 if (ctxt->d & Sse)
4639 ctxt->op_bytes = 16;
4640 else if (ctxt->d & Mmx)
4641 ctxt->op_bytes = 8;
4642 }
1253791d 4643
dde7e6d1 4644 /* ModRM and SIB bytes. */
9dac77fa 4645 if (ctxt->d & ModRM) {
f09ed83e 4646 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4647 if (!has_seg_override) {
4648 has_seg_override = true;
4649 ctxt->seg_override = ctxt->modrm_seg;
4650 }
9dac77fa 4651 } else if (ctxt->d & MemAbs)
f09ed83e 4652 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4653 if (rc != X86EMUL_CONTINUE)
4654 goto done;
4655
573e80fe
BD		 4656 if (!has_seg_override)
4657 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4658
573e80fe 4659 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4660
dde7e6d1
AK		 4661 /*
4662 * Decode and fetch the source operand: register, memory
4663 * or immediate.
4664 */
0fe59128 4665 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4666 if (rc != X86EMUL_CONTINUE)
4667 goto done;
4668
dde7e6d1
AK		 4669 /*
4670 * Decode and fetch the second source operand: register, memory
4671 * or immediate.
4672 */
4dd6a57d 4673 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4674 if (rc != X86EMUL_CONTINUE)
4675 goto done;
4676
dde7e6d1 4677 /* Decode and fetch the destination operand: register or memory. */
a9945549 4678 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4679
41061cdb 4680 if (ctxt->rip_relative)
1c1c35ae
NA		 4681 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4682 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4683
a430c916 4684done:
1d2887e2 4685 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4686}
4687
1cb3f3ae
XG		 4688bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4689{
4690 return ctxt->d & PageTable;
4691}
4692
3e2f65d5
GN		 4693static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4694{
3e2f65d5
GN		 4695 /* The second termination condition only applies for REPE
4696 * and REPNE. Test if the repeat string operation prefix is
4697 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4698 * corresponding termination condition according to:
4699 * - if REPE/REPZ and ZF = 0 then done
4700 * - if REPNE/REPNZ and ZF = 1 then done
4701 */
9dac77fa
AK		 4702 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4703 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4704 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4705 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4706 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4707 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4708 return true;
4709
4710 return false;
4711}
4712
cbe2c9d3
AK		 4713static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4714{
4715 bool fault = false;
4716
4717 ctxt->ops->get_fpu(ctxt);
4718 asm volatile("1: fwait \n\t"
4719 "2: \n\t"
4720 ".pushsection .fixup,\"ax\" \n\t"
4721 "3: \n\t"
4722 "movb $1, %[fault] \n\t"
4723 "jmp 2b \n\t"
4724 ".popsection \n\t"
4725 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4726 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4727 ctxt->ops->put_fpu(ctxt);
4728
4729 if (unlikely(fault))
4730 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4731
4732 return X86EMUL_CONTINUE;
4733}
4734
4735static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4736 struct operand *op)
4737{
4738 if (op->type == OP_MM)
4739 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4740}
4741
e28bbd44
AK		 4742static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4743{
4744 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4745 if (!(ctxt->d & ByteOp))
4746 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4747 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4748 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4749 [fastop]"+S"(fop)
4750 : "c"(ctxt->src2.val));
e28bbd44 4751 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4752 if (!fop) /* exception is returned in fop variable */
4753 return emulate_de(ctxt);
e28bbd44
AK		 4754 return X86EMUL_CONTINUE;
4755}
dd856efa 4756
1498507a
BD		 4757void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4758{
573e80fe
BD		 4759 memset(&ctxt->rip_relative, 0,
4760 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4761
1498507a
BD		 4762 ctxt->io_read.pos = 0;
4763 ctxt->io_read.end = 0;
1498507a
BD		 4764 ctxt->mem_read.end = 0;
4765}
4766
7b105ca2 4767int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4768{
0225fb50 4769 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4770 int rc = X86EMUL_CONTINUE;
9dac77fa 4771 int saved_dst_type = ctxt->dst.type;
8b4caf66 4772
9dac77fa 4773 ctxt->mem_read.pos = 0;
310b5d30 4774
e24186e0
PB		 4775 /* LOCK prefix is allowed only with some instructions */
4776 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4777 rc = emulate_ud(ctxt);
1161624f
GN		 4778 goto done;
4779 }
4780
e24186e0 4781 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4782 rc = emulate_ud(ctxt);
d380a5e4
GN		 4783 goto done;
4784 }
4785
d40a6898
PB		 4786 if (unlikely(ctxt->d &
4787 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4788 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4789 (ctxt->d & Undefined)) {
4790 rc = emulate_ud(ctxt);
4791 goto done;
4792 }
1253791d 4793
d40a6898
PB		 4794 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4795 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4796 rc = emulate_ud(ctxt);
cbe2c9d3 4797 goto done;
d40a6898 4798 }
cbe2c9d3 4799
d40a6898
PB		 4800 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4801 rc = emulate_nm(ctxt);
c4f035c6 4802 goto done;
d40a6898 4803 }
c4f035c6 4804
d40a6898
PB		 4805 if (ctxt->d & Mmx) {
4806 rc = flush_pending_x87_faults(ctxt);
4807 if (rc != X86EMUL_CONTINUE)
4808 goto done;
4809 /*
4810 * Now that we know the fpu is exception safe, we can fetch
4811 * operands from it.
4812 */
4813 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4814 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4815 if (!(ctxt->d & Mov))
4816 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4817 }
e92805ac 4818
685bbf4a 4819 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4820 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4821 X86_ICPT_PRE_EXCEPT);
4822 if (rc != X86EMUL_CONTINUE)
4823 goto done;
4824 }
8ea7d6ae 4825
64a38292
NA		 4826 /* Instruction can only be executed in protected mode */
4827 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4828 rc = emulate_ud(ctxt);
4829 goto done;
4830 }
4831
d40a6898
PB		 4832 /* Privileged instruction can be executed only in CPL=0 */
4833 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4834 if (ctxt->d & PrivUD)
4835 rc = emulate_ud(ctxt);
4836 else
4837 rc = emulate_gp(ctxt, 0);
d09beabd 4838 goto done;
d40a6898 4839 }
d09beabd 4840
d40a6898 4841 /* Do instruction specific permission checks */
685bbf4a 4842 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4843 rc = ctxt->check_perm(ctxt);
4844 if (rc != X86EMUL_CONTINUE)
4845 goto done;
4846 }
4847
685bbf4a 4848 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4849 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4850 X86_ICPT_POST_EXCEPT);
4851 if (rc != X86EMUL_CONTINUE)
4852 goto done;
4853 }
4854
4855 if (ctxt->rep_prefix && (ctxt->d & String)) {
4856 /* All REP prefixes have the same first termination condition */
4857 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4858 ctxt->eip = ctxt->_eip;
4467c3f1 4859 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4860 goto done;
4861 }
b9fa9d6b 4862 }
b9fa9d6b
AK		 4863 }
4864
9dac77fa
AK		 4865 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4866 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4867 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4868 if (rc != X86EMUL_CONTINUE)
8b4caf66 4869 goto done;
9dac77fa 4870 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4871 }
4872
9dac77fa
AK		 4873 if (ctxt->src2.type == OP_MEM) {
4874 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4875 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4876 if (rc != X86EMUL_CONTINUE)
4877 goto done;
4878 }
4879
9dac77fa 4880 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4881 goto special_insn;
4882
4883
9dac77fa 4884 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4885 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4886 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4887 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4888 if (rc != X86EMUL_CONTINUE)
4889 goto done;
038e51de 4890 }
9dac77fa 4891 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4892
018a98db
AK		 4893special_insn:
4894
685bbf4a 4895 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4896 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4897 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4898 if (rc != X86EMUL_CONTINUE)
4899 goto done;
4900 }
4901
b9a1ecb9
NA		 4902 if (ctxt->rep_prefix && (ctxt->d & String))
4903 ctxt->eflags |= EFLG_RF;
4904 else
4905 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4906
9dac77fa 4907 if (ctxt->execute) {
e28bbd44
AK		 4908 if (ctxt->d & Fastop) {
4909 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4910 rc = fastop(ctxt, fop);
4911 if (rc != X86EMUL_CONTINUE)
4912 goto done;
4913 goto writeback;
4914 }
9dac77fa 4915 rc = ctxt->execute(ctxt);
ef65c889
AK		 4916 if (rc != X86EMUL_CONTINUE)
4917 goto done;
4918 goto writeback;
4919 }
4920
1ce19dc1 4921 if (ctxt->opcode_len == 2)
6aa8b732 4922 goto twobyte_insn;
0bc5eedb
BP		 4923 else if (ctxt->opcode_len == 3)
4924 goto threebyte_insn;
6aa8b732 4925
9dac77fa 4926 switch (ctxt->b) {
6aa8b732 4927 case 0x63: /* movsxd */
8b4caf66 4928 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4929 goto cannot_emulate;
9dac77fa 4930 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4931 break;
b2833e3c 4932 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4933 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4934 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4935 break;
7e0b54b1 4936 case 0x8d: /* lea r16/r32, m */
9dac77fa 4937 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4938 break;
3d9e77df 4939 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4940 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4941 ctxt->dst.type = OP_NONE;
4942 else
4943 rc = em_xchg(ctxt);
e4f973ae 4944 break;
e8b6fa70 4945 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4946 switch (ctxt->op_bytes) {
4947 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4948 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4949 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4950 }
4951 break;
6e154e56 4952 case 0xcc: /* int3 */
5c5df76b
TY		 4953 rc = emulate_int(ctxt, 3);
4954 break;
6e154e56 4955 case 0xcd: /* int n */
9dac77fa 4956 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4957 break;
4958 case 0xce: /* into */
5c5df76b
TY		 4959 if (ctxt->eflags & EFLG_OF)
4960 rc = emulate_int(ctxt, 4);
6e154e56 4961 break;
1a52e051 4962 case 0xe9: /* jmp rel */
db5b0762 4963 case 0xeb: /* jmp rel short */
234f3ce4 4964 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4965 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4966 break;
111de5d6 4967 case 0xf4: /* hlt */
6c3287f7 4968 ctxt->ops->halt(ctxt);
19fdfa0d 4969 break;
111de5d6
AK		 4970 case 0xf5: /* cmc */
4971 /* complement carry flag from eflags reg */
4972 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4973 break;
4974 case 0xf8: /* clc */
4975 ctxt->eflags &= ~EFLG_CF;
111de5d6 4976 break;
8744aa9a
MG		 4977 case 0xf9: /* stc */
4978 ctxt->eflags |= EFLG_CF;
4979 break;
fb4616f4
MG		 4980 case 0xfc: /* cld */
4981 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4982 break;
4983 case 0xfd: /* std */
4984 ctxt->eflags |= EFLG_DF;
fb4616f4 4985 break;
91269b8f
AK		 4986 default:
4987 goto cannot_emulate;
6aa8b732 4988 }
018a98db 4989
7d9ddaed
AK		 4990 if (rc != X86EMUL_CONTINUE)
4991 goto done;
4992
018a98db 4993writeback:
fb32b1ed
AK		 4994 if (ctxt->d & SrcWrite) {
4995 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4996 rc = writeback(ctxt, &ctxt->src);
4997 if (rc != X86EMUL_CONTINUE)
4998 goto done;
4999 }
ee212297
NA		 5000 if (!(ctxt->d & NoWrite)) {
5001 rc = writeback(ctxt, &ctxt->dst);
5002 if (rc != X86EMUL_CONTINUE)
5003 goto done;
5004 }
018a98db 5005
5cd21917
GN		 5006 /*
5007 * restore dst type in case the decoding will be reused
5008 * (happens for string instruction )
5009 */
9dac77fa 5010 ctxt->dst.type = saved_dst_type;
5cd21917 5011
9dac77fa 5012 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5013 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5014
9dac77fa 5015 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5016 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5017
9dac77fa 5018 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5019 unsigned int count;
9dac77fa 5020 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5021 if ((ctxt->d & SrcMask) == SrcSI)
5022 count = ctxt->src.count;
5023 else
5024 count = ctxt->dst.count;
01485a22 5025 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5026
d2ddd1c4
GN		 5027 if (!string_insn_completed(ctxt)) {
5028 /*
5029 * Re-enter guest when pio read ahead buffer is empty
5030 * or, if it is not used, after each 1024 iteration.
5031 */
dd856efa 5032 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5033 (r->end == 0 || r->end != r->pos)) {
5034 /*
5035 * Reset read cache. Usually happens before
5036 * decode, but since instruction is restarted
5037 * we have to do it here.
5038 */
9dac77fa 5039 ctxt->mem_read.end = 0;
dd856efa 5040 writeback_registers(ctxt);
d2ddd1c4
GN		 5041 return EMULATION_RESTART;
5042 }
5043 goto done; /* skip rip writeback */
0fa6ccbd 5044 }
b9a1ecb9 5045 ctxt->eflags &= ~EFLG_RF;
5cd21917 5046 }
d2ddd1c4 5047
9dac77fa 5048 ctxt->eip = ctxt->_eip;
018a98db
AK		 5049
5050done:
e0ad0b47
PB		 5051 if (rc == X86EMUL_PROPAGATE_FAULT) {
5052 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5053 ctxt->have_exception = true;
e0ad0b47 5054 }
775fde86
JR		 5055 if (rc == X86EMUL_INTERCEPTED)
5056 return EMULATION_INTERCEPTED;
5057
dd856efa
AK		 5058 if (rc == X86EMUL_CONTINUE)
5059 writeback_registers(ctxt);
5060
d2ddd1c4 5061 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5062
5063twobyte_insn:
9dac77fa 5064 switch (ctxt->b) {
018a98db 5065 case 0x09: /* wbinvd */
cfb22375 5066 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5067 break;
5068 case 0x08: /* invd */
018a98db
AK		 5069 case 0x0d: /* GrpP (prefetch) */
5070 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5071 case 0x1f: /* nop */
018a98db
AK		 5072 break;
5073 case 0x20: /* mov cr, reg */
9dac77fa 5074 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5075 break;
6aa8b732 5076 case 0x21: /* mov from dr to reg */
9dac77fa 5077 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5078 break;
6aa8b732 5079 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5080 if (test_cc(ctxt->b, ctxt->eflags))
5081 ctxt->dst.val = ctxt->src.val;
5082 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5083 ctxt->op_bytes != 4)
9dac77fa 5084 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5085 break;
b2833e3c 5086 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5087 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5088 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5089 break;
ee45b58e 5090 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5091 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5092 break;
6aa8b732 5093 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5094 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5095 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5096 : (u16) ctxt->src.val;
6aa8b732 5097 break;
6aa8b732 5098 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5099 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5100 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5101 (s16) ctxt->src.val;
6aa8b732 5102 break;
91269b8f
AK		 5103 default:
5104 goto cannot_emulate;
6aa8b732 5105 }
7d9ddaed 5106
0bc5eedb
BP		 5107threebyte_insn:
5108
7d9ddaed
AK		 5109 if (rc != X86EMUL_CONTINUE)
5110 goto done;
5111
6aa8b732
AK		 5112 goto writeback;
5113
5114cannot_emulate:
a0c0ab2f 5115 return EMULATION_FAILED;
6aa8b732 5116}
dd856efa
AK		 5117
5118void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5119{
5120 invalidate_registers(ctxt);
5121}
5122
5123void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5124{
5125 writeback_registers(ctxt);
5126}
Linux kernel - Deliverables
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