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KVM: x86 emulator: Remove unused arg from writeback()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
46561646 76#define GroupMask (7<<14) /* Opcode uses one of the group mechanisms */
e09d082c 77#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
46561646
AK		 78#define GroupDual (2<<14) /* Alternate decoding of mod == 3 */
79#define Prefix (3<<14) /* Instruction varies with 66/f2/f3 prefix */
80#define RMExt (4<<14) /* Opcode extension in ModRM r/m if mod == 3 */
1253791d 81#define Sse (1<<17) /* SSE Vector instruction */
d8769fed 82/* Misc flags */
8ea7d6ae 83#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 84#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 85#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 86#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
7db41eb7 96#define Src2Imm (4<<29)
0dc8d10f 97#define Src2Mask (7<<29)
6aa8b732 98
d0e53325
AK		 99#define X2(x...) x, x
100#define X3(x...) X2(x), x
101#define X4(x...) X2(x), X2(x)
102#define X5(x...) X4(x), x
103#define X6(x...) X4(x), X2(x)
104#define X7(x...) X4(x), X3(x)
105#define X8(x...) X4(x), X4(x)
106#define X16(x...) X8(x), X8(x)
83babbca 107
d65b1dee
AK		 108struct opcode {
109 u32 flags;
c4f035c6 110 u8 intercept;
120df890 111 union {
ef65c889 112 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 113 struct opcode *group;
114 struct group_dual *gdual;
0d7cdee8 115 struct gprefix *gprefix;
120df890 116 } u;
d09beabd 117 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 118};
119
120struct group_dual {
121 struct opcode mod012[8];
122 struct opcode mod3[8];
d65b1dee
AK		 123};
124
0d7cdee8
AK		 125struct gprefix {
126 struct opcode pfx_no;
127 struct opcode pfx_66;
128 struct opcode pfx_f2;
129 struct opcode pfx_f3;
130};
131
6aa8b732 132/* EFLAGS bit definitions. */
d4c6a154
GN		 133#define EFLG_ID (1<<21)
134#define EFLG_VIP (1<<20)
135#define EFLG_VIF (1<<19)
136#define EFLG_AC (1<<18)
b1d86143
AP		 137#define EFLG_VM (1<<17)
138#define EFLG_RF (1<<16)
d4c6a154
GN		 139#define EFLG_IOPL (3<<12)
140#define EFLG_NT (1<<14)
6aa8b732
AK		 141#define EFLG_OF (1<<11)
142#define EFLG_DF (1<<10)
b1d86143 143#define EFLG_IF (1<<9)
d4c6a154 144#define EFLG_TF (1<<8)
6aa8b732
AK		 145#define EFLG_SF (1<<7)
146#define EFLG_ZF (1<<6)
147#define EFLG_AF (1<<4)
148#define EFLG_PF (1<<2)
149#define EFLG_CF (1<<0)
150
62bd430e
MG		 151#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
152#define EFLG_RESERVED_ONE_MASK 2
153
6aa8b732
AK		 154/*
155 * Instruction emulation:
156 * Most instructions are emulated directly via a fragment of inline assembly
157 * code. This allows us to save/restore EFLAGS and thus very easily pick up
158 * any modified flags.
159 */
160
05b3e0c2 161#if defined(CONFIG_X86_64)
6aa8b732
AK		 162#define _LO32 "k" /* force 32-bit operand */
163#define _STK "%%rsp" /* stack pointer */
164#elif defined(__i386__)
165#define _LO32 "" /* force 32-bit operand */
166#define _STK "%%esp" /* stack pointer */
167#endif
168
169/*
170 * These EFLAGS bits are restored from saved value during emulation, and
171 * any changes are written back to the saved value after emulation.
172 */
173#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
174
175/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 176#define _PRE_EFLAGS(_sav, _msk, _tmp) \
177 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
178 "movl %"_sav",%"_LO32 _tmp"; " \
179 "push %"_tmp"; " \
180 "push %"_tmp"; " \
181 "movl %"_msk",%"_LO32 _tmp"; " \
182 "andl %"_LO32 _tmp",("_STK"); " \
183 "pushf; " \
184 "notl %"_LO32 _tmp"; " \
185 "andl %"_LO32 _tmp",("_STK"); " \
186 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
187 "pop %"_tmp"; " \
188 "orl %"_LO32 _tmp",("_STK"); " \
189 "popf; " \
190 "pop %"_sav"; "
6aa8b732
AK		 191
192/* After executing instruction: write-back necessary bits in EFLAGS. */
193#define _POST_EFLAGS(_sav, _msk, _tmp) \
194 /* _sav |= EFLAGS & _msk; */ \
195 "pushf; " \
196 "pop %"_tmp"; " \
197 "andl %"_msk",%"_LO32 _tmp"; " \
198 "orl %"_LO32 _tmp",%"_sav"; "
199
dda96d8f
AK		 200#ifdef CONFIG_X86_64
201#define ON64(x) x
202#else
203#define ON64(x)
204#endif
205
b3b3d25a 206#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 207 do { \
208 __asm__ __volatile__ ( \
209 _PRE_EFLAGS("0", "4", "2") \
210 _op _suffix " %"_x"3,%1; " \
211 _POST_EFLAGS("0", "4", "2") \
fb2c2641 212 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 213 "=&r" (_tmp) \
214 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 215 } while (0)
6b7ad61f
AK		 216
217
6aa8b732
AK		 218/* Raw emulation: instruction has two explicit operands. */
219#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 220 do { \
221 unsigned long _tmp; \
222 \
223 switch ((_dst).bytes) { \
224 case 2: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 226 break; \
227 case 4: \
b3b3d25a 228 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 229 break; \
230 case 8: \
b3b3d25a 231 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 232 break; \
233 } \
6aa8b732
AK		 234 } while (0)
235
236#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
237 do { \
6b7ad61f 238 unsigned long _tmp; \
d77c26fc 239 switch ((_dst).bytes) { \
6aa8b732 240 case 1: \
b3b3d25a 241 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 242 break; \
243 default: \
244 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
245 _wx, _wy, _lx, _ly, _qx, _qy); \
246 break; \
247 } \
248 } while (0)
249
250/* Source operand is byte-sized and may be restricted to just %cl. */
251#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
252 __emulate_2op(_op, _src, _dst, _eflags, \
253 "b", "c", "b", "c", "b", "c", "b", "c")
254
255/* Source operand is byte, word, long or quad sized. */
256#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
257 __emulate_2op(_op, _src, _dst, _eflags, \
258 "b", "q", "w", "r", _LO32, "r", "", "r")
259
260/* Source operand is word, long or quad sized. */
261#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
262 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
263 "w", "r", _LO32, "r", "", "r")
264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 266#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
267 do { \
268 unsigned long _tmp; \
269 _type _clv = (_cl).val; \
270 _type _srcv = (_src).val; \
271 _type _dstv = (_dst).val; \
272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
277 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
281 (_cl).val = (unsigned long) _clv; \
282 (_src).val = (unsigned long) _srcv; \
283 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
7295261c
AK		 286#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
287 do { \
288 switch ((_dst).bytes) { \
289 case 2: \
290 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "w", unsigned short); \
292 break; \
293 case 4: \
294 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
295 "l", unsigned int); \
296 break; \
297 case 8: \
298 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
299 "q", unsigned long)); \
300 break; \
301 } \
d175226a
GT		 302 } while (0)
303
dda96d8f 304#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 305 do { \
306 unsigned long _tmp; \
307 \
dda96d8f
AK		 308 __asm__ __volatile__ ( \
309 _PRE_EFLAGS("0", "3", "2") \
310 _op _suffix " %1; " \
311 _POST_EFLAGS("0", "3", "2") \
312 : "=m" (_eflags), "+m" ((_dst).val), \
313 "=&r" (_tmp) \
314 : "i" (EFLAGS_MASK)); \
315 } while (0)
316
317/* Instruction has only one explicit operand (no source operand). */
318#define emulate_1op(_op, _dst, _eflags) \
319 do { \
d77c26fc 320 switch ((_dst).bytes) { \
dda96d8f
AK		 321 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
322 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
323 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
324 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 325 } \
326 } while (0)
327
3f9f53b0
MG		 328#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
329 do { \
330 unsigned long _tmp; \
331 \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "1") \
334 _op _suffix " %5; " \
335 _POST_EFLAGS("0", "4", "1") \
336 : "=m" (_eflags), "=&r" (_tmp), \
337 "+a" (_rax), "+d" (_rdx) \
338 : "i" (EFLAGS_MASK), "m" ((_src).val), \
339 "a" (_rax), "d" (_rdx)); \
340 } while (0)
341
f6b3597b
AK		 342#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
343 do { \
344 unsigned long _tmp; \
345 \
346 __asm__ __volatile__ ( \
347 _PRE_EFLAGS("0", "5", "1") \
348 "1: \n\t" \
349 _op _suffix " %6; " \
350 "2: \n\t" \
351 _POST_EFLAGS("0", "5", "1") \
352 ".pushsection .fixup,\"ax\" \n\t" \
353 "3: movb $1, %4 \n\t" \
354 "jmp 2b \n\t" \
355 ".popsection \n\t" \
356 _ASM_EXTABLE(1b, 3b) \
357 : "=m" (_eflags), "=&r" (_tmp), \
358 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
359 : "i" (EFLAGS_MASK), "m" ((_src).val), \
360 "a" (_rax), "d" (_rdx)); \
361 } while (0)
362
3f9f53b0 363/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 364#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
365 do { \
366 switch((_src).bytes) { \
367 case 1: \
368 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
369 _eflags, "b"); \
370 break; \
371 case 2: \
372 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
373 _eflags, "w"); \
374 break; \
375 case 4: \
376 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
377 _eflags, "l"); \
378 break; \
379 case 8: \
380 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
381 _eflags, "q")); \
382 break; \
3f9f53b0
MG		 383 } \
384 } while (0)
385
f6b3597b
AK		 386#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
387 do { \
388 switch((_src).bytes) { \
389 case 1: \
390 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
391 _eflags, "b", _ex); \
392 break; \
393 case 2: \
394 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
395 _eflags, "w", _ex); \
396 break; \
397 case 4: \
398 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
399 _eflags, "l", _ex); \
400 break; \
401 case 8: ON64( \
402 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
403 _eflags, "q", _ex)); \
404 break; \
405 } \
406 } while (0)
407
6aa8b732
AK		 408/* Fetch next part of the instruction being emulated. */
409#define insn_fetch(_type, _size, _eip) \
410({ unsigned long _x; \
62266869 411 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 412 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 413 goto done; \
414 (_eip) += (_size); \
415 (_type)_x; \
416})
417
7295261c 418#define insn_fetch_arr(_arr, _size, _eip) \
414e6277
GN		 419({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
420 if (rc != X86EMUL_CONTINUE) \
421 goto done; \
422 (_eip) += (_size); \
423})
424
8a76d7f2
JR		 425static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
426 enum x86_intercept intercept,
427 enum x86_intercept_stage stage)
428{
429 struct x86_instruction_info info = {
430 .intercept = intercept,
431 .rep_prefix = ctxt->decode.rep_prefix,
432 .modrm_mod = ctxt->decode.modrm_mod,
433 .modrm_reg = ctxt->decode.modrm_reg,
434 .modrm_rm = ctxt->decode.modrm_rm,
435 .src_val = ctxt->decode.src.val64,
436 .src_bytes = ctxt->decode.src.bytes,
437 .dst_bytes = ctxt->decode.dst.bytes,
438 .ad_bytes = ctxt->decode.ad_bytes,
439 .next_rip = ctxt->eip,
440 };
441
2953538e 442 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 443}
444
ddcb2885
HH		 445static inline unsigned long ad_mask(struct decode_cache *c)
446{
447 return (1UL << (c->ad_bytes << 3)) - 1;
448}
449
6aa8b732 450/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 451static inline unsigned long
452address_mask(struct decode_cache *c, unsigned long reg)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 return reg;
456 else
457 return reg & ad_mask(c);
458}
459
460static inline unsigned long
90de84f5 461register_address(struct decode_cache *c, unsigned long reg)
e4706772 462{
90de84f5 463 return address_mask(c, reg);
e4706772
HH		 464}
465
7a957275
HH		 466static inline void
467register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
468{
469 if (c->ad_bytes == sizeof(unsigned long))
470 *reg += inc;
471 else
472 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
473}
6aa8b732 474
7a957275
HH		 475static inline void jmp_rel(struct decode_cache *c, int rel)
476{
477 register_address_increment(c, &c->eip, rel);
478}
098c937b 479
56697687
AK		 480static u32 desc_limit_scaled(struct desc_struct *desc)
481{
482 u32 limit = get_desc_limit(desc);
483
484 return desc->g ? (limit << 12) | 0xfff : limit;
485}
486
7a5b56df
AK		 487static void set_seg_override(struct decode_cache *c, int seg)
488{
489 c->has_seg_override = true;
490 c->seg_override = seg;
491}
492
79168fd1
GN		 493static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
494 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 495{
496 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
497 return 0;
498
4bff1e86 499 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 500}
501
90de84f5 502static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
90de84f5 503 struct decode_cache *c)
7a5b56df
AK		 504{
505 if (!c->has_seg_override)
506 return 0;
507
90de84f5 508 return c->seg_override;
7a5b56df
AK		 509}
510
35d3d4a1
AK		 511static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
54b8486f 513{
da9cb575
AK		 514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
35d3d4a1 517 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 518}
519
3b88e41a
JR		 520static int emulate_db(struct x86_emulate_ctxt *ctxt)
521{
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523}
524
35d3d4a1 525static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 528}
529
618ff15d
AK		 530static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531{
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533}
534
35d3d4a1 535static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 536{
35d3d4a1 537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 538}
539
35d3d4a1 540static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 543}
544
34d1f490
AK		 545static int emulate_de(struct x86_emulate_ctxt *ctxt)
546{
35d3d4a1 547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 548}
549
1253791d
AK		 550static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553}
554
1aa36616
AK		 555static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
556{
557 u16 selector;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
561 return selector;
562}
563
564static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
565 unsigned seg)
566{
567 u16 dummy;
568 u32 base3;
569 struct desc_struct desc;
570
571 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
572 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
573}
574
3d9b938e 575static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 576 struct segmented_address addr,
3d9b938e 577 unsigned size, bool write, bool fetch,
52fd8b44
AK		 578 ulong *linear)
579{
580 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 581 struct desc_struct desc;
582 bool usable;
52fd8b44 583 ulong la;
618ff15d 584 u32 lim;
1aa36616 585 u16 sel;
618ff15d 586 unsigned cpl, rpl;
52fd8b44
AK		 587
588 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 589 switch (ctxt->mode) {
590 case X86EMUL_MODE_REAL:
591 break;
592 case X86EMUL_MODE_PROT64:
593 if (((signed long)la << 16) >> 16 != la)
594 return emulate_gp(ctxt, 0);
595 break;
596 default:
1aa36616
AK		 597 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
598 addr.seg);
618ff15d
AK		 599 if (!usable)
600 goto bad;
601 /* code segment or read-only data segment */
602 if (((desc.type & 8) || !(desc.type & 2)) && write)
603 goto bad;
604 /* unreadable code segment */
3d9b938e 605 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 606 goto bad;
607 lim = desc_limit_scaled(&desc);
608 if ((desc.type & 8) || !(desc.type & 4)) {
609 /* expand-up segment */
610 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
611 goto bad;
612 } else {
613 /* exapand-down segment */
614 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
615 goto bad;
616 lim = desc.d ? 0xffffffff : 0xffff;
617 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
618 goto bad;
619 }
717746e3 620 cpl = ctxt->ops->cpl(ctxt);
1aa36616 621 rpl = sel & 3;
618ff15d
AK		 622 cpl = max(cpl, rpl);
623 if (!(desc.type & 8)) {
624 /* data segment */
625 if (cpl > desc.dpl)
626 goto bad;
627 } else if ((desc.type & 8) && !(desc.type & 4)) {
628 /* nonconforming code segment */
629 if (cpl != desc.dpl)
630 goto bad;
631 } else if ((desc.type & 8) && (desc.type & 4)) {
632 /* conforming code segment */
633 if (cpl < desc.dpl)
634 goto bad;
635 }
636 break;
637 }
3d9b938e 638 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 639 la &= (u32)-1;
640 *linear = la;
641 return X86EMUL_CONTINUE;
618ff15d
AK		 642bad:
643 if (addr.seg == VCPU_SREG_SS)
644 return emulate_ss(ctxt, addr.seg);
645 else
646 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 647}
648
3d9b938e
NE		 649static int linearize(struct x86_emulate_ctxt *ctxt,
650 struct segmented_address addr,
651 unsigned size, bool write,
652 ulong *linear)
653{
654 return __linearize(ctxt, addr, size, write, false, linear);
655}
656
657
3ca3ac4d
AK		 658static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
659 struct segmented_address addr,
660 void *data,
661 unsigned size)
662{
9fa088f4
AK		 663 int rc;
664 ulong linear;
665
83b8795a 666 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 667 if (rc != X86EMUL_CONTINUE)
668 return rc;
0f65dd70 669 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 670}
671
62266869
AK		 672static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
2fb53ad8 674 unsigned long eip, u8 *dest)
62266869
AK		 675{
676 struct fetch_cache *fc = &ctxt->decode.fetch;
677 int rc;
2fb53ad8 678 int size, cur_size;
62266869 679
2fb53ad8 680 if (eip == fc->end) {
3d9b938e
NE		 681 unsigned long linear;
682 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 683 cur_size = fc->end - fc->start;
684 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 685 rc = __linearize(ctxt, addr, size, false, true, &linear);
686 if (rc != X86EMUL_CONTINUE)
687 return rc;
0f65dd70
AK		 688 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
689 size, &ctxt->exception);
3e2815e9 690 if (rc != X86EMUL_CONTINUE)
62266869 691 return rc;
2fb53ad8 692 fc->end += size;
62266869 693 }
2fb53ad8 694 *dest = fc->data[eip - fc->start];
3e2815e9 695 return X86EMUL_CONTINUE;
62266869
AK		 696}
697
698static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
699 struct x86_emulate_ops *ops,
700 unsigned long eip, void *dest, unsigned size)
701{
3e2815e9 702 int rc;
62266869 703
eb3c79e6 704 /* x86 instructions are limited to 15 bytes. */
063db061 705 if (eip + size - ctxt->eip > 15)
eb3c79e6 706 return X86EMUL_UNHANDLEABLE;
62266869
AK		 707 while (size--) {
708 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 709 if (rc != X86EMUL_CONTINUE)
62266869
AK		 710 return rc;
711 }
3e2815e9 712 return X86EMUL_CONTINUE;
62266869
AK		 713}
714
1e3c5cb0
RR		 715/*
716 * Given the 'reg' portion of a ModRM byte, and a register block, return a
717 * pointer into the block that addresses the relevant register.
718 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
719 */
720static void *decode_register(u8 modrm_reg, unsigned long *regs,
721 int highbyte_regs)
6aa8b732
AK		 722{
723 void *p;
724
725 p = &regs[modrm_reg];
726 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
727 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
728 return p;
729}
730
731static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 732 struct segmented_address addr,
6aa8b732
AK		 733 u16 *size, unsigned long *address, int op_bytes)
734{
735 int rc;
736
737 if (op_bytes == 2)
738 op_bytes = 3;
739 *address = 0;
3ca3ac4d 740 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 741 if (rc != X86EMUL_CONTINUE)
6aa8b732 742 return rc;
30b31ab6 743 addr.ea += 2;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 745 return rc;
746}
747
bbe9abbd
NK		 748static int test_cc(unsigned int condition, unsigned int flags)
749{
750 int rc = 0;
751
752 switch ((condition & 15) >> 1) {
753 case 0: /* o */
754 rc |= (flags & EFLG_OF);
755 break;
756 case 1: /* b/c/nae */
757 rc |= (flags & EFLG_CF);
758 break;
759 case 2: /* z/e */
760 rc |= (flags & EFLG_ZF);
761 break;
762 case 3: /* be/na */
763 rc |= (flags & (EFLG_CF|EFLG_ZF));
764 break;
765 case 4: /* s */
766 rc |= (flags & EFLG_SF);
767 break;
768 case 5: /* p/pe */
769 rc |= (flags & EFLG_PF);
770 break;
771 case 7: /* le/ng */
772 rc |= (flags & EFLG_ZF);
773 /* fall through */
774 case 6: /* l/nge */
775 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
776 break;
777 }
778
779 /* Odd condition identifiers (lsb == 1) have inverted sense. */
780 return (!!rc ^ (condition & 1));
781}
782
91ff3cb4
AK		 783static void fetch_register_operand(struct operand *op)
784{
785 switch (op->bytes) {
786 case 1:
787 op->val = *(u8 *)op->addr.reg;
788 break;
789 case 2:
790 op->val = *(u16 *)op->addr.reg;
791 break;
792 case 4:
793 op->val = *(u32 *)op->addr.reg;
794 break;
795 case 8:
796 op->val = *(u64 *)op->addr.reg;
797 break;
798 }
799}
800
1253791d
AK		 801static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
802{
803 ctxt->ops->get_fpu(ctxt);
804 switch (reg) {
805 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
806 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
807 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
808 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
809 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
810 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
811 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
812 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
813#ifdef CONFIG_X86_64
814 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
815 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
816 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
817 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
818 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
819 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
820 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
821 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
822#endif
823 default: BUG();
824 }
825 ctxt->ops->put_fpu(ctxt);
826}
827
828static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
829 int reg)
830{
831 ctxt->ops->get_fpu(ctxt);
832 switch (reg) {
833 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
834 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
835 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
836 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
837 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
838 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
839 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
840 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
841#ifdef CONFIG_X86_64
842 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
843 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
844 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
845 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
846 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
847 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
848 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
849 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
850#endif
851 default: BUG();
852 }
853 ctxt->ops->put_fpu(ctxt);
854}
855
856static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
857 struct operand *op,
3c118e24 858 struct decode_cache *c,
3c118e24
AK		 859 int inhibit_bytereg)
860{
33615aa9 861 unsigned reg = c->modrm_reg;
9f1ef3f8 862 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 863
864 if (!(c->d & ModRM))
865 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 866
867 if (c->d & Sse) {
868 op->type = OP_XMM;
869 op->bytes = 16;
870 op->addr.xmm = reg;
871 read_sse_reg(ctxt, &op->vec_val, reg);
872 return;
873 }
874
3c118e24
AK		 875 op->type = OP_REG;
876 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 877 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 878 op->bytes = 1;
879 } else {
1a6440ae 880 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 881 op->bytes = c->op_bytes;
3c118e24 882 }
91ff3cb4 883 fetch_register_operand(op);
3c118e24
AK		 884 op->orig_val = op->val;
885}
886
1c73ef66 887static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 888 struct x86_emulate_ops *ops,
889 struct operand *op)
1c73ef66
AK		 890{
891 struct decode_cache *c = &ctxt->decode;
892 u8 sib;
f5b4edcd 893 int index_reg = 0, base_reg = 0, scale;
3e2815e9 894 int rc = X86EMUL_CONTINUE;
2dbd0dd7 895 ulong modrm_ea = 0;
1c73ef66
AK		 896
897 if (c->rex_prefix) {
898 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
899 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
900 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
901 }
902
903 c->modrm = insn_fetch(u8, 1, c->eip);
904 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
905 c->modrm_reg |= (c->modrm & 0x38) >> 3;
906 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 907 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 908
909 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 910 op->type = OP_REG;
911 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
912 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 913 c->regs, c->d & ByteOp);
1253791d
AK		 914 if (c->d & Sse) {
915 op->type = OP_XMM;
916 op->bytes = 16;
917 op->addr.xmm = c->modrm_rm;
918 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
919 return rc;
920 }
2dbd0dd7 921 fetch_register_operand(op);
1c73ef66
AK		 922 return rc;
923 }
924
2dbd0dd7
AK		 925 op->type = OP_MEM;
926
1c73ef66
AK		 927 if (c->ad_bytes == 2) {
928 unsigned bx = c->regs[VCPU_REGS_RBX];
929 unsigned bp = c->regs[VCPU_REGS_RBP];
930 unsigned si = c->regs[VCPU_REGS_RSI];
931 unsigned di = c->regs[VCPU_REGS_RDI];
932
933 /* 16-bit ModR/M decode. */
934 switch (c->modrm_mod) {
935 case 0:
936 if (c->modrm_rm == 6)
2dbd0dd7 937 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 938 break;
939 case 1:
2dbd0dd7 940 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 941 break;
942 case 2:
2dbd0dd7 943 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 944 break;
945 }
946 switch (c->modrm_rm) {
947 case 0:
2dbd0dd7 948 modrm_ea += bx + si;
1c73ef66
AK		 949 break;
950 case 1:
2dbd0dd7 951 modrm_ea += bx + di;
1c73ef66
AK		 952 break;
953 case 2:
2dbd0dd7 954 modrm_ea += bp + si;
1c73ef66
AK		 955 break;
956 case 3:
2dbd0dd7 957 modrm_ea += bp + di;
1c73ef66
AK		 958 break;
959 case 4:
2dbd0dd7 960 modrm_ea += si;
1c73ef66
AK		 961 break;
962 case 5:
2dbd0dd7 963 modrm_ea += di;
1c73ef66
AK		 964 break;
965 case 6:
966 if (c->modrm_mod != 0)
2dbd0dd7 967 modrm_ea += bp;
1c73ef66
AK		 968 break;
969 case 7:
2dbd0dd7 970 modrm_ea += bx;
1c73ef66
AK		 971 break;
972 }
973 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
974 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 975 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 976 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 977 } else {
978 /* 32/64-bit ModR/M decode. */
84411d85 979 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 980 sib = insn_fetch(u8, 1, c->eip);
981 index_reg |= (sib >> 3) & 7;
982 base_reg |= sib & 7;
983 scale = sib >> 6;
984
dc71d0f1 985 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 986 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 987 else
2dbd0dd7 988 modrm_ea += c->regs[base_reg];
dc71d0f1 989 if (index_reg != 4)
2dbd0dd7 990 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 991 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
992 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 993 c->rip_relative = 1;
84411d85 994 } else
2dbd0dd7 995 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 996 switch (c->modrm_mod) {
997 case 0:
998 if (c->modrm_rm == 5)
2dbd0dd7 999 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1000 break;
1001 case 1:
2dbd0dd7 1002 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 1003 break;
1004 case 2:
2dbd0dd7 1005 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1006 break;
1007 }
1008 }
90de84f5 1009 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1010done:
1011 return rc;
1012}
1013
1014static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 1015 struct x86_emulate_ops *ops,
1016 struct operand *op)
1c73ef66
AK		 1017{
1018 struct decode_cache *c = &ctxt->decode;
3e2815e9 1019 int rc = X86EMUL_CONTINUE;
1c73ef66 1020
2dbd0dd7 1021 op->type = OP_MEM;
1c73ef66
AK		 1022 switch (c->ad_bytes) {
1023 case 2:
90de84f5 1024 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1025 break;
1026 case 4:
90de84f5 1027 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1028 break;
1029 case 8:
90de84f5 1030 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1031 break;
1032 }
1033done:
1034 return rc;
1035}
1036
35c843c4
WY		 1037static void fetch_bit_operand(struct decode_cache *c)
1038{
7129eeca 1039 long sv = 0, mask;
35c843c4 1040
3885f18f 1041 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1042 mask = ~(c->dst.bytes * 8 - 1);
1043
1044 if (c->src.bytes == 2)
1045 sv = (s16)c->src.val & (s16)mask;
1046 else if (c->src.bytes == 4)
1047 sv = (s32)c->src.val & (s32)mask;
1048
90de84f5 1049 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1050 }
ba7ff2b7
WY		 1051
1052 /* only subword offset */
1053 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1054}
1055
dde7e6d1
AK		 1056static int read_emulated(struct x86_emulate_ctxt *ctxt,
1057 struct x86_emulate_ops *ops,
1058 unsigned long addr, void *dest, unsigned size)
6aa8b732 1059{
dde7e6d1
AK		 1060 int rc;
1061 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1062
dde7e6d1
AK		 1063 while (size) {
1064 int n = min(size, 8u);
1065 size -= n;
1066 if (mc->pos < mc->end)
1067 goto read_cached;
5cd21917 1068
0f65dd70
AK		 1069 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1070 &ctxt->exception);
dde7e6d1
AK		 1071 if (rc != X86EMUL_CONTINUE)
1072 return rc;
1073 mc->end += n;
6aa8b732 1074
dde7e6d1
AK		 1075 read_cached:
1076 memcpy(dest, mc->data + mc->pos, n);
1077 mc->pos += n;
1078 dest += n;
1079 addr += n;
6aa8b732 1080 }
dde7e6d1
AK		 1081 return X86EMUL_CONTINUE;
1082}
6aa8b732 1083
3ca3ac4d
AK		 1084static int segmented_read(struct x86_emulate_ctxt *ctxt,
1085 struct segmented_address addr,
1086 void *data,
1087 unsigned size)
1088{
9fa088f4
AK		 1089 int rc;
1090 ulong linear;
1091
83b8795a 1092 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1093 if (rc != X86EMUL_CONTINUE)
1094 return rc;
1095 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1096}
1097
1098static int segmented_write(struct x86_emulate_ctxt *ctxt,
1099 struct segmented_address addr,
1100 const void *data,
1101 unsigned size)
1102{
9fa088f4
AK		 1103 int rc;
1104 ulong linear;
1105
83b8795a 1106 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1107 if (rc != X86EMUL_CONTINUE)
1108 return rc;
0f65dd70
AK		 1109 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1110 &ctxt->exception);
3ca3ac4d
AK		 1111}
1112
1113static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1114 struct segmented_address addr,
1115 const void *orig_data, const void *data,
1116 unsigned size)
1117{
9fa088f4
AK		 1118 int rc;
1119 ulong linear;
1120
83b8795a 1121 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1122 if (rc != X86EMUL_CONTINUE)
1123 return rc;
0f65dd70
AK		 1124 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1125 size, &ctxt->exception);
3ca3ac4d
AK		 1126}
1127
dde7e6d1
AK		 1128static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1129 struct x86_emulate_ops *ops,
1130 unsigned int size, unsigned short port,
1131 void *dest)
1132{
1133 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1134
dde7e6d1
AK		 1135 if (rc->pos == rc->end) { /* refill pio read ahead */
1136 struct decode_cache *c = &ctxt->decode;
1137 unsigned int in_page, n;
1138 unsigned int count = c->rep_prefix ?
1139 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1140 in_page = (ctxt->eflags & EFLG_DF) ?
1141 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1142 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1143 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1144 count);
1145 if (n == 0)
1146 n = 1;
1147 rc->pos = rc->end = 0;
ca1d4a9e 1148 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1149 return 0;
1150 rc->end = n * size;
6aa8b732
AK		 1151 }
1152
dde7e6d1
AK		 1153 memcpy(dest, rc->data + rc->pos, size);
1154 rc->pos += size;
1155 return 1;
1156}
6aa8b732 1157
dde7e6d1
AK		 1158static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1159 struct x86_emulate_ops *ops,
1160 u16 selector, struct desc_ptr *dt)
1161{
1162 if (selector & 1 << 2) {
1163 struct desc_struct desc;
1aa36616
AK		 1164 u16 sel;
1165
dde7e6d1 1166 memset (dt, 0, sizeof *dt);
1aa36616 1167 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1168 return;
e09d082c 1169
dde7e6d1
AK		 1170 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1171 dt->address = get_desc_base(&desc);
1172 } else
4bff1e86 1173 ops->get_gdt(ctxt, dt);
dde7e6d1 1174}
120df890 1175
dde7e6d1
AK		 1176/* allowed just for 8 bytes segments */
1177static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1178 struct x86_emulate_ops *ops,
1179 u16 selector, struct desc_struct *desc)
1180{
1181 struct desc_ptr dt;
1182 u16 index = selector >> 3;
1183 int ret;
dde7e6d1 1184 ulong addr;
120df890 1185
dde7e6d1 1186 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1187
35d3d4a1
AK		 1188 if (dt.size < index * 8 + 7)
1189 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1190 addr = dt.address + index * 8;
0f65dd70 1191 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1192
dde7e6d1
AK		 1193 return ret;
1194}
ef65c889 1195
dde7e6d1
AK		 1196/* allowed just for 8 bytes segments */
1197static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, struct desc_struct *desc)
1200{
1201 struct desc_ptr dt;
1202 u16 index = selector >> 3;
dde7e6d1
AK		 1203 ulong addr;
1204 int ret;
6aa8b732 1205
dde7e6d1 1206 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1207
35d3d4a1
AK		 1208 if (dt.size < index * 8 + 7)
1209 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1210
dde7e6d1 1211 addr = dt.address + index * 8;
0f65dd70 1212 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1213
dde7e6d1
AK		 1214 return ret;
1215}
c7e75a3d 1216
5601d05b 1217/* Does not support long mode */
dde7e6d1
AK		 1218static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1219 struct x86_emulate_ops *ops,
1220 u16 selector, int seg)
1221{
1222 struct desc_struct seg_desc;
1223 u8 dpl, rpl, cpl;
1224 unsigned err_vec = GP_VECTOR;
1225 u32 err_code = 0;
1226 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1227 int ret;
69f55cb1 1228
dde7e6d1 1229 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1230
dde7e6d1
AK		 1231 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1232 || ctxt->mode == X86EMUL_MODE_REAL) {
1233 /* set real mode segment descriptor */
1234 set_desc_base(&seg_desc, selector << 4);
1235 set_desc_limit(&seg_desc, 0xffff);
1236 seg_desc.type = 3;
1237 seg_desc.p = 1;
1238 seg_desc.s = 1;
1239 goto load;
1240 }
1241
1242 /* NULL selector is not valid for TR, CS and SS */
1243 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1244 && null_selector)
1245 goto exception;
1246
1247 /* TR should be in GDT only */
1248 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1249 goto exception;
1250
1251 if (null_selector) /* for NULL selector skip all following checks */
1252 goto load;
1253
1254 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1255 if (ret != X86EMUL_CONTINUE)
1256 return ret;
1257
1258 err_code = selector & 0xfffc;
1259 err_vec = GP_VECTOR;
1260
1261 /* can't load system descriptor into segment selecor */
1262 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1263 goto exception;
1264
1265 if (!seg_desc.p) {
1266 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1267 goto exception;
1268 }
1269
1270 rpl = selector & 3;
1271 dpl = seg_desc.dpl;
717746e3 1272 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1273
1274 switch (seg) {
1275 case VCPU_SREG_SS:
1276 /*
1277 * segment is not a writable data segment or segment
1278 * selector's RPL != CPL or segment selector's RPL != CPL
1279 */
1280 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1281 goto exception;
6aa8b732 1282 break;
dde7e6d1
AK		 1283 case VCPU_SREG_CS:
1284 if (!(seg_desc.type & 8))
1285 goto exception;
1286
1287 if (seg_desc.type & 4) {
1288 /* conforming */
1289 if (dpl > cpl)
1290 goto exception;
1291 } else {
1292 /* nonconforming */
1293 if (rpl > cpl || dpl != cpl)
1294 goto exception;
1295 }
1296 /* CS(RPL) <- CPL */
1297 selector = (selector & 0xfffc) | cpl;
6aa8b732 1298 break;
dde7e6d1
AK		 1299 case VCPU_SREG_TR:
1300 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1301 goto exception;
1302 break;
1303 case VCPU_SREG_LDTR:
1304 if (seg_desc.s || seg_desc.type != 2)
1305 goto exception;
1306 break;
1307 default: /* DS, ES, FS, or GS */
4e62417b 1308 /*
dde7e6d1
AK		 1309 * segment is not a data or readable code segment or
1310 * ((segment is a data or nonconforming code segment)
1311 * and (both RPL and CPL > DPL))
4e62417b 1312 */
dde7e6d1
AK		 1313 if ((seg_desc.type & 0xa) == 0x8 ||
1314 (((seg_desc.type & 0xc) != 0xc) &&
1315 (rpl > dpl && cpl > dpl)))
1316 goto exception;
6aa8b732 1317 break;
dde7e6d1
AK		 1318 }
1319
1320 if (seg_desc.s) {
1321 /* mark segment as accessed */
1322 seg_desc.type |= 1;
1323 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1324 if (ret != X86EMUL_CONTINUE)
1325 return ret;
1326 }
1327load:
1aa36616 1328 ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1329 return X86EMUL_CONTINUE;
1330exception:
1331 emulate_exception(ctxt, err_vec, err_code, true);
1332 return X86EMUL_PROPAGATE_FAULT;
1333}
1334
31be40b3
WY		 1335static void write_register_operand(struct operand *op)
1336{
1337 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1338 switch (op->bytes) {
1339 case 1:
1340 *(u8 *)op->addr.reg = (u8)op->val;
1341 break;
1342 case 2:
1343 *(u16 *)op->addr.reg = (u16)op->val;
1344 break;
1345 case 4:
1346 *op->addr.reg = (u32)op->val;
1347 break; /* 64b: zero-extend */
1348 case 8:
1349 *op->addr.reg = op->val;
1350 break;
1351 }
1352}
1353
adddcecf 1354static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1355{
1356 int rc;
1357 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1358
1359 switch (c->dst.type) {
1360 case OP_REG:
31be40b3 1361 write_register_operand(&c->dst);
6aa8b732 1362 break;
dde7e6d1
AK		 1363 case OP_MEM:
1364 if (c->lock_prefix)
3ca3ac4d
AK		 1365 rc = segmented_cmpxchg(ctxt,
1366 c->dst.addr.mem,
1367 &c->dst.orig_val,
1368 &c->dst.val,
1369 c->dst.bytes);
341de7e3 1370 else
3ca3ac4d
AK		 1371 rc = segmented_write(ctxt,
1372 c->dst.addr.mem,
1373 &c->dst.val,
1374 c->dst.bytes);
dde7e6d1
AK		 1375 if (rc != X86EMUL_CONTINUE)
1376 return rc;
a682e354 1377 break;
1253791d
AK		 1378 case OP_XMM:
1379 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1380 break;
dde7e6d1
AK		 1381 case OP_NONE:
1382 /* no writeback */
414e6277 1383 break;
dde7e6d1 1384 default:
414e6277 1385 break;
6aa8b732 1386 }
dde7e6d1
AK		 1387 return X86EMUL_CONTINUE;
1388}
6aa8b732 1389
4487b3b4 1390static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1391{
1392 struct decode_cache *c = &ctxt->decode;
4179bb02 1393 struct segmented_address addr;
0dc8d10f 1394
dde7e6d1 1395 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1396 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1397 addr.seg = VCPU_SREG_SS;
1398
1399 /* Disable writeback. */
1400 c->dst.type = OP_NONE;
1401 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1402}
69f55cb1 1403
dde7e6d1
AK		 1404static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1405 struct x86_emulate_ops *ops,
1406 void *dest, int len)
1407{
1408 struct decode_cache *c = &ctxt->decode;
1409 int rc;
90de84f5 1410 struct segmented_address addr;
8b4caf66 1411
90de84f5
AK		 1412 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1413 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1414 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1415 if (rc != X86EMUL_CONTINUE)
1416 return rc;
1417
1418 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1419 return rc;
8b4caf66
LV		 1420}
1421
c54fe504
TY		 1422static int em_pop(struct x86_emulate_ctxt *ctxt)
1423{
1424 struct decode_cache *c = &ctxt->decode;
1425
1426 return emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1427}
1428
dde7e6d1
AK		 1429static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1430 struct x86_emulate_ops *ops,
1431 void *dest, int len)
9de41573
GN		 1432{
1433 int rc;
dde7e6d1
AK		 1434 unsigned long val, change_mask;
1435 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1436 int cpl = ops->cpl(ctxt);
9de41573 1437
dde7e6d1
AK		 1438 rc = emulate_pop(ctxt, ops, &val, len);
1439 if (rc != X86EMUL_CONTINUE)
1440 return rc;
9de41573 1441
dde7e6d1
AK		 1442 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1443 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1444
dde7e6d1
AK		 1445 switch(ctxt->mode) {
1446 case X86EMUL_MODE_PROT64:
1447 case X86EMUL_MODE_PROT32:
1448 case X86EMUL_MODE_PROT16:
1449 if (cpl == 0)
1450 change_mask |= EFLG_IOPL;
1451 if (cpl <= iopl)
1452 change_mask |= EFLG_IF;
1453 break;
1454 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1455 if (iopl < 3)
1456 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1457 change_mask |= EFLG_IF;
1458 break;
1459 default: /* real mode */
1460 change_mask |= (EFLG_IOPL | EFLG_IF);
1461 break;
9de41573 1462 }
dde7e6d1
AK		 1463
1464 *(unsigned long *)dest =
1465 (ctxt->eflags & ~change_mask) | (val & change_mask);
1466
1467 return rc;
9de41573
GN		 1468}
1469
62aaa2f0
TY		 1470static int em_popf(struct x86_emulate_ctxt *ctxt)
1471{
1472 struct decode_cache *c = &ctxt->decode;
1473
1474 c->dst.type = OP_REG;
1475 c->dst.addr.reg = &ctxt->eflags;
1476 c->dst.bytes = c->op_bytes;
1477 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1478}
1479
4179bb02
TY		 1480static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1481 struct x86_emulate_ops *ops, int seg)
7b262e90 1482{
dde7e6d1 1483 struct decode_cache *c = &ctxt->decode;
7b262e90 1484
1aa36616 1485 c->src.val = get_segment_selector(ctxt, seg);
7b262e90 1486
4487b3b4 1487 return em_push(ctxt);
7b262e90
GN		 1488}
1489
dde7e6d1
AK		 1490static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1491 struct x86_emulate_ops *ops, int seg)
38ba30ba 1492{
dde7e6d1
AK		 1493 struct decode_cache *c = &ctxt->decode;
1494 unsigned long selector;
1495 int rc;
38ba30ba 1496
dde7e6d1
AK		 1497 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1498 if (rc != X86EMUL_CONTINUE)
1499 return rc;
1500
1501 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1502 return rc;
38ba30ba
GN		 1503}
1504
b96a7fad 1505static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1506{
dde7e6d1
AK		 1507 struct decode_cache *c = &ctxt->decode;
1508 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1509 int rc = X86EMUL_CONTINUE;
1510 int reg = VCPU_REGS_RAX;
38ba30ba 1511
dde7e6d1
AK		 1512 while (reg <= VCPU_REGS_RDI) {
1513 (reg == VCPU_REGS_RSP) ?
1514 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1515
4487b3b4 1516 rc = em_push(ctxt);
dde7e6d1
AK		 1517 if (rc != X86EMUL_CONTINUE)
1518 return rc;
38ba30ba 1519
dde7e6d1 1520 ++reg;
38ba30ba 1521 }
38ba30ba 1522
dde7e6d1 1523 return rc;
38ba30ba
GN		 1524}
1525
62aaa2f0
TY		 1526static int em_pushf(struct x86_emulate_ctxt *ctxt)
1527{
1528 struct decode_cache *c = &ctxt->decode;
1529
1530 c->src.val = (unsigned long)ctxt->eflags;
1531 return em_push(ctxt);
1532}
1533
b96a7fad 1534static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1535{
dde7e6d1
AK		 1536 struct decode_cache *c = &ctxt->decode;
1537 int rc = X86EMUL_CONTINUE;
1538 int reg = VCPU_REGS_RDI;
38ba30ba 1539
dde7e6d1
AK		 1540 while (reg >= VCPU_REGS_RAX) {
1541 if (reg == VCPU_REGS_RSP) {
1542 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1543 c->op_bytes);
1544 --reg;
1545 }
38ba30ba 1546
b96a7fad 1547 rc = emulate_pop(ctxt, ctxt->ops, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1548 if (rc != X86EMUL_CONTINUE)
1549 break;
1550 --reg;
38ba30ba 1551 }
dde7e6d1 1552 return rc;
38ba30ba
GN		 1553}
1554
6e154e56
MG		 1555int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1556 struct x86_emulate_ops *ops, int irq)
1557{
1558 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1559 int rc;
6e154e56
MG		 1560 struct desc_ptr dt;
1561 gva_t cs_addr;
1562 gva_t eip_addr;
1563 u16 cs, eip;
6e154e56
MG		 1564
1565 /* TODO: Add limit checks */
1566 c->src.val = ctxt->eflags;
4487b3b4 1567 rc = em_push(ctxt);
5c56e1cf
AK		 1568 if (rc != X86EMUL_CONTINUE)
1569 return rc;
6e154e56
MG		 1570
1571 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1572
1aa36616 1573 c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1574 rc = em_push(ctxt);
5c56e1cf
AK		 1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
6e154e56
MG		 1577
1578 c->src.val = c->eip;
4487b3b4 1579 rc = em_push(ctxt);
5c56e1cf
AK		 1580 if (rc != X86EMUL_CONTINUE)
1581 return rc;
1582
4bff1e86 1583 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1584
1585 eip_addr = dt.address + (irq << 2);
1586 cs_addr = dt.address + (irq << 2) + 2;
1587
0f65dd70 1588 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1589 if (rc != X86EMUL_CONTINUE)
1590 return rc;
1591
0f65dd70 1592 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1593 if (rc != X86EMUL_CONTINUE)
1594 return rc;
1595
1596 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1597 if (rc != X86EMUL_CONTINUE)
1598 return rc;
1599
1600 c->eip = eip;
1601
1602 return rc;
1603}
1604
1605static int emulate_int(struct x86_emulate_ctxt *ctxt,
1606 struct x86_emulate_ops *ops, int irq)
1607{
1608 switch(ctxt->mode) {
1609 case X86EMUL_MODE_REAL:
1610 return emulate_int_real(ctxt, ops, irq);
1611 case X86EMUL_MODE_VM86:
1612 case X86EMUL_MODE_PROT16:
1613 case X86EMUL_MODE_PROT32:
1614 case X86EMUL_MODE_PROT64:
1615 default:
1616 /* Protected mode interrupts unimplemented yet */
1617 return X86EMUL_UNHANDLEABLE;
1618 }
1619}
1620
dde7e6d1
AK		 1621static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1622 struct x86_emulate_ops *ops)
38ba30ba 1623{
dde7e6d1
AK		 1624 struct decode_cache *c = &ctxt->decode;
1625 int rc = X86EMUL_CONTINUE;
1626 unsigned long temp_eip = 0;
1627 unsigned long temp_eflags = 0;
1628 unsigned long cs = 0;
1629 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1630 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1631 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1632 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1633
dde7e6d1 1634 /* TODO: Add stack limit check */
38ba30ba 1635
dde7e6d1 1636 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1637
dde7e6d1
AK		 1638 if (rc != X86EMUL_CONTINUE)
1639 return rc;
38ba30ba 1640
35d3d4a1
AK		 1641 if (temp_eip & ~0xffff)
1642 return emulate_gp(ctxt, 0);
38ba30ba 1643
dde7e6d1 1644 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1645
dde7e6d1
AK		 1646 if (rc != X86EMUL_CONTINUE)
1647 return rc;
38ba30ba 1648
dde7e6d1 1649 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1650
dde7e6d1
AK		 1651 if (rc != X86EMUL_CONTINUE)
1652 return rc;
38ba30ba 1653
dde7e6d1 1654 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1655
dde7e6d1
AK		 1656 if (rc != X86EMUL_CONTINUE)
1657 return rc;
38ba30ba 1658
dde7e6d1 1659 c->eip = temp_eip;
38ba30ba 1660
38ba30ba 1661
dde7e6d1
AK		 1662 if (c->op_bytes == 4)
1663 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1664 else if (c->op_bytes == 2) {
1665 ctxt->eflags &= ~0xffff;
1666 ctxt->eflags |= temp_eflags;
38ba30ba 1667 }
dde7e6d1
AK		 1668
1669 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1670 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1671
1672 return rc;
38ba30ba
GN		 1673}
1674
dde7e6d1
AK		 1675static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1676 struct x86_emulate_ops* ops)
c37eda13 1677{
dde7e6d1
AK		 1678 switch(ctxt->mode) {
1679 case X86EMUL_MODE_REAL:
1680 return emulate_iret_real(ctxt, ops);
1681 case X86EMUL_MODE_VM86:
1682 case X86EMUL_MODE_PROT16:
1683 case X86EMUL_MODE_PROT32:
1684 case X86EMUL_MODE_PROT64:
c37eda13 1685 default:
dde7e6d1
AK		 1686 /* iret from protected mode unimplemented yet */
1687 return X86EMUL_UNHANDLEABLE;
c37eda13 1688 }
c37eda13
WY		 1689}
1690
dde7e6d1 1691static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1692 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1693{
1694 struct decode_cache *c = &ctxt->decode;
1695
dde7e6d1 1696 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1697}
1698
dde7e6d1 1699static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1700{
05f086f8 1701 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1702 switch (c->modrm_reg) {
1703 case 0: /* rol */
05f086f8 1704 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1705 break;
1706 case 1: /* ror */
05f086f8 1707 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1708 break;
1709 case 2: /* rcl */
05f086f8 1710 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1711 break;
1712 case 3: /* rcr */
05f086f8 1713 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1714 break;
1715 case 4: /* sal/shl */
1716 case 6: /* sal/shl */
05f086f8 1717 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1718 break;
1719 case 5: /* shr */
05f086f8 1720 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1721 break;
1722 case 7: /* sar */
05f086f8 1723 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1724 break;
1725 }
1726}
1727
1728static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1729 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1730{
1731 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1732 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1733 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1734 u8 de = 0;
8cdbd2c9
LV		 1735
1736 switch (c->modrm_reg) {
1737 case 0 ... 1: /* test */
05f086f8 1738 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1739 break;
1740 case 2: /* not */
1741 c->dst.val = ~c->dst.val;
1742 break;
1743 case 3: /* neg */
05f086f8 1744 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1745 break;
3f9f53b0
MG		 1746 case 4: /* mul */
1747 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1748 break;
1749 case 5: /* imul */
1750 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1751 break;
1752 case 6: /* div */
34d1f490
AK		 1753 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1754 ctxt->eflags, de);
3f9f53b0
MG		 1755 break;
1756 case 7: /* idiv */
34d1f490
AK		 1757 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1758 ctxt->eflags, de);
3f9f53b0 1759 break;
8cdbd2c9 1760 default:
8c5eee30 1761 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1762 }
34d1f490
AK		 1763 if (de)
1764 return emulate_de(ctxt);
8c5eee30 1765 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1766}
1767
4487b3b4 1768static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1769{
1770 struct decode_cache *c = &ctxt->decode;
4179bb02 1771 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1772
1773 switch (c->modrm_reg) {
1774 case 0: /* inc */
05f086f8 1775 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1776 break;
1777 case 1: /* dec */
05f086f8 1778 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1779 break;
d19292e4
MG		 1780 case 2: /* call near abs */ {
1781 long int old_eip;
1782 old_eip = c->eip;
1783 c->eip = c->src.val;
1784 c->src.val = old_eip;
4487b3b4 1785 rc = em_push(ctxt);
d19292e4
MG		 1786 break;
1787 }
8cdbd2c9 1788 case 4: /* jmp abs */
fd60754e 1789 c->eip = c->src.val;
8cdbd2c9
LV		 1790 break;
1791 case 6: /* push */
4487b3b4 1792 rc = em_push(ctxt);
8cdbd2c9 1793 break;
8cdbd2c9 1794 }
4179bb02 1795 return rc;
8cdbd2c9
LV		 1796}
1797
1798static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1799 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1800{
1801 struct decode_cache *c = &ctxt->decode;
16518d5a 1802 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1803
1804 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1805 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1806 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1807 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1808 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1809 } else {
16518d5a
AK		 1810 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1811 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1812
05f086f8 1813 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1814 }
1b30eaa8 1815 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1816}
1817
a77ab5ea
AK		 1818static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1819 struct x86_emulate_ops *ops)
1820{
1821 struct decode_cache *c = &ctxt->decode;
1822 int rc;
1823 unsigned long cs;
1824
1825 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1826 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1827 return rc;
1828 if (c->op_bytes == 4)
1829 c->eip = (u32)c->eip;
1830 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1831 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1832 return rc;
2e873022 1833 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1834 return rc;
1835}
1836
09b5f4d3
WY		 1837static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1838 struct x86_emulate_ops *ops, int seg)
1839{
1840 struct decode_cache *c = &ctxt->decode;
1841 unsigned short sel;
1842 int rc;
1843
1844 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1845
1846 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
1849
1850 c->dst.val = c->src.val;
1851 return rc;
1852}
1853
e66bb2cc
AP		 1854static inline void
1855setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1856 struct x86_emulate_ops *ops, struct desc_struct *cs,
1857 struct desc_struct *ss)
e66bb2cc 1858{
1aa36616
AK		 1859 u16 selector;
1860
79168fd1 1861 memset(cs, 0, sizeof(struct desc_struct));
1aa36616 1862 ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1863 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1864
1865 cs->l = 0; /* will be adjusted later */
79168fd1 1866 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1867 cs->g = 1; /* 4kb granularity */
79168fd1 1868 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1869 cs->type = 0x0b; /* Read, Execute, Accessed */
1870 cs->s = 1;
1871 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1872 cs->p = 1;
1873 cs->d = 1;
e66bb2cc 1874
79168fd1
GN		 1875 set_desc_base(ss, 0); /* flat segment */
1876 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1877 ss->g = 1; /* 4kb granularity */
1878 ss->s = 1;
1879 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1880 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1881 ss->dpl = 0;
79168fd1 1882 ss->p = 1;
e66bb2cc
AP		 1883}
1884
1885static int
3fb1b5db 1886emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1887{
1888 struct decode_cache *c = &ctxt->decode;
79168fd1 1889 struct desc_struct cs, ss;
e66bb2cc 1890 u64 msr_data;
79168fd1 1891 u16 cs_sel, ss_sel;
c2ad2bb3 1892 u64 efer = 0;
e66bb2cc
AP		 1893
1894 /* syscall is not available in real mode */
2e901c4c 1895 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1896 ctxt->mode == X86EMUL_MODE_VM86)
1897 return emulate_ud(ctxt);
e66bb2cc 1898
c2ad2bb3 1899 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1900 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1901
717746e3 1902 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1903 msr_data >>= 32;
79168fd1
GN		 1904 cs_sel = (u16)(msr_data & 0xfffc);
1905 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1906
c2ad2bb3 1907 if (efer & EFER_LMA) {
79168fd1 1908 cs.d = 0;
e66bb2cc
AP		 1909 cs.l = 1;
1910 }
1aa36616
AK		 1911 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1912 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc
AP		 1913
1914 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1915 if (efer & EFER_LMA) {
e66bb2cc
AP		 1916#ifdef CONFIG_X86_64
1917 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1918
717746e3 1919 ops->get_msr(ctxt,
3fb1b5db
GN		 1920 ctxt->mode == X86EMUL_MODE_PROT64 ?
1921 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1922 c->eip = msr_data;
1923
717746e3 1924 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1925 ctxt->eflags &= ~(msr_data | EFLG_RF);
1926#endif
1927 } else {
1928 /* legacy mode */
717746e3 1929 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1930 c->eip = (u32)msr_data;
1931
1932 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1933 }
1934
e54cfa97 1935 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1936}
1937
8c604352 1938static int
3fb1b5db 1939emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1940{
1941 struct decode_cache *c = &ctxt->decode;
79168fd1 1942 struct desc_struct cs, ss;
8c604352 1943 u64 msr_data;
79168fd1 1944 u16 cs_sel, ss_sel;
c2ad2bb3 1945 u64 efer = 0;
8c604352 1946
c2ad2bb3 1947 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1948 /* inject #GP if in real mode */
35d3d4a1
AK		 1949 if (ctxt->mode == X86EMUL_MODE_REAL)
1950 return emulate_gp(ctxt, 0);
8c604352
AP		 1951
1952 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1953 * Therefore, we inject an #UD.
1954 */
35d3d4a1
AK		 1955 if (ctxt->mode == X86EMUL_MODE_PROT64)
1956 return emulate_ud(ctxt);
8c604352 1957
79168fd1 1958 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1959
717746e3 1960 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1961 switch (ctxt->mode) {
1962 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1963 if ((msr_data & 0xfffc) == 0x0)
1964 return emulate_gp(ctxt, 0);
8c604352
AP		 1965 break;
1966 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1967 if (msr_data == 0x0)
1968 return emulate_gp(ctxt, 0);
8c604352
AP		 1969 break;
1970 }
1971
1972 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1973 cs_sel = (u16)msr_data;
1974 cs_sel &= ~SELECTOR_RPL_MASK;
1975 ss_sel = cs_sel + 8;
1976 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1977 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1978 cs.d = 0;
8c604352
AP		 1979 cs.l = 1;
1980 }
1981
1aa36616
AK		 1982 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1983 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1984
717746e3 1985 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1986 c->eip = msr_data;
1987
717746e3 1988 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1989 c->regs[VCPU_REGS_RSP] = msr_data;
1990
e54cfa97 1991 return X86EMUL_CONTINUE;
8c604352
AP		 1992}
1993
4668f050 1994static int
3fb1b5db 1995emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1996{
1997 struct decode_cache *c = &ctxt->decode;
79168fd1 1998 struct desc_struct cs, ss;
4668f050
AP		 1999 u64 msr_data;
2000 int usermode;
79168fd1 2001 u16 cs_sel, ss_sel;
4668f050 2002
a0044755
GN		 2003 /* inject #GP if in real mode or Virtual 8086 mode */
2004 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2005 ctxt->mode == X86EMUL_MODE_VM86)
2006 return emulate_gp(ctxt, 0);
4668f050 2007
79168fd1 2008 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2009
2010 if ((c->rex_prefix & 0x8) != 0x0)
2011 usermode = X86EMUL_MODE_PROT64;
2012 else
2013 usermode = X86EMUL_MODE_PROT32;
2014
2015 cs.dpl = 3;
2016 ss.dpl = 3;
717746e3 2017 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2018 switch (usermode) {
2019 case X86EMUL_MODE_PROT32:
79168fd1 2020 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2021 if ((msr_data & 0xfffc) == 0x0)
2022 return emulate_gp(ctxt, 0);
79168fd1 2023 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2024 break;
2025 case X86EMUL_MODE_PROT64:
79168fd1 2026 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2027 if (msr_data == 0x0)
2028 return emulate_gp(ctxt, 0);
79168fd1
GN		 2029 ss_sel = cs_sel + 8;
2030 cs.d = 0;
4668f050
AP		 2031 cs.l = 1;
2032 break;
2033 }
79168fd1
GN		 2034 cs_sel |= SELECTOR_RPL_MASK;
2035 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2036
1aa36616
AK		 2037 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2038 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2039
bdb475a3
GN		 2040 c->eip = c->regs[VCPU_REGS_RDX];
2041 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2042
e54cfa97 2043 return X86EMUL_CONTINUE;
4668f050
AP		 2044}
2045
9c537244
GN		 2046static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2047 struct x86_emulate_ops *ops)
f850e2e6
GN		 2048{
2049 int iopl;
2050 if (ctxt->mode == X86EMUL_MODE_REAL)
2051 return false;
2052 if (ctxt->mode == X86EMUL_MODE_VM86)
2053 return true;
2054 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2055 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2056}
2057
2058static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2059 struct x86_emulate_ops *ops,
2060 u16 port, u16 len)
2061{
79168fd1 2062 struct desc_struct tr_seg;
5601d05b 2063 u32 base3;
f850e2e6 2064 int r;
1aa36616 2065 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2066 unsigned mask = (1 << len) - 1;
5601d05b 2067 unsigned long base;
f850e2e6 2068
1aa36616 2069 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2070 if (!tr_seg.p)
f850e2e6 2071 return false;
79168fd1 2072 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2073 return false;
5601d05b
GN		 2074 base = get_desc_base(&tr_seg);
2075#ifdef CONFIG_X86_64
2076 base |= ((u64)base3) << 32;
2077#endif
0f65dd70 2078 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2079 if (r != X86EMUL_CONTINUE)
2080 return false;
79168fd1 2081 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2082 return false;
0f65dd70 2083 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2084 if (r != X86EMUL_CONTINUE)
2085 return false;
2086 if ((perm >> bit_idx) & mask)
2087 return false;
2088 return true;
2089}
2090
2091static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2092 struct x86_emulate_ops *ops,
2093 u16 port, u16 len)
2094{
4fc40f07
GN		 2095 if (ctxt->perm_ok)
2096 return true;
2097
9c537244 2098 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2099 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2100 return false;
4fc40f07
GN		 2101
2102 ctxt->perm_ok = true;
2103
f850e2e6
GN		 2104 return true;
2105}
2106
38ba30ba
GN		 2107static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2108 struct x86_emulate_ops *ops,
2109 struct tss_segment_16 *tss)
2110{
2111 struct decode_cache *c = &ctxt->decode;
2112
2113 tss->ip = c->eip;
2114 tss->flag = ctxt->eflags;
2115 tss->ax = c->regs[VCPU_REGS_RAX];
2116 tss->cx = c->regs[VCPU_REGS_RCX];
2117 tss->dx = c->regs[VCPU_REGS_RDX];
2118 tss->bx = c->regs[VCPU_REGS_RBX];
2119 tss->sp = c->regs[VCPU_REGS_RSP];
2120 tss->bp = c->regs[VCPU_REGS_RBP];
2121 tss->si = c->regs[VCPU_REGS_RSI];
2122 tss->di = c->regs[VCPU_REGS_RDI];
2123
1aa36616
AK		 2124 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2125 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2126 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2127 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2128 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2129}
2130
2131static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2132 struct x86_emulate_ops *ops,
2133 struct tss_segment_16 *tss)
2134{
2135 struct decode_cache *c = &ctxt->decode;
2136 int ret;
2137
2138 c->eip = tss->ip;
2139 ctxt->eflags = tss->flag | 2;
2140 c->regs[VCPU_REGS_RAX] = tss->ax;
2141 c->regs[VCPU_REGS_RCX] = tss->cx;
2142 c->regs[VCPU_REGS_RDX] = tss->dx;
2143 c->regs[VCPU_REGS_RBX] = tss->bx;
2144 c->regs[VCPU_REGS_RSP] = tss->sp;
2145 c->regs[VCPU_REGS_RBP] = tss->bp;
2146 c->regs[VCPU_REGS_RSI] = tss->si;
2147 c->regs[VCPU_REGS_RDI] = tss->di;
2148
2149 /*
2150 * SDM says that segment selectors are loaded before segment
2151 * descriptors
2152 */
1aa36616
AK		 2153 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2154 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2155 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2156 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2157 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2158
2159 /*
2160 * Now load segment descriptors. If fault happenes at this stage
2161 * it is handled in a context of new task
2162 */
2163 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2164 if (ret != X86EMUL_CONTINUE)
2165 return ret;
2166 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2167 if (ret != X86EMUL_CONTINUE)
2168 return ret;
2169 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2170 if (ret != X86EMUL_CONTINUE)
2171 return ret;
2172 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2173 if (ret != X86EMUL_CONTINUE)
2174 return ret;
2175 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2176 if (ret != X86EMUL_CONTINUE)
2177 return ret;
2178
2179 return X86EMUL_CONTINUE;
2180}
2181
2182static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2183 struct x86_emulate_ops *ops,
2184 u16 tss_selector, u16 old_tss_sel,
2185 ulong old_tss_base, struct desc_struct *new_desc)
2186{
2187 struct tss_segment_16 tss_seg;
2188 int ret;
bcc55cba 2189 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2190
0f65dd70 2191 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2192 &ctxt->exception);
db297e3d 2193 if (ret != X86EMUL_CONTINUE)
38ba30ba 2194 /* FIXME: need to provide precise fault address */
38ba30ba 2195 return ret;
38ba30ba
GN		 2196
2197 save_state_to_tss16(ctxt, ops, &tss_seg);
2198
0f65dd70 2199 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2200 &ctxt->exception);
db297e3d 2201 if (ret != X86EMUL_CONTINUE)
38ba30ba 2202 /* FIXME: need to provide precise fault address */
38ba30ba 2203 return ret;
38ba30ba 2204
0f65dd70 2205 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2206 &ctxt->exception);
db297e3d 2207 if (ret != X86EMUL_CONTINUE)
38ba30ba 2208 /* FIXME: need to provide precise fault address */
38ba30ba 2209 return ret;
38ba30ba
GN		 2210
2211 if (old_tss_sel != 0xffff) {
2212 tss_seg.prev_task_link = old_tss_sel;
2213
0f65dd70 2214 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2215 &tss_seg.prev_task_link,
2216 sizeof tss_seg.prev_task_link,
0f65dd70 2217 &ctxt->exception);
db297e3d 2218 if (ret != X86EMUL_CONTINUE)
38ba30ba 2219 /* FIXME: need to provide precise fault address */
38ba30ba 2220 return ret;
38ba30ba
GN		 2221 }
2222
2223 return load_state_from_tss16(ctxt, ops, &tss_seg);
2224}
2225
2226static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2227 struct x86_emulate_ops *ops,
2228 struct tss_segment_32 *tss)
2229{
2230 struct decode_cache *c = &ctxt->decode;
2231
717746e3 2232 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2233 tss->eip = c->eip;
2234 tss->eflags = ctxt->eflags;
2235 tss->eax = c->regs[VCPU_REGS_RAX];
2236 tss->ecx = c->regs[VCPU_REGS_RCX];
2237 tss->edx = c->regs[VCPU_REGS_RDX];
2238 tss->ebx = c->regs[VCPU_REGS_RBX];
2239 tss->esp = c->regs[VCPU_REGS_RSP];
2240 tss->ebp = c->regs[VCPU_REGS_RBP];
2241 tss->esi = c->regs[VCPU_REGS_RSI];
2242 tss->edi = c->regs[VCPU_REGS_RDI];
2243
1aa36616
AK		 2244 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2245 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2246 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2247 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2248 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2249 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2250 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2251}
2252
2253static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2254 struct x86_emulate_ops *ops,
2255 struct tss_segment_32 *tss)
2256{
2257 struct decode_cache *c = &ctxt->decode;
2258 int ret;
2259
717746e3 2260 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2261 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2262 c->eip = tss->eip;
2263 ctxt->eflags = tss->eflags | 2;
2264 c->regs[VCPU_REGS_RAX] = tss->eax;
2265 c->regs[VCPU_REGS_RCX] = tss->ecx;
2266 c->regs[VCPU_REGS_RDX] = tss->edx;
2267 c->regs[VCPU_REGS_RBX] = tss->ebx;
2268 c->regs[VCPU_REGS_RSP] = tss->esp;
2269 c->regs[VCPU_REGS_RBP] = tss->ebp;
2270 c->regs[VCPU_REGS_RSI] = tss->esi;
2271 c->regs[VCPU_REGS_RDI] = tss->edi;
2272
2273 /*
2274 * SDM says that segment selectors are loaded before segment
2275 * descriptors
2276 */
1aa36616
AK		 2277 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2278 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2279 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2280 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2281 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2282 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2283 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2284
2285 /*
2286 * Now load segment descriptors. If fault happenes at this stage
2287 * it is handled in a context of new task
2288 */
2289 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2290 if (ret != X86EMUL_CONTINUE)
2291 return ret;
2292 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2293 if (ret != X86EMUL_CONTINUE)
2294 return ret;
2295 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2296 if (ret != X86EMUL_CONTINUE)
2297 return ret;
2298 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2299 if (ret != X86EMUL_CONTINUE)
2300 return ret;
2301 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2302 if (ret != X86EMUL_CONTINUE)
2303 return ret;
2304 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2308 if (ret != X86EMUL_CONTINUE)
2309 return ret;
2310
2311 return X86EMUL_CONTINUE;
2312}
2313
2314static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2315 struct x86_emulate_ops *ops,
2316 u16 tss_selector, u16 old_tss_sel,
2317 ulong old_tss_base, struct desc_struct *new_desc)
2318{
2319 struct tss_segment_32 tss_seg;
2320 int ret;
bcc55cba 2321 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2322
0f65dd70 2323 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2324 &ctxt->exception);
db297e3d 2325 if (ret != X86EMUL_CONTINUE)
38ba30ba 2326 /* FIXME: need to provide precise fault address */
38ba30ba 2327 return ret;
38ba30ba
GN		 2328
2329 save_state_to_tss32(ctxt, ops, &tss_seg);
2330
0f65dd70 2331 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2332 &ctxt->exception);
db297e3d 2333 if (ret != X86EMUL_CONTINUE)
38ba30ba 2334 /* FIXME: need to provide precise fault address */
38ba30ba 2335 return ret;
38ba30ba 2336
0f65dd70 2337 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2338 &ctxt->exception);
db297e3d 2339 if (ret != X86EMUL_CONTINUE)
38ba30ba 2340 /* FIXME: need to provide precise fault address */
38ba30ba 2341 return ret;
38ba30ba
GN		 2342
2343 if (old_tss_sel != 0xffff) {
2344 tss_seg.prev_task_link = old_tss_sel;
2345
0f65dd70 2346 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2347 &tss_seg.prev_task_link,
2348 sizeof tss_seg.prev_task_link,
0f65dd70 2349 &ctxt->exception);
db297e3d 2350 if (ret != X86EMUL_CONTINUE)
38ba30ba 2351 /* FIXME: need to provide precise fault address */
38ba30ba 2352 return ret;
38ba30ba
GN		 2353 }
2354
2355 return load_state_from_tss32(ctxt, ops, &tss_seg);
2356}
2357
2358static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2359 struct x86_emulate_ops *ops,
2360 u16 tss_selector, int reason,
2361 bool has_error_code, u32 error_code)
38ba30ba
GN		 2362{
2363 struct desc_struct curr_tss_desc, next_tss_desc;
2364 int ret;
1aa36616 2365 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2366 ulong old_tss_base =
4bff1e86 2367 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2368 u32 desc_limit;
38ba30ba
GN		 2369
2370 /* FIXME: old_tss_base == ~0 ? */
2371
2372 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2373 if (ret != X86EMUL_CONTINUE)
2374 return ret;
2375 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
2378
2379 /* FIXME: check that next_tss_desc is tss */
2380
2381 if (reason != TASK_SWITCH_IRET) {
2382 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2383 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2384 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2385 }
2386
ceffb459
GN		 2387 desc_limit = desc_limit_scaled(&next_tss_desc);
2388 if (!next_tss_desc.p ||
2389 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2390 desc_limit < 0x2b)) {
54b8486f 2391 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2392 return X86EMUL_PROPAGATE_FAULT;
2393 }
2394
2395 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2396 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2397 write_segment_descriptor(ctxt, ops, old_tss_sel,
2398 &curr_tss_desc);
2399 }
2400
2401 if (reason == TASK_SWITCH_IRET)
2402 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2403
2404 /* set back link to prev task only if NT bit is set in eflags
2405 note that old_tss_sel is not used afetr this point */
2406 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2407 old_tss_sel = 0xffff;
2408
2409 if (next_tss_desc.type & 8)
2410 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2411 old_tss_base, &next_tss_desc);
2412 else
2413 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2414 old_tss_base, &next_tss_desc);
0760d448
JK		 2415 if (ret != X86EMUL_CONTINUE)
2416 return ret;
38ba30ba
GN		 2417
2418 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2419 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2420
2421 if (reason != TASK_SWITCH_IRET) {
2422 next_tss_desc.type |= (1 << 1); /* set busy flag */
2423 write_segment_descriptor(ctxt, ops, tss_selector,
2424 &next_tss_desc);
2425 }
2426
717746e3 2427 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2428 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2429
e269fb21
JK		 2430 if (has_error_code) {
2431 struct decode_cache *c = &ctxt->decode;
2432
2433 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2434 c->lock_prefix = 0;
2435 c->src.val = (unsigned long) error_code;
4487b3b4 2436 ret = em_push(ctxt);
e269fb21
JK		 2437 }
2438
38ba30ba
GN		 2439 return ret;
2440}
2441
2442int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2443 u16 tss_selector, int reason,
2444 bool has_error_code, u32 error_code)
38ba30ba 2445{
9aabc88f 2446 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2447 struct decode_cache *c = &ctxt->decode;
2448 int rc;
2449
38ba30ba 2450 c->eip = ctxt->eip;
e269fb21 2451 c->dst.type = OP_NONE;
38ba30ba 2452
e269fb21
JK		 2453 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2454 has_error_code, error_code);
38ba30ba 2455
4179bb02
TY		 2456 if (rc == X86EMUL_CONTINUE)
2457 ctxt->eip = c->eip;
38ba30ba 2458
a0c0ab2f 2459 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2460}
2461
90de84f5 2462static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2463 int reg, struct operand *op)
a682e354
GN		 2464{
2465 struct decode_cache *c = &ctxt->decode;
2466 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2467
d9271123 2468 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2469 op->addr.mem.ea = register_address(c, c->regs[reg]);
2470 op->addr.mem.seg = seg;
a682e354
GN		 2471}
2472
7af04fc0
AK		 2473static int em_das(struct x86_emulate_ctxt *ctxt)
2474{
2475 struct decode_cache *c = &ctxt->decode;
2476 u8 al, old_al;
2477 bool af, cf, old_cf;
2478
2479 cf = ctxt->eflags & X86_EFLAGS_CF;
2480 al = c->dst.val;
2481
2482 old_al = al;
2483 old_cf = cf;
2484 cf = false;
2485 af = ctxt->eflags & X86_EFLAGS_AF;
2486 if ((al & 0x0f) > 9 || af) {
2487 al -= 6;
2488 cf = old_cf | (al >= 250);
2489 af = true;
2490 } else {
2491 af = false;
2492 }
2493 if (old_al > 0x99 || old_cf) {
2494 al -= 0x60;
2495 cf = true;
2496 }
2497
2498 c->dst.val = al;
2499 /* Set PF, ZF, SF */
2500 c->src.type = OP_IMM;
2501 c->src.val = 0;
2502 c->src.bytes = 1;
2503 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2504 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2505 if (cf)
2506 ctxt->eflags |= X86_EFLAGS_CF;
2507 if (af)
2508 ctxt->eflags |= X86_EFLAGS_AF;
2509 return X86EMUL_CONTINUE;
2510}
2511
0ef753b8
AK		 2512static int em_call_far(struct x86_emulate_ctxt *ctxt)
2513{
2514 struct decode_cache *c = &ctxt->decode;
2515 u16 sel, old_cs;
2516 ulong old_eip;
2517 int rc;
2518
1aa36616 2519 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2520 old_eip = c->eip;
2521
2522 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2523 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2524 return X86EMUL_CONTINUE;
2525
2526 c->eip = 0;
2527 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2528
2529 c->src.val = old_cs;
4487b3b4 2530 rc = em_push(ctxt);
0ef753b8
AK		 2531 if (rc != X86EMUL_CONTINUE)
2532 return rc;
2533
2534 c->src.val = old_eip;
4487b3b4 2535 return em_push(ctxt);
0ef753b8
AK		 2536}
2537
40ece7c7
AK		 2538static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2539{
2540 struct decode_cache *c = &ctxt->decode;
2541 int rc;
2542
2543 c->dst.type = OP_REG;
2544 c->dst.addr.reg = &c->eip;
2545 c->dst.bytes = c->op_bytes;
2546 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2547 if (rc != X86EMUL_CONTINUE)
2548 return rc;
2549 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2550 return X86EMUL_CONTINUE;
2551}
2552
d67fc27a
TY		 2553static int em_add(struct x86_emulate_ctxt *ctxt)
2554{
2555 struct decode_cache *c = &ctxt->decode;
2556
2557 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2558 return X86EMUL_CONTINUE;
2559}
2560
2561static int em_or(struct x86_emulate_ctxt *ctxt)
2562{
2563 struct decode_cache *c = &ctxt->decode;
2564
2565 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2566 return X86EMUL_CONTINUE;
2567}
2568
2569static int em_adc(struct x86_emulate_ctxt *ctxt)
2570{
2571 struct decode_cache *c = &ctxt->decode;
2572
2573 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2574 return X86EMUL_CONTINUE;
2575}
2576
2577static int em_sbb(struct x86_emulate_ctxt *ctxt)
2578{
2579 struct decode_cache *c = &ctxt->decode;
2580
2581 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2582 return X86EMUL_CONTINUE;
2583}
2584
2585static int em_and(struct x86_emulate_ctxt *ctxt)
2586{
2587 struct decode_cache *c = &ctxt->decode;
2588
2589 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2590 return X86EMUL_CONTINUE;
2591}
2592
2593static int em_sub(struct x86_emulate_ctxt *ctxt)
2594{
2595 struct decode_cache *c = &ctxt->decode;
2596
2597 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2598 return X86EMUL_CONTINUE;
2599}
2600
2601static int em_xor(struct x86_emulate_ctxt *ctxt)
2602{
2603 struct decode_cache *c = &ctxt->decode;
2604
2605 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2606 return X86EMUL_CONTINUE;
2607}
2608
2609static int em_cmp(struct x86_emulate_ctxt *ctxt)
2610{
2611 struct decode_cache *c = &ctxt->decode;
2612
2613 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2614 /* Disable writeback. */
2615 c->dst.type = OP_NONE;
2616 return X86EMUL_CONTINUE;
2617}
2618
5c82aa29 2619static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2620{
2621 struct decode_cache *c = &ctxt->decode;
2622
f3a1b9f4
AK		 2623 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2624 return X86EMUL_CONTINUE;
2625}
2626
5c82aa29
AK		 2627static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2628{
2629 struct decode_cache *c = &ctxt->decode;
2630
2631 c->dst.val = c->src2.val;
2632 return em_imul(ctxt);
2633}
2634
61429142
AK		 2635static int em_cwd(struct x86_emulate_ctxt *ctxt)
2636{
2637 struct decode_cache *c = &ctxt->decode;
2638
2639 c->dst.type = OP_REG;
2640 c->dst.bytes = c->src.bytes;
2641 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2642 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2643
2644 return X86EMUL_CONTINUE;
2645}
2646
48bb5d3c
AK		 2647static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2648{
48bb5d3c
AK		 2649 struct decode_cache *c = &ctxt->decode;
2650 u64 tsc = 0;
2651
717746e3 2652 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2653 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2654 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2655 return X86EMUL_CONTINUE;
2656}
2657
b9eac5f4
AK		 2658static int em_mov(struct x86_emulate_ctxt *ctxt)
2659{
2660 struct decode_cache *c = &ctxt->decode;
2661 c->dst.val = c->src.val;
2662 return X86EMUL_CONTINUE;
2663}
2664
aa97bb48
AK		 2665static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2666{
2667 struct decode_cache *c = &ctxt->decode;
2668 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2669 return X86EMUL_CONTINUE;
2670}
2671
38503911
AK		 2672static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2673{
2674 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2675 int rc;
2676 ulong linear;
2677
83b8795a 2678 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2679 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2680 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2681 /* Disable writeback. */
2682 c->dst.type = OP_NONE;
2683 return X86EMUL_CONTINUE;
2684}
2685
2d04a05b
AK		 2686static int em_clts(struct x86_emulate_ctxt *ctxt)
2687{
2688 ulong cr0;
2689
2690 cr0 = ctxt->ops->get_cr(ctxt, 0);
2691 cr0 &= ~X86_CR0_TS;
2692 ctxt->ops->set_cr(ctxt, 0, cr0);
2693 return X86EMUL_CONTINUE;
2694}
2695
26d05cc7
AK		 2696static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2697{
2698 struct decode_cache *c = &ctxt->decode;
2699 int rc;
2700
2701 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2702 return X86EMUL_UNHANDLEABLE;
2703
2704 rc = ctxt->ops->fix_hypercall(ctxt);
2705 if (rc != X86EMUL_CONTINUE)
2706 return rc;
2707
2708 /* Let the processor re-execute the fixed hypercall */
2709 c->eip = ctxt->eip;
2710 /* Disable writeback. */
2711 c->dst.type = OP_NONE;
2712 return X86EMUL_CONTINUE;
2713}
2714
2715static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2716{
2717 struct decode_cache *c = &ctxt->decode;
2718 struct desc_ptr desc_ptr;
2719 int rc;
2720
509cf9fe 2721 rc = read_descriptor(ctxt, c->src.addr.mem,
26d05cc7
AK		 2722 &desc_ptr.size, &desc_ptr.address,
2723 c->op_bytes);
2724 if (rc != X86EMUL_CONTINUE)
2725 return rc;
2726 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2727 /* Disable writeback. */
2728 c->dst.type = OP_NONE;
2729 return X86EMUL_CONTINUE;
2730}
2731
5ef39c71 2732static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2733{
2734 struct decode_cache *c = &ctxt->decode;
2735 int rc;
2736
5ef39c71
AK		 2737 rc = ctxt->ops->fix_hypercall(ctxt);
2738
26d05cc7
AK		 2739 /* Disable writeback. */
2740 c->dst.type = OP_NONE;
2741 return rc;
2742}
2743
2744static int em_lidt(struct x86_emulate_ctxt *ctxt)
2745{
2746 struct decode_cache *c = &ctxt->decode;
2747 struct desc_ptr desc_ptr;
2748 int rc;
2749
509cf9fe
TY		 2750 rc = read_descriptor(ctxt, c->src.addr.mem,
2751 &desc_ptr.size, &desc_ptr.address,
26d05cc7
AK		 2752 c->op_bytes);
2753 if (rc != X86EMUL_CONTINUE)
2754 return rc;
2755 ctxt->ops->set_idt(ctxt, &desc_ptr);
2756 /* Disable writeback. */
2757 c->dst.type = OP_NONE;
2758 return X86EMUL_CONTINUE;
2759}
2760
2761static int em_smsw(struct x86_emulate_ctxt *ctxt)
2762{
2763 struct decode_cache *c = &ctxt->decode;
2764
2765 c->dst.bytes = 2;
2766 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2767 return X86EMUL_CONTINUE;
2768}
2769
2770static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2771{
2772 struct decode_cache *c = &ctxt->decode;
2773 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2774 | (c->src.val & 0x0f));
2775 c->dst.type = OP_NONE;
2776 return X86EMUL_CONTINUE;
2777}
2778
cfec82cb
JR		 2779static bool valid_cr(int nr)
2780{
2781 switch (nr) {
2782 case 0:
2783 case 2 ... 4:
2784 case 8:
2785 return true;
2786 default:
2787 return false;
2788 }
2789}
2790
2791static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2792{
2793 struct decode_cache *c = &ctxt->decode;
2794
2795 if (!valid_cr(c->modrm_reg))
2796 return emulate_ud(ctxt);
2797
2798 return X86EMUL_CONTINUE;
2799}
2800
2801static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2802{
2803 struct decode_cache *c = &ctxt->decode;
2804 u64 new_val = c->src.val64;
2805 int cr = c->modrm_reg;
c2ad2bb3 2806 u64 efer = 0;
cfec82cb
JR		 2807
2808 static u64 cr_reserved_bits[] = {
2809 0xffffffff00000000ULL,
2810 0, 0, 0, /* CR3 checked later */
2811 CR4_RESERVED_BITS,
2812 0, 0, 0,
2813 CR8_RESERVED_BITS,
2814 };
2815
2816 if (!valid_cr(cr))
2817 return emulate_ud(ctxt);
2818
2819 if (new_val & cr_reserved_bits[cr])
2820 return emulate_gp(ctxt, 0);
2821
2822 switch (cr) {
2823 case 0: {
c2ad2bb3 2824 u64 cr4;
cfec82cb
JR		 2825 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2826 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2827 return emulate_gp(ctxt, 0);
2828
717746e3
AK		 2829 cr4 = ctxt->ops->get_cr(ctxt, 4);
2830 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2831
2832 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2833 !(cr4 & X86_CR4_PAE))
2834 return emulate_gp(ctxt, 0);
2835
2836 break;
2837 }
2838 case 3: {
2839 u64 rsvd = 0;
2840
c2ad2bb3
AK		 2841 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2842 if (efer & EFER_LMA)
cfec82cb 2843 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2844 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2845 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2846 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2847 rsvd = CR3_NONPAE_RESERVED_BITS;
2848
2849 if (new_val & rsvd)
2850 return emulate_gp(ctxt, 0);
2851
2852 break;
2853 }
2854 case 4: {
c2ad2bb3 2855 u64 cr4;
cfec82cb 2856
717746e3
AK		 2857 cr4 = ctxt->ops->get_cr(ctxt, 4);
2858 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2859
2860 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2861 return emulate_gp(ctxt, 0);
2862
2863 break;
2864 }
2865 }
2866
2867 return X86EMUL_CONTINUE;
2868}
2869
3b88e41a
JR		 2870static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2871{
2872 unsigned long dr7;
2873
717746e3 2874 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2875
2876 /* Check if DR7.Global_Enable is set */
2877 return dr7 & (1 << 13);
2878}
2879
2880static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2881{
2882 struct decode_cache *c = &ctxt->decode;
2883 int dr = c->modrm_reg;
2884 u64 cr4;
2885
2886 if (dr > 7)
2887 return emulate_ud(ctxt);
2888
717746e3 2889 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2890 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2891 return emulate_ud(ctxt);
2892
2893 if (check_dr7_gd(ctxt))
2894 return emulate_db(ctxt);
2895
2896 return X86EMUL_CONTINUE;
2897}
2898
2899static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2900{
2901 struct decode_cache *c = &ctxt->decode;
2902 u64 new_val = c->src.val64;
2903 int dr = c->modrm_reg;
2904
2905 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2906 return emulate_gp(ctxt, 0);
2907
2908 return check_dr_read(ctxt);
2909}
2910
01de8b09
JR		 2911static int check_svme(struct x86_emulate_ctxt *ctxt)
2912{
2913 u64 efer;
2914
717746e3 2915 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2916
2917 if (!(efer & EFER_SVME))
2918 return emulate_ud(ctxt);
2919
2920 return X86EMUL_CONTINUE;
2921}
2922
2923static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2924{
fe870ab9 2925 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2926
2927 /* Valid physical address? */
d4224449 2928 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2929 return emulate_gp(ctxt, 0);
2930
2931 return check_svme(ctxt);
2932}
2933
d7eb8203
JR		 2934static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2935{
717746e3 2936 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2937
717746e3 2938 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2939 return emulate_ud(ctxt);
2940
2941 return X86EMUL_CONTINUE;
2942}
2943
8061252e
JR		 2944static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2945{
717746e3 2946 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2947 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2948
717746e3 2949 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2950 (rcx > 3))
2951 return emulate_gp(ctxt, 0);
2952
2953 return X86EMUL_CONTINUE;
2954}
2955
f6511935
JR		 2956static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2957{
2958 struct decode_cache *c = &ctxt->decode;
2959
2960 c->dst.bytes = min(c->dst.bytes, 4u);
2961 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2962 return emulate_gp(ctxt, 0);
2963
2964 return X86EMUL_CONTINUE;
2965}
2966
2967static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2968{
2969 struct decode_cache *c = &ctxt->decode;
2970
2971 c->src.bytes = min(c->src.bytes, 4u);
2972 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2973 return emulate_gp(ctxt, 0);
2974
2975 return X86EMUL_CONTINUE;
2976}
2977
73fba5f4 2978#define D(_y) { .flags = (_y) }
c4f035c6 2979#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2980#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2981 .check_perm = (_p) }
73fba5f4 2982#define N D(0)
01de8b09 2983#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2984#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2985#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2986#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2987#define II(_f, _e, _i) \
2988 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2989#define IIP(_f, _e, _i, _p) \
2990 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2991 .check_perm = (_p) }
aa97bb48 2992#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2993
8d8f4e9f 2994#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2995#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2996#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2997
d67fc27a
TY		 2998#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2999 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3000 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3001
d7eb8203
JR		 3002static struct opcode group7_rm1[] = {
3003 DI(SrcNone | ModRM | Priv, monitor),
3004 DI(SrcNone | ModRM | Priv, mwait),
3005 N, N, N, N, N, N,
3006};
3007
01de8b09
JR		 3008static struct opcode group7_rm3[] = {
3009 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3010 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3011 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3012 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3013 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3014 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3015 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3016 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3017};
6230f7fc 3018
d7eb8203
JR		 3019static struct opcode group7_rm7[] = {
3020 N,
3021 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3022 N, N, N, N, N, N,
3023};
d67fc27a 3024
73fba5f4 3025static struct opcode group1[] = {
d67fc27a
TY		 3026 I(Lock, em_add),
3027 I(Lock, em_or),
3028 I(Lock, em_adc),
3029 I(Lock, em_sbb),
3030 I(Lock, em_and),
3031 I(Lock, em_sub),
3032 I(Lock, em_xor),
3033 I(0, em_cmp),
73fba5f4
AK		 3034};
3035
3036static struct opcode group1A[] = {
3037 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3038};
3039
3040static struct opcode group3[] = {
3041 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3042 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3043 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3044};
3045
3046static struct opcode group4[] = {
3047 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3048 N, N, N, N, N, N,
3049};
3050
3051static struct opcode group5[] = {
3052 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3053 D(SrcMem | ModRM | Stack),
3054 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3055 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3056 D(SrcMem | ModRM | Stack), N,
3057};
3058
dee6bb70
JR		 3059static struct opcode group6[] = {
3060 DI(ModRM | Prot, sldt),
3061 DI(ModRM | Prot, str),
3062 DI(ModRM | Prot | Priv, lldt),
3063 DI(ModRM | Prot | Priv, ltr),
3064 N, N, N, N,
3065};
3066
73fba5f4 3067static struct group_dual group7 = { {
dee6bb70
JR		 3068 DI(ModRM | Mov | DstMem | Priv, sgdt),
3069 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3070 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3071 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3072 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3073 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3074 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3075}, {
5ef39c71
AK		 3076 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3077 EXT(0, group7_rm1),
01de8b09 3078 N, EXT(0, group7_rm3),
5ef39c71
AK		 3079 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3080 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3081} };
3082
3083static struct opcode group8[] = {
3084 N, N, N, N,
3085 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3086 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3087};
3088
3089static struct group_dual group9 = { {
3090 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3091}, {
3092 N, N, N, N, N, N, N, N,
3093} };
3094
a4d4a7c1
AK		 3095static struct opcode group11[] = {
3096 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3097};
3098
aa97bb48
AK		 3099static struct gprefix pfx_0f_6f_0f_7f = {
3100 N, N, N, I(Sse, em_movdqu),
3101};
3102
73fba5f4
AK		 3103static struct opcode opcode_table[256] = {
3104 /* 0x00 - 0x07 */
d67fc27a 3105 I6ALU(Lock, em_add),
73fba5f4
AK		 3106 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3107 /* 0x08 - 0x0F */
d67fc27a 3108 I6ALU(Lock, em_or),
73fba5f4
AK		 3109 D(ImplicitOps | Stack | No64), N,
3110 /* 0x10 - 0x17 */
d67fc27a 3111 I6ALU(Lock, em_adc),
73fba5f4
AK		 3112 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3113 /* 0x18 - 0x1F */
d67fc27a 3114 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3115 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3116 /* 0x20 - 0x27 */
d67fc27a 3117 I6ALU(Lock, em_and), N, N,
73fba5f4 3118 /* 0x28 - 0x2F */
d67fc27a 3119 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3120 /* 0x30 - 0x37 */
d67fc27a 3121 I6ALU(Lock, em_xor), N, N,
73fba5f4 3122 /* 0x38 - 0x3F */
d67fc27a 3123 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3124 /* 0x40 - 0x4F */
3125 X16(D(DstReg)),
3126 /* 0x50 - 0x57 */
63540382 3127 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3128 /* 0x58 - 0x5F */
c54fe504 3129 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3130 /* 0x60 - 0x67 */
b96a7fad
TY		 3131 I(ImplicitOps | Stack | No64, em_pusha),
3132 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3133 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3134 N, N, N, N,
3135 /* 0x68 - 0x6F */
d46164db
AK		 3136 I(SrcImm | Mov | Stack, em_push),
3137 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3138 I(SrcImmByte | Mov | Stack, em_push),
3139 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 3140 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3141 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3142 /* 0x70 - 0x7F */
3143 X16(D(SrcImmByte)),
3144 /* 0x80 - 0x87 */
3145 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3146 G(DstMem | SrcImm | ModRM | Group, group1),
3147 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3148 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3149 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3150 /* 0x88 - 0x8F */
b9eac5f4
AK		 3151 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3152 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3153 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3154 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3155 /* 0x90 - 0x97 */
bf608f88 3156 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3157 /* 0x98 - 0x9F */
61429142 3158 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3159 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3160 II(ImplicitOps | Stack, em_pushf, pushf),
3161 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3162 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3163 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3164 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3165 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3166 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3167 /* 0xA8 - 0xAF */
50748613 3168 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3169 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3170 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3171 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3172 /* 0xB0 - 0xB7 */
b9eac5f4 3173 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3174 /* 0xB8 - 0xBF */
b9eac5f4 3175 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3176 /* 0xC0 - 0xC7 */
d2c6c7ad 3177 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3178 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3179 D(ImplicitOps | Stack),
09b5f4d3 3180 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3181 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3182 /* 0xC8 - 0xCF */
3183 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3184 D(ImplicitOps), DI(SrcImmByte, intn),
3185 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3186 /* 0xD0 - 0xD7 */
d2c6c7ad 3187 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3188 N, N, N, N,
3189 /* 0xD8 - 0xDF */
3190 N, N, N, N, N, N, N, N,
3191 /* 0xE0 - 0xE7 */
e4abac67 3192 X4(D(SrcImmByte)),
f6511935
JR		 3193 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3194 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3195 /* 0xE8 - 0xEF */
3196 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3197 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 3198 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3199 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 3200 /* 0xF0 - 0xF7 */
bf608f88 3201 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3202 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3203 G(ByteOp, group3), G(0, group3),
73fba5f4 3204 /* 0xF8 - 0xFF */
8744aa9a 3205 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3206 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3207};
3208
3209static struct opcode twobyte_table[256] = {
3210 /* 0x00 - 0x0F */
dee6bb70 3211 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3212 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3213 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3214 N, D(ImplicitOps | ModRM), N, N,
3215 /* 0x10 - 0x1F */
3216 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3217 /* 0x20 - 0x2F */
cfec82cb 3218 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3219 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3220 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3221 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3222 N, N, N, N,
3223 N, N, N, N, N, N, N, N,
3224 /* 0x30 - 0x3F */
8061252e
JR		 3225 DI(ImplicitOps | Priv, wrmsr),
3226 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3227 DI(ImplicitOps | Priv, rdmsr),
3228 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3229 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3230 N, N,
73fba5f4
AK		 3231 N, N, N, N, N, N, N, N,
3232 /* 0x40 - 0x4F */
3233 X16(D(DstReg | SrcMem | ModRM | Mov)),
3234 /* 0x50 - 0x5F */
3235 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3236 /* 0x60 - 0x6F */
aa97bb48
AK		 3237 N, N, N, N,
3238 N, N, N, N,
3239 N, N, N, N,
3240 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3241 /* 0x70 - 0x7F */
aa97bb48
AK		 3242 N, N, N, N,
3243 N, N, N, N,
3244 N, N, N, N,
3245 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3246 /* 0x80 - 0x8F */
3247 X16(D(SrcImm)),
3248 /* 0x90 - 0x9F */
ee45b58e 3249 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3250 /* 0xA0 - 0xA7 */
3251 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3252 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3253 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3254 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3255 /* 0xA8 - 0xAF */
3256 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3257 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3258 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3259 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3260 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3261 /* 0xB0 - 0xB7 */
739ae406 3262 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3263 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3264 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3265 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3266 /* 0xB8 - 0xBF */
3267 N, N,
ba7ff2b7 3268 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3269 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3270 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3271 /* 0xC0 - 0xCF */
739ae406 3272 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3273 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3274 N, N, N, GD(0, &group9),
3275 N, N, N, N, N, N, N, N,
3276 /* 0xD0 - 0xDF */
3277 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3278 /* 0xE0 - 0xEF */
3279 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3280 /* 0xF0 - 0xFF */
3281 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3282};
3283
3284#undef D
3285#undef N
3286#undef G
3287#undef GD
3288#undef I
aa97bb48 3289#undef GP
01de8b09 3290#undef EXT
73fba5f4 3291
8d8f4e9f 3292#undef D2bv
f6511935 3293#undef D2bvIP
8d8f4e9f 3294#undef I2bv
d67fc27a 3295#undef I6ALU
8d8f4e9f 3296
39f21ee5
AK		 3297static unsigned imm_size(struct decode_cache *c)
3298{
3299 unsigned size;
3300
3301 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3302 if (size == 8)
3303 size = 4;
3304 return size;
3305}
3306
3307static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3308 unsigned size, bool sign_extension)
3309{
3310 struct decode_cache *c = &ctxt->decode;
3311 struct x86_emulate_ops *ops = ctxt->ops;
3312 int rc = X86EMUL_CONTINUE;
3313
3314 op->type = OP_IMM;
3315 op->bytes = size;
90de84f5 3316 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3317 /* NB. Immediates are sign-extended as necessary. */
3318 switch (op->bytes) {
3319 case 1:
3320 op->val = insn_fetch(s8, 1, c->eip);
3321 break;
3322 case 2:
3323 op->val = insn_fetch(s16, 2, c->eip);
3324 break;
3325 case 4:
3326 op->val = insn_fetch(s32, 4, c->eip);
3327 break;
3328 }
3329 if (!sign_extension) {
3330 switch (op->bytes) {
3331 case 1:
3332 op->val &= 0xff;
3333 break;
3334 case 2:
3335 op->val &= 0xffff;
3336 break;
3337 case 4:
3338 op->val &= 0xffffffff;
3339 break;
3340 }
3341 }
3342done:
3343 return rc;
3344}
3345
dde7e6d1 3346int
dc25e89e 3347x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3348{
3349 struct x86_emulate_ops *ops = ctxt->ops;
3350 struct decode_cache *c = &ctxt->decode;
3351 int rc = X86EMUL_CONTINUE;
3352 int mode = ctxt->mode;
46561646 3353 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3354 bool op_prefix = false;
46561646 3355 struct opcode opcode;
2dbd0dd7 3356 struct operand memop = { .type = OP_NONE };
dde7e6d1 3357
dde7e6d1 3358 c->eip = ctxt->eip;
dc25e89e
AP		 3359 c->fetch.start = c->eip;
3360 c->fetch.end = c->fetch.start + insn_len;
3361 if (insn_len > 0)
3362 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3363
3364 switch (mode) {
3365 case X86EMUL_MODE_REAL:
3366 case X86EMUL_MODE_VM86:
3367 case X86EMUL_MODE_PROT16:
3368 def_op_bytes = def_ad_bytes = 2;
3369 break;
3370 case X86EMUL_MODE_PROT32:
3371 def_op_bytes = def_ad_bytes = 4;
3372 break;
3373#ifdef CONFIG_X86_64
3374 case X86EMUL_MODE_PROT64:
3375 def_op_bytes = 4;
3376 def_ad_bytes = 8;
3377 break;
3378#endif
3379 default:
3380 return -1;
3381 }
3382
3383 c->op_bytes = def_op_bytes;
3384 c->ad_bytes = def_ad_bytes;
3385
3386 /* Legacy prefixes. */
3387 for (;;) {
3388 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3389 case 0x66: /* operand-size override */
0d7cdee8 3390 op_prefix = true;
dde7e6d1
AK		 3391 /* switch between 2/4 bytes */
3392 c->op_bytes = def_op_bytes ^ 6;
3393 break;
3394 case 0x67: /* address-size override */
3395 if (mode == X86EMUL_MODE_PROT64)
3396 /* switch between 4/8 bytes */
3397 c->ad_bytes = def_ad_bytes ^ 12;
3398 else
3399 /* switch between 2/4 bytes */
3400 c->ad_bytes = def_ad_bytes ^ 6;
3401 break;
3402 case 0x26: /* ES override */
3403 case 0x2e: /* CS override */
3404 case 0x36: /* SS override */
3405 case 0x3e: /* DS override */
3406 set_seg_override(c, (c->b >> 3) & 3);
3407 break;
3408 case 0x64: /* FS override */
3409 case 0x65: /* GS override */
3410 set_seg_override(c, c->b & 7);
3411 break;
3412 case 0x40 ... 0x4f: /* REX */
3413 if (mode != X86EMUL_MODE_PROT64)
3414 goto done_prefixes;
3415 c->rex_prefix = c->b;
3416 continue;
3417 case 0xf0: /* LOCK */
3418 c->lock_prefix = 1;
3419 break;
3420 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3421 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3422 c->rep_prefix = c->b;
dde7e6d1
AK		 3423 break;
3424 default:
3425 goto done_prefixes;
3426 }
3427
3428 /* Any legacy prefix after a REX prefix nullifies its effect. */
3429
3430 c->rex_prefix = 0;
3431 }
3432
3433done_prefixes:
3434
3435 /* REX prefix. */
1e87e3ef
AK		 3436 if (c->rex_prefix & 8)
3437 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3438
3439 /* Opcode byte(s). */
3440 opcode = opcode_table[c->b];
d3ad6243
WY		 3441 /* Two-byte opcode? */
3442 if (c->b == 0x0f) {
3443 c->twobyte = 1;
3444 c->b = insn_fetch(u8, 1, c->eip);
3445 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3446 }
3447 c->d = opcode.flags;
3448
46561646
AK		 3449 while (c->d & GroupMask) {
3450 switch (c->d & GroupMask) {
3451 case Group:
3452 c->modrm = insn_fetch(u8, 1, c->eip);
3453 --c->eip;
3454 goffset = (c->modrm >> 3) & 7;
3455 opcode = opcode.u.group[goffset];
3456 break;
3457 case GroupDual:
3458 c->modrm = insn_fetch(u8, 1, c->eip);
3459 --c->eip;
3460 goffset = (c->modrm >> 3) & 7;
3461 if ((c->modrm >> 6) == 3)
3462 opcode = opcode.u.gdual->mod3[goffset];
3463 else
3464 opcode = opcode.u.gdual->mod012[goffset];
3465 break;
3466 case RMExt:
01de8b09
JR		 3467 goffset = c->modrm & 7;
3468 opcode = opcode.u.group[goffset];
46561646
AK		 3469 break;
3470 case Prefix:
3471 if (c->rep_prefix && op_prefix)
3472 return X86EMUL_UNHANDLEABLE;
3473 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3474 switch (simd_prefix) {
3475 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3476 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3477 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3478 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3479 }
3480 break;
3481 default:
0d7cdee8 3482 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3483 }
46561646
AK		 3484
3485 c->d &= ~GroupMask;
0d7cdee8
AK		 3486 c->d |= opcode.flags;
3487 }
3488
dde7e6d1 3489 c->execute = opcode.u.execute;
d09beabd 3490 c->check_perm = opcode.check_perm;
c4f035c6 3491 c->intercept = opcode.intercept;
dde7e6d1
AK		 3492
3493 /* Unrecognised? */
d53db5ef 3494 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3495 return -1;
dde7e6d1 3496
d867162c
AK		 3497 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3498 return -1;
3499
dde7e6d1
AK		 3500 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3501 c->op_bytes = 8;
3502
7f9b4b75
AK		 3503 if (c->d & Op3264) {
3504 if (mode == X86EMUL_MODE_PROT64)
3505 c->op_bytes = 8;
3506 else
3507 c->op_bytes = 4;
3508 }
3509
1253791d
AK		 3510 if (c->d & Sse)
3511 c->op_bytes = 16;
3512
dde7e6d1 3513 /* ModRM and SIB bytes. */
09ee57cd 3514 if (c->d & ModRM) {
2dbd0dd7 3515 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3516 if (!c->has_seg_override)
3517 set_seg_override(c, c->modrm_seg);
3518 } else if (c->d & MemAbs)
2dbd0dd7 3519 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3520 if (rc != X86EMUL_CONTINUE)
3521 goto done;
3522
3523 if (!c->has_seg_override)
3524 set_seg_override(c, VCPU_SREG_DS);
3525
c1ed6dea 3526 memop.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1 3527
2dbd0dd7 3528 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3529 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3530
2dbd0dd7 3531 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3532 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3533
3534 /*
3535 * Decode and fetch the source operand: register, memory
3536 * or immediate.
3537 */
3538 switch (c->d & SrcMask) {
3539 case SrcNone:
3540 break;
3541 case SrcReg:
1253791d 3542 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3543 break;
3544 case SrcMem16:
2dbd0dd7 3545 memop.bytes = 2;
dde7e6d1
AK		 3546 goto srcmem_common;
3547 case SrcMem32:
2dbd0dd7 3548 memop.bytes = 4;
dde7e6d1
AK		 3549 goto srcmem_common;
3550 case SrcMem:
2dbd0dd7 3551 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3552 c->op_bytes;
dde7e6d1 3553 srcmem_common:
2dbd0dd7 3554 c->src = memop;
dde7e6d1 3555 break;
b250e605 3556 case SrcImmU16:
39f21ee5
AK		 3557 rc = decode_imm(ctxt, &c->src, 2, false);
3558 break;
dde7e6d1 3559 case SrcImm:
39f21ee5
AK		 3560 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3561 break;
dde7e6d1 3562 case SrcImmU:
39f21ee5 3563 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3564 break;
3565 case SrcImmByte:
39f21ee5
AK		 3566 rc = decode_imm(ctxt, &c->src, 1, true);
3567 break;
dde7e6d1 3568 case SrcImmUByte:
39f21ee5 3569 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3570 break;
3571 case SrcAcc:
3572 c->src.type = OP_REG;
3573 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3574 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3575 fetch_register_operand(&c->src);
dde7e6d1
AK		 3576 break;
3577 case SrcOne:
3578 c->src.bytes = 1;
3579 c->src.val = 1;
3580 break;
3581 case SrcSI:
3582 c->src.type = OP_MEM;
3583 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3584 c->src.addr.mem.ea =
3585 register_address(c, c->regs[VCPU_REGS_RSI]);
c1ed6dea 3586 c->src.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1
AK		 3587 c->src.val = 0;
3588 break;
3589 case SrcImmFAddr:
3590 c->src.type = OP_IMM;
90de84f5 3591 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3592 c->src.bytes = c->op_bytes + 2;
3593 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3594 break;
3595 case SrcMemFAddr:
2dbd0dd7
AK		 3596 memop.bytes = c->op_bytes + 2;
3597 goto srcmem_common;
dde7e6d1
AK		 3598 break;
3599 }
3600
39f21ee5
AK		 3601 if (rc != X86EMUL_CONTINUE)
3602 goto done;
3603
dde7e6d1
AK		 3604 /*
3605 * Decode and fetch the second source operand: register, memory
3606 * or immediate.
3607 */
3608 switch (c->d & Src2Mask) {
3609 case Src2None:
3610 break;
3611 case Src2CL:
3612 c->src2.bytes = 1;
3613 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3614 break;
3615 case Src2ImmByte:
39f21ee5 3616 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3617 break;
3618 case Src2One:
3619 c->src2.bytes = 1;
3620 c->src2.val = 1;
3621 break;
7db41eb7
AK		 3622 case Src2Imm:
3623 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3624 break;
dde7e6d1
AK		 3625 }
3626
39f21ee5
AK		 3627 if (rc != X86EMUL_CONTINUE)
3628 goto done;
3629
dde7e6d1
AK		 3630 /* Decode and fetch the destination operand: register or memory. */
3631 switch (c->d & DstMask) {
dde7e6d1 3632 case DstReg:
1253791d 3633 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3634 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3635 break;
943858e2
WY		 3636 case DstImmUByte:
3637 c->dst.type = OP_IMM;
90de84f5 3638 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3639 c->dst.bytes = 1;
3640 c->dst.val = insn_fetch(u8, 1, c->eip);
3641 break;
dde7e6d1
AK		 3642 case DstMem:
3643 case DstMem64:
2dbd0dd7 3644 c->dst = memop;
dde7e6d1
AK		 3645 if ((c->d & DstMask) == DstMem64)
3646 c->dst.bytes = 8;
3647 else
3648 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3649 if (c->d & BitOp)
3650 fetch_bit_operand(c);
2dbd0dd7 3651 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3652 break;
3653 case DstAcc:
3654 c->dst.type = OP_REG;
3655 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3656 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3657 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3658 c->dst.orig_val = c->dst.val;
3659 break;
3660 case DstDI:
3661 c->dst.type = OP_MEM;
3662 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3663 c->dst.addr.mem.ea =
3664 register_address(c, c->regs[VCPU_REGS_RDI]);
3665 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3666 c->dst.val = 0;
3667 break;
36089fed
WY		 3668 case ImplicitOps:
3669 /* Special instructions do their own operand decoding. */
3670 default:
3671 c->dst.type = OP_NONE; /* Disable writeback. */
3672 return 0;
dde7e6d1
AK		 3673 }
3674
3675done:
a0c0ab2f 3676 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3677}
3678
3e2f65d5
GN		 3679static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3680{
3681 struct decode_cache *c = &ctxt->decode;
3682
3683 /* The second termination condition only applies for REPE
3684 * and REPNE. Test if the repeat string operation prefix is
3685 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3686 * corresponding termination condition according to:
3687 * - if REPE/REPZ and ZF = 0 then done
3688 * - if REPNE/REPNZ and ZF = 1 then done
3689 */
3690 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3691 (c->b == 0xae) || (c->b == 0xaf))
3692 && (((c->rep_prefix == REPE_PREFIX) &&
3693 ((ctxt->eflags & EFLG_ZF) == 0))
3694 || ((c->rep_prefix == REPNE_PREFIX) &&
3695 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3696 return true;
3697
3698 return false;
3699}
3700
8b4caf66 3701int
9aabc88f 3702x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3703{
9aabc88f 3704 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3705 u64 msr_data;
8b4caf66 3706 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3707 int rc = X86EMUL_CONTINUE;
5cd21917 3708 int saved_dst_type = c->dst.type;
6e154e56 3709 int irq; /* Used for int 3, int, and into */
8b4caf66 3710
9de41573 3711 ctxt->decode.mem_read.pos = 0;
310b5d30 3712
1161624f 3713 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3714 rc = emulate_ud(ctxt);
1161624f
GN		 3715 goto done;
3716 }
3717
d380a5e4 3718 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3719 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3720 rc = emulate_ud(ctxt);
d380a5e4
GN		 3721 goto done;
3722 }
3723
081bca0e 3724 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3725 rc = emulate_ud(ctxt);
081bca0e
AK		 3726 goto done;
3727 }
3728
1253791d 3729 if ((c->d & Sse)
717746e3
AK		 3730 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3731 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3732 rc = emulate_ud(ctxt);
3733 goto done;
3734 }
3735
717746e3 3736 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3737 rc = emulate_nm(ctxt);
3738 goto done;
3739 }
3740
c4f035c6 3741 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3742 rc = emulator_check_intercept(ctxt, c->intercept,
3743 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3744 if (rc != X86EMUL_CONTINUE)
3745 goto done;
3746 }
3747
e92805ac 3748 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3749 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3750 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3751 goto done;
3752 }
3753
8ea7d6ae
JR		 3754 /* Instruction can only be executed in protected mode */
3755 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3756 rc = emulate_ud(ctxt);
3757 goto done;
3758 }
3759
d09beabd
JR		 3760 /* Do instruction specific permission checks */
3761 if (c->check_perm) {
3762 rc = c->check_perm(ctxt);
3763 if (rc != X86EMUL_CONTINUE)
3764 goto done;
3765 }
3766
c4f035c6 3767 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3768 rc = emulator_check_intercept(ctxt, c->intercept,
3769 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3770 if (rc != X86EMUL_CONTINUE)
3771 goto done;
3772 }
3773
b9fa9d6b
AK		 3774 if (c->rep_prefix && (c->d & String)) {
3775 /* All REP prefixes have the same first termination condition */
c73e197b 3776 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3777 ctxt->eip = c->eip;
b9fa9d6b
AK		 3778 goto done;
3779 }
b9fa9d6b
AK		 3780 }
3781
c483c02a 3782 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3783 rc = segmented_read(ctxt, c->src.addr.mem,
3784 c->src.valptr, c->src.bytes);
b60d513c 3785 if (rc != X86EMUL_CONTINUE)
8b4caf66 3786 goto done;
16518d5a 3787 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3788 }
3789
e35b7b9c 3790 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3791 rc = segmented_read(ctxt, c->src2.addr.mem,
3792 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3793 if (rc != X86EMUL_CONTINUE)
3794 goto done;
3795 }
3796
8b4caf66
LV		 3797 if ((c->d & DstMask) == ImplicitOps)
3798 goto special_insn;
3799
3800
69f55cb1
GN		 3801 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3802 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3803 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3804 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3805 if (rc != X86EMUL_CONTINUE)
3806 goto done;
038e51de 3807 }
e4e03ded 3808 c->dst.orig_val = c->dst.val;
038e51de 3809
018a98db
AK		 3810special_insn:
3811
c4f035c6 3812 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3813 rc = emulator_check_intercept(ctxt, c->intercept,
3814 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3815 if (rc != X86EMUL_CONTINUE)
3816 goto done;
3817 }
3818
ef65c889
AK		 3819 if (c->execute) {
3820 rc = c->execute(ctxt);
3821 if (rc != X86EMUL_CONTINUE)
3822 goto done;
3823 goto writeback;
3824 }
3825
e4e03ded 3826 if (c->twobyte)
6aa8b732
AK		 3827 goto twobyte_insn;
3828
e4e03ded 3829 switch (c->b) {
0934ac9d 3830 case 0x06: /* push es */
4179bb02 3831 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3832 break;
3833 case 0x07: /* pop es */
0934ac9d 3834 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3835 break;
0934ac9d 3836 case 0x0e: /* push cs */
4179bb02 3837 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3838 break;
0934ac9d 3839 case 0x16: /* push ss */
4179bb02 3840 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3841 break;
3842 case 0x17: /* pop ss */
0934ac9d 3843 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3844 break;
0934ac9d 3845 case 0x1e: /* push ds */
4179bb02 3846 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3847 break;
3848 case 0x1f: /* pop ds */
0934ac9d 3849 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3850 break;
33615aa9
AK		 3851 case 0x40 ... 0x47: /* inc r16/r32 */
3852 emulate_1op("inc", c->dst, ctxt->eflags);
3853 break;
3854 case 0x48 ... 0x4f: /* dec r16/r32 */
3855 emulate_1op("dec", c->dst, ctxt->eflags);
3856 break;
6aa8b732 3857 case 0x63: /* movsxd */
8b4caf66 3858 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3859 goto cannot_emulate;
e4e03ded 3860 c->dst.val = (s32) c->src.val;
6aa8b732 3861 break;
018a98db
AK		 3862 case 0x6c: /* insb */
3863 case 0x6d: /* insw/insd */
a13a63fa
WY		 3864 c->src.val = c->regs[VCPU_REGS_RDX];
3865 goto do_io_in;
018a98db
AK		 3866 case 0x6e: /* outsb */
3867 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3868 c->dst.val = c->regs[VCPU_REGS_RDX];
3869 goto do_io_out;
7972995b 3870 break;
b2833e3c 3871 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3872 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3873 jmp_rel(c, c->src.val);
018a98db 3874 break;
6aa8b732 3875 case 0x84 ... 0x85:
dfb507c4 3876 test:
05f086f8 3877 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3878 break;
3879 case 0x86 ... 0x87: /* xchg */
b13354f8 3880 xchg:
6aa8b732 3881 /* Write back the register source. */
31be40b3
WY		 3882 c->src.val = c->dst.val;
3883 write_register_operand(&c->src);
6aa8b732
AK		 3884 /*
3885 * Write back the memory destination with implicit LOCK
3886 * prefix.
3887 */
31be40b3 3888 c->dst.val = c->src.orig_val;
e4e03ded 3889 c->lock_prefix = 1;
6aa8b732 3890 break;
79168fd1
GN		 3891 case 0x8c: /* mov r/m, sreg */
3892 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3893 rc = emulate_ud(ctxt);
5e3ae6c5 3894 goto done;
38d5bc6d 3895 }
1aa36616 3896 c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3897 break;
7e0b54b1 3898 case 0x8d: /* lea r16/r32, m */
90de84f5 3899 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3900 break;
4257198a
GT		 3901 case 0x8e: { /* mov seg, r/m16 */
3902 uint16_t sel;
4257198a
GT		 3903
3904 sel = c->src.val;
8b9f4414 3905
c697518a
GN		 3906 if (c->modrm_reg == VCPU_SREG_CS ||
3907 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3908 rc = emulate_ud(ctxt);
8b9f4414
GN		 3909 goto done;
3910 }
3911
310b5d30 3912 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3913 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3914
2e873022 3915 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3916
3917 c->dst.type = OP_NONE; /* Disable writeback. */
3918 break;
3919 }
6aa8b732 3920 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3921 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3922 break;
3d9e77df
AK		 3923 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3924 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3925 break;
b13354f8 3926 goto xchg;
e8b6fa70
WY		 3927 case 0x98: /* cbw/cwde/cdqe */
3928 switch (c->op_bytes) {
3929 case 2: c->dst.val = (s8)c->dst.val; break;
3930 case 4: c->dst.val = (s16)c->dst.val; break;
3931 case 8: c->dst.val = (s32)c->dst.val; break;
3932 }
3933 break;
dfb507c4
MG		 3934 case 0xa8 ... 0xa9: /* test ax, imm */
3935 goto test;
018a98db
AK		 3936 case 0xc0 ... 0xc1:
3937 emulate_grp2(ctxt);
3938 break;
111de5d6 3939 case 0xc3: /* ret */
cf5de4f8 3940 c->dst.type = OP_REG;
1a6440ae 3941 c->dst.addr.reg = &c->eip;
cf5de4f8 3942 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3943 rc = em_pop(ctxt);
3944 break;
09b5f4d3
WY		 3945 case 0xc4: /* les */
3946 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3947 break;
3948 case 0xc5: /* lds */
3949 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3950 break;
a77ab5ea
AK		 3951 case 0xcb: /* ret far */
3952 rc = emulate_ret_far(ctxt, ops);
62bd430e 3953 break;
6e154e56
MG		 3954 case 0xcc: /* int3 */
3955 irq = 3;
3956 goto do_interrupt;
3957 case 0xcd: /* int n */
3958 irq = c->src.val;
3959 do_interrupt:
3960 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3961 break;
3962 case 0xce: /* into */
3963 if (ctxt->eflags & EFLG_OF) {
3964 irq = 4;
3965 goto do_interrupt;
3966 }
3967 break;
62bd430e
MG		 3968 case 0xcf: /* iret */
3969 rc = emulate_iret(ctxt, ops);
a77ab5ea 3970 break;
018a98db 3971 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3972 emulate_grp2(ctxt);
3973 break;
3974 case 0xd2 ... 0xd3: /* Grp2 */
3975 c->src.val = c->regs[VCPU_REGS_RCX];
3976 emulate_grp2(ctxt);
3977 break;
f2f31845
WY		 3978 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3979 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3980 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3981 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3982 jmp_rel(c, c->src.val);
3983 break;
e4abac67
WY		 3984 case 0xe3: /* jcxz/jecxz/jrcxz */
3985 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3986 jmp_rel(c, c->src.val);
3987 break;
a6a3034c
MG		 3988 case 0xe4: /* inb */
3989 case 0xe5: /* in */
cf8f70bf 3990 goto do_io_in;
a6a3034c
MG		 3991 case 0xe6: /* outb */
3992 case 0xe7: /* out */
cf8f70bf 3993 goto do_io_out;
1a52e051 3994 case 0xe8: /* call (near) */ {
d53c4777 3995 long int rel = c->src.val;
e4e03ded 3996 c->src.val = (unsigned long) c->eip;
7a957275 3997 jmp_rel(c, rel);
4487b3b4 3998 rc = em_push(ctxt);
8cdbd2c9 3999 break;
1a52e051
NK		 4000 }
4001 case 0xe9: /* jmp rel */
954cd36f 4002 goto jmp;
414e6277
GN		 4003 case 0xea: { /* jmp far */
4004 unsigned short sel;
ea79849d 4005 jump_far:
414e6277
GN		 4006 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
4007
4947e7cd
GN		 4008 rc = load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS);
4009 if (rc != X86EMUL_CONTINUE)
c697518a 4010 goto done;
954cd36f 4011
414e6277
GN		 4012 c->eip = 0;
4013 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 4014 break;
414e6277 4015 }
954cd36f
GT		 4016 case 0xeb:
4017 jmp: /* jmp rel short */
7a957275 4018 jmp_rel(c, c->src.val);
a01af5ec 4019 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4020 break;
a6a3034c
MG		 4021 case 0xec: /* in al,dx */
4022 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 4023 c->src.val = c->regs[VCPU_REGS_RDX];
4024 do_io_in:
7b262e90
GN		 4025 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4026 &c->dst.val))
cf8f70bf
GN		 4027 goto done; /* IO is needed */
4028 break;
ce7a0ad3
WY		 4029 case 0xee: /* out dx,al */
4030 case 0xef: /* out dx,(e/r)ax */
41167be5 4031 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 4032 do_io_out:
ca1d4a9e
AK		 4033 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4034 &c->src.val, 1);
cf8f70bf 4035 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4036 break;
111de5d6 4037 case 0xf4: /* hlt */
6c3287f7 4038 ctxt->ops->halt(ctxt);
19fdfa0d 4039 break;
111de5d6
AK		 4040 case 0xf5: /* cmc */
4041 /* complement carry flag from eflags reg */
4042 ctxt->eflags ^= EFLG_CF;
111de5d6 4043 break;
018a98db 4044 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 4045 rc = emulate_grp3(ctxt, ops);
018a98db 4046 break;
111de5d6
AK		 4047 case 0xf8: /* clc */
4048 ctxt->eflags &= ~EFLG_CF;
111de5d6 4049 break;
8744aa9a
MG		 4050 case 0xf9: /* stc */
4051 ctxt->eflags |= EFLG_CF;
4052 break;
111de5d6 4053 case 0xfa: /* cli */
07cbc6c1 4054 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4055 rc = emulate_gp(ctxt, 0);
07cbc6c1 4056 goto done;
36089fed 4057 } else
f850e2e6 4058 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4059 break;
4060 case 0xfb: /* sti */
07cbc6c1 4061 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4062 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4063 goto done;
4064 } else {
95cb2295 4065 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4066 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4067 }
111de5d6 4068 break;
fb4616f4
MG		 4069 case 0xfc: /* cld */
4070 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4071 break;
4072 case 0xfd: /* std */
4073 ctxt->eflags |= EFLG_DF;
fb4616f4 4074 break;
ea79849d
GN		 4075 case 0xfe: /* Grp4 */
4076 grp45:
4487b3b4 4077 rc = emulate_grp45(ctxt);
018a98db 4078 break;
ea79849d
GN		 4079 case 0xff: /* Grp5 */
4080 if (c->modrm_reg == 5)
4081 goto jump_far;
4082 goto grp45;
91269b8f
AK		 4083 default:
4084 goto cannot_emulate;
6aa8b732 4085 }
018a98db 4086
7d9ddaed
AK		 4087 if (rc != X86EMUL_CONTINUE)
4088 goto done;
4089
018a98db 4090writeback:
adddcecf 4091 rc = writeback(ctxt);
1b30eaa8 4092 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4093 goto done;
4094
5cd21917
GN		 4095 /*
4096 * restore dst type in case the decoding will be reused
4097 * (happens for string instruction )
4098 */
4099 c->dst.type = saved_dst_type;
4100
a682e354 4101 if ((c->d & SrcMask) == SrcSI)
c1ed6dea 4102 string_addr_inc(ctxt, seg_override(ctxt, c),
79168fd1 4103 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4104
4105 if ((c->d & DstMask) == DstDI)
90de84f5 4106 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4107 &c->dst);
d9271123 4108
5cd21917 4109 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4110 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4111 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4112
d2ddd1c4
GN		 4113 if (!string_insn_completed(ctxt)) {
4114 /*
4115 * Re-enter guest when pio read ahead buffer is empty
4116 * or, if it is not used, after each 1024 iteration.
4117 */
4118 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4119 (r->end == 0 || r->end != r->pos)) {
4120 /*
4121 * Reset read cache. Usually happens before
4122 * decode, but since instruction is restarted
4123 * we have to do it here.
4124 */
4125 ctxt->decode.mem_read.end = 0;
4126 return EMULATION_RESTART;
4127 }
4128 goto done; /* skip rip writeback */
0fa6ccbd 4129 }
5cd21917 4130 }
d2ddd1c4
GN		 4131
4132 ctxt->eip = c->eip;
018a98db
AK		 4133
4134done:
da9cb575
AK		 4135 if (rc == X86EMUL_PROPAGATE_FAULT)
4136 ctxt->have_exception = true;
775fde86
JR		 4137 if (rc == X86EMUL_INTERCEPTED)
4138 return EMULATION_INTERCEPTED;
4139
d2ddd1c4 4140 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4141
4142twobyte_insn:
e4e03ded 4143 switch (c->b) {
e99f0507 4144 case 0x05: /* syscall */
3fb1b5db 4145 rc = emulate_syscall(ctxt, ops);
e99f0507 4146 break;
018a98db 4147 case 0x06:
2d04a05b 4148 rc = em_clts(ctxt);
018a98db 4149 break;
018a98db 4150 case 0x09: /* wbinvd */
cfb22375 4151 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4152 break;
4153 case 0x08: /* invd */
018a98db
AK		 4154 case 0x0d: /* GrpP (prefetch) */
4155 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4156 break;
4157 case 0x20: /* mov cr, reg */
717746e3 4158 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4159 break;
6aa8b732 4160 case 0x21: /* mov from dr to reg */
717746e3 4161 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4162 break;
018a98db 4163 case 0x22: /* mov reg, cr */
717746e3 4164 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4165 emulate_gp(ctxt, 0);
da9cb575 4166 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4167 goto done;
4168 }
018a98db
AK		 4169 c->dst.type = OP_NONE;
4170 break;
6aa8b732 4171 case 0x23: /* mov from reg to dr */
717746e3 4172 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4173 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4174 ~0ULL : ~0U)) < 0) {
338dbc97 4175 /* #UD condition is already handled by the code above */
54b8486f 4176 emulate_gp(ctxt, 0);
da9cb575 4177 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4178 goto done;
4179 }
4180
a01af5ec 4181 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4182 break;
018a98db
AK		 4183 case 0x30:
4184 /* wrmsr */
4185 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4186 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4187 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4188 emulate_gp(ctxt, 0);
da9cb575 4189 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4190 goto done;
018a98db
AK		 4191 }
4192 rc = X86EMUL_CONTINUE;
018a98db
AK		 4193 break;
4194 case 0x32:
4195 /* rdmsr */
717746e3 4196 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4197 emulate_gp(ctxt, 0);
da9cb575 4198 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4199 goto done;
018a98db
AK		 4200 } else {
4201 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4202 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4203 }
4204 rc = X86EMUL_CONTINUE;
018a98db 4205 break;
e99f0507 4206 case 0x34: /* sysenter */
3fb1b5db 4207 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4208 break;
4209 case 0x35: /* sysexit */
3fb1b5db 4210 rc = emulate_sysexit(ctxt, ops);
e99f0507 4211 break;
6aa8b732 4212 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4213 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4214 if (!test_cc(c->b, ctxt->eflags))
4215 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4216 break;
b2833e3c 4217 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4218 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4219 jmp_rel(c, c->src.val);
018a98db 4220 break;
ee45b58e
WY		 4221 case 0x90 ... 0x9f: /* setcc r/m8 */
4222 c->dst.val = test_cc(c->b, ctxt->eflags);
4223 break;
0934ac9d 4224 case 0xa0: /* push fs */
4179bb02 4225 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4226 break;
4227 case 0xa1: /* pop fs */
4228 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4229 break;
7de75248
NK		 4230 case 0xa3:
4231 bt: /* bt */
e4f8e039 4232 c->dst.type = OP_NONE;
e4e03ded
LV		 4233 /* only subword offset */
4234 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4235 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4236 break;
9bf8ea42
GT		 4237 case 0xa4: /* shld imm8, r, r/m */
4238 case 0xa5: /* shld cl, r, r/m */
4239 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4240 break;
0934ac9d 4241 case 0xa8: /* push gs */
4179bb02 4242 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4243 break;
4244 case 0xa9: /* pop gs */
4245 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4246 break;
7de75248
NK		 4247 case 0xab:
4248 bts: /* bts */
05f086f8 4249 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4250 break;
9bf8ea42
GT		 4251 case 0xac: /* shrd imm8, r, r/m */
4252 case 0xad: /* shrd cl, r, r/m */
4253 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4254 break;
2a7c5b8b
GC		 4255 case 0xae: /* clflush */
4256 break;
6aa8b732
AK		 4257 case 0xb0 ... 0xb1: /* cmpxchg */
4258 /*
4259 * Save real source value, then compare EAX against
4260 * destination.
4261 */
e4e03ded
LV		 4262 c->src.orig_val = c->src.val;
4263 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4264 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4265 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4266 /* Success: write back to memory. */
e4e03ded 4267 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4268 } else {
4269 /* Failure: write the value we saw to EAX. */
e4e03ded 4270 c->dst.type = OP_REG;
1a6440ae 4271 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4272 }
4273 break;
09b5f4d3
WY		 4274 case 0xb2: /* lss */
4275 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4276 break;
6aa8b732
AK		 4277 case 0xb3:
4278 btr: /* btr */
05f086f8 4279 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4280 break;
09b5f4d3
WY		 4281 case 0xb4: /* lfs */
4282 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4283 break;
4284 case 0xb5: /* lgs */
4285 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4286 break;
6aa8b732 4287 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4288 c->dst.bytes = c->op_bytes;
4289 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4290 : (u16) c->src.val;
6aa8b732 4291 break;
6aa8b732 4292 case 0xba: /* Grp8 */
e4e03ded 4293 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4294 case 0:
4295 goto bt;
4296 case 1:
4297 goto bts;
4298 case 2:
4299 goto btr;
4300 case 3:
4301 goto btc;
4302 }
4303 break;
7de75248
NK		 4304 case 0xbb:
4305 btc: /* btc */
05f086f8 4306 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4307 break;
d9574a25
WY		 4308 case 0xbc: { /* bsf */
4309 u8 zf;
4310 __asm__ ("bsf %2, %0; setz %1"
4311 : "=r"(c->dst.val), "=q"(zf)
4312 : "r"(c->src.val));
4313 ctxt->eflags &= ~X86_EFLAGS_ZF;
4314 if (zf) {
4315 ctxt->eflags |= X86_EFLAGS_ZF;
4316 c->dst.type = OP_NONE; /* Disable writeback. */
4317 }
4318 break;
4319 }
4320 case 0xbd: { /* bsr */
4321 u8 zf;
4322 __asm__ ("bsr %2, %0; setz %1"
4323 : "=r"(c->dst.val), "=q"(zf)
4324 : "r"(c->src.val));
4325 ctxt->eflags &= ~X86_EFLAGS_ZF;
4326 if (zf) {
4327 ctxt->eflags |= X86_EFLAGS_ZF;
4328 c->dst.type = OP_NONE; /* Disable writeback. */
4329 }
4330 break;
4331 }
6aa8b732 4332 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4333 c->dst.bytes = c->op_bytes;
4334 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4335 (s16) c->src.val;
6aa8b732 4336 break;
92f738a5
WY		 4337 case 0xc0 ... 0xc1: /* xadd */
4338 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4339 /* Write back the register source. */
4340 c->src.val = c->dst.orig_val;
4341 write_register_operand(&c->src);
4342 break;
a012e65a 4343 case 0xc3: /* movnti */
e4e03ded
LV		 4344 c->dst.bytes = c->op_bytes;
4345 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4346 (u64) c->src.val;
a012e65a 4347 break;
6aa8b732 4348 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4349 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4350 break;
91269b8f
AK		 4351 default:
4352 goto cannot_emulate;
6aa8b732 4353 }
7d9ddaed
AK		 4354
4355 if (rc != X86EMUL_CONTINUE)
4356 goto done;
4357
6aa8b732
AK		 4358 goto writeback;
4359
4360cannot_emulate:
a0c0ab2f 4361 return EMULATION_FAILED;
6aa8b732 4362}
Linux kernel - Deliverables
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