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KVM: VMX: fix incorrect cached cpl value with real/v8086 modes
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
5e2c6883 46#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 61#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 62
63#define OpBits 5 /* Width of operand field */
b1ea50b2 64#define OpMask ((1ull << OpBits) - 1)
a9945549 65
6aa8b732
AK		 66/*
67 * Opcode effective-address decode tables.
68 * Note that we only emulate instructions that have at least one memory
69 * operand (excluding implicit stack references). We assume that stack
70 * references and instruction fetches will never occur in special memory
71 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
72 * not be handled.
73 */
74
75/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 76#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 77/* Destination operand type. */
a9945549
AK		 78#define DstShift 1
79#define ImplicitOps (OpImplicit << DstShift)
80#define DstReg (OpReg << DstShift)
81#define DstMem (OpMem << DstShift)
82#define DstAcc (OpAcc << DstShift)
83#define DstDI (OpDI << DstShift)
84#define DstMem64 (OpMem64 << DstShift)
85#define DstImmUByte (OpImmUByte << DstShift)
86#define DstDX (OpDX << DstShift)
87#define DstMask (OpMask << DstShift)
6aa8b732 88/* Source operand type. */
0fe59128
AK		 89#define SrcShift 6
90#define SrcNone (OpNone << SrcShift)
91#define SrcReg (OpReg << SrcShift)
92#define SrcMem (OpMem << SrcShift)
93#define SrcMem16 (OpMem16 << SrcShift)
94#define SrcMem32 (OpMem32 << SrcShift)
95#define SrcImm (OpImm << SrcShift)
96#define SrcImmByte (OpImmByte << SrcShift)
97#define SrcOne (OpOne << SrcShift)
98#define SrcImmUByte (OpImmUByte << SrcShift)
99#define SrcImmU (OpImmU << SrcShift)
100#define SrcSI (OpSI << SrcShift)
101#define SrcImmFAddr (OpImmFAddr << SrcShift)
102#define SrcMemFAddr (OpMemFAddr << SrcShift)
103#define SrcAcc (OpAcc << SrcShift)
104#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 105#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 106#define SrcDX (OpDX << SrcShift)
28867cee 107#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 108#define SrcMask (OpMask << SrcShift)
221192bd
MT		 109#define BitOp (1<<11)
110#define MemAbs (1<<12) /* Memory operand is absolute displacement */
111#define String (1<<13) /* String instruction (rep capable) */
112#define Stack (1<<14) /* Stack instruction (push/pop) */
113#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
114#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
115#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
116#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
117#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 118#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 119#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 120/* Generic ModRM decode. */
121#define ModRM (1<<19)
122/* Destination is only written; never read. */
123#define Mov (1<<20)
d8769fed 124/* Misc flags */
8ea7d6ae 125#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 126#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 127#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 128#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 129#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 130#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 131#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 132#define No64 (1<<28)
d5ae7ce8 133#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 134/* Source 2 operand type */
d5ae7ce8 135#define Src2Shift (30)
4dd6a57d
AK		 136#define Src2None (OpNone << Src2Shift)
137#define Src2CL (OpCL << Src2Shift)
138#define Src2ImmByte (OpImmByte << Src2Shift)
139#define Src2One (OpOne << Src2Shift)
140#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 141#define Src2ES (OpES << Src2Shift)
142#define Src2CS (OpCS << Src2Shift)
143#define Src2SS (OpSS << Src2Shift)
144#define Src2DS (OpDS << Src2Shift)
145#define Src2FS (OpFS << Src2Shift)
146#define Src2GS (OpGS << Src2Shift)
4dd6a57d 147#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 148#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 149#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
150#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
151#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 152
d0e53325
AK		 153#define X2(x...) x, x
154#define X3(x...) X2(x), x
155#define X4(x...) X2(x), X2(x)
156#define X5(x...) X4(x), x
157#define X6(x...) X4(x), X2(x)
158#define X7(x...) X4(x), X3(x)
159#define X8(x...) X4(x), X4(x)
160#define X16(x...) X8(x), X8(x)
83babbca 161
d65b1dee 162struct opcode {
b1ea50b2
AK		 163 u64 flags : 56;
164 u64 intercept : 8;
120df890 165 union {
ef65c889 166 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 167 const struct opcode *group;
168 const struct group_dual *gdual;
169 const struct gprefix *gprefix;
045a282c 170 const struct escape *esc;
120df890 171 } u;
d09beabd 172 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 173};
174
175struct group_dual {
176 struct opcode mod012[8];
177 struct opcode mod3[8];
d65b1dee
AK		 178};
179
0d7cdee8
AK		 180struct gprefix {
181 struct opcode pfx_no;
182 struct opcode pfx_66;
183 struct opcode pfx_f2;
184 struct opcode pfx_f3;
185};
186
045a282c
GN		 187struct escape {
188 struct opcode op[8];
189 struct opcode high[64];
190};
191
6aa8b732 192/* EFLAGS bit definitions. */
d4c6a154
GN		 193#define EFLG_ID (1<<21)
194#define EFLG_VIP (1<<20)
195#define EFLG_VIF (1<<19)
196#define EFLG_AC (1<<18)
b1d86143
AP		 197#define EFLG_VM (1<<17)
198#define EFLG_RF (1<<16)
d4c6a154
GN		 199#define EFLG_IOPL (3<<12)
200#define EFLG_NT (1<<14)
6aa8b732
AK		 201#define EFLG_OF (1<<11)
202#define EFLG_DF (1<<10)
b1d86143 203#define EFLG_IF (1<<9)
d4c6a154 204#define EFLG_TF (1<<8)
6aa8b732
AK		 205#define EFLG_SF (1<<7)
206#define EFLG_ZF (1<<6)
207#define EFLG_AF (1<<4)
208#define EFLG_PF (1<<2)
209#define EFLG_CF (1<<0)
210
62bd430e
MG		 211#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
212#define EFLG_RESERVED_ONE_MASK 2
213
dd856efa
AK		 214static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
215{
216 if (!(ctxt->regs_valid & (1 << nr))) {
217 ctxt->regs_valid |= 1 << nr;
218 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
219 }
220 return ctxt->_regs[nr];
221}
222
223static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
224{
225 ctxt->regs_valid |= 1 << nr;
226 ctxt->regs_dirty |= 1 << nr;
227 return &ctxt->_regs[nr];
228}
229
230static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
231{
232 reg_read(ctxt, nr);
233 return reg_write(ctxt, nr);
234}
235
236static void writeback_registers(struct x86_emulate_ctxt *ctxt)
237{
238 unsigned reg;
239
240 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
241 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
242}
243
244static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
245{
246 ctxt->regs_dirty = 0;
247 ctxt->regs_valid = 0;
248}
249
6aa8b732
AK		 250/*
251 * Instruction emulation:
252 * Most instructions are emulated directly via a fragment of inline assembly
253 * code. This allows us to save/restore EFLAGS and thus very easily pick up
254 * any modified flags.
255 */
256
05b3e0c2 257#if defined(CONFIG_X86_64)
6aa8b732
AK		 258#define _LO32 "k" /* force 32-bit operand */
259#define _STK "%%rsp" /* stack pointer */
260#elif defined(__i386__)
261#define _LO32 "" /* force 32-bit operand */
262#define _STK "%%esp" /* stack pointer */
263#endif
264
265/*
266 * These EFLAGS bits are restored from saved value during emulation, and
267 * any changes are written back to the saved value after emulation.
268 */
269#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
270
271/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 272#define _PRE_EFLAGS(_sav, _msk, _tmp) \
273 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
274 "movl %"_sav",%"_LO32 _tmp"; " \
275 "push %"_tmp"; " \
276 "push %"_tmp"; " \
277 "movl %"_msk",%"_LO32 _tmp"; " \
278 "andl %"_LO32 _tmp",("_STK"); " \
279 "pushf; " \
280 "notl %"_LO32 _tmp"; " \
281 "andl %"_LO32 _tmp",("_STK"); " \
282 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
283 "pop %"_tmp"; " \
284 "orl %"_LO32 _tmp",("_STK"); " \
285 "popf; " \
286 "pop %"_sav"; "
6aa8b732
AK		 287
288/* After executing instruction: write-back necessary bits in EFLAGS. */
289#define _POST_EFLAGS(_sav, _msk, _tmp) \
290 /* _sav |= EFLAGS & _msk; */ \
291 "pushf; " \
292 "pop %"_tmp"; " \
293 "andl %"_msk",%"_LO32 _tmp"; " \
294 "orl %"_LO32 _tmp",%"_sav"; "
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
a31b9cea 302#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 303 do { \
304 __asm__ __volatile__ ( \
305 _PRE_EFLAGS("0", "4", "2") \
306 _op _suffix " %"_x"3,%1; " \
307 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 308 : "=m" ((ctxt)->eflags), \
309 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 310 "=&r" (_tmp) \
a31b9cea 311 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 312 } while (0)
6b7ad61f
AK		 313
314
6aa8b732 315/* Raw emulation: instruction has two explicit operands. */
a31b9cea 316#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 317 do { \
318 unsigned long _tmp; \
319 \
a31b9cea 320 switch ((ctxt)->dst.bytes) { \
6b7ad61f 321 case 2: \
a31b9cea 322 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 323 break; \
324 case 4: \
a31b9cea 325 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 326 break; \
327 case 8: \
a31b9cea 328 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 329 break; \
330 } \
6aa8b732
AK		 331 } while (0)
332
a31b9cea 333#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 334 do { \
6b7ad61f 335 unsigned long _tmp; \
a31b9cea 336 switch ((ctxt)->dst.bytes) { \
6aa8b732 337 case 1: \
a31b9cea 338 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 339 break; \
340 default: \
a31b9cea 341 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 342 _wx, _wy, _lx, _ly, _qx, _qy); \
343 break; \
344 } \
345 } while (0)
346
347/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 348#define emulate_2op_SrcB(ctxt, _op) \
349 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 350
351/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 352#define emulate_2op_SrcV(ctxt, _op) \
353 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 354
355/* Source operand is word, long or quad sized. */
a31b9cea
AK		 356#define emulate_2op_SrcV_nobyte(ctxt, _op) \
357 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 358
d175226a 359/* Instruction has three operands and one operand is stored in ECX register */
29053a60 360#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 361 do { \
362 unsigned long _tmp; \
761441b9
AK		 363 _type _clv = (ctxt)->src2.val; \
364 _type _srcv = (ctxt)->src.val; \
365 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 366 \
367 __asm__ __volatile__ ( \
368 _PRE_EFLAGS("0", "5", "2") \
369 _op _suffix " %4,%1 \n" \
370 _POST_EFLAGS("0", "5", "2") \
761441b9 371 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 372 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
373 ); \
374 \
761441b9
AK		 375 (ctxt)->src2.val = (unsigned long) _clv; \
376 (ctxt)->src2.val = (unsigned long) _srcv; \
377 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 378 } while (0)
379
761441b9 380#define emulate_2op_cl(ctxt, _op) \
7295261c 381 do { \
761441b9 382 switch ((ctxt)->dst.bytes) { \
7295261c 383 case 2: \
29053a60 384 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 385 break; \
386 case 4: \
29053a60 387 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 388 break; \
389 case 8: \
29053a60 390 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 391 break; \
392 } \
d175226a
GT		 393 } while (0)
394
d1eef45d 395#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 396 do { \
397 unsigned long _tmp; \
398 \
dda96d8f
AK		 399 __asm__ __volatile__ ( \
400 _PRE_EFLAGS("0", "3", "2") \
401 _op _suffix " %1; " \
402 _POST_EFLAGS("0", "3", "2") \
d1eef45d 403 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 404 "=&r" (_tmp) \
405 : "i" (EFLAGS_MASK)); \
406 } while (0)
407
408/* Instruction has only one explicit operand (no source operand). */
d1eef45d 409#define emulate_1op(ctxt, _op) \
dda96d8f 410 do { \
d1eef45d
AK		 411 switch ((ctxt)->dst.bytes) { \
412 case 1: __emulate_1op(ctxt, _op, "b"); break; \
413 case 2: __emulate_1op(ctxt, _op, "w"); break; \
414 case 4: __emulate_1op(ctxt, _op, "l"); break; \
415 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 416 } \
417 } while (0)
418
e8f2b1d6 419#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 420 do { \
421 unsigned long _tmp; \
dd856efa
AK		 422 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
423 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 424 \
425 __asm__ __volatile__ ( \
426 _PRE_EFLAGS("0", "5", "1") \
427 "1: \n\t" \
428 _op _suffix " %6; " \
429 "2: \n\t" \
430 _POST_EFLAGS("0", "5", "1") \
431 ".pushsection .fixup,\"ax\" \n\t" \
432 "3: movb $1, %4 \n\t" \
433 "jmp 2b \n\t" \
434 ".popsection \n\t" \
435 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 436 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
437 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 438 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 439 } while (0)
440
3f9f53b0 441/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 442#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 443 do { \
e8f2b1d6 444 switch((ctxt)->src.bytes) { \
7295261c 445 case 1: \
e8f2b1d6 446 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 447 break; \
448 case 2: \
e8f2b1d6 449 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 450 break; \
451 case 4: \
e8f2b1d6 452 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 453 break; \
454 case 8: ON64( \
e8f2b1d6 455 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 456 break; \
457 } \
458 } while (0)
459
8a76d7f2
JR		 460static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
461 enum x86_intercept intercept,
462 enum x86_intercept_stage stage)
463{
464 struct x86_instruction_info info = {
465 .intercept = intercept,
9dac77fa
AK		 466 .rep_prefix = ctxt->rep_prefix,
467 .modrm_mod = ctxt->modrm_mod,
468 .modrm_reg = ctxt->modrm_reg,
469 .modrm_rm = ctxt->modrm_rm,
470 .src_val = ctxt->src.val64,
471 .src_bytes = ctxt->src.bytes,
472 .dst_bytes = ctxt->dst.bytes,
473 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 474 .next_rip = ctxt->eip,
475 };
476
2953538e 477 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 478}
479
f47cfa31
AK		 480static void assign_masked(ulong *dest, ulong src, ulong mask)
481{
482 *dest = (*dest & ~mask) | (src & mask);
483}
484
9dac77fa 485static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 486{
9dac77fa 487 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 488}
489
f47cfa31
AK		 490static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
491{
492 u16 sel;
493 struct desc_struct ss;
494
495 if (ctxt->mode == X86EMUL_MODE_PROT64)
496 return ~0UL;
497 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
498 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
499}
500
612e89f0
AK		 501static int stack_size(struct x86_emulate_ctxt *ctxt)
502{
503 return (__fls(stack_mask(ctxt)) + 1) >> 3;
504}
505
6aa8b732 506/* Access/update address held in a register, based on addressing mode. */
e4706772 507static inline unsigned long
9dac77fa 508address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 509{
9dac77fa 510 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 511 return reg;
512 else
9dac77fa 513 return reg & ad_mask(ctxt);
e4706772
HH		 514}
515
516static inline unsigned long
9dac77fa 517register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 518{
9dac77fa 519 return address_mask(ctxt, reg);
e4706772
HH		 520}
521
5ad105e5
AK		 522static void masked_increment(ulong *reg, ulong mask, int inc)
523{
524 assign_masked(reg, *reg + inc, mask);
525}
526
7a957275 527static inline void
9dac77fa 528register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 529{
5ad105e5
AK		 530 ulong mask;
531
9dac77fa 532 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 533 mask = ~0UL;
7a957275 534 else
5ad105e5
AK		 535 mask = ad_mask(ctxt);
536 masked_increment(reg, mask, inc);
537}
538
539static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
540{
dd856efa 541 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 542}
6aa8b732 543
9dac77fa 544static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 545{
9dac77fa 546 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 547}
098c937b 548
56697687
AK		 549static u32 desc_limit_scaled(struct desc_struct *desc)
550{
551 u32 limit = get_desc_limit(desc);
552
553 return desc->g ? (limit << 12) | 0xfff : limit;
554}
555
9dac77fa 556static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 557{
9dac77fa
AK		 558 ctxt->has_seg_override = true;
559 ctxt->seg_override = seg;
7a5b56df
AK		 560}
561
7b105ca2 562static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 563{
564 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
565 return 0;
566
7b105ca2 567 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 568}
569
9dac77fa 570static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 571{
9dac77fa 572 if (!ctxt->has_seg_override)
7a5b56df
AK		 573 return 0;
574
9dac77fa 575 return ctxt->seg_override;
7a5b56df
AK		 576}
577
35d3d4a1
AK		 578static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
579 u32 error, bool valid)
54b8486f 580{
da9cb575
AK		 581 ctxt->exception.vector = vec;
582 ctxt->exception.error_code = error;
583 ctxt->exception.error_code_valid = valid;
35d3d4a1 584 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 585}
586
3b88e41a
JR		 587static int emulate_db(struct x86_emulate_ctxt *ctxt)
588{
589 return emulate_exception(ctxt, DB_VECTOR, 0, false);
590}
591
35d3d4a1 592static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 593{
35d3d4a1 594 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 595}
596
618ff15d
AK		 597static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
598{
599 return emulate_exception(ctxt, SS_VECTOR, err, true);
600}
601
35d3d4a1 602static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 603{
35d3d4a1 604 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 605}
606
35d3d4a1 607static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 608{
35d3d4a1 609 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 610}
611
34d1f490
AK		 612static int emulate_de(struct x86_emulate_ctxt *ctxt)
613{
35d3d4a1 614 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 615}
616
1253791d
AK		 617static int emulate_nm(struct x86_emulate_ctxt *ctxt)
618{
619 return emulate_exception(ctxt, NM_VECTOR, 0, false);
620}
621
1aa36616
AK		 622static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
623{
624 u16 selector;
625 struct desc_struct desc;
626
627 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
628 return selector;
629}
630
631static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
632 unsigned seg)
633{
634 u16 dummy;
635 u32 base3;
636 struct desc_struct desc;
637
638 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
639 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
640}
641
1c11b376
AK		 642/*
643 * x86 defines three classes of vector instructions: explicitly
644 * aligned, explicitly unaligned, and the rest, which change behaviour
645 * depending on whether they're AVX encoded or not.
646 *
647 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
648 * subject to the same check.
649 */
650static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
651{
652 if (likely(size < 16))
653 return false;
654
655 if (ctxt->d & Aligned)
656 return true;
657 else if (ctxt->d & Unaligned)
658 return false;
659 else if (ctxt->d & Avx)
660 return false;
661 else
662 return true;
663}
664
3d9b938e 665static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 666 struct segmented_address addr,
3d9b938e 667 unsigned size, bool write, bool fetch,
52fd8b44
AK		 668 ulong *linear)
669{
618ff15d
AK		 670 struct desc_struct desc;
671 bool usable;
52fd8b44 672 ulong la;
618ff15d 673 u32 lim;
1aa36616 674 u16 sel;
3a78a4f4 675 unsigned cpl;
52fd8b44 676
7b105ca2 677 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 678 switch (ctxt->mode) {
618ff15d
AK		 679 case X86EMUL_MODE_PROT64:
680 if (((signed long)la << 16) >> 16 != la)
681 return emulate_gp(ctxt, 0);
682 break;
683 default:
1aa36616
AK		 684 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
685 addr.seg);
618ff15d
AK		 686 if (!usable)
687 goto bad;
58b7825b
GN		 688 /* code segment in protected mode or read-only data segment */
689 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
690 || !(desc.type & 2)) && write)
618ff15d
AK		 691 goto bad;
692 /* unreadable code segment */
3d9b938e 693 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 694 goto bad;
695 lim = desc_limit_scaled(&desc);
696 if ((desc.type & 8) || !(desc.type & 4)) {
697 /* expand-up segment */
698 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
699 goto bad;
700 } else {
fc058680 701 /* expand-down segment */
618ff15d
AK		 702 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
703 goto bad;
704 lim = desc.d ? 0xffffffff : 0xffff;
705 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
706 goto bad;
707 }
717746e3 708 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 709 if (!(desc.type & 8)) {
710 /* data segment */
711 if (cpl > desc.dpl)
712 goto bad;
713 } else if ((desc.type & 8) && !(desc.type & 4)) {
714 /* nonconforming code segment */
715 if (cpl != desc.dpl)
716 goto bad;
717 } else if ((desc.type & 8) && (desc.type & 4)) {
718 /* conforming code segment */
719 if (cpl < desc.dpl)
720 goto bad;
721 }
722 break;
723 }
9dac77fa 724 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 725 la &= (u32)-1;
1c11b376
AK		 726 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
727 return emulate_gp(ctxt, 0);
52fd8b44
AK		 728 *linear = la;
729 return X86EMUL_CONTINUE;
618ff15d
AK		 730bad:
731 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 732 return emulate_ss(ctxt, sel);
618ff15d 733 else
0afbe2f8 734 return emulate_gp(ctxt, sel);
52fd8b44
AK		 735}
736
3d9b938e
NE		 737static int linearize(struct x86_emulate_ctxt *ctxt,
738 struct segmented_address addr,
739 unsigned size, bool write,
740 ulong *linear)
741{
742 return __linearize(ctxt, addr, size, write, false, linear);
743}
744
745
3ca3ac4d
AK		 746static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
747 struct segmented_address addr,
748 void *data,
749 unsigned size)
750{
9fa088f4
AK		 751 int rc;
752 ulong linear;
753
83b8795a 754 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 755 if (rc != X86EMUL_CONTINUE)
756 return rc;
0f65dd70 757 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 758}
759
807941b1
TY		 760/*
761 * Fetch the next byte of the instruction being emulated which is pointed to
762 * by ctxt->_eip, then increment ctxt->_eip.
763 *
764 * Also prefetch the remaining bytes of the instruction without crossing page
765 * boundary if they are not in fetch_cache yet.
766 */
767static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 768{
9dac77fa 769 struct fetch_cache *fc = &ctxt->fetch;
62266869 770 int rc;
2fb53ad8 771 int size, cur_size;
62266869 772
807941b1 773 if (ctxt->_eip == fc->end) {
3d9b938e 774 unsigned long linear;
807941b1
TY		 775 struct segmented_address addr = { .seg = VCPU_SREG_CS,
776 .ea = ctxt->_eip };
2fb53ad8 777 cur_size = fc->end - fc->start;
807941b1
TY		 778 size = min(15UL - cur_size,
779 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 780 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 781 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 782 return rc;
ef5d75cc
TY		 783 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
784 size, &ctxt->exception);
7d88bb48 785 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 786 return rc;
2fb53ad8 787 fc->end += size;
62266869 788 }
807941b1
TY		 789 *dest = fc->data[ctxt->_eip - fc->start];
790 ctxt->_eip++;
3e2815e9 791 return X86EMUL_CONTINUE;
62266869
AK		 792}
793
794static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 795 void *dest, unsigned size)
62266869 796{
3e2815e9 797 int rc;
62266869 798
eb3c79e6 799 /* x86 instructions are limited to 15 bytes. */
7d88bb48 800 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 801 return X86EMUL_UNHANDLEABLE;
62266869 802 while (size--) {
807941b1 803 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 804 if (rc != X86EMUL_CONTINUE)
62266869
AK		 805 return rc;
806 }
3e2815e9 807 return X86EMUL_CONTINUE;
62266869
AK		 808}
809
67cbc90d 810/* Fetch next part of the instruction being emulated. */
e85a1085 811#define insn_fetch(_type, _ctxt) \
67cbc90d 812({ unsigned long _x; \
e85a1085 813 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 814 if (rc != X86EMUL_CONTINUE) \
815 goto done; \
67cbc90d
TY		 816 (_type)_x; \
817})
818
807941b1
TY		 819#define insn_fetch_arr(_arr, _size, _ctxt) \
820({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 821 if (rc != X86EMUL_CONTINUE) \
822 goto done; \
67cbc90d
TY		 823})
824
1e3c5cb0
RR		 825/*
826 * Given the 'reg' portion of a ModRM byte, and a register block, return a
827 * pointer into the block that addresses the relevant register.
828 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
829 */
dd856efa 830static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 831 int highbyte_regs)
6aa8b732
AK		 832{
833 void *p;
834
6aa8b732 835 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 836 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
837 else
838 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 839 return p;
840}
841
842static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 843 struct segmented_address addr,
6aa8b732
AK		 844 u16 *size, unsigned long *address, int op_bytes)
845{
846 int rc;
847
848 if (op_bytes == 2)
849 op_bytes = 3;
850 *address = 0;
3ca3ac4d 851 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 852 if (rc != X86EMUL_CONTINUE)
6aa8b732 853 return rc;
30b31ab6 854 addr.ea += 2;
3ca3ac4d 855 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 856 return rc;
857}
858
bbe9abbd
NK		 859static int test_cc(unsigned int condition, unsigned int flags)
860{
861 int rc = 0;
862
863 switch ((condition & 15) >> 1) {
864 case 0: /* o */
865 rc |= (flags & EFLG_OF);
866 break;
867 case 1: /* b/c/nae */
868 rc |= (flags & EFLG_CF);
869 break;
870 case 2: /* z/e */
871 rc |= (flags & EFLG_ZF);
872 break;
873 case 3: /* be/na */
874 rc |= (flags & (EFLG_CF|EFLG_ZF));
875 break;
876 case 4: /* s */
877 rc |= (flags & EFLG_SF);
878 break;
879 case 5: /* p/pe */
880 rc |= (flags & EFLG_PF);
881 break;
882 case 7: /* le/ng */
883 rc |= (flags & EFLG_ZF);
884 /* fall through */
885 case 6: /* l/nge */
886 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
887 break;
888 }
889
890 /* Odd condition identifiers (lsb == 1) have inverted sense. */
891 return (!!rc ^ (condition & 1));
892}
893
91ff3cb4
AK		 894static void fetch_register_operand(struct operand *op)
895{
896 switch (op->bytes) {
897 case 1:
898 op->val = *(u8 *)op->addr.reg;
899 break;
900 case 2:
901 op->val = *(u16 *)op->addr.reg;
902 break;
903 case 4:
904 op->val = *(u32 *)op->addr.reg;
905 break;
906 case 8:
907 op->val = *(u64 *)op->addr.reg;
908 break;
909 }
910}
911
1253791d
AK		 912static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
913{
914 ctxt->ops->get_fpu(ctxt);
915 switch (reg) {
89a87c67
MK		 916 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
917 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
918 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
919 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
920 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
921 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
922 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
923 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 924#ifdef CONFIG_X86_64
89a87c67
MK		 925 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
926 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
927 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
928 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
929 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
930 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
931 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
932 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 933#endif
934 default: BUG();
935 }
936 ctxt->ops->put_fpu(ctxt);
937}
938
939static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
940 int reg)
941{
942 ctxt->ops->get_fpu(ctxt);
943 switch (reg) {
89a87c67
MK		 944 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
945 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
946 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
947 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
948 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
949 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
950 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
951 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 952#ifdef CONFIG_X86_64
89a87c67
MK		 953 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
954 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
955 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
956 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
957 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
958 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
959 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
960 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 961#endif
962 default: BUG();
963 }
964 ctxt->ops->put_fpu(ctxt);
965}
966
cbe2c9d3
AK		 967static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
968{
969 ctxt->ops->get_fpu(ctxt);
970 switch (reg) {
971 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
972 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
973 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
974 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
975 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
976 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
977 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
978 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
979 default: BUG();
980 }
981 ctxt->ops->put_fpu(ctxt);
982}
983
984static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
985{
986 ctxt->ops->get_fpu(ctxt);
987 switch (reg) {
988 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
989 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
990 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
991 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
992 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
993 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
994 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
995 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
996 default: BUG();
997 }
998 ctxt->ops->put_fpu(ctxt);
999}
1000
045a282c
GN		 1001static int em_fninit(struct x86_emulate_ctxt *ctxt)
1002{
1003 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1004 return emulate_nm(ctxt);
1005
1006 ctxt->ops->get_fpu(ctxt);
1007 asm volatile("fninit");
1008 ctxt->ops->put_fpu(ctxt);
1009 return X86EMUL_CONTINUE;
1010}
1011
1012static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1013{
1014 u16 fcw;
1015
1016 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1017 return emulate_nm(ctxt);
1018
1019 ctxt->ops->get_fpu(ctxt);
1020 asm volatile("fnstcw %0": "+m"(fcw));
1021 ctxt->ops->put_fpu(ctxt);
1022
1023 /* force 2 byte destination */
1024 ctxt->dst.bytes = 2;
1025 ctxt->dst.val = fcw;
1026
1027 return X86EMUL_CONTINUE;
1028}
1029
1030static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1031{
1032 u16 fsw;
1033
1034 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1035 return emulate_nm(ctxt);
1036
1037 ctxt->ops->get_fpu(ctxt);
1038 asm volatile("fnstsw %0": "+m"(fsw));
1039 ctxt->ops->put_fpu(ctxt);
1040
1041 /* force 2 byte destination */
1042 ctxt->dst.bytes = 2;
1043 ctxt->dst.val = fsw;
1044
1045 return X86EMUL_CONTINUE;
1046}
1047
1253791d 1048static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1049 struct operand *op)
3c118e24 1050{
9dac77fa
AK		 1051 unsigned reg = ctxt->modrm_reg;
1052 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1053
9dac77fa
AK		 1054 if (!(ctxt->d & ModRM))
1055 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1056
9dac77fa 1057 if (ctxt->d & Sse) {
1253791d
AK		 1058 op->type = OP_XMM;
1059 op->bytes = 16;
1060 op->addr.xmm = reg;
1061 read_sse_reg(ctxt, &op->vec_val, reg);
1062 return;
1063 }
cbe2c9d3
AK		 1064 if (ctxt->d & Mmx) {
1065 reg &= 7;
1066 op->type = OP_MM;
1067 op->bytes = 8;
1068 op->addr.mm = reg;
1069 return;
1070 }
1253791d 1071
3c118e24 1072 op->type = OP_REG;
2adb5ad9 1073 if (ctxt->d & ByteOp) {
dd856efa 1074 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1075 op->bytes = 1;
1076 } else {
dd856efa 1077 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1078 op->bytes = ctxt->op_bytes;
3c118e24 1079 }
91ff3cb4 1080 fetch_register_operand(op);
3c118e24
AK		 1081 op->orig_val = op->val;
1082}
1083
a6e3407b
AK		 1084static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1085{
1086 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1087 ctxt->modrm_seg = VCPU_SREG_SS;
1088}
1089
1c73ef66 1090static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1091 struct operand *op)
1c73ef66 1092{
1c73ef66 1093 u8 sib;
f5b4edcd 1094 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1095 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1096 ulong modrm_ea = 0;
1c73ef66 1097
9dac77fa
AK		 1098 if (ctxt->rex_prefix) {
1099 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1100 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1101 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1102 }
1103
9dac77fa
AK		 1104 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1105 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1106 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1107 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1108
9dac77fa 1109 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1110 op->type = OP_REG;
9dac77fa 1111 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1112 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1113 if (ctxt->d & Sse) {
1253791d
AK		 1114 op->type = OP_XMM;
1115 op->bytes = 16;
9dac77fa
AK		 1116 op->addr.xmm = ctxt->modrm_rm;
1117 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1118 return rc;
1119 }
cbe2c9d3
AK		 1120 if (ctxt->d & Mmx) {
1121 op->type = OP_MM;
1122 op->bytes = 8;
1123 op->addr.xmm = ctxt->modrm_rm & 7;
1124 return rc;
1125 }
2dbd0dd7 1126 fetch_register_operand(op);
1c73ef66
AK		 1127 return rc;
1128 }
1129
2dbd0dd7
AK		 1130 op->type = OP_MEM;
1131
9dac77fa 1132 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1133 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1134 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1135 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1136 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1137
1138 /* 16-bit ModR/M decode. */
9dac77fa 1139 switch (ctxt->modrm_mod) {
1c73ef66 1140 case 0:
9dac77fa 1141 if (ctxt->modrm_rm == 6)
e85a1085 1142 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1143 break;
1144 case 1:
e85a1085 1145 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1146 break;
1147 case 2:
e85a1085 1148 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1149 break;
1150 }
9dac77fa 1151 switch (ctxt->modrm_rm) {
1c73ef66 1152 case 0:
2dbd0dd7 1153 modrm_ea += bx + si;
1c73ef66
AK		 1154 break;
1155 case 1:
2dbd0dd7 1156 modrm_ea += bx + di;
1c73ef66
AK		 1157 break;
1158 case 2:
2dbd0dd7 1159 modrm_ea += bp + si;
1c73ef66
AK		 1160 break;
1161 case 3:
2dbd0dd7 1162 modrm_ea += bp + di;
1c73ef66
AK		 1163 break;
1164 case 4:
2dbd0dd7 1165 modrm_ea += si;
1c73ef66
AK		 1166 break;
1167 case 5:
2dbd0dd7 1168 modrm_ea += di;
1c73ef66
AK		 1169 break;
1170 case 6:
9dac77fa 1171 if (ctxt->modrm_mod != 0)
2dbd0dd7 1172 modrm_ea += bp;
1c73ef66
AK		 1173 break;
1174 case 7:
2dbd0dd7 1175 modrm_ea += bx;
1c73ef66
AK		 1176 break;
1177 }
9dac77fa
AK		 1178 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1179 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1180 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1181 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1182 } else {
1183 /* 32/64-bit ModR/M decode. */
9dac77fa 1184 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1185 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1186 index_reg |= (sib >> 3) & 7;
1187 base_reg |= sib & 7;
1188 scale = sib >> 6;
1189
9dac77fa 1190 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1191 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1192 else {
dd856efa 1193 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1194 adjust_modrm_seg(ctxt, base_reg);
1195 }
dc71d0f1 1196 if (index_reg != 4)
dd856efa 1197 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1198 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1199 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1200 ctxt->rip_relative = 1;
a6e3407b
AK		 1201 } else {
1202 base_reg = ctxt->modrm_rm;
dd856efa 1203 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1204 adjust_modrm_seg(ctxt, base_reg);
1205 }
9dac77fa 1206 switch (ctxt->modrm_mod) {
1c73ef66 1207 case 0:
9dac77fa 1208 if (ctxt->modrm_rm == 5)
e85a1085 1209 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1210 break;
1211 case 1:
e85a1085 1212 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1213 break;
1214 case 2:
e85a1085 1215 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1216 break;
1217 }
1218 }
90de84f5 1219 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1220done:
1221 return rc;
1222}
1223
1224static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1225 struct operand *op)
1c73ef66 1226{
3e2815e9 1227 int rc = X86EMUL_CONTINUE;
1c73ef66 1228
2dbd0dd7 1229 op->type = OP_MEM;
9dac77fa 1230 switch (ctxt->ad_bytes) {
1c73ef66 1231 case 2:
e85a1085 1232 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1233 break;
1234 case 4:
e85a1085 1235 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1236 break;
1237 case 8:
e85a1085 1238 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1239 break;
1240 }
1241done:
1242 return rc;
1243}
1244
9dac77fa 1245static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1246{
7129eeca 1247 long sv = 0, mask;
35c843c4 1248
9dac77fa
AK		 1249 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1250 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1251
9dac77fa
AK		 1252 if (ctxt->src.bytes == 2)
1253 sv = (s16)ctxt->src.val & (s16)mask;
1254 else if (ctxt->src.bytes == 4)
1255 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1256
9dac77fa 1257 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1258 }
ba7ff2b7
WY		 1259
1260 /* only subword offset */
9dac77fa 1261 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1262}
1263
dde7e6d1 1264static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1265 unsigned long addr, void *dest, unsigned size)
6aa8b732 1266{
dde7e6d1 1267 int rc;
9dac77fa 1268 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1269
f23b070e
XG		 1270 if (mc->pos < mc->end)
1271 goto read_cached;
6aa8b732 1272
f23b070e
XG		 1273 WARN_ON((mc->end + size) >= sizeof(mc->data));
1274
1275 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1276 &ctxt->exception);
1277 if (rc != X86EMUL_CONTINUE)
1278 return rc;
1279
1280 mc->end += size;
1281
1282read_cached:
1283 memcpy(dest, mc->data + mc->pos, size);
1284 mc->pos += size;
dde7e6d1
AK		 1285 return X86EMUL_CONTINUE;
1286}
6aa8b732 1287
3ca3ac4d
AK		 1288static int segmented_read(struct x86_emulate_ctxt *ctxt,
1289 struct segmented_address addr,
1290 void *data,
1291 unsigned size)
1292{
9fa088f4
AK		 1293 int rc;
1294 ulong linear;
1295
83b8795a 1296 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1297 if (rc != X86EMUL_CONTINUE)
1298 return rc;
7b105ca2 1299 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1300}
1301
1302static int segmented_write(struct x86_emulate_ctxt *ctxt,
1303 struct segmented_address addr,
1304 const void *data,
1305 unsigned size)
1306{
9fa088f4
AK		 1307 int rc;
1308 ulong linear;
1309
83b8795a 1310 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1311 if (rc != X86EMUL_CONTINUE)
1312 return rc;
0f65dd70
AK		 1313 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1314 &ctxt->exception);
3ca3ac4d
AK		 1315}
1316
1317static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1318 struct segmented_address addr,
1319 const void *orig_data, const void *data,
1320 unsigned size)
1321{
9fa088f4
AK		 1322 int rc;
1323 ulong linear;
1324
83b8795a 1325 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1326 if (rc != X86EMUL_CONTINUE)
1327 return rc;
0f65dd70
AK		 1328 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1329 size, &ctxt->exception);
3ca3ac4d
AK		 1330}
1331
dde7e6d1 1332static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1333 unsigned int size, unsigned short port,
1334 void *dest)
1335{
9dac77fa 1336 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1337
dde7e6d1 1338 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1339 unsigned int in_page, n;
9dac77fa 1340 unsigned int count = ctxt->rep_prefix ?
dd856efa 1341 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1342 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1343 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1344 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1345 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1346 count);
1347 if (n == 0)
1348 n = 1;
1349 rc->pos = rc->end = 0;
7b105ca2 1350 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1351 return 0;
1352 rc->end = n * size;
6aa8b732
AK		 1353 }
1354
b3356bf0
GN		 1355 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1356 ctxt->dst.data = rc->data + rc->pos;
1357 ctxt->dst.type = OP_MEM_STR;
1358 ctxt->dst.count = (rc->end - rc->pos) / size;
1359 rc->pos = rc->end;
1360 } else {
1361 memcpy(dest, rc->data + rc->pos, size);
1362 rc->pos += size;
1363 }
dde7e6d1
AK		 1364 return 1;
1365}
6aa8b732 1366
7f3d35fd
KW		 1367static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1368 u16 index, struct desc_struct *desc)
1369{
1370 struct desc_ptr dt;
1371 ulong addr;
1372
1373 ctxt->ops->get_idt(ctxt, &dt);
1374
1375 if (dt.size < index * 8 + 7)
1376 return emulate_gp(ctxt, index << 3 | 0x2);
1377
1378 addr = dt.address + index * 8;
1379 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1380 &ctxt->exception);
1381}
1382
dde7e6d1 1383static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1384 u16 selector, struct desc_ptr *dt)
1385{
0225fb50 1386 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1387
dde7e6d1
AK		 1388 if (selector & 1 << 2) {
1389 struct desc_struct desc;
1aa36616
AK		 1390 u16 sel;
1391
dde7e6d1 1392 memset (dt, 0, sizeof *dt);
1aa36616 1393 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1394 return;
e09d082c 1395
dde7e6d1
AK		 1396 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1397 dt->address = get_desc_base(&desc);
1398 } else
4bff1e86 1399 ops->get_gdt(ctxt, dt);
dde7e6d1 1400}
120df890 1401
dde7e6d1
AK		 1402/* allowed just for 8 bytes segments */
1403static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1404 u16 selector, struct desc_struct *desc,
1405 ulong *desc_addr_p)
dde7e6d1
AK		 1406{
1407 struct desc_ptr dt;
1408 u16 index = selector >> 3;
dde7e6d1 1409 ulong addr;
120df890 1410
7b105ca2 1411 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1412
35d3d4a1
AK		 1413 if (dt.size < index * 8 + 7)
1414 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1415
e919464b 1416 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1417 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1418 &ctxt->exception);
dde7e6d1 1419}
ef65c889 1420
dde7e6d1
AK		 1421/* allowed just for 8 bytes segments */
1422static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1423 u16 selector, struct desc_struct *desc)
1424{
1425 struct desc_ptr dt;
1426 u16 index = selector >> 3;
dde7e6d1 1427 ulong addr;
6aa8b732 1428
7b105ca2 1429 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1430
35d3d4a1
AK		 1431 if (dt.size < index * 8 + 7)
1432 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1433
dde7e6d1 1434 addr = dt.address + index * 8;
7b105ca2
TY		 1435 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1436 &ctxt->exception);
dde7e6d1 1437}
c7e75a3d 1438
5601d05b 1439/* Does not support long mode */
dde7e6d1 1440static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1441 u16 selector, int seg)
1442{
869be99c 1443 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1444 u8 dpl, rpl, cpl;
1445 unsigned err_vec = GP_VECTOR;
1446 u32 err_code = 0;
1447 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1448 ulong desc_addr;
dde7e6d1 1449 int ret;
03ebebeb 1450 u16 dummy;
69f55cb1 1451
dde7e6d1 1452 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1453
dde7e6d1
AK		 1454 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1455 || ctxt->mode == X86EMUL_MODE_REAL) {
1456 /* set real mode segment descriptor */
03ebebeb 1457 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1458 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1459 goto load;
1460 }
1461
79d5b4c3
AK		 1462 rpl = selector & 3;
1463 cpl = ctxt->ops->cpl(ctxt);
1464
1465 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1466 if ((seg == VCPU_SREG_CS
1467 || (seg == VCPU_SREG_SS
1468 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1469 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1470 && null_selector)
1471 goto exception;
1472
1473 /* TR should be in GDT only */
1474 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1475 goto exception;
1476
1477 if (null_selector) /* for NULL selector skip all following checks */
1478 goto load;
1479
e919464b 1480 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1481 if (ret != X86EMUL_CONTINUE)
1482 return ret;
1483
1484 err_code = selector & 0xfffc;
1485 err_vec = GP_VECTOR;
1486
fc058680 1487 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1488 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1489 goto exception;
1490
1491 if (!seg_desc.p) {
1492 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1493 goto exception;
1494 }
1495
dde7e6d1 1496 dpl = seg_desc.dpl;
dde7e6d1
AK		 1497
1498 switch (seg) {
1499 case VCPU_SREG_SS:
1500 /*
1501 * segment is not a writable data segment or segment
1502 * selector's RPL != CPL or segment selector's RPL != CPL
1503 */
1504 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1505 goto exception;
6aa8b732 1506 break;
dde7e6d1
AK		 1507 case VCPU_SREG_CS:
1508 if (!(seg_desc.type & 8))
1509 goto exception;
1510
1511 if (seg_desc.type & 4) {
1512 /* conforming */
1513 if (dpl > cpl)
1514 goto exception;
1515 } else {
1516 /* nonconforming */
1517 if (rpl > cpl || dpl != cpl)
1518 goto exception;
1519 }
1520 /* CS(RPL) <- CPL */
1521 selector = (selector & 0xfffc) | cpl;
6aa8b732 1522 break;
dde7e6d1
AK		 1523 case VCPU_SREG_TR:
1524 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1525 goto exception;
869be99c
AK		 1526 old_desc = seg_desc;
1527 seg_desc.type |= 2; /* busy */
1528 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1529 sizeof(seg_desc), &ctxt->exception);
1530 if (ret != X86EMUL_CONTINUE)
1531 return ret;
dde7e6d1
AK		 1532 break;
1533 case VCPU_SREG_LDTR:
1534 if (seg_desc.s || seg_desc.type != 2)
1535 goto exception;
1536 break;
1537 default: /* DS, ES, FS, or GS */
4e62417b 1538 /*
dde7e6d1
AK		 1539 * segment is not a data or readable code segment or
1540 * ((segment is a data or nonconforming code segment)
1541 * and (both RPL and CPL > DPL))
4e62417b 1542 */
dde7e6d1
AK		 1543 if ((seg_desc.type & 0xa) == 0x8 ||
1544 (((seg_desc.type & 0xc) != 0xc) &&
1545 (rpl > dpl && cpl > dpl)))
1546 goto exception;
6aa8b732 1547 break;
dde7e6d1
AK		 1548 }
1549
1550 if (seg_desc.s) {
1551 /* mark segment as accessed */
1552 seg_desc.type |= 1;
7b105ca2 1553 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1554 if (ret != X86EMUL_CONTINUE)
1555 return ret;
1556 }
1557load:
7b105ca2 1558 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1559 return X86EMUL_CONTINUE;
1560exception:
1561 emulate_exception(ctxt, err_vec, err_code, true);
1562 return X86EMUL_PROPAGATE_FAULT;
1563}
1564
31be40b3
WY		 1565static void write_register_operand(struct operand *op)
1566{
1567 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1568 switch (op->bytes) {
1569 case 1:
1570 *(u8 *)op->addr.reg = (u8)op->val;
1571 break;
1572 case 2:
1573 *(u16 *)op->addr.reg = (u16)op->val;
1574 break;
1575 case 4:
1576 *op->addr.reg = (u32)op->val;
1577 break; /* 64b: zero-extend */
1578 case 8:
1579 *op->addr.reg = op->val;
1580 break;
1581 }
1582}
1583
adddcecf 1584static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1585{
1586 int rc;
dde7e6d1 1587
9dac77fa 1588 switch (ctxt->dst.type) {
dde7e6d1 1589 case OP_REG:
9dac77fa 1590 write_register_operand(&ctxt->dst);
6aa8b732 1591 break;
dde7e6d1 1592 case OP_MEM:
9dac77fa 1593 if (ctxt->lock_prefix)
3ca3ac4d 1594 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1595 ctxt->dst.addr.mem,
1596 &ctxt->dst.orig_val,
1597 &ctxt->dst.val,
1598 ctxt->dst.bytes);
341de7e3 1599 else
3ca3ac4d 1600 rc = segmented_write(ctxt,
9dac77fa
AK		 1601 ctxt->dst.addr.mem,
1602 &ctxt->dst.val,
1603 ctxt->dst.bytes);
dde7e6d1
AK		 1604 if (rc != X86EMUL_CONTINUE)
1605 return rc;
a682e354 1606 break;
b3356bf0
GN		 1607 case OP_MEM_STR:
1608 rc = segmented_write(ctxt,
1609 ctxt->dst.addr.mem,
1610 ctxt->dst.data,
1611 ctxt->dst.bytes * ctxt->dst.count);
1612 if (rc != X86EMUL_CONTINUE)
1613 return rc;
1614 break;
1253791d 1615 case OP_XMM:
9dac77fa 1616 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1617 break;
cbe2c9d3
AK		 1618 case OP_MM:
1619 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1620 break;
dde7e6d1
AK		 1621 case OP_NONE:
1622 /* no writeback */
414e6277 1623 break;
dde7e6d1 1624 default:
414e6277 1625 break;
6aa8b732 1626 }
dde7e6d1
AK		 1627 return X86EMUL_CONTINUE;
1628}
6aa8b732 1629
51ddff50 1630static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1631{
4179bb02 1632 struct segmented_address addr;
0dc8d10f 1633
5ad105e5 1634 rsp_increment(ctxt, -bytes);
dd856efa 1635 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1636 addr.seg = VCPU_SREG_SS;
1637
51ddff50
AK		 1638 return segmented_write(ctxt, addr, data, bytes);
1639}
1640
1641static int em_push(struct x86_emulate_ctxt *ctxt)
1642{
4179bb02 1643 /* Disable writeback. */
9dac77fa 1644 ctxt->dst.type = OP_NONE;
51ddff50 1645 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1646}
69f55cb1 1647
dde7e6d1 1648static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1649 void *dest, int len)
1650{
dde7e6d1 1651 int rc;
90de84f5 1652 struct segmented_address addr;
8b4caf66 1653
dd856efa 1654 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1655 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1656 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1657 if (rc != X86EMUL_CONTINUE)
1658 return rc;
1659
5ad105e5 1660 rsp_increment(ctxt, len);
dde7e6d1 1661 return rc;
8b4caf66
LV		 1662}
1663
c54fe504
TY		 1664static int em_pop(struct x86_emulate_ctxt *ctxt)
1665{
9dac77fa 1666 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1667}
1668
dde7e6d1 1669static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1670 void *dest, int len)
9de41573
GN		 1671{
1672 int rc;
dde7e6d1
AK		 1673 unsigned long val, change_mask;
1674 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1675 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1676
3b9be3bf 1677 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1678 if (rc != X86EMUL_CONTINUE)
1679 return rc;
9de41573 1680
dde7e6d1
AK		 1681 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1682 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1683
dde7e6d1
AK		 1684 switch(ctxt->mode) {
1685 case X86EMUL_MODE_PROT64:
1686 case X86EMUL_MODE_PROT32:
1687 case X86EMUL_MODE_PROT16:
1688 if (cpl == 0)
1689 change_mask |= EFLG_IOPL;
1690 if (cpl <= iopl)
1691 change_mask |= EFLG_IF;
1692 break;
1693 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1694 if (iopl < 3)
1695 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1696 change_mask |= EFLG_IF;
1697 break;
1698 default: /* real mode */
1699 change_mask |= (EFLG_IOPL | EFLG_IF);
1700 break;
9de41573 1701 }
dde7e6d1
AK		 1702
1703 *(unsigned long *)dest =
1704 (ctxt->eflags & ~change_mask) | (val & change_mask);
1705
1706 return rc;
9de41573
GN		 1707}
1708
62aaa2f0
TY		 1709static int em_popf(struct x86_emulate_ctxt *ctxt)
1710{
9dac77fa
AK		 1711 ctxt->dst.type = OP_REG;
1712 ctxt->dst.addr.reg = &ctxt->eflags;
1713 ctxt->dst.bytes = ctxt->op_bytes;
1714 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1715}
1716
612e89f0
AK		 1717static int em_enter(struct x86_emulate_ctxt *ctxt)
1718{
1719 int rc;
1720 unsigned frame_size = ctxt->src.val;
1721 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1722 ulong rbp;
612e89f0
AK		 1723
1724 if (nesting_level)
1725 return X86EMUL_UNHANDLEABLE;
1726
dd856efa
AK		 1727 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1728 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
dd856efa 1731 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1732 stack_mask(ctxt));
dd856efa
AK		 1733 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1734 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1735 stack_mask(ctxt));
1736 return X86EMUL_CONTINUE;
1737}
1738
f47cfa31
AK		 1739static int em_leave(struct x86_emulate_ctxt *ctxt)
1740{
dd856efa 1741 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1742 stack_mask(ctxt));
dd856efa 1743 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1744}
1745
1cd196ea 1746static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1747{
1cd196ea
AK		 1748 int seg = ctxt->src2.val;
1749
9dac77fa 1750 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1751
4487b3b4 1752 return em_push(ctxt);
7b262e90
GN		 1753}
1754
1cd196ea 1755static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1756{
1cd196ea 1757 int seg = ctxt->src2.val;
dde7e6d1
AK		 1758 unsigned long selector;
1759 int rc;
38ba30ba 1760
9dac77fa 1761 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
1764
7b105ca2 1765 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1766 return rc;
38ba30ba
GN		 1767}
1768
b96a7fad 1769static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1770{
dd856efa 1771 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1772 int rc = X86EMUL_CONTINUE;
1773 int reg = VCPU_REGS_RAX;
38ba30ba 1774
dde7e6d1
AK		 1775 while (reg <= VCPU_REGS_RDI) {
1776 (reg == VCPU_REGS_RSP) ?
dd856efa 1777 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1778
4487b3b4 1779 rc = em_push(ctxt);
dde7e6d1
AK		 1780 if (rc != X86EMUL_CONTINUE)
1781 return rc;
38ba30ba 1782
dde7e6d1 1783 ++reg;
38ba30ba 1784 }
38ba30ba 1785
dde7e6d1 1786 return rc;
38ba30ba
GN		 1787}
1788
62aaa2f0
TY		 1789static int em_pushf(struct x86_emulate_ctxt *ctxt)
1790{
9dac77fa 1791 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1792 return em_push(ctxt);
1793}
1794
b96a7fad 1795static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1796{
dde7e6d1
AK		 1797 int rc = X86EMUL_CONTINUE;
1798 int reg = VCPU_REGS_RDI;
38ba30ba 1799
dde7e6d1
AK		 1800 while (reg >= VCPU_REGS_RAX) {
1801 if (reg == VCPU_REGS_RSP) {
5ad105e5 1802 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1803 --reg;
1804 }
38ba30ba 1805
dd856efa 1806 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1807 if (rc != X86EMUL_CONTINUE)
1808 break;
1809 --reg;
38ba30ba 1810 }
dde7e6d1 1811 return rc;
38ba30ba
GN		 1812}
1813
dd856efa 1814static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1815{
0225fb50 1816 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1817 int rc;
6e154e56
MG		 1818 struct desc_ptr dt;
1819 gva_t cs_addr;
1820 gva_t eip_addr;
1821 u16 cs, eip;
6e154e56
MG		 1822
1823 /* TODO: Add limit checks */
9dac77fa 1824 ctxt->src.val = ctxt->eflags;
4487b3b4 1825 rc = em_push(ctxt);
5c56e1cf
AK		 1826 if (rc != X86EMUL_CONTINUE)
1827 return rc;
6e154e56
MG		 1828
1829 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1830
9dac77fa 1831 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1832 rc = em_push(ctxt);
5c56e1cf
AK		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
6e154e56 1835
9dac77fa 1836 ctxt->src.val = ctxt->_eip;
4487b3b4 1837 rc = em_push(ctxt);
5c56e1cf
AK		 1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
1840
4bff1e86 1841 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1842
1843 eip_addr = dt.address + (irq << 2);
1844 cs_addr = dt.address + (irq << 2) + 2;
1845
0f65dd70 1846 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
1849
0f65dd70 1850 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1851 if (rc != X86EMUL_CONTINUE)
1852 return rc;
1853
7b105ca2 1854 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
1857
9dac77fa 1858 ctxt->_eip = eip;
6e154e56
MG		 1859
1860 return rc;
1861}
1862
dd856efa
AK		 1863int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1864{
1865 int rc;
1866
1867 invalidate_registers(ctxt);
1868 rc = __emulate_int_real(ctxt, irq);
1869 if (rc == X86EMUL_CONTINUE)
1870 writeback_registers(ctxt);
1871 return rc;
1872}
1873
7b105ca2 1874static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1875{
1876 switch(ctxt->mode) {
1877 case X86EMUL_MODE_REAL:
dd856efa 1878 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1879 case X86EMUL_MODE_VM86:
1880 case X86EMUL_MODE_PROT16:
1881 case X86EMUL_MODE_PROT32:
1882 case X86EMUL_MODE_PROT64:
1883 default:
1884 /* Protected mode interrupts unimplemented yet */
1885 return X86EMUL_UNHANDLEABLE;
1886 }
1887}
1888
7b105ca2 1889static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1890{
dde7e6d1
AK		 1891 int rc = X86EMUL_CONTINUE;
1892 unsigned long temp_eip = 0;
1893 unsigned long temp_eflags = 0;
1894 unsigned long cs = 0;
1895 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1896 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1897 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1898 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1899
dde7e6d1 1900 /* TODO: Add stack limit check */
38ba30ba 1901
9dac77fa 1902 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1903
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
38ba30ba 1906
35d3d4a1
AK		 1907 if (temp_eip & ~0xffff)
1908 return emulate_gp(ctxt, 0);
38ba30ba 1909
9dac77fa 1910 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1911
dde7e6d1
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
38ba30ba 1914
9dac77fa 1915 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1916
dde7e6d1
AK		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
38ba30ba 1919
7b105ca2 1920 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1921
dde7e6d1
AK		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
38ba30ba 1924
9dac77fa 1925 ctxt->_eip = temp_eip;
38ba30ba 1926
38ba30ba 1927
9dac77fa 1928 if (ctxt->op_bytes == 4)
dde7e6d1 1929 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1930 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1931 ctxt->eflags &= ~0xffff;
1932 ctxt->eflags |= temp_eflags;
38ba30ba 1933 }
dde7e6d1
AK		 1934
1935 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1936 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1937
1938 return rc;
38ba30ba
GN		 1939}
1940
e01991e7 1941static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1942{
dde7e6d1
AK		 1943 switch(ctxt->mode) {
1944 case X86EMUL_MODE_REAL:
7b105ca2 1945 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1946 case X86EMUL_MODE_VM86:
1947 case X86EMUL_MODE_PROT16:
1948 case X86EMUL_MODE_PROT32:
1949 case X86EMUL_MODE_PROT64:
c37eda13 1950 default:
dde7e6d1
AK		 1951 /* iret from protected mode unimplemented yet */
1952 return X86EMUL_UNHANDLEABLE;
c37eda13 1953 }
c37eda13
WY		 1954}
1955
d2f62766
TY		 1956static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1957{
d2f62766
TY		 1958 int rc;
1959 unsigned short sel;
1960
9dac77fa 1961 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1962
7b105ca2 1963 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1964 if (rc != X86EMUL_CONTINUE)
1965 return rc;
1966
9dac77fa
AK		 1967 ctxt->_eip = 0;
1968 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1969 return X86EMUL_CONTINUE;
1970}
1971
51187683 1972static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1973{
9dac77fa 1974 switch (ctxt->modrm_reg) {
8cdbd2c9 1975 case 0: /* rol */
a31b9cea 1976 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1977 break;
1978 case 1: /* ror */
a31b9cea 1979 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1980 break;
1981 case 2: /* rcl */
a31b9cea 1982 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1983 break;
1984 case 3: /* rcr */
a31b9cea 1985 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1986 break;
1987 case 4: /* sal/shl */
1988 case 6: /* sal/shl */
a31b9cea 1989 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1990 break;
1991 case 5: /* shr */
a31b9cea 1992 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1993 break;
1994 case 7: /* sar */
a31b9cea 1995 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1996 break;
1997 }
51187683 1998 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1999}
2000
3329ece1
AK		 2001static int em_not(struct x86_emulate_ctxt *ctxt)
2002{
2003 ctxt->dst.val = ~ctxt->dst.val;
2004 return X86EMUL_CONTINUE;
2005}
2006
2007static int em_neg(struct x86_emulate_ctxt *ctxt)
2008{
2009 emulate_1op(ctxt, "neg");
2010 return X86EMUL_CONTINUE;
2011}
2012
2013static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2014{
2015 u8 ex = 0;
2016
2017 emulate_1op_rax_rdx(ctxt, "mul", ex);
2018 return X86EMUL_CONTINUE;
2019}
2020
2021static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2022{
2023 u8 ex = 0;
2024
2025 emulate_1op_rax_rdx(ctxt, "imul", ex);
2026 return X86EMUL_CONTINUE;
2027}
2028
2029static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2030{
34d1f490 2031 u8 de = 0;
8cdbd2c9 2032
3329ece1
AK		 2033 emulate_1op_rax_rdx(ctxt, "div", de);
2034 if (de)
2035 return emulate_de(ctxt);
2036 return X86EMUL_CONTINUE;
2037}
2038
2039static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2040{
2041 u8 de = 0;
2042
2043 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2044 if (de)
2045 return emulate_de(ctxt);
8c5eee30 2046 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2047}
2048
51187683 2049static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2050{
4179bb02 2051 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2052
9dac77fa 2053 switch (ctxt->modrm_reg) {
8cdbd2c9 2054 case 0: /* inc */
d1eef45d 2055 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2056 break;
2057 case 1: /* dec */
d1eef45d 2058 emulate_1op(ctxt, "dec");
8cdbd2c9 2059 break;
d19292e4
MG		 2060 case 2: /* call near abs */ {
2061 long int old_eip;
9dac77fa
AK		 2062 old_eip = ctxt->_eip;
2063 ctxt->_eip = ctxt->src.val;
2064 ctxt->src.val = old_eip;
4487b3b4 2065 rc = em_push(ctxt);
d19292e4
MG		 2066 break;
2067 }
8cdbd2c9 2068 case 4: /* jmp abs */
9dac77fa 2069 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2070 break;
d2f62766
TY		 2071 case 5: /* jmp far */
2072 rc = em_jmp_far(ctxt);
2073 break;
8cdbd2c9 2074 case 6: /* push */
4487b3b4 2075 rc = em_push(ctxt);
8cdbd2c9 2076 break;
8cdbd2c9 2077 }
4179bb02 2078 return rc;
8cdbd2c9
LV		 2079}
2080
e0dac408 2081static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2082{
9dac77fa 2083 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2084
dd856efa
AK		 2085 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2086 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2087 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2088 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2089 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2090 } else {
dd856efa
AK		 2091 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2092 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2093
05f086f8 2094 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2095 }
1b30eaa8 2096 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2097}
2098
ebda02c2
TY		 2099static int em_ret(struct x86_emulate_ctxt *ctxt)
2100{
9dac77fa
AK		 2101 ctxt->dst.type = OP_REG;
2102 ctxt->dst.addr.reg = &ctxt->_eip;
2103 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2104 return em_pop(ctxt);
2105}
2106
e01991e7 2107static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2108{
a77ab5ea
AK		 2109 int rc;
2110 unsigned long cs;
2111
9dac77fa 2112 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2113 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2114 return rc;
9dac77fa
AK		 2115 if (ctxt->op_bytes == 4)
2116 ctxt->_eip = (u32)ctxt->_eip;
2117 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2118 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2119 return rc;
7b105ca2 2120 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2121 return rc;
2122}
2123
e940b5c2
TY		 2124static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2125{
2126 /* Save real source value, then compare EAX against destination. */
2127 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2128 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2129 emulate_2op_SrcV(ctxt, "cmp");
2130
2131 if (ctxt->eflags & EFLG_ZF) {
2132 /* Success: write back to memory. */
2133 ctxt->dst.val = ctxt->src.orig_val;
2134 } else {
2135 /* Failure: write the value we saw to EAX. */
2136 ctxt->dst.type = OP_REG;
dd856efa 2137 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2138 }
2139 return X86EMUL_CONTINUE;
2140}
2141
d4b4325f 2142static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2143{
d4b4325f 2144 int seg = ctxt->src2.val;
09b5f4d3
WY		 2145 unsigned short sel;
2146 int rc;
2147
9dac77fa 2148 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2149
7b105ca2 2150 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2151 if (rc != X86EMUL_CONTINUE)
2152 return rc;
2153
9dac77fa 2154 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2155 return rc;
2156}
2157
7b105ca2 2158static void
e66bb2cc 2159setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2160 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2161{
e66bb2cc 2162 cs->l = 0; /* will be adjusted later */
79168fd1 2163 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2164 cs->g = 1; /* 4kb granularity */
79168fd1 2165 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2166 cs->type = 0x0b; /* Read, Execute, Accessed */
2167 cs->s = 1;
2168 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2169 cs->p = 1;
2170 cs->d = 1;
99245b50 2171 cs->avl = 0;
e66bb2cc 2172
79168fd1
GN		 2173 set_desc_base(ss, 0); /* flat segment */
2174 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2175 ss->g = 1; /* 4kb granularity */
2176 ss->s = 1;
2177 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2178 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2179 ss->dpl = 0;
79168fd1 2180 ss->p = 1;
99245b50
GN		 2181 ss->l = 0;
2182 ss->avl = 0;
e66bb2cc
AP		 2183}
2184
1a18a69b
AK		 2185static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2186{
2187 u32 eax, ebx, ecx, edx;
2188
2189 eax = ecx = 0;
0017f93a
AK		 2190 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2191 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2192 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2193 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2194}
2195
c2226fc9
SB		 2196static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2197{
0225fb50 2198 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2199 u32 eax, ebx, ecx, edx;
2200
2201 /*
2202 * syscall should always be enabled in longmode - so only become
2203 * vendor specific (cpuid) if other modes are active...
2204 */
2205 if (ctxt->mode == X86EMUL_MODE_PROT64)
2206 return true;
2207
2208 eax = 0x00000000;
2209 ecx = 0x00000000;
0017f93a
AK		 2210 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2211 /*
2212 * Intel ("GenuineIntel")
2213 * remark: Intel CPUs only support "syscall" in 64bit
2214 * longmode. Also an 64bit guest with a
2215 * 32bit compat-app running will #UD !! While this
2216 * behaviour can be fixed (by emulating) into AMD
2217 * response - CPUs of AMD can't behave like Intel.
2218 */
2219 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2220 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2221 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2222 return false;
2223
2224 /* AMD ("AuthenticAMD") */
2225 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2226 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2227 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2228 return true;
2229
2230 /* AMD ("AMDisbetter!") */
2231 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2232 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2233 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2234 return true;
c2226fc9
SB		 2235
2236 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2237 return false;
2238}
2239
e01991e7 2240static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2241{
0225fb50 2242 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2243 struct desc_struct cs, ss;
e66bb2cc 2244 u64 msr_data;
79168fd1 2245 u16 cs_sel, ss_sel;
c2ad2bb3 2246 u64 efer = 0;
e66bb2cc
AP		 2247
2248 /* syscall is not available in real mode */
2e901c4c 2249 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2250 ctxt->mode == X86EMUL_MODE_VM86)
2251 return emulate_ud(ctxt);
e66bb2cc 2252
c2226fc9
SB		 2253 if (!(em_syscall_is_enabled(ctxt)))
2254 return emulate_ud(ctxt);
2255
c2ad2bb3 2256 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2257 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2258
c2226fc9
SB		 2259 if (!(efer & EFER_SCE))
2260 return emulate_ud(ctxt);
2261
717746e3 2262 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2263 msr_data >>= 32;
79168fd1
GN		 2264 cs_sel = (u16)(msr_data & 0xfffc);
2265 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2266
c2ad2bb3 2267 if (efer & EFER_LMA) {
79168fd1 2268 cs.d = 0;
e66bb2cc
AP		 2269 cs.l = 1;
2270 }
1aa36616
AK		 2271 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2272 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2273
dd856efa 2274 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2275 if (efer & EFER_LMA) {
e66bb2cc 2276#ifdef CONFIG_X86_64
dd856efa 2277 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2278
717746e3 2279 ops->get_msr(ctxt,
3fb1b5db
GN		 2280 ctxt->mode == X86EMUL_MODE_PROT64 ?
2281 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2282 ctxt->_eip = msr_data;
e66bb2cc 2283
717746e3 2284 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2285 ctxt->eflags &= ~(msr_data | EFLG_RF);
2286#endif
2287 } else {
2288 /* legacy mode */
717746e3 2289 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2290 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2291
2292 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2293 }
2294
e54cfa97 2295 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2296}
2297
e01991e7 2298static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2299{
0225fb50 2300 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2301 struct desc_struct cs, ss;
8c604352 2302 u64 msr_data;
79168fd1 2303 u16 cs_sel, ss_sel;
c2ad2bb3 2304 u64 efer = 0;
8c604352 2305
7b105ca2 2306 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2307 /* inject #GP if in real mode */
35d3d4a1
AK		 2308 if (ctxt->mode == X86EMUL_MODE_REAL)
2309 return emulate_gp(ctxt, 0);
8c604352 2310
1a18a69b
AK		 2311 /*
2312 * Not recognized on AMD in compat mode (but is recognized in legacy
2313 * mode).
2314 */
2315 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2316 && !vendor_intel(ctxt))
2317 return emulate_ud(ctxt);
2318
8c604352
AP		 2319 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2320 * Therefore, we inject an #UD.
2321 */
35d3d4a1
AK		 2322 if (ctxt->mode == X86EMUL_MODE_PROT64)
2323 return emulate_ud(ctxt);
8c604352 2324
7b105ca2 2325 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2326
717746e3 2327 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2328 switch (ctxt->mode) {
2329 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2330 if ((msr_data & 0xfffc) == 0x0)
2331 return emulate_gp(ctxt, 0);
8c604352
AP		 2332 break;
2333 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2334 if (msr_data == 0x0)
2335 return emulate_gp(ctxt, 0);
8c604352 2336 break;
9d1b39a9
GN		 2337 default:
2338 break;
8c604352
AP		 2339 }
2340
2341 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2342 cs_sel = (u16)msr_data;
2343 cs_sel &= ~SELECTOR_RPL_MASK;
2344 ss_sel = cs_sel + 8;
2345 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2346 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2347 cs.d = 0;
8c604352
AP		 2348 cs.l = 1;
2349 }
2350
1aa36616
AK		 2351 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2352 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2353
717746e3 2354 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2355 ctxt->_eip = msr_data;
8c604352 2356
717746e3 2357 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2358 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2359
e54cfa97 2360 return X86EMUL_CONTINUE;
8c604352
AP		 2361}
2362
e01991e7 2363static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2364{
0225fb50 2365 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2366 struct desc_struct cs, ss;
4668f050
AP		 2367 u64 msr_data;
2368 int usermode;
1249b96e 2369 u16 cs_sel = 0, ss_sel = 0;
4668f050 2370
a0044755
GN		 2371 /* inject #GP if in real mode or Virtual 8086 mode */
2372 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2373 ctxt->mode == X86EMUL_MODE_VM86)
2374 return emulate_gp(ctxt, 0);
4668f050 2375
7b105ca2 2376 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2377
9dac77fa 2378 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2379 usermode = X86EMUL_MODE_PROT64;
2380 else
2381 usermode = X86EMUL_MODE_PROT32;
2382
2383 cs.dpl = 3;
2384 ss.dpl = 3;
717746e3 2385 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2386 switch (usermode) {
2387 case X86EMUL_MODE_PROT32:
79168fd1 2388 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2389 if ((msr_data & 0xfffc) == 0x0)
2390 return emulate_gp(ctxt, 0);
79168fd1 2391 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2392 break;
2393 case X86EMUL_MODE_PROT64:
79168fd1 2394 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2395 if (msr_data == 0x0)
2396 return emulate_gp(ctxt, 0);
79168fd1
GN		 2397 ss_sel = cs_sel + 8;
2398 cs.d = 0;
4668f050
AP		 2399 cs.l = 1;
2400 break;
2401 }
79168fd1
GN		 2402 cs_sel |= SELECTOR_RPL_MASK;
2403 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2404
1aa36616
AK		 2405 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2406 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2407
dd856efa
AK		 2408 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2409 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2410
e54cfa97 2411 return X86EMUL_CONTINUE;
4668f050
AP		 2412}
2413
7b105ca2 2414static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2415{
2416 int iopl;
2417 if (ctxt->mode == X86EMUL_MODE_REAL)
2418 return false;
2419 if (ctxt->mode == X86EMUL_MODE_VM86)
2420 return true;
2421 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2422 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2423}
2424
2425static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2426 u16 port, u16 len)
2427{
0225fb50 2428 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2429 struct desc_struct tr_seg;
5601d05b 2430 u32 base3;
f850e2e6 2431 int r;
1aa36616 2432 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2433 unsigned mask = (1 << len) - 1;
5601d05b 2434 unsigned long base;
f850e2e6 2435
1aa36616 2436 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2437 if (!tr_seg.p)
f850e2e6 2438 return false;
79168fd1 2439 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2440 return false;
5601d05b
GN		 2441 base = get_desc_base(&tr_seg);
2442#ifdef CONFIG_X86_64
2443 base |= ((u64)base3) << 32;
2444#endif
0f65dd70 2445 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2446 if (r != X86EMUL_CONTINUE)
2447 return false;
79168fd1 2448 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2449 return false;
0f65dd70 2450 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2451 if (r != X86EMUL_CONTINUE)
2452 return false;
2453 if ((perm >> bit_idx) & mask)
2454 return false;
2455 return true;
2456}
2457
2458static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2459 u16 port, u16 len)
2460{
4fc40f07
GN		 2461 if (ctxt->perm_ok)
2462 return true;
2463
7b105ca2
TY		 2464 if (emulator_bad_iopl(ctxt))
2465 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2466 return false;
4fc40f07
GN		 2467
2468 ctxt->perm_ok = true;
2469
f850e2e6
GN		 2470 return true;
2471}
2472
38ba30ba 2473static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2474 struct tss_segment_16 *tss)
2475{
9dac77fa 2476 tss->ip = ctxt->_eip;
38ba30ba 2477 tss->flag = ctxt->eflags;
dd856efa
AK		 2478 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2479 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2480 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2481 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2482 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2483 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2484 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2485 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2486
1aa36616
AK		 2487 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2488 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2489 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2490 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2491 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2492}
2493
2494static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2495 struct tss_segment_16 *tss)
2496{
38ba30ba
GN		 2497 int ret;
2498
9dac77fa 2499 ctxt->_eip = tss->ip;
38ba30ba 2500 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2501 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2502 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2503 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2504 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2505 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2506 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2507 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2508 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2509
2510 /*
2511 * SDM says that segment selectors are loaded before segment
2512 * descriptors
2513 */
1aa36616
AK		 2514 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2515 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2516 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2517 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2518 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2519
2520 /*
fc058680 2521 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2522 * it is handled in a context of new task
2523 */
7b105ca2 2524 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2525 if (ret != X86EMUL_CONTINUE)
2526 return ret;
7b105ca2 2527 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2528 if (ret != X86EMUL_CONTINUE)
2529 return ret;
7b105ca2 2530 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2531 if (ret != X86EMUL_CONTINUE)
2532 return ret;
7b105ca2 2533 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2534 if (ret != X86EMUL_CONTINUE)
2535 return ret;
7b105ca2 2536 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2537 if (ret != X86EMUL_CONTINUE)
2538 return ret;
2539
2540 return X86EMUL_CONTINUE;
2541}
2542
2543static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2544 u16 tss_selector, u16 old_tss_sel,
2545 ulong old_tss_base, struct desc_struct *new_desc)
2546{
0225fb50 2547 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2548 struct tss_segment_16 tss_seg;
2549 int ret;
bcc55cba 2550 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2551
0f65dd70 2552 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2553 &ctxt->exception);
db297e3d 2554 if (ret != X86EMUL_CONTINUE)
38ba30ba 2555 /* FIXME: need to provide precise fault address */
38ba30ba 2556 return ret;
38ba30ba 2557
7b105ca2 2558 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2559
0f65dd70 2560 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2561 &ctxt->exception);
db297e3d 2562 if (ret != X86EMUL_CONTINUE)
38ba30ba 2563 /* FIXME: need to provide precise fault address */
38ba30ba 2564 return ret;
38ba30ba 2565
0f65dd70 2566 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2567 &ctxt->exception);
db297e3d 2568 if (ret != X86EMUL_CONTINUE)
38ba30ba 2569 /* FIXME: need to provide precise fault address */
38ba30ba 2570 return ret;
38ba30ba
GN		 2571
2572 if (old_tss_sel != 0xffff) {
2573 tss_seg.prev_task_link = old_tss_sel;
2574
0f65dd70 2575 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2576 &tss_seg.prev_task_link,
2577 sizeof tss_seg.prev_task_link,
0f65dd70 2578 &ctxt->exception);
db297e3d 2579 if (ret != X86EMUL_CONTINUE)
38ba30ba 2580 /* FIXME: need to provide precise fault address */
38ba30ba 2581 return ret;
38ba30ba
GN		 2582 }
2583
7b105ca2 2584 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2585}
2586
2587static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2588 struct tss_segment_32 *tss)
2589{
7b105ca2 2590 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2591 tss->eip = ctxt->_eip;
38ba30ba 2592 tss->eflags = ctxt->eflags;
dd856efa
AK		 2593 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2594 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2595 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2596 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2597 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2598 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2599 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2600 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2601
1aa36616
AK		 2602 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2603 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2604 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2605 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2606 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2607 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2608 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2609}
2610
2611static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2612 struct tss_segment_32 *tss)
2613{
38ba30ba
GN		 2614 int ret;
2615
7b105ca2 2616 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2617 return emulate_gp(ctxt, 0);
9dac77fa 2618 ctxt->_eip = tss->eip;
38ba30ba 2619 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2620
2621 /* General purpose registers */
dd856efa
AK		 2622 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2623 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2624 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2625 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2626 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2627 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2628 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2629 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2630
2631 /*
2632 * SDM says that segment selectors are loaded before segment
2633 * descriptors
2634 */
1aa36616
AK		 2635 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2636 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2637 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2638 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2639 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2640 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2641 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2642
4cee4798
KW		 2643 /*
2644 * If we're switching between Protected Mode and VM86, we need to make
2645 * sure to update the mode before loading the segment descriptors so
2646 * that the selectors are interpreted correctly.
2647 *
2648 * Need to get rflags to the vcpu struct immediately because it
2649 * influences the CPL which is checked at least when loading the segment
2650 * descriptors and when pushing an error code to the new kernel stack.
2651 *
2652 * TODO Introduce a separate ctxt->ops->set_cpl callback
2653 */
2654 if (ctxt->eflags & X86_EFLAGS_VM)
2655 ctxt->mode = X86EMUL_MODE_VM86;
2656 else
2657 ctxt->mode = X86EMUL_MODE_PROT32;
2658
2659 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2660
38ba30ba
GN		 2661 /*
2662 * Now load segment descriptors. If fault happenes at this stage
2663 * it is handled in a context of new task
2664 */
7b105ca2 2665 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2666 if (ret != X86EMUL_CONTINUE)
2667 return ret;
7b105ca2 2668 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2669 if (ret != X86EMUL_CONTINUE)
2670 return ret;
7b105ca2 2671 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2672 if (ret != X86EMUL_CONTINUE)
2673 return ret;
7b105ca2 2674 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2675 if (ret != X86EMUL_CONTINUE)
2676 return ret;
7b105ca2 2677 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2678 if (ret != X86EMUL_CONTINUE)
2679 return ret;
7b105ca2 2680 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2681 if (ret != X86EMUL_CONTINUE)
2682 return ret;
7b105ca2 2683 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2684 if (ret != X86EMUL_CONTINUE)
2685 return ret;
2686
2687 return X86EMUL_CONTINUE;
2688}
2689
2690static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2691 u16 tss_selector, u16 old_tss_sel,
2692 ulong old_tss_base, struct desc_struct *new_desc)
2693{
0225fb50 2694 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2695 struct tss_segment_32 tss_seg;
2696 int ret;
bcc55cba 2697 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2698
0f65dd70 2699 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2700 &ctxt->exception);
db297e3d 2701 if (ret != X86EMUL_CONTINUE)
38ba30ba 2702 /* FIXME: need to provide precise fault address */
38ba30ba 2703 return ret;
38ba30ba 2704
7b105ca2 2705 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2706
0f65dd70 2707 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2708 &ctxt->exception);
db297e3d 2709 if (ret != X86EMUL_CONTINUE)
38ba30ba 2710 /* FIXME: need to provide precise fault address */
38ba30ba 2711 return ret;
38ba30ba 2712
0f65dd70 2713 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2714 &ctxt->exception);
db297e3d 2715 if (ret != X86EMUL_CONTINUE)
38ba30ba 2716 /* FIXME: need to provide precise fault address */
38ba30ba 2717 return ret;
38ba30ba
GN		 2718
2719 if (old_tss_sel != 0xffff) {
2720 tss_seg.prev_task_link = old_tss_sel;
2721
0f65dd70 2722 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2723 &tss_seg.prev_task_link,
2724 sizeof tss_seg.prev_task_link,
0f65dd70 2725 &ctxt->exception);
db297e3d 2726 if (ret != X86EMUL_CONTINUE)
38ba30ba 2727 /* FIXME: need to provide precise fault address */
38ba30ba 2728 return ret;
38ba30ba
GN		 2729 }
2730
7b105ca2 2731 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2732}
2733
2734static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2735 u16 tss_selector, int idt_index, int reason,
e269fb21 2736 bool has_error_code, u32 error_code)
38ba30ba 2737{
0225fb50 2738 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2739 struct desc_struct curr_tss_desc, next_tss_desc;
2740 int ret;
1aa36616 2741 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2742 ulong old_tss_base =
4bff1e86 2743 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2744 u32 desc_limit;
e919464b 2745 ulong desc_addr;
38ba30ba
GN		 2746
2747 /* FIXME: old_tss_base == ~0 ? */
2748
e919464b 2749 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2750 if (ret != X86EMUL_CONTINUE)
2751 return ret;
e919464b 2752 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2753 if (ret != X86EMUL_CONTINUE)
2754 return ret;
2755
2756 /* FIXME: check that next_tss_desc is tss */
2757
7f3d35fd
KW		 2758 /*
2759 * Check privileges. The three cases are task switch caused by...
2760 *
2761 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2762 * 2. Exception/IRQ/iret: No check is performed
fc058680 2763 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2764 */
2765 if (reason == TASK_SWITCH_GATE) {
2766 if (idt_index != -1) {
2767 /* Software interrupts */
2768 struct desc_struct task_gate_desc;
2769 int dpl;
2770
2771 ret = read_interrupt_descriptor(ctxt, idt_index,
2772 &task_gate_desc);
2773 if (ret != X86EMUL_CONTINUE)
2774 return ret;
2775
2776 dpl = task_gate_desc.dpl;
2777 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2778 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2779 }
2780 } else if (reason != TASK_SWITCH_IRET) {
2781 int dpl = next_tss_desc.dpl;
2782 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2783 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2784 }
2785
7f3d35fd 2786
ceffb459
GN		 2787 desc_limit = desc_limit_scaled(&next_tss_desc);
2788 if (!next_tss_desc.p ||
2789 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2790 desc_limit < 0x2b)) {
54b8486f 2791 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2792 return X86EMUL_PROPAGATE_FAULT;
2793 }
2794
2795 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2796 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2797 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2798 }
2799
2800 if (reason == TASK_SWITCH_IRET)
2801 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2802
2803 /* set back link to prev task only if NT bit is set in eflags
fc058680 2804 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2805 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2806 old_tss_sel = 0xffff;
2807
2808 if (next_tss_desc.type & 8)
7b105ca2 2809 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2810 old_tss_base, &next_tss_desc);
2811 else
7b105ca2 2812 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2813 old_tss_base, &next_tss_desc);
0760d448
JK		 2814 if (ret != X86EMUL_CONTINUE)
2815 return ret;
38ba30ba
GN		 2816
2817 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2818 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2819
2820 if (reason != TASK_SWITCH_IRET) {
2821 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2822 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2823 }
2824
717746e3 2825 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2826 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2827
e269fb21 2828 if (has_error_code) {
9dac77fa
AK		 2829 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2830 ctxt->lock_prefix = 0;
2831 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2832 ret = em_push(ctxt);
e269fb21
JK		 2833 }
2834
38ba30ba
GN		 2835 return ret;
2836}
2837
2838int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2839 u16 tss_selector, int idt_index, int reason,
e269fb21 2840 bool has_error_code, u32 error_code)
38ba30ba 2841{
38ba30ba
GN		 2842 int rc;
2843
dd856efa 2844 invalidate_registers(ctxt);
9dac77fa
AK		 2845 ctxt->_eip = ctxt->eip;
2846 ctxt->dst.type = OP_NONE;
38ba30ba 2847
7f3d35fd 2848 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2849 has_error_code, error_code);
38ba30ba 2850
dd856efa 2851 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2852 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2853 writeback_registers(ctxt);
2854 }
38ba30ba 2855
a0c0ab2f 2856 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2857}
2858
f3bd64c6
GN		 2859static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2860 struct operand *op)
a682e354 2861{
b3356bf0 2862 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2863
dd856efa
AK		 2864 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2865 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2866}
2867
7af04fc0
AK		 2868static int em_das(struct x86_emulate_ctxt *ctxt)
2869{
7af04fc0
AK		 2870 u8 al, old_al;
2871 bool af, cf, old_cf;
2872
2873 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2874 al = ctxt->dst.val;
7af04fc0
AK		 2875
2876 old_al = al;
2877 old_cf = cf;
2878 cf = false;
2879 af = ctxt->eflags & X86_EFLAGS_AF;
2880 if ((al & 0x0f) > 9 || af) {
2881 al -= 6;
2882 cf = old_cf | (al >= 250);
2883 af = true;
2884 } else {
2885 af = false;
2886 }
2887 if (old_al > 0x99 || old_cf) {
2888 al -= 0x60;
2889 cf = true;
2890 }
2891
9dac77fa 2892 ctxt->dst.val = al;
7af04fc0 2893 /* Set PF, ZF, SF */
9dac77fa
AK		 2894 ctxt->src.type = OP_IMM;
2895 ctxt->src.val = 0;
2896 ctxt->src.bytes = 1;
a31b9cea 2897 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2898 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2899 if (cf)
2900 ctxt->eflags |= X86_EFLAGS_CF;
2901 if (af)
2902 ctxt->eflags |= X86_EFLAGS_AF;
2903 return X86EMUL_CONTINUE;
2904}
2905
7f662273
GN		 2906static int em_aad(struct x86_emulate_ctxt *ctxt)
2907{
2908 u8 al = ctxt->dst.val & 0xff;
2909 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2910
2911 al = (al + (ah * ctxt->src.val)) & 0xff;
2912
2913 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2914
2915 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2916
2917 if (!al)
2918 ctxt->eflags |= X86_EFLAGS_ZF;
2919 if (!(al & 1))
2920 ctxt->eflags |= X86_EFLAGS_PF;
2921 if (al & 0x80)
2922 ctxt->eflags |= X86_EFLAGS_SF;
2923
2924 return X86EMUL_CONTINUE;
2925}
2926
d4ddafcd
TY		 2927static int em_call(struct x86_emulate_ctxt *ctxt)
2928{
2929 long rel = ctxt->src.val;
2930
2931 ctxt->src.val = (unsigned long)ctxt->_eip;
2932 jmp_rel(ctxt, rel);
2933 return em_push(ctxt);
2934}
2935
0ef753b8
AK		 2936static int em_call_far(struct x86_emulate_ctxt *ctxt)
2937{
0ef753b8
AK		 2938 u16 sel, old_cs;
2939 ulong old_eip;
2940 int rc;
2941
1aa36616 2942 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2943 old_eip = ctxt->_eip;
0ef753b8 2944
9dac77fa 2945 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2946 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2947 return X86EMUL_CONTINUE;
2948
9dac77fa
AK		 2949 ctxt->_eip = 0;
2950 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2951
9dac77fa 2952 ctxt->src.val = old_cs;
4487b3b4 2953 rc = em_push(ctxt);
0ef753b8
AK		 2954 if (rc != X86EMUL_CONTINUE)
2955 return rc;
2956
9dac77fa 2957 ctxt->src.val = old_eip;
4487b3b4 2958 return em_push(ctxt);
0ef753b8
AK		 2959}
2960
40ece7c7
AK		 2961static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2962{
40ece7c7
AK		 2963 int rc;
2964
9dac77fa
AK		 2965 ctxt->dst.type = OP_REG;
2966 ctxt->dst.addr.reg = &ctxt->_eip;
2967 ctxt->dst.bytes = ctxt->op_bytes;
2968 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2969 if (rc != X86EMUL_CONTINUE)
2970 return rc;
5ad105e5 2971 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2972 return X86EMUL_CONTINUE;
2973}
2974
d67fc27a
TY		 2975static int em_add(struct x86_emulate_ctxt *ctxt)
2976{
a31b9cea 2977 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2978 return X86EMUL_CONTINUE;
2979}
2980
2981static int em_or(struct x86_emulate_ctxt *ctxt)
2982{
a31b9cea 2983 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2984 return X86EMUL_CONTINUE;
2985}
2986
2987static int em_adc(struct x86_emulate_ctxt *ctxt)
2988{
a31b9cea 2989 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2990 return X86EMUL_CONTINUE;
2991}
2992
2993static int em_sbb(struct x86_emulate_ctxt *ctxt)
2994{
a31b9cea 2995 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2996 return X86EMUL_CONTINUE;
2997}
2998
2999static int em_and(struct x86_emulate_ctxt *ctxt)
3000{
a31b9cea 3001 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 3002 return X86EMUL_CONTINUE;
3003}
3004
3005static int em_sub(struct x86_emulate_ctxt *ctxt)
3006{
a31b9cea 3007 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 3008 return X86EMUL_CONTINUE;
3009}
3010
3011static int em_xor(struct x86_emulate_ctxt *ctxt)
3012{
a31b9cea 3013 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 3014 return X86EMUL_CONTINUE;
3015}
3016
3017static int em_cmp(struct x86_emulate_ctxt *ctxt)
3018{
a31b9cea 3019 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 3020 /* Disable writeback. */
9dac77fa 3021 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 3022 return X86EMUL_CONTINUE;
3023}
3024
9f21ca59
TY		 3025static int em_test(struct x86_emulate_ctxt *ctxt)
3026{
a31b9cea 3027 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 3028 /* Disable writeback. */
3029 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 3030 return X86EMUL_CONTINUE;
3031}
3032
e4f973ae
TY		 3033static int em_xchg(struct x86_emulate_ctxt *ctxt)
3034{
e4f973ae 3035 /* Write back the register source. */
9dac77fa
AK		 3036 ctxt->src.val = ctxt->dst.val;
3037 write_register_operand(&ctxt->src);
e4f973ae
TY		 3038
3039 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3040 ctxt->dst.val = ctxt->src.orig_val;
3041 ctxt->lock_prefix = 1;
e4f973ae
TY		 3042 return X86EMUL_CONTINUE;
3043}
3044
5c82aa29 3045static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 3046{
a31b9cea 3047 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 3048 return X86EMUL_CONTINUE;
3049}
3050
5c82aa29
AK		 3051static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3052{
9dac77fa 3053 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3054 return em_imul(ctxt);
3055}
3056
61429142
AK		 3057static int em_cwd(struct x86_emulate_ctxt *ctxt)
3058{
9dac77fa
AK		 3059 ctxt->dst.type = OP_REG;
3060 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3061 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3062 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3063
3064 return X86EMUL_CONTINUE;
3065}
3066
48bb5d3c
AK		 3067static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3068{
48bb5d3c
AK		 3069 u64 tsc = 0;
3070
717746e3 3071 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3072 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3073 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3074 return X86EMUL_CONTINUE;
3075}
3076
222d21aa
AK		 3077static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3078{
3079 u64 pmc;
3080
dd856efa 3081 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3082 return emulate_gp(ctxt, 0);
dd856efa
AK		 3083 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3084 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3085 return X86EMUL_CONTINUE;
3086}
3087
b9eac5f4
AK		 3088static int em_mov(struct x86_emulate_ctxt *ctxt)
3089{
49597d81 3090 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3091 return X86EMUL_CONTINUE;
3092}
3093
bc00f8d2
TY		 3094static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3095{
3096 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3097 return emulate_gp(ctxt, 0);
3098
3099 /* Disable writeback. */
3100 ctxt->dst.type = OP_NONE;
3101 return X86EMUL_CONTINUE;
3102}
3103
3104static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3105{
3106 unsigned long val;
3107
3108 if (ctxt->mode == X86EMUL_MODE_PROT64)
3109 val = ctxt->src.val & ~0ULL;
3110 else
3111 val = ctxt->src.val & ~0U;
3112
3113 /* #UD condition is already handled. */
3114 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3115 return emulate_gp(ctxt, 0);
3116
3117 /* Disable writeback. */
3118 ctxt->dst.type = OP_NONE;
3119 return X86EMUL_CONTINUE;
3120}
3121
e1e210b0
TY		 3122static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3123{
3124 u64 msr_data;
3125
dd856efa
AK		 3126 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3127 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3128 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3129 return emulate_gp(ctxt, 0);
3130
3131 return X86EMUL_CONTINUE;
3132}
3133
3134static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3135{
3136 u64 msr_data;
3137
dd856efa 3138 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3139 return emulate_gp(ctxt, 0);
3140
dd856efa
AK		 3141 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3142 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3143 return X86EMUL_CONTINUE;
3144}
3145
1bd5f469
TY		 3146static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3147{
9dac77fa 3148 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3149 return emulate_ud(ctxt);
3150
9dac77fa 3151 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3152 return X86EMUL_CONTINUE;
3153}
3154
3155static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3156{
9dac77fa 3157 u16 sel = ctxt->src.val;
1bd5f469 3158
9dac77fa 3159 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3160 return emulate_ud(ctxt);
3161
9dac77fa 3162 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3163 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3164
3165 /* Disable writeback. */
9dac77fa
AK		 3166 ctxt->dst.type = OP_NONE;
3167 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3168}
3169
a14e579f
AK		 3170static int em_lldt(struct x86_emulate_ctxt *ctxt)
3171{
3172 u16 sel = ctxt->src.val;
3173
3174 /* Disable writeback. */
3175 ctxt->dst.type = OP_NONE;
3176 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3177}
3178
80890006
AK		 3179static int em_ltr(struct x86_emulate_ctxt *ctxt)
3180{
3181 u16 sel = ctxt->src.val;
3182
3183 /* Disable writeback. */
3184 ctxt->dst.type = OP_NONE;
3185 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3186}
3187
38503911
AK		 3188static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3189{
9fa088f4
AK		 3190 int rc;
3191 ulong linear;
3192
9dac77fa 3193 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3194 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3195 ctxt->ops->invlpg(ctxt, linear);
38503911 3196 /* Disable writeback. */
9dac77fa 3197 ctxt->dst.type = OP_NONE;
38503911
AK		 3198 return X86EMUL_CONTINUE;
3199}
3200
2d04a05b
AK		 3201static int em_clts(struct x86_emulate_ctxt *ctxt)
3202{
3203 ulong cr0;
3204
3205 cr0 = ctxt->ops->get_cr(ctxt, 0);
3206 cr0 &= ~X86_CR0_TS;
3207 ctxt->ops->set_cr(ctxt, 0, cr0);
3208 return X86EMUL_CONTINUE;
3209}
3210
26d05cc7
AK		 3211static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3212{
26d05cc7
AK		 3213 int rc;
3214
9dac77fa 3215 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3216 return X86EMUL_UNHANDLEABLE;
3217
3218 rc = ctxt->ops->fix_hypercall(ctxt);
3219 if (rc != X86EMUL_CONTINUE)
3220 return rc;
3221
3222 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3223 ctxt->_eip = ctxt->eip;
26d05cc7 3224 /* Disable writeback. */
9dac77fa 3225 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3226 return X86EMUL_CONTINUE;
3227}
3228
96051572
AK		 3229static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3230 void (*get)(struct x86_emulate_ctxt *ctxt,
3231 struct desc_ptr *ptr))
3232{
3233 struct desc_ptr desc_ptr;
3234
3235 if (ctxt->mode == X86EMUL_MODE_PROT64)
3236 ctxt->op_bytes = 8;
3237 get(ctxt, &desc_ptr);
3238 if (ctxt->op_bytes == 2) {
3239 ctxt->op_bytes = 4;
3240 desc_ptr.address &= 0x00ffffff;
3241 }
3242 /* Disable writeback. */
3243 ctxt->dst.type = OP_NONE;
3244 return segmented_write(ctxt, ctxt->dst.addr.mem,
3245 &desc_ptr, 2 + ctxt->op_bytes);
3246}
3247
3248static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3249{
3250 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3251}
3252
3253static int em_sidt(struct x86_emulate_ctxt *ctxt)
3254{
3255 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3256}
3257
26d05cc7
AK		 3258static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3259{
26d05cc7
AK		 3260 struct desc_ptr desc_ptr;
3261 int rc;
3262
510425ff
AK		 3263 if (ctxt->mode == X86EMUL_MODE_PROT64)
3264 ctxt->op_bytes = 8;
9dac77fa 3265 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3266 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3267 ctxt->op_bytes);
26d05cc7
AK		 3268 if (rc != X86EMUL_CONTINUE)
3269 return rc;
3270 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3271 /* Disable writeback. */
9dac77fa 3272 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3273 return X86EMUL_CONTINUE;
3274}
3275
5ef39c71 3276static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3277{
26d05cc7
AK		 3278 int rc;
3279
5ef39c71
AK		 3280 rc = ctxt->ops->fix_hypercall(ctxt);
3281
26d05cc7 3282 /* Disable writeback. */
9dac77fa 3283 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3284 return rc;
3285}
3286
3287static int em_lidt(struct x86_emulate_ctxt *ctxt)
3288{
26d05cc7
AK		 3289 struct desc_ptr desc_ptr;
3290 int rc;
3291
510425ff
AK		 3292 if (ctxt->mode == X86EMUL_MODE_PROT64)
3293 ctxt->op_bytes = 8;
9dac77fa 3294 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3295 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3296 ctxt->op_bytes);
26d05cc7
AK		 3297 if (rc != X86EMUL_CONTINUE)
3298 return rc;
3299 ctxt->ops->set_idt(ctxt, &desc_ptr);
3300 /* Disable writeback. */
9dac77fa 3301 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3302 return X86EMUL_CONTINUE;
3303}
3304
3305static int em_smsw(struct x86_emulate_ctxt *ctxt)
3306{
9dac77fa
AK		 3307 ctxt->dst.bytes = 2;
3308 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3309 return X86EMUL_CONTINUE;
3310}
3311
3312static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3313{
26d05cc7 3314 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3315 | (ctxt->src.val & 0x0f));
3316 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3317 return X86EMUL_CONTINUE;
3318}
3319
d06e03ad
TY		 3320static int em_loop(struct x86_emulate_ctxt *ctxt)
3321{
dd856efa
AK		 3322 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3323 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3324 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3325 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3326
3327 return X86EMUL_CONTINUE;
3328}
3329
3330static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3331{
dd856efa 3332 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3333 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3334
3335 return X86EMUL_CONTINUE;
3336}
3337
d7841a4b
TY		 3338static int em_in(struct x86_emulate_ctxt *ctxt)
3339{
3340 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3341 &ctxt->dst.val))
3342 return X86EMUL_IO_NEEDED;
3343
3344 return X86EMUL_CONTINUE;
3345}
3346
3347static int em_out(struct x86_emulate_ctxt *ctxt)
3348{
3349 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3350 &ctxt->src.val, 1);
3351 /* Disable writeback. */
3352 ctxt->dst.type = OP_NONE;
3353 return X86EMUL_CONTINUE;
3354}
3355
f411e6cd
TY		 3356static int em_cli(struct x86_emulate_ctxt *ctxt)
3357{
3358 if (emulator_bad_iopl(ctxt))
3359 return emulate_gp(ctxt, 0);
3360
3361 ctxt->eflags &= ~X86_EFLAGS_IF;
3362 return X86EMUL_CONTINUE;
3363}
3364
3365static int em_sti(struct x86_emulate_ctxt *ctxt)
3366{
3367 if (emulator_bad_iopl(ctxt))
3368 return emulate_gp(ctxt, 0);
3369
3370 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3371 ctxt->eflags |= X86_EFLAGS_IF;
3372 return X86EMUL_CONTINUE;
3373}
3374
ce7faab2
TY		 3375static int em_bt(struct x86_emulate_ctxt *ctxt)
3376{
3377 /* Disable writeback. */
3378 ctxt->dst.type = OP_NONE;
3379 /* only subword offset */
3380 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3381
3382 emulate_2op_SrcV_nobyte(ctxt, "bt");
3383 return X86EMUL_CONTINUE;
3384}
3385
3386static int em_bts(struct x86_emulate_ctxt *ctxt)
3387{
3388 emulate_2op_SrcV_nobyte(ctxt, "bts");
3389 return X86EMUL_CONTINUE;
3390}
3391
3392static int em_btr(struct x86_emulate_ctxt *ctxt)
3393{
3394 emulate_2op_SrcV_nobyte(ctxt, "btr");
3395 return X86EMUL_CONTINUE;
3396}
3397
3398static int em_btc(struct x86_emulate_ctxt *ctxt)
3399{
3400 emulate_2op_SrcV_nobyte(ctxt, "btc");
3401 return X86EMUL_CONTINUE;
3402}
3403
ff227392
TY		 3404static int em_bsf(struct x86_emulate_ctxt *ctxt)
3405{
d54e4237 3406 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3407 return X86EMUL_CONTINUE;
3408}
3409
3410static int em_bsr(struct x86_emulate_ctxt *ctxt)
3411{
d54e4237 3412 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3413 return X86EMUL_CONTINUE;
3414}
3415
6d6eede4
AK		 3416static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3417{
3418 u32 eax, ebx, ecx, edx;
3419
dd856efa
AK		 3420 eax = reg_read(ctxt, VCPU_REGS_RAX);
3421 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3422 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3423 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3424 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3425 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3426 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3427 return X86EMUL_CONTINUE;
3428}
3429
2dd7caa0
AK		 3430static int em_lahf(struct x86_emulate_ctxt *ctxt)
3431{
dd856efa
AK		 3432 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3433 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3434 return X86EMUL_CONTINUE;
3435}
3436
9299836e
AK		 3437static int em_bswap(struct x86_emulate_ctxt *ctxt)
3438{
3439 switch (ctxt->op_bytes) {
3440#ifdef CONFIG_X86_64
3441 case 8:
3442 asm("bswap %0" : "+r"(ctxt->dst.val));
3443 break;
3444#endif
3445 default:
3446 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3447 break;
3448 }
3449 return X86EMUL_CONTINUE;
3450}
3451
cfec82cb
JR		 3452static bool valid_cr(int nr)
3453{
3454 switch (nr) {
3455 case 0:
3456 case 2 ... 4:
3457 case 8:
3458 return true;
3459 default:
3460 return false;
3461 }
3462}
3463
3464static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3465{
9dac77fa 3466 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3467 return emulate_ud(ctxt);
3468
3469 return X86EMUL_CONTINUE;
3470}
3471
3472static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3473{
9dac77fa
AK		 3474 u64 new_val = ctxt->src.val64;
3475 int cr = ctxt->modrm_reg;
c2ad2bb3 3476 u64 efer = 0;
cfec82cb
JR		 3477
3478 static u64 cr_reserved_bits[] = {
3479 0xffffffff00000000ULL,
3480 0, 0, 0, /* CR3 checked later */
3481 CR4_RESERVED_BITS,
3482 0, 0, 0,
3483 CR8_RESERVED_BITS,
3484 };
3485
3486 if (!valid_cr(cr))
3487 return emulate_ud(ctxt);
3488
3489 if (new_val & cr_reserved_bits[cr])
3490 return emulate_gp(ctxt, 0);
3491
3492 switch (cr) {
3493 case 0: {
c2ad2bb3 3494 u64 cr4;
cfec82cb
JR		 3495 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3496 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3497 return emulate_gp(ctxt, 0);
3498
717746e3
AK		 3499 cr4 = ctxt->ops->get_cr(ctxt, 4);
3500 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3501
3502 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3503 !(cr4 & X86_CR4_PAE))
3504 return emulate_gp(ctxt, 0);
3505
3506 break;
3507 }
3508 case 3: {
3509 u64 rsvd = 0;
3510
c2ad2bb3
AK		 3511 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3512 if (efer & EFER_LMA)
cfec82cb 3513 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3514 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3515 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3516 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3517 rsvd = CR3_NONPAE_RESERVED_BITS;
3518
3519 if (new_val & rsvd)
3520 return emulate_gp(ctxt, 0);
3521
3522 break;
3523 }
3524 case 4: {
717746e3 3525 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3526
3527 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3528 return emulate_gp(ctxt, 0);
3529
3530 break;
3531 }
3532 }
3533
3534 return X86EMUL_CONTINUE;
3535}
3536
3b88e41a
JR		 3537static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3538{
3539 unsigned long dr7;
3540
717746e3 3541 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3542
3543 /* Check if DR7.Global_Enable is set */
3544 return dr7 & (1 << 13);
3545}
3546
3547static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3548{
9dac77fa 3549 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3550 u64 cr4;
3551
3552 if (dr > 7)
3553 return emulate_ud(ctxt);
3554
717746e3 3555 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3556 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3557 return emulate_ud(ctxt);
3558
3559 if (check_dr7_gd(ctxt))
3560 return emulate_db(ctxt);
3561
3562 return X86EMUL_CONTINUE;
3563}
3564
3565static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3566{
9dac77fa
AK		 3567 u64 new_val = ctxt->src.val64;
3568 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3569
3570 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3571 return emulate_gp(ctxt, 0);
3572
3573 return check_dr_read(ctxt);
3574}
3575
01de8b09
JR		 3576static int check_svme(struct x86_emulate_ctxt *ctxt)
3577{
3578 u64 efer;
3579
717746e3 3580 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3581
3582 if (!(efer & EFER_SVME))
3583 return emulate_ud(ctxt);
3584
3585 return X86EMUL_CONTINUE;
3586}
3587
3588static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3589{
dd856efa 3590 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3591
3592 /* Valid physical address? */
d4224449 3593 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3594 return emulate_gp(ctxt, 0);
3595
3596 return check_svme(ctxt);
3597}
3598
d7eb8203
JR		 3599static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3600{
717746e3 3601 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3602
717746e3 3603 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3604 return emulate_ud(ctxt);
3605
3606 return X86EMUL_CONTINUE;
3607}
3608
8061252e
JR		 3609static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3610{
717746e3 3611 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3612 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3613
717746e3 3614 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3615 (rcx > 3))
3616 return emulate_gp(ctxt, 0);
3617
3618 return X86EMUL_CONTINUE;
3619}
3620
f6511935
JR		 3621static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3622{
9dac77fa
AK		 3623 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3624 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3625 return emulate_gp(ctxt, 0);
3626
3627 return X86EMUL_CONTINUE;
3628}
3629
3630static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3631{
9dac77fa
AK		 3632 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3633 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3634 return emulate_gp(ctxt, 0);
3635
3636 return X86EMUL_CONTINUE;
3637}
3638
73fba5f4 3639#define D(_y) { .flags = (_y) }
c4f035c6 3640#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3641#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3642 .check_perm = (_p) }
73fba5f4 3643#define N D(0)
01de8b09 3644#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3645#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3646#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3647#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3648#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3649#define II(_f, _e, _i) \
3650 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3651#define IIP(_f, _e, _i, _p) \
3652 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3653 .check_perm = (_p) }
aa97bb48 3654#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3655
8d8f4e9f 3656#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3657#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3658#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3659#define I2bvIP(_f, _e, _i, _p) \
3660 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3661
d67fc27a
TY		 3662#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3663 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3664 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3665
fd0a0d82 3666static const struct opcode group7_rm1[] = {
1c2545be
TY		 3667 DI(SrcNone | Priv, monitor),
3668 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3669 N, N, N, N, N, N,
3670};
3671
fd0a0d82 3672static const struct opcode group7_rm3[] = {
1c2545be
TY		 3673 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3674 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3675 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3676 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3677 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3678 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3679 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3680 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3681};
6230f7fc 3682
fd0a0d82 3683static const struct opcode group7_rm7[] = {
d7eb8203 3684 N,
1c2545be 3685 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3686 N, N, N, N, N, N,
3687};
d67fc27a 3688
fd0a0d82 3689static const struct opcode group1[] = {
d67fc27a 3690 I(Lock, em_add),
d5ae7ce8 3691 I(Lock | PageTable, em_or),
d67fc27a
TY		 3692 I(Lock, em_adc),
3693 I(Lock, em_sbb),
d5ae7ce8 3694 I(Lock | PageTable, em_and),
d67fc27a
TY		 3695 I(Lock, em_sub),
3696 I(Lock, em_xor),
3697 I(0, em_cmp),
73fba5f4
AK		 3698};
3699
fd0a0d82 3700static const struct opcode group1A[] = {
1c2545be 3701 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3702};
3703
fd0a0d82 3704static const struct opcode group3[] = {
1c2545be
TY		 3705 I(DstMem | SrcImm, em_test),
3706 I(DstMem | SrcImm, em_test),
3707 I(DstMem | SrcNone | Lock, em_not),
3708 I(DstMem | SrcNone | Lock, em_neg),
3709 I(SrcMem, em_mul_ex),
3710 I(SrcMem, em_imul_ex),
3711 I(SrcMem, em_div_ex),
3712 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3713};
3714
fd0a0d82 3715static const struct opcode group4[] = {
1c2545be
TY		 3716 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3717 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3718 N, N, N, N, N, N,
3719};
3720
fd0a0d82 3721static const struct opcode group5[] = {
1c2545be
TY		 3722 I(DstMem | SrcNone | Lock, em_grp45),
3723 I(DstMem | SrcNone | Lock, em_grp45),
3724 I(SrcMem | Stack, em_grp45),
3725 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3726 I(SrcMem | Stack, em_grp45),
3727 I(SrcMemFAddr | ImplicitOps, em_grp45),
3728 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3729};
3730
fd0a0d82 3731static const struct opcode group6[] = {
1c2545be
TY		 3732 DI(Prot, sldt),
3733 DI(Prot, str),
a14e579f 3734 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3735 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3736 N, N, N, N,
3737};
3738
fd0a0d82 3739static const struct group_dual group7 = { {
96051572
AK		 3740 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3741 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3742 II(SrcMem | Priv, em_lgdt, lgdt),
3743 II(SrcMem | Priv, em_lidt, lidt),
3744 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3745 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3746 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3747}, {
1c2545be 3748 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3749 EXT(0, group7_rm1),
01de8b09 3750 N, EXT(0, group7_rm3),
1c2545be
TY		 3751 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3752 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3753 EXT(0, group7_rm7),
73fba5f4
AK		 3754} };
3755
fd0a0d82 3756static const struct opcode group8[] = {
73fba5f4 3757 N, N, N, N,
1c2545be
TY		 3758 I(DstMem | SrcImmByte, em_bt),
3759 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3760 I(DstMem | SrcImmByte | Lock, em_btr),
3761 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3762};
3763
fd0a0d82 3764static const struct group_dual group9 = { {
1c2545be 3765 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3766}, {
3767 N, N, N, N, N, N, N, N,
3768} };
3769
fd0a0d82 3770static const struct opcode group11[] = {
1c2545be 3771 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3772 X7(D(Undefined)),
a4d4a7c1
AK		 3773};
3774
fd0a0d82 3775static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3776 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3777};
3778
fd0a0d82 3779static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3780 I(0, em_mov), N, N, N,
3781};
3782
045a282c
GN		 3783static const struct escape escape_d9 = { {
3784 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3785}, {
3786 /* 0xC0 - 0xC7 */
3787 N, N, N, N, N, N, N, N,
3788 /* 0xC8 - 0xCF */
3789 N, N, N, N, N, N, N, N,
3790 /* 0xD0 - 0xC7 */
3791 N, N, N, N, N, N, N, N,
3792 /* 0xD8 - 0xDF */
3793 N, N, N, N, N, N, N, N,
3794 /* 0xE0 - 0xE7 */
3795 N, N, N, N, N, N, N, N,
3796 /* 0xE8 - 0xEF */
3797 N, N, N, N, N, N, N, N,
3798 /* 0xF0 - 0xF7 */
3799 N, N, N, N, N, N, N, N,
3800 /* 0xF8 - 0xFF */
3801 N, N, N, N, N, N, N, N,
3802} };
3803
3804static const struct escape escape_db = { {
3805 N, N, N, N, N, N, N, N,
3806}, {
3807 /* 0xC0 - 0xC7 */
3808 N, N, N, N, N, N, N, N,
3809 /* 0xC8 - 0xCF */
3810 N, N, N, N, N, N, N, N,
3811 /* 0xD0 - 0xC7 */
3812 N, N, N, N, N, N, N, N,
3813 /* 0xD8 - 0xDF */
3814 N, N, N, N, N, N, N, N,
3815 /* 0xE0 - 0xE7 */
3816 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3817 /* 0xE8 - 0xEF */
3818 N, N, N, N, N, N, N, N,
3819 /* 0xF0 - 0xF7 */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xF8 - 0xFF */
3822 N, N, N, N, N, N, N, N,
3823} };
3824
3825static const struct escape escape_dd = { {
3826 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3827}, {
3828 /* 0xC0 - 0xC7 */
3829 N, N, N, N, N, N, N, N,
3830 /* 0xC8 - 0xCF */
3831 N, N, N, N, N, N, N, N,
3832 /* 0xD0 - 0xC7 */
3833 N, N, N, N, N, N, N, N,
3834 /* 0xD8 - 0xDF */
3835 N, N, N, N, N, N, N, N,
3836 /* 0xE0 - 0xE7 */
3837 N, N, N, N, N, N, N, N,
3838 /* 0xE8 - 0xEF */
3839 N, N, N, N, N, N, N, N,
3840 /* 0xF0 - 0xF7 */
3841 N, N, N, N, N, N, N, N,
3842 /* 0xF8 - 0xFF */
3843 N, N, N, N, N, N, N, N,
3844} };
3845
fd0a0d82 3846static const struct opcode opcode_table[256] = {
73fba5f4 3847 /* 0x00 - 0x07 */
d67fc27a 3848 I6ALU(Lock, em_add),
1cd196ea
AK		 3849 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3850 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3851 /* 0x08 - 0x0F */
d5ae7ce8 3852 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3853 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3854 N,
73fba5f4 3855 /* 0x10 - 0x17 */
d67fc27a 3856 I6ALU(Lock, em_adc),
1cd196ea
AK		 3857 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3858 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3859 /* 0x18 - 0x1F */
d67fc27a 3860 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3861 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3862 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3863 /* 0x20 - 0x27 */
d5ae7ce8 3864 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3865 /* 0x28 - 0x2F */
d67fc27a 3866 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3867 /* 0x30 - 0x37 */
d67fc27a 3868 I6ALU(Lock, em_xor), N, N,
73fba5f4 3869 /* 0x38 - 0x3F */
d67fc27a 3870 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3871 /* 0x40 - 0x4F */
3872 X16(D(DstReg)),
3873 /* 0x50 - 0x57 */
63540382 3874 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3875 /* 0x58 - 0x5F */
c54fe504 3876 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3877 /* 0x60 - 0x67 */
b96a7fad
TY		 3878 I(ImplicitOps | Stack | No64, em_pusha),
3879 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3880 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3881 N, N, N, N,
3882 /* 0x68 - 0x6F */
d46164db
AK		 3883 I(SrcImm | Mov | Stack, em_push),
3884 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3885 I(SrcImmByte | Mov | Stack, em_push),
3886 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3887 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3888 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3889 /* 0x70 - 0x7F */
3890 X16(D(SrcImmByte)),
3891 /* 0x80 - 0x87 */
1c2545be
TY		 3892 G(ByteOp | DstMem | SrcImm, group1),
3893 G(DstMem | SrcImm, group1),
3894 G(ByteOp | DstMem | SrcImm | No64, group1),
3895 G(DstMem | SrcImmByte, group1),
9f21ca59 3896 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3897 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3898 /* 0x88 - 0x8F */
d5ae7ce8 3899 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3900 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3901 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3902 D(ModRM | SrcMem | NoAccess | DstReg),
3903 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3904 G(0, group1A),
73fba5f4 3905 /* 0x90 - 0x97 */
bf608f88 3906 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3907 /* 0x98 - 0x9F */
61429142 3908 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3909 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3910 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3911 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3912 /* 0xA0 - 0xA7 */
b9eac5f4 3913 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3914 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3915 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3916 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3917 /* 0xA8 - 0xAF */
9f21ca59 3918 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3919 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3920 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3921 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3922 /* 0xB0 - 0xB7 */
b9eac5f4 3923 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3924 /* 0xB8 - 0xBF */
5e2c6883 3925 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3926 /* 0xC0 - 0xC7 */
d2c6c7ad 3927 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3928 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3929 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3930 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3931 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3932 G(ByteOp, group11), G(0, group11),
73fba5f4 3933 /* 0xC8 - 0xCF */
612e89f0
AK		 3934 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3935 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3936 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3937 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3938 /* 0xD0 - 0xD7 */
d2c6c7ad 3939 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3940 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3941 /* 0xD8 - 0xDF */
045a282c 3942 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3943 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3944 X3(I(SrcImmByte, em_loop)),
3945 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3946 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3947 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3948 /* 0xE8 - 0xEF */
d4ddafcd 3949 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3950 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3951 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3952 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3953 /* 0xF0 - 0xF7 */
bf608f88 3954 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3955 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3956 G(ByteOp, group3), G(0, group3),
73fba5f4 3957 /* 0xF8 - 0xFF */
f411e6cd
TY		 3958 D(ImplicitOps), D(ImplicitOps),
3959 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3960 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3961};
3962
fd0a0d82 3963static const struct opcode twobyte_table[256] = {
73fba5f4 3964 /* 0x00 - 0x0F */
dee6bb70 3965 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3966 N, I(ImplicitOps | VendorSpecific, em_syscall),
3967 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3968 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3969 N, D(ImplicitOps | ModRM), N, N,
3970 /* 0x10 - 0x1F */
3971 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3972 /* 0x20 - 0x2F */
cfec82cb 3973 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3974 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3975 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3976 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3977 N, N, N, N,
3e114eb4
AK		 3978 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3979 N, N, N, N,
73fba5f4 3980 /* 0x30 - 0x3F */
e1e210b0 3981 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3982 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3983 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3984 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3985 I(ImplicitOps | VendorSpecific, em_sysenter),
3986 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3987 N, N,
73fba5f4
AK		 3988 N, N, N, N, N, N, N, N,
3989 /* 0x40 - 0x4F */
3990 X16(D(DstReg | SrcMem | ModRM | Mov)),
3991 /* 0x50 - 0x5F */
3992 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3993 /* 0x60 - 0x6F */
aa97bb48
AK		 3994 N, N, N, N,
3995 N, N, N, N,
3996 N, N, N, N,
3997 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3998 /* 0x70 - 0x7F */
aa97bb48
AK		 3999 N, N, N, N,
4000 N, N, N, N,
4001 N, N, N, N,
4002 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4003 /* 0x80 - 0x8F */
4004 X16(D(SrcImm)),
4005 /* 0x90 - 0x9F */
ee45b58e 4006 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4007 /* 0xA0 - 0xA7 */
1cd196ea 4008 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 4009 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 4010 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4011 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
4012 /* 0xA8 - 0xAF */
1cd196ea 4013 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4014 DI(ImplicitOps, rsm),
ce7faab2 4015 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 4016 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4017 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 4018 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4019 /* 0xB0 - 0xB7 */
e940b5c2 4020 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4021 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 4022 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4023 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4024 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4025 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4026 /* 0xB8 - 0xBF */
4027 N, N,
ce7faab2
TY		 4028 G(BitOp, group8),
4029 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 4030 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4031 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4032 /* 0xC0 - 0xC7 */
739ae406 4033 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4034 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4035 N, N, N, GD(0, &group9),
9299836e
AK		 4036 /* 0xC8 - 0xCF */
4037 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4038 /* 0xD0 - 0xDF */
4039 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4040 /* 0xE0 - 0xEF */
4041 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4042 /* 0xF0 - 0xFF */
4043 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4044};
4045
4046#undef D
4047#undef N
4048#undef G
4049#undef GD
4050#undef I
aa97bb48 4051#undef GP
01de8b09 4052#undef EXT
73fba5f4 4053
8d8f4e9f 4054#undef D2bv
f6511935 4055#undef D2bvIP
8d8f4e9f 4056#undef I2bv
d7841a4b 4057#undef I2bvIP
d67fc27a 4058#undef I6ALU
8d8f4e9f 4059
9dac77fa 4060static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4061{
4062 unsigned size;
4063
9dac77fa 4064 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4065 if (size == 8)
4066 size = 4;
4067 return size;
4068}
4069
4070static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4071 unsigned size, bool sign_extension)
4072{
39f21ee5
AK		 4073 int rc = X86EMUL_CONTINUE;
4074
4075 op->type = OP_IMM;
4076 op->bytes = size;
9dac77fa 4077 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4078 /* NB. Immediates are sign-extended as necessary. */
4079 switch (op->bytes) {
4080 case 1:
e85a1085 4081 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4082 break;
4083 case 2:
e85a1085 4084 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4085 break;
4086 case 4:
e85a1085 4087 op->val = insn_fetch(s32, ctxt);
39f21ee5 4088 break;
5e2c6883
NA		 4089 case 8:
4090 op->val = insn_fetch(s64, ctxt);
4091 break;
39f21ee5
AK		 4092 }
4093 if (!sign_extension) {
4094 switch (op->bytes) {
4095 case 1:
4096 op->val &= 0xff;
4097 break;
4098 case 2:
4099 op->val &= 0xffff;
4100 break;
4101 case 4:
4102 op->val &= 0xffffffff;
4103 break;
4104 }
4105 }
4106done:
4107 return rc;
4108}
4109
a9945549
AK		 4110static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4111 unsigned d)
4112{
4113 int rc = X86EMUL_CONTINUE;
4114
4115 switch (d) {
4116 case OpReg:
2adb5ad9 4117 decode_register_operand(ctxt, op);
a9945549
AK		 4118 break;
4119 case OpImmUByte:
608aabe3 4120 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4121 break;
4122 case OpMem:
41ddf978 4123 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4124 mem_common:
4125 *op = ctxt->memop;
4126 ctxt->memopp = op;
4127 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4128 fetch_bit_operand(ctxt);
4129 op->orig_val = op->val;
4130 break;
41ddf978
AK		 4131 case OpMem64:
4132 ctxt->memop.bytes = 8;
4133 goto mem_common;
a9945549
AK		 4134 case OpAcc:
4135 op->type = OP_REG;
4136 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4137 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4138 fetch_register_operand(op);
4139 op->orig_val = op->val;
4140 break;
4141 case OpDI:
4142 op->type = OP_MEM;
4143 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4144 op->addr.mem.ea =
dd856efa 4145 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4146 op->addr.mem.seg = VCPU_SREG_ES;
4147 op->val = 0;
b3356bf0 4148 op->count = 1;
a9945549
AK		 4149 break;
4150 case OpDX:
4151 op->type = OP_REG;
4152 op->bytes = 2;
dd856efa 4153 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4154 fetch_register_operand(op);
4155 break;
4dd6a57d
AK		 4156 case OpCL:
4157 op->bytes = 1;
dd856efa 4158 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4159 break;
4160 case OpImmByte:
4161 rc = decode_imm(ctxt, op, 1, true);
4162 break;
4163 case OpOne:
4164 op->bytes = 1;
4165 op->val = 1;
4166 break;
4167 case OpImm:
4168 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4169 break;
5e2c6883
NA		 4170 case OpImm64:
4171 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4172 break;
28867cee
AK		 4173 case OpMem8:
4174 ctxt->memop.bytes = 1;
4175 goto mem_common;
0fe59128
AK		 4176 case OpMem16:
4177 ctxt->memop.bytes = 2;
4178 goto mem_common;
4179 case OpMem32:
4180 ctxt->memop.bytes = 4;
4181 goto mem_common;
4182 case OpImmU16:
4183 rc = decode_imm(ctxt, op, 2, false);
4184 break;
4185 case OpImmU:
4186 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4187 break;
4188 case OpSI:
4189 op->type = OP_MEM;
4190 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4191 op->addr.mem.ea =
dd856efa 4192 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4193 op->addr.mem.seg = seg_override(ctxt);
4194 op->val = 0;
b3356bf0 4195 op->count = 1;
0fe59128
AK		 4196 break;
4197 case OpImmFAddr:
4198 op->type = OP_IMM;
4199 op->addr.mem.ea = ctxt->_eip;
4200 op->bytes = ctxt->op_bytes + 2;
4201 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4202 break;
4203 case OpMemFAddr:
4204 ctxt->memop.bytes = ctxt->op_bytes + 2;
4205 goto mem_common;
c191a7a0
AK		 4206 case OpES:
4207 op->val = VCPU_SREG_ES;
4208 break;
4209 case OpCS:
4210 op->val = VCPU_SREG_CS;
4211 break;
4212 case OpSS:
4213 op->val = VCPU_SREG_SS;
4214 break;
4215 case OpDS:
4216 op->val = VCPU_SREG_DS;
4217 break;
4218 case OpFS:
4219 op->val = VCPU_SREG_FS;
4220 break;
4221 case OpGS:
4222 op->val = VCPU_SREG_GS;
4223 break;
a9945549
AK		 4224 case OpImplicit:
4225 /* Special instructions do their own operand decoding. */
4226 default:
4227 op->type = OP_NONE; /* Disable writeback. */
4228 break;
4229 }
4230
4231done:
4232 return rc;
4233}
4234
ef5d75cc 4235int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4236{
dde7e6d1
AK		 4237 int rc = X86EMUL_CONTINUE;
4238 int mode = ctxt->mode;
46561646 4239 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4240 bool op_prefix = false;
46561646 4241 struct opcode opcode;
dde7e6d1 4242
f09ed83e
AK		 4243 ctxt->memop.type = OP_NONE;
4244 ctxt->memopp = NULL;
9dac77fa
AK		 4245 ctxt->_eip = ctxt->eip;
4246 ctxt->fetch.start = ctxt->_eip;
4247 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4248 if (insn_len > 0)
9dac77fa 4249 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4250
4251 switch (mode) {
4252 case X86EMUL_MODE_REAL:
4253 case X86EMUL_MODE_VM86:
4254 case X86EMUL_MODE_PROT16:
4255 def_op_bytes = def_ad_bytes = 2;
4256 break;
4257 case X86EMUL_MODE_PROT32:
4258 def_op_bytes = def_ad_bytes = 4;
4259 break;
4260#ifdef CONFIG_X86_64
4261 case X86EMUL_MODE_PROT64:
4262 def_op_bytes = 4;
4263 def_ad_bytes = 8;
4264 break;
4265#endif
4266 default:
1d2887e2 4267 return EMULATION_FAILED;
dde7e6d1
AK		 4268 }
4269
9dac77fa
AK		 4270 ctxt->op_bytes = def_op_bytes;
4271 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4272
4273 /* Legacy prefixes. */
4274 for (;;) {
e85a1085 4275 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4276 case 0x66: /* operand-size override */
0d7cdee8 4277 op_prefix = true;
dde7e6d1 4278 /* switch between 2/4 bytes */
9dac77fa 4279 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4280 break;
4281 case 0x67: /* address-size override */
4282 if (mode == X86EMUL_MODE_PROT64)
4283 /* switch between 4/8 bytes */
9dac77fa 4284 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4285 else
4286 /* switch between 2/4 bytes */
9dac77fa 4287 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4288 break;
4289 case 0x26: /* ES override */
4290 case 0x2e: /* CS override */
4291 case 0x36: /* SS override */
4292 case 0x3e: /* DS override */
9dac77fa 4293 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4294 break;
4295 case 0x64: /* FS override */
4296 case 0x65: /* GS override */
9dac77fa 4297 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4298 break;
4299 case 0x40 ... 0x4f: /* REX */
4300 if (mode != X86EMUL_MODE_PROT64)
4301 goto done_prefixes;
9dac77fa 4302 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4303 continue;
4304 case 0xf0: /* LOCK */
9dac77fa 4305 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4306 break;
4307 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4308 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4309 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4310 break;
4311 default:
4312 goto done_prefixes;
4313 }
4314
4315 /* Any legacy prefix after a REX prefix nullifies its effect. */
4316
9dac77fa 4317 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4318 }
4319
4320done_prefixes:
4321
4322 /* REX prefix. */
9dac77fa
AK		 4323 if (ctxt->rex_prefix & 8)
4324 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4325
4326 /* Opcode byte(s). */
9dac77fa 4327 opcode = opcode_table[ctxt->b];
d3ad6243 4328 /* Two-byte opcode? */
9dac77fa
AK		 4329 if (ctxt->b == 0x0f) {
4330 ctxt->twobyte = 1;
e85a1085 4331 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4332 opcode = twobyte_table[ctxt->b];
dde7e6d1 4333 }
9dac77fa 4334 ctxt->d = opcode.flags;
dde7e6d1 4335
9f4260e7
TY		 4336 if (ctxt->d & ModRM)
4337 ctxt->modrm = insn_fetch(u8, ctxt);
4338
9dac77fa
AK		 4339 while (ctxt->d & GroupMask) {
4340 switch (ctxt->d & GroupMask) {
46561646 4341 case Group:
9dac77fa 4342 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4343 opcode = opcode.u.group[goffset];
4344 break;
4345 case GroupDual:
9dac77fa
AK		 4346 goffset = (ctxt->modrm >> 3) & 7;
4347 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4348 opcode = opcode.u.gdual->mod3[goffset];
4349 else
4350 opcode = opcode.u.gdual->mod012[goffset];
4351 break;
4352 case RMExt:
9dac77fa 4353 goffset = ctxt->modrm & 7;
01de8b09 4354 opcode = opcode.u.group[goffset];
46561646
AK		 4355 break;
4356 case Prefix:
9dac77fa 4357 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4358 return EMULATION_FAILED;
9dac77fa 4359 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4360 switch (simd_prefix) {
4361 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4362 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4363 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4364 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4365 }
4366 break;
045a282c
GN		 4367 case Escape:
4368 if (ctxt->modrm > 0xbf)
4369 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4370 else
4371 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4372 break;
46561646 4373 default:
1d2887e2 4374 return EMULATION_FAILED;
0d7cdee8 4375 }
46561646 4376
b1ea50b2 4377 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4378 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4379 }
4380
9dac77fa
AK		 4381 ctxt->execute = opcode.u.execute;
4382 ctxt->check_perm = opcode.check_perm;
4383 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4384
4385 /* Unrecognised? */
9dac77fa 4386 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4387 return EMULATION_FAILED;
dde7e6d1 4388
9dac77fa 4389 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4390 return EMULATION_FAILED;
d867162c 4391
9dac77fa
AK		 4392 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4393 ctxt->op_bytes = 8;
dde7e6d1 4394
9dac77fa 4395 if (ctxt->d & Op3264) {
7f9b4b75 4396 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4397 ctxt->op_bytes = 8;
7f9b4b75 4398 else
9dac77fa 4399 ctxt->op_bytes = 4;
7f9b4b75
AK		 4400 }
4401
9dac77fa
AK		 4402 if (ctxt->d & Sse)
4403 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4404 else if (ctxt->d & Mmx)
4405 ctxt->op_bytes = 8;
1253791d 4406
dde7e6d1 4407 /* ModRM and SIB bytes. */
9dac77fa 4408 if (ctxt->d & ModRM) {
f09ed83e 4409 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4410 if (!ctxt->has_seg_override)
4411 set_seg_override(ctxt, ctxt->modrm_seg);
4412 } else if (ctxt->d & MemAbs)
f09ed83e 4413 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4414 if (rc != X86EMUL_CONTINUE)
4415 goto done;
4416
9dac77fa
AK		 4417 if (!ctxt->has_seg_override)
4418 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4419
f09ed83e 4420 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4421
f09ed83e
AK		 4422 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4423 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4424
dde7e6d1
AK		 4425 /*
4426 * Decode and fetch the source operand: register, memory
4427 * or immediate.
4428 */
0fe59128 4429 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4430 if (rc != X86EMUL_CONTINUE)
4431 goto done;
4432
dde7e6d1
AK		 4433 /*
4434 * Decode and fetch the second source operand: register, memory
4435 * or immediate.
4436 */
4dd6a57d 4437 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4438 if (rc != X86EMUL_CONTINUE)
4439 goto done;
4440
dde7e6d1 4441 /* Decode and fetch the destination operand: register or memory. */
a9945549 4442 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4443
4444done:
f09ed83e
AK		 4445 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4446 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4447
1d2887e2 4448 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4449}
4450
1cb3f3ae
XG		 4451bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4452{
4453 return ctxt->d & PageTable;
4454}
4455
3e2f65d5
GN		 4456static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4457{
3e2f65d5
GN		 4458 /* The second termination condition only applies for REPE
4459 * and REPNE. Test if the repeat string operation prefix is
4460 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4461 * corresponding termination condition according to:
4462 * - if REPE/REPZ and ZF = 0 then done
4463 * - if REPNE/REPNZ and ZF = 1 then done
4464 */
9dac77fa
AK		 4465 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4466 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4467 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4468 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4469 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4470 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4471 return true;
4472
4473 return false;
4474}
4475
cbe2c9d3
AK		 4476static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4477{
4478 bool fault = false;
4479
4480 ctxt->ops->get_fpu(ctxt);
4481 asm volatile("1: fwait \n\t"
4482 "2: \n\t"
4483 ".pushsection .fixup,\"ax\" \n\t"
4484 "3: \n\t"
4485 "movb $1, %[fault] \n\t"
4486 "jmp 2b \n\t"
4487 ".popsection \n\t"
4488 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4489 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4490 ctxt->ops->put_fpu(ctxt);
4491
4492 if (unlikely(fault))
4493 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4494
4495 return X86EMUL_CONTINUE;
4496}
4497
4498static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4499 struct operand *op)
4500{
4501 if (op->type == OP_MM)
4502 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4503}
4504
dd856efa 4505
7b105ca2 4506int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4507{
0225fb50 4508 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4509 int rc = X86EMUL_CONTINUE;
9dac77fa 4510 int saved_dst_type = ctxt->dst.type;
8b4caf66 4511
9dac77fa 4512 ctxt->mem_read.pos = 0;
310b5d30 4513
9dac77fa 4514 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4515 rc = emulate_ud(ctxt);
1161624f
GN		 4516 goto done;
4517 }
4518
d380a5e4 4519 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4520 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4521 rc = emulate_ud(ctxt);
d380a5e4
GN		 4522 goto done;
4523 }
4524
9dac77fa 4525 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4526 rc = emulate_ud(ctxt);
081bca0e
AK		 4527 goto done;
4528 }
4529
cbe2c9d3
AK		 4530 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4531 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4532 rc = emulate_ud(ctxt);
4533 goto done;
4534 }
4535
cbe2c9d3 4536 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4537 rc = emulate_nm(ctxt);
4538 goto done;
4539 }
4540
cbe2c9d3
AK		 4541 if (ctxt->d & Mmx) {
4542 rc = flush_pending_x87_faults(ctxt);
4543 if (rc != X86EMUL_CONTINUE)
4544 goto done;
4545 /*
4546 * Now that we know the fpu is exception safe, we can fetch
4547 * operands from it.
4548 */
4549 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4550 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4551 if (!(ctxt->d & Mov))
4552 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4553 }
4554
9dac77fa
AK		 4555 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4556 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4557 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4558 if (rc != X86EMUL_CONTINUE)
4559 goto done;
4560 }
4561
e92805ac 4562 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4563 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4564 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4565 goto done;
4566 }
4567
8ea7d6ae 4568 /* Instruction can only be executed in protected mode */
9d1b39a9 4569 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4570 rc = emulate_ud(ctxt);
4571 goto done;
4572 }
4573
d09beabd 4574 /* Do instruction specific permission checks */
9dac77fa
AK		 4575 if (ctxt->check_perm) {
4576 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4577 if (rc != X86EMUL_CONTINUE)
4578 goto done;
4579 }
4580
9dac77fa
AK		 4581 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4582 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4583 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4584 if (rc != X86EMUL_CONTINUE)
4585 goto done;
4586 }
4587
9dac77fa 4588 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4589 /* All REP prefixes have the same first termination condition */
dd856efa 4590 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4591 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4592 goto done;
4593 }
b9fa9d6b
AK		 4594 }
4595
9dac77fa
AK		 4596 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4597 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4598 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4599 if (rc != X86EMUL_CONTINUE)
8b4caf66 4600 goto done;
9dac77fa 4601 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4602 }
4603
9dac77fa
AK		 4604 if (ctxt->src2.type == OP_MEM) {
4605 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4606 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4607 if (rc != X86EMUL_CONTINUE)
4608 goto done;
4609 }
4610
9dac77fa 4611 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4612 goto special_insn;
4613
4614
9dac77fa 4615 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4616 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4617 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4618 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
038e51de 4621 }
9dac77fa 4622 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4623
018a98db
AK		 4624special_insn:
4625
9dac77fa
AK		 4626 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4627 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4628 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4629 if (rc != X86EMUL_CONTINUE)
4630 goto done;
4631 }
4632
9dac77fa
AK		 4633 if (ctxt->execute) {
4634 rc = ctxt->execute(ctxt);
ef65c889
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637 goto writeback;
4638 }
4639
9dac77fa 4640 if (ctxt->twobyte)
6aa8b732
AK		 4641 goto twobyte_insn;
4642
9dac77fa 4643 switch (ctxt->b) {
33615aa9 4644 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4645 emulate_1op(ctxt, "inc");
33615aa9
AK		 4646 break;
4647 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4648 emulate_1op(ctxt, "dec");
33615aa9 4649 break;
6aa8b732 4650 case 0x63: /* movsxd */
8b4caf66 4651 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4652 goto cannot_emulate;
9dac77fa 4653 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4654 break;
b2833e3c 4655 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4656 if (test_cc(ctxt->b, ctxt->eflags))
4657 jmp_rel(ctxt, ctxt->src.val);
018a98db 4658 break;
7e0b54b1 4659 case 0x8d: /* lea r16/r32, m */
9dac77fa 4660 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4661 break;
3d9e77df 4662 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4663 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4664 break;
e4f973ae
TY		 4665 rc = em_xchg(ctxt);
4666 break;
e8b6fa70 4667 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4668 switch (ctxt->op_bytes) {
4669 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4670 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4671 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4672 }
4673 break;
018a98db 4674 case 0xc0 ... 0xc1:
51187683 4675 rc = em_grp2(ctxt);
018a98db 4676 break;
6e154e56 4677 case 0xcc: /* int3 */
5c5df76b
TY		 4678 rc = emulate_int(ctxt, 3);
4679 break;
6e154e56 4680 case 0xcd: /* int n */
9dac77fa 4681 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4682 break;
4683 case 0xce: /* into */
5c5df76b
TY		 4684 if (ctxt->eflags & EFLG_OF)
4685 rc = emulate_int(ctxt, 4);
6e154e56 4686 break;
018a98db 4687 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4688 rc = em_grp2(ctxt);
018a98db
AK		 4689 break;
4690 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4691 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4692 rc = em_grp2(ctxt);
018a98db 4693 break;
1a52e051 4694 case 0xe9: /* jmp rel */
db5b0762 4695 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4696 jmp_rel(ctxt, ctxt->src.val);
4697 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4698 break;
111de5d6 4699 case 0xf4: /* hlt */
6c3287f7 4700 ctxt->ops->halt(ctxt);
19fdfa0d 4701 break;
111de5d6
AK		 4702 case 0xf5: /* cmc */
4703 /* complement carry flag from eflags reg */
4704 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4705 break;
4706 case 0xf8: /* clc */
4707 ctxt->eflags &= ~EFLG_CF;
111de5d6 4708 break;
8744aa9a
MG		 4709 case 0xf9: /* stc */
4710 ctxt->eflags |= EFLG_CF;
4711 break;
fb4616f4
MG		 4712 case 0xfc: /* cld */
4713 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4714 break;
4715 case 0xfd: /* std */
4716 ctxt->eflags |= EFLG_DF;
fb4616f4 4717 break;
91269b8f
AK		 4718 default:
4719 goto cannot_emulate;
6aa8b732 4720 }
018a98db 4721
7d9ddaed
AK		 4722 if (rc != X86EMUL_CONTINUE)
4723 goto done;
4724
018a98db 4725writeback:
adddcecf 4726 rc = writeback(ctxt);
1b30eaa8 4727 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4728 goto done;
4729
5cd21917
GN		 4730 /*
4731 * restore dst type in case the decoding will be reused
4732 * (happens for string instruction )
4733 */
9dac77fa 4734 ctxt->dst.type = saved_dst_type;
5cd21917 4735
9dac77fa 4736 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4737 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4738
9dac77fa 4739 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4740 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4741
9dac77fa 4742 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4743 unsigned int count;
9dac77fa 4744 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4745 if ((ctxt->d & SrcMask) == SrcSI)
4746 count = ctxt->src.count;
4747 else
4748 count = ctxt->dst.count;
4749 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4750 -count);
3e2f65d5 4751
d2ddd1c4
GN		 4752 if (!string_insn_completed(ctxt)) {
4753 /*
4754 * Re-enter guest when pio read ahead buffer is empty
4755 * or, if it is not used, after each 1024 iteration.
4756 */
dd856efa 4757 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4758 (r->end == 0 || r->end != r->pos)) {
4759 /*
4760 * Reset read cache. Usually happens before
4761 * decode, but since instruction is restarted
4762 * we have to do it here.
4763 */
9dac77fa 4764 ctxt->mem_read.end = 0;
dd856efa 4765 writeback_registers(ctxt);
d2ddd1c4
GN		 4766 return EMULATION_RESTART;
4767 }
4768 goto done; /* skip rip writeback */
0fa6ccbd 4769 }
5cd21917 4770 }
d2ddd1c4 4771
9dac77fa 4772 ctxt->eip = ctxt->_eip;
018a98db
AK		 4773
4774done:
da9cb575
AK		 4775 if (rc == X86EMUL_PROPAGATE_FAULT)
4776 ctxt->have_exception = true;
775fde86
JR		 4777 if (rc == X86EMUL_INTERCEPTED)
4778 return EMULATION_INTERCEPTED;
4779
dd856efa
AK		 4780 if (rc == X86EMUL_CONTINUE)
4781 writeback_registers(ctxt);
4782
d2ddd1c4 4783 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4784
4785twobyte_insn:
9dac77fa 4786 switch (ctxt->b) {
018a98db 4787 case 0x09: /* wbinvd */
cfb22375 4788 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4789 break;
4790 case 0x08: /* invd */
018a98db
AK		 4791 case 0x0d: /* GrpP (prefetch) */
4792 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4793 break;
4794 case 0x20: /* mov cr, reg */
9dac77fa 4795 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4796 break;
6aa8b732 4797 case 0x21: /* mov from dr to reg */
9dac77fa 4798 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4799 break;
6aa8b732 4800 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4801 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4802 if (!test_cc(ctxt->b, ctxt->eflags))
4803 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4804 break;
b2833e3c 4805 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4806 if (test_cc(ctxt->b, ctxt->eflags))
4807 jmp_rel(ctxt, ctxt->src.val);
018a98db 4808 break;
ee45b58e 4809 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4810 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4811 break;
9bf8ea42
GT		 4812 case 0xa4: /* shld imm8, r, r/m */
4813 case 0xa5: /* shld cl, r, r/m */
761441b9 4814 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4815 break;
9bf8ea42
GT		 4816 case 0xac: /* shrd imm8, r, r/m */
4817 case 0xad: /* shrd cl, r, r/m */
761441b9 4818 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4819 break;
2a7c5b8b
GC		 4820 case 0xae: /* clflush */
4821 break;
6aa8b732 4822 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4823 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4824 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4825 : (u16) ctxt->src.val;
6aa8b732 4826 break;
6aa8b732 4827 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4828 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4829 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4830 (s16) ctxt->src.val;
6aa8b732 4831 break;
92f738a5 4832 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4833 emulate_2op_SrcV(ctxt, "add");
92f738a5 4834 /* Write back the register source. */
9dac77fa
AK		 4835 ctxt->src.val = ctxt->dst.orig_val;
4836 write_register_operand(&ctxt->src);
92f738a5 4837 break;
a012e65a 4838 case 0xc3: /* movnti */
9dac77fa
AK		 4839 ctxt->dst.bytes = ctxt->op_bytes;
4840 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4841 (u64) ctxt->src.val;
a012e65a 4842 break;
91269b8f
AK		 4843 default:
4844 goto cannot_emulate;
6aa8b732 4845 }
7d9ddaed
AK		 4846
4847 if (rc != X86EMUL_CONTINUE)
4848 goto done;
4849
6aa8b732
AK		 4850 goto writeback;
4851
4852cannot_emulate:
a0c0ab2f 4853 return EMULATION_FAILED;
6aa8b732 4854}
dd856efa
AK		 4855
4856void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4857{
4858 invalidate_registers(ctxt);
4859}
4860
4861void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4862{
4863 writeback_registers(ctxt);
4864}
Linux kernel - Deliverables
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