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KVM: x86 emulator: use struct operand for mov reg,dr and mov dr,reg for reg op
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
57#define DstMask (7<<1)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 85/* Misc flags */
7f9b4b75 86#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
d0e53325
AK		 98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
83babbca 106
d65b1dee
AK		 107struct opcode {
108 u32 flags;
120df890 109 union {
ef65c889 110 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 111 struct opcode *group;
112 struct group_dual *gdual;
113 } u;
114};
115
116struct group_dual {
117 struct opcode mod012[8];
118 struct opcode mod3[8];
d65b1dee
AK		 119};
120
6aa8b732 121/* EFLAGS bit definitions. */
d4c6a154
GN		 122#define EFLG_ID (1<<21)
123#define EFLG_VIP (1<<20)
124#define EFLG_VIF (1<<19)
125#define EFLG_AC (1<<18)
b1d86143
AP		 126#define EFLG_VM (1<<17)
127#define EFLG_RF (1<<16)
d4c6a154
GN		 128#define EFLG_IOPL (3<<12)
129#define EFLG_NT (1<<14)
6aa8b732
AK		 130#define EFLG_OF (1<<11)
131#define EFLG_DF (1<<10)
b1d86143 132#define EFLG_IF (1<<9)
d4c6a154 133#define EFLG_TF (1<<8)
6aa8b732
AK		 134#define EFLG_SF (1<<7)
135#define EFLG_ZF (1<<6)
136#define EFLG_AF (1<<4)
137#define EFLG_PF (1<<2)
138#define EFLG_CF (1<<0)
139
62bd430e
MG		 140#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
141#define EFLG_RESERVED_ONE_MASK 2
142
6aa8b732
AK		 143/*
144 * Instruction emulation:
145 * Most instructions are emulated directly via a fragment of inline assembly
146 * code. This allows us to save/restore EFLAGS and thus very easily pick up
147 * any modified flags.
148 */
149
05b3e0c2 150#if defined(CONFIG_X86_64)
6aa8b732
AK		 151#define _LO32 "k" /* force 32-bit operand */
152#define _STK "%%rsp" /* stack pointer */
153#elif defined(__i386__)
154#define _LO32 "" /* force 32-bit operand */
155#define _STK "%%esp" /* stack pointer */
156#endif
157
158/*
159 * These EFLAGS bits are restored from saved value during emulation, and
160 * any changes are written back to the saved value after emulation.
161 */
162#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
163
164/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 165#define _PRE_EFLAGS(_sav, _msk, _tmp) \
166 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
167 "movl %"_sav",%"_LO32 _tmp"; " \
168 "push %"_tmp"; " \
169 "push %"_tmp"; " \
170 "movl %"_msk",%"_LO32 _tmp"; " \
171 "andl %"_LO32 _tmp",("_STK"); " \
172 "pushf; " \
173 "notl %"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
175 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
176 "pop %"_tmp"; " \
177 "orl %"_LO32 _tmp",("_STK"); " \
178 "popf; " \
179 "pop %"_sav"; "
6aa8b732
AK		 180
181/* After executing instruction: write-back necessary bits in EFLAGS. */
182#define _POST_EFLAGS(_sav, _msk, _tmp) \
183 /* _sav |= EFLAGS & _msk; */ \
184 "pushf; " \
185 "pop %"_tmp"; " \
186 "andl %"_msk",%"_LO32 _tmp"; " \
187 "orl %"_LO32 _tmp",%"_sav"; "
188
dda96d8f
AK		 189#ifdef CONFIG_X86_64
190#define ON64(x) x
191#else
192#define ON64(x)
193#endif
194
6b7ad61f
AK		 195#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
196 do { \
197 __asm__ __volatile__ ( \
198 _PRE_EFLAGS("0", "4", "2") \
199 _op _suffix " %"_x"3,%1; " \
200 _POST_EFLAGS("0", "4", "2") \
201 : "=m" (_eflags), "=m" ((_dst).val), \
202 "=&r" (_tmp) \
203 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 204 } while (0)
6b7ad61f
AK		 205
206
6aa8b732
AK		 207/* Raw emulation: instruction has two explicit operands. */
208#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 209 do { \
210 unsigned long _tmp; \
211 \
212 switch ((_dst).bytes) { \
213 case 2: \
214 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
215 break; \
216 case 4: \
217 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
218 break; \
219 case 8: \
220 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
221 break; \
222 } \
6aa8b732
AK		 223 } while (0)
224
225#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
226 do { \
6b7ad61f 227 unsigned long _tmp; \
d77c26fc 228 switch ((_dst).bytes) { \
6aa8b732 229 case 1: \
6b7ad61f 230 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 231 break; \
232 default: \
233 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
234 _wx, _wy, _lx, _ly, _qx, _qy); \
235 break; \
236 } \
237 } while (0)
238
239/* Source operand is byte-sized and may be restricted to just %cl. */
240#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
241 __emulate_2op(_op, _src, _dst, _eflags, \
242 "b", "c", "b", "c", "b", "c", "b", "c")
243
244/* Source operand is byte, word, long or quad sized. */
245#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
246 __emulate_2op(_op, _src, _dst, _eflags, \
247 "b", "q", "w", "r", _LO32, "r", "", "r")
248
249/* Source operand is word, long or quad sized. */
250#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
251 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
252 "w", "r", _LO32, "r", "", "r")
253
d175226a
GT		 254/* Instruction has three operands and one operand is stored in ECX register */
255#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
256 do { \
257 unsigned long _tmp; \
258 _type _clv = (_cl).val; \
259 _type _srcv = (_src).val; \
260 _type _dstv = (_dst).val; \
261 \
262 __asm__ __volatile__ ( \
263 _PRE_EFLAGS("0", "5", "2") \
264 _op _suffix " %4,%1 \n" \
265 _POST_EFLAGS("0", "5", "2") \
266 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
267 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
268 ); \
269 \
270 (_cl).val = (unsigned long) _clv; \
271 (_src).val = (unsigned long) _srcv; \
272 (_dst).val = (unsigned long) _dstv; \
273 } while (0)
274
275#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
276 do { \
277 switch ((_dst).bytes) { \
278 case 2: \
279 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
280 "w", unsigned short); \
281 break; \
282 case 4: \
283 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
284 "l", unsigned int); \
285 break; \
286 case 8: \
287 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
288 "q", unsigned long)); \
289 break; \
290 } \
291 } while (0)
292
dda96d8f 293#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 294 do { \
295 unsigned long _tmp; \
296 \
dda96d8f
AK		 297 __asm__ __volatile__ ( \
298 _PRE_EFLAGS("0", "3", "2") \
299 _op _suffix " %1; " \
300 _POST_EFLAGS("0", "3", "2") \
301 : "=m" (_eflags), "+m" ((_dst).val), \
302 "=&r" (_tmp) \
303 : "i" (EFLAGS_MASK)); \
304 } while (0)
305
306/* Instruction has only one explicit operand (no source operand). */
307#define emulate_1op(_op, _dst, _eflags) \
308 do { \
d77c26fc 309 switch ((_dst).bytes) { \
dda96d8f
AK		 310 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
311 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
312 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
313 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 314 } \
315 } while (0)
316
6aa8b732
AK		 317/* Fetch next part of the instruction being emulated. */
318#define insn_fetch(_type, _size, _eip) \
319({ unsigned long _x; \
62266869 320 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 321 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 322 goto done; \
323 (_eip) += (_size); \
324 (_type)_x; \
325})
326
414e6277
GN		 327#define insn_fetch_arr(_arr, _size, _eip) \
328({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
329 if (rc != X86EMUL_CONTINUE) \
330 goto done; \
331 (_eip) += (_size); \
332})
333
ddcb2885
HH		 334static inline unsigned long ad_mask(struct decode_cache *c)
335{
336 return (1UL << (c->ad_bytes << 3)) - 1;
337}
338
6aa8b732 339/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 340static inline unsigned long
341address_mask(struct decode_cache *c, unsigned long reg)
342{
343 if (c->ad_bytes == sizeof(unsigned long))
344 return reg;
345 else
346 return reg & ad_mask(c);
347}
348
349static inline unsigned long
350register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
351{
352 return base + address_mask(c, reg);
353}
354
7a957275
HH		 355static inline void
356register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
357{
358 if (c->ad_bytes == sizeof(unsigned long))
359 *reg += inc;
360 else
361 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
362}
6aa8b732 363
7a957275
HH		 364static inline void jmp_rel(struct decode_cache *c, int rel)
365{
366 register_address_increment(c, &c->eip, rel);
367}
098c937b 368
7a5b56df
AK		 369static void set_seg_override(struct decode_cache *c, int seg)
370{
371 c->has_seg_override = true;
372 c->seg_override = seg;
373}
374
79168fd1
GN		 375static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
376 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 377{
378 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
379 return 0;
380
79168fd1 381 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 382}
383
384static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 385 struct x86_emulate_ops *ops,
7a5b56df
AK		 386 struct decode_cache *c)
387{
388 if (!c->has_seg_override)
389 return 0;
390
79168fd1 391 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 392}
393
79168fd1
GN		 394static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
395 struct x86_emulate_ops *ops)
7a5b56df 396{
79168fd1 397 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 398}
399
79168fd1
GN		 400static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
401 struct x86_emulate_ops *ops)
7a5b56df 402{
79168fd1 403 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 404}
405
54b8486f
GN		 406static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
407 u32 error, bool valid)
408{
409 ctxt->exception = vec;
410 ctxt->error_code = error;
411 ctxt->error_code_valid = valid;
412 ctxt->restart = false;
413}
414
415static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
416{
417 emulate_exception(ctxt, GP_VECTOR, err, true);
418}
419
420static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
421 int err)
422{
423 ctxt->cr2 = addr;
424 emulate_exception(ctxt, PF_VECTOR, err, true);
425}
426
427static void emulate_ud(struct x86_emulate_ctxt *ctxt)
428{
429 emulate_exception(ctxt, UD_VECTOR, 0, false);
430}
431
432static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
433{
434 emulate_exception(ctxt, TS_VECTOR, err, true);
435}
436
62266869
AK		 437static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
438 struct x86_emulate_ops *ops,
2fb53ad8 439 unsigned long eip, u8 *dest)
62266869
AK		 440{
441 struct fetch_cache *fc = &ctxt->decode.fetch;
442 int rc;
2fb53ad8 443 int size, cur_size;
62266869 444
2fb53ad8
AK		 445 if (eip == fc->end) {
446 cur_size = fc->end - fc->start;
447 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
448 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
449 size, ctxt->vcpu, NULL);
3e2815e9 450 if (rc != X86EMUL_CONTINUE)
62266869 451 return rc;
2fb53ad8 452 fc->end += size;
62266869 453 }
2fb53ad8 454 *dest = fc->data[eip - fc->start];
3e2815e9 455 return X86EMUL_CONTINUE;
62266869
AK		 456}
457
458static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
459 struct x86_emulate_ops *ops,
460 unsigned long eip, void *dest, unsigned size)
461{
3e2815e9 462 int rc;
62266869 463
eb3c79e6 464 /* x86 instructions are limited to 15 bytes. */
063db061 465 if (eip + size - ctxt->eip > 15)
eb3c79e6 466 return X86EMUL_UNHANDLEABLE;
62266869
AK		 467 while (size--) {
468 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 469 if (rc != X86EMUL_CONTINUE)
62266869
AK		 470 return rc;
471 }
3e2815e9 472 return X86EMUL_CONTINUE;
62266869
AK		 473}
474
1e3c5cb0
RR		 475/*
476 * Given the 'reg' portion of a ModRM byte, and a register block, return a
477 * pointer into the block that addresses the relevant register.
478 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
479 */
480static void *decode_register(u8 modrm_reg, unsigned long *regs,
481 int highbyte_regs)
6aa8b732
AK		 482{
483 void *p;
484
485 p = &regs[modrm_reg];
486 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
487 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
488 return p;
489}
490
491static int read_descriptor(struct x86_emulate_ctxt *ctxt,
492 struct x86_emulate_ops *ops,
1a6440ae 493 ulong addr,
6aa8b732
AK		 494 u16 *size, unsigned long *address, int op_bytes)
495{
496 int rc;
497
498 if (op_bytes == 2)
499 op_bytes = 3;
500 *address = 0;
1a6440ae 501 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 502 if (rc != X86EMUL_CONTINUE)
6aa8b732 503 return rc;
1a6440ae 504 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 505 return rc;
506}
507
bbe9abbd
NK		 508static int test_cc(unsigned int condition, unsigned int flags)
509{
510 int rc = 0;
511
512 switch ((condition & 15) >> 1) {
513 case 0: /* o */
514 rc |= (flags & EFLG_OF);
515 break;
516 case 1: /* b/c/nae */
517 rc |= (flags & EFLG_CF);
518 break;
519 case 2: /* z/e */
520 rc |= (flags & EFLG_ZF);
521 break;
522 case 3: /* be/na */
523 rc |= (flags & (EFLG_CF|EFLG_ZF));
524 break;
525 case 4: /* s */
526 rc |= (flags & EFLG_SF);
527 break;
528 case 5: /* p/pe */
529 rc |= (flags & EFLG_PF);
530 break;
531 case 7: /* le/ng */
532 rc |= (flags & EFLG_ZF);
533 /* fall through */
534 case 6: /* l/nge */
535 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
536 break;
537 }
538
539 /* Odd condition identifiers (lsb == 1) have inverted sense. */
540 return (!!rc ^ (condition & 1));
541}
542
91ff3cb4
AK		 543static void fetch_register_operand(struct operand *op)
544{
545 switch (op->bytes) {
546 case 1:
547 op->val = *(u8 *)op->addr.reg;
548 break;
549 case 2:
550 op->val = *(u16 *)op->addr.reg;
551 break;
552 case 4:
553 op->val = *(u32 *)op->addr.reg;
554 break;
555 case 8:
556 op->val = *(u64 *)op->addr.reg;
557 break;
558 }
559}
560
3c118e24
AK		 561static void decode_register_operand(struct operand *op,
562 struct decode_cache *c,
3c118e24
AK		 563 int inhibit_bytereg)
564{
33615aa9 565 unsigned reg = c->modrm_reg;
9f1ef3f8 566 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 567
568 if (!(c->d & ModRM))
569 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 570 op->type = OP_REG;
571 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 572 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 573 op->bytes = 1;
574 } else {
1a6440ae 575 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 576 op->bytes = c->op_bytes;
3c118e24 577 }
91ff3cb4 578 fetch_register_operand(op);
3c118e24
AK		 579 op->orig_val = op->val;
580}
581
1c73ef66
AK		 582static int decode_modrm(struct x86_emulate_ctxt *ctxt,
583 struct x86_emulate_ops *ops)
584{
585 struct decode_cache *c = &ctxt->decode;
586 u8 sib;
f5b4edcd 587 int index_reg = 0, base_reg = 0, scale;
3e2815e9 588 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 589
590 if (c->rex_prefix) {
591 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
592 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
593 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
594 }
595
596 c->modrm = insn_fetch(u8, 1, c->eip);
597 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
598 c->modrm_reg |= (c->modrm & 0x38) >> 3;
599 c->modrm_rm |= (c->modrm & 0x07);
600 c->modrm_ea = 0;
09ee57cd 601 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 602
603 if (c->modrm_mod == 3) {
107d6d2e
AK		 604 c->modrm_ptr = decode_register(c->modrm_rm,
605 c->regs, c->d & ByteOp);
606 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 607 return rc;
608 }
609
610 if (c->ad_bytes == 2) {
611 unsigned bx = c->regs[VCPU_REGS_RBX];
612 unsigned bp = c->regs[VCPU_REGS_RBP];
613 unsigned si = c->regs[VCPU_REGS_RSI];
614 unsigned di = c->regs[VCPU_REGS_RDI];
615
616 /* 16-bit ModR/M decode. */
617 switch (c->modrm_mod) {
618 case 0:
619 if (c->modrm_rm == 6)
620 c->modrm_ea += insn_fetch(u16, 2, c->eip);
621 break;
622 case 1:
623 c->modrm_ea += insn_fetch(s8, 1, c->eip);
624 break;
625 case 2:
626 c->modrm_ea += insn_fetch(u16, 2, c->eip);
627 break;
628 }
629 switch (c->modrm_rm) {
630 case 0:
631 c->modrm_ea += bx + si;
632 break;
633 case 1:
634 c->modrm_ea += bx + di;
635 break;
636 case 2:
637 c->modrm_ea += bp + si;
638 break;
639 case 3:
640 c->modrm_ea += bp + di;
641 break;
642 case 4:
643 c->modrm_ea += si;
644 break;
645 case 5:
646 c->modrm_ea += di;
647 break;
648 case 6:
649 if (c->modrm_mod != 0)
650 c->modrm_ea += bp;
651 break;
652 case 7:
653 c->modrm_ea += bx;
654 break;
655 }
656 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
657 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 658 c->modrm_seg = VCPU_SREG_SS;
1c73ef66
AK		 659 c->modrm_ea = (u16)c->modrm_ea;
660 } else {
661 /* 32/64-bit ModR/M decode. */
84411d85 662 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 663 sib = insn_fetch(u8, 1, c->eip);
664 index_reg |= (sib >> 3) & 7;
665 base_reg |= sib & 7;
666 scale = sib >> 6;
667
dc71d0f1
AK		 668 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
669 c->modrm_ea += insn_fetch(s32, 4, c->eip);
670 else
1c73ef66 671 c->modrm_ea += c->regs[base_reg];
dc71d0f1 672 if (index_reg != 4)
1c73ef66 673 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 674 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
675 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 676 c->rip_relative = 1;
84411d85 677 } else
1c73ef66 678 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 679 switch (c->modrm_mod) {
680 case 0:
681 if (c->modrm_rm == 5)
682 c->modrm_ea += insn_fetch(s32, 4, c->eip);
683 break;
684 case 1:
685 c->modrm_ea += insn_fetch(s8, 1, c->eip);
686 break;
687 case 2:
688 c->modrm_ea += insn_fetch(s32, 4, c->eip);
689 break;
690 }
691 }
1c73ef66
AK		 692done:
693 return rc;
694}
695
696static int decode_abs(struct x86_emulate_ctxt *ctxt,
697 struct x86_emulate_ops *ops)
698{
699 struct decode_cache *c = &ctxt->decode;
3e2815e9 700 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 701
702 switch (c->ad_bytes) {
703 case 2:
704 c->modrm_ea = insn_fetch(u16, 2, c->eip);
705 break;
706 case 4:
707 c->modrm_ea = insn_fetch(u32, 4, c->eip);
708 break;
709 case 8:
710 c->modrm_ea = insn_fetch(u64, 8, c->eip);
711 break;
712 }
713done:
714 return rc;
715}
716
dde7e6d1
AK		 717static int read_emulated(struct x86_emulate_ctxt *ctxt,
718 struct x86_emulate_ops *ops,
719 unsigned long addr, void *dest, unsigned size)
6aa8b732 720{
dde7e6d1
AK		 721 int rc;
722 struct read_cache *mc = &ctxt->decode.mem_read;
723 u32 err;
6aa8b732 724
dde7e6d1
AK		 725 while (size) {
726 int n = min(size, 8u);
727 size -= n;
728 if (mc->pos < mc->end)
729 goto read_cached;
5cd21917 730
dde7e6d1
AK		 731 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
732 ctxt->vcpu);
733 if (rc == X86EMUL_PROPAGATE_FAULT)
734 emulate_pf(ctxt, addr, err);
735 if (rc != X86EMUL_CONTINUE)
736 return rc;
737 mc->end += n;
6aa8b732 738
dde7e6d1
AK		 739 read_cached:
740 memcpy(dest, mc->data + mc->pos, n);
741 mc->pos += n;
742 dest += n;
743 addr += n;
6aa8b732 744 }
dde7e6d1
AK		 745 return X86EMUL_CONTINUE;
746}
6aa8b732 747
dde7e6d1
AK		 748static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
749 struct x86_emulate_ops *ops,
750 unsigned int size, unsigned short port,
751 void *dest)
752{
753 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 754
dde7e6d1
AK		 755 if (rc->pos == rc->end) { /* refill pio read ahead */
756 struct decode_cache *c = &ctxt->decode;
757 unsigned int in_page, n;
758 unsigned int count = c->rep_prefix ?
759 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
760 in_page = (ctxt->eflags & EFLG_DF) ?
761 offset_in_page(c->regs[VCPU_REGS_RDI]) :
762 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
763 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
764 count);
765 if (n == 0)
766 n = 1;
767 rc->pos = rc->end = 0;
768 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
769 return 0;
770 rc->end = n * size;
6aa8b732
AK		 771 }
772
dde7e6d1
AK		 773 memcpy(dest, rc->data + rc->pos, size);
774 rc->pos += size;
775 return 1;
776}
6aa8b732 777
dde7e6d1
AK		 778static u32 desc_limit_scaled(struct desc_struct *desc)
779{
780 u32 limit = get_desc_limit(desc);
6aa8b732 781
dde7e6d1
AK		 782 return desc->g ? (limit << 12) | 0xfff : limit;
783}
6aa8b732 784
dde7e6d1
AK		 785static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
786 struct x86_emulate_ops *ops,
787 u16 selector, struct desc_ptr *dt)
788{
789 if (selector & 1 << 2) {
790 struct desc_struct desc;
791 memset (dt, 0, sizeof *dt);
792 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
793 return;
e09d082c 794
dde7e6d1
AK		 795 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
796 dt->address = get_desc_base(&desc);
797 } else
798 ops->get_gdt(dt, ctxt->vcpu);
799}
120df890 800
dde7e6d1
AK		 801/* allowed just for 8 bytes segments */
802static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
803 struct x86_emulate_ops *ops,
804 u16 selector, struct desc_struct *desc)
805{
806 struct desc_ptr dt;
807 u16 index = selector >> 3;
808 int ret;
809 u32 err;
810 ulong addr;
120df890 811
dde7e6d1 812 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 813
dde7e6d1
AK		 814 if (dt.size < index * 8 + 7) {
815 emulate_gp(ctxt, selector & 0xfffc);
816 return X86EMUL_PROPAGATE_FAULT;
e09d082c 817 }
dde7e6d1
AK		 818 addr = dt.address + index * 8;
819 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
820 if (ret == X86EMUL_PROPAGATE_FAULT)
821 emulate_pf(ctxt, addr, err);
e09d082c 822
dde7e6d1
AK		 823 return ret;
824}
ef65c889 825
dde7e6d1
AK		 826/* allowed just for 8 bytes segments */
827static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
828 struct x86_emulate_ops *ops,
829 u16 selector, struct desc_struct *desc)
830{
831 struct desc_ptr dt;
832 u16 index = selector >> 3;
833 u32 err;
834 ulong addr;
835 int ret;
6aa8b732 836
dde7e6d1 837 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 838
dde7e6d1
AK		 839 if (dt.size < index * 8 + 7) {
840 emulate_gp(ctxt, selector & 0xfffc);
841 return X86EMUL_PROPAGATE_FAULT;
842 }
6aa8b732 843
dde7e6d1
AK		 844 addr = dt.address + index * 8;
845 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
846 if (ret == X86EMUL_PROPAGATE_FAULT)
847 emulate_pf(ctxt, addr, err);
c7e75a3d 848
dde7e6d1
AK		 849 return ret;
850}
c7e75a3d 851
dde7e6d1
AK		 852static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
853 struct x86_emulate_ops *ops,
854 u16 selector, int seg)
855{
856 struct desc_struct seg_desc;
857 u8 dpl, rpl, cpl;
858 unsigned err_vec = GP_VECTOR;
859 u32 err_code = 0;
860 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
861 int ret;
69f55cb1 862
dde7e6d1 863 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 864
dde7e6d1
AK		 865 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
866 || ctxt->mode == X86EMUL_MODE_REAL) {
867 /* set real mode segment descriptor */
868 set_desc_base(&seg_desc, selector << 4);
869 set_desc_limit(&seg_desc, 0xffff);
870 seg_desc.type = 3;
871 seg_desc.p = 1;
872 seg_desc.s = 1;
873 goto load;
874 }
875
876 /* NULL selector is not valid for TR, CS and SS */
877 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
878 && null_selector)
879 goto exception;
880
881 /* TR should be in GDT only */
882 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
883 goto exception;
884
885 if (null_selector) /* for NULL selector skip all following checks */
886 goto load;
887
888 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
889 if (ret != X86EMUL_CONTINUE)
890 return ret;
891
892 err_code = selector & 0xfffc;
893 err_vec = GP_VECTOR;
894
895 /* can't load system descriptor into segment selecor */
896 if (seg <= VCPU_SREG_GS && !seg_desc.s)
897 goto exception;
898
899 if (!seg_desc.p) {
900 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
901 goto exception;
902 }
903
904 rpl = selector & 3;
905 dpl = seg_desc.dpl;
906 cpl = ops->cpl(ctxt->vcpu);
907
908 switch (seg) {
909 case VCPU_SREG_SS:
910 /*
911 * segment is not a writable data segment or segment
912 * selector's RPL != CPL or segment selector's RPL != CPL
913 */
914 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
915 goto exception;
6aa8b732 916 break;
dde7e6d1
AK		 917 case VCPU_SREG_CS:
918 if (!(seg_desc.type & 8))
919 goto exception;
920
921 if (seg_desc.type & 4) {
922 /* conforming */
923 if (dpl > cpl)
924 goto exception;
925 } else {
926 /* nonconforming */
927 if (rpl > cpl || dpl != cpl)
928 goto exception;
929 }
930 /* CS(RPL) <- CPL */
931 selector = (selector & 0xfffc) | cpl;
6aa8b732 932 break;
dde7e6d1
AK		 933 case VCPU_SREG_TR:
934 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
935 goto exception;
936 break;
937 case VCPU_SREG_LDTR:
938 if (seg_desc.s || seg_desc.type != 2)
939 goto exception;
940 break;
941 default: /* DS, ES, FS, or GS */
4e62417b 942 /*
dde7e6d1
AK		 943 * segment is not a data or readable code segment or
944 * ((segment is a data or nonconforming code segment)
945 * and (both RPL and CPL > DPL))
4e62417b 946 */
dde7e6d1
AK		 947 if ((seg_desc.type & 0xa) == 0x8 ||
948 (((seg_desc.type & 0xc) != 0xc) &&
949 (rpl > dpl && cpl > dpl)))
950 goto exception;
6aa8b732 951 break;
dde7e6d1
AK		 952 }
953
954 if (seg_desc.s) {
955 /* mark segment as accessed */
956 seg_desc.type |= 1;
957 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
958 if (ret != X86EMUL_CONTINUE)
959 return ret;
960 }
961load:
962 ops->set_segment_selector(selector, seg, ctxt->vcpu);
963 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
964 return X86EMUL_CONTINUE;
965exception:
966 emulate_exception(ctxt, err_vec, err_code, true);
967 return X86EMUL_PROPAGATE_FAULT;
968}
969
970static inline int writeback(struct x86_emulate_ctxt *ctxt,
971 struct x86_emulate_ops *ops)
972{
973 int rc;
974 struct decode_cache *c = &ctxt->decode;
975 u32 err;
976
977 switch (c->dst.type) {
978 case OP_REG:
979 /* The 4-byte case *is* correct:
980 * in 64-bit mode we zero-extend.
981 */
982 switch (c->dst.bytes) {
6aa8b732 983 case 1:
1a6440ae 984 *(u8 *)c->dst.addr.reg = (u8)c->dst.val;
6aa8b732
AK		 985 break;
986 case 2:
1a6440ae 987 *(u16 *)c->dst.addr.reg = (u16)c->dst.val;
6aa8b732
AK		 988 break;
989 case 4:
1a6440ae 990 *c->dst.addr.reg = (u32)c->dst.val;
dde7e6d1
AK		 991 break; /* 64b: zero-ext */
992 case 8:
1a6440ae 993 *c->dst.addr.reg = c->dst.val;
6aa8b732
AK		 994 break;
995 }
996 break;
dde7e6d1
AK		 997 case OP_MEM:
998 if (c->lock_prefix)
999 rc = ops->cmpxchg_emulated(
1a6440ae 1000 c->dst.addr.mem,
dde7e6d1
AK		 1001 &c->dst.orig_val,
1002 &c->dst.val,
1003 c->dst.bytes,
1004 &err,
1005 ctxt->vcpu);
341de7e3 1006 else
dde7e6d1 1007 rc = ops->write_emulated(
1a6440ae 1008 c->dst.addr.mem,
dde7e6d1
AK		 1009 &c->dst.val,
1010 c->dst.bytes,
1011 &err,
1012 ctxt->vcpu);
1013 if (rc == X86EMUL_PROPAGATE_FAULT)
1a6440ae 1014 emulate_pf(ctxt, c->dst.addr.mem, err);
dde7e6d1
AK		 1015 if (rc != X86EMUL_CONTINUE)
1016 return rc;
a682e354 1017 break;
dde7e6d1
AK		 1018 case OP_NONE:
1019 /* no writeback */
414e6277 1020 break;
dde7e6d1 1021 default:
414e6277 1022 break;
6aa8b732 1023 }
dde7e6d1
AK		 1024 return X86EMUL_CONTINUE;
1025}
6aa8b732 1026
dde7e6d1
AK		 1027static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1028 struct x86_emulate_ops *ops)
1029{
1030 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1031
dde7e6d1
AK		 1032 c->dst.type = OP_MEM;
1033 c->dst.bytes = c->op_bytes;
1034 c->dst.val = c->src.val;
1035 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1036 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1037 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1038}
69f55cb1 1039
dde7e6d1
AK		 1040static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1041 struct x86_emulate_ops *ops,
1042 void *dest, int len)
1043{
1044 struct decode_cache *c = &ctxt->decode;
1045 int rc;
8b4caf66 1046
dde7e6d1
AK		 1047 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1048 c->regs[VCPU_REGS_RSP]),
1049 dest, len);
1050 if (rc != X86EMUL_CONTINUE)
1051 return rc;
1052
1053 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1054 return rc;
8b4caf66
LV		 1055}
1056
dde7e6d1
AK		 1057static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1058 struct x86_emulate_ops *ops,
1059 void *dest, int len)
9de41573
GN		 1060{
1061 int rc;
dde7e6d1
AK		 1062 unsigned long val, change_mask;
1063 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1064 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1065
dde7e6d1
AK		 1066 rc = emulate_pop(ctxt, ops, &val, len);
1067 if (rc != X86EMUL_CONTINUE)
1068 return rc;
9de41573 1069
dde7e6d1
AK		 1070 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1071 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1072
dde7e6d1
AK		 1073 switch(ctxt->mode) {
1074 case X86EMUL_MODE_PROT64:
1075 case X86EMUL_MODE_PROT32:
1076 case X86EMUL_MODE_PROT16:
1077 if (cpl == 0)
1078 change_mask |= EFLG_IOPL;
1079 if (cpl <= iopl)
1080 change_mask |= EFLG_IF;
1081 break;
1082 case X86EMUL_MODE_VM86:
1083 if (iopl < 3) {
1084 emulate_gp(ctxt, 0);
1085 return X86EMUL_PROPAGATE_FAULT;
1086 }
1087 change_mask |= EFLG_IF;
1088 break;
1089 default: /* real mode */
1090 change_mask |= (EFLG_IOPL | EFLG_IF);
1091 break;
9de41573 1092 }
dde7e6d1
AK		 1093
1094 *(unsigned long *)dest =
1095 (ctxt->eflags & ~change_mask) | (val & change_mask);
1096
1097 return rc;
9de41573
GN		 1098}
1099
dde7e6d1
AK		 1100static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1101 struct x86_emulate_ops *ops, int seg)
7b262e90 1102{
dde7e6d1 1103 struct decode_cache *c = &ctxt->decode;
7b262e90 1104
dde7e6d1 1105 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1106
dde7e6d1 1107 emulate_push(ctxt, ops);
7b262e90
GN		 1108}
1109
dde7e6d1
AK		 1110static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1111 struct x86_emulate_ops *ops, int seg)
38ba30ba 1112{
dde7e6d1
AK		 1113 struct decode_cache *c = &ctxt->decode;
1114 unsigned long selector;
1115 int rc;
38ba30ba 1116
dde7e6d1
AK		 1117 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1118 if (rc != X86EMUL_CONTINUE)
1119 return rc;
1120
1121 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1122 return rc;
38ba30ba
GN		 1123}
1124
dde7e6d1
AK		 1125static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1126 struct x86_emulate_ops *ops)
38ba30ba 1127{
dde7e6d1
AK		 1128 struct decode_cache *c = &ctxt->decode;
1129 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1130 int rc = X86EMUL_CONTINUE;
1131 int reg = VCPU_REGS_RAX;
38ba30ba 1132
dde7e6d1
AK		 1133 while (reg <= VCPU_REGS_RDI) {
1134 (reg == VCPU_REGS_RSP) ?
1135 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1136
dde7e6d1 1137 emulate_push(ctxt, ops);
38ba30ba 1138
dde7e6d1
AK		 1139 rc = writeback(ctxt, ops);
1140 if (rc != X86EMUL_CONTINUE)
1141 return rc;
38ba30ba 1142
dde7e6d1 1143 ++reg;
38ba30ba 1144 }
38ba30ba 1145
dde7e6d1
AK		 1146 /* Disable writeback. */
1147 c->dst.type = OP_NONE;
1148
1149 return rc;
38ba30ba
GN		 1150}
1151
dde7e6d1
AK		 1152static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1153 struct x86_emulate_ops *ops)
38ba30ba 1154{
dde7e6d1
AK		 1155 struct decode_cache *c = &ctxt->decode;
1156 int rc = X86EMUL_CONTINUE;
1157 int reg = VCPU_REGS_RDI;
38ba30ba 1158
dde7e6d1
AK		 1159 while (reg >= VCPU_REGS_RAX) {
1160 if (reg == VCPU_REGS_RSP) {
1161 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1162 c->op_bytes);
1163 --reg;
1164 }
38ba30ba 1165
dde7e6d1
AK		 1166 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1167 if (rc != X86EMUL_CONTINUE)
1168 break;
1169 --reg;
38ba30ba 1170 }
dde7e6d1 1171 return rc;
38ba30ba
GN		 1172}
1173
dde7e6d1
AK		 1174static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1175 struct x86_emulate_ops *ops)
38ba30ba 1176{
dde7e6d1
AK		 1177 struct decode_cache *c = &ctxt->decode;
1178 int rc = X86EMUL_CONTINUE;
1179 unsigned long temp_eip = 0;
1180 unsigned long temp_eflags = 0;
1181 unsigned long cs = 0;
1182 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1183 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1184 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1185 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1186
dde7e6d1 1187 /* TODO: Add stack limit check */
38ba30ba 1188
dde7e6d1 1189 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1190
dde7e6d1
AK		 1191 if (rc != X86EMUL_CONTINUE)
1192 return rc;
38ba30ba 1193
dde7e6d1
AK		 1194 if (temp_eip & ~0xffff) {
1195 emulate_gp(ctxt, 0);
1196 return X86EMUL_PROPAGATE_FAULT;
1197 }
38ba30ba 1198
dde7e6d1 1199 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1200
dde7e6d1
AK		 1201 if (rc != X86EMUL_CONTINUE)
1202 return rc;
38ba30ba 1203
dde7e6d1 1204 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1205
dde7e6d1
AK		 1206 if (rc != X86EMUL_CONTINUE)
1207 return rc;
38ba30ba 1208
dde7e6d1 1209 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1210
dde7e6d1
AK		 1211 if (rc != X86EMUL_CONTINUE)
1212 return rc;
38ba30ba 1213
dde7e6d1 1214 c->eip = temp_eip;
38ba30ba 1215
38ba30ba 1216
dde7e6d1
AK		 1217 if (c->op_bytes == 4)
1218 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1219 else if (c->op_bytes == 2) {
1220 ctxt->eflags &= ~0xffff;
1221 ctxt->eflags |= temp_eflags;
38ba30ba 1222 }
dde7e6d1
AK		 1223
1224 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1225 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1226
1227 return rc;
38ba30ba
GN		 1228}
1229
dde7e6d1
AK		 1230static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1231 struct x86_emulate_ops* ops)
c37eda13 1232{
dde7e6d1
AK		 1233 switch(ctxt->mode) {
1234 case X86EMUL_MODE_REAL:
1235 return emulate_iret_real(ctxt, ops);
1236 case X86EMUL_MODE_VM86:
1237 case X86EMUL_MODE_PROT16:
1238 case X86EMUL_MODE_PROT32:
1239 case X86EMUL_MODE_PROT64:
c37eda13 1240 default:
dde7e6d1
AK		 1241 /* iret from protected mode unimplemented yet */
1242 return X86EMUL_UNHANDLEABLE;
c37eda13 1243 }
c37eda13
WY		 1244}
1245
dde7e6d1 1246static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1247 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1248{
1249 struct decode_cache *c = &ctxt->decode;
1250
dde7e6d1 1251 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1252}
1253
dde7e6d1 1254static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1255{
05f086f8 1256 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1257 switch (c->modrm_reg) {
1258 case 0: /* rol */
05f086f8 1259 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1260 break;
1261 case 1: /* ror */
05f086f8 1262 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1263 break;
1264 case 2: /* rcl */
05f086f8 1265 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1266 break;
1267 case 3: /* rcr */
05f086f8 1268 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1269 break;
1270 case 4: /* sal/shl */
1271 case 6: /* sal/shl */
05f086f8 1272 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1273 break;
1274 case 5: /* shr */
05f086f8 1275 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1276 break;
1277 case 7: /* sar */
05f086f8 1278 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1279 break;
1280 }
1281}
1282
1283static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1284 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1285{
1286 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1287
1288 switch (c->modrm_reg) {
1289 case 0 ... 1: /* test */
05f086f8 1290 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1291 break;
1292 case 2: /* not */
1293 c->dst.val = ~c->dst.val;
1294 break;
1295 case 3: /* neg */
05f086f8 1296 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1297 break;
1298 default:
aca06a83 1299 return 0;
8cdbd2c9 1300 }
aca06a83 1301 return 1;
8cdbd2c9
LV		 1302}
1303
1304static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1305 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1306{
1307 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1308
1309 switch (c->modrm_reg) {
1310 case 0: /* inc */
05f086f8 1311 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1312 break;
1313 case 1: /* dec */
05f086f8 1314 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1315 break;
d19292e4
MG		 1316 case 2: /* call near abs */ {
1317 long int old_eip;
1318 old_eip = c->eip;
1319 c->eip = c->src.val;
1320 c->src.val = old_eip;
79168fd1 1321 emulate_push(ctxt, ops);
d19292e4
MG		 1322 break;
1323 }
8cdbd2c9 1324 case 4: /* jmp abs */
fd60754e 1325 c->eip = c->src.val;
8cdbd2c9
LV		 1326 break;
1327 case 6: /* push */
79168fd1 1328 emulate_push(ctxt, ops);
8cdbd2c9 1329 break;
8cdbd2c9 1330 }
1b30eaa8 1331 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1332}
1333
1334static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1335 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1336{
1337 struct decode_cache *c = &ctxt->decode;
16518d5a 1338 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1339
1340 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1341 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1342 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1343 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1344 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1345 } else {
16518d5a
AK		 1346 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1347 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1348
05f086f8 1349 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1350 }
1b30eaa8 1351 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1352}
1353
a77ab5ea
AK		 1354static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1355 struct x86_emulate_ops *ops)
1356{
1357 struct decode_cache *c = &ctxt->decode;
1358 int rc;
1359 unsigned long cs;
1360
1361 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1362 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1363 return rc;
1364 if (c->op_bytes == 4)
1365 c->eip = (u32)c->eip;
1366 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1367 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1368 return rc;
2e873022 1369 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1370 return rc;
1371}
1372
e66bb2cc
AP		 1373static inline void
1374setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1375 struct x86_emulate_ops *ops, struct desc_struct *cs,
1376 struct desc_struct *ss)
e66bb2cc 1377{
79168fd1
GN		 1378 memset(cs, 0, sizeof(struct desc_struct));
1379 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1380 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1381
1382 cs->l = 0; /* will be adjusted later */
79168fd1 1383 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1384 cs->g = 1; /* 4kb granularity */
79168fd1 1385 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1386 cs->type = 0x0b; /* Read, Execute, Accessed */
1387 cs->s = 1;
1388 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1389 cs->p = 1;
1390 cs->d = 1;
e66bb2cc 1391
79168fd1
GN		 1392 set_desc_base(ss, 0); /* flat segment */
1393 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1394 ss->g = 1; /* 4kb granularity */
1395 ss->s = 1;
1396 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1397 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1398 ss->dpl = 0;
79168fd1 1399 ss->p = 1;
e66bb2cc
AP		 1400}
1401
1402static int
3fb1b5db 1403emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1404{
1405 struct decode_cache *c = &ctxt->decode;
79168fd1 1406 struct desc_struct cs, ss;
e66bb2cc 1407 u64 msr_data;
79168fd1 1408 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1409
1410 /* syscall is not available in real mode */
2e901c4c
GN		 1411 if (ctxt->mode == X86EMUL_MODE_REAL ||
1412 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1413 emulate_ud(ctxt);
2e901c4c
GN		 1414 return X86EMUL_PROPAGATE_FAULT;
1415 }
e66bb2cc 1416
79168fd1 1417 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1418
3fb1b5db 1419 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1420 msr_data >>= 32;
79168fd1
GN		 1421 cs_sel = (u16)(msr_data & 0xfffc);
1422 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1423
1424 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1425 cs.d = 0;
e66bb2cc
AP		 1426 cs.l = 1;
1427 }
79168fd1
GN		 1428 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1429 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1430 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1431 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1432
1433 c->regs[VCPU_REGS_RCX] = c->eip;
1434 if (is_long_mode(ctxt->vcpu)) {
1435#ifdef CONFIG_X86_64
1436 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1437
3fb1b5db
GN		 1438 ops->get_msr(ctxt->vcpu,
1439 ctxt->mode == X86EMUL_MODE_PROT64 ?
1440 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1441 c->eip = msr_data;
1442
3fb1b5db 1443 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1444 ctxt->eflags &= ~(msr_data | EFLG_RF);
1445#endif
1446 } else {
1447 /* legacy mode */
3fb1b5db 1448 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1449 c->eip = (u32)msr_data;
1450
1451 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1452 }
1453
e54cfa97 1454 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1455}
1456
8c604352 1457static int
3fb1b5db 1458emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1459{
1460 struct decode_cache *c = &ctxt->decode;
79168fd1 1461 struct desc_struct cs, ss;
8c604352 1462 u64 msr_data;
79168fd1 1463 u16 cs_sel, ss_sel;
8c604352 1464
a0044755
GN		 1465 /* inject #GP if in real mode */
1466 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1467 emulate_gp(ctxt, 0);
2e901c4c 1468 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1469 }
1470
1471 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1472 * Therefore, we inject an #UD.
1473 */
2e901c4c 1474 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1475 emulate_ud(ctxt);
2e901c4c
GN		 1476 return X86EMUL_PROPAGATE_FAULT;
1477 }
8c604352 1478
79168fd1 1479 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1480
3fb1b5db 1481 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1482 switch (ctxt->mode) {
1483 case X86EMUL_MODE_PROT32:
1484 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1485 emulate_gp(ctxt, 0);
e54cfa97 1486 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1487 }
1488 break;
1489 case X86EMUL_MODE_PROT64:
1490 if (msr_data == 0x0) {
54b8486f 1491 emulate_gp(ctxt, 0);
e54cfa97 1492 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1493 }
1494 break;
1495 }
1496
1497 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1498 cs_sel = (u16)msr_data;
1499 cs_sel &= ~SELECTOR_RPL_MASK;
1500 ss_sel = cs_sel + 8;
1501 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1502 if (ctxt->mode == X86EMUL_MODE_PROT64
1503 || is_long_mode(ctxt->vcpu)) {
79168fd1 1504 cs.d = 0;
8c604352
AP		 1505 cs.l = 1;
1506 }
1507
79168fd1
GN		 1508 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1509 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1510 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1511 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1512
3fb1b5db 1513 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1514 c->eip = msr_data;
1515
3fb1b5db 1516 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1517 c->regs[VCPU_REGS_RSP] = msr_data;
1518
e54cfa97 1519 return X86EMUL_CONTINUE;
8c604352
AP		 1520}
1521
4668f050 1522static int
3fb1b5db 1523emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1524{
1525 struct decode_cache *c = &ctxt->decode;
79168fd1 1526 struct desc_struct cs, ss;
4668f050
AP		 1527 u64 msr_data;
1528 int usermode;
79168fd1 1529 u16 cs_sel, ss_sel;
4668f050 1530
a0044755
GN		 1531 /* inject #GP if in real mode or Virtual 8086 mode */
1532 if (ctxt->mode == X86EMUL_MODE_REAL ||
1533 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1534 emulate_gp(ctxt, 0);
2e901c4c 1535 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1536 }
1537
79168fd1 1538 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1539
1540 if ((c->rex_prefix & 0x8) != 0x0)
1541 usermode = X86EMUL_MODE_PROT64;
1542 else
1543 usermode = X86EMUL_MODE_PROT32;
1544
1545 cs.dpl = 3;
1546 ss.dpl = 3;
3fb1b5db 1547 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1548 switch (usermode) {
1549 case X86EMUL_MODE_PROT32:
79168fd1 1550 cs_sel = (u16)(msr_data + 16);
4668f050 1551 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1552 emulate_gp(ctxt, 0);
e54cfa97 1553 return X86EMUL_PROPAGATE_FAULT;
4668f050 1554 }
79168fd1 1555 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1556 break;
1557 case X86EMUL_MODE_PROT64:
79168fd1 1558 cs_sel = (u16)(msr_data + 32);
4668f050 1559 if (msr_data == 0x0) {
54b8486f 1560 emulate_gp(ctxt, 0);
e54cfa97 1561 return X86EMUL_PROPAGATE_FAULT;
4668f050 1562 }
79168fd1
GN		 1563 ss_sel = cs_sel + 8;
1564 cs.d = 0;
4668f050
AP		 1565 cs.l = 1;
1566 break;
1567 }
79168fd1
GN		 1568 cs_sel |= SELECTOR_RPL_MASK;
1569 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1570
79168fd1
GN		 1571 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1572 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1573 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1574 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1575
bdb475a3
GN		 1576 c->eip = c->regs[VCPU_REGS_RDX];
1577 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1578
e54cfa97 1579 return X86EMUL_CONTINUE;
4668f050
AP		 1580}
1581
9c537244
GN		 1582static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1583 struct x86_emulate_ops *ops)
f850e2e6
GN		 1584{
1585 int iopl;
1586 if (ctxt->mode == X86EMUL_MODE_REAL)
1587 return false;
1588 if (ctxt->mode == X86EMUL_MODE_VM86)
1589 return true;
1590 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1591 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1592}
1593
1594static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1595 struct x86_emulate_ops *ops,
1596 u16 port, u16 len)
1597{
79168fd1 1598 struct desc_struct tr_seg;
f850e2e6
GN		 1599 int r;
1600 u16 io_bitmap_ptr;
1601 u8 perm, bit_idx = port & 0x7;
1602 unsigned mask = (1 << len) - 1;
1603
79168fd1
GN		 1604 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1605 if (!tr_seg.p)
f850e2e6 1606 return false;
79168fd1 1607 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1608 return false;
79168fd1
GN		 1609 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1610 ctxt->vcpu, NULL);
f850e2e6
GN		 1611 if (r != X86EMUL_CONTINUE)
1612 return false;
79168fd1 1613 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1614 return false;
79168fd1
GN		 1615 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1616 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1617 if (r != X86EMUL_CONTINUE)
1618 return false;
1619 if ((perm >> bit_idx) & mask)
1620 return false;
1621 return true;
1622}
1623
1624static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1625 struct x86_emulate_ops *ops,
1626 u16 port, u16 len)
1627{
4fc40f07
GN		 1628 if (ctxt->perm_ok)
1629 return true;
1630
9c537244 1631 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1632 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1633 return false;
4fc40f07
GN		 1634
1635 ctxt->perm_ok = true;
1636
f850e2e6
GN		 1637 return true;
1638}
1639
38ba30ba
GN		 1640static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1641 struct x86_emulate_ops *ops,
1642 struct tss_segment_16 *tss)
1643{
1644 struct decode_cache *c = &ctxt->decode;
1645
1646 tss->ip = c->eip;
1647 tss->flag = ctxt->eflags;
1648 tss->ax = c->regs[VCPU_REGS_RAX];
1649 tss->cx = c->regs[VCPU_REGS_RCX];
1650 tss->dx = c->regs[VCPU_REGS_RDX];
1651 tss->bx = c->regs[VCPU_REGS_RBX];
1652 tss->sp = c->regs[VCPU_REGS_RSP];
1653 tss->bp = c->regs[VCPU_REGS_RBP];
1654 tss->si = c->regs[VCPU_REGS_RSI];
1655 tss->di = c->regs[VCPU_REGS_RDI];
1656
1657 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1658 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1659 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1660 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1661 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1662}
1663
1664static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1665 struct x86_emulate_ops *ops,
1666 struct tss_segment_16 *tss)
1667{
1668 struct decode_cache *c = &ctxt->decode;
1669 int ret;
1670
1671 c->eip = tss->ip;
1672 ctxt->eflags = tss->flag | 2;
1673 c->regs[VCPU_REGS_RAX] = tss->ax;
1674 c->regs[VCPU_REGS_RCX] = tss->cx;
1675 c->regs[VCPU_REGS_RDX] = tss->dx;
1676 c->regs[VCPU_REGS_RBX] = tss->bx;
1677 c->regs[VCPU_REGS_RSP] = tss->sp;
1678 c->regs[VCPU_REGS_RBP] = tss->bp;
1679 c->regs[VCPU_REGS_RSI] = tss->si;
1680 c->regs[VCPU_REGS_RDI] = tss->di;
1681
1682 /*
1683 * SDM says that segment selectors are loaded before segment
1684 * descriptors
1685 */
1686 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1687 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1688 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1689 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1690 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1691
1692 /*
1693 * Now load segment descriptors. If fault happenes at this stage
1694 * it is handled in a context of new task
1695 */
1696 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1697 if (ret != X86EMUL_CONTINUE)
1698 return ret;
1699 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1700 if (ret != X86EMUL_CONTINUE)
1701 return ret;
1702 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1703 if (ret != X86EMUL_CONTINUE)
1704 return ret;
1705 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1706 if (ret != X86EMUL_CONTINUE)
1707 return ret;
1708 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1709 if (ret != X86EMUL_CONTINUE)
1710 return ret;
1711
1712 return X86EMUL_CONTINUE;
1713}
1714
1715static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1716 struct x86_emulate_ops *ops,
1717 u16 tss_selector, u16 old_tss_sel,
1718 ulong old_tss_base, struct desc_struct *new_desc)
1719{
1720 struct tss_segment_16 tss_seg;
1721 int ret;
1722 u32 err, new_tss_base = get_desc_base(new_desc);
1723
1724 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1725 &err);
1726 if (ret == X86EMUL_PROPAGATE_FAULT) {
1727 /* FIXME: need to provide precise fault address */
54b8486f 1728 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1729 return ret;
1730 }
1731
1732 save_state_to_tss16(ctxt, ops, &tss_seg);
1733
1734 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1735 &err);
1736 if (ret == X86EMUL_PROPAGATE_FAULT) {
1737 /* FIXME: need to provide precise fault address */
54b8486f 1738 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1739 return ret;
1740 }
1741
1742 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1743 &err);
1744 if (ret == X86EMUL_PROPAGATE_FAULT) {
1745 /* FIXME: need to provide precise fault address */
54b8486f 1746 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1747 return ret;
1748 }
1749
1750 if (old_tss_sel != 0xffff) {
1751 tss_seg.prev_task_link = old_tss_sel;
1752
1753 ret = ops->write_std(new_tss_base,
1754 &tss_seg.prev_task_link,
1755 sizeof tss_seg.prev_task_link,
1756 ctxt->vcpu, &err);
1757 if (ret == X86EMUL_PROPAGATE_FAULT) {
1758 /* FIXME: need to provide precise fault address */
54b8486f 1759 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1760 return ret;
1761 }
1762 }
1763
1764 return load_state_from_tss16(ctxt, ops, &tss_seg);
1765}
1766
1767static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1768 struct x86_emulate_ops *ops,
1769 struct tss_segment_32 *tss)
1770{
1771 struct decode_cache *c = &ctxt->decode;
1772
1773 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1774 tss->eip = c->eip;
1775 tss->eflags = ctxt->eflags;
1776 tss->eax = c->regs[VCPU_REGS_RAX];
1777 tss->ecx = c->regs[VCPU_REGS_RCX];
1778 tss->edx = c->regs[VCPU_REGS_RDX];
1779 tss->ebx = c->regs[VCPU_REGS_RBX];
1780 tss->esp = c->regs[VCPU_REGS_RSP];
1781 tss->ebp = c->regs[VCPU_REGS_RBP];
1782 tss->esi = c->regs[VCPU_REGS_RSI];
1783 tss->edi = c->regs[VCPU_REGS_RDI];
1784
1785 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1786 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1787 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1788 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1789 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1790 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1791 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1792}
1793
1794static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1795 struct x86_emulate_ops *ops,
1796 struct tss_segment_32 *tss)
1797{
1798 struct decode_cache *c = &ctxt->decode;
1799 int ret;
1800
0f12244f 1801 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 1802 emulate_gp(ctxt, 0);
0f12244f
GN		 1803 return X86EMUL_PROPAGATE_FAULT;
1804 }
38ba30ba
GN		 1805 c->eip = tss->eip;
1806 ctxt->eflags = tss->eflags | 2;
1807 c->regs[VCPU_REGS_RAX] = tss->eax;
1808 c->regs[VCPU_REGS_RCX] = tss->ecx;
1809 c->regs[VCPU_REGS_RDX] = tss->edx;
1810 c->regs[VCPU_REGS_RBX] = tss->ebx;
1811 c->regs[VCPU_REGS_RSP] = tss->esp;
1812 c->regs[VCPU_REGS_RBP] = tss->ebp;
1813 c->regs[VCPU_REGS_RSI] = tss->esi;
1814 c->regs[VCPU_REGS_RDI] = tss->edi;
1815
1816 /*
1817 * SDM says that segment selectors are loaded before segment
1818 * descriptors
1819 */
1820 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1821 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1822 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1823 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1824 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1825 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1826 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1827
1828 /*
1829 * Now load segment descriptors. If fault happenes at this stage
1830 * it is handled in a context of new task
1831 */
1832 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1833 if (ret != X86EMUL_CONTINUE)
1834 return ret;
1835 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1836 if (ret != X86EMUL_CONTINUE)
1837 return ret;
1838 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1839 if (ret != X86EMUL_CONTINUE)
1840 return ret;
1841 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1842 if (ret != X86EMUL_CONTINUE)
1843 return ret;
1844 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1845 if (ret != X86EMUL_CONTINUE)
1846 return ret;
1847 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1848 if (ret != X86EMUL_CONTINUE)
1849 return ret;
1850 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1851 if (ret != X86EMUL_CONTINUE)
1852 return ret;
1853
1854 return X86EMUL_CONTINUE;
1855}
1856
1857static int task_switch_32(struct x86_emulate_ctxt *ctxt,
1858 struct x86_emulate_ops *ops,
1859 u16 tss_selector, u16 old_tss_sel,
1860 ulong old_tss_base, struct desc_struct *new_desc)
1861{
1862 struct tss_segment_32 tss_seg;
1863 int ret;
1864 u32 err, new_tss_base = get_desc_base(new_desc);
1865
1866 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1867 &err);
1868 if (ret == X86EMUL_PROPAGATE_FAULT) {
1869 /* FIXME: need to provide precise fault address */
54b8486f 1870 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1871 return ret;
1872 }
1873
1874 save_state_to_tss32(ctxt, ops, &tss_seg);
1875
1876 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1877 &err);
1878 if (ret == X86EMUL_PROPAGATE_FAULT) {
1879 /* FIXME: need to provide precise fault address */
54b8486f 1880 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1881 return ret;
1882 }
1883
1884 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1885 &err);
1886 if (ret == X86EMUL_PROPAGATE_FAULT) {
1887 /* FIXME: need to provide precise fault address */
54b8486f 1888 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1889 return ret;
1890 }
1891
1892 if (old_tss_sel != 0xffff) {
1893 tss_seg.prev_task_link = old_tss_sel;
1894
1895 ret = ops->write_std(new_tss_base,
1896 &tss_seg.prev_task_link,
1897 sizeof tss_seg.prev_task_link,
1898 ctxt->vcpu, &err);
1899 if (ret == X86EMUL_PROPAGATE_FAULT) {
1900 /* FIXME: need to provide precise fault address */
54b8486f 1901 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1902 return ret;
1903 }
1904 }
1905
1906 return load_state_from_tss32(ctxt, ops, &tss_seg);
1907}
1908
1909static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1910 struct x86_emulate_ops *ops,
1911 u16 tss_selector, int reason,
1912 bool has_error_code, u32 error_code)
38ba30ba
GN		 1913{
1914 struct desc_struct curr_tss_desc, next_tss_desc;
1915 int ret;
1916 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
1917 ulong old_tss_base =
5951c442 1918 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 1919 u32 desc_limit;
38ba30ba
GN		 1920
1921 /* FIXME: old_tss_base == ~0 ? */
1922
1923 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
1924 if (ret != X86EMUL_CONTINUE)
1925 return ret;
1926 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
1927 if (ret != X86EMUL_CONTINUE)
1928 return ret;
1929
1930 /* FIXME: check that next_tss_desc is tss */
1931
1932 if (reason != TASK_SWITCH_IRET) {
1933 if ((tss_selector & 3) > next_tss_desc.dpl ||
1934 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 1935 emulate_gp(ctxt, 0);
38ba30ba
GN		 1936 return X86EMUL_PROPAGATE_FAULT;
1937 }
1938 }
1939
ceffb459
GN		 1940 desc_limit = desc_limit_scaled(&next_tss_desc);
1941 if (!next_tss_desc.p ||
1942 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
1943 desc_limit < 0x2b)) {
54b8486f 1944 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 1945 return X86EMUL_PROPAGATE_FAULT;
1946 }
1947
1948 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
1949 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
1950 write_segment_descriptor(ctxt, ops, old_tss_sel,
1951 &curr_tss_desc);
1952 }
1953
1954 if (reason == TASK_SWITCH_IRET)
1955 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
1956
1957 /* set back link to prev task only if NT bit is set in eflags
1958 note that old_tss_sel is not used afetr this point */
1959 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
1960 old_tss_sel = 0xffff;
1961
1962 if (next_tss_desc.type & 8)
1963 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
1964 old_tss_base, &next_tss_desc);
1965 else
1966 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
1967 old_tss_base, &next_tss_desc);
0760d448
JK		 1968 if (ret != X86EMUL_CONTINUE)
1969 return ret;
38ba30ba
GN		 1970
1971 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
1972 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
1973
1974 if (reason != TASK_SWITCH_IRET) {
1975 next_tss_desc.type |= (1 << 1); /* set busy flag */
1976 write_segment_descriptor(ctxt, ops, tss_selector,
1977 &next_tss_desc);
1978 }
1979
1980 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
1981 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
1982 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
1983
e269fb21
JK		 1984 if (has_error_code) {
1985 struct decode_cache *c = &ctxt->decode;
1986
1987 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
1988 c->lock_prefix = 0;
1989 c->src.val = (unsigned long) error_code;
79168fd1 1990 emulate_push(ctxt, ops);
e269fb21
JK		 1991 }
1992
38ba30ba
GN		 1993 return ret;
1994}
1995
1996int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1997 u16 tss_selector, int reason,
1998 bool has_error_code, u32 error_code)
38ba30ba 1999{
9aabc88f 2000 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2001 struct decode_cache *c = &ctxt->decode;
2002 int rc;
2003
38ba30ba 2004 c->eip = ctxt->eip;
e269fb21 2005 c->dst.type = OP_NONE;
38ba30ba 2006
e269fb21
JK		 2007 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2008 has_error_code, error_code);
38ba30ba
GN		 2009
2010 if (rc == X86EMUL_CONTINUE) {
e269fb21 2011 rc = writeback(ctxt, ops);
95c55886
GN		 2012 if (rc == X86EMUL_CONTINUE)
2013 ctxt->eip = c->eip;
38ba30ba
GN		 2014 }
2015
19d04437 2016 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2017}
2018
a682e354 2019static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2020 int reg, struct operand *op)
a682e354
GN		 2021{
2022 struct decode_cache *c = &ctxt->decode;
2023 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2024
d9271123 2025 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2026 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2027}
2028
63540382
AK		 2029static int em_push(struct x86_emulate_ctxt *ctxt)
2030{
2031 emulate_push(ctxt, ctxt->ops);
2032 return X86EMUL_CONTINUE;
2033}
2034
73fba5f4
AK		 2035#define D(_y) { .flags = (_y) }
2036#define N D(0)
2037#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2038#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2039#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2040
2041static struct opcode group1[] = {
2042 X7(D(Lock)), N
2043};
2044
2045static struct opcode group1A[] = {
2046 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2047};
2048
2049static struct opcode group3[] = {
2050 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2051 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2052 X4(D(Undefined)),
2053};
2054
2055static struct opcode group4[] = {
2056 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2057 N, N, N, N, N, N,
2058};
2059
2060static struct opcode group5[] = {
2061 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2062 D(SrcMem | ModRM | Stack), N,
2063 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2064 D(SrcMem | ModRM | Stack), N,
2065};
2066
2067static struct group_dual group7 = { {
2068 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2069 D(SrcNone | ModRM | DstMem | Mov), N,
2070 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2071}, {
2072 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2073 D(SrcNone | ModRM | DstMem | Mov), N,
2074 D(SrcMem16 | ModRM | Mov | Priv), N,
2075} };
2076
2077static struct opcode group8[] = {
2078 N, N, N, N,
2079 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2080 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2081};
2082
2083static struct group_dual group9 = { {
2084 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2085}, {
2086 N, N, N, N, N, N, N, N,
2087} };
2088
2089static struct opcode opcode_table[256] = {
2090 /* 0x00 - 0x07 */
2091 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2092 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2093 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2094 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2095 /* 0x08 - 0x0F */
2096 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2097 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2098 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2099 D(ImplicitOps | Stack | No64), N,
2100 /* 0x10 - 0x17 */
2101 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2102 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2103 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2104 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2105 /* 0x18 - 0x1F */
2106 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2107 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2108 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2109 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2110 /* 0x20 - 0x27 */
2111 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2112 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2113 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2114 /* 0x28 - 0x2F */
2115 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2116 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2117 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2118 /* 0x30 - 0x37 */
2119 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2120 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2121 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2122 /* 0x38 - 0x3F */
2123 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2124 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2125 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2126 N, N,
2127 /* 0x40 - 0x4F */
2128 X16(D(DstReg)),
2129 /* 0x50 - 0x57 */
63540382 2130 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2131 /* 0x58 - 0x5F */
2132 X8(D(DstReg | Stack)),
2133 /* 0x60 - 0x67 */
2134 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2135 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2136 N, N, N, N,
2137 /* 0x68 - 0x6F */
63540382
AK		 2138 I(SrcImm | Mov | Stack, em_push), N,
2139 I(SrcImmByte | Mov | Stack, em_push), N,
73fba5f4
AK		 2140 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2141 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2142 /* 0x70 - 0x7F */
2143 X16(D(SrcImmByte)),
2144 /* 0x80 - 0x87 */
2145 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2146 G(DstMem | SrcImm | ModRM | Group, group1),
2147 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2148 G(DstMem | SrcImmByte | ModRM | Group, group1),
2149 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2150 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2151 /* 0x88 - 0x8F */
2152 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2153 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2154 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
2155 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2156 /* 0x90 - 0x97 */
3d9e77df 2157 X8(D(SrcAcc | DstReg)),
73fba5f4
AK		 2158 /* 0x98 - 0x9F */
2159 N, N, D(SrcImmFAddr | No64), N,
2160 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2161 /* 0xA0 - 0xA7 */
2162 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2163 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2164 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2165 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2166 /* 0xA8 - 0xAF */
2167 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
2168 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2169 D(ByteOp | DstDI | String), D(DstDI | String),
2170 /* 0xB0 - 0xB7 */
2171 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2172 /* 0xB8 - 0xBF */
2173 X8(D(DstReg | SrcImm | Mov)),
2174 /* 0xC0 - 0xC7 */
2175 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2176 N, D(ImplicitOps | Stack), N, N,
2177 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2178 /* 0xC8 - 0xCF */
2179 N, N, N, D(ImplicitOps | Stack),
2180 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2181 /* 0xD0 - 0xD7 */
2182 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2183 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2184 N, N, N, N,
2185 /* 0xD8 - 0xDF */
2186 N, N, N, N, N, N, N, N,
2187 /* 0xE0 - 0xE7 */
2188 N, N, N, N,
2189 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2190 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2191 /* 0xE8 - 0xEF */
2192 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2193 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2194 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2195 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2196 /* 0xF0 - 0xF7 */
2197 N, N, N, N,
2198 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2199 /* 0xF8 - 0xFF */
2200 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
2201 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2202};
2203
2204static struct opcode twobyte_table[256] = {
2205 /* 0x00 - 0x0F */
2206 N, GD(0, &group7), N, N,
2207 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2208 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2209 N, D(ImplicitOps | ModRM), N, N,
2210 /* 0x10 - 0x1F */
2211 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2212 /* 0x20 - 0x2F */
b27f3856
AK		 2213 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2214 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2215 N, N, N, N,
2216 N, N, N, N, N, N, N, N,
2217 /* 0x30 - 0x3F */
2218 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2219 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2220 N, N, N, N, N, N, N, N,
2221 /* 0x40 - 0x4F */
2222 X16(D(DstReg | SrcMem | ModRM | Mov)),
2223 /* 0x50 - 0x5F */
2224 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2225 /* 0x60 - 0x6F */
2226 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2227 /* 0x70 - 0x7F */
2228 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2229 /* 0x80 - 0x8F */
2230 X16(D(SrcImm)),
2231 /* 0x90 - 0x9F */
2232 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2233 /* 0xA0 - 0xA7 */
2234 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2235 N, D(DstMem | SrcReg | ModRM | BitOp),
2236 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2237 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2238 /* 0xA8 - 0xAF */
2239 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2240 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2241 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2242 D(DstMem | SrcReg | Src2CL | ModRM),
2243 D(ModRM), N,
2244 /* 0xB0 - 0xB7 */
2245 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2246 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2247 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2248 D(DstReg | SrcMem16 | ModRM | Mov),
2249 /* 0xB8 - 0xBF */
2250 N, N,
2251 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2252 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2253 D(DstReg | SrcMem16 | ModRM | Mov),
2254 /* 0xC0 - 0xCF */
2255 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
2256 N, N, N, GD(0, &group9),
2257 N, N, N, N, N, N, N, N,
2258 /* 0xD0 - 0xDF */
2259 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2260 /* 0xE0 - 0xEF */
2261 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2262 /* 0xF0 - 0xFF */
2263 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2264};
2265
2266#undef D
2267#undef N
2268#undef G
2269#undef GD
2270#undef I
2271
dde7e6d1
AK		 2272int
2273x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2274{
2275 struct x86_emulate_ops *ops = ctxt->ops;
2276 struct decode_cache *c = &ctxt->decode;
2277 int rc = X86EMUL_CONTINUE;
2278 int mode = ctxt->mode;
2279 int def_op_bytes, def_ad_bytes, dual, goffset;
2280 struct opcode opcode, *g_mod012, *g_mod3;
2281
2282 /* we cannot decode insn before we complete previous rep insn */
2283 WARN_ON(ctxt->restart);
2284
2285 c->eip = ctxt->eip;
2286 c->fetch.start = c->fetch.end = c->eip;
2287 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2288
2289 switch (mode) {
2290 case X86EMUL_MODE_REAL:
2291 case X86EMUL_MODE_VM86:
2292 case X86EMUL_MODE_PROT16:
2293 def_op_bytes = def_ad_bytes = 2;
2294 break;
2295 case X86EMUL_MODE_PROT32:
2296 def_op_bytes = def_ad_bytes = 4;
2297 break;
2298#ifdef CONFIG_X86_64
2299 case X86EMUL_MODE_PROT64:
2300 def_op_bytes = 4;
2301 def_ad_bytes = 8;
2302 break;
2303#endif
2304 default:
2305 return -1;
2306 }
2307
2308 c->op_bytes = def_op_bytes;
2309 c->ad_bytes = def_ad_bytes;
2310
2311 /* Legacy prefixes. */
2312 for (;;) {
2313 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2314 case 0x66: /* operand-size override */
2315 /* switch between 2/4 bytes */
2316 c->op_bytes = def_op_bytes ^ 6;
2317 break;
2318 case 0x67: /* address-size override */
2319 if (mode == X86EMUL_MODE_PROT64)
2320 /* switch between 4/8 bytes */
2321 c->ad_bytes = def_ad_bytes ^ 12;
2322 else
2323 /* switch between 2/4 bytes */
2324 c->ad_bytes = def_ad_bytes ^ 6;
2325 break;
2326 case 0x26: /* ES override */
2327 case 0x2e: /* CS override */
2328 case 0x36: /* SS override */
2329 case 0x3e: /* DS override */
2330 set_seg_override(c, (c->b >> 3) & 3);
2331 break;
2332 case 0x64: /* FS override */
2333 case 0x65: /* GS override */
2334 set_seg_override(c, c->b & 7);
2335 break;
2336 case 0x40 ... 0x4f: /* REX */
2337 if (mode != X86EMUL_MODE_PROT64)
2338 goto done_prefixes;
2339 c->rex_prefix = c->b;
2340 continue;
2341 case 0xf0: /* LOCK */
2342 c->lock_prefix = 1;
2343 break;
2344 case 0xf2: /* REPNE/REPNZ */
2345 c->rep_prefix = REPNE_PREFIX;
2346 break;
2347 case 0xf3: /* REP/REPE/REPZ */
2348 c->rep_prefix = REPE_PREFIX;
2349 break;
2350 default:
2351 goto done_prefixes;
2352 }
2353
2354 /* Any legacy prefix after a REX prefix nullifies its effect. */
2355
2356 c->rex_prefix = 0;
2357 }
2358
2359done_prefixes:
2360
2361 /* REX prefix. */
1e87e3ef
AK		 2362 if (c->rex_prefix & 8)
2363 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2364
2365 /* Opcode byte(s). */
2366 opcode = opcode_table[c->b];
2367 if (opcode.flags == 0) {
2368 /* Two-byte opcode? */
2369 if (c->b == 0x0f) {
2370 c->twobyte = 1;
2371 c->b = insn_fetch(u8, 1, c->eip);
2372 opcode = twobyte_table[c->b];
2373 }
2374 }
2375 c->d = opcode.flags;
2376
2377 if (c->d & Group) {
2378 dual = c->d & GroupDual;
2379 c->modrm = insn_fetch(u8, 1, c->eip);
2380 --c->eip;
2381
2382 if (c->d & GroupDual) {
2383 g_mod012 = opcode.u.gdual->mod012;
2384 g_mod3 = opcode.u.gdual->mod3;
2385 } else
2386 g_mod012 = g_mod3 = opcode.u.group;
2387
2388 c->d &= ~(Group | GroupDual);
2389
2390 goffset = (c->modrm >> 3) & 7;
2391
2392 if ((c->modrm >> 6) == 3)
2393 opcode = g_mod3[goffset];
2394 else
2395 opcode = g_mod012[goffset];
2396 c->d |= opcode.flags;
2397 }
2398
2399 c->execute = opcode.u.execute;
2400
2401 /* Unrecognised? */
2402 if (c->d == 0 || (c->d & Undefined)) {
2403 DPRINTF("Cannot emulate %02x\n", c->b);
2404 return -1;
2405 }
2406
2407 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2408 c->op_bytes = 8;
2409
7f9b4b75
AK		 2410 if (c->d & Op3264) {
2411 if (mode == X86EMUL_MODE_PROT64)
2412 c->op_bytes = 8;
2413 else
2414 c->op_bytes = 4;
2415 }
2416
dde7e6d1 2417 /* ModRM and SIB bytes. */
09ee57cd 2418 if (c->d & ModRM) {
dde7e6d1 2419 rc = decode_modrm(ctxt, ops);
09ee57cd
AK		 2420 if (!c->has_seg_override)
2421 set_seg_override(c, c->modrm_seg);
2422 } else if (c->d & MemAbs)
dde7e6d1
AK		 2423 rc = decode_abs(ctxt, ops);
2424 if (rc != X86EMUL_CONTINUE)
2425 goto done;
2426
2427 if (!c->has_seg_override)
2428 set_seg_override(c, VCPU_SREG_DS);
2429
2430 if (!(!c->twobyte && c->b == 0x8d))
2431 c->modrm_ea += seg_override_base(ctxt, ops, c);
2432
2433 if (c->ad_bytes != 8)
2434 c->modrm_ea = (u32)c->modrm_ea;
2435
2436 if (c->rip_relative)
2437 c->modrm_ea += c->eip;
2438
2439 /*
2440 * Decode and fetch the source operand: register, memory
2441 * or immediate.
2442 */
2443 switch (c->d & SrcMask) {
2444 case SrcNone:
2445 break;
2446 case SrcReg:
2447 decode_register_operand(&c->src, c, 0);
2448 break;
2449 case SrcMem16:
2450 c->src.bytes = 2;
2451 goto srcmem_common;
2452 case SrcMem32:
2453 c->src.bytes = 4;
2454 goto srcmem_common;
2455 case SrcMem:
2456 c->src.bytes = (c->d & ByteOp) ? 1 :
2457 c->op_bytes;
2458 /* Don't fetch the address for invlpg: it could be unmapped. */
2459 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
2460 break;
2461 srcmem_common:
2462 /*
2463 * For instructions with a ModR/M byte, switch to register
2464 * access if Mod = 3.
2465 */
2466 if ((c->d & ModRM) && c->modrm_mod == 3) {
2467 c->src.type = OP_REG;
2468 c->src.val = c->modrm_val;
1a6440ae 2469 c->src.addr.reg = c->modrm_ptr;
dde7e6d1
AK		 2470 break;
2471 }
2472 c->src.type = OP_MEM;
1a6440ae 2473 c->src.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2474 c->src.val = 0;
2475 break;
2476 case SrcImm:
2477 case SrcImmU:
2478 c->src.type = OP_IMM;
1a6440ae 2479 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2480 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2481 if (c->src.bytes == 8)
2482 c->src.bytes = 4;
2483 /* NB. Immediates are sign-extended as necessary. */
2484 switch (c->src.bytes) {
2485 case 1:
2486 c->src.val = insn_fetch(s8, 1, c->eip);
2487 break;
2488 case 2:
2489 c->src.val = insn_fetch(s16, 2, c->eip);
2490 break;
2491 case 4:
2492 c->src.val = insn_fetch(s32, 4, c->eip);
2493 break;
2494 }
2495 if ((c->d & SrcMask) == SrcImmU) {
2496 switch (c->src.bytes) {
2497 case 1:
2498 c->src.val &= 0xff;
2499 break;
2500 case 2:
2501 c->src.val &= 0xffff;
2502 break;
2503 case 4:
2504 c->src.val &= 0xffffffff;
2505 break;
2506 }
2507 }
2508 break;
2509 case SrcImmByte:
2510 case SrcImmUByte:
2511 c->src.type = OP_IMM;
1a6440ae 2512 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2513 c->src.bytes = 1;
2514 if ((c->d & SrcMask) == SrcImmByte)
2515 c->src.val = insn_fetch(s8, 1, c->eip);
2516 else
2517 c->src.val = insn_fetch(u8, 1, c->eip);
2518 break;
2519 case SrcAcc:
2520 c->src.type = OP_REG;
2521 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2522 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2523 fetch_register_operand(&c->src);
dde7e6d1
AK		 2524 break;
2525 case SrcOne:
2526 c->src.bytes = 1;
2527 c->src.val = 1;
2528 break;
2529 case SrcSI:
2530 c->src.type = OP_MEM;
2531 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2532 c->src.addr.mem =
dde7e6d1
AK		 2533 register_address(c, seg_override_base(ctxt, ops, c),
2534 c->regs[VCPU_REGS_RSI]);
2535 c->src.val = 0;
2536 break;
2537 case SrcImmFAddr:
2538 c->src.type = OP_IMM;
1a6440ae 2539 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2540 c->src.bytes = c->op_bytes + 2;
2541 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2542 break;
2543 case SrcMemFAddr:
2544 c->src.type = OP_MEM;
1a6440ae 2545 c->src.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2546 c->src.bytes = c->op_bytes + 2;
2547 break;
2548 }
2549
2550 /*
2551 * Decode and fetch the second source operand: register, memory
2552 * or immediate.
2553 */
2554 switch (c->d & Src2Mask) {
2555 case Src2None:
2556 break;
2557 case Src2CL:
2558 c->src2.bytes = 1;
2559 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2560 break;
2561 case Src2ImmByte:
2562 c->src2.type = OP_IMM;
1a6440ae 2563 c->src2.addr.mem = c->eip;
dde7e6d1
AK		 2564 c->src2.bytes = 1;
2565 c->src2.val = insn_fetch(u8, 1, c->eip);
2566 break;
2567 case Src2One:
2568 c->src2.bytes = 1;
2569 c->src2.val = 1;
2570 break;
2571 }
2572
2573 /* Decode and fetch the destination operand: register or memory. */
2574 switch (c->d & DstMask) {
2575 case ImplicitOps:
2576 /* Special instructions do their own operand decoding. */
2577 return 0;
2578 case DstReg:
2579 decode_register_operand(&c->dst, c,
2580 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2581 break;
2582 case DstMem:
2583 case DstMem64:
2584 if ((c->d & ModRM) && c->modrm_mod == 3) {
2585 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2586 c->dst.type = OP_REG;
2587 c->dst.val = c->dst.orig_val = c->modrm_val;
1a6440ae 2588 c->dst.addr.reg = c->modrm_ptr;
dde7e6d1
AK		 2589 break;
2590 }
2591 c->dst.type = OP_MEM;
1a6440ae 2592 c->dst.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2593 if ((c->d & DstMask) == DstMem64)
2594 c->dst.bytes = 8;
2595 else
2596 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2597 c->dst.val = 0;
2598 if (c->d & BitOp) {
2599 unsigned long mask = ~(c->dst.bytes * 8 - 1);
2600
1a6440ae 2601 c->dst.addr.mem = c->dst.addr.mem +
dde7e6d1
AK		 2602 (c->src.val & mask) / 8;
2603 }
2604 break;
2605 case DstAcc:
2606 c->dst.type = OP_REG;
2607 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2608 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2609 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2610 c->dst.orig_val = c->dst.val;
2611 break;
2612 case DstDI:
2613 c->dst.type = OP_MEM;
2614 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2615 c->dst.addr.mem =
dde7e6d1
AK		 2616 register_address(c, es_base(ctxt, ops),
2617 c->regs[VCPU_REGS_RDI]);
2618 c->dst.val = 0;
2619 break;
2620 }
2621
2622done:
2623 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2624}
2625
8b4caf66 2626int
9aabc88f 2627x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2628{
9aabc88f 2629 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2630 u64 msr_data;
8b4caf66 2631 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2632 int rc = X86EMUL_CONTINUE;
5cd21917 2633 int saved_dst_type = c->dst.type;
8b4caf66 2634
9de41573 2635 ctxt->decode.mem_read.pos = 0;
310b5d30 2636
1161624f 2637 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2638 emulate_ud(ctxt);
1161624f
GN		 2639 goto done;
2640 }
2641
d380a5e4 2642 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2643 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2644 emulate_ud(ctxt);
d380a5e4
GN		 2645 goto done;
2646 }
2647
e92805ac 2648 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2649 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2650 emulate_gp(ctxt, 0);
e92805ac
GN		 2651 goto done;
2652 }
2653
b9fa9d6b 2654 if (c->rep_prefix && (c->d & String)) {
5cd21917 2655 ctxt->restart = true;
b9fa9d6b 2656 /* All REP prefixes have the same first termination condition */
c73e197b 2657 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2658 string_done:
2659 ctxt->restart = false;
95c55886 2660 ctxt->eip = c->eip;
b9fa9d6b
AK		 2661 goto done;
2662 }
2663 /* The second termination condition only applies for REPE
2664 * and REPNE. Test if the repeat string operation prefix is
2665 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2666 * corresponding termination condition according to:
2667 * - if REPE/REPZ and ZF = 0 then done
2668 * - if REPNE/REPNZ and ZF = 1 then done
2669 */
2670 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2671 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2672 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2673 ((ctxt->eflags & EFLG_ZF) == 0))
2674 goto string_done;
b9fa9d6b 2675 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2676 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2677 goto string_done;
b9fa9d6b 2678 }
063db061 2679 c->eip = ctxt->eip;
b9fa9d6b
AK		 2680 }
2681
8b4caf66 2682 if (c->src.type == OP_MEM) {
1a6440ae 2683 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 2684 c->src.valptr, c->src.bytes);
b60d513c 2685 if (rc != X86EMUL_CONTINUE)
8b4caf66 2686 goto done;
16518d5a 2687 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2688 }
2689
e35b7b9c 2690 if (c->src2.type == OP_MEM) {
1a6440ae 2691 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 2692 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2693 if (rc != X86EMUL_CONTINUE)
2694 goto done;
2695 }
2696
8b4caf66
LV		 2697 if ((c->d & DstMask) == ImplicitOps)
2698 goto special_insn;
2699
2700
69f55cb1
GN		 2701 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2702 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 2703 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 2704 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2705 if (rc != X86EMUL_CONTINUE)
2706 goto done;
038e51de 2707 }
e4e03ded 2708 c->dst.orig_val = c->dst.val;
038e51de 2709
018a98db
AK		 2710special_insn:
2711
ef65c889
AK		 2712 if (c->execute) {
2713 rc = c->execute(ctxt);
2714 if (rc != X86EMUL_CONTINUE)
2715 goto done;
2716 goto writeback;
2717 }
2718
e4e03ded 2719 if (c->twobyte)
6aa8b732
AK		 2720 goto twobyte_insn;
2721
e4e03ded 2722 switch (c->b) {
6aa8b732
AK		 2723 case 0x00 ... 0x05:
2724 add: /* add */
05f086f8 2725 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2726 break;
0934ac9d 2727 case 0x06: /* push es */
79168fd1 2728 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2729 break;
2730 case 0x07: /* pop es */
0934ac9d 2731 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2732 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2733 goto done;
2734 break;
6aa8b732
AK		 2735 case 0x08 ... 0x0d:
2736 or: /* or */
05f086f8 2737 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2738 break;
0934ac9d 2739 case 0x0e: /* push cs */
79168fd1 2740 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2741 break;
6aa8b732
AK		 2742 case 0x10 ... 0x15:
2743 adc: /* adc */
05f086f8 2744 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2745 break;
0934ac9d 2746 case 0x16: /* push ss */
79168fd1 2747 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2748 break;
2749 case 0x17: /* pop ss */
0934ac9d 2750 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2751 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2752 goto done;
2753 break;
6aa8b732
AK		 2754 case 0x18 ... 0x1d:
2755 sbb: /* sbb */
05f086f8 2756 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2757 break;
0934ac9d 2758 case 0x1e: /* push ds */
79168fd1 2759 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2760 break;
2761 case 0x1f: /* pop ds */
0934ac9d 2762 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2763 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2764 goto done;
2765 break;
aa3a816b 2766 case 0x20 ... 0x25:
6aa8b732 2767 and: /* and */
05f086f8 2768 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2769 break;
2770 case 0x28 ... 0x2d:
2771 sub: /* sub */
05f086f8 2772 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2773 break;
2774 case 0x30 ... 0x35:
2775 xor: /* xor */
05f086f8 2776 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2777 break;
2778 case 0x38 ... 0x3d:
2779 cmp: /* cmp */
05f086f8 2780 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2781 break;
33615aa9
AK		 2782 case 0x40 ... 0x47: /* inc r16/r32 */
2783 emulate_1op("inc", c->dst, ctxt->eflags);
2784 break;
2785 case 0x48 ... 0x4f: /* dec r16/r32 */
2786 emulate_1op("dec", c->dst, ctxt->eflags);
2787 break;
33615aa9
AK		 2788 case 0x58 ... 0x5f: /* pop reg */
2789 pop_instruction:
350f69dc 2790 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2791 if (rc != X86EMUL_CONTINUE)
33615aa9 2792 goto done;
33615aa9 2793 break;
abcf14b5 2794 case 0x60: /* pusha */
c37eda13
WY		 2795 rc = emulate_pusha(ctxt, ops);
2796 if (rc != X86EMUL_CONTINUE)
2797 goto done;
abcf14b5
MG		 2798 break;
2799 case 0x61: /* popa */
2800 rc = emulate_popa(ctxt, ops);
1b30eaa8 2801 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2802 goto done;
2803 break;
6aa8b732 2804 case 0x63: /* movsxd */
8b4caf66 2805 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2806 goto cannot_emulate;
e4e03ded 2807 c->dst.val = (s32) c->src.val;
6aa8b732 2808 break;
018a98db
AK		 2809 case 0x6c: /* insb */
2810 case 0x6d: /* insw/insd */
7972995b 2811 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2812 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2813 c->dst.bytes)) {
54b8486f 2814 emulate_gp(ctxt, 0);
f850e2e6
GN		 2815 goto done;
2816 }
7b262e90
GN		 2817 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2818 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2819 goto done; /* IO is needed, skip writeback */
2820 break;
018a98db
AK		 2821 case 0x6e: /* outsb */
2822 case 0x6f: /* outsw/outsd */
7972995b 2823 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2824 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2825 c->src.bytes)) {
54b8486f 2826 emulate_gp(ctxt, 0);
f850e2e6
GN		 2827 goto done;
2828 }
7972995b
GN		 2829 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2830 &c->src.val, 1, ctxt->vcpu);
2831
2832 c->dst.type = OP_NONE; /* nothing to writeback */
2833 break;
b2833e3c 2834 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2835 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2836 jmp_rel(c, c->src.val);
018a98db 2837 break;
6aa8b732 2838 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2839 switch (c->modrm_reg) {
6aa8b732
AK		 2840 case 0:
2841 goto add;
2842 case 1:
2843 goto or;
2844 case 2:
2845 goto adc;
2846 case 3:
2847 goto sbb;
2848 case 4:
2849 goto and;
2850 case 5:
2851 goto sub;
2852 case 6:
2853 goto xor;
2854 case 7:
2855 goto cmp;
2856 }
2857 break;
2858 case 0x84 ... 0x85:
dfb507c4 2859 test:
05f086f8 2860 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2861 break;
2862 case 0x86 ... 0x87: /* xchg */
b13354f8 2863 xchg:
6aa8b732 2864 /* Write back the register source. */
e4e03ded 2865 switch (c->dst.bytes) {
6aa8b732 2866 case 1:
1a6440ae 2867 *(u8 *) c->src.addr.reg = (u8) c->dst.val;
6aa8b732
AK		 2868 break;
2869 case 2:
1a6440ae 2870 *(u16 *) c->src.addr.reg = (u16) c->dst.val;
6aa8b732
AK		 2871 break;
2872 case 4:
1a6440ae 2873 *c->src.addr.reg = (u32) c->dst.val;
6aa8b732
AK		 2874 break; /* 64b reg: zero-extend */
2875 case 8:
1a6440ae 2876 *c->src.addr.reg = c->dst.val;
6aa8b732
AK		 2877 break;
2878 }
2879 /*
2880 * Write back the memory destination with implicit LOCK
2881 * prefix.
2882 */
e4e03ded
LV		 2883 c->dst.val = c->src.val;
2884 c->lock_prefix = 1;
6aa8b732 2885 break;
6aa8b732 2886 case 0x88 ... 0x8b: /* mov */
7de75248 2887 goto mov;
79168fd1
GN		 2888 case 0x8c: /* mov r/m, sreg */
2889 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2890 emulate_ud(ctxt);
5e3ae6c5 2891 goto done;
38d5bc6d 2892 }
79168fd1 2893 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2894 break;
7e0b54b1 2895 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2896 c->dst.val = c->modrm_ea;
7e0b54b1 2897 break;
4257198a
GT		 2898 case 0x8e: { /* mov seg, r/m16 */
2899 uint16_t sel;
4257198a
GT		 2900
2901 sel = c->src.val;
8b9f4414 2902
c697518a
GN		 2903 if (c->modrm_reg == VCPU_SREG_CS ||
2904 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2905 emulate_ud(ctxt);
8b9f4414
GN		 2906 goto done;
2907 }
2908
310b5d30 2909 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2910 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2911
2e873022 2912 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2913
2914 c->dst.type = OP_NONE; /* Disable writeback. */
2915 break;
2916 }
6aa8b732 2917 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2918 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2919 if (rc != X86EMUL_CONTINUE)
6aa8b732 2920 goto done;
6aa8b732 2921 break;
3d9e77df
AK		 2922 case 0x90 ... 0x97: /* nop / xchg reg, rax */
2923 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
2924 goto done;
b13354f8 2925 goto xchg;
fd2a7608 2926 case 0x9c: /* pushf */
05f086f8 2927 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2928 emulate_push(ctxt, ops);
8cdbd2c9 2929 break;
535eabcf 2930 case 0x9d: /* popf */
2b48cc75 2931 c->dst.type = OP_REG;
1a6440ae 2932 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 2933 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2934 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2935 if (rc != X86EMUL_CONTINUE)
2936 goto done;
2937 break;
5d55f299 2938 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2939 case 0xa4 ... 0xa5: /* movs */
a682e354 2940 goto mov;
6aa8b732 2941 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2942 c->dst.type = OP_NONE; /* Disable writeback. */
1a6440ae 2943 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
a682e354 2944 goto cmp;
dfb507c4
MG		 2945 case 0xa8 ... 0xa9: /* test ax, imm */
2946 goto test;
6aa8b732 2947 case 0xaa ... 0xab: /* stos */
e4e03ded 2948 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2949 break;
2950 case 0xac ... 0xad: /* lods */
a682e354 2951 goto mov;
6aa8b732
AK		 2952 case 0xae ... 0xaf: /* scas */
2953 DPRINTF("Urk! I don't handle SCAS.\n");
2954 goto cannot_emulate;
a5e2e82b 2955 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2956 goto mov;
018a98db
AK		 2957 case 0xc0 ... 0xc1:
2958 emulate_grp2(ctxt);
2959 break;
111de5d6 2960 case 0xc3: /* ret */
cf5de4f8 2961 c->dst.type = OP_REG;
1a6440ae 2962 c->dst.addr.reg = &c->eip;
cf5de4f8 2963 c->dst.bytes = c->op_bytes;
111de5d6 2964 goto pop_instruction;
018a98db
AK		 2965 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2966 mov:
2967 c->dst.val = c->src.val;
2968 break;
a77ab5ea
AK		 2969 case 0xcb: /* ret far */
2970 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2971 if (rc != X86EMUL_CONTINUE)
2972 goto done;
2973 break;
2974 case 0xcf: /* iret */
2975 rc = emulate_iret(ctxt, ops);
2976
1b30eaa8 2977 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2978 goto done;
2979 break;
018a98db
AK		 2980 case 0xd0 ... 0xd1: /* Grp2 */
2981 c->src.val = 1;
2982 emulate_grp2(ctxt);
2983 break;
2984 case 0xd2 ... 0xd3: /* Grp2 */
2985 c->src.val = c->regs[VCPU_REGS_RCX];
2986 emulate_grp2(ctxt);
2987 break;
a6a3034c
MG		 2988 case 0xe4: /* inb */
2989 case 0xe5: /* in */
cf8f70bf 2990 goto do_io_in;
a6a3034c
MG		 2991 case 0xe6: /* outb */
2992 case 0xe7: /* out */
cf8f70bf 2993 goto do_io_out;
1a52e051 2994 case 0xe8: /* call (near) */ {
d53c4777 2995 long int rel = c->src.val;
e4e03ded 2996 c->src.val = (unsigned long) c->eip;
7a957275 2997 jmp_rel(c, rel);
79168fd1 2998 emulate_push(ctxt, ops);
8cdbd2c9 2999 break;
1a52e051
NK		 3000 }
3001 case 0xe9: /* jmp rel */
954cd36f 3002 goto jmp;
414e6277
GN		 3003 case 0xea: { /* jmp far */
3004 unsigned short sel;
ea79849d 3005 jump_far:
414e6277
GN		 3006 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3007
3008 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3009 goto done;
954cd36f 3010
414e6277
GN		 3011 c->eip = 0;
3012 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3013 break;
414e6277 3014 }
954cd36f
GT		 3015 case 0xeb:
3016 jmp: /* jmp rel short */
7a957275 3017 jmp_rel(c, c->src.val);
a01af5ec 3018 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3019 break;
a6a3034c
MG		 3020 case 0xec: /* in al,dx */
3021 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3022 c->src.val = c->regs[VCPU_REGS_RDX];
3023 do_io_in:
3024 c->dst.bytes = min(c->dst.bytes, 4u);
3025 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3026 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3027 goto done;
3028 }
7b262e90
GN		 3029 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3030 &c->dst.val))
cf8f70bf
GN		 3031 goto done; /* IO is needed */
3032 break;
ce7a0ad3
WY		 3033 case 0xee: /* out dx,al */
3034 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3035 c->src.val = c->regs[VCPU_REGS_RDX];
3036 do_io_out:
3037 c->dst.bytes = min(c->dst.bytes, 4u);
3038 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3039 emulate_gp(ctxt, 0);
f850e2e6
GN		 3040 goto done;
3041 }
cf8f70bf
GN		 3042 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3043 ctxt->vcpu);
3044 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3045 break;
111de5d6 3046 case 0xf4: /* hlt */
ad312c7c 3047 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3048 break;
111de5d6
AK		 3049 case 0xf5: /* cmc */
3050 /* complement carry flag from eflags reg */
3051 ctxt->eflags ^= EFLG_CF;
3052 c->dst.type = OP_NONE; /* Disable writeback. */
3053 break;
018a98db 3054 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3055 if (!emulate_grp3(ctxt, ops))
3056 goto cannot_emulate;
018a98db 3057 break;
111de5d6
AK		 3058 case 0xf8: /* clc */
3059 ctxt->eflags &= ~EFLG_CF;
3060 c->dst.type = OP_NONE; /* Disable writeback. */
3061 break;
3062 case 0xfa: /* cli */
07cbc6c1 3063 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3064 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3065 goto done;
3066 } else {
f850e2e6
GN		 3067 ctxt->eflags &= ~X86_EFLAGS_IF;
3068 c->dst.type = OP_NONE; /* Disable writeback. */
3069 }
111de5d6
AK		 3070 break;
3071 case 0xfb: /* sti */
07cbc6c1 3072 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3073 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3074 goto done;
3075 } else {
95cb2295 3076 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3077 ctxt->eflags |= X86_EFLAGS_IF;
3078 c->dst.type = OP_NONE; /* Disable writeback. */
3079 }
111de5d6 3080 break;
fb4616f4
MG		 3081 case 0xfc: /* cld */
3082 ctxt->eflags &= ~EFLG_DF;
3083 c->dst.type = OP_NONE; /* Disable writeback. */
3084 break;
3085 case 0xfd: /* std */
3086 ctxt->eflags |= EFLG_DF;
3087 c->dst.type = OP_NONE; /* Disable writeback. */
3088 break;
ea79849d
GN		 3089 case 0xfe: /* Grp4 */
3090 grp45:
018a98db 3091 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3092 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3093 goto done;
3094 break;
ea79849d
GN		 3095 case 0xff: /* Grp5 */
3096 if (c->modrm_reg == 5)
3097 goto jump_far;
3098 goto grp45;
91269b8f
AK		 3099 default:
3100 goto cannot_emulate;
6aa8b732 3101 }
018a98db
AK		 3102
3103writeback:
3104 rc = writeback(ctxt, ops);
1b30eaa8 3105 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3106 goto done;
3107
5cd21917
GN		 3108 /*
3109 * restore dst type in case the decoding will be reused
3110 * (happens for string instruction )
3111 */
3112 c->dst.type = saved_dst_type;
3113
a682e354 3114 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3115 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3116 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3117
3118 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3119 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3120 &c->dst);
d9271123 3121
5cd21917 3122 if (c->rep_prefix && (c->d & String)) {
7b262e90 3123 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3124 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3125 /*
3126 * Re-enter guest when pio read ahead buffer is empty or,
3127 * if it is not used, after each 1024 iteration.
3128 */
3129 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3130 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3131 ctxt->restart = false;
3132 }
9de41573
GN		 3133 /*
3134 * reset read cache here in case string instruction is restared
3135 * without decoding
3136 */
3137 ctxt->decode.mem_read.end = 0;
95c55886 3138 ctxt->eip = c->eip;
018a98db
AK		 3139
3140done:
cb404fe0 3141 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3142
3143twobyte_insn:
e4e03ded 3144 switch (c->b) {
6aa8b732 3145 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3146 switch (c->modrm_reg) {
6aa8b732
AK		 3147 u16 size;
3148 unsigned long address;
3149
aca7f966 3150 case 0: /* vmcall */
e4e03ded 3151 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3152 goto cannot_emulate;
3153
7aa81cc0 3154 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3155 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3156 goto done;
3157
33e3885d 3158 /* Let the processor re-execute the fixed hypercall */
063db061 3159 c->eip = ctxt->eip;
16286d08
AK		 3160 /* Disable writeback. */
3161 c->dst.type = OP_NONE;
aca7f966 3162 break;
6aa8b732 3163 case 2: /* lgdt */
1a6440ae 3164 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3165 &size, &address, c->op_bytes);
1b30eaa8 3166 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3167 goto done;
3168 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3169 /* Disable writeback. */
3170 c->dst.type = OP_NONE;
6aa8b732 3171 break;
aca7f966 3172 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3173 if (c->modrm_mod == 3) {
3174 switch (c->modrm_rm) {
3175 case 1:
3176 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3177 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3178 goto done;
3179 break;
3180 default:
3181 goto cannot_emulate;
3182 }
aca7f966 3183 } else {
1a6440ae 3184 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3185 &size, &address,
e4e03ded 3186 c->op_bytes);
1b30eaa8 3187 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3188 goto done;
3189 realmode_lidt(ctxt->vcpu, size, address);
3190 }
16286d08
AK		 3191 /* Disable writeback. */
3192 c->dst.type = OP_NONE;
6aa8b732
AK		 3193 break;
3194 case 4: /* smsw */
16286d08 3195 c->dst.bytes = 2;
52a46617 3196 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3197 break;
3198 case 6: /* lmsw */
9928ff60 3199 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3200 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3201 c->dst.type = OP_NONE;
6aa8b732 3202 break;
6e1e5ffe 3203 case 5: /* not defined */
54b8486f 3204 emulate_ud(ctxt);
6e1e5ffe 3205 goto done;
6aa8b732 3206 case 7: /* invlpg*/
69f55cb1 3207 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3208 /* Disable writeback. */
3209 c->dst.type = OP_NONE;
6aa8b732
AK		 3210 break;
3211 default:
3212 goto cannot_emulate;
3213 }
3214 break;
e99f0507 3215 case 0x05: /* syscall */
3fb1b5db 3216 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3217 if (rc != X86EMUL_CONTINUE)
3218 goto done;
e66bb2cc
AP		 3219 else
3220 goto writeback;
e99f0507 3221 break;
018a98db
AK		 3222 case 0x06:
3223 emulate_clts(ctxt->vcpu);
3224 c->dst.type = OP_NONE;
3225 break;
018a98db 3226 case 0x09: /* wbinvd */
f5f48ee1
SY		 3227 kvm_emulate_wbinvd(ctxt->vcpu);
3228 c->dst.type = OP_NONE;
3229 break;
3230 case 0x08: /* invd */
018a98db
AK		 3231 case 0x0d: /* GrpP (prefetch) */
3232 case 0x18: /* Grp16 (prefetch/nop) */
3233 c->dst.type = OP_NONE;
3234 break;
3235 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3236 switch (c->modrm_reg) {
3237 case 1:
3238 case 5 ... 7:
3239 case 9 ... 15:
54b8486f 3240 emulate_ud(ctxt);
6aebfa6e
GN		 3241 goto done;
3242 }
1a0c7d44 3243 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3244 break;
6aa8b732 3245 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3246 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3247 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3248 emulate_ud(ctxt);
1e470be5
GN		 3249 goto done;
3250 }
b27f3856 3251 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3252 break;
018a98db 3253 case 0x22: /* mov reg, cr */
1a0c7d44 3254 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3255 emulate_gp(ctxt, 0);
0f12244f
GN		 3256 goto done;
3257 }
018a98db
AK		 3258 c->dst.type = OP_NONE;
3259 break;
6aa8b732 3260 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3261 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3262 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3263 emulate_ud(ctxt);
1e470be5
GN		 3264 goto done;
3265 }
35aa5375 3266
b27f3856 3267 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3268 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3269 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3270 /* #UD condition is already handled by the code above */
54b8486f 3271 emulate_gp(ctxt, 0);
338dbc97
GN		 3272 goto done;
3273 }
3274
a01af5ec 3275 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3276 break;
018a98db
AK		 3277 case 0x30:
3278 /* wrmsr */
3279 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3280 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3281 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3282 emulate_gp(ctxt, 0);
fd525365 3283 goto done;
018a98db
AK		 3284 }
3285 rc = X86EMUL_CONTINUE;
3286 c->dst.type = OP_NONE;
3287 break;
3288 case 0x32:
3289 /* rdmsr */
3fb1b5db 3290 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3291 emulate_gp(ctxt, 0);
fd525365 3292 goto done;
018a98db
AK		 3293 } else {
3294 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3295 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3296 }
3297 rc = X86EMUL_CONTINUE;
3298 c->dst.type = OP_NONE;
3299 break;
e99f0507 3300 case 0x34: /* sysenter */
3fb1b5db 3301 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3302 if (rc != X86EMUL_CONTINUE)
3303 goto done;
8c604352
AP		 3304 else
3305 goto writeback;
e99f0507
AP		 3306 break;
3307 case 0x35: /* sysexit */
3fb1b5db 3308 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3309 if (rc != X86EMUL_CONTINUE)
3310 goto done;
4668f050
AP		 3311 else
3312 goto writeback;
e99f0507 3313 break;
6aa8b732 3314 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3315 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3316 if (!test_cc(c->b, ctxt->eflags))
3317 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3318 break;
b2833e3c 3319 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3320 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3321 jmp_rel(c, c->src.val);
018a98db
AK		 3322 c->dst.type = OP_NONE;
3323 break;
0934ac9d 3324 case 0xa0: /* push fs */
79168fd1 3325 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3326 break;
3327 case 0xa1: /* pop fs */
3328 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3329 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3330 goto done;
3331 break;
7de75248
NK		 3332 case 0xa3:
3333 bt: /* bt */
e4f8e039 3334 c->dst.type = OP_NONE;
e4e03ded
LV		 3335 /* only subword offset */
3336 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3337 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3338 break;
9bf8ea42
GT		 3339 case 0xa4: /* shld imm8, r, r/m */
3340 case 0xa5: /* shld cl, r, r/m */
3341 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3342 break;
0934ac9d 3343 case 0xa8: /* push gs */
79168fd1 3344 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3345 break;
3346 case 0xa9: /* pop gs */
3347 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3348 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3349 goto done;
3350 break;
7de75248
NK		 3351 case 0xab:
3352 bts: /* bts */
e4e03ded
LV		 3353 /* only subword offset */
3354 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3355 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3356 break;
9bf8ea42
GT		 3357 case 0xac: /* shrd imm8, r, r/m */
3358 case 0xad: /* shrd cl, r, r/m */
3359 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3360 break;
2a7c5b8b
GC		 3361 case 0xae: /* clflush */
3362 break;
6aa8b732
AK		 3363 case 0xb0 ... 0xb1: /* cmpxchg */
3364 /*
3365 * Save real source value, then compare EAX against
3366 * destination.
3367 */
e4e03ded
LV		 3368 c->src.orig_val = c->src.val;
3369 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3370 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3371 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3372 /* Success: write back to memory. */
e4e03ded 3373 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3374 } else {
3375 /* Failure: write the value we saw to EAX. */
e4e03ded 3376 c->dst.type = OP_REG;
1a6440ae 3377 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3378 }
3379 break;
6aa8b732
AK		 3380 case 0xb3:
3381 btr: /* btr */
e4e03ded
LV		 3382 /* only subword offset */
3383 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3384 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3385 break;
6aa8b732 3386 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3387 c->dst.bytes = c->op_bytes;
3388 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3389 : (u16) c->src.val;
6aa8b732 3390 break;
6aa8b732 3391 case 0xba: /* Grp8 */
e4e03ded 3392 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3393 case 0:
3394 goto bt;
3395 case 1:
3396 goto bts;
3397 case 2:
3398 goto btr;
3399 case 3:
3400 goto btc;
3401 }
3402 break;
7de75248
NK		 3403 case 0xbb:
3404 btc: /* btc */
e4e03ded
LV		 3405 /* only subword offset */
3406 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3407 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3408 break;
6aa8b732 3409 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3410 c->dst.bytes = c->op_bytes;
3411 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3412 (s16) c->src.val;
6aa8b732 3413 break;
a012e65a 3414 case 0xc3: /* movnti */
e4e03ded
LV		 3415 c->dst.bytes = c->op_bytes;
3416 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3417 (u64) c->src.val;
a012e65a 3418 break;
6aa8b732 3419 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3420 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3421 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3422 goto done;
3423 break;
91269b8f
AK		 3424 default:
3425 goto cannot_emulate;
6aa8b732
AK		 3426 }
3427 goto writeback;
3428
3429cannot_emulate:
e4e03ded 3430 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3431 return -1;
3432}
Linux kernel - Deliverables
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