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KVM: x86 emulator: pass destination type to ____emulate_2op()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 57#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 58#define DstMask (7<<1)
6aa8b732 59/* Source operand type. */
9c9fddd0
GT		 60#define SrcNone (0<<4) /* No source operand. */
61#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
62#define SrcReg (1<<4) /* Register operand. */
63#define SrcMem (2<<4) /* Memory operand. */
64#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
65#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
66#define SrcImm (5<<4) /* Immediate operand. */
67#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 68#define SrcOne (7<<4) /* Implied '1' */
341de7e3 69#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 70#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 71#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 72#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
73#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 74#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 75#define SrcMask (0xf<<4)
6aa8b732 76/* Generic ModRM decode. */
341de7e3 77#define ModRM (1<<8)
6aa8b732 78/* Destination is only written; never read. */
341de7e3
GN		 79#define Mov (1<<9)
80#define BitOp (1<<10)
81#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 82#define String (1<<12) /* String instruction (rep capable) */
83#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 84#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 86/* Misc flags */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
98#define Src2Mask (7<<29)
6aa8b732 99
d0e53325
AK		 100#define X2(x...) x, x
101#define X3(x...) X2(x), x
102#define X4(x...) X2(x), X2(x)
103#define X5(x...) X4(x), x
104#define X6(x...) X4(x), X2(x)
105#define X7(x...) X4(x), X3(x)
106#define X8(x...) X4(x), X4(x)
107#define X16(x...) X8(x), X8(x)
83babbca 108
d65b1dee
AK		 109struct opcode {
110 u32 flags;
120df890 111 union {
ef65c889 112 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 113 struct opcode *group;
114 struct group_dual *gdual;
115 } u;
116};
117
118struct group_dual {
119 struct opcode mod012[8];
120 struct opcode mod3[8];
d65b1dee
AK		 121};
122
6aa8b732 123/* EFLAGS bit definitions. */
d4c6a154
GN		 124#define EFLG_ID (1<<21)
125#define EFLG_VIP (1<<20)
126#define EFLG_VIF (1<<19)
127#define EFLG_AC (1<<18)
b1d86143
AP		 128#define EFLG_VM (1<<17)
129#define EFLG_RF (1<<16)
d4c6a154
GN		 130#define EFLG_IOPL (3<<12)
131#define EFLG_NT (1<<14)
6aa8b732
AK		 132#define EFLG_OF (1<<11)
133#define EFLG_DF (1<<10)
b1d86143 134#define EFLG_IF (1<<9)
d4c6a154 135#define EFLG_TF (1<<8)
6aa8b732
AK		 136#define EFLG_SF (1<<7)
137#define EFLG_ZF (1<<6)
138#define EFLG_AF (1<<4)
139#define EFLG_PF (1<<2)
140#define EFLG_CF (1<<0)
141
62bd430e
MG		 142#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
143#define EFLG_RESERVED_ONE_MASK 2
144
6aa8b732
AK		 145/*
146 * Instruction emulation:
147 * Most instructions are emulated directly via a fragment of inline assembly
148 * code. This allows us to save/restore EFLAGS and thus very easily pick up
149 * any modified flags.
150 */
151
05b3e0c2 152#if defined(CONFIG_X86_64)
6aa8b732
AK		 153#define _LO32 "k" /* force 32-bit operand */
154#define _STK "%%rsp" /* stack pointer */
155#elif defined(__i386__)
156#define _LO32 "" /* force 32-bit operand */
157#define _STK "%%esp" /* stack pointer */
158#endif
159
160/*
161 * These EFLAGS bits are restored from saved value during emulation, and
162 * any changes are written back to the saved value after emulation.
163 */
164#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
165
166/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 167#define _PRE_EFLAGS(_sav, _msk, _tmp) \
168 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
169 "movl %"_sav",%"_LO32 _tmp"; " \
170 "push %"_tmp"; " \
171 "push %"_tmp"; " \
172 "movl %"_msk",%"_LO32 _tmp"; " \
173 "andl %"_LO32 _tmp",("_STK"); " \
174 "pushf; " \
175 "notl %"_LO32 _tmp"; " \
176 "andl %"_LO32 _tmp",("_STK"); " \
177 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
178 "pop %"_tmp"; " \
179 "orl %"_LO32 _tmp",("_STK"); " \
180 "popf; " \
181 "pop %"_sav"; "
6aa8b732
AK		 182
183/* After executing instruction: write-back necessary bits in EFLAGS. */
184#define _POST_EFLAGS(_sav, _msk, _tmp) \
185 /* _sav |= EFLAGS & _msk; */ \
186 "pushf; " \
187 "pop %"_tmp"; " \
188 "andl %"_msk",%"_LO32 _tmp"; " \
189 "orl %"_LO32 _tmp",%"_sav"; "
190
dda96d8f
AK		 191#ifdef CONFIG_X86_64
192#define ON64(x) x
193#else
194#define ON64(x)
195#endif
196
b3b3d25a 197#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 198 do { \
199 __asm__ __volatile__ ( \
200 _PRE_EFLAGS("0", "4", "2") \
201 _op _suffix " %"_x"3,%1; " \
202 _POST_EFLAGS("0", "4", "2") \
b3b3d25a 203 : "=m" (_eflags), "=m" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 204 "=&r" (_tmp) \
205 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 206 } while (0)
6b7ad61f
AK		 207
208
6aa8b732
AK		 209/* Raw emulation: instruction has two explicit operands. */
210#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 211 do { \
212 unsigned long _tmp; \
213 \
214 switch ((_dst).bytes) { \
215 case 2: \
b3b3d25a 216 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 217 break; \
218 case 4: \
b3b3d25a 219 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 220 break; \
221 case 8: \
b3b3d25a 222 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 223 break; \
224 } \
6aa8b732
AK		 225 } while (0)
226
227#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
228 do { \
6b7ad61f 229 unsigned long _tmp; \
d77c26fc 230 switch ((_dst).bytes) { \
6aa8b732 231 case 1: \
b3b3d25a 232 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 233 break; \
234 default: \
235 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
236 _wx, _wy, _lx, _ly, _qx, _qy); \
237 break; \
238 } \
239 } while (0)
240
241/* Source operand is byte-sized and may be restricted to just %cl. */
242#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
243 __emulate_2op(_op, _src, _dst, _eflags, \
244 "b", "c", "b", "c", "b", "c", "b", "c")
245
246/* Source operand is byte, word, long or quad sized. */
247#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
248 __emulate_2op(_op, _src, _dst, _eflags, \
249 "b", "q", "w", "r", _LO32, "r", "", "r")
250
251/* Source operand is word, long or quad sized. */
252#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
253 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
254 "w", "r", _LO32, "r", "", "r")
255
d175226a
GT		 256/* Instruction has three operands and one operand is stored in ECX register */
257#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
258 do { \
259 unsigned long _tmp; \
260 _type _clv = (_cl).val; \
261 _type _srcv = (_src).val; \
262 _type _dstv = (_dst).val; \
263 \
264 __asm__ __volatile__ ( \
265 _PRE_EFLAGS("0", "5", "2") \
266 _op _suffix " %4,%1 \n" \
267 _POST_EFLAGS("0", "5", "2") \
268 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
269 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
270 ); \
271 \
272 (_cl).val = (unsigned long) _clv; \
273 (_src).val = (unsigned long) _srcv; \
274 (_dst).val = (unsigned long) _dstv; \
275 } while (0)
276
277#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
278 do { \
279 switch ((_dst).bytes) { \
280 case 2: \
281 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
282 "w", unsigned short); \
283 break; \
284 case 4: \
285 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
286 "l", unsigned int); \
287 break; \
288 case 8: \
289 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "q", unsigned long)); \
291 break; \
292 } \
293 } while (0)
294
dda96d8f 295#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 296 do { \
297 unsigned long _tmp; \
298 \
dda96d8f
AK		 299 __asm__ __volatile__ ( \
300 _PRE_EFLAGS("0", "3", "2") \
301 _op _suffix " %1; " \
302 _POST_EFLAGS("0", "3", "2") \
303 : "=m" (_eflags), "+m" ((_dst).val), \
304 "=&r" (_tmp) \
305 : "i" (EFLAGS_MASK)); \
306 } while (0)
307
308/* Instruction has only one explicit operand (no source operand). */
309#define emulate_1op(_op, _dst, _eflags) \
310 do { \
d77c26fc 311 switch ((_dst).bytes) { \
dda96d8f
AK		 312 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
313 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
314 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
315 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 316 } \
317 } while (0)
318
3f9f53b0
MG		 319#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
320 do { \
321 unsigned long _tmp; \
322 \
323 __asm__ __volatile__ ( \
324 _PRE_EFLAGS("0", "4", "1") \
325 _op _suffix " %5; " \
326 _POST_EFLAGS("0", "4", "1") \
327 : "=m" (_eflags), "=&r" (_tmp), \
328 "+a" (_rax), "+d" (_rdx) \
329 : "i" (EFLAGS_MASK), "m" ((_src).val), \
330 "a" (_rax), "d" (_rdx)); \
331 } while (0)
332
333/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
334#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
335 do { \
336 switch((_src).bytes) { \
337 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
338 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
339 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
340 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
341 } \
342 } while (0)
343
6aa8b732
AK		 344/* Fetch next part of the instruction being emulated. */
345#define insn_fetch(_type, _size, _eip) \
346({ unsigned long _x; \
62266869 347 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 348 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 349 goto done; \
350 (_eip) += (_size); \
351 (_type)_x; \
352})
353
414e6277
GN		 354#define insn_fetch_arr(_arr, _size, _eip) \
355({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
356 if (rc != X86EMUL_CONTINUE) \
357 goto done; \
358 (_eip) += (_size); \
359})
360
ddcb2885
HH		 361static inline unsigned long ad_mask(struct decode_cache *c)
362{
363 return (1UL << (c->ad_bytes << 3)) - 1;
364}
365
6aa8b732 366/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 367static inline unsigned long
368address_mask(struct decode_cache *c, unsigned long reg)
369{
370 if (c->ad_bytes == sizeof(unsigned long))
371 return reg;
372 else
373 return reg & ad_mask(c);
374}
375
376static inline unsigned long
377register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
378{
379 return base + address_mask(c, reg);
380}
381
7a957275
HH		 382static inline void
383register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
384{
385 if (c->ad_bytes == sizeof(unsigned long))
386 *reg += inc;
387 else
388 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
389}
6aa8b732 390
7a957275
HH		 391static inline void jmp_rel(struct decode_cache *c, int rel)
392{
393 register_address_increment(c, &c->eip, rel);
394}
098c937b 395
7a5b56df
AK		 396static void set_seg_override(struct decode_cache *c, int seg)
397{
398 c->has_seg_override = true;
399 c->seg_override = seg;
400}
401
79168fd1
GN		 402static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
403 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 404{
405 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
406 return 0;
407
79168fd1 408 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 409}
410
411static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 412 struct x86_emulate_ops *ops,
7a5b56df
AK		 413 struct decode_cache *c)
414{
415 if (!c->has_seg_override)
416 return 0;
417
79168fd1 418 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 419}
420
79168fd1
GN		 421static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
422 struct x86_emulate_ops *ops)
7a5b56df 423{
79168fd1 424 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 425}
426
79168fd1
GN		 427static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
428 struct x86_emulate_ops *ops)
7a5b56df 429{
79168fd1 430 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 431}
432
54b8486f
GN		 433static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
434 u32 error, bool valid)
435{
436 ctxt->exception = vec;
437 ctxt->error_code = error;
438 ctxt->error_code_valid = valid;
439 ctxt->restart = false;
440}
441
442static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
443{
444 emulate_exception(ctxt, GP_VECTOR, err, true);
445}
446
447static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
448 int err)
449{
450 ctxt->cr2 = addr;
451 emulate_exception(ctxt, PF_VECTOR, err, true);
452}
453
454static void emulate_ud(struct x86_emulate_ctxt *ctxt)
455{
456 emulate_exception(ctxt, UD_VECTOR, 0, false);
457}
458
459static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
460{
461 emulate_exception(ctxt, TS_VECTOR, err, true);
462}
463
62266869
AK		 464static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
465 struct x86_emulate_ops *ops,
2fb53ad8 466 unsigned long eip, u8 *dest)
62266869
AK		 467{
468 struct fetch_cache *fc = &ctxt->decode.fetch;
469 int rc;
2fb53ad8 470 int size, cur_size;
62266869 471
2fb53ad8
AK		 472 if (eip == fc->end) {
473 cur_size = fc->end - fc->start;
474 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
475 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
476 size, ctxt->vcpu, NULL);
3e2815e9 477 if (rc != X86EMUL_CONTINUE)
62266869 478 return rc;
2fb53ad8 479 fc->end += size;
62266869 480 }
2fb53ad8 481 *dest = fc->data[eip - fc->start];
3e2815e9 482 return X86EMUL_CONTINUE;
62266869
AK		 483}
484
485static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
486 struct x86_emulate_ops *ops,
487 unsigned long eip, void *dest, unsigned size)
488{
3e2815e9 489 int rc;
62266869 490
eb3c79e6 491 /* x86 instructions are limited to 15 bytes. */
063db061 492 if (eip + size - ctxt->eip > 15)
eb3c79e6 493 return X86EMUL_UNHANDLEABLE;
62266869
AK		 494 while (size--) {
495 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 496 if (rc != X86EMUL_CONTINUE)
62266869
AK		 497 return rc;
498 }
3e2815e9 499 return X86EMUL_CONTINUE;
62266869
AK		 500}
501
1e3c5cb0
RR		 502/*
503 * Given the 'reg' portion of a ModRM byte, and a register block, return a
504 * pointer into the block that addresses the relevant register.
505 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
506 */
507static void *decode_register(u8 modrm_reg, unsigned long *regs,
508 int highbyte_regs)
6aa8b732
AK		 509{
510 void *p;
511
512 p = &regs[modrm_reg];
513 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
514 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
515 return p;
516}
517
518static int read_descriptor(struct x86_emulate_ctxt *ctxt,
519 struct x86_emulate_ops *ops,
1a6440ae 520 ulong addr,
6aa8b732
AK		 521 u16 *size, unsigned long *address, int op_bytes)
522{
523 int rc;
524
525 if (op_bytes == 2)
526 op_bytes = 3;
527 *address = 0;
1a6440ae 528 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 529 if (rc != X86EMUL_CONTINUE)
6aa8b732 530 return rc;
1a6440ae 531 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 532 return rc;
533}
534
bbe9abbd
NK		 535static int test_cc(unsigned int condition, unsigned int flags)
536{
537 int rc = 0;
538
539 switch ((condition & 15) >> 1) {
540 case 0: /* o */
541 rc |= (flags & EFLG_OF);
542 break;
543 case 1: /* b/c/nae */
544 rc |= (flags & EFLG_CF);
545 break;
546 case 2: /* z/e */
547 rc |= (flags & EFLG_ZF);
548 break;
549 case 3: /* be/na */
550 rc |= (flags & (EFLG_CF|EFLG_ZF));
551 break;
552 case 4: /* s */
553 rc |= (flags & EFLG_SF);
554 break;
555 case 5: /* p/pe */
556 rc |= (flags & EFLG_PF);
557 break;
558 case 7: /* le/ng */
559 rc |= (flags & EFLG_ZF);
560 /* fall through */
561 case 6: /* l/nge */
562 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
563 break;
564 }
565
566 /* Odd condition identifiers (lsb == 1) have inverted sense. */
567 return (!!rc ^ (condition & 1));
568}
569
91ff3cb4
AK		 570static void fetch_register_operand(struct operand *op)
571{
572 switch (op->bytes) {
573 case 1:
574 op->val = *(u8 *)op->addr.reg;
575 break;
576 case 2:
577 op->val = *(u16 *)op->addr.reg;
578 break;
579 case 4:
580 op->val = *(u32 *)op->addr.reg;
581 break;
582 case 8:
583 op->val = *(u64 *)op->addr.reg;
584 break;
585 }
586}
587
3c118e24
AK		 588static void decode_register_operand(struct operand *op,
589 struct decode_cache *c,
3c118e24
AK		 590 int inhibit_bytereg)
591{
33615aa9 592 unsigned reg = c->modrm_reg;
9f1ef3f8 593 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 594
595 if (!(c->d & ModRM))
596 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 597 op->type = OP_REG;
598 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 599 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 600 op->bytes = 1;
601 } else {
1a6440ae 602 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 603 op->bytes = c->op_bytes;
3c118e24 604 }
91ff3cb4 605 fetch_register_operand(op);
3c118e24
AK		 606 op->orig_val = op->val;
607}
608
1c73ef66 609static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 610 struct x86_emulate_ops *ops,
611 struct operand *op)
1c73ef66
AK		 612{
613 struct decode_cache *c = &ctxt->decode;
614 u8 sib;
f5b4edcd 615 int index_reg = 0, base_reg = 0, scale;
3e2815e9 616 int rc = X86EMUL_CONTINUE;
2dbd0dd7 617 ulong modrm_ea = 0;
1c73ef66
AK		 618
619 if (c->rex_prefix) {
620 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
621 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
622 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
623 }
624
625 c->modrm = insn_fetch(u8, 1, c->eip);
626 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
627 c->modrm_reg |= (c->modrm & 0x38) >> 3;
628 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 629 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 630
631 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 632 op->type = OP_REG;
633 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
634 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 635 c->regs, c->d & ByteOp);
2dbd0dd7 636 fetch_register_operand(op);
1c73ef66
AK		 637 return rc;
638 }
639
2dbd0dd7
AK		 640 op->type = OP_MEM;
641
1c73ef66
AK		 642 if (c->ad_bytes == 2) {
643 unsigned bx = c->regs[VCPU_REGS_RBX];
644 unsigned bp = c->regs[VCPU_REGS_RBP];
645 unsigned si = c->regs[VCPU_REGS_RSI];
646 unsigned di = c->regs[VCPU_REGS_RDI];
647
648 /* 16-bit ModR/M decode. */
649 switch (c->modrm_mod) {
650 case 0:
651 if (c->modrm_rm == 6)
2dbd0dd7 652 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 653 break;
654 case 1:
2dbd0dd7 655 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 656 break;
657 case 2:
2dbd0dd7 658 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 659 break;
660 }
661 switch (c->modrm_rm) {
662 case 0:
2dbd0dd7 663 modrm_ea += bx + si;
1c73ef66
AK		 664 break;
665 case 1:
2dbd0dd7 666 modrm_ea += bx + di;
1c73ef66
AK		 667 break;
668 case 2:
2dbd0dd7 669 modrm_ea += bp + si;
1c73ef66
AK		 670 break;
671 case 3:
2dbd0dd7 672 modrm_ea += bp + di;
1c73ef66
AK		 673 break;
674 case 4:
2dbd0dd7 675 modrm_ea += si;
1c73ef66
AK		 676 break;
677 case 5:
2dbd0dd7 678 modrm_ea += di;
1c73ef66
AK		 679 break;
680 case 6:
681 if (c->modrm_mod != 0)
2dbd0dd7 682 modrm_ea += bp;
1c73ef66
AK		 683 break;
684 case 7:
2dbd0dd7 685 modrm_ea += bx;
1c73ef66
AK		 686 break;
687 }
688 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
689 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 690 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 691 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 692 } else {
693 /* 32/64-bit ModR/M decode. */
84411d85 694 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 695 sib = insn_fetch(u8, 1, c->eip);
696 index_reg |= (sib >> 3) & 7;
697 base_reg |= sib & 7;
698 scale = sib >> 6;
699
dc71d0f1 700 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 701 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 702 else
2dbd0dd7 703 modrm_ea += c->regs[base_reg];
dc71d0f1 704 if (index_reg != 4)
2dbd0dd7 705 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 706 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
707 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 708 c->rip_relative = 1;
84411d85 709 } else
2dbd0dd7 710 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 711 switch (c->modrm_mod) {
712 case 0:
713 if (c->modrm_rm == 5)
2dbd0dd7 714 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 715 break;
716 case 1:
2dbd0dd7 717 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 718 break;
719 case 2:
2dbd0dd7 720 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 721 break;
722 }
723 }
2dbd0dd7 724 op->addr.mem = modrm_ea;
1c73ef66
AK		 725done:
726 return rc;
727}
728
729static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 730 struct x86_emulate_ops *ops,
731 struct operand *op)
1c73ef66
AK		 732{
733 struct decode_cache *c = &ctxt->decode;
3e2815e9 734 int rc = X86EMUL_CONTINUE;
1c73ef66 735
2dbd0dd7 736 op->type = OP_MEM;
1c73ef66
AK		 737 switch (c->ad_bytes) {
738 case 2:
2dbd0dd7 739 op->addr.mem = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 740 break;
741 case 4:
2dbd0dd7 742 op->addr.mem = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 743 break;
744 case 8:
2dbd0dd7 745 op->addr.mem = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 746 break;
747 }
748done:
749 return rc;
750}
751
35c843c4
WY		 752static void fetch_bit_operand(struct decode_cache *c)
753{
754 long sv, mask;
755
3885f18f 756 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 757 mask = ~(c->dst.bytes * 8 - 1);
758
759 if (c->src.bytes == 2)
760 sv = (s16)c->src.val & (s16)mask;
761 else if (c->src.bytes == 4)
762 sv = (s32)c->src.val & (s32)mask;
763
764 c->dst.addr.mem += (sv >> 3);
765 }
ba7ff2b7
WY		 766
767 /* only subword offset */
768 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 769}
770
dde7e6d1
AK		 771static int read_emulated(struct x86_emulate_ctxt *ctxt,
772 struct x86_emulate_ops *ops,
773 unsigned long addr, void *dest, unsigned size)
6aa8b732 774{
dde7e6d1
AK		 775 int rc;
776 struct read_cache *mc = &ctxt->decode.mem_read;
777 u32 err;
6aa8b732 778
dde7e6d1
AK		 779 while (size) {
780 int n = min(size, 8u);
781 size -= n;
782 if (mc->pos < mc->end)
783 goto read_cached;
5cd21917 784
dde7e6d1
AK		 785 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
786 ctxt->vcpu);
787 if (rc == X86EMUL_PROPAGATE_FAULT)
788 emulate_pf(ctxt, addr, err);
789 if (rc != X86EMUL_CONTINUE)
790 return rc;
791 mc->end += n;
6aa8b732 792
dde7e6d1
AK		 793 read_cached:
794 memcpy(dest, mc->data + mc->pos, n);
795 mc->pos += n;
796 dest += n;
797 addr += n;
6aa8b732 798 }
dde7e6d1
AK		 799 return X86EMUL_CONTINUE;
800}
6aa8b732 801
dde7e6d1
AK		 802static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
803 struct x86_emulate_ops *ops,
804 unsigned int size, unsigned short port,
805 void *dest)
806{
807 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 808
dde7e6d1
AK		 809 if (rc->pos == rc->end) { /* refill pio read ahead */
810 struct decode_cache *c = &ctxt->decode;
811 unsigned int in_page, n;
812 unsigned int count = c->rep_prefix ?
813 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
814 in_page = (ctxt->eflags & EFLG_DF) ?
815 offset_in_page(c->regs[VCPU_REGS_RDI]) :
816 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
817 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
818 count);
819 if (n == 0)
820 n = 1;
821 rc->pos = rc->end = 0;
822 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
823 return 0;
824 rc->end = n * size;
6aa8b732
AK		 825 }
826
dde7e6d1
AK		 827 memcpy(dest, rc->data + rc->pos, size);
828 rc->pos += size;
829 return 1;
830}
6aa8b732 831
dde7e6d1
AK		 832static u32 desc_limit_scaled(struct desc_struct *desc)
833{
834 u32 limit = get_desc_limit(desc);
6aa8b732 835
dde7e6d1
AK		 836 return desc->g ? (limit << 12) | 0xfff : limit;
837}
6aa8b732 838
dde7e6d1
AK		 839static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
840 struct x86_emulate_ops *ops,
841 u16 selector, struct desc_ptr *dt)
842{
843 if (selector & 1 << 2) {
844 struct desc_struct desc;
845 memset (dt, 0, sizeof *dt);
846 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
847 return;
e09d082c 848
dde7e6d1
AK		 849 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
850 dt->address = get_desc_base(&desc);
851 } else
852 ops->get_gdt(dt, ctxt->vcpu);
853}
120df890 854
dde7e6d1
AK		 855/* allowed just for 8 bytes segments */
856static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
857 struct x86_emulate_ops *ops,
858 u16 selector, struct desc_struct *desc)
859{
860 struct desc_ptr dt;
861 u16 index = selector >> 3;
862 int ret;
863 u32 err;
864 ulong addr;
120df890 865
dde7e6d1 866 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 867
dde7e6d1
AK		 868 if (dt.size < index * 8 + 7) {
869 emulate_gp(ctxt, selector & 0xfffc);
870 return X86EMUL_PROPAGATE_FAULT;
e09d082c 871 }
dde7e6d1
AK		 872 addr = dt.address + index * 8;
873 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
874 if (ret == X86EMUL_PROPAGATE_FAULT)
875 emulate_pf(ctxt, addr, err);
e09d082c 876
dde7e6d1
AK		 877 return ret;
878}
ef65c889 879
dde7e6d1
AK		 880/* allowed just for 8 bytes segments */
881static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
882 struct x86_emulate_ops *ops,
883 u16 selector, struct desc_struct *desc)
884{
885 struct desc_ptr dt;
886 u16 index = selector >> 3;
887 u32 err;
888 ulong addr;
889 int ret;
6aa8b732 890
dde7e6d1 891 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 892
dde7e6d1
AK		 893 if (dt.size < index * 8 + 7) {
894 emulate_gp(ctxt, selector & 0xfffc);
895 return X86EMUL_PROPAGATE_FAULT;
896 }
6aa8b732 897
dde7e6d1
AK		 898 addr = dt.address + index * 8;
899 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
900 if (ret == X86EMUL_PROPAGATE_FAULT)
901 emulate_pf(ctxt, addr, err);
c7e75a3d 902
dde7e6d1
AK		 903 return ret;
904}
c7e75a3d 905
dde7e6d1
AK		 906static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
907 struct x86_emulate_ops *ops,
908 u16 selector, int seg)
909{
910 struct desc_struct seg_desc;
911 u8 dpl, rpl, cpl;
912 unsigned err_vec = GP_VECTOR;
913 u32 err_code = 0;
914 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
915 int ret;
69f55cb1 916
dde7e6d1 917 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 918
dde7e6d1
AK		 919 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
920 || ctxt->mode == X86EMUL_MODE_REAL) {
921 /* set real mode segment descriptor */
922 set_desc_base(&seg_desc, selector << 4);
923 set_desc_limit(&seg_desc, 0xffff);
924 seg_desc.type = 3;
925 seg_desc.p = 1;
926 seg_desc.s = 1;
927 goto load;
928 }
929
930 /* NULL selector is not valid for TR, CS and SS */
931 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
932 && null_selector)
933 goto exception;
934
935 /* TR should be in GDT only */
936 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
937 goto exception;
938
939 if (null_selector) /* for NULL selector skip all following checks */
940 goto load;
941
942 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
943 if (ret != X86EMUL_CONTINUE)
944 return ret;
945
946 err_code = selector & 0xfffc;
947 err_vec = GP_VECTOR;
948
949 /* can't load system descriptor into segment selecor */
950 if (seg <= VCPU_SREG_GS && !seg_desc.s)
951 goto exception;
952
953 if (!seg_desc.p) {
954 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
955 goto exception;
956 }
957
958 rpl = selector & 3;
959 dpl = seg_desc.dpl;
960 cpl = ops->cpl(ctxt->vcpu);
961
962 switch (seg) {
963 case VCPU_SREG_SS:
964 /*
965 * segment is not a writable data segment or segment
966 * selector's RPL != CPL or segment selector's RPL != CPL
967 */
968 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
969 goto exception;
6aa8b732 970 break;
dde7e6d1
AK		 971 case VCPU_SREG_CS:
972 if (!(seg_desc.type & 8))
973 goto exception;
974
975 if (seg_desc.type & 4) {
976 /* conforming */
977 if (dpl > cpl)
978 goto exception;
979 } else {
980 /* nonconforming */
981 if (rpl > cpl || dpl != cpl)
982 goto exception;
983 }
984 /* CS(RPL) <- CPL */
985 selector = (selector & 0xfffc) | cpl;
6aa8b732 986 break;
dde7e6d1
AK		 987 case VCPU_SREG_TR:
988 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
989 goto exception;
990 break;
991 case VCPU_SREG_LDTR:
992 if (seg_desc.s || seg_desc.type != 2)
993 goto exception;
994 break;
995 default: /* DS, ES, FS, or GS */
4e62417b 996 /*
dde7e6d1
AK		 997 * segment is not a data or readable code segment or
998 * ((segment is a data or nonconforming code segment)
999 * and (both RPL and CPL > DPL))
4e62417b 1000 */
dde7e6d1
AK		 1001 if ((seg_desc.type & 0xa) == 0x8 ||
1002 (((seg_desc.type & 0xc) != 0xc) &&
1003 (rpl > dpl && cpl > dpl)))
1004 goto exception;
6aa8b732 1005 break;
dde7e6d1
AK		 1006 }
1007
1008 if (seg_desc.s) {
1009 /* mark segment as accessed */
1010 seg_desc.type |= 1;
1011 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1012 if (ret != X86EMUL_CONTINUE)
1013 return ret;
1014 }
1015load:
1016 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1017 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1018 return X86EMUL_CONTINUE;
1019exception:
1020 emulate_exception(ctxt, err_vec, err_code, true);
1021 return X86EMUL_PROPAGATE_FAULT;
1022}
1023
31be40b3
WY		 1024static void write_register_operand(struct operand *op)
1025{
1026 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1027 switch (op->bytes) {
1028 case 1:
1029 *(u8 *)op->addr.reg = (u8)op->val;
1030 break;
1031 case 2:
1032 *(u16 *)op->addr.reg = (u16)op->val;
1033 break;
1034 case 4:
1035 *op->addr.reg = (u32)op->val;
1036 break; /* 64b: zero-extend */
1037 case 8:
1038 *op->addr.reg = op->val;
1039 break;
1040 }
1041}
1042
dde7e6d1
AK		 1043static inline int writeback(struct x86_emulate_ctxt *ctxt,
1044 struct x86_emulate_ops *ops)
1045{
1046 int rc;
1047 struct decode_cache *c = &ctxt->decode;
1048 u32 err;
1049
1050 switch (c->dst.type) {
1051 case OP_REG:
31be40b3 1052 write_register_operand(&c->dst);
6aa8b732 1053 break;
dde7e6d1
AK		 1054 case OP_MEM:
1055 if (c->lock_prefix)
1056 rc = ops->cmpxchg_emulated(
1a6440ae 1057 c->dst.addr.mem,
dde7e6d1
AK		 1058 &c->dst.orig_val,
1059 &c->dst.val,
1060 c->dst.bytes,
1061 &err,
1062 ctxt->vcpu);
341de7e3 1063 else
dde7e6d1 1064 rc = ops->write_emulated(
1a6440ae 1065 c->dst.addr.mem,
dde7e6d1
AK		 1066 &c->dst.val,
1067 c->dst.bytes,
1068 &err,
1069 ctxt->vcpu);
1070 if (rc == X86EMUL_PROPAGATE_FAULT)
1a6440ae 1071 emulate_pf(ctxt, c->dst.addr.mem, err);
dde7e6d1
AK		 1072 if (rc != X86EMUL_CONTINUE)
1073 return rc;
a682e354 1074 break;
dde7e6d1
AK		 1075 case OP_NONE:
1076 /* no writeback */
414e6277 1077 break;
dde7e6d1 1078 default:
414e6277 1079 break;
6aa8b732 1080 }
dde7e6d1
AK		 1081 return X86EMUL_CONTINUE;
1082}
6aa8b732 1083
dde7e6d1
AK		 1084static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1085 struct x86_emulate_ops *ops)
1086{
1087 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1088
dde7e6d1
AK		 1089 c->dst.type = OP_MEM;
1090 c->dst.bytes = c->op_bytes;
1091 c->dst.val = c->src.val;
1092 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1093 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1094 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1095}
69f55cb1 1096
dde7e6d1
AK		 1097static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1098 struct x86_emulate_ops *ops,
1099 void *dest, int len)
1100{
1101 struct decode_cache *c = &ctxt->decode;
1102 int rc;
8b4caf66 1103
dde7e6d1
AK		 1104 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1105 c->regs[VCPU_REGS_RSP]),
1106 dest, len);
1107 if (rc != X86EMUL_CONTINUE)
1108 return rc;
1109
1110 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1111 return rc;
8b4caf66
LV		 1112}
1113
dde7e6d1
AK		 1114static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1115 struct x86_emulate_ops *ops,
1116 void *dest, int len)
9de41573
GN		 1117{
1118 int rc;
dde7e6d1
AK		 1119 unsigned long val, change_mask;
1120 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1121 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1122
dde7e6d1
AK		 1123 rc = emulate_pop(ctxt, ops, &val, len);
1124 if (rc != X86EMUL_CONTINUE)
1125 return rc;
9de41573 1126
dde7e6d1
AK		 1127 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1128 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1129
dde7e6d1
AK		 1130 switch(ctxt->mode) {
1131 case X86EMUL_MODE_PROT64:
1132 case X86EMUL_MODE_PROT32:
1133 case X86EMUL_MODE_PROT16:
1134 if (cpl == 0)
1135 change_mask |= EFLG_IOPL;
1136 if (cpl <= iopl)
1137 change_mask |= EFLG_IF;
1138 break;
1139 case X86EMUL_MODE_VM86:
1140 if (iopl < 3) {
1141 emulate_gp(ctxt, 0);
1142 return X86EMUL_PROPAGATE_FAULT;
1143 }
1144 change_mask |= EFLG_IF;
1145 break;
1146 default: /* real mode */
1147 change_mask |= (EFLG_IOPL | EFLG_IF);
1148 break;
9de41573 1149 }
dde7e6d1
AK		 1150
1151 *(unsigned long *)dest =
1152 (ctxt->eflags & ~change_mask) | (val & change_mask);
1153
1154 return rc;
9de41573
GN		 1155}
1156
dde7e6d1
AK		 1157static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1158 struct x86_emulate_ops *ops, int seg)
7b262e90 1159{
dde7e6d1 1160 struct decode_cache *c = &ctxt->decode;
7b262e90 1161
dde7e6d1 1162 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1163
dde7e6d1 1164 emulate_push(ctxt, ops);
7b262e90
GN		 1165}
1166
dde7e6d1
AK		 1167static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1168 struct x86_emulate_ops *ops, int seg)
38ba30ba 1169{
dde7e6d1
AK		 1170 struct decode_cache *c = &ctxt->decode;
1171 unsigned long selector;
1172 int rc;
38ba30ba 1173
dde7e6d1
AK		 1174 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1175 if (rc != X86EMUL_CONTINUE)
1176 return rc;
1177
1178 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1179 return rc;
38ba30ba
GN		 1180}
1181
dde7e6d1
AK		 1182static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1183 struct x86_emulate_ops *ops)
38ba30ba 1184{
dde7e6d1
AK		 1185 struct decode_cache *c = &ctxt->decode;
1186 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1187 int rc = X86EMUL_CONTINUE;
1188 int reg = VCPU_REGS_RAX;
38ba30ba 1189
dde7e6d1
AK		 1190 while (reg <= VCPU_REGS_RDI) {
1191 (reg == VCPU_REGS_RSP) ?
1192 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1193
dde7e6d1 1194 emulate_push(ctxt, ops);
38ba30ba 1195
dde7e6d1
AK		 1196 rc = writeback(ctxt, ops);
1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
38ba30ba 1199
dde7e6d1 1200 ++reg;
38ba30ba 1201 }
38ba30ba 1202
dde7e6d1
AK		 1203 /* Disable writeback. */
1204 c->dst.type = OP_NONE;
1205
1206 return rc;
38ba30ba
GN		 1207}
1208
dde7e6d1
AK		 1209static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1210 struct x86_emulate_ops *ops)
38ba30ba 1211{
dde7e6d1
AK		 1212 struct decode_cache *c = &ctxt->decode;
1213 int rc = X86EMUL_CONTINUE;
1214 int reg = VCPU_REGS_RDI;
38ba30ba 1215
dde7e6d1
AK		 1216 while (reg >= VCPU_REGS_RAX) {
1217 if (reg == VCPU_REGS_RSP) {
1218 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1219 c->op_bytes);
1220 --reg;
1221 }
38ba30ba 1222
dde7e6d1
AK		 1223 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1224 if (rc != X86EMUL_CONTINUE)
1225 break;
1226 --reg;
38ba30ba 1227 }
dde7e6d1 1228 return rc;
38ba30ba
GN		 1229}
1230
6e154e56
MG		 1231int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1232 struct x86_emulate_ops *ops, int irq)
1233{
1234 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1235 int rc;
6e154e56
MG		 1236 struct desc_ptr dt;
1237 gva_t cs_addr;
1238 gva_t eip_addr;
1239 u16 cs, eip;
1240 u32 err;
1241
1242 /* TODO: Add limit checks */
1243 c->src.val = ctxt->eflags;
1244 emulate_push(ctxt, ops);
5c56e1cf
AK		 1245 rc = writeback(ctxt, ops);
1246 if (rc != X86EMUL_CONTINUE)
1247 return rc;
6e154e56
MG		 1248
1249 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1250
1251 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1252 emulate_push(ctxt, ops);
5c56e1cf
AK		 1253 rc = writeback(ctxt, ops);
1254 if (rc != X86EMUL_CONTINUE)
1255 return rc;
6e154e56
MG		 1256
1257 c->src.val = c->eip;
1258 emulate_push(ctxt, ops);
5c56e1cf
AK		 1259 rc = writeback(ctxt, ops);
1260 if (rc != X86EMUL_CONTINUE)
1261 return rc;
1262
1263 c->dst.type = OP_NONE;
6e154e56
MG		 1264
1265 ops->get_idt(&dt, ctxt->vcpu);
1266
1267 eip_addr = dt.address + (irq << 2);
1268 cs_addr = dt.address + (irq << 2) + 2;
1269
1270 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1271 if (rc != X86EMUL_CONTINUE)
1272 return rc;
1273
1274 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
1277
1278 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1279 if (rc != X86EMUL_CONTINUE)
1280 return rc;
1281
1282 c->eip = eip;
1283
1284 return rc;
1285}
1286
1287static int emulate_int(struct x86_emulate_ctxt *ctxt,
1288 struct x86_emulate_ops *ops, int irq)
1289{
1290 switch(ctxt->mode) {
1291 case X86EMUL_MODE_REAL:
1292 return emulate_int_real(ctxt, ops, irq);
1293 case X86EMUL_MODE_VM86:
1294 case X86EMUL_MODE_PROT16:
1295 case X86EMUL_MODE_PROT32:
1296 case X86EMUL_MODE_PROT64:
1297 default:
1298 /* Protected mode interrupts unimplemented yet */
1299 return X86EMUL_UNHANDLEABLE;
1300 }
1301}
1302
dde7e6d1
AK		 1303static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1304 struct x86_emulate_ops *ops)
38ba30ba 1305{
dde7e6d1
AK		 1306 struct decode_cache *c = &ctxt->decode;
1307 int rc = X86EMUL_CONTINUE;
1308 unsigned long temp_eip = 0;
1309 unsigned long temp_eflags = 0;
1310 unsigned long cs = 0;
1311 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1312 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1313 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1314 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1315
dde7e6d1 1316 /* TODO: Add stack limit check */
38ba30ba 1317
dde7e6d1 1318 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1319
dde7e6d1
AK		 1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
38ba30ba 1322
dde7e6d1
AK		 1323 if (temp_eip & ~0xffff) {
1324 emulate_gp(ctxt, 0);
1325 return X86EMUL_PROPAGATE_FAULT;
1326 }
38ba30ba 1327
dde7e6d1 1328 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1329
dde7e6d1
AK		 1330 if (rc != X86EMUL_CONTINUE)
1331 return rc;
38ba30ba 1332
dde7e6d1 1333 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1334
dde7e6d1
AK		 1335 if (rc != X86EMUL_CONTINUE)
1336 return rc;
38ba30ba 1337
dde7e6d1 1338 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1339
dde7e6d1
AK		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
38ba30ba 1342
dde7e6d1 1343 c->eip = temp_eip;
38ba30ba 1344
38ba30ba 1345
dde7e6d1
AK		 1346 if (c->op_bytes == 4)
1347 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1348 else if (c->op_bytes == 2) {
1349 ctxt->eflags &= ~0xffff;
1350 ctxt->eflags |= temp_eflags;
38ba30ba 1351 }
dde7e6d1
AK		 1352
1353 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1354 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1355
1356 return rc;
38ba30ba
GN		 1357}
1358
dde7e6d1
AK		 1359static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1360 struct x86_emulate_ops* ops)
c37eda13 1361{
dde7e6d1
AK		 1362 switch(ctxt->mode) {
1363 case X86EMUL_MODE_REAL:
1364 return emulate_iret_real(ctxt, ops);
1365 case X86EMUL_MODE_VM86:
1366 case X86EMUL_MODE_PROT16:
1367 case X86EMUL_MODE_PROT32:
1368 case X86EMUL_MODE_PROT64:
c37eda13 1369 default:
dde7e6d1
AK		 1370 /* iret from protected mode unimplemented yet */
1371 return X86EMUL_UNHANDLEABLE;
c37eda13 1372 }
c37eda13
WY		 1373}
1374
dde7e6d1 1375static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1376 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1377{
1378 struct decode_cache *c = &ctxt->decode;
1379
dde7e6d1 1380 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1381}
1382
dde7e6d1 1383static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1384{
05f086f8 1385 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1386 switch (c->modrm_reg) {
1387 case 0: /* rol */
05f086f8 1388 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1389 break;
1390 case 1: /* ror */
05f086f8 1391 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1392 break;
1393 case 2: /* rcl */
05f086f8 1394 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1395 break;
1396 case 3: /* rcr */
05f086f8 1397 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1398 break;
1399 case 4: /* sal/shl */
1400 case 6: /* sal/shl */
05f086f8 1401 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1402 break;
1403 case 5: /* shr */
05f086f8 1404 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1405 break;
1406 case 7: /* sar */
05f086f8 1407 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1408 break;
1409 }
1410}
1411
1412static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1413 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1414{
1415 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1416 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1417 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
8cdbd2c9
LV		 1418
1419 switch (c->modrm_reg) {
1420 case 0 ... 1: /* test */
05f086f8 1421 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1422 break;
1423 case 2: /* not */
1424 c->dst.val = ~c->dst.val;
1425 break;
1426 case 3: /* neg */
05f086f8 1427 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1428 break;
3f9f53b0
MG		 1429 case 4: /* mul */
1430 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1431 break;
1432 case 5: /* imul */
1433 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1434 break;
1435 case 6: /* div */
1436 emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
1437 break;
1438 case 7: /* idiv */
1439 emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
1440 break;
8cdbd2c9 1441 default:
8c5eee30 1442 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1443 }
8c5eee30 1444 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1445}
1446
1447static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1448 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1449{
1450 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1451
1452 switch (c->modrm_reg) {
1453 case 0: /* inc */
05f086f8 1454 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1455 break;
1456 case 1: /* dec */
05f086f8 1457 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1458 break;
d19292e4
MG		 1459 case 2: /* call near abs */ {
1460 long int old_eip;
1461 old_eip = c->eip;
1462 c->eip = c->src.val;
1463 c->src.val = old_eip;
79168fd1 1464 emulate_push(ctxt, ops);
d19292e4
MG		 1465 break;
1466 }
8cdbd2c9 1467 case 4: /* jmp abs */
fd60754e 1468 c->eip = c->src.val;
8cdbd2c9
LV		 1469 break;
1470 case 6: /* push */
79168fd1 1471 emulate_push(ctxt, ops);
8cdbd2c9 1472 break;
8cdbd2c9 1473 }
1b30eaa8 1474 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1475}
1476
1477static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1478 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1479{
1480 struct decode_cache *c = &ctxt->decode;
16518d5a 1481 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1482
1483 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1484 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1485 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1486 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1487 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1488 } else {
16518d5a
AK		 1489 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1490 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1491
05f086f8 1492 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1493 }
1b30eaa8 1494 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1495}
1496
a77ab5ea
AK		 1497static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1498 struct x86_emulate_ops *ops)
1499{
1500 struct decode_cache *c = &ctxt->decode;
1501 int rc;
1502 unsigned long cs;
1503
1504 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1505 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1506 return rc;
1507 if (c->op_bytes == 4)
1508 c->eip = (u32)c->eip;
1509 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1510 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1511 return rc;
2e873022 1512 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1513 return rc;
1514}
1515
e66bb2cc
AP		 1516static inline void
1517setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1518 struct x86_emulate_ops *ops, struct desc_struct *cs,
1519 struct desc_struct *ss)
e66bb2cc 1520{
79168fd1
GN		 1521 memset(cs, 0, sizeof(struct desc_struct));
1522 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1523 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1524
1525 cs->l = 0; /* will be adjusted later */
79168fd1 1526 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1527 cs->g = 1; /* 4kb granularity */
79168fd1 1528 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1529 cs->type = 0x0b; /* Read, Execute, Accessed */
1530 cs->s = 1;
1531 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1532 cs->p = 1;
1533 cs->d = 1;
e66bb2cc 1534
79168fd1
GN		 1535 set_desc_base(ss, 0); /* flat segment */
1536 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1537 ss->g = 1; /* 4kb granularity */
1538 ss->s = 1;
1539 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1540 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1541 ss->dpl = 0;
79168fd1 1542 ss->p = 1;
e66bb2cc
AP		 1543}
1544
1545static int
3fb1b5db 1546emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1547{
1548 struct decode_cache *c = &ctxt->decode;
79168fd1 1549 struct desc_struct cs, ss;
e66bb2cc 1550 u64 msr_data;
79168fd1 1551 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1552
1553 /* syscall is not available in real mode */
2e901c4c
GN		 1554 if (ctxt->mode == X86EMUL_MODE_REAL ||
1555 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1556 emulate_ud(ctxt);
2e901c4c
GN		 1557 return X86EMUL_PROPAGATE_FAULT;
1558 }
e66bb2cc 1559
79168fd1 1560 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1561
3fb1b5db 1562 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1563 msr_data >>= 32;
79168fd1
GN		 1564 cs_sel = (u16)(msr_data & 0xfffc);
1565 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1566
1567 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1568 cs.d = 0;
e66bb2cc
AP		 1569 cs.l = 1;
1570 }
79168fd1
GN		 1571 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1572 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1573 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1574 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1575
1576 c->regs[VCPU_REGS_RCX] = c->eip;
1577 if (is_long_mode(ctxt->vcpu)) {
1578#ifdef CONFIG_X86_64
1579 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1580
3fb1b5db
GN		 1581 ops->get_msr(ctxt->vcpu,
1582 ctxt->mode == X86EMUL_MODE_PROT64 ?
1583 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1584 c->eip = msr_data;
1585
3fb1b5db 1586 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1587 ctxt->eflags &= ~(msr_data | EFLG_RF);
1588#endif
1589 } else {
1590 /* legacy mode */
3fb1b5db 1591 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1592 c->eip = (u32)msr_data;
1593
1594 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1595 }
1596
e54cfa97 1597 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1598}
1599
8c604352 1600static int
3fb1b5db 1601emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1602{
1603 struct decode_cache *c = &ctxt->decode;
79168fd1 1604 struct desc_struct cs, ss;
8c604352 1605 u64 msr_data;
79168fd1 1606 u16 cs_sel, ss_sel;
8c604352 1607
a0044755
GN		 1608 /* inject #GP if in real mode */
1609 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1610 emulate_gp(ctxt, 0);
2e901c4c 1611 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1612 }
1613
1614 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1615 * Therefore, we inject an #UD.
1616 */
2e901c4c 1617 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1618 emulate_ud(ctxt);
2e901c4c
GN		 1619 return X86EMUL_PROPAGATE_FAULT;
1620 }
8c604352 1621
79168fd1 1622 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1623
3fb1b5db 1624 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1625 switch (ctxt->mode) {
1626 case X86EMUL_MODE_PROT32:
1627 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1628 emulate_gp(ctxt, 0);
e54cfa97 1629 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1630 }
1631 break;
1632 case X86EMUL_MODE_PROT64:
1633 if (msr_data == 0x0) {
54b8486f 1634 emulate_gp(ctxt, 0);
e54cfa97 1635 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1636 }
1637 break;
1638 }
1639
1640 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1641 cs_sel = (u16)msr_data;
1642 cs_sel &= ~SELECTOR_RPL_MASK;
1643 ss_sel = cs_sel + 8;
1644 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1645 if (ctxt->mode == X86EMUL_MODE_PROT64
1646 || is_long_mode(ctxt->vcpu)) {
79168fd1 1647 cs.d = 0;
8c604352
AP		 1648 cs.l = 1;
1649 }
1650
79168fd1
GN		 1651 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1652 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1653 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1654 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1655
3fb1b5db 1656 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1657 c->eip = msr_data;
1658
3fb1b5db 1659 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1660 c->regs[VCPU_REGS_RSP] = msr_data;
1661
e54cfa97 1662 return X86EMUL_CONTINUE;
8c604352
AP		 1663}
1664
4668f050 1665static int
3fb1b5db 1666emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1667{
1668 struct decode_cache *c = &ctxt->decode;
79168fd1 1669 struct desc_struct cs, ss;
4668f050
AP		 1670 u64 msr_data;
1671 int usermode;
79168fd1 1672 u16 cs_sel, ss_sel;
4668f050 1673
a0044755
GN		 1674 /* inject #GP if in real mode or Virtual 8086 mode */
1675 if (ctxt->mode == X86EMUL_MODE_REAL ||
1676 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1677 emulate_gp(ctxt, 0);
2e901c4c 1678 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1679 }
1680
79168fd1 1681 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1682
1683 if ((c->rex_prefix & 0x8) != 0x0)
1684 usermode = X86EMUL_MODE_PROT64;
1685 else
1686 usermode = X86EMUL_MODE_PROT32;
1687
1688 cs.dpl = 3;
1689 ss.dpl = 3;
3fb1b5db 1690 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1691 switch (usermode) {
1692 case X86EMUL_MODE_PROT32:
79168fd1 1693 cs_sel = (u16)(msr_data + 16);
4668f050 1694 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1695 emulate_gp(ctxt, 0);
e54cfa97 1696 return X86EMUL_PROPAGATE_FAULT;
4668f050 1697 }
79168fd1 1698 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1699 break;
1700 case X86EMUL_MODE_PROT64:
79168fd1 1701 cs_sel = (u16)(msr_data + 32);
4668f050 1702 if (msr_data == 0x0) {
54b8486f 1703 emulate_gp(ctxt, 0);
e54cfa97 1704 return X86EMUL_PROPAGATE_FAULT;
4668f050 1705 }
79168fd1
GN		 1706 ss_sel = cs_sel + 8;
1707 cs.d = 0;
4668f050
AP		 1708 cs.l = 1;
1709 break;
1710 }
79168fd1
GN		 1711 cs_sel |= SELECTOR_RPL_MASK;
1712 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1713
79168fd1
GN		 1714 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1715 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1716 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1717 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1718
bdb475a3
GN		 1719 c->eip = c->regs[VCPU_REGS_RDX];
1720 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1721
e54cfa97 1722 return X86EMUL_CONTINUE;
4668f050
AP		 1723}
1724
9c537244
GN		 1725static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1726 struct x86_emulate_ops *ops)
f850e2e6
GN		 1727{
1728 int iopl;
1729 if (ctxt->mode == X86EMUL_MODE_REAL)
1730 return false;
1731 if (ctxt->mode == X86EMUL_MODE_VM86)
1732 return true;
1733 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1734 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1735}
1736
1737static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1738 struct x86_emulate_ops *ops,
1739 u16 port, u16 len)
1740{
79168fd1 1741 struct desc_struct tr_seg;
f850e2e6
GN		 1742 int r;
1743 u16 io_bitmap_ptr;
1744 u8 perm, bit_idx = port & 0x7;
1745 unsigned mask = (1 << len) - 1;
1746
79168fd1
GN		 1747 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1748 if (!tr_seg.p)
f850e2e6 1749 return false;
79168fd1 1750 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1751 return false;
79168fd1
GN		 1752 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1753 ctxt->vcpu, NULL);
f850e2e6
GN		 1754 if (r != X86EMUL_CONTINUE)
1755 return false;
79168fd1 1756 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1757 return false;
79168fd1
GN		 1758 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1759 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1760 if (r != X86EMUL_CONTINUE)
1761 return false;
1762 if ((perm >> bit_idx) & mask)
1763 return false;
1764 return true;
1765}
1766
1767static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1768 struct x86_emulate_ops *ops,
1769 u16 port, u16 len)
1770{
4fc40f07
GN		 1771 if (ctxt->perm_ok)
1772 return true;
1773
9c537244 1774 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1775 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1776 return false;
4fc40f07
GN		 1777
1778 ctxt->perm_ok = true;
1779
f850e2e6
GN		 1780 return true;
1781}
1782
38ba30ba
GN		 1783static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1784 struct x86_emulate_ops *ops,
1785 struct tss_segment_16 *tss)
1786{
1787 struct decode_cache *c = &ctxt->decode;
1788
1789 tss->ip = c->eip;
1790 tss->flag = ctxt->eflags;
1791 tss->ax = c->regs[VCPU_REGS_RAX];
1792 tss->cx = c->regs[VCPU_REGS_RCX];
1793 tss->dx = c->regs[VCPU_REGS_RDX];
1794 tss->bx = c->regs[VCPU_REGS_RBX];
1795 tss->sp = c->regs[VCPU_REGS_RSP];
1796 tss->bp = c->regs[VCPU_REGS_RBP];
1797 tss->si = c->regs[VCPU_REGS_RSI];
1798 tss->di = c->regs[VCPU_REGS_RDI];
1799
1800 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1801 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1802 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1803 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1804 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1805}
1806
1807static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1808 struct x86_emulate_ops *ops,
1809 struct tss_segment_16 *tss)
1810{
1811 struct decode_cache *c = &ctxt->decode;
1812 int ret;
1813
1814 c->eip = tss->ip;
1815 ctxt->eflags = tss->flag | 2;
1816 c->regs[VCPU_REGS_RAX] = tss->ax;
1817 c->regs[VCPU_REGS_RCX] = tss->cx;
1818 c->regs[VCPU_REGS_RDX] = tss->dx;
1819 c->regs[VCPU_REGS_RBX] = tss->bx;
1820 c->regs[VCPU_REGS_RSP] = tss->sp;
1821 c->regs[VCPU_REGS_RBP] = tss->bp;
1822 c->regs[VCPU_REGS_RSI] = tss->si;
1823 c->regs[VCPU_REGS_RDI] = tss->di;
1824
1825 /*
1826 * SDM says that segment selectors are loaded before segment
1827 * descriptors
1828 */
1829 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1830 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1831 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1832 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1833 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1834
1835 /*
1836 * Now load segment descriptors. If fault happenes at this stage
1837 * it is handled in a context of new task
1838 */
1839 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1840 if (ret != X86EMUL_CONTINUE)
1841 return ret;
1842 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1843 if (ret != X86EMUL_CONTINUE)
1844 return ret;
1845 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1846 if (ret != X86EMUL_CONTINUE)
1847 return ret;
1848 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1849 if (ret != X86EMUL_CONTINUE)
1850 return ret;
1851 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1852 if (ret != X86EMUL_CONTINUE)
1853 return ret;
1854
1855 return X86EMUL_CONTINUE;
1856}
1857
1858static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1859 struct x86_emulate_ops *ops,
1860 u16 tss_selector, u16 old_tss_sel,
1861 ulong old_tss_base, struct desc_struct *new_desc)
1862{
1863 struct tss_segment_16 tss_seg;
1864 int ret;
1865 u32 err, new_tss_base = get_desc_base(new_desc);
1866
1867 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1868 &err);
1869 if (ret == X86EMUL_PROPAGATE_FAULT) {
1870 /* FIXME: need to provide precise fault address */
54b8486f 1871 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1872 return ret;
1873 }
1874
1875 save_state_to_tss16(ctxt, ops, &tss_seg);
1876
1877 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1878 &err);
1879 if (ret == X86EMUL_PROPAGATE_FAULT) {
1880 /* FIXME: need to provide precise fault address */
54b8486f 1881 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1882 return ret;
1883 }
1884
1885 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1886 &err);
1887 if (ret == X86EMUL_PROPAGATE_FAULT) {
1888 /* FIXME: need to provide precise fault address */
54b8486f 1889 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1890 return ret;
1891 }
1892
1893 if (old_tss_sel != 0xffff) {
1894 tss_seg.prev_task_link = old_tss_sel;
1895
1896 ret = ops->write_std(new_tss_base,
1897 &tss_seg.prev_task_link,
1898 sizeof tss_seg.prev_task_link,
1899 ctxt->vcpu, &err);
1900 if (ret == X86EMUL_PROPAGATE_FAULT) {
1901 /* FIXME: need to provide precise fault address */
54b8486f 1902 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1903 return ret;
1904 }
1905 }
1906
1907 return load_state_from_tss16(ctxt, ops, &tss_seg);
1908}
1909
1910static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1911 struct x86_emulate_ops *ops,
1912 struct tss_segment_32 *tss)
1913{
1914 struct decode_cache *c = &ctxt->decode;
1915
1916 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1917 tss->eip = c->eip;
1918 tss->eflags = ctxt->eflags;
1919 tss->eax = c->regs[VCPU_REGS_RAX];
1920 tss->ecx = c->regs[VCPU_REGS_RCX];
1921 tss->edx = c->regs[VCPU_REGS_RDX];
1922 tss->ebx = c->regs[VCPU_REGS_RBX];
1923 tss->esp = c->regs[VCPU_REGS_RSP];
1924 tss->ebp = c->regs[VCPU_REGS_RBP];
1925 tss->esi = c->regs[VCPU_REGS_RSI];
1926 tss->edi = c->regs[VCPU_REGS_RDI];
1927
1928 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1929 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1930 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1931 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1932 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1933 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1934 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1935}
1936
1937static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1938 struct x86_emulate_ops *ops,
1939 struct tss_segment_32 *tss)
1940{
1941 struct decode_cache *c = &ctxt->decode;
1942 int ret;
1943
0f12244f 1944 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 1945 emulate_gp(ctxt, 0);
0f12244f
GN		 1946 return X86EMUL_PROPAGATE_FAULT;
1947 }
38ba30ba
GN		 1948 c->eip = tss->eip;
1949 ctxt->eflags = tss->eflags | 2;
1950 c->regs[VCPU_REGS_RAX] = tss->eax;
1951 c->regs[VCPU_REGS_RCX] = tss->ecx;
1952 c->regs[VCPU_REGS_RDX] = tss->edx;
1953 c->regs[VCPU_REGS_RBX] = tss->ebx;
1954 c->regs[VCPU_REGS_RSP] = tss->esp;
1955 c->regs[VCPU_REGS_RBP] = tss->ebp;
1956 c->regs[VCPU_REGS_RSI] = tss->esi;
1957 c->regs[VCPU_REGS_RDI] = tss->edi;
1958
1959 /*
1960 * SDM says that segment selectors are loaded before segment
1961 * descriptors
1962 */
1963 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1964 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1965 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1966 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1967 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1968 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1969 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1970
1971 /*
1972 * Now load segment descriptors. If fault happenes at this stage
1973 * it is handled in a context of new task
1974 */
1975 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1976 if (ret != X86EMUL_CONTINUE)
1977 return ret;
1978 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1979 if (ret != X86EMUL_CONTINUE)
1980 return ret;
1981 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1982 if (ret != X86EMUL_CONTINUE)
1983 return ret;
1984 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1985 if (ret != X86EMUL_CONTINUE)
1986 return ret;
1987 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1988 if (ret != X86EMUL_CONTINUE)
1989 return ret;
1990 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1991 if (ret != X86EMUL_CONTINUE)
1992 return ret;
1993 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1994 if (ret != X86EMUL_CONTINUE)
1995 return ret;
1996
1997 return X86EMUL_CONTINUE;
1998}
1999
2000static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2001 struct x86_emulate_ops *ops,
2002 u16 tss_selector, u16 old_tss_sel,
2003 ulong old_tss_base, struct desc_struct *new_desc)
2004{
2005 struct tss_segment_32 tss_seg;
2006 int ret;
2007 u32 err, new_tss_base = get_desc_base(new_desc);
2008
2009 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2010 &err);
2011 if (ret == X86EMUL_PROPAGATE_FAULT) {
2012 /* FIXME: need to provide precise fault address */
54b8486f 2013 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2014 return ret;
2015 }
2016
2017 save_state_to_tss32(ctxt, ops, &tss_seg);
2018
2019 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2020 &err);
2021 if (ret == X86EMUL_PROPAGATE_FAULT) {
2022 /* FIXME: need to provide precise fault address */
54b8486f 2023 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2024 return ret;
2025 }
2026
2027 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2028 &err);
2029 if (ret == X86EMUL_PROPAGATE_FAULT) {
2030 /* FIXME: need to provide precise fault address */
54b8486f 2031 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2032 return ret;
2033 }
2034
2035 if (old_tss_sel != 0xffff) {
2036 tss_seg.prev_task_link = old_tss_sel;
2037
2038 ret = ops->write_std(new_tss_base,
2039 &tss_seg.prev_task_link,
2040 sizeof tss_seg.prev_task_link,
2041 ctxt->vcpu, &err);
2042 if (ret == X86EMUL_PROPAGATE_FAULT) {
2043 /* FIXME: need to provide precise fault address */
54b8486f 2044 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2045 return ret;
2046 }
2047 }
2048
2049 return load_state_from_tss32(ctxt, ops, &tss_seg);
2050}
2051
2052static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2053 struct x86_emulate_ops *ops,
2054 u16 tss_selector, int reason,
2055 bool has_error_code, u32 error_code)
38ba30ba
GN		 2056{
2057 struct desc_struct curr_tss_desc, next_tss_desc;
2058 int ret;
2059 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2060 ulong old_tss_base =
5951c442 2061 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2062 u32 desc_limit;
38ba30ba
GN		 2063
2064 /* FIXME: old_tss_base == ~0 ? */
2065
2066 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2067 if (ret != X86EMUL_CONTINUE)
2068 return ret;
2069 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2070 if (ret != X86EMUL_CONTINUE)
2071 return ret;
2072
2073 /* FIXME: check that next_tss_desc is tss */
2074
2075 if (reason != TASK_SWITCH_IRET) {
2076 if ((tss_selector & 3) > next_tss_desc.dpl ||
2077 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2078 emulate_gp(ctxt, 0);
38ba30ba
GN		 2079 return X86EMUL_PROPAGATE_FAULT;
2080 }
2081 }
2082
ceffb459
GN		 2083 desc_limit = desc_limit_scaled(&next_tss_desc);
2084 if (!next_tss_desc.p ||
2085 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2086 desc_limit < 0x2b)) {
54b8486f 2087 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2088 return X86EMUL_PROPAGATE_FAULT;
2089 }
2090
2091 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2092 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2093 write_segment_descriptor(ctxt, ops, old_tss_sel,
2094 &curr_tss_desc);
2095 }
2096
2097 if (reason == TASK_SWITCH_IRET)
2098 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2099
2100 /* set back link to prev task only if NT bit is set in eflags
2101 note that old_tss_sel is not used afetr this point */
2102 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2103 old_tss_sel = 0xffff;
2104
2105 if (next_tss_desc.type & 8)
2106 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2107 old_tss_base, &next_tss_desc);
2108 else
2109 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2110 old_tss_base, &next_tss_desc);
0760d448
JK		 2111 if (ret != X86EMUL_CONTINUE)
2112 return ret;
38ba30ba
GN		 2113
2114 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2115 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2116
2117 if (reason != TASK_SWITCH_IRET) {
2118 next_tss_desc.type |= (1 << 1); /* set busy flag */
2119 write_segment_descriptor(ctxt, ops, tss_selector,
2120 &next_tss_desc);
2121 }
2122
2123 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2124 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2125 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2126
e269fb21
JK		 2127 if (has_error_code) {
2128 struct decode_cache *c = &ctxt->decode;
2129
2130 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2131 c->lock_prefix = 0;
2132 c->src.val = (unsigned long) error_code;
79168fd1 2133 emulate_push(ctxt, ops);
e269fb21
JK		 2134 }
2135
38ba30ba
GN		 2136 return ret;
2137}
2138
2139int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2140 u16 tss_selector, int reason,
2141 bool has_error_code, u32 error_code)
38ba30ba 2142{
9aabc88f 2143 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2144 struct decode_cache *c = &ctxt->decode;
2145 int rc;
2146
38ba30ba 2147 c->eip = ctxt->eip;
e269fb21 2148 c->dst.type = OP_NONE;
38ba30ba 2149
e269fb21
JK		 2150 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2151 has_error_code, error_code);
38ba30ba
GN		 2152
2153 if (rc == X86EMUL_CONTINUE) {
e269fb21 2154 rc = writeback(ctxt, ops);
95c55886
GN		 2155 if (rc == X86EMUL_CONTINUE)
2156 ctxt->eip = c->eip;
38ba30ba
GN		 2157 }
2158
19d04437 2159 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2160}
2161
a682e354 2162static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2163 int reg, struct operand *op)
a682e354
GN		 2164{
2165 struct decode_cache *c = &ctxt->decode;
2166 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2167
d9271123 2168 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2169 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2170}
2171
63540382
AK		 2172static int em_push(struct x86_emulate_ctxt *ctxt)
2173{
2174 emulate_push(ctxt, ctxt->ops);
2175 return X86EMUL_CONTINUE;
2176}
2177
73fba5f4
AK		 2178#define D(_y) { .flags = (_y) }
2179#define N D(0)
2180#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2181#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2182#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2183
2184static struct opcode group1[] = {
2185 X7(D(Lock)), N
2186};
2187
2188static struct opcode group1A[] = {
2189 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2190};
2191
2192static struct opcode group3[] = {
2193 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2194 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2195 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2196};
2197
2198static struct opcode group4[] = {
2199 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2200 N, N, N, N, N, N,
2201};
2202
2203static struct opcode group5[] = {
2204 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2205 D(SrcMem | ModRM | Stack), N,
2206 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2207 D(SrcMem | ModRM | Stack), N,
2208};
2209
2210static struct group_dual group7 = { {
2211 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2212 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2213 D(SrcMem16 | ModRM | Mov | Priv),
2214 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4
AK		 2215}, {
2216 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2217 D(SrcNone | ModRM | DstMem | Mov), N,
2218 D(SrcMem16 | ModRM | Mov | Priv), N,
2219} };
2220
2221static struct opcode group8[] = {
2222 N, N, N, N,
2223 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2224 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2225};
2226
2227static struct group_dual group9 = { {
2228 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2229}, {
2230 N, N, N, N, N, N, N, N,
2231} };
2232
2233static struct opcode opcode_table[256] = {
2234 /* 0x00 - 0x07 */
2235 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2236 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2237 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2238 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2239 /* 0x08 - 0x0F */
2240 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2241 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2242 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2243 D(ImplicitOps | Stack | No64), N,
2244 /* 0x10 - 0x17 */
2245 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2246 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2247 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2248 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2249 /* 0x18 - 0x1F */
2250 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2251 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2252 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2253 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2254 /* 0x20 - 0x27 */
2255 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2256 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2257 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2258 /* 0x28 - 0x2F */
2259 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2260 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2261 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2262 /* 0x30 - 0x37 */
2263 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2264 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2265 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2266 /* 0x38 - 0x3F */
2267 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2268 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2269 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2270 N, N,
2271 /* 0x40 - 0x4F */
2272 X16(D(DstReg)),
2273 /* 0x50 - 0x57 */
63540382 2274 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2275 /* 0x58 - 0x5F */
2276 X8(D(DstReg | Stack)),
2277 /* 0x60 - 0x67 */
2278 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2279 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2280 N, N, N, N,
2281 /* 0x68 - 0x6F */
63540382
AK		 2282 I(SrcImm | Mov | Stack, em_push), N,
2283 I(SrcImmByte | Mov | Stack, em_push), N,
73fba5f4
AK		 2284 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2285 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2286 /* 0x70 - 0x7F */
2287 X16(D(SrcImmByte)),
2288 /* 0x80 - 0x87 */
2289 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2290 G(DstMem | SrcImm | ModRM | Group, group1),
2291 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2292 G(DstMem | SrcImmByte | ModRM | Group, group1),
2293 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2294 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2295 /* 0x88 - 0x8F */
2296 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2297 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
342fc630 2298 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2299 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2300 /* 0x90 - 0x97 */
3d9e77df 2301 X8(D(SrcAcc | DstReg)),
73fba5f4 2302 /* 0x98 - 0x9F */
e8b6fa70 2303 D(DstAcc | SrcNone), N, D(SrcImmFAddr | No64), N,
73fba5f4
AK		 2304 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2305 /* 0xA0 - 0xA7 */
2306 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2307 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2308 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2309 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2310 /* 0xA8 - 0xAF */
06cb7046
WY		 2311 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
2312 D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
73fba5f4 2313 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
f6b33fc5 2314 D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String),
73fba5f4
AK		 2315 /* 0xB0 - 0xB7 */
2316 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2317 /* 0xB8 - 0xBF */
2318 X8(D(DstReg | SrcImm | Mov)),
2319 /* 0xC0 - 0xC7 */
2320 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2321 N, D(ImplicitOps | Stack), N, N,
2322 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2323 /* 0xC8 - 0xCF */
2324 N, N, N, D(ImplicitOps | Stack),
2325 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2326 /* 0xD0 - 0xD7 */
c034da8b 2327 D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
73fba5f4
AK		 2328 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2329 N, N, N, N,
2330 /* 0xD8 - 0xDF */
2331 N, N, N, N, N, N, N, N,
2332 /* 0xE0 - 0xE7 */
f2f31845 2333 X3(D(SrcImmByte)), N,
73fba5f4 2334 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
41167be5 2335 D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte),
73fba5f4
AK		 2336 /* 0xE8 - 0xEF */
2337 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2338 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2339 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
41167be5 2340 D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps),
73fba5f4
AK		 2341 /* 0xF0 - 0xF7 */
2342 N, N, N, N,
2343 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2344 /* 0xF8 - 0xFF */
8744aa9a 2345 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2346 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2347};
2348
2349static struct opcode twobyte_table[256] = {
2350 /* 0x00 - 0x0F */
2351 N, GD(0, &group7), N, N,
2352 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2353 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2354 N, D(ImplicitOps | ModRM), N, N,
2355 /* 0x10 - 0x1F */
2356 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2357 /* 0x20 - 0x2F */
b27f3856
AK		 2358 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2359 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2360 N, N, N, N,
2361 N, N, N, N, N, N, N, N,
2362 /* 0x30 - 0x3F */
2363 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2364 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2365 N, N, N, N, N, N, N, N,
2366 /* 0x40 - 0x4F */
2367 X16(D(DstReg | SrcMem | ModRM | Mov)),
2368 /* 0x50 - 0x5F */
2369 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2370 /* 0x60 - 0x6F */
2371 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2372 /* 0x70 - 0x7F */
2373 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2374 /* 0x80 - 0x8F */
2375 X16(D(SrcImm)),
2376 /* 0x90 - 0x9F */
ee45b58e 2377 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2378 /* 0xA0 - 0xA7 */
2379 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2380 N, D(DstMem | SrcReg | ModRM | BitOp),
2381 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2382 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2383 /* 0xA8 - 0xAF */
2384 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2385 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2386 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2387 D(DstMem | SrcReg | Src2CL | ModRM),
2388 D(ModRM), N,
2389 /* 0xB0 - 0xB7 */
2390 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2391 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2392 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2393 D(DstReg | SrcMem16 | ModRM | Mov),
2394 /* 0xB8 - 0xBF */
2395 N, N,
ba7ff2b7 2396 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2397 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2398 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2399 /* 0xC0 - 0xCF */
92f738a5
WY		 2400 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2401 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2402 N, N, N, GD(0, &group9),
2403 N, N, N, N, N, N, N, N,
2404 /* 0xD0 - 0xDF */
2405 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2406 /* 0xE0 - 0xEF */
2407 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2408 /* 0xF0 - 0xFF */
2409 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2410};
2411
2412#undef D
2413#undef N
2414#undef G
2415#undef GD
2416#undef I
2417
dde7e6d1
AK		 2418int
2419x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2420{
2421 struct x86_emulate_ops *ops = ctxt->ops;
2422 struct decode_cache *c = &ctxt->decode;
2423 int rc = X86EMUL_CONTINUE;
2424 int mode = ctxt->mode;
2425 int def_op_bytes, def_ad_bytes, dual, goffset;
2426 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2427 struct operand memop = { .type = OP_NONE };
dde7e6d1
AK		 2428
2429 /* we cannot decode insn before we complete previous rep insn */
2430 WARN_ON(ctxt->restart);
2431
2432 c->eip = ctxt->eip;
2433 c->fetch.start = c->fetch.end = c->eip;
2434 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2435
2436 switch (mode) {
2437 case X86EMUL_MODE_REAL:
2438 case X86EMUL_MODE_VM86:
2439 case X86EMUL_MODE_PROT16:
2440 def_op_bytes = def_ad_bytes = 2;
2441 break;
2442 case X86EMUL_MODE_PROT32:
2443 def_op_bytes = def_ad_bytes = 4;
2444 break;
2445#ifdef CONFIG_X86_64
2446 case X86EMUL_MODE_PROT64:
2447 def_op_bytes = 4;
2448 def_ad_bytes = 8;
2449 break;
2450#endif
2451 default:
2452 return -1;
2453 }
2454
2455 c->op_bytes = def_op_bytes;
2456 c->ad_bytes = def_ad_bytes;
2457
2458 /* Legacy prefixes. */
2459 for (;;) {
2460 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2461 case 0x66: /* operand-size override */
2462 /* switch between 2/4 bytes */
2463 c->op_bytes = def_op_bytes ^ 6;
2464 break;
2465 case 0x67: /* address-size override */
2466 if (mode == X86EMUL_MODE_PROT64)
2467 /* switch between 4/8 bytes */
2468 c->ad_bytes = def_ad_bytes ^ 12;
2469 else
2470 /* switch between 2/4 bytes */
2471 c->ad_bytes = def_ad_bytes ^ 6;
2472 break;
2473 case 0x26: /* ES override */
2474 case 0x2e: /* CS override */
2475 case 0x36: /* SS override */
2476 case 0x3e: /* DS override */
2477 set_seg_override(c, (c->b >> 3) & 3);
2478 break;
2479 case 0x64: /* FS override */
2480 case 0x65: /* GS override */
2481 set_seg_override(c, c->b & 7);
2482 break;
2483 case 0x40 ... 0x4f: /* REX */
2484 if (mode != X86EMUL_MODE_PROT64)
2485 goto done_prefixes;
2486 c->rex_prefix = c->b;
2487 continue;
2488 case 0xf0: /* LOCK */
2489 c->lock_prefix = 1;
2490 break;
2491 case 0xf2: /* REPNE/REPNZ */
2492 c->rep_prefix = REPNE_PREFIX;
2493 break;
2494 case 0xf3: /* REP/REPE/REPZ */
2495 c->rep_prefix = REPE_PREFIX;
2496 break;
2497 default:
2498 goto done_prefixes;
2499 }
2500
2501 /* Any legacy prefix after a REX prefix nullifies its effect. */
2502
2503 c->rex_prefix = 0;
2504 }
2505
2506done_prefixes:
2507
2508 /* REX prefix. */
1e87e3ef
AK		 2509 if (c->rex_prefix & 8)
2510 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2511
2512 /* Opcode byte(s). */
2513 opcode = opcode_table[c->b];
d3ad6243
WY		 2514 /* Two-byte opcode? */
2515 if (c->b == 0x0f) {
2516 c->twobyte = 1;
2517 c->b = insn_fetch(u8, 1, c->eip);
2518 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2519 }
2520 c->d = opcode.flags;
2521
2522 if (c->d & Group) {
2523 dual = c->d & GroupDual;
2524 c->modrm = insn_fetch(u8, 1, c->eip);
2525 --c->eip;
2526
2527 if (c->d & GroupDual) {
2528 g_mod012 = opcode.u.gdual->mod012;
2529 g_mod3 = opcode.u.gdual->mod3;
2530 } else
2531 g_mod012 = g_mod3 = opcode.u.group;
2532
2533 c->d &= ~(Group | GroupDual);
2534
2535 goffset = (c->modrm >> 3) & 7;
2536
2537 if ((c->modrm >> 6) == 3)
2538 opcode = g_mod3[goffset];
2539 else
2540 opcode = g_mod012[goffset];
2541 c->d |= opcode.flags;
2542 }
2543
2544 c->execute = opcode.u.execute;
2545
2546 /* Unrecognised? */
2547 if (c->d == 0 || (c->d & Undefined)) {
2548 DPRINTF("Cannot emulate %02x\n", c->b);
2549 return -1;
2550 }
2551
2552 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2553 c->op_bytes = 8;
2554
7f9b4b75
AK		 2555 if (c->d & Op3264) {
2556 if (mode == X86EMUL_MODE_PROT64)
2557 c->op_bytes = 8;
2558 else
2559 c->op_bytes = 4;
2560 }
2561
dde7e6d1 2562 /* ModRM and SIB bytes. */
09ee57cd 2563 if (c->d & ModRM) {
2dbd0dd7 2564 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2565 if (!c->has_seg_override)
2566 set_seg_override(c, c->modrm_seg);
2567 } else if (c->d & MemAbs)
2dbd0dd7 2568 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2569 if (rc != X86EMUL_CONTINUE)
2570 goto done;
2571
2572 if (!c->has_seg_override)
2573 set_seg_override(c, VCPU_SREG_DS);
2574
2dbd0dd7
AK		 2575 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2576 memop.addr.mem += seg_override_base(ctxt, ops, c);
dde7e6d1 2577
2dbd0dd7
AK		 2578 if (memop.type == OP_MEM && c->ad_bytes != 8)
2579 memop.addr.mem = (u32)memop.addr.mem;
dde7e6d1 2580
2dbd0dd7
AK		 2581 if (memop.type == OP_MEM && c->rip_relative)
2582 memop.addr.mem += c->eip;
dde7e6d1
AK		 2583
2584 /*
2585 * Decode and fetch the source operand: register, memory
2586 * or immediate.
2587 */
2588 switch (c->d & SrcMask) {
2589 case SrcNone:
2590 break;
2591 case SrcReg:
2592 decode_register_operand(&c->src, c, 0);
2593 break;
2594 case SrcMem16:
2dbd0dd7 2595 memop.bytes = 2;
dde7e6d1
AK		 2596 goto srcmem_common;
2597 case SrcMem32:
2dbd0dd7 2598 memop.bytes = 4;
dde7e6d1
AK		 2599 goto srcmem_common;
2600 case SrcMem:
2dbd0dd7 2601 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2602 c->op_bytes;
dde7e6d1 2603 srcmem_common:
2dbd0dd7 2604 c->src = memop;
dde7e6d1
AK		 2605 break;
2606 case SrcImm:
2607 case SrcImmU:
2608 c->src.type = OP_IMM;
1a6440ae 2609 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2610 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2611 if (c->src.bytes == 8)
2612 c->src.bytes = 4;
2613 /* NB. Immediates are sign-extended as necessary. */
2614 switch (c->src.bytes) {
2615 case 1:
2616 c->src.val = insn_fetch(s8, 1, c->eip);
2617 break;
2618 case 2:
2619 c->src.val = insn_fetch(s16, 2, c->eip);
2620 break;
2621 case 4:
2622 c->src.val = insn_fetch(s32, 4, c->eip);
2623 break;
2624 }
2625 if ((c->d & SrcMask) == SrcImmU) {
2626 switch (c->src.bytes) {
2627 case 1:
2628 c->src.val &= 0xff;
2629 break;
2630 case 2:
2631 c->src.val &= 0xffff;
2632 break;
2633 case 4:
2634 c->src.val &= 0xffffffff;
2635 break;
2636 }
2637 }
2638 break;
2639 case SrcImmByte:
2640 case SrcImmUByte:
2641 c->src.type = OP_IMM;
1a6440ae 2642 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2643 c->src.bytes = 1;
2644 if ((c->d & SrcMask) == SrcImmByte)
2645 c->src.val = insn_fetch(s8, 1, c->eip);
2646 else
2647 c->src.val = insn_fetch(u8, 1, c->eip);
2648 break;
2649 case SrcAcc:
2650 c->src.type = OP_REG;
2651 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2652 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2653 fetch_register_operand(&c->src);
dde7e6d1
AK		 2654 break;
2655 case SrcOne:
2656 c->src.bytes = 1;
2657 c->src.val = 1;
2658 break;
2659 case SrcSI:
2660 c->src.type = OP_MEM;
2661 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2662 c->src.addr.mem =
dde7e6d1
AK		 2663 register_address(c, seg_override_base(ctxt, ops, c),
2664 c->regs[VCPU_REGS_RSI]);
2665 c->src.val = 0;
2666 break;
2667 case SrcImmFAddr:
2668 c->src.type = OP_IMM;
1a6440ae 2669 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2670 c->src.bytes = c->op_bytes + 2;
2671 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2672 break;
2673 case SrcMemFAddr:
2dbd0dd7
AK		 2674 memop.bytes = c->op_bytes + 2;
2675 goto srcmem_common;
dde7e6d1
AK		 2676 break;
2677 }
2678
2679 /*
2680 * Decode and fetch the second source operand: register, memory
2681 * or immediate.
2682 */
2683 switch (c->d & Src2Mask) {
2684 case Src2None:
2685 break;
2686 case Src2CL:
2687 c->src2.bytes = 1;
2688 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2689 break;
2690 case Src2ImmByte:
2691 c->src2.type = OP_IMM;
1a6440ae 2692 c->src2.addr.mem = c->eip;
dde7e6d1
AK		 2693 c->src2.bytes = 1;
2694 c->src2.val = insn_fetch(u8, 1, c->eip);
2695 break;
2696 case Src2One:
2697 c->src2.bytes = 1;
2698 c->src2.val = 1;
2699 break;
2700 }
2701
2702 /* Decode and fetch the destination operand: register or memory. */
2703 switch (c->d & DstMask) {
dde7e6d1
AK		 2704 case DstReg:
2705 decode_register_operand(&c->dst, c,
2706 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2707 break;
943858e2
WY		 2708 case DstImmUByte:
2709 c->dst.type = OP_IMM;
2710 c->dst.addr.mem = c->eip;
2711 c->dst.bytes = 1;
2712 c->dst.val = insn_fetch(u8, 1, c->eip);
2713 break;
dde7e6d1
AK		 2714 case DstMem:
2715 case DstMem64:
2dbd0dd7 2716 c->dst = memop;
dde7e6d1
AK		 2717 if ((c->d & DstMask) == DstMem64)
2718 c->dst.bytes = 8;
2719 else
2720 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2721 if (c->d & BitOp)
2722 fetch_bit_operand(c);
2dbd0dd7 2723 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2724 break;
2725 case DstAcc:
2726 c->dst.type = OP_REG;
2727 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2728 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2729 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2730 c->dst.orig_val = c->dst.val;
2731 break;
2732 case DstDI:
2733 c->dst.type = OP_MEM;
2734 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2735 c->dst.addr.mem =
dde7e6d1
AK		 2736 register_address(c, es_base(ctxt, ops),
2737 c->regs[VCPU_REGS_RDI]);
2738 c->dst.val = 0;
2739 break;
36089fed
WY		 2740 case ImplicitOps:
2741 /* Special instructions do their own operand decoding. */
2742 default:
2743 c->dst.type = OP_NONE; /* Disable writeback. */
2744 return 0;
dde7e6d1
AK		 2745 }
2746
2747done:
2748 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2749}
2750
8b4caf66 2751int
9aabc88f 2752x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2753{
9aabc88f 2754 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2755 u64 msr_data;
8b4caf66 2756 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2757 int rc = X86EMUL_CONTINUE;
5cd21917 2758 int saved_dst_type = c->dst.type;
6e154e56 2759 int irq; /* Used for int 3, int, and into */
8b4caf66 2760
9de41573 2761 ctxt->decode.mem_read.pos = 0;
310b5d30 2762
1161624f 2763 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2764 emulate_ud(ctxt);
1161624f
GN		 2765 goto done;
2766 }
2767
d380a5e4 2768 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2769 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2770 emulate_ud(ctxt);
d380a5e4
GN		 2771 goto done;
2772 }
2773
e92805ac 2774 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2775 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2776 emulate_gp(ctxt, 0);
e92805ac
GN		 2777 goto done;
2778 }
2779
b9fa9d6b 2780 if (c->rep_prefix && (c->d & String)) {
5cd21917 2781 ctxt->restart = true;
b9fa9d6b 2782 /* All REP prefixes have the same first termination condition */
c73e197b 2783 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917 2784 ctxt->restart = false;
95c55886 2785 ctxt->eip = c->eip;
b9fa9d6b
AK		 2786 goto done;
2787 }
b9fa9d6b
AK		 2788 }
2789
c483c02a 2790 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
1a6440ae 2791 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 2792 c->src.valptr, c->src.bytes);
b60d513c 2793 if (rc != X86EMUL_CONTINUE)
8b4caf66 2794 goto done;
16518d5a 2795 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2796 }
2797
e35b7b9c 2798 if (c->src2.type == OP_MEM) {
1a6440ae 2799 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 2800 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2801 if (rc != X86EMUL_CONTINUE)
2802 goto done;
2803 }
2804
8b4caf66
LV		 2805 if ((c->d & DstMask) == ImplicitOps)
2806 goto special_insn;
2807
2808
69f55cb1
GN		 2809 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2810 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 2811 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 2812 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2813 if (rc != X86EMUL_CONTINUE)
2814 goto done;
038e51de 2815 }
e4e03ded 2816 c->dst.orig_val = c->dst.val;
038e51de 2817
018a98db
AK		 2818special_insn:
2819
ef65c889
AK		 2820 if (c->execute) {
2821 rc = c->execute(ctxt);
2822 if (rc != X86EMUL_CONTINUE)
2823 goto done;
2824 goto writeback;
2825 }
2826
e4e03ded 2827 if (c->twobyte)
6aa8b732
AK		 2828 goto twobyte_insn;
2829
e4e03ded 2830 switch (c->b) {
6aa8b732
AK		 2831 case 0x00 ... 0x05:
2832 add: /* add */
05f086f8 2833 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2834 break;
0934ac9d 2835 case 0x06: /* push es */
79168fd1 2836 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2837 break;
2838 case 0x07: /* pop es */
0934ac9d 2839 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2840 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2841 goto done;
2842 break;
6aa8b732
AK		 2843 case 0x08 ... 0x0d:
2844 or: /* or */
05f086f8 2845 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2846 break;
0934ac9d 2847 case 0x0e: /* push cs */
79168fd1 2848 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2849 break;
6aa8b732
AK		 2850 case 0x10 ... 0x15:
2851 adc: /* adc */
05f086f8 2852 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2853 break;
0934ac9d 2854 case 0x16: /* push ss */
79168fd1 2855 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2856 break;
2857 case 0x17: /* pop ss */
0934ac9d 2858 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2859 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2860 goto done;
2861 break;
6aa8b732
AK		 2862 case 0x18 ... 0x1d:
2863 sbb: /* sbb */
05f086f8 2864 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2865 break;
0934ac9d 2866 case 0x1e: /* push ds */
79168fd1 2867 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2868 break;
2869 case 0x1f: /* pop ds */
0934ac9d 2870 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2871 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2872 goto done;
2873 break;
aa3a816b 2874 case 0x20 ... 0x25:
6aa8b732 2875 and: /* and */
05f086f8 2876 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2877 break;
2878 case 0x28 ... 0x2d:
2879 sub: /* sub */
05f086f8 2880 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2881 break;
2882 case 0x30 ... 0x35:
2883 xor: /* xor */
05f086f8 2884 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2885 break;
2886 case 0x38 ... 0x3d:
2887 cmp: /* cmp */
05f086f8 2888 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2889 break;
33615aa9
AK		 2890 case 0x40 ... 0x47: /* inc r16/r32 */
2891 emulate_1op("inc", c->dst, ctxt->eflags);
2892 break;
2893 case 0x48 ... 0x4f: /* dec r16/r32 */
2894 emulate_1op("dec", c->dst, ctxt->eflags);
2895 break;
33615aa9
AK		 2896 case 0x58 ... 0x5f: /* pop reg */
2897 pop_instruction:
350f69dc 2898 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2899 if (rc != X86EMUL_CONTINUE)
33615aa9 2900 goto done;
33615aa9 2901 break;
abcf14b5 2902 case 0x60: /* pusha */
c37eda13
WY		 2903 rc = emulate_pusha(ctxt, ops);
2904 if (rc != X86EMUL_CONTINUE)
2905 goto done;
abcf14b5
MG		 2906 break;
2907 case 0x61: /* popa */
2908 rc = emulate_popa(ctxt, ops);
1b30eaa8 2909 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2910 goto done;
2911 break;
6aa8b732 2912 case 0x63: /* movsxd */
8b4caf66 2913 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2914 goto cannot_emulate;
e4e03ded 2915 c->dst.val = (s32) c->src.val;
6aa8b732 2916 break;
018a98db
AK		 2917 case 0x6c: /* insb */
2918 case 0x6d: /* insw/insd */
a13a63fa
WY		 2919 c->src.val = c->regs[VCPU_REGS_RDX];
2920 goto do_io_in;
018a98db
AK		 2921 case 0x6e: /* outsb */
2922 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 2923 c->dst.val = c->regs[VCPU_REGS_RDX];
2924 goto do_io_out;
7972995b 2925 break;
b2833e3c 2926 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2927 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2928 jmp_rel(c, c->src.val);
018a98db 2929 break;
6aa8b732 2930 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2931 switch (c->modrm_reg) {
6aa8b732
AK		 2932 case 0:
2933 goto add;
2934 case 1:
2935 goto or;
2936 case 2:
2937 goto adc;
2938 case 3:
2939 goto sbb;
2940 case 4:
2941 goto and;
2942 case 5:
2943 goto sub;
2944 case 6:
2945 goto xor;
2946 case 7:
2947 goto cmp;
2948 }
2949 break;
2950 case 0x84 ... 0x85:
dfb507c4 2951 test:
05f086f8 2952 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2953 break;
2954 case 0x86 ... 0x87: /* xchg */
b13354f8 2955 xchg:
6aa8b732 2956 /* Write back the register source. */
31be40b3
WY		 2957 c->src.val = c->dst.val;
2958 write_register_operand(&c->src);
6aa8b732
AK		 2959 /*
2960 * Write back the memory destination with implicit LOCK
2961 * prefix.
2962 */
31be40b3 2963 c->dst.val = c->src.orig_val;
e4e03ded 2964 c->lock_prefix = 1;
6aa8b732 2965 break;
6aa8b732 2966 case 0x88 ... 0x8b: /* mov */
7de75248 2967 goto mov;
79168fd1
GN		 2968 case 0x8c: /* mov r/m, sreg */
2969 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2970 emulate_ud(ctxt);
5e3ae6c5 2971 goto done;
38d5bc6d 2972 }
79168fd1 2973 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2974 break;
7e0b54b1 2975 case 0x8d: /* lea r16/r32, m */
342fc630 2976 c->dst.val = c->src.addr.mem;
7e0b54b1 2977 break;
4257198a
GT		 2978 case 0x8e: { /* mov seg, r/m16 */
2979 uint16_t sel;
4257198a
GT		 2980
2981 sel = c->src.val;
8b9f4414 2982
c697518a
GN		 2983 if (c->modrm_reg == VCPU_SREG_CS ||
2984 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2985 emulate_ud(ctxt);
8b9f4414
GN		 2986 goto done;
2987 }
2988
310b5d30 2989 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2990 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2991
2e873022 2992 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2993
2994 c->dst.type = OP_NONE; /* Disable writeback. */
2995 break;
2996 }
6aa8b732 2997 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2998 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2999 if (rc != X86EMUL_CONTINUE)
6aa8b732 3000 goto done;
6aa8b732 3001 break;
3d9e77df
AK		 3002 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3003 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3004 break;
b13354f8 3005 goto xchg;
e8b6fa70
WY		 3006 case 0x98: /* cbw/cwde/cdqe */
3007 switch (c->op_bytes) {
3008 case 2: c->dst.val = (s8)c->dst.val; break;
3009 case 4: c->dst.val = (s16)c->dst.val; break;
3010 case 8: c->dst.val = (s32)c->dst.val; break;
3011 }
3012 break;
fd2a7608 3013 case 0x9c: /* pushf */
05f086f8 3014 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3015 emulate_push(ctxt, ops);
8cdbd2c9 3016 break;
535eabcf 3017 case 0x9d: /* popf */
2b48cc75 3018 c->dst.type = OP_REG;
1a6440ae 3019 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3020 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 3021 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3022 if (rc != X86EMUL_CONTINUE)
3023 goto done;
3024 break;
5d55f299 3025 case 0xa0 ... 0xa3: /* mov */
6aa8b732 3026 case 0xa4 ... 0xa5: /* movs */
a682e354 3027 goto mov;
6aa8b732 3028 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3029 c->dst.type = OP_NONE; /* Disable writeback. */
1a6440ae 3030 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
a682e354 3031 goto cmp;
dfb507c4
MG		 3032 case 0xa8 ... 0xa9: /* test ax, imm */
3033 goto test;
6aa8b732 3034 case 0xaa ... 0xab: /* stos */
6aa8b732 3035 case 0xac ... 0xad: /* lods */
a682e354 3036 goto mov;
6aa8b732 3037 case 0xae ... 0xaf: /* scas */
f6b33fc5 3038 goto cmp;
a5e2e82b 3039 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 3040 goto mov;
018a98db
AK		 3041 case 0xc0 ... 0xc1:
3042 emulate_grp2(ctxt);
3043 break;
111de5d6 3044 case 0xc3: /* ret */
cf5de4f8 3045 c->dst.type = OP_REG;
1a6440ae 3046 c->dst.addr.reg = &c->eip;
cf5de4f8 3047 c->dst.bytes = c->op_bytes;
111de5d6 3048 goto pop_instruction;
018a98db
AK		 3049 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3050 mov:
3051 c->dst.val = c->src.val;
3052 break;
a77ab5ea
AK		 3053 case 0xcb: /* ret far */
3054 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 3055 if (rc != X86EMUL_CONTINUE)
3056 goto done;
3057 break;
6e154e56
MG		 3058 case 0xcc: /* int3 */
3059 irq = 3;
3060 goto do_interrupt;
3061 case 0xcd: /* int n */
3062 irq = c->src.val;
3063 do_interrupt:
3064 rc = emulate_int(ctxt, ops, irq);
3065 if (rc != X86EMUL_CONTINUE)
3066 goto done;
3067 break;
3068 case 0xce: /* into */
3069 if (ctxt->eflags & EFLG_OF) {
3070 irq = 4;
3071 goto do_interrupt;
3072 }
3073 break;
62bd430e
MG		 3074 case 0xcf: /* iret */
3075 rc = emulate_iret(ctxt, ops);
3076
1b30eaa8 3077 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 3078 goto done;
3079 break;
018a98db 3080 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3081 emulate_grp2(ctxt);
3082 break;
3083 case 0xd2 ... 0xd3: /* Grp2 */
3084 c->src.val = c->regs[VCPU_REGS_RCX];
3085 emulate_grp2(ctxt);
3086 break;
f2f31845
WY		 3087 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3088 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3089 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3090 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3091 jmp_rel(c, c->src.val);
3092 break;
a6a3034c
MG		 3093 case 0xe4: /* inb */
3094 case 0xe5: /* in */
cf8f70bf 3095 goto do_io_in;
a6a3034c
MG		 3096 case 0xe6: /* outb */
3097 case 0xe7: /* out */
cf8f70bf 3098 goto do_io_out;
1a52e051 3099 case 0xe8: /* call (near) */ {
d53c4777 3100 long int rel = c->src.val;
e4e03ded 3101 c->src.val = (unsigned long) c->eip;
7a957275 3102 jmp_rel(c, rel);
79168fd1 3103 emulate_push(ctxt, ops);
8cdbd2c9 3104 break;
1a52e051
NK		 3105 }
3106 case 0xe9: /* jmp rel */
954cd36f 3107 goto jmp;
414e6277
GN		 3108 case 0xea: { /* jmp far */
3109 unsigned short sel;
ea79849d 3110 jump_far:
414e6277
GN		 3111 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3112
3113 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3114 goto done;
954cd36f 3115
414e6277
GN		 3116 c->eip = 0;
3117 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3118 break;
414e6277 3119 }
954cd36f
GT		 3120 case 0xeb:
3121 jmp: /* jmp rel short */
7a957275 3122 jmp_rel(c, c->src.val);
a01af5ec 3123 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3124 break;
a6a3034c
MG		 3125 case 0xec: /* in al,dx */
3126 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3127 c->src.val = c->regs[VCPU_REGS_RDX];
3128 do_io_in:
3129 c->dst.bytes = min(c->dst.bytes, 4u);
3130 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3131 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3132 goto done;
3133 }
7b262e90
GN		 3134 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3135 &c->dst.val))
cf8f70bf
GN		 3136 goto done; /* IO is needed */
3137 break;
ce7a0ad3
WY		 3138 case 0xee: /* out dx,al */
3139 case 0xef: /* out dx,(e/r)ax */
41167be5 3140 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3141 do_io_out:
41167be5
WY		 3142 c->src.bytes = min(c->src.bytes, 4u);
3143 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3144 c->src.bytes)) {
54b8486f 3145 emulate_gp(ctxt, 0);
f850e2e6
GN		 3146 goto done;
3147 }
41167be5
WY		 3148 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3149 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3150 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3151 break;
111de5d6 3152 case 0xf4: /* hlt */
ad312c7c 3153 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3154 break;
111de5d6
AK		 3155 case 0xf5: /* cmc */
3156 /* complement carry flag from eflags reg */
3157 ctxt->eflags ^= EFLG_CF;
111de5d6 3158 break;
018a98db 3159 case 0xf6 ... 0xf7: /* Grp3 */
8c5eee30 3160 if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
aca06a83 3161 goto cannot_emulate;
018a98db 3162 break;
111de5d6
AK		 3163 case 0xf8: /* clc */
3164 ctxt->eflags &= ~EFLG_CF;
111de5d6 3165 break;
8744aa9a
MG		 3166 case 0xf9: /* stc */
3167 ctxt->eflags |= EFLG_CF;
3168 break;
111de5d6 3169 case 0xfa: /* cli */
07cbc6c1 3170 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3171 emulate_gp(ctxt, 0);
07cbc6c1 3172 goto done;
36089fed 3173 } else
f850e2e6 3174 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3175 break;
3176 case 0xfb: /* sti */
07cbc6c1 3177 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3178 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3179 goto done;
3180 } else {
95cb2295 3181 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3182 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3183 }
111de5d6 3184 break;
fb4616f4
MG		 3185 case 0xfc: /* cld */
3186 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3187 break;
3188 case 0xfd: /* std */
3189 ctxt->eflags |= EFLG_DF;
fb4616f4 3190 break;
ea79849d
GN		 3191 case 0xfe: /* Grp4 */
3192 grp45:
018a98db 3193 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3194 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3195 goto done;
3196 break;
ea79849d
GN		 3197 case 0xff: /* Grp5 */
3198 if (c->modrm_reg == 5)
3199 goto jump_far;
3200 goto grp45;
91269b8f
AK		 3201 default:
3202 goto cannot_emulate;
6aa8b732 3203 }
018a98db
AK		 3204
3205writeback:
3206 rc = writeback(ctxt, ops);
1b30eaa8 3207 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3208 goto done;
3209
5cd21917
GN		 3210 /*
3211 * restore dst type in case the decoding will be reused
3212 * (happens for string instruction )
3213 */
3214 c->dst.type = saved_dst_type;
3215
a682e354 3216 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3217 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3218 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3219
3220 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3221 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3222 &c->dst);
d9271123 3223
5cd21917 3224 if (c->rep_prefix && (c->d & String)) {
7b262e90 3225 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3226 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
0fa6ccbd
AK		 3227 /* The second termination condition only applies for REPE
3228 * and REPNE. Test if the repeat string operation prefix is
3229 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3230 * corresponding termination condition according to:
3231 * - if REPE/REPZ and ZF = 0 then done
3232 * - if REPNE/REPNZ and ZF = 1 then done
3233 */
3234 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3235 (c->b == 0xae) || (c->b == 0xaf))
3236 && (((c->rep_prefix == REPE_PREFIX) &&
3237 ((ctxt->eflags & EFLG_ZF) == 0))
3238 || ((c->rep_prefix == REPNE_PREFIX) &&
3239 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3240 ctxt->restart = false;
7b262e90
GN		 3241 /*
3242 * Re-enter guest when pio read ahead buffer is empty or,
3243 * if it is not used, after each 1024 iteration.
3244 */
0fa6ccbd
AK		 3245 else if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3246 (rc->end != 0 && rc->end == rc->pos)) {
5cd21917 3247 ctxt->restart = false;
0fa6ccbd
AK		 3248 c->eip = ctxt->eip;
3249 }
5cd21917 3250 }
9de41573
GN		 3251 /*
3252 * reset read cache here in case string instruction is restared
3253 * without decoding
3254 */
3255 ctxt->decode.mem_read.end = 0;
0fa6ccbd
AK		 3256 if (!ctxt->restart)
3257 ctxt->eip = c->eip;
018a98db
AK		 3258
3259done:
cb404fe0 3260 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3261
3262twobyte_insn:
e4e03ded 3263 switch (c->b) {
6aa8b732 3264 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3265 switch (c->modrm_reg) {
6aa8b732
AK		 3266 u16 size;
3267 unsigned long address;
3268
aca7f966 3269 case 0: /* vmcall */
e4e03ded 3270 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3271 goto cannot_emulate;
3272
7aa81cc0 3273 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3274 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3275 goto done;
3276
33e3885d 3277 /* Let the processor re-execute the fixed hypercall */
063db061 3278 c->eip = ctxt->eip;
16286d08
AK		 3279 /* Disable writeback. */
3280 c->dst.type = OP_NONE;
aca7f966 3281 break;
6aa8b732 3282 case 2: /* lgdt */
1a6440ae 3283 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3284 &size, &address, c->op_bytes);
1b30eaa8 3285 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3286 goto done;
3287 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3288 /* Disable writeback. */
3289 c->dst.type = OP_NONE;
6aa8b732 3290 break;
aca7f966 3291 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3292 if (c->modrm_mod == 3) {
3293 switch (c->modrm_rm) {
3294 case 1:
3295 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3296 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3297 goto done;
3298 break;
3299 default:
3300 goto cannot_emulate;
3301 }
aca7f966 3302 } else {
1a6440ae 3303 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3304 &size, &address,
e4e03ded 3305 c->op_bytes);
1b30eaa8 3306 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3307 goto done;
3308 realmode_lidt(ctxt->vcpu, size, address);
3309 }
16286d08
AK		 3310 /* Disable writeback. */
3311 c->dst.type = OP_NONE;
6aa8b732
AK		 3312 break;
3313 case 4: /* smsw */
16286d08 3314 c->dst.bytes = 2;
52a46617 3315 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3316 break;
3317 case 6: /* lmsw */
9928ff60 3318 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3319 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3320 c->dst.type = OP_NONE;
6aa8b732 3321 break;
6e1e5ffe 3322 case 5: /* not defined */
54b8486f 3323 emulate_ud(ctxt);
6e1e5ffe 3324 goto done;
6aa8b732 3325 case 7: /* invlpg*/
1f6f0580 3326 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
16286d08
AK		 3327 /* Disable writeback. */
3328 c->dst.type = OP_NONE;
6aa8b732
AK		 3329 break;
3330 default:
3331 goto cannot_emulate;
3332 }
3333 break;
e99f0507 3334 case 0x05: /* syscall */
3fb1b5db 3335 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3336 if (rc != X86EMUL_CONTINUE)
3337 goto done;
e66bb2cc
AP		 3338 else
3339 goto writeback;
e99f0507 3340 break;
018a98db
AK		 3341 case 0x06:
3342 emulate_clts(ctxt->vcpu);
018a98db 3343 break;
018a98db 3344 case 0x09: /* wbinvd */
f5f48ee1 3345 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3346 break;
3347 case 0x08: /* invd */
018a98db
AK		 3348 case 0x0d: /* GrpP (prefetch) */
3349 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3350 break;
3351 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3352 switch (c->modrm_reg) {
3353 case 1:
3354 case 5 ... 7:
3355 case 9 ... 15:
54b8486f 3356 emulate_ud(ctxt);
6aebfa6e
GN		 3357 goto done;
3358 }
1a0c7d44 3359 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3360 break;
6aa8b732 3361 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3362 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3363 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3364 emulate_ud(ctxt);
1e470be5
GN		 3365 goto done;
3366 }
b27f3856 3367 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3368 break;
018a98db 3369 case 0x22: /* mov reg, cr */
1a0c7d44 3370 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3371 emulate_gp(ctxt, 0);
0f12244f
GN		 3372 goto done;
3373 }
018a98db
AK		 3374 c->dst.type = OP_NONE;
3375 break;
6aa8b732 3376 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3377 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3378 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3379 emulate_ud(ctxt);
1e470be5
GN		 3380 goto done;
3381 }
35aa5375 3382
b27f3856 3383 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3384 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3385 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3386 /* #UD condition is already handled by the code above */
54b8486f 3387 emulate_gp(ctxt, 0);
338dbc97
GN		 3388 goto done;
3389 }
3390
a01af5ec 3391 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3392 break;
018a98db
AK		 3393 case 0x30:
3394 /* wrmsr */
3395 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3396 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3397 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3398 emulate_gp(ctxt, 0);
fd525365 3399 goto done;
018a98db
AK		 3400 }
3401 rc = X86EMUL_CONTINUE;
018a98db
AK		 3402 break;
3403 case 0x32:
3404 /* rdmsr */
3fb1b5db 3405 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3406 emulate_gp(ctxt, 0);
fd525365 3407 goto done;
018a98db
AK		 3408 } else {
3409 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3410 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3411 }
3412 rc = X86EMUL_CONTINUE;
018a98db 3413 break;
e99f0507 3414 case 0x34: /* sysenter */
3fb1b5db 3415 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3416 if (rc != X86EMUL_CONTINUE)
3417 goto done;
8c604352
AP		 3418 else
3419 goto writeback;
e99f0507
AP		 3420 break;
3421 case 0x35: /* sysexit */
3fb1b5db 3422 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3423 if (rc != X86EMUL_CONTINUE)
3424 goto done;
4668f050
AP		 3425 else
3426 goto writeback;
e99f0507 3427 break;
6aa8b732 3428 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3429 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3430 if (!test_cc(c->b, ctxt->eflags))
3431 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3432 break;
b2833e3c 3433 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3434 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3435 jmp_rel(c, c->src.val);
018a98db 3436 break;
ee45b58e
WY		 3437 case 0x90 ... 0x9f: /* setcc r/m8 */
3438 c->dst.val = test_cc(c->b, ctxt->eflags);
3439 break;
0934ac9d 3440 case 0xa0: /* push fs */
79168fd1 3441 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3442 break;
3443 case 0xa1: /* pop fs */
3444 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3445 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3446 goto done;
3447 break;
7de75248
NK		 3448 case 0xa3:
3449 bt: /* bt */
e4f8e039 3450 c->dst.type = OP_NONE;
e4e03ded
LV		 3451 /* only subword offset */
3452 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3453 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3454 break;
9bf8ea42
GT		 3455 case 0xa4: /* shld imm8, r, r/m */
3456 case 0xa5: /* shld cl, r, r/m */
3457 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3458 break;
0934ac9d 3459 case 0xa8: /* push gs */
79168fd1 3460 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3461 break;
3462 case 0xa9: /* pop gs */
3463 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3464 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3465 goto done;
3466 break;
7de75248
NK		 3467 case 0xab:
3468 bts: /* bts */
05f086f8 3469 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3470 break;
9bf8ea42
GT		 3471 case 0xac: /* shrd imm8, r, r/m */
3472 case 0xad: /* shrd cl, r, r/m */
3473 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3474 break;
2a7c5b8b
GC		 3475 case 0xae: /* clflush */
3476 break;
6aa8b732
AK		 3477 case 0xb0 ... 0xb1: /* cmpxchg */
3478 /*
3479 * Save real source value, then compare EAX against
3480 * destination.
3481 */
e4e03ded
LV		 3482 c->src.orig_val = c->src.val;
3483 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3484 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3485 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3486 /* Success: write back to memory. */
e4e03ded 3487 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3488 } else {
3489 /* Failure: write the value we saw to EAX. */
e4e03ded 3490 c->dst.type = OP_REG;
1a6440ae 3491 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3492 }
3493 break;
6aa8b732
AK		 3494 case 0xb3:
3495 btr: /* btr */
05f086f8 3496 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3497 break;
6aa8b732 3498 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3499 c->dst.bytes = c->op_bytes;
3500 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3501 : (u16) c->src.val;
6aa8b732 3502 break;
6aa8b732 3503 case 0xba: /* Grp8 */
e4e03ded 3504 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3505 case 0:
3506 goto bt;
3507 case 1:
3508 goto bts;
3509 case 2:
3510 goto btr;
3511 case 3:
3512 goto btc;
3513 }
3514 break;
7de75248
NK		 3515 case 0xbb:
3516 btc: /* btc */
05f086f8 3517 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3518 break;
d9574a25
WY		 3519 case 0xbc: { /* bsf */
3520 u8 zf;
3521 __asm__ ("bsf %2, %0; setz %1"
3522 : "=r"(c->dst.val), "=q"(zf)
3523 : "r"(c->src.val));
3524 ctxt->eflags &= ~X86_EFLAGS_ZF;
3525 if (zf) {
3526 ctxt->eflags |= X86_EFLAGS_ZF;
3527 c->dst.type = OP_NONE; /* Disable writeback. */
3528 }
3529 break;
3530 }
3531 case 0xbd: { /* bsr */
3532 u8 zf;
3533 __asm__ ("bsr %2, %0; setz %1"
3534 : "=r"(c->dst.val), "=q"(zf)
3535 : "r"(c->src.val));
3536 ctxt->eflags &= ~X86_EFLAGS_ZF;
3537 if (zf) {
3538 ctxt->eflags |= X86_EFLAGS_ZF;
3539 c->dst.type = OP_NONE; /* Disable writeback. */
3540 }
3541 break;
3542 }
6aa8b732 3543 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3544 c->dst.bytes = c->op_bytes;
3545 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3546 (s16) c->src.val;
6aa8b732 3547 break;
92f738a5
WY		 3548 case 0xc0 ... 0xc1: /* xadd */
3549 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3550 /* Write back the register source. */
3551 c->src.val = c->dst.orig_val;
3552 write_register_operand(&c->src);
3553 break;
a012e65a 3554 case 0xc3: /* movnti */
e4e03ded
LV		 3555 c->dst.bytes = c->op_bytes;
3556 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3557 (u64) c->src.val;
a012e65a 3558 break;
6aa8b732 3559 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3560 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3561 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3562 goto done;
3563 break;
91269b8f
AK		 3564 default:
3565 goto cannot_emulate;
6aa8b732
AK		 3566 }
3567 goto writeback;
3568
3569cannot_emulate:
e4e03ded 3570 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3571 return -1;
3572}
Linux kernel - Deliverables
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