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KVM: x86: CMOV emulation on legacy mode is wrong
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 128#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 129#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 130/* Generic ModRM decode. */
131#define ModRM (1<<19)
132/* Destination is only written; never read. */
133#define Mov (1<<20)
d8769fed 134/* Misc flags */
8ea7d6ae 135#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 136#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 137#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 138#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 139#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 140#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 141#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 142#define No64 (1<<28)
d5ae7ce8 143#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 144#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 145/* Source 2 operand type */
0b789eee 146#define Src2Shift (31)
4dd6a57d 147#define Src2None (OpNone << Src2Shift)
ab2c5ce6 148#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 149#define Src2CL (OpCL << Src2Shift)
150#define Src2ImmByte (OpImmByte << Src2Shift)
151#define Src2One (OpOne << Src2Shift)
152#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 153#define Src2ES (OpES << Src2Shift)
154#define Src2CS (OpCS << Src2Shift)
155#define Src2SS (OpSS << Src2Shift)
156#define Src2DS (OpDS << Src2Shift)
157#define Src2FS (OpFS << Src2Shift)
158#define Src2GS (OpGS << Src2Shift)
4dd6a57d 159#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 160#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 161#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
162#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
163#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 164#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 165#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 166#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 167#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 168#define Intercept ((u64)1 << 48) /* Has valid intercept field */
169#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 170#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 171#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 172#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 173#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 174
820207c8 175#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 176
d0e53325
AK		 177#define X2(x...) x, x
178#define X3(x...) X2(x), x
179#define X4(x...) X2(x), X2(x)
180#define X5(x...) X4(x), x
181#define X6(x...) X4(x), X2(x)
182#define X7(x...) X4(x), X3(x)
183#define X8(x...) X4(x), X4(x)
184#define X16(x...) X8(x), X8(x)
83babbca 185
e28bbd44
AK		 186#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
187#define FASTOP_SIZE 8
188
189/*
190 * fastop functions have a special calling convention:
191 *
017da7b6
AK		 192 * dst: rax (in/out)
193 * src: rdx (in/out)
e28bbd44
AK		 194 * src2: rcx (in)
195 * flags: rflags (in/out)
b8c0b6ae 196 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 197 *
198 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
199 * different operand sizes can be reached by calculation, rather than a jump
200 * table (which would be bigger than the code).
201 *
202 * fastop functions are declared as taking a never-defined fastop parameter,
203 * so they can't be called from C directly.
204 */
205
206struct fastop;
207
d65b1dee 208struct opcode {
b1ea50b2
AK		 209 u64 flags : 56;
210 u64 intercept : 8;
120df890 211 union {
ef65c889 212 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 213 const struct opcode *group;
214 const struct group_dual *gdual;
215 const struct gprefix *gprefix;
045a282c 216 const struct escape *esc;
39f062ff 217 const struct instr_dual *idual;
2276b511 218 const struct mode_dual *mdual;
e28bbd44 219 void (*fastop)(struct fastop *fake);
120df890 220 } u;
d09beabd 221 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 222};
223
224struct group_dual {
225 struct opcode mod012[8];
226 struct opcode mod3[8];
d65b1dee
AK		 227};
228
0d7cdee8
AK		 229struct gprefix {
230 struct opcode pfx_no;
231 struct opcode pfx_66;
232 struct opcode pfx_f2;
233 struct opcode pfx_f3;
234};
235
045a282c
GN		 236struct escape {
237 struct opcode op[8];
238 struct opcode high[64];
239};
240
39f062ff
NA		 241struct instr_dual {
242 struct opcode mod012;
243 struct opcode mod3;
244};
245
2276b511
NA		 246struct mode_dual {
247 struct opcode mode32;
248 struct opcode mode64;
249};
250
6aa8b732 251/* EFLAGS bit definitions. */
d4c6a154
GN		 252#define EFLG_ID (1<<21)
253#define EFLG_VIP (1<<20)
254#define EFLG_VIF (1<<19)
255#define EFLG_AC (1<<18)
b1d86143
AP		 256#define EFLG_VM (1<<17)
257#define EFLG_RF (1<<16)
d4c6a154
GN		 258#define EFLG_IOPL (3<<12)
259#define EFLG_NT (1<<14)
6aa8b732
AK		 260#define EFLG_OF (1<<11)
261#define EFLG_DF (1<<10)
b1d86143 262#define EFLG_IF (1<<9)
d4c6a154 263#define EFLG_TF (1<<8)
6aa8b732
AK		 264#define EFLG_SF (1<<7)
265#define EFLG_ZF (1<<6)
266#define EFLG_AF (1<<4)
267#define EFLG_PF (1<<2)
268#define EFLG_CF (1<<0)
269
62bd430e
MG		 270#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
271#define EFLG_RESERVED_ONE_MASK 2
272
3dc4bc4f
NA		 273enum x86_transfer_type {
274 X86_TRANSFER_NONE,
275 X86_TRANSFER_CALL_JMP,
276 X86_TRANSFER_RET,
277 X86_TRANSFER_TASK_SWITCH,
278};
279
dd856efa
AK		 280static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
281{
282 if (!(ctxt->regs_valid & (1 << nr))) {
283 ctxt->regs_valid |= 1 << nr;
284 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
285 }
286 return ctxt->_regs[nr];
287}
288
289static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
290{
291 ctxt->regs_valid |= 1 << nr;
292 ctxt->regs_dirty |= 1 << nr;
293 return &ctxt->_regs[nr];
294}
295
296static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
297{
298 reg_read(ctxt, nr);
299 return reg_write(ctxt, nr);
300}
301
302static void writeback_registers(struct x86_emulate_ctxt *ctxt)
303{
304 unsigned reg;
305
306 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
307 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
308}
309
310static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
311{
312 ctxt->regs_dirty = 0;
313 ctxt->regs_valid = 0;
314}
315
6aa8b732
AK		 316/*
317 * These EFLAGS bits are restored from saved value during emulation, and
318 * any changes are written back to the saved value after emulation.
319 */
320#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
321
dda96d8f
AK		 322#ifdef CONFIG_X86_64
323#define ON64(x) x
324#else
325#define ON64(x)
326#endif
327
4d758349
AK		 328static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
329
b7d491e7
AK		 330#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
331#define FOP_RET "ret \n\t"
332
333#define FOP_START(op) \
334 extern void em_##op(struct fastop *fake); \
335 asm(".pushsection .text, \"ax\" \n\t" \
336 ".global em_" #op " \n\t" \
337 FOP_ALIGN \
338 "em_" #op ": \n\t"
339
340#define FOP_END \
341 ".popsection")
342
0bdea068
AK		 343#define FOPNOP() FOP_ALIGN FOP_RET
344
b7d491e7 345#define FOP1E(op, dst) \
b8c0b6ae
AK		 346 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
347
348#define FOP1EEX(op, dst) \
349 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 350
351#define FASTOP1(op) \
352 FOP_START(op) \
353 FOP1E(op##b, al) \
354 FOP1E(op##w, ax) \
355 FOP1E(op##l, eax) \
356 ON64(FOP1E(op##q, rax)) \
357 FOP_END
358
b9fa409b
AK		 359/* 1-operand, using src2 (for MUL/DIV r/m) */
360#define FASTOP1SRC2(op, name) \
361 FOP_START(name) \
362 FOP1E(op, cl) \
363 FOP1E(op, cx) \
364 FOP1E(op, ecx) \
365 ON64(FOP1E(op, rcx)) \
366 FOP_END
367
b8c0b6ae
AK		 368/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
369#define FASTOP1SRC2EX(op, name) \
370 FOP_START(name) \
371 FOP1EEX(op, cl) \
372 FOP1EEX(op, cx) \
373 FOP1EEX(op, ecx) \
374 ON64(FOP1EEX(op, rcx)) \
375 FOP_END
376
f7857f35
AK		 377#define FOP2E(op, dst, src) \
378 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
379
380#define FASTOP2(op) \
381 FOP_START(op) \
017da7b6
AK		 382 FOP2E(op##b, al, dl) \
383 FOP2E(op##w, ax, dx) \
384 FOP2E(op##l, eax, edx) \
385 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 386 FOP_END
387
11c363ba
AK		 388/* 2 operand, word only */
389#define FASTOP2W(op) \
390 FOP_START(op) \
391 FOPNOP() \
017da7b6
AK		 392 FOP2E(op##w, ax, dx) \
393 FOP2E(op##l, eax, edx) \
394 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 395 FOP_END
396
007a3b54
AK		 397/* 2 operand, src is CL */
398#define FASTOP2CL(op) \
399 FOP_START(op) \
400 FOP2E(op##b, al, cl) \
401 FOP2E(op##w, ax, cl) \
402 FOP2E(op##l, eax, cl) \
403 ON64(FOP2E(op##q, rax, cl)) \
404 FOP_END
405
5aca3722
NA		 406/* 2 operand, src and dest are reversed */
407#define FASTOP2R(op, name) \
408 FOP_START(name) \
409 FOP2E(op##b, dl, al) \
410 FOP2E(op##w, dx, ax) \
411 FOP2E(op##l, edx, eax) \
412 ON64(FOP2E(op##q, rdx, rax)) \
413 FOP_END
414
0bdea068
AK		 415#define FOP3E(op, dst, src, src2) \
416 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
417
418/* 3-operand, word-only, src2=cl */
419#define FASTOP3WCL(op) \
420 FOP_START(op) \
421 FOPNOP() \
017da7b6
AK		 422 FOP3E(op##w, ax, dx, cl) \
423 FOP3E(op##l, eax, edx, cl) \
424 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 425 FOP_END
426
9ae9feba
AK		 427/* Special case for SETcc - 1 instruction per cc */
428#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
429
b8c0b6ae
AK		 430asm(".global kvm_fastop_exception \n"
431 "kvm_fastop_exception: xor %esi, %esi; ret");
432
9ae9feba
AK		 433FOP_START(setcc)
434FOP_SETCC(seto)
435FOP_SETCC(setno)
436FOP_SETCC(setc)
437FOP_SETCC(setnc)
438FOP_SETCC(setz)
439FOP_SETCC(setnz)
440FOP_SETCC(setbe)
441FOP_SETCC(setnbe)
442FOP_SETCC(sets)
443FOP_SETCC(setns)
444FOP_SETCC(setp)
445FOP_SETCC(setnp)
446FOP_SETCC(setl)
447FOP_SETCC(setnl)
448FOP_SETCC(setle)
449FOP_SETCC(setnle)
450FOP_END;
451
326f578f
PB		 452FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
453FOP_END;
454
8a76d7f2
JR		 455static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
456 enum x86_intercept intercept,
457 enum x86_intercept_stage stage)
458{
459 struct x86_instruction_info info = {
460 .intercept = intercept,
9dac77fa
AK		 461 .rep_prefix = ctxt->rep_prefix,
462 .modrm_mod = ctxt->modrm_mod,
463 .modrm_reg = ctxt->modrm_reg,
464 .modrm_rm = ctxt->modrm_rm,
465 .src_val = ctxt->src.val64,
6cbc5f5a 466 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 467 .src_bytes = ctxt->src.bytes,
468 .dst_bytes = ctxt->dst.bytes,
469 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 470 .next_rip = ctxt->eip,
471 };
472
2953538e 473 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 474}
475
f47cfa31
AK		 476static void assign_masked(ulong *dest, ulong src, ulong mask)
477{
478 *dest = (*dest & ~mask) | (src & mask);
479}
480
9dac77fa 481static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 482{
9dac77fa 483 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 484}
485
f47cfa31
AK		 486static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
487{
488 u16 sel;
489 struct desc_struct ss;
490
491 if (ctxt->mode == X86EMUL_MODE_PROT64)
492 return ~0UL;
493 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
494 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
495}
496
612e89f0
AK		 497static int stack_size(struct x86_emulate_ctxt *ctxt)
498{
499 return (__fls(stack_mask(ctxt)) + 1) >> 3;
500}
501
6aa8b732 502/* Access/update address held in a register, based on addressing mode. */
e4706772 503static inline unsigned long
9dac77fa 504address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 505{
9dac77fa 506 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 507 return reg;
508 else
9dac77fa 509 return reg & ad_mask(ctxt);
e4706772
HH		 510}
511
512static inline unsigned long
01485a22 513register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 514{
01485a22 515 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 516}
517
5ad105e5
AK		 518static void masked_increment(ulong *reg, ulong mask, int inc)
519{
520 assign_masked(reg, *reg + inc, mask);
521}
522
7a957275 523static inline void
01485a22 524register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 525{
5ad105e5
AK		 526 ulong mask;
527
9dac77fa 528 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 529 mask = ~0UL;
7a957275 530 else
5ad105e5 531 mask = ad_mask(ctxt);
01485a22 532 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 533}
534
535static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
536{
dd856efa 537 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 538}
6aa8b732 539
56697687
AK		 540static u32 desc_limit_scaled(struct desc_struct *desc)
541{
542 u32 limit = get_desc_limit(desc);
543
544 return desc->g ? (limit << 12) | 0xfff : limit;
545}
546
7b105ca2 547static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 548{
549 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
550 return 0;
551
7b105ca2 552 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 553}
554
35d3d4a1
AK		 555static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
556 u32 error, bool valid)
54b8486f 557{
e0ad0b47 558 WARN_ON(vec > 0x1f);
da9cb575
AK		 559 ctxt->exception.vector = vec;
560 ctxt->exception.error_code = error;
561 ctxt->exception.error_code_valid = valid;
35d3d4a1 562 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 563}
564
3b88e41a
JR		 565static int emulate_db(struct x86_emulate_ctxt *ctxt)
566{
567 return emulate_exception(ctxt, DB_VECTOR, 0, false);
568}
569
35d3d4a1 570static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 571{
35d3d4a1 572 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 573}
574
618ff15d
AK		 575static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
576{
577 return emulate_exception(ctxt, SS_VECTOR, err, true);
578}
579
35d3d4a1 580static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 581{
35d3d4a1 582 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 583}
584
35d3d4a1 585static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 586{
35d3d4a1 587 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 588}
589
34d1f490
AK		 590static int emulate_de(struct x86_emulate_ctxt *ctxt)
591{
35d3d4a1 592 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 593}
594
1253791d
AK		 595static int emulate_nm(struct x86_emulate_ctxt *ctxt)
596{
597 return emulate_exception(ctxt, NM_VECTOR, 0, false);
598}
599
1aa36616
AK		 600static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
601{
602 u16 selector;
603 struct desc_struct desc;
604
605 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
606 return selector;
607}
608
609static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
610 unsigned seg)
611{
612 u16 dummy;
613 u32 base3;
614 struct desc_struct desc;
615
616 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
617 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
618}
619
1c11b376
AK		 620/*
621 * x86 defines three classes of vector instructions: explicitly
622 * aligned, explicitly unaligned, and the rest, which change behaviour
623 * depending on whether they're AVX encoded or not.
624 *
625 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
626 * subject to the same check.
627 */
628static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
629{
630 if (likely(size < 16))
631 return false;
632
633 if (ctxt->d & Aligned)
634 return true;
635 else if (ctxt->d & Unaligned)
636 return false;
637 else if (ctxt->d & Avx)
638 return false;
639 else
640 return true;
641}
642
d09155d2
PB		 643static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
644 struct segmented_address addr,
645 unsigned *max_size, unsigned size,
646 bool write, bool fetch,
d50eaa18 647 enum x86emul_mode mode, ulong *linear)
52fd8b44 648{
618ff15d
AK		 649 struct desc_struct desc;
650 bool usable;
52fd8b44 651 ulong la;
618ff15d 652 u32 lim;
1aa36616 653 u16 sel;
52fd8b44 654
7b105ca2 655 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 656 *max_size = 0;
d50eaa18 657 switch (mode) {
618ff15d 658 case X86EMUL_MODE_PROT64:
4be4de7e 659 if (is_noncanonical_address(la))
abc7d8a4 660 goto bad;
fd56e154
PB		 661
662 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
663 if (size > *max_size)
664 goto bad;
618ff15d
AK		 665 break;
666 default:
1aa36616
AK		 667 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
668 addr.seg);
618ff15d
AK		 669 if (!usable)
670 goto bad;
58b7825b
GN		 671 /* code segment in protected mode or read-only data segment */
672 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
673 || !(desc.type & 2)) && write)
618ff15d
AK		 674 goto bad;
675 /* unreadable code segment */
3d9b938e 676 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 677 goto bad;
678 lim = desc_limit_scaled(&desc);
997b0412 679 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 680 /* expand-down segment */
fd56e154 681 if (addr.ea <= lim)
618ff15d
AK		 682 goto bad;
683 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 684 }
997b0412
PB		 685 if (addr.ea > lim)
686 goto bad;
bac15531
NA		 687 if (lim == 0xffffffff)
688 *max_size = ~0u;
689 else {
690 *max_size = (u64)lim + 1 - addr.ea;
691 if (size > *max_size)
692 goto bad;
693 }
31ff6488 694 la &= (u32)-1;
618ff15d
AK		 695 break;
696 }
1c11b376
AK		 697 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
698 return emulate_gp(ctxt, 0);
52fd8b44
AK		 699 *linear = la;
700 return X86EMUL_CONTINUE;
618ff15d
AK		 701bad:
702 if (addr.seg == VCPU_SREG_SS)
3606189f 703 return emulate_ss(ctxt, 0);
618ff15d 704 else
3606189f 705 return emulate_gp(ctxt, 0);
52fd8b44
AK		 706}
707
3d9b938e
NE		 708static int linearize(struct x86_emulate_ctxt *ctxt,
709 struct segmented_address addr,
710 unsigned size, bool write,
711 ulong *linear)
712{
fd56e154 713 unsigned max_size;
d50eaa18
NA		 714 return __linearize(ctxt, addr, &max_size, size, write, false,
715 ctxt->mode, linear);
3d9b938e
NE		 716}
717
d50eaa18
NA		 718static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
719 enum x86emul_mode mode)
720{
721 ulong linear;
722 int rc;
723 unsigned max_size;
724 struct segmented_address addr = { .seg = VCPU_SREG_CS,
725 .ea = dst };
726
727 if (ctxt->op_bytes != sizeof(unsigned long))
728 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
729 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
730 if (rc == X86EMUL_CONTINUE)
731 ctxt->_eip = addr.ea;
732 return rc;
733}
734
735static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
736{
737 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 738}
739
d50eaa18
NA		 740static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
741 const struct desc_struct *cs_desc)
742{
743 enum x86emul_mode mode = ctxt->mode;
82268083 744 int rc;
d50eaa18
NA		 745
746#ifdef CONFIG_X86_64
82268083
NA		 747 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
748 if (cs_desc->l) {
749 u64 efer = 0;
d50eaa18 750
82268083
NA		 751 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
752 if (efer & EFER_LMA)
753 mode = X86EMUL_MODE_PROT64;
754 } else
755 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 756 }
757#endif
758 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
759 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 760 rc = assign_eip(ctxt, dst, mode);
761 if (rc == X86EMUL_CONTINUE)
762 ctxt->mode = mode;
763 return rc;
d50eaa18
NA		 764}
765
766static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
767{
768 return assign_eip_near(ctxt, ctxt->_eip + rel);
769}
3d9b938e 770
3ca3ac4d
AK		 771static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
772 struct segmented_address addr,
773 void *data,
774 unsigned size)
775{
9fa088f4
AK		 776 int rc;
777 ulong linear;
778
83b8795a 779 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 780 if (rc != X86EMUL_CONTINUE)
781 return rc;
0f65dd70 782 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 783}
784
807941b1 785/*
285ca9e9 786 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 787 * boundary if they are not in fetch_cache yet.
788 */
9506d57d 789static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 790{
62266869 791 int rc;
fd56e154 792 unsigned size, max_size;
285ca9e9 793 unsigned long linear;
17052f16 794 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 795 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 796 .ea = ctxt->eip + cur_size };
797
fd56e154
PB		 798 /*
799 * We do not know exactly how many bytes will be needed, and
800 * __linearize is expensive, so fetch as much as possible. We
801 * just have to avoid going beyond the 15 byte limit, the end
802 * of the segment, or the end of the page.
803 *
804 * __linearize is called with size 0 so that it does not do any
805 * boundary check itself. Instead, we use max_size to check
806 * against op_size.
807 */
d50eaa18
NA		 808 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
809 &linear);
719d5a9b
PB		 810 if (unlikely(rc != X86EMUL_CONTINUE))
811 return rc;
812
fd56e154 813 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 814 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 815
816 /*
817 * One instruction can only straddle two pages,
818 * and one has been loaded at the beginning of
819 * x86_decode_insn. So, if not enough bytes
820 * still, we must have hit the 15-byte boundary.
821 */
822 if (unlikely(size < op_size))
fd56e154
PB		 823 return emulate_gp(ctxt, 0);
824
17052f16 825 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 826 size, &ctxt->exception);
827 if (unlikely(rc != X86EMUL_CONTINUE))
828 return rc;
17052f16 829 ctxt->fetch.end += size;
3e2815e9 830 return X86EMUL_CONTINUE;
62266869
AK		 831}
832
9506d57d
PB		 833static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
834 unsigned size)
62266869 835{
08da44ae
NA		 836 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
837
838 if (unlikely(done_size < size))
839 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 840 else
841 return X86EMUL_CONTINUE;
62266869
AK		 842}
843
67cbc90d 844/* Fetch next part of the instruction being emulated. */
e85a1085 845#define insn_fetch(_type, _ctxt) \
9506d57d 846({ _type _x; \
9506d57d
PB		 847 \
848 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 849 if (rc != X86EMUL_CONTINUE) \
850 goto done; \
9506d57d 851 ctxt->_eip += sizeof(_type); \
17052f16
PB		 852 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
853 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 854 _x; \
67cbc90d
TY		 855})
856
807941b1 857#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 858({ \
9506d57d 859 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 860 if (rc != X86EMUL_CONTINUE) \
861 goto done; \
9506d57d 862 ctxt->_eip += (_size); \
17052f16
PB		 863 memcpy(_arr, ctxt->fetch.ptr, _size); \
864 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 865})
866
1e3c5cb0
RR		 867/*
868 * Given the 'reg' portion of a ModRM byte, and a register block, return a
869 * pointer into the block that addresses the relevant register.
870 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
871 */
dd856efa 872static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 873 int byteop)
6aa8b732
AK		 874{
875 void *p;
aa9ac1a6 876 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 877
6aa8b732 878 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 879 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
880 else
881 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 882 return p;
883}
884
885static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 886 struct segmented_address addr,
6aa8b732
AK		 887 u16 *size, unsigned long *address, int op_bytes)
888{
889 int rc;
890
891 if (op_bytes == 2)
892 op_bytes = 3;
893 *address = 0;
3ca3ac4d 894 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 895 if (rc != X86EMUL_CONTINUE)
6aa8b732 896 return rc;
30b31ab6 897 addr.ea += 2;
3ca3ac4d 898 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 899 return rc;
900}
901
34b77652
AK		 902FASTOP2(add);
903FASTOP2(or);
904FASTOP2(adc);
905FASTOP2(sbb);
906FASTOP2(and);
907FASTOP2(sub);
908FASTOP2(xor);
909FASTOP2(cmp);
910FASTOP2(test);
911
b9fa409b
AK		 912FASTOP1SRC2(mul, mul_ex);
913FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 914FASTOP1SRC2EX(div, div_ex);
915FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 916
34b77652
AK		 917FASTOP3WCL(shld);
918FASTOP3WCL(shrd);
919
920FASTOP2W(imul);
921
922FASTOP1(not);
923FASTOP1(neg);
924FASTOP1(inc);
925FASTOP1(dec);
926
927FASTOP2CL(rol);
928FASTOP2CL(ror);
929FASTOP2CL(rcl);
930FASTOP2CL(rcr);
931FASTOP2CL(shl);
932FASTOP2CL(shr);
933FASTOP2CL(sar);
934
935FASTOP2W(bsf);
936FASTOP2W(bsr);
937FASTOP2W(bt);
938FASTOP2W(bts);
939FASTOP2W(btr);
940FASTOP2W(btc);
941
e47a5f5f
AK		 942FASTOP2(xadd);
943
5aca3722
NA		 944FASTOP2R(cmp, cmp_r);
945
9ae9feba 946static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 947{
9ae9feba
AK		 948 u8 rc;
949 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 950
9ae9feba 951 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 952 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 953 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
954 return rc;
bbe9abbd
NK		 955}
956
91ff3cb4
AK		 957static void fetch_register_operand(struct operand *op)
958{
959 switch (op->bytes) {
960 case 1:
961 op->val = *(u8 *)op->addr.reg;
962 break;
963 case 2:
964 op->val = *(u16 *)op->addr.reg;
965 break;
966 case 4:
967 op->val = *(u32 *)op->addr.reg;
968 break;
969 case 8:
970 op->val = *(u64 *)op->addr.reg;
971 break;
972 }
973}
974
1253791d
AK		 975static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
976{
977 ctxt->ops->get_fpu(ctxt);
978 switch (reg) {
89a87c67
MK		 979 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
980 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
981 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
982 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
983 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
984 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
985 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
986 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 987#ifdef CONFIG_X86_64
89a87c67
MK		 988 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
989 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
990 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
991 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
992 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
993 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
994 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
995 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 996#endif
997 default: BUG();
998 }
999 ctxt->ops->put_fpu(ctxt);
1000}
1001
1002static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1003 int reg)
1004{
1005 ctxt->ops->get_fpu(ctxt);
1006 switch (reg) {
89a87c67
MK		 1007 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1008 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1009 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1010 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1011 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1012 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1013 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1014 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1015#ifdef CONFIG_X86_64
89a87c67
MK		 1016 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1017 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1018 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1019 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1020 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1021 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1022 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1023 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1024#endif
1025 default: BUG();
1026 }
1027 ctxt->ops->put_fpu(ctxt);
1028}
1029
cbe2c9d3
AK		 1030static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1031{
1032 ctxt->ops->get_fpu(ctxt);
1033 switch (reg) {
1034 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1035 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1036 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1037 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1038 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1039 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1040 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1041 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1042 default: BUG();
1043 }
1044 ctxt->ops->put_fpu(ctxt);
1045}
1046
1047static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1048{
1049 ctxt->ops->get_fpu(ctxt);
1050 switch (reg) {
1051 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1052 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1053 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1054 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1055 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1056 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1057 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1058 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1059 default: BUG();
1060 }
1061 ctxt->ops->put_fpu(ctxt);
1062}
1063
045a282c
GN		 1064static int em_fninit(struct x86_emulate_ctxt *ctxt)
1065{
1066 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1067 return emulate_nm(ctxt);
1068
1069 ctxt->ops->get_fpu(ctxt);
1070 asm volatile("fninit");
1071 ctxt->ops->put_fpu(ctxt);
1072 return X86EMUL_CONTINUE;
1073}
1074
1075static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1076{
1077 u16 fcw;
1078
1079 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1080 return emulate_nm(ctxt);
1081
1082 ctxt->ops->get_fpu(ctxt);
1083 asm volatile("fnstcw %0": "+m"(fcw));
1084 ctxt->ops->put_fpu(ctxt);
1085
045a282c
GN		 1086 ctxt->dst.val = fcw;
1087
1088 return X86EMUL_CONTINUE;
1089}
1090
1091static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1092{
1093 u16 fsw;
1094
1095 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1096 return emulate_nm(ctxt);
1097
1098 ctxt->ops->get_fpu(ctxt);
1099 asm volatile("fnstsw %0": "+m"(fsw));
1100 ctxt->ops->put_fpu(ctxt);
1101
045a282c
GN		 1102 ctxt->dst.val = fsw;
1103
1104 return X86EMUL_CONTINUE;
1105}
1106
1253791d 1107static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1108 struct operand *op)
3c118e24 1109{
9dac77fa 1110 unsigned reg = ctxt->modrm_reg;
33615aa9 1111
9dac77fa
AK		 1112 if (!(ctxt->d & ModRM))
1113 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1114
9dac77fa 1115 if (ctxt->d & Sse) {
1253791d
AK		 1116 op->type = OP_XMM;
1117 op->bytes = 16;
1118 op->addr.xmm = reg;
1119 read_sse_reg(ctxt, &op->vec_val, reg);
1120 return;
1121 }
cbe2c9d3
AK		 1122 if (ctxt->d & Mmx) {
1123 reg &= 7;
1124 op->type = OP_MM;
1125 op->bytes = 8;
1126 op->addr.mm = reg;
1127 return;
1128 }
1253791d 1129
3c118e24 1130 op->type = OP_REG;
6d4d85ec
GN		 1131 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1132 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1133
91ff3cb4 1134 fetch_register_operand(op);
3c118e24
AK		 1135 op->orig_val = op->val;
1136}
1137
a6e3407b
AK		 1138static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1139{
1140 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1141 ctxt->modrm_seg = VCPU_SREG_SS;
1142}
1143
1c73ef66 1144static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1145 struct operand *op)
1c73ef66 1146{
1c73ef66 1147 u8 sib;
02357bdc 1148 int index_reg, base_reg, scale;
3e2815e9 1149 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1150 ulong modrm_ea = 0;
1c73ef66 1151
02357bdc
BD		 1152 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1153 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1154 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1155
02357bdc 1156 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1157 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1158 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1159 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1160
9b88ae99 1161 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1162 op->type = OP_REG;
9dac77fa 1163 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1164 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1165 ctxt->d & ByteOp);
9dac77fa 1166 if (ctxt->d & Sse) {
1253791d
AK		 1167 op->type = OP_XMM;
1168 op->bytes = 16;
9dac77fa
AK		 1169 op->addr.xmm = ctxt->modrm_rm;
1170 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1171 return rc;
1172 }
cbe2c9d3
AK		 1173 if (ctxt->d & Mmx) {
1174 op->type = OP_MM;
1175 op->bytes = 8;
bdc90722 1176 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1177 return rc;
1178 }
2dbd0dd7 1179 fetch_register_operand(op);
1c73ef66
AK		 1180 return rc;
1181 }
1182
2dbd0dd7
AK		 1183 op->type = OP_MEM;
1184
9dac77fa 1185 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1186 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1187 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1188 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1189 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1190
1191 /* 16-bit ModR/M decode. */
9dac77fa 1192 switch (ctxt->modrm_mod) {
1c73ef66 1193 case 0:
9dac77fa 1194 if (ctxt->modrm_rm == 6)
e85a1085 1195 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1196 break;
1197 case 1:
e85a1085 1198 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1199 break;
1200 case 2:
e85a1085 1201 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1202 break;
1203 }
9dac77fa 1204 switch (ctxt->modrm_rm) {
1c73ef66 1205 case 0:
2dbd0dd7 1206 modrm_ea += bx + si;
1c73ef66
AK		 1207 break;
1208 case 1:
2dbd0dd7 1209 modrm_ea += bx + di;
1c73ef66
AK		 1210 break;
1211 case 2:
2dbd0dd7 1212 modrm_ea += bp + si;
1c73ef66
AK		 1213 break;
1214 case 3:
2dbd0dd7 1215 modrm_ea += bp + di;
1c73ef66
AK		 1216 break;
1217 case 4:
2dbd0dd7 1218 modrm_ea += si;
1c73ef66
AK		 1219 break;
1220 case 5:
2dbd0dd7 1221 modrm_ea += di;
1c73ef66
AK		 1222 break;
1223 case 6:
9dac77fa 1224 if (ctxt->modrm_mod != 0)
2dbd0dd7 1225 modrm_ea += bp;
1c73ef66
AK		 1226 break;
1227 case 7:
2dbd0dd7 1228 modrm_ea += bx;
1c73ef66
AK		 1229 break;
1230 }
9dac77fa
AK		 1231 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1232 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1233 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1234 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1235 } else {
1236 /* 32/64-bit ModR/M decode. */
9dac77fa 1237 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1238 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1239 index_reg |= (sib >> 3) & 7;
1240 base_reg |= sib & 7;
1241 scale = sib >> 6;
1242
9dac77fa 1243 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1244 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1245 else {
dd856efa 1246 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1247 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1248 /* Increment ESP on POP [ESP] */
1249 if ((ctxt->d & IncSP) &&
1250 base_reg == VCPU_REGS_RSP)
1251 modrm_ea += ctxt->op_bytes;
a6e3407b 1252 }
dc71d0f1 1253 if (index_reg != 4)
dd856efa 1254 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1255 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1256 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1257 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1258 ctxt->rip_relative = 1;
a6e3407b
AK		 1259 } else {
1260 base_reg = ctxt->modrm_rm;
dd856efa 1261 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1262 adjust_modrm_seg(ctxt, base_reg);
1263 }
9dac77fa 1264 switch (ctxt->modrm_mod) {
1c73ef66 1265 case 1:
e85a1085 1266 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1267 break;
1268 case 2:
e85a1085 1269 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1270 break;
1271 }
1272 }
90de84f5 1273 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1274 if (ctxt->ad_bytes != 8)
1275 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1276
1c73ef66
AK		 1277done:
1278 return rc;
1279}
1280
1281static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1282 struct operand *op)
1c73ef66 1283{
3e2815e9 1284 int rc = X86EMUL_CONTINUE;
1c73ef66 1285
2dbd0dd7 1286 op->type = OP_MEM;
9dac77fa 1287 switch (ctxt->ad_bytes) {
1c73ef66 1288 case 2:
e85a1085 1289 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1290 break;
1291 case 4:
e85a1085 1292 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1293 break;
1294 case 8:
e85a1085 1295 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1296 break;
1297 }
1298done:
1299 return rc;
1300}
1301
9dac77fa 1302static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1303{
7129eeca 1304 long sv = 0, mask;
35c843c4 1305
9dac77fa 1306 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1307 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1308
9dac77fa
AK		 1309 if (ctxt->src.bytes == 2)
1310 sv = (s16)ctxt->src.val & (s16)mask;
1311 else if (ctxt->src.bytes == 4)
1312 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1313 else
1314 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1315
1c1c35ae
NA		 1316 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1317 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1318 }
ba7ff2b7
WY		 1319
1320 /* only subword offset */
9dac77fa 1321 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1322}
1323
dde7e6d1 1324static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1325 unsigned long addr, void *dest, unsigned size)
6aa8b732 1326{
dde7e6d1 1327 int rc;
9dac77fa 1328 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1329
f23b070e
XG		 1330 if (mc->pos < mc->end)
1331 goto read_cached;
6aa8b732 1332
f23b070e
XG		 1333 WARN_ON((mc->end + size) >= sizeof(mc->data));
1334
1335 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1336 &ctxt->exception);
1337 if (rc != X86EMUL_CONTINUE)
1338 return rc;
1339
1340 mc->end += size;
1341
1342read_cached:
1343 memcpy(dest, mc->data + mc->pos, size);
1344 mc->pos += size;
dde7e6d1
AK		 1345 return X86EMUL_CONTINUE;
1346}
6aa8b732 1347
3ca3ac4d
AK		 1348static int segmented_read(struct x86_emulate_ctxt *ctxt,
1349 struct segmented_address addr,
1350 void *data,
1351 unsigned size)
1352{
9fa088f4
AK		 1353 int rc;
1354 ulong linear;
1355
83b8795a 1356 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
7b105ca2 1359 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1360}
1361
1362static int segmented_write(struct x86_emulate_ctxt *ctxt,
1363 struct segmented_address addr,
1364 const void *data,
1365 unsigned size)
1366{
9fa088f4
AK		 1367 int rc;
1368 ulong linear;
1369
83b8795a 1370 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1371 if (rc != X86EMUL_CONTINUE)
1372 return rc;
0f65dd70
AK		 1373 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1374 &ctxt->exception);
3ca3ac4d
AK		 1375}
1376
1377static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1378 struct segmented_address addr,
1379 const void *orig_data, const void *data,
1380 unsigned size)
1381{
9fa088f4
AK		 1382 int rc;
1383 ulong linear;
1384
83b8795a 1385 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1386 if (rc != X86EMUL_CONTINUE)
1387 return rc;
0f65dd70
AK		 1388 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1389 size, &ctxt->exception);
3ca3ac4d
AK		 1390}
1391
dde7e6d1 1392static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1393 unsigned int size, unsigned short port,
1394 void *dest)
1395{
9dac77fa 1396 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1397
dde7e6d1 1398 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1399 unsigned int in_page, n;
9dac77fa 1400 unsigned int count = ctxt->rep_prefix ?
dd856efa 1401 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1402 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1403 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1404 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1405 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1406 if (n == 0)
1407 n = 1;
1408 rc->pos = rc->end = 0;
7b105ca2 1409 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1410 return 0;
1411 rc->end = n * size;
6aa8b732
AK		 1412 }
1413
e6e39f04
NA		 1414 if (ctxt->rep_prefix && (ctxt->d & String) &&
1415 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1416 ctxt->dst.data = rc->data + rc->pos;
1417 ctxt->dst.type = OP_MEM_STR;
1418 ctxt->dst.count = (rc->end - rc->pos) / size;
1419 rc->pos = rc->end;
1420 } else {
1421 memcpy(dest, rc->data + rc->pos, size);
1422 rc->pos += size;
1423 }
dde7e6d1
AK		 1424 return 1;
1425}
6aa8b732 1426
7f3d35fd
KW		 1427static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1428 u16 index, struct desc_struct *desc)
1429{
1430 struct desc_ptr dt;
1431 ulong addr;
1432
1433 ctxt->ops->get_idt(ctxt, &dt);
1434
1435 if (dt.size < index * 8 + 7)
1436 return emulate_gp(ctxt, index << 3 | 0x2);
1437
1438 addr = dt.address + index * 8;
1439 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1440 &ctxt->exception);
1441}
1442
dde7e6d1 1443static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1444 u16 selector, struct desc_ptr *dt)
1445{
0225fb50 1446 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1447 u32 base3 = 0;
7b105ca2 1448
dde7e6d1
AK		 1449 if (selector & 1 << 2) {
1450 struct desc_struct desc;
1aa36616
AK		 1451 u16 sel;
1452
dde7e6d1 1453 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1454 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1455 VCPU_SREG_LDTR))
dde7e6d1 1456 return;
e09d082c 1457
dde7e6d1 1458 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1459 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1460 } else
4bff1e86 1461 ops->get_gdt(ctxt, dt);
dde7e6d1 1462}
120df890 1463
edccda7c
NA		 1464static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1465 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1466{
1467 struct desc_ptr dt;
1468 u16 index = selector >> 3;
dde7e6d1 1469 ulong addr;
120df890 1470
7b105ca2 1471 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1472
35d3d4a1
AK		 1473 if (dt.size < index * 8 + 7)
1474 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1475
edccda7c
NA		 1476 addr = dt.address + index * 8;
1477
1478#ifdef CONFIG_X86_64
1479 if (addr >> 32 != 0) {
1480 u64 efer = 0;
1481
1482 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1483 if (!(efer & EFER_LMA))
1484 addr &= (u32)-1;
1485 }
1486#endif
1487
1488 *desc_addr_p = addr;
1489 return X86EMUL_CONTINUE;
1490}
1491
1492/* allowed just for 8 bytes segments */
1493static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1494 u16 selector, struct desc_struct *desc,
1495 ulong *desc_addr_p)
1496{
1497 int rc;
1498
1499 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1500 if (rc != X86EMUL_CONTINUE)
1501 return rc;
1502
1503 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1504 &ctxt->exception);
dde7e6d1 1505}
ef65c889 1506
dde7e6d1
AK		 1507/* allowed just for 8 bytes segments */
1508static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1509 u16 selector, struct desc_struct *desc)
1510{
edccda7c 1511 int rc;
dde7e6d1 1512 ulong addr;
6aa8b732 1513
edccda7c
NA		 1514 rc = get_descriptor_ptr(ctxt, selector, &addr);
1515 if (rc != X86EMUL_CONTINUE)
1516 return rc;
6aa8b732 1517
7b105ca2
TY		 1518 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1519 &ctxt->exception);
dde7e6d1 1520}
c7e75a3d 1521
5601d05b 1522/* Does not support long mode */
2356aaeb 1523static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1524 u16 selector, int seg, u8 cpl,
3dc4bc4f 1525 enum x86_transfer_type transfer,
d1442d85 1526 struct desc_struct *desc)
dde7e6d1 1527{
869be99c 1528 struct desc_struct seg_desc, old_desc;
2356aaeb 1529 u8 dpl, rpl;
dde7e6d1
AK		 1530 unsigned err_vec = GP_VECTOR;
1531 u32 err_code = 0;
1532 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1533 ulong desc_addr;
dde7e6d1 1534 int ret;
03ebebeb 1535 u16 dummy;
e37a75a1 1536 u32 base3 = 0;
69f55cb1 1537
dde7e6d1 1538 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1539
f8da94e9
KW		 1540 if (ctxt->mode == X86EMUL_MODE_REAL) {
1541 /* set real mode segment descriptor (keep limit etc. for
1542 * unreal mode) */
03ebebeb 1543 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1544 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1545 goto load;
f8da94e9
KW		 1546 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1547 /* VM86 needs a clean new segment descriptor */
1548 set_desc_base(&seg_desc, selector << 4);
1549 set_desc_limit(&seg_desc, 0xffff);
1550 seg_desc.type = 3;
1551 seg_desc.p = 1;
1552 seg_desc.s = 1;
1553 seg_desc.dpl = 3;
1554 goto load;
dde7e6d1
AK		 1555 }
1556
79d5b4c3 1557 rpl = selector & 3;
79d5b4c3
AK		 1558
1559 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1560 if ((seg == VCPU_SREG_CS
1561 || (seg == VCPU_SREG_SS
1562 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1563 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1564 && null_selector)
1565 goto exception;
1566
1567 /* TR should be in GDT only */
1568 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1569 goto exception;
1570
1571 if (null_selector) /* for NULL selector skip all following checks */
1572 goto load;
1573
e919464b 1574 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1575 if (ret != X86EMUL_CONTINUE)
1576 return ret;
1577
1578 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1579 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1580 GP_VECTOR;
dde7e6d1 1581
fc058680 1582 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1583 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1584 if (transfer == X86_TRANSFER_CALL_JMP)
1585 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1586 goto exception;
3dc4bc4f 1587 }
dde7e6d1
AK		 1588
1589 if (!seg_desc.p) {
1590 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1591 goto exception;
1592 }
1593
dde7e6d1 1594 dpl = seg_desc.dpl;
dde7e6d1
AK		 1595
1596 switch (seg) {
1597 case VCPU_SREG_SS:
1598 /*
1599 * segment is not a writable data segment or segment
1600 * selector's RPL != CPL or segment selector's RPL != CPL
1601 */
1602 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1603 goto exception;
6aa8b732 1604 break;
dde7e6d1
AK		 1605 case VCPU_SREG_CS:
1606 if (!(seg_desc.type & 8))
1607 goto exception;
1608
1609 if (seg_desc.type & 4) {
1610 /* conforming */
1611 if (dpl > cpl)
1612 goto exception;
1613 } else {
1614 /* nonconforming */
1615 if (rpl > cpl || dpl != cpl)
1616 goto exception;
1617 }
040c8dc8
NA		 1618 /* in long-mode d/b must be clear if l is set */
1619 if (seg_desc.d && seg_desc.l) {
1620 u64 efer = 0;
1621
1622 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1623 if (efer & EFER_LMA)
1624 goto exception;
1625 }
1626
dde7e6d1
AK		 1627 /* CS(RPL) <- CPL */
1628 selector = (selector & 0xfffc) | cpl;
6aa8b732 1629 break;
dde7e6d1
AK		 1630 case VCPU_SREG_TR:
1631 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1632 goto exception;
869be99c
AK		 1633 old_desc = seg_desc;
1634 seg_desc.type |= 2; /* busy */
1635 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1636 sizeof(seg_desc), &ctxt->exception);
1637 if (ret != X86EMUL_CONTINUE)
1638 return ret;
dde7e6d1
AK		 1639 break;
1640 case VCPU_SREG_LDTR:
1641 if (seg_desc.s || seg_desc.type != 2)
1642 goto exception;
1643 break;
1644 default: /* DS, ES, FS, or GS */
4e62417b 1645 /*
dde7e6d1
AK		 1646 * segment is not a data or readable code segment or
1647 * ((segment is a data or nonconforming code segment)
1648 * and (both RPL and CPL > DPL))
4e62417b 1649 */
dde7e6d1
AK		 1650 if ((seg_desc.type & 0xa) == 0x8 ||
1651 (((seg_desc.type & 0xc) != 0xc) &&
1652 (rpl > dpl && cpl > dpl)))
1653 goto exception;
6aa8b732 1654 break;
dde7e6d1
AK		 1655 }
1656
1657 if (seg_desc.s) {
1658 /* mark segment as accessed */
e2cefa74
NA		 1659 if (!(seg_desc.type & 1)) {
1660 seg_desc.type |= 1;
1661 ret = write_segment_descriptor(ctxt, selector,
1662 &seg_desc);
1663 if (ret != X86EMUL_CONTINUE)
1664 return ret;
1665 }
e37a75a1
NA		 1666 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1667 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1668 sizeof(base3), &ctxt->exception);
1669 if (ret != X86EMUL_CONTINUE)
1670 return ret;
9a9abf6b
NA		 1671 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1672 ((u64)base3 << 32)))
1673 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1674 }
1675load:
e37a75a1 1676 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1677 if (desc)
1678 *desc = seg_desc;
dde7e6d1
AK		 1679 return X86EMUL_CONTINUE;
1680exception:
592f0858 1681 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1682}
1683
2356aaeb
PB		 1684static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1685 u16 selector, int seg)
1686{
1687 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1688 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1689 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1690}
1691
31be40b3
WY		 1692static void write_register_operand(struct operand *op)
1693{
1694 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1695 switch (op->bytes) {
1696 case 1:
1697 *(u8 *)op->addr.reg = (u8)op->val;
1698 break;
1699 case 2:
1700 *(u16 *)op->addr.reg = (u16)op->val;
1701 break;
1702 case 4:
1703 *op->addr.reg = (u32)op->val;
1704 break; /* 64b: zero-extend */
1705 case 8:
1706 *op->addr.reg = op->val;
1707 break;
1708 }
1709}
1710
fb32b1ed 1711static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1712{
fb32b1ed 1713 switch (op->type) {
dde7e6d1 1714 case OP_REG:
fb32b1ed 1715 write_register_operand(op);
6aa8b732 1716 break;
dde7e6d1 1717 case OP_MEM:
9dac77fa 1718 if (ctxt->lock_prefix)
f5f87dfb
PB		 1719 return segmented_cmpxchg(ctxt,
1720 op->addr.mem,
1721 &op->orig_val,
1722 &op->val,
1723 op->bytes);
1724 else
1725 return segmented_write(ctxt,
fb32b1ed 1726 op->addr.mem,
fb32b1ed
AK		 1727 &op->val,
1728 op->bytes);
a682e354 1729 break;
b3356bf0 1730 case OP_MEM_STR:
f5f87dfb
PB		 1731 return segmented_write(ctxt,
1732 op->addr.mem,
1733 op->data,
1734 op->bytes * op->count);
b3356bf0 1735 break;
1253791d 1736 case OP_XMM:
fb32b1ed 1737 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1738 break;
cbe2c9d3 1739 case OP_MM:
fb32b1ed 1740 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1741 break;
dde7e6d1
AK		 1742 case OP_NONE:
1743 /* no writeback */
414e6277 1744 break;
dde7e6d1 1745 default:
414e6277 1746 break;
6aa8b732 1747 }
dde7e6d1
AK		 1748 return X86EMUL_CONTINUE;
1749}
6aa8b732 1750
51ddff50 1751static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1752{
4179bb02 1753 struct segmented_address addr;
0dc8d10f 1754
5ad105e5 1755 rsp_increment(ctxt, -bytes);
dd856efa 1756 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1757 addr.seg = VCPU_SREG_SS;
1758
51ddff50
AK		 1759 return segmented_write(ctxt, addr, data, bytes);
1760}
1761
1762static int em_push(struct x86_emulate_ctxt *ctxt)
1763{
4179bb02 1764 /* Disable writeback. */
9dac77fa 1765 ctxt->dst.type = OP_NONE;
51ddff50 1766 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1767}
69f55cb1 1768
dde7e6d1 1769static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1770 void *dest, int len)
1771{
dde7e6d1 1772 int rc;
90de84f5 1773 struct segmented_address addr;
8b4caf66 1774
dd856efa 1775 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1776 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1777 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1778 if (rc != X86EMUL_CONTINUE)
1779 return rc;
1780
5ad105e5 1781 rsp_increment(ctxt, len);
dde7e6d1 1782 return rc;
8b4caf66
LV		 1783}
1784
c54fe504
TY		 1785static int em_pop(struct x86_emulate_ctxt *ctxt)
1786{
9dac77fa 1787 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1788}
1789
dde7e6d1 1790static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1791 void *dest, int len)
9de41573
GN		 1792{
1793 int rc;
dde7e6d1
AK		 1794 unsigned long val, change_mask;
1795 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1796 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1797
3b9be3bf 1798 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1799 if (rc != X86EMUL_CONTINUE)
1800 return rc;
9de41573 1801
dde7e6d1 1802 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1803 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1804
dde7e6d1
AK		 1805 switch(ctxt->mode) {
1806 case X86EMUL_MODE_PROT64:
1807 case X86EMUL_MODE_PROT32:
1808 case X86EMUL_MODE_PROT16:
1809 if (cpl == 0)
1810 change_mask |= EFLG_IOPL;
1811 if (cpl <= iopl)
1812 change_mask |= EFLG_IF;
1813 break;
1814 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1815 if (iopl < 3)
1816 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1817 change_mask |= EFLG_IF;
1818 break;
1819 default: /* real mode */
1820 change_mask |= (EFLG_IOPL | EFLG_IF);
1821 break;
9de41573 1822 }
dde7e6d1
AK		 1823
1824 *(unsigned long *)dest =
1825 (ctxt->eflags & ~change_mask) | (val & change_mask);
1826
1827 return rc;
9de41573
GN		 1828}
1829
62aaa2f0
TY		 1830static int em_popf(struct x86_emulate_ctxt *ctxt)
1831{
9dac77fa
AK		 1832 ctxt->dst.type = OP_REG;
1833 ctxt->dst.addr.reg = &ctxt->eflags;
1834 ctxt->dst.bytes = ctxt->op_bytes;
1835 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1836}
1837
612e89f0
AK		 1838static int em_enter(struct x86_emulate_ctxt *ctxt)
1839{
1840 int rc;
1841 unsigned frame_size = ctxt->src.val;
1842 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1843 ulong rbp;
612e89f0
AK		 1844
1845 if (nesting_level)
1846 return X86EMUL_UNHANDLEABLE;
1847
dd856efa
AK		 1848 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1849 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1850 if (rc != X86EMUL_CONTINUE)
1851 return rc;
dd856efa 1852 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1853 stack_mask(ctxt));
dd856efa
AK		 1854 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1855 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1856 stack_mask(ctxt));
1857 return X86EMUL_CONTINUE;
1858}
1859
f47cfa31
AK		 1860static int em_leave(struct x86_emulate_ctxt *ctxt)
1861{
dd856efa 1862 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1863 stack_mask(ctxt));
dd856efa 1864 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1865}
1866
1cd196ea 1867static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1868{
1cd196ea
AK		 1869 int seg = ctxt->src2.val;
1870
9dac77fa 1871 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1872 if (ctxt->op_bytes == 4) {
1873 rsp_increment(ctxt, -2);
1874 ctxt->op_bytes = 2;
1875 }
7b262e90 1876
4487b3b4 1877 return em_push(ctxt);
7b262e90
GN		 1878}
1879
1cd196ea 1880static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1881{
1cd196ea 1882 int seg = ctxt->src2.val;
dde7e6d1
AK		 1883 unsigned long selector;
1884 int rc;
38ba30ba 1885
3313bc4e 1886 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1887 if (rc != X86EMUL_CONTINUE)
1888 return rc;
1889
a5457e7b
PB		 1890 if (ctxt->modrm_reg == VCPU_SREG_SS)
1891 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1892 if (ctxt->op_bytes > 2)
1893 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1894
7b105ca2 1895 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1896 return rc;
38ba30ba
GN		 1897}
1898
b96a7fad 1899static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1900{
dd856efa 1901 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1902 int rc = X86EMUL_CONTINUE;
1903 int reg = VCPU_REGS_RAX;
38ba30ba 1904
dde7e6d1
AK		 1905 while (reg <= VCPU_REGS_RDI) {
1906 (reg == VCPU_REGS_RSP) ?
dd856efa 1907 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1908
4487b3b4 1909 rc = em_push(ctxt);
dde7e6d1
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
38ba30ba 1912
dde7e6d1 1913 ++reg;
38ba30ba 1914 }
38ba30ba 1915
dde7e6d1 1916 return rc;
38ba30ba
GN		 1917}
1918
62aaa2f0
TY		 1919static int em_pushf(struct x86_emulate_ctxt *ctxt)
1920{
bc397a6c 1921 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1922 return em_push(ctxt);
1923}
1924
b96a7fad 1925static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1926{
dde7e6d1
AK		 1927 int rc = X86EMUL_CONTINUE;
1928 int reg = VCPU_REGS_RDI;
38ba30ba 1929
dde7e6d1
AK		 1930 while (reg >= VCPU_REGS_RAX) {
1931 if (reg == VCPU_REGS_RSP) {
5ad105e5 1932 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1933 --reg;
1934 }
38ba30ba 1935
dd856efa 1936 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1937 if (rc != X86EMUL_CONTINUE)
1938 break;
1939 --reg;
38ba30ba 1940 }
dde7e6d1 1941 return rc;
38ba30ba
GN		 1942}
1943
dd856efa 1944static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1945{
0225fb50 1946 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1947 int rc;
6e154e56
MG		 1948 struct desc_ptr dt;
1949 gva_t cs_addr;
1950 gva_t eip_addr;
1951 u16 cs, eip;
6e154e56
MG		 1952
1953 /* TODO: Add limit checks */
9dac77fa 1954 ctxt->src.val = ctxt->eflags;
4487b3b4 1955 rc = em_push(ctxt);
5c56e1cf
AK		 1956 if (rc != X86EMUL_CONTINUE)
1957 return rc;
6e154e56
MG		 1958
1959 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1960
9dac77fa 1961 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1962 rc = em_push(ctxt);
5c56e1cf
AK		 1963 if (rc != X86EMUL_CONTINUE)
1964 return rc;
6e154e56 1965
9dac77fa 1966 ctxt->src.val = ctxt->_eip;
4487b3b4 1967 rc = em_push(ctxt);
5c56e1cf
AK		 1968 if (rc != X86EMUL_CONTINUE)
1969 return rc;
1970
4bff1e86 1971 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1972
1973 eip_addr = dt.address + (irq << 2);
1974 cs_addr = dt.address + (irq << 2) + 2;
1975
0f65dd70 1976 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1977 if (rc != X86EMUL_CONTINUE)
1978 return rc;
1979
0f65dd70 1980 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1981 if (rc != X86EMUL_CONTINUE)
1982 return rc;
1983
7b105ca2 1984 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
1987
9dac77fa 1988 ctxt->_eip = eip;
6e154e56
MG		 1989
1990 return rc;
1991}
1992
dd856efa
AK		 1993int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1994{
1995 int rc;
1996
1997 invalidate_registers(ctxt);
1998 rc = __emulate_int_real(ctxt, irq);
1999 if (rc == X86EMUL_CONTINUE)
2000 writeback_registers(ctxt);
2001 return rc;
2002}
2003
7b105ca2 2004static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2005{
2006 switch(ctxt->mode) {
2007 case X86EMUL_MODE_REAL:
dd856efa 2008 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2009 case X86EMUL_MODE_VM86:
2010 case X86EMUL_MODE_PROT16:
2011 case X86EMUL_MODE_PROT32:
2012 case X86EMUL_MODE_PROT64:
2013 default:
2014 /* Protected mode interrupts unimplemented yet */
2015 return X86EMUL_UNHANDLEABLE;
2016 }
2017}
2018
7b105ca2 2019static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2020{
dde7e6d1
AK		 2021 int rc = X86EMUL_CONTINUE;
2022 unsigned long temp_eip = 0;
2023 unsigned long temp_eflags = 0;
2024 unsigned long cs = 0;
2025 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2026 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2027 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2028 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2029
dde7e6d1 2030 /* TODO: Add stack limit check */
38ba30ba 2031
9dac77fa 2032 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2033
dde7e6d1
AK		 2034 if (rc != X86EMUL_CONTINUE)
2035 return rc;
38ba30ba 2036
35d3d4a1
AK		 2037 if (temp_eip & ~0xffff)
2038 return emulate_gp(ctxt, 0);
38ba30ba 2039
9dac77fa 2040 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2041
dde7e6d1
AK		 2042 if (rc != X86EMUL_CONTINUE)
2043 return rc;
38ba30ba 2044
9dac77fa 2045 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2046
dde7e6d1
AK		 2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
38ba30ba 2049
7b105ca2 2050 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2051
dde7e6d1
AK		 2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
38ba30ba 2054
9dac77fa 2055 ctxt->_eip = temp_eip;
38ba30ba 2056
38ba30ba 2057
9dac77fa 2058 if (ctxt->op_bytes == 4)
dde7e6d1 2059 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2060 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2061 ctxt->eflags &= ~0xffff;
2062 ctxt->eflags |= temp_eflags;
38ba30ba 2063 }
dde7e6d1
AK		 2064
2065 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2066 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
801806d9 2067 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2068
2069 return rc;
38ba30ba
GN		 2070}
2071
e01991e7 2072static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2073{
dde7e6d1
AK		 2074 switch(ctxt->mode) {
2075 case X86EMUL_MODE_REAL:
7b105ca2 2076 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2077 case X86EMUL_MODE_VM86:
2078 case X86EMUL_MODE_PROT16:
2079 case X86EMUL_MODE_PROT32:
2080 case X86EMUL_MODE_PROT64:
c37eda13 2081 default:
dde7e6d1
AK		 2082 /* iret from protected mode unimplemented yet */
2083 return X86EMUL_UNHANDLEABLE;
c37eda13 2084 }
c37eda13
WY		 2085}
2086
d2f62766
TY		 2087static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2088{
d2f62766 2089 int rc;
d1442d85
NA		 2090 unsigned short sel, old_sel;
2091 struct desc_struct old_desc, new_desc;
2092 const struct x86_emulate_ops *ops = ctxt->ops;
2093 u8 cpl = ctxt->ops->cpl(ctxt);
2094
2095 /* Assignment of RIP may only fail in 64-bit mode */
2096 if (ctxt->mode == X86EMUL_MODE_PROT64)
2097 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2098 VCPU_SREG_CS);
d2f62766 2099
9dac77fa 2100 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2101
3dc4bc4f
NA		 2102 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2103 X86_TRANSFER_CALL_JMP,
d1442d85 2104 &new_desc);
d2f62766
TY		 2105 if (rc != X86EMUL_CONTINUE)
2106 return rc;
2107
d50eaa18 2108 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2109 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2110 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2111 /* assigning eip failed; restore the old cs */
2112 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2113 return rc;
2114 }
2115 return rc;
d2f62766
TY		 2116}
2117
f7784046 2118static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2119{
f7784046
NA		 2120 return assign_eip_near(ctxt, ctxt->src.val);
2121}
8cdbd2c9 2122
f7784046
NA		 2123static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2124{
2125 int rc;
2126 long int old_eip;
2127
2128 old_eip = ctxt->_eip;
2129 rc = assign_eip_near(ctxt, ctxt->src.val);
2130 if (rc != X86EMUL_CONTINUE)
2131 return rc;
2132 ctxt->src.val = old_eip;
2133 rc = em_push(ctxt);
4179bb02 2134 return rc;
8cdbd2c9
LV		 2135}
2136
e0dac408 2137static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2138{
9dac77fa 2139 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2140
aaa05f24
NA		 2141 if (ctxt->dst.bytes == 16)
2142 return X86EMUL_UNHANDLEABLE;
2143
dd856efa
AK		 2144 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2145 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2146 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2147 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2148 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2149 } else {
dd856efa
AK		 2150 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2151 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2152
05f086f8 2153 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2154 }
1b30eaa8 2155 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2156}
2157
ebda02c2
TY		 2158static int em_ret(struct x86_emulate_ctxt *ctxt)
2159{
234f3ce4
NA		 2160 int rc;
2161 unsigned long eip;
2162
2163 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2164 if (rc != X86EMUL_CONTINUE)
2165 return rc;
2166
2167 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2168}
2169
e01991e7 2170static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2171{
a77ab5ea 2172 int rc;
d1442d85
NA		 2173 unsigned long eip, cs;
2174 u16 old_cs;
9e8919ae 2175 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2176 struct desc_struct old_desc, new_desc;
2177 const struct x86_emulate_ops *ops = ctxt->ops;
2178
2179 if (ctxt->mode == X86EMUL_MODE_PROT64)
2180 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2181 VCPU_SREG_CS);
a77ab5ea 2182
d1442d85 2183 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2184 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2185 return rc;
9dac77fa 2186 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2187 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2188 return rc;
9e8919ae
NA		 2189 /* Outer-privilege level return is not implemented */
2190 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2191 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2192 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2193 X86_TRANSFER_RET,
d1442d85
NA		 2194 &new_desc);
2195 if (rc != X86EMUL_CONTINUE)
2196 return rc;
d50eaa18 2197 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2198 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2199 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2200 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2201 }
a77ab5ea
AK		 2202 return rc;
2203}
2204
3261107e
BR		 2205static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2206{
2207 int rc;
2208
2209 rc = em_ret_far(ctxt);
2210 if (rc != X86EMUL_CONTINUE)
2211 return rc;
2212 rsp_increment(ctxt, ctxt->src.val);
2213 return X86EMUL_CONTINUE;
2214}
2215
e940b5c2
TY		 2216static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2217{
2218 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2219 ctxt->dst.orig_val = ctxt->dst.val;
2220 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2221 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2222 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2223 fastop(ctxt, em_cmp);
e940b5c2
TY		 2224
2225 if (ctxt->eflags & EFLG_ZF) {
2fcf5c8a
NA		 2226 /* Success: write back to memory; no update of EAX */
2227 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2228 ctxt->dst.val = ctxt->src.orig_val;
2229 } else {
2230 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2231 ctxt->src.type = OP_REG;
2232 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2233 ctxt->src.val = ctxt->dst.orig_val;
2234 /* Create write-cycle to dest by writing the same value */
37c564f2 2235 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2236 }
2237 return X86EMUL_CONTINUE;
2238}
2239
d4b4325f 2240static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2241{
d4b4325f 2242 int seg = ctxt->src2.val;
09b5f4d3
WY		 2243 unsigned short sel;
2244 int rc;
2245
9dac77fa 2246 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2247
7b105ca2 2248 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2249 if (rc != X86EMUL_CONTINUE)
2250 return rc;
2251
9dac77fa 2252 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2253 return rc;
2254}
2255
7b105ca2 2256static void
e66bb2cc 2257setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2258 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2259{
e66bb2cc 2260 cs->l = 0; /* will be adjusted later */
79168fd1 2261 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2262 cs->g = 1; /* 4kb granularity */
79168fd1 2263 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2264 cs->type = 0x0b; /* Read, Execute, Accessed */
2265 cs->s = 1;
2266 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2267 cs->p = 1;
2268 cs->d = 1;
99245b50 2269 cs->avl = 0;
e66bb2cc 2270
79168fd1
GN		 2271 set_desc_base(ss, 0); /* flat segment */
2272 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2273 ss->g = 1; /* 4kb granularity */
2274 ss->s = 1;
2275 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2276 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2277 ss->dpl = 0;
79168fd1 2278 ss->p = 1;
99245b50
GN		 2279 ss->l = 0;
2280 ss->avl = 0;
e66bb2cc
AP		 2281}
2282
1a18a69b
AK		 2283static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2284{
2285 u32 eax, ebx, ecx, edx;
2286
2287 eax = ecx = 0;
0017f93a
AK		 2288 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2289 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2290 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2291 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2292}
2293
c2226fc9
SB		 2294static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2295{
0225fb50 2296 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2297 u32 eax, ebx, ecx, edx;
2298
2299 /*
2300 * syscall should always be enabled in longmode - so only become
2301 * vendor specific (cpuid) if other modes are active...
2302 */
2303 if (ctxt->mode == X86EMUL_MODE_PROT64)
2304 return true;
2305
2306 eax = 0x00000000;
2307 ecx = 0x00000000;
0017f93a
AK		 2308 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2309 /*
2310 * Intel ("GenuineIntel")
2311 * remark: Intel CPUs only support "syscall" in 64bit
2312 * longmode. Also an 64bit guest with a
2313 * 32bit compat-app running will #UD !! While this
2314 * behaviour can be fixed (by emulating) into AMD
2315 * response - CPUs of AMD can't behave like Intel.
2316 */
2317 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2318 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2319 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2320 return false;
2321
2322 /* AMD ("AuthenticAMD") */
2323 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2324 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2325 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2326 return true;
2327
2328 /* AMD ("AMDisbetter!") */
2329 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2330 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2331 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2332 return true;
c2226fc9
SB		 2333
2334 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2335 return false;
2336}
2337
e01991e7 2338static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2339{
0225fb50 2340 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2341 struct desc_struct cs, ss;
e66bb2cc 2342 u64 msr_data;
79168fd1 2343 u16 cs_sel, ss_sel;
c2ad2bb3 2344 u64 efer = 0;
e66bb2cc
AP		 2345
2346 /* syscall is not available in real mode */
2e901c4c 2347 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2348 ctxt->mode == X86EMUL_MODE_VM86)
2349 return emulate_ud(ctxt);
e66bb2cc 2350
c2226fc9
SB		 2351 if (!(em_syscall_is_enabled(ctxt)))
2352 return emulate_ud(ctxt);
2353
c2ad2bb3 2354 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2355 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2356
c2226fc9
SB		 2357 if (!(efer & EFER_SCE))
2358 return emulate_ud(ctxt);
2359
717746e3 2360 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2361 msr_data >>= 32;
79168fd1
GN		 2362 cs_sel = (u16)(msr_data & 0xfffc);
2363 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2364
c2ad2bb3 2365 if (efer & EFER_LMA) {
79168fd1 2366 cs.d = 0;
e66bb2cc
AP		 2367 cs.l = 1;
2368 }
1aa36616
AK		 2369 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2370 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2371
dd856efa 2372 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2373 if (efer & EFER_LMA) {
e66bb2cc 2374#ifdef CONFIG_X86_64
6c6cb69b 2375 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2376
717746e3 2377 ops->get_msr(ctxt,
3fb1b5db
GN		 2378 ctxt->mode == X86EMUL_MODE_PROT64 ?
2379 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2380 ctxt->_eip = msr_data;
e66bb2cc 2381
717746e3 2382 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2383 ctxt->eflags &= ~msr_data;
807c1425 2384 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2385#endif
2386 } else {
2387 /* legacy mode */
717746e3 2388 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2389 ctxt->_eip = (u32)msr_data;
e66bb2cc 2390
6c6cb69b 2391 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2392 }
2393
e54cfa97 2394 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2395}
2396
e01991e7 2397static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2398{
0225fb50 2399 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2400 struct desc_struct cs, ss;
8c604352 2401 u64 msr_data;
79168fd1 2402 u16 cs_sel, ss_sel;
c2ad2bb3 2403 u64 efer = 0;
8c604352 2404
7b105ca2 2405 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2406 /* inject #GP if in real mode */
35d3d4a1
AK		 2407 if (ctxt->mode == X86EMUL_MODE_REAL)
2408 return emulate_gp(ctxt, 0);
8c604352 2409
1a18a69b
AK		 2410 /*
2411 * Not recognized on AMD in compat mode (but is recognized in legacy
2412 * mode).
2413 */
f3747379 2414 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2415 && !vendor_intel(ctxt))
2416 return emulate_ud(ctxt);
2417
b2c9d43e 2418 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2419 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2420 return X86EMUL_UNHANDLEABLE;
8c604352 2421
7b105ca2 2422 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2423
717746e3 2424 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2425 if ((msr_data & 0xfffc) == 0x0)
2426 return emulate_gp(ctxt, 0);
8c604352 2427
6c6cb69b 2428 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
f3747379 2429 cs_sel = (u16)msr_data & ~SELECTOR_RPL_MASK;
79168fd1 2430 ss_sel = cs_sel + 8;
f3747379 2431 if (efer & EFER_LMA) {
79168fd1 2432 cs.d = 0;
8c604352
AP		 2433 cs.l = 1;
2434 }
2435
1aa36616
AK		 2436 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2437 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2438
717746e3 2439 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2440 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2441
717746e3 2442 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2443 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2444 (u32)msr_data;
8c604352 2445
e54cfa97 2446 return X86EMUL_CONTINUE;
8c604352
AP		 2447}
2448
e01991e7 2449static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2450{
0225fb50 2451 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2452 struct desc_struct cs, ss;
234f3ce4 2453 u64 msr_data, rcx, rdx;
4668f050 2454 int usermode;
1249b96e 2455 u16 cs_sel = 0, ss_sel = 0;
4668f050 2456
a0044755
GN		 2457 /* inject #GP if in real mode or Virtual 8086 mode */
2458 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2459 ctxt->mode == X86EMUL_MODE_VM86)
2460 return emulate_gp(ctxt, 0);
4668f050 2461
7b105ca2 2462 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2463
9dac77fa 2464 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2465 usermode = X86EMUL_MODE_PROT64;
2466 else
2467 usermode = X86EMUL_MODE_PROT32;
2468
234f3ce4
NA		 2469 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2470 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2471
4668f050
AP		 2472 cs.dpl = 3;
2473 ss.dpl = 3;
717746e3 2474 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2475 switch (usermode) {
2476 case X86EMUL_MODE_PROT32:
79168fd1 2477 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2478 if ((msr_data & 0xfffc) == 0x0)
2479 return emulate_gp(ctxt, 0);
79168fd1 2480 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2481 rcx = (u32)rcx;
2482 rdx = (u32)rdx;
4668f050
AP		 2483 break;
2484 case X86EMUL_MODE_PROT64:
79168fd1 2485 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2486 if (msr_data == 0x0)
2487 return emulate_gp(ctxt, 0);
79168fd1
GN		 2488 ss_sel = cs_sel + 8;
2489 cs.d = 0;
4668f050 2490 cs.l = 1;
234f3ce4
NA		 2491 if (is_noncanonical_address(rcx) ||
2492 is_noncanonical_address(rdx))
2493 return emulate_gp(ctxt, 0);
4668f050
AP		 2494 break;
2495 }
79168fd1
GN		 2496 cs_sel |= SELECTOR_RPL_MASK;
2497 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2498
1aa36616
AK		 2499 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2500 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2501
234f3ce4
NA		 2502 ctxt->_eip = rdx;
2503 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2504
e54cfa97 2505 return X86EMUL_CONTINUE;
4668f050
AP		 2506}
2507
7b105ca2 2508static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2509{
2510 int iopl;
2511 if (ctxt->mode == X86EMUL_MODE_REAL)
2512 return false;
2513 if (ctxt->mode == X86EMUL_MODE_VM86)
2514 return true;
2515 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2516 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2517}
2518
2519static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2520 u16 port, u16 len)
2521{
0225fb50 2522 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2523 struct desc_struct tr_seg;
5601d05b 2524 u32 base3;
f850e2e6 2525 int r;
1aa36616 2526 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2527 unsigned mask = (1 << len) - 1;
5601d05b 2528 unsigned long base;
f850e2e6 2529
1aa36616 2530 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2531 if (!tr_seg.p)
f850e2e6 2532 return false;
79168fd1 2533 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2534 return false;
5601d05b
GN		 2535 base = get_desc_base(&tr_seg);
2536#ifdef CONFIG_X86_64
2537 base |= ((u64)base3) << 32;
2538#endif
0f65dd70 2539 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2540 if (r != X86EMUL_CONTINUE)
2541 return false;
79168fd1 2542 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2543 return false;
0f65dd70 2544 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2545 if (r != X86EMUL_CONTINUE)
2546 return false;
2547 if ((perm >> bit_idx) & mask)
2548 return false;
2549 return true;
2550}
2551
2552static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2553 u16 port, u16 len)
2554{
4fc40f07
GN		 2555 if (ctxt->perm_ok)
2556 return true;
2557
7b105ca2
TY		 2558 if (emulator_bad_iopl(ctxt))
2559 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2560 return false;
4fc40f07
GN		 2561
2562 ctxt->perm_ok = true;
2563
f850e2e6
GN		 2564 return true;
2565}
2566
38ba30ba 2567static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2568 struct tss_segment_16 *tss)
2569{
9dac77fa 2570 tss->ip = ctxt->_eip;
38ba30ba 2571 tss->flag = ctxt->eflags;
dd856efa
AK		 2572 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2573 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2574 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2575 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2576 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2577 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2578 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2579 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2580
1aa36616
AK		 2581 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2582 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2583 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2584 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2585 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2586}
2587
2588static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2589 struct tss_segment_16 *tss)
2590{
38ba30ba 2591 int ret;
2356aaeb 2592 u8 cpl;
38ba30ba 2593
9dac77fa 2594 ctxt->_eip = tss->ip;
38ba30ba 2595 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2596 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2597 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2598 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2599 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2600 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2601 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2602 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2603 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2604
2605 /*
2606 * SDM says that segment selectors are loaded before segment
2607 * descriptors
2608 */
1aa36616
AK		 2609 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2610 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2611 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2612 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2613 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2614
2356aaeb
PB		 2615 cpl = tss->cs & 3;
2616
38ba30ba 2617 /*
fc058680 2618 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2619 * it is handled in a context of new task
2620 */
d1442d85 2621 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2622 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2623 if (ret != X86EMUL_CONTINUE)
2624 return ret;
d1442d85 2625 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2626 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
d1442d85 2629 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2630 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2631 if (ret != X86EMUL_CONTINUE)
2632 return ret;
d1442d85 2633 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2634 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2635 if (ret != X86EMUL_CONTINUE)
2636 return ret;
d1442d85 2637 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2638 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2639 if (ret != X86EMUL_CONTINUE)
2640 return ret;
2641
2642 return X86EMUL_CONTINUE;
2643}
2644
2645static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2646 u16 tss_selector, u16 old_tss_sel,
2647 ulong old_tss_base, struct desc_struct *new_desc)
2648{
0225fb50 2649 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2650 struct tss_segment_16 tss_seg;
2651 int ret;
bcc55cba 2652 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2653
0f65dd70 2654 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2655 &ctxt->exception);
db297e3d 2656 if (ret != X86EMUL_CONTINUE)
38ba30ba 2657 return ret;
38ba30ba 2658
7b105ca2 2659 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2660
0f65dd70 2661 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2662 &ctxt->exception);
db297e3d 2663 if (ret != X86EMUL_CONTINUE)
38ba30ba 2664 return ret;
38ba30ba 2665
0f65dd70 2666 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2667 &ctxt->exception);
db297e3d 2668 if (ret != X86EMUL_CONTINUE)
38ba30ba 2669 return ret;
38ba30ba
GN		 2670
2671 if (old_tss_sel != 0xffff) {
2672 tss_seg.prev_task_link = old_tss_sel;
2673
0f65dd70 2674 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2675 &tss_seg.prev_task_link,
2676 sizeof tss_seg.prev_task_link,
0f65dd70 2677 &ctxt->exception);
db297e3d 2678 if (ret != X86EMUL_CONTINUE)
38ba30ba 2679 return ret;
38ba30ba
GN		 2680 }
2681
7b105ca2 2682 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2683}
2684
2685static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2686 struct tss_segment_32 *tss)
2687{
5c7411e2 2688 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2689 tss->eip = ctxt->_eip;
38ba30ba 2690 tss->eflags = ctxt->eflags;
dd856efa
AK		 2691 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2692 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2693 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2694 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2695 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2696 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2697 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2698 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2699
1aa36616
AK		 2700 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2701 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2702 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2703 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2704 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2705 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2706}
2707
2708static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2709 struct tss_segment_32 *tss)
2710{
38ba30ba 2711 int ret;
2356aaeb 2712 u8 cpl;
38ba30ba 2713
7b105ca2 2714 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2715 return emulate_gp(ctxt, 0);
9dac77fa 2716 ctxt->_eip = tss->eip;
38ba30ba 2717 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2718
2719 /* General purpose registers */
dd856efa
AK		 2720 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2721 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2722 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2723 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2724 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2725 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2726 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2727 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2728
2729 /*
2730 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2731 * descriptors. This is important because CPL checks will
2732 * use CS.RPL.
38ba30ba 2733 */
1aa36616
AK		 2734 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2735 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2736 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2737 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2738 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2739 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2740 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2741
4cee4798
KW		 2742 /*
2743 * If we're switching between Protected Mode and VM86, we need to make
2744 * sure to update the mode before loading the segment descriptors so
2745 * that the selectors are interpreted correctly.
4cee4798 2746 */
2356aaeb 2747 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2748 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2749 cpl = 3;
2750 } else {
4cee4798 2751 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2752 cpl = tss->cs & 3;
2753 }
4cee4798 2754
38ba30ba
GN		 2755 /*
2756 * Now load segment descriptors. If fault happenes at this stage
2757 * it is handled in a context of new task
2758 */
d1442d85 2759 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2760 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2761 if (ret != X86EMUL_CONTINUE)
2762 return ret;
d1442d85 2763 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2764 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2765 if (ret != X86EMUL_CONTINUE)
2766 return ret;
d1442d85 2767 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2768 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2769 if (ret != X86EMUL_CONTINUE)
2770 return ret;
d1442d85 2771 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2772 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2773 if (ret != X86EMUL_CONTINUE)
2774 return ret;
d1442d85 2775 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2776 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2777 if (ret != X86EMUL_CONTINUE)
2778 return ret;
d1442d85 2779 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2780 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2781 if (ret != X86EMUL_CONTINUE)
2782 return ret;
d1442d85 2783 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2784 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2785 if (ret != X86EMUL_CONTINUE)
2786 return ret;
2787
2788 return X86EMUL_CONTINUE;
2789}
2790
2791static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2792 u16 tss_selector, u16 old_tss_sel,
2793 ulong old_tss_base, struct desc_struct *new_desc)
2794{
0225fb50 2795 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2796 struct tss_segment_32 tss_seg;
2797 int ret;
bcc55cba 2798 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2799 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2800 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2801
0f65dd70 2802 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2803 &ctxt->exception);
db297e3d 2804 if (ret != X86EMUL_CONTINUE)
38ba30ba 2805 return ret;
38ba30ba 2806
7b105ca2 2807 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2808
5c7411e2
NA		 2809 /* Only GP registers and segment selectors are saved */
2810 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2811 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2812 if (ret != X86EMUL_CONTINUE)
38ba30ba 2813 return ret;
38ba30ba 2814
0f65dd70 2815 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2816 &ctxt->exception);
db297e3d 2817 if (ret != X86EMUL_CONTINUE)
38ba30ba 2818 return ret;
38ba30ba
GN		 2819
2820 if (old_tss_sel != 0xffff) {
2821 tss_seg.prev_task_link = old_tss_sel;
2822
0f65dd70 2823 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2824 &tss_seg.prev_task_link,
2825 sizeof tss_seg.prev_task_link,
0f65dd70 2826 &ctxt->exception);
db297e3d 2827 if (ret != X86EMUL_CONTINUE)
38ba30ba 2828 return ret;
38ba30ba
GN		 2829 }
2830
7b105ca2 2831 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2832}
2833
2834static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2835 u16 tss_selector, int idt_index, int reason,
e269fb21 2836 bool has_error_code, u32 error_code)
38ba30ba 2837{
0225fb50 2838 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2839 struct desc_struct curr_tss_desc, next_tss_desc;
2840 int ret;
1aa36616 2841 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2842 ulong old_tss_base =
4bff1e86 2843 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2844 u32 desc_limit;
e919464b 2845 ulong desc_addr;
38ba30ba
GN		 2846
2847 /* FIXME: old_tss_base == ~0 ? */
2848
e919464b 2849 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2850 if (ret != X86EMUL_CONTINUE)
2851 return ret;
e919464b 2852 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2853 if (ret != X86EMUL_CONTINUE)
2854 return ret;
2855
2856 /* FIXME: check that next_tss_desc is tss */
2857
7f3d35fd
KW		 2858 /*
2859 * Check privileges. The three cases are task switch caused by...
2860 *
2861 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2862 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2863 * 3. jmp/call to TSS/task-gate: No check is performed since the
2864 * hardware checks it before exiting.
7f3d35fd
KW		 2865 */
2866 if (reason == TASK_SWITCH_GATE) {
2867 if (idt_index != -1) {
2868 /* Software interrupts */
2869 struct desc_struct task_gate_desc;
2870 int dpl;
2871
2872 ret = read_interrupt_descriptor(ctxt, idt_index,
2873 &task_gate_desc);
2874 if (ret != X86EMUL_CONTINUE)
2875 return ret;
2876
2877 dpl = task_gate_desc.dpl;
2878 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2879 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2880 }
38ba30ba
GN		 2881 }
2882
ceffb459
GN		 2883 desc_limit = desc_limit_scaled(&next_tss_desc);
2884 if (!next_tss_desc.p ||
2885 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2886 desc_limit < 0x2b)) {
592f0858 2887 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2888 }
2889
2890 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2891 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2892 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2893 }
2894
2895 if (reason == TASK_SWITCH_IRET)
2896 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2897
2898 /* set back link to prev task only if NT bit is set in eflags
fc058680 2899 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2900 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2901 old_tss_sel = 0xffff;
2902
2903 if (next_tss_desc.type & 8)
7b105ca2 2904 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2905 old_tss_base, &next_tss_desc);
2906 else
7b105ca2 2907 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2908 old_tss_base, &next_tss_desc);
0760d448
JK		 2909 if (ret != X86EMUL_CONTINUE)
2910 return ret;
38ba30ba
GN		 2911
2912 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2913 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2914
2915 if (reason != TASK_SWITCH_IRET) {
2916 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2917 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2918 }
2919
717746e3 2920 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2921 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2922
e269fb21 2923 if (has_error_code) {
9dac77fa
AK		 2924 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2925 ctxt->lock_prefix = 0;
2926 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2927 ret = em_push(ctxt);
e269fb21
JK		 2928 }
2929
38ba30ba
GN		 2930 return ret;
2931}
2932
2933int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2934 u16 tss_selector, int idt_index, int reason,
e269fb21 2935 bool has_error_code, u32 error_code)
38ba30ba 2936{
38ba30ba
GN		 2937 int rc;
2938
dd856efa 2939 invalidate_registers(ctxt);
9dac77fa
AK		 2940 ctxt->_eip = ctxt->eip;
2941 ctxt->dst.type = OP_NONE;
38ba30ba 2942
7f3d35fd 2943 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2944 has_error_code, error_code);
38ba30ba 2945
dd856efa 2946 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2947 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2948 writeback_registers(ctxt);
2949 }
38ba30ba 2950
a0c0ab2f 2951 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2952}
2953
f3bd64c6
GN		 2954static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2955 struct operand *op)
a682e354 2956{
b3356bf0 2957 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2958
01485a22
PB		 2959 register_address_increment(ctxt, reg, df * op->bytes);
2960 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2961}
2962
7af04fc0
AK		 2963static int em_das(struct x86_emulate_ctxt *ctxt)
2964{
7af04fc0
AK		 2965 u8 al, old_al;
2966 bool af, cf, old_cf;
2967
2968 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2969 al = ctxt->dst.val;
7af04fc0
AK		 2970
2971 old_al = al;
2972 old_cf = cf;
2973 cf = false;
2974 af = ctxt->eflags & X86_EFLAGS_AF;
2975 if ((al & 0x0f) > 9 || af) {
2976 al -= 6;
2977 cf = old_cf | (al >= 250);
2978 af = true;
2979 } else {
2980 af = false;
2981 }
2982 if (old_al > 0x99 || old_cf) {
2983 al -= 0x60;
2984 cf = true;
2985 }
2986
9dac77fa 2987 ctxt->dst.val = al;
7af04fc0 2988 /* Set PF, ZF, SF */
9dac77fa
AK		 2989 ctxt->src.type = OP_IMM;
2990 ctxt->src.val = 0;
2991 ctxt->src.bytes = 1;
158de57f 2992 fastop(ctxt, em_or);
7af04fc0
AK		 2993 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2994 if (cf)
2995 ctxt->eflags |= X86_EFLAGS_CF;
2996 if (af)
2997 ctxt->eflags |= X86_EFLAGS_AF;
2998 return X86EMUL_CONTINUE;
2999}
3000
a035d5c6
PB		 3001static int em_aam(struct x86_emulate_ctxt *ctxt)
3002{
3003 u8 al, ah;
3004
3005 if (ctxt->src.val == 0)
3006 return emulate_de(ctxt);
3007
3008 al = ctxt->dst.val & 0xff;
3009 ah = al / ctxt->src.val;
3010 al %= ctxt->src.val;
3011
3012 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3013
3014 /* Set PF, ZF, SF */
3015 ctxt->src.type = OP_IMM;
3016 ctxt->src.val = 0;
3017 ctxt->src.bytes = 1;
3018 fastop(ctxt, em_or);
3019
3020 return X86EMUL_CONTINUE;
3021}
3022
7f662273
GN		 3023static int em_aad(struct x86_emulate_ctxt *ctxt)
3024{
3025 u8 al = ctxt->dst.val & 0xff;
3026 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3027
3028 al = (al + (ah * ctxt->src.val)) & 0xff;
3029
3030 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3031
f583c29b
GN		 3032 /* Set PF, ZF, SF */
3033 ctxt->src.type = OP_IMM;
3034 ctxt->src.val = 0;
3035 ctxt->src.bytes = 1;
3036 fastop(ctxt, em_or);
7f662273
GN		 3037
3038 return X86EMUL_CONTINUE;
3039}
3040
d4ddafcd
TY		 3041static int em_call(struct x86_emulate_ctxt *ctxt)
3042{
234f3ce4 3043 int rc;
d4ddafcd
TY		 3044 long rel = ctxt->src.val;
3045
3046 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3047 rc = jmp_rel(ctxt, rel);
3048 if (rc != X86EMUL_CONTINUE)
3049 return rc;
d4ddafcd
TY		 3050 return em_push(ctxt);
3051}
3052
0ef753b8
AK		 3053static int em_call_far(struct x86_emulate_ctxt *ctxt)
3054{
0ef753b8
AK		 3055 u16 sel, old_cs;
3056 ulong old_eip;
3057 int rc;
d1442d85
NA		 3058 struct desc_struct old_desc, new_desc;
3059 const struct x86_emulate_ops *ops = ctxt->ops;
3060 int cpl = ctxt->ops->cpl(ctxt);
82268083 3061 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3062
9dac77fa 3063 old_eip = ctxt->_eip;
d1442d85 3064 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3065
9dac77fa 3066 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3067 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3068 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3069 if (rc != X86EMUL_CONTINUE)
80976dbb 3070 return rc;
0ef753b8 3071
d50eaa18 3072 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3073 if (rc != X86EMUL_CONTINUE)
3074 goto fail;
0ef753b8 3075
9dac77fa 3076 ctxt->src.val = old_cs;
4487b3b4 3077 rc = em_push(ctxt);
0ef753b8 3078 if (rc != X86EMUL_CONTINUE)
d1442d85 3079 goto fail;
0ef753b8 3080
9dac77fa 3081 ctxt->src.val = old_eip;
d1442d85
NA		 3082 rc = em_push(ctxt);
3083 /* If we failed, we tainted the memory, but the very least we should
3084 restore cs */
82268083
NA		 3085 if (rc != X86EMUL_CONTINUE) {
3086 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3087 goto fail;
82268083 3088 }
d1442d85
NA		 3089 return rc;
3090fail:
3091 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3092 ctxt->mode = prev_mode;
d1442d85
NA		 3093 return rc;
3094
0ef753b8
AK		 3095}
3096
40ece7c7
AK		 3097static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3098{
40ece7c7 3099 int rc;
234f3ce4 3100 unsigned long eip;
40ece7c7 3101
234f3ce4
NA		 3102 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3103 if (rc != X86EMUL_CONTINUE)
3104 return rc;
3105 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3106 if (rc != X86EMUL_CONTINUE)
3107 return rc;
5ad105e5 3108 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3109 return X86EMUL_CONTINUE;
3110}
3111
e4f973ae
TY		 3112static int em_xchg(struct x86_emulate_ctxt *ctxt)
3113{
e4f973ae 3114 /* Write back the register source. */
9dac77fa
AK		 3115 ctxt->src.val = ctxt->dst.val;
3116 write_register_operand(&ctxt->src);
e4f973ae
TY		 3117
3118 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3119 ctxt->dst.val = ctxt->src.orig_val;
3120 ctxt->lock_prefix = 1;
e4f973ae
TY		 3121 return X86EMUL_CONTINUE;
3122}
3123
5c82aa29
AK		 3124static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3125{
9dac77fa 3126 ctxt->dst.val = ctxt->src2.val;
4d758349 3127 return fastop(ctxt, em_imul);
5c82aa29
AK		 3128}
3129
61429142
AK		 3130static int em_cwd(struct x86_emulate_ctxt *ctxt)
3131{
9dac77fa
AK		 3132 ctxt->dst.type = OP_REG;
3133 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3134 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3135 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3136
3137 return X86EMUL_CONTINUE;
3138}
3139
48bb5d3c
AK		 3140static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3141{
48bb5d3c
AK		 3142 u64 tsc = 0;
3143
717746e3 3144 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3145 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3146 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3147 return X86EMUL_CONTINUE;
3148}
3149
222d21aa
AK		 3150static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3151{
3152 u64 pmc;
3153
dd856efa 3154 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3155 return emulate_gp(ctxt, 0);
dd856efa
AK		 3156 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3157 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3158 return X86EMUL_CONTINUE;
3159}
3160
b9eac5f4
AK		 3161static int em_mov(struct x86_emulate_ctxt *ctxt)
3162{
54cfdb3e 3163 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3164 return X86EMUL_CONTINUE;
3165}
3166
84cffe49
BP		 3167#define FFL(x) bit(X86_FEATURE_##x)
3168
3169static int em_movbe(struct x86_emulate_ctxt *ctxt)
3170{
3171 u32 ebx, ecx, edx, eax = 1;
3172 u16 tmp;
3173
3174 /*
3175 * Check MOVBE is set in the guest-visible CPUID leaf.
3176 */
3177 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3178 if (!(ecx & FFL(MOVBE)))
3179 return emulate_ud(ctxt);
3180
3181 switch (ctxt->op_bytes) {
3182 case 2:
3183 /*
3184 * From MOVBE definition: "...When the operand size is 16 bits,
3185 * the upper word of the destination register remains unchanged
3186 * ..."
3187 *
3188 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3189 * rules so we have to do the operation almost per hand.
3190 */
3191 tmp = (u16)ctxt->src.val;
3192 ctxt->dst.val &= ~0xffffUL;
3193 ctxt->dst.val |= (unsigned long)swab16(tmp);
3194 break;
3195 case 4:
3196 ctxt->dst.val = swab32((u32)ctxt->src.val);
3197 break;
3198 case 8:
3199 ctxt->dst.val = swab64(ctxt->src.val);
3200 break;
3201 default:
592f0858 3202 BUG();
84cffe49
BP		 3203 }
3204 return X86EMUL_CONTINUE;
3205}
3206
bc00f8d2
TY		 3207static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3208{
3209 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3210 return emulate_gp(ctxt, 0);
3211
3212 /* Disable writeback. */
3213 ctxt->dst.type = OP_NONE;
3214 return X86EMUL_CONTINUE;
3215}
3216
3217static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3218{
3219 unsigned long val;
3220
3221 if (ctxt->mode == X86EMUL_MODE_PROT64)
3222 val = ctxt->src.val & ~0ULL;
3223 else
3224 val = ctxt->src.val & ~0U;
3225
3226 /* #UD condition is already handled. */
3227 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3228 return emulate_gp(ctxt, 0);
3229
3230 /* Disable writeback. */
3231 ctxt->dst.type = OP_NONE;
3232 return X86EMUL_CONTINUE;
3233}
3234
e1e210b0
TY		 3235static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3236{
3237 u64 msr_data;
3238
dd856efa
AK		 3239 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3240 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3241 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3242 return emulate_gp(ctxt, 0);
3243
3244 return X86EMUL_CONTINUE;
3245}
3246
3247static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3248{
3249 u64 msr_data;
3250
dd856efa 3251 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3252 return emulate_gp(ctxt, 0);
3253
dd856efa
AK		 3254 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3255 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3256 return X86EMUL_CONTINUE;
3257}
3258
1bd5f469
TY		 3259static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3260{
9dac77fa 3261 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3262 return emulate_ud(ctxt);
3263
9dac77fa 3264 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3265 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3266 ctxt->dst.bytes = 2;
1bd5f469
TY		 3267 return X86EMUL_CONTINUE;
3268}
3269
3270static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3271{
9dac77fa 3272 u16 sel = ctxt->src.val;
1bd5f469 3273
9dac77fa 3274 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3275 return emulate_ud(ctxt);
3276
9dac77fa 3277 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3278 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3279
3280 /* Disable writeback. */
9dac77fa
AK		 3281 ctxt->dst.type = OP_NONE;
3282 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3283}
3284
a14e579f
AK		 3285static int em_lldt(struct x86_emulate_ctxt *ctxt)
3286{
3287 u16 sel = ctxt->src.val;
3288
3289 /* Disable writeback. */
3290 ctxt->dst.type = OP_NONE;
3291 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3292}
3293
80890006
AK		 3294static int em_ltr(struct x86_emulate_ctxt *ctxt)
3295{
3296 u16 sel = ctxt->src.val;
3297
3298 /* Disable writeback. */
3299 ctxt->dst.type = OP_NONE;
3300 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3301}
3302
38503911
AK		 3303static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3304{
9fa088f4
AK		 3305 int rc;
3306 ulong linear;
3307
9dac77fa 3308 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3309 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3310 ctxt->ops->invlpg(ctxt, linear);
38503911 3311 /* Disable writeback. */
9dac77fa 3312 ctxt->dst.type = OP_NONE;
38503911
AK		 3313 return X86EMUL_CONTINUE;
3314}
3315
2d04a05b
AK		 3316static int em_clts(struct x86_emulate_ctxt *ctxt)
3317{
3318 ulong cr0;
3319
3320 cr0 = ctxt->ops->get_cr(ctxt, 0);
3321 cr0 &= ~X86_CR0_TS;
3322 ctxt->ops->set_cr(ctxt, 0, cr0);
3323 return X86EMUL_CONTINUE;
3324}
3325
b34a8051 3326static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3327{
0f54a321 3328 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3329
26d05cc7
AK		 3330 if (rc != X86EMUL_CONTINUE)
3331 return rc;
3332
3333 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3334 ctxt->_eip = ctxt->eip;
26d05cc7 3335 /* Disable writeback. */
9dac77fa 3336 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3337 return X86EMUL_CONTINUE;
3338}
3339
96051572
AK		 3340static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3341 void (*get)(struct x86_emulate_ctxt *ctxt,
3342 struct desc_ptr *ptr))
3343{
3344 struct desc_ptr desc_ptr;
3345
3346 if (ctxt->mode == X86EMUL_MODE_PROT64)
3347 ctxt->op_bytes = 8;
3348 get(ctxt, &desc_ptr);
3349 if (ctxt->op_bytes == 2) {
3350 ctxt->op_bytes = 4;
3351 desc_ptr.address &= 0x00ffffff;
3352 }
3353 /* Disable writeback. */
3354 ctxt->dst.type = OP_NONE;
3355 return segmented_write(ctxt, ctxt->dst.addr.mem,
3356 &desc_ptr, 2 + ctxt->op_bytes);
3357}
3358
3359static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3360{
3361 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3362}
3363
3364static int em_sidt(struct x86_emulate_ctxt *ctxt)
3365{
3366 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3367}
3368
5b7f6a1e 3369static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3370{
26d05cc7
AK		 3371 struct desc_ptr desc_ptr;
3372 int rc;
3373
510425ff
AK		 3374 if (ctxt->mode == X86EMUL_MODE_PROT64)
3375 ctxt->op_bytes = 8;
9dac77fa 3376 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3377 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3378 ctxt->op_bytes);
26d05cc7
AK		 3379 if (rc != X86EMUL_CONTINUE)
3380 return rc;
9a9abf6b
NA		 3381 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3382 is_noncanonical_address(desc_ptr.address))
3383 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3384 if (lgdt)
3385 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3386 else
3387 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3388 /* Disable writeback. */
9dac77fa 3389 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3390 return X86EMUL_CONTINUE;
3391}
3392
5b7f6a1e
NA		 3393static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3394{
3395 return em_lgdt_lidt(ctxt, true);
3396}
3397
26d05cc7
AK		 3398static int em_lidt(struct x86_emulate_ctxt *ctxt)
3399{
5b7f6a1e 3400 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3401}
3402
3403static int em_smsw(struct x86_emulate_ctxt *ctxt)
3404{
32e94d06
NA		 3405 if (ctxt->dst.type == OP_MEM)
3406 ctxt->dst.bytes = 2;
9dac77fa 3407 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3408 return X86EMUL_CONTINUE;
3409}
3410
3411static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3412{
26d05cc7 3413 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3414 | (ctxt->src.val & 0x0f));
3415 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3416 return X86EMUL_CONTINUE;
3417}
3418
d06e03ad
TY		 3419static int em_loop(struct x86_emulate_ctxt *ctxt)
3420{
234f3ce4
NA		 3421 int rc = X86EMUL_CONTINUE;
3422
01485a22 3423 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3424 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3425 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3426 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3427
234f3ce4 3428 return rc;
d06e03ad
TY		 3429}
3430
3431static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3432{
234f3ce4
NA		 3433 int rc = X86EMUL_CONTINUE;
3434
dd856efa 3435 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3436 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3437
234f3ce4 3438 return rc;
d06e03ad
TY		 3439}
3440
d7841a4b
TY		 3441static int em_in(struct x86_emulate_ctxt *ctxt)
3442{
3443 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3444 &ctxt->dst.val))
3445 return X86EMUL_IO_NEEDED;
3446
3447 return X86EMUL_CONTINUE;
3448}
3449
3450static int em_out(struct x86_emulate_ctxt *ctxt)
3451{
3452 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3453 &ctxt->src.val, 1);
3454 /* Disable writeback. */
3455 ctxt->dst.type = OP_NONE;
3456 return X86EMUL_CONTINUE;
3457}
3458
f411e6cd
TY		 3459static int em_cli(struct x86_emulate_ctxt *ctxt)
3460{
3461 if (emulator_bad_iopl(ctxt))
3462 return emulate_gp(ctxt, 0);
3463
3464 ctxt->eflags &= ~X86_EFLAGS_IF;
3465 return X86EMUL_CONTINUE;
3466}
3467
3468static int em_sti(struct x86_emulate_ctxt *ctxt)
3469{
3470 if (emulator_bad_iopl(ctxt))
3471 return emulate_gp(ctxt, 0);
3472
3473 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3474 ctxt->eflags |= X86_EFLAGS_IF;
3475 return X86EMUL_CONTINUE;
3476}
3477
6d6eede4
AK		 3478static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3479{
3480 u32 eax, ebx, ecx, edx;
3481
dd856efa
AK		 3482 eax = reg_read(ctxt, VCPU_REGS_RAX);
3483 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3484 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3485 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3486 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3487 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3488 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3489 return X86EMUL_CONTINUE;
3490}
3491
98f73630
PB		 3492static int em_sahf(struct x86_emulate_ctxt *ctxt)
3493{
3494 u32 flags;
3495
3496 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3497 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3498
3499 ctxt->eflags &= ~0xffUL;
3500 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3501 return X86EMUL_CONTINUE;
3502}
3503
2dd7caa0
AK		 3504static int em_lahf(struct x86_emulate_ctxt *ctxt)
3505{
dd856efa
AK		 3506 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3507 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3508 return X86EMUL_CONTINUE;
3509}
3510
9299836e
AK		 3511static int em_bswap(struct x86_emulate_ctxt *ctxt)
3512{
3513 switch (ctxt->op_bytes) {
3514#ifdef CONFIG_X86_64
3515 case 8:
3516 asm("bswap %0" : "+r"(ctxt->dst.val));
3517 break;
3518#endif
3519 default:
3520 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3521 break;
3522 }
3523 return X86EMUL_CONTINUE;
3524}
3525
13e457e0
NA		 3526static int em_clflush(struct x86_emulate_ctxt *ctxt)
3527{
3528 /* emulating clflush regardless of cpuid */
3529 return X86EMUL_CONTINUE;
3530}
3531
2276b511
NA		 3532static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3533{
3534 ctxt->dst.val = (s32) ctxt->src.val;
3535 return X86EMUL_CONTINUE;
3536}
3537
cfec82cb
JR		 3538static bool valid_cr(int nr)
3539{
3540 switch (nr) {
3541 case 0:
3542 case 2 ... 4:
3543 case 8:
3544 return true;
3545 default:
3546 return false;
3547 }
3548}
3549
3550static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3551{
9dac77fa 3552 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3553 return emulate_ud(ctxt);
3554
3555 return X86EMUL_CONTINUE;
3556}
3557
3558static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3559{
9dac77fa
AK		 3560 u64 new_val = ctxt->src.val64;
3561 int cr = ctxt->modrm_reg;
c2ad2bb3 3562 u64 efer = 0;
cfec82cb
JR		 3563
3564 static u64 cr_reserved_bits[] = {
3565 0xffffffff00000000ULL,
3566 0, 0, 0, /* CR3 checked later */
3567 CR4_RESERVED_BITS,
3568 0, 0, 0,
3569 CR8_RESERVED_BITS,
3570 };
3571
3572 if (!valid_cr(cr))
3573 return emulate_ud(ctxt);
3574
3575 if (new_val & cr_reserved_bits[cr])
3576 return emulate_gp(ctxt, 0);
3577
3578 switch (cr) {
3579 case 0: {
c2ad2bb3 3580 u64 cr4;
cfec82cb
JR		 3581 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3582 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3583 return emulate_gp(ctxt, 0);
3584
717746e3
AK		 3585 cr4 = ctxt->ops->get_cr(ctxt, 4);
3586 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3587
3588 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3589 !(cr4 & X86_CR4_PAE))
3590 return emulate_gp(ctxt, 0);
3591
3592 break;
3593 }
3594 case 3: {
3595 u64 rsvd = 0;
3596
c2ad2bb3
AK		 3597 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3598 if (efer & EFER_LMA)
9d88fca7 3599 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3600
3601 if (new_val & rsvd)
3602 return emulate_gp(ctxt, 0);
3603
3604 break;
3605 }
3606 case 4: {
717746e3 3607 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3608
3609 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3610 return emulate_gp(ctxt, 0);
3611
3612 break;
3613 }
3614 }
3615
3616 return X86EMUL_CONTINUE;
3617}
3618
3b88e41a
JR		 3619static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3620{
3621 unsigned long dr7;
3622
717746e3 3623 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3624
3625 /* Check if DR7.Global_Enable is set */
3626 return dr7 & (1 << 13);
3627}
3628
3629static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3630{
9dac77fa 3631 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3632 u64 cr4;
3633
3634 if (dr > 7)
3635 return emulate_ud(ctxt);
3636
717746e3 3637 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3638 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3639 return emulate_ud(ctxt);
3640
6d2a0526
NA		 3641 if (check_dr7_gd(ctxt)) {
3642 ulong dr6;
3643
3644 ctxt->ops->get_dr(ctxt, 6, &dr6);
3645 dr6 &= ~15;
3646 dr6 |= DR6_BD | DR6_RTM;
3647 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3648 return emulate_db(ctxt);
6d2a0526 3649 }
3b88e41a
JR		 3650
3651 return X86EMUL_CONTINUE;
3652}
3653
3654static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3655{
9dac77fa
AK		 3656 u64 new_val = ctxt->src.val64;
3657 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3658
3659 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3660 return emulate_gp(ctxt, 0);
3661
3662 return check_dr_read(ctxt);
3663}
3664
01de8b09
JR		 3665static int check_svme(struct x86_emulate_ctxt *ctxt)
3666{
3667 u64 efer;
3668
717746e3 3669 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3670
3671 if (!(efer & EFER_SVME))
3672 return emulate_ud(ctxt);
3673
3674 return X86EMUL_CONTINUE;
3675}
3676
3677static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3678{
dd856efa 3679 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3680
3681 /* Valid physical address? */
d4224449 3682 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3683 return emulate_gp(ctxt, 0);
3684
3685 return check_svme(ctxt);
3686}
3687
d7eb8203
JR		 3688static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3689{
717746e3 3690 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3691
717746e3 3692 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3693 return emulate_ud(ctxt);
3694
3695 return X86EMUL_CONTINUE;
3696}
3697
8061252e
JR		 3698static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3699{
717746e3 3700 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3701 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3702
717746e3 3703 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3704 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3705 return emulate_gp(ctxt, 0);
3706
3707 return X86EMUL_CONTINUE;
3708}
3709
f6511935
JR		 3710static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3711{
9dac77fa
AK		 3712 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3713 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3714 return emulate_gp(ctxt, 0);
3715
3716 return X86EMUL_CONTINUE;
3717}
3718
3719static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3720{
9dac77fa
AK		 3721 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3722 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3723 return emulate_gp(ctxt, 0);
3724
3725 return X86EMUL_CONTINUE;
3726}
3727
73fba5f4 3728#define D(_y) { .flags = (_y) }
d40a6898
PB		 3729#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3730#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3731 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3732#define N D(NotImpl)
01de8b09 3733#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3734#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3735#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3736#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 3737#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 3738#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3739#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3740#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3741#define II(_f, _e, _i) \
d40a6898 3742 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3743#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3744 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3745 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3746#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3747
8d8f4e9f 3748#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3749#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3750#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3751#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3752#define I2bvIP(_f, _e, _i, _p) \
3753 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3754
fb864fbc
AK		 3755#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3756 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3757 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3758
0f54a321
NA		 3759static const struct opcode group7_rm0[] = {
3760 N,
b34a8051 3761 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 3762 N, N, N, N, N, N,
3763};
3764
fd0a0d82 3765static const struct opcode group7_rm1[] = {
1c2545be
TY		 3766 DI(SrcNone | Priv, monitor),
3767 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3768 N, N, N, N, N, N,
3769};
3770
fd0a0d82 3771static const struct opcode group7_rm3[] = {
1c2545be 3772 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 3773 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 3774 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3775 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3776 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3777 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3778 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3779 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3780};
6230f7fc 3781
fd0a0d82 3782static const struct opcode group7_rm7[] = {
d7eb8203 3783 N,
1c2545be 3784 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3785 N, N, N, N, N, N,
3786};
d67fc27a 3787
fd0a0d82 3788static const struct opcode group1[] = {
fb864fbc
AK		 3789 F(Lock, em_add),
3790 F(Lock | PageTable, em_or),
3791 F(Lock, em_adc),
3792 F(Lock, em_sbb),
3793 F(Lock | PageTable, em_and),
3794 F(Lock, em_sub),
3795 F(Lock, em_xor),
3796 F(NoWrite, em_cmp),
73fba5f4
AK		 3797};
3798
fd0a0d82 3799static const struct opcode group1A[] = {
ab708099 3800 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3801};
3802
007a3b54
AK		 3803static const struct opcode group2[] = {
3804 F(DstMem | ModRM, em_rol),
3805 F(DstMem | ModRM, em_ror),
3806 F(DstMem | ModRM, em_rcl),
3807 F(DstMem | ModRM, em_rcr),
3808 F(DstMem | ModRM, em_shl),
3809 F(DstMem | ModRM, em_shr),
3810 F(DstMem | ModRM, em_shl),
3811 F(DstMem | ModRM, em_sar),
3812};
3813
fd0a0d82 3814static const struct opcode group3[] = {
fb864fbc
AK		 3815 F(DstMem | SrcImm | NoWrite, em_test),
3816 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3817 F(DstMem | SrcNone | Lock, em_not),
3818 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3819 F(DstXacc | Src2Mem, em_mul_ex),
3820 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3821 F(DstXacc | Src2Mem, em_div_ex),
3822 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3823};
3824
fd0a0d82 3825static const struct opcode group4[] = {
95413dc4
AK		 3826 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3827 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3828 N, N, N, N, N, N,
3829};
3830
fd0a0d82 3831static const struct opcode group5[] = {
95413dc4
AK		 3832 F(DstMem | SrcNone | Lock, em_inc),
3833 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3834 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3835 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3836 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3837 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3838 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3839};
3840
fd0a0d82 3841static const struct opcode group6[] = {
63ea0a49
NA		 3842 DI(Prot | DstMem, sldt),
3843 DI(Prot | DstMem, str),
a14e579f 3844 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3845 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3846 N, N, N, N,
3847};
3848
fd0a0d82 3849static const struct group_dual group7 = { {
606b1c3e
NA		 3850 II(Mov | DstMem, em_sgdt, sgdt),
3851 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3852 II(SrcMem | Priv, em_lgdt, lgdt),
3853 II(SrcMem | Priv, em_lidt, lidt),
3854 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3855 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3856 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3857}, {
0f54a321 3858 EXT(0, group7_rm0),
5ef39c71 3859 EXT(0, group7_rm1),
01de8b09 3860 N, EXT(0, group7_rm3),
1c2545be
TY		 3861 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3862 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3863 EXT(0, group7_rm7),
73fba5f4
AK		 3864} };
3865
fd0a0d82 3866static const struct opcode group8[] = {
73fba5f4 3867 N, N, N, N,
11c363ba
AK		 3868 F(DstMem | SrcImmByte | NoWrite, em_bt),
3869 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3870 F(DstMem | SrcImmByte | Lock, em_btr),
3871 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3872};
3873
fd0a0d82 3874static const struct group_dual group9 = { {
1c2545be 3875 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3876}, {
3877 N, N, N, N, N, N, N, N,
3878} };
3879
fd0a0d82 3880static const struct opcode group11[] = {
1c2545be 3881 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3882 X7(D(Undefined)),
a4d4a7c1
AK		 3883};
3884
13e457e0 3885static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3886 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3887};
3888
3889static const struct group_dual group15 = { {
3890 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3891}, {
3892 N, N, N, N, N, N, N, N,
3893} };
3894
fd0a0d82 3895static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3896 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3897};
3898
39f062ff
NA		 3899static const struct instr_dual instr_dual_0f_2b = {
3900 I(0, em_mov), N
3901};
3902
d5b77069 3903static const struct gprefix pfx_0f_2b = {
39f062ff 3904 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3905};
3906
27ce8258 3907static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3908 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3909};
3910
0a37027e
AW		 3911static const struct gprefix pfx_0f_e7 = {
3912 N, I(Sse, em_mov), N, N,
3913};
3914
045a282c 3915static const struct escape escape_d9 = { {
16bebefe 3916 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3917}, {
3918 /* 0xC0 - 0xC7 */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xC8 - 0xCF */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xD0 - 0xC7 */
3923 N, N, N, N, N, N, N, N,
3924 /* 0xD8 - 0xDF */
3925 N, N, N, N, N, N, N, N,
3926 /* 0xE0 - 0xE7 */
3927 N, N, N, N, N, N, N, N,
3928 /* 0xE8 - 0xEF */
3929 N, N, N, N, N, N, N, N,
3930 /* 0xF0 - 0xF7 */
3931 N, N, N, N, N, N, N, N,
3932 /* 0xF8 - 0xFF */
3933 N, N, N, N, N, N, N, N,
3934} };
3935
3936static const struct escape escape_db = { {
3937 N, N, N, N, N, N, N, N,
3938}, {
3939 /* 0xC0 - 0xC7 */
3940 N, N, N, N, N, N, N, N,
3941 /* 0xC8 - 0xCF */
3942 N, N, N, N, N, N, N, N,
3943 /* 0xD0 - 0xC7 */
3944 N, N, N, N, N, N, N, N,
3945 /* 0xD8 - 0xDF */
3946 N, N, N, N, N, N, N, N,
3947 /* 0xE0 - 0xE7 */
3948 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3949 /* 0xE8 - 0xEF */
3950 N, N, N, N, N, N, N, N,
3951 /* 0xF0 - 0xF7 */
3952 N, N, N, N, N, N, N, N,
3953 /* 0xF8 - 0xFF */
3954 N, N, N, N, N, N, N, N,
3955} };
3956
3957static const struct escape escape_dd = { {
16bebefe 3958 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3959}, {
3960 /* 0xC0 - 0xC7 */
3961 N, N, N, N, N, N, N, N,
3962 /* 0xC8 - 0xCF */
3963 N, N, N, N, N, N, N, N,
3964 /* 0xD0 - 0xC7 */
3965 N, N, N, N, N, N, N, N,
3966 /* 0xD8 - 0xDF */
3967 N, N, N, N, N, N, N, N,
3968 /* 0xE0 - 0xE7 */
3969 N, N, N, N, N, N, N, N,
3970 /* 0xE8 - 0xEF */
3971 N, N, N, N, N, N, N, N,
3972 /* 0xF0 - 0xF7 */
3973 N, N, N, N, N, N, N, N,
3974 /* 0xF8 - 0xFF */
3975 N, N, N, N, N, N, N, N,
3976} };
3977
39f062ff
NA		 3978static const struct instr_dual instr_dual_0f_c3 = {
3979 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3980};
3981
2276b511
NA		 3982static const struct mode_dual mode_dual_63 = {
3983 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
3984};
3985
fd0a0d82 3986static const struct opcode opcode_table[256] = {
73fba5f4 3987 /* 0x00 - 0x07 */
fb864fbc 3988 F6ALU(Lock, em_add),
1cd196ea
AK		 3989 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3990 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3991 /* 0x08 - 0x0F */
fb864fbc 3992 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3993 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3994 N,
73fba5f4 3995 /* 0x10 - 0x17 */
fb864fbc 3996 F6ALU(Lock, em_adc),
1cd196ea
AK		 3997 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3998 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3999 /* 0x18 - 0x1F */
fb864fbc 4000 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4001 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4002 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4003 /* 0x20 - 0x27 */
fb864fbc 4004 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4005 /* 0x28 - 0x2F */
fb864fbc 4006 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4007 /* 0x30 - 0x37 */
fb864fbc 4008 F6ALU(Lock, em_xor), N, N,
73fba5f4 4009 /* 0x38 - 0x3F */
fb864fbc 4010 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4011 /* 0x40 - 0x4F */
95413dc4 4012 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4013 /* 0x50 - 0x57 */
63540382 4014 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4015 /* 0x58 - 0x5F */
c54fe504 4016 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4017 /* 0x60 - 0x67 */
b96a7fad
TY		 4018 I(ImplicitOps | Stack | No64, em_pusha),
4019 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4020 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4021 N, N, N, N,
4022 /* 0x68 - 0x6F */
d46164db
AK		 4023 I(SrcImm | Mov | Stack, em_push),
4024 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4025 I(SrcImmByte | Mov | Stack, em_push),
4026 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4027 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4028 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4029 /* 0x70 - 0x7F */
58b7075d 4030 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4031 /* 0x80 - 0x87 */
1c2545be
TY		 4032 G(ByteOp | DstMem | SrcImm, group1),
4033 G(DstMem | SrcImm, group1),
4034 G(ByteOp | DstMem | SrcImm | No64, group1),
4035 G(DstMem | SrcImmByte, group1),
fb864fbc 4036 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4037 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4038 /* 0x88 - 0x8F */
d5ae7ce8 4039 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4040 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4041 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4042 D(ModRM | SrcMem | NoAccess | DstReg),
4043 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4044 G(0, group1A),
73fba5f4 4045 /* 0x90 - 0x97 */
bf608f88 4046 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4047 /* 0x98 - 0x9F */
61429142 4048 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4049 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4050 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4051 II(ImplicitOps | Stack, em_popf, popf),
4052 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4053 /* 0xA0 - 0xA7 */
b9eac5f4 4054 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4055 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4056 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4057 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4058 /* 0xA8 - 0xAF */
fb864fbc 4059 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4060 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4061 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4062 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4063 /* 0xB0 - 0xB7 */
b9eac5f4 4064 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4065 /* 0xB8 - 0xBF */
5e2c6883 4066 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4067 /* 0xC0 - 0xC7 */
007a3b54 4068 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4069 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4070 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4071 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4072 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4073 G(ByteOp, group11), G(0, group11),
73fba5f4 4074 /* 0xC8 - 0xCF */
612e89f0 4075 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4076 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4077 I(ImplicitOps, em_ret_far),
3c6e276f 4078 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4079 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4080 /* 0xD0 - 0xD7 */
007a3b54
AK		 4081 G(Src2One | ByteOp, group2), G(Src2One, group2),
4082 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4083 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4084 I(DstAcc | SrcImmUByte | No64, em_aad),
4085 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4086 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4087 /* 0xD8 - 0xDF */
045a282c 4088 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4089 /* 0xE0 - 0xE7 */
58b7075d
NA		 4090 X3(I(SrcImmByte | NearBranch, em_loop)),
4091 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4092 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4093 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4094 /* 0xE8 - 0xEF */
58b7075d
NA		 4095 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4096 I(SrcImmFAddr | No64, em_jmp_far),
4097 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4098 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4099 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4100 /* 0xF0 - 0xF7 */
bf608f88 4101 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4102 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4103 G(ByteOp, group3), G(0, group3),
73fba5f4 4104 /* 0xF8 - 0xFF */
f411e6cd
TY		 4105 D(ImplicitOps), D(ImplicitOps),
4106 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4107 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4108};
4109
fd0a0d82 4110static const struct opcode twobyte_table[256] = {
73fba5f4 4111 /* 0x00 - 0x0F */
dee6bb70 4112 G(0, group6), GD(0, &group7), N, N,
b51e974f 4113 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4114 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4115 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4116 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4117 /* 0x10 - 0x1F */
103f98ea 4118 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4119 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4120 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4121 /* 0x20 - 0x2F */
9b88ae99
NA		 4122 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4123 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4124 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4125 check_cr_write),
4126 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4127 check_dr_write),
73fba5f4 4128 N, N, N, N,
27ce8258
IM		 4129 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4130 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4131 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4132 N, N, N, N,
73fba5f4 4133 /* 0x30 - 0x3F */
e1e210b0 4134 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4135 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4136 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4137 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4138 I(ImplicitOps | EmulateOnUD, em_sysenter),
4139 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4140 N, N,
73fba5f4
AK		 4141 N, N, N, N, N, N, N, N,
4142 /* 0x40 - 0x4F */
140bad89 4143 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4144 /* 0x50 - 0x5F */
4145 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4146 /* 0x60 - 0x6F */
aa97bb48
AK		 4147 N, N, N, N,
4148 N, N, N, N,
4149 N, N, N, N,
4150 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4151 /* 0x70 - 0x7F */
aa97bb48
AK		 4152 N, N, N, N,
4153 N, N, N, N,
4154 N, N, N, N,
4155 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4156 /* 0x80 - 0x8F */
58b7075d 4157 X16(D(SrcImm | NearBranch)),
73fba5f4 4158 /* 0x90 - 0x9F */
ee45b58e 4159 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4160 /* 0xA0 - 0xA7 */
1cd196ea 4161 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4162 II(ImplicitOps, em_cpuid, cpuid),
4163 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4164 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4165 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4166 /* 0xA8 - 0xAF */
1cd196ea 4167 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4168 DI(ImplicitOps, rsm),
11c363ba 4169 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4170 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4171 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4172 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4173 /* 0xB0 - 0xB7 */
2fcf5c8a 4174 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4175 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4176 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4177 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4178 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4179 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4180 /* 0xB8 - 0xBF */
4181 N, N,
ce7faab2 4182 G(BitOp, group8),
11c363ba
AK		 4183 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4184 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4185 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4186 /* 0xC0 - 0xC7 */
e47a5f5f 4187 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4188 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4189 N, N, N, GD(0, &group9),
9299836e
AK		 4190 /* 0xC8 - 0xCF */
4191 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4192 /* 0xD0 - 0xDF */
4193 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4194 /* 0xE0 - 0xEF */
0a37027e
AW		 4195 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4196 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4197 /* 0xF0 - 0xFF */
4198 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4199};
4200
39f062ff
NA		 4201static const struct instr_dual instr_dual_0f_38_f0 = {
4202 I(DstReg | SrcMem | Mov, em_movbe), N
4203};
4204
4205static const struct instr_dual instr_dual_0f_38_f1 = {
4206 I(DstMem | SrcReg | Mov, em_movbe), N
4207};
4208
0bc5eedb 4209static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4210 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4211};
4212
4213static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4214 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4215};
4216
4217/*
4218 * Insns below are selected by the prefix which indexed by the third opcode
4219 * byte.
4220 */
4221static const struct opcode opcode_map_0f_38[256] = {
4222 /* 0x00 - 0x7f */
4223 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4224 /* 0x80 - 0xef */
4225 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4226 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4227 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4228 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4229 /* 0xf2 - 0xff */
4230 N, N, X4(N), X8(N)
0bc5eedb
BP		 4231};
4232
73fba5f4
AK		 4233#undef D
4234#undef N
4235#undef G
4236#undef GD
4237#undef I
aa97bb48 4238#undef GP
01de8b09 4239#undef EXT
2276b511 4240#undef MD
2b42fce6 4241#undef ID
73fba5f4 4242
8d8f4e9f 4243#undef D2bv
f6511935 4244#undef D2bvIP
8d8f4e9f 4245#undef I2bv
d7841a4b 4246#undef I2bvIP
d67fc27a 4247#undef I6ALU
8d8f4e9f 4248
9dac77fa 4249static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4250{
4251 unsigned size;
4252
9dac77fa 4253 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4254 if (size == 8)
4255 size = 4;
4256 return size;
4257}
4258
4259static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4260 unsigned size, bool sign_extension)
4261{
39f21ee5
AK		 4262 int rc = X86EMUL_CONTINUE;
4263
4264 op->type = OP_IMM;
4265 op->bytes = size;
9dac77fa 4266 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4267 /* NB. Immediates are sign-extended as necessary. */
4268 switch (op->bytes) {
4269 case 1:
e85a1085 4270 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4271 break;
4272 case 2:
e85a1085 4273 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4274 break;
4275 case 4:
e85a1085 4276 op->val = insn_fetch(s32, ctxt);
39f21ee5 4277 break;
5e2c6883
NA		 4278 case 8:
4279 op->val = insn_fetch(s64, ctxt);
4280 break;
39f21ee5
AK		 4281 }
4282 if (!sign_extension) {
4283 switch (op->bytes) {
4284 case 1:
4285 op->val &= 0xff;
4286 break;
4287 case 2:
4288 op->val &= 0xffff;
4289 break;
4290 case 4:
4291 op->val &= 0xffffffff;
4292 break;
4293 }
4294 }
4295done:
4296 return rc;
4297}
4298
a9945549
AK		 4299static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4300 unsigned d)
4301{
4302 int rc = X86EMUL_CONTINUE;
4303
4304 switch (d) {
4305 case OpReg:
2adb5ad9 4306 decode_register_operand(ctxt, op);
a9945549
AK		 4307 break;
4308 case OpImmUByte:
608aabe3 4309 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4310 break;
4311 case OpMem:
41ddf978 4312 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4313 mem_common:
4314 *op = ctxt->memop;
4315 ctxt->memopp = op;
96888977 4316 if (ctxt->d & BitOp)
a9945549
AK		 4317 fetch_bit_operand(ctxt);
4318 op->orig_val = op->val;
4319 break;
41ddf978 4320 case OpMem64:
aaa05f24 4321 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4322 goto mem_common;
a9945549
AK		 4323 case OpAcc:
4324 op->type = OP_REG;
4325 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4326 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4327 fetch_register_operand(op);
4328 op->orig_val = op->val;
4329 break;
820207c8
AK		 4330 case OpAccLo:
4331 op->type = OP_REG;
4332 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4333 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4334 fetch_register_operand(op);
4335 op->orig_val = op->val;
4336 break;
4337 case OpAccHi:
4338 if (ctxt->d & ByteOp) {
4339 op->type = OP_NONE;
4340 break;
4341 }
4342 op->type = OP_REG;
4343 op->bytes = ctxt->op_bytes;
4344 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4345 fetch_register_operand(op);
4346 op->orig_val = op->val;
4347 break;
a9945549
AK		 4348 case OpDI:
4349 op->type = OP_MEM;
4350 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4351 op->addr.mem.ea =
01485a22 4352 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4353 op->addr.mem.seg = VCPU_SREG_ES;
4354 op->val = 0;
b3356bf0 4355 op->count = 1;
a9945549
AK		 4356 break;
4357 case OpDX:
4358 op->type = OP_REG;
4359 op->bytes = 2;
dd856efa 4360 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4361 fetch_register_operand(op);
4362 break;
4dd6a57d 4363 case OpCL:
d29b9d7e 4364 op->type = OP_IMM;
4dd6a57d 4365 op->bytes = 1;
dd856efa 4366 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4367 break;
4368 case OpImmByte:
4369 rc = decode_imm(ctxt, op, 1, true);
4370 break;
4371 case OpOne:
d29b9d7e 4372 op->type = OP_IMM;
4dd6a57d
AK		 4373 op->bytes = 1;
4374 op->val = 1;
4375 break;
4376 case OpImm:
4377 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4378 break;
5e2c6883
NA		 4379 case OpImm64:
4380 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4381 break;
28867cee
AK		 4382 case OpMem8:
4383 ctxt->memop.bytes = 1;
660696d1 4384 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4385 ctxt->memop.addr.reg = decode_register(ctxt,
4386 ctxt->modrm_rm, true);
660696d1
GN		 4387 fetch_register_operand(&ctxt->memop);
4388 }
28867cee 4389 goto mem_common;
0fe59128
AK		 4390 case OpMem16:
4391 ctxt->memop.bytes = 2;
4392 goto mem_common;
4393 case OpMem32:
4394 ctxt->memop.bytes = 4;
4395 goto mem_common;
4396 case OpImmU16:
4397 rc = decode_imm(ctxt, op, 2, false);
4398 break;
4399 case OpImmU:
4400 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4401 break;
4402 case OpSI:
4403 op->type = OP_MEM;
4404 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4405 op->addr.mem.ea =
01485a22 4406 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4407 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4408 op->val = 0;
b3356bf0 4409 op->count = 1;
0fe59128 4410 break;
7fa57952
PB		 4411 case OpXLat:
4412 op->type = OP_MEM;
4413 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4414 op->addr.mem.ea =
01485a22 4415 address_mask(ctxt,
7fa57952
PB		 4416 reg_read(ctxt, VCPU_REGS_RBX) +
4417 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4418 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4419 op->val = 0;
4420 break;
0fe59128
AK		 4421 case OpImmFAddr:
4422 op->type = OP_IMM;
4423 op->addr.mem.ea = ctxt->_eip;
4424 op->bytes = ctxt->op_bytes + 2;
4425 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4426 break;
4427 case OpMemFAddr:
4428 ctxt->memop.bytes = ctxt->op_bytes + 2;
4429 goto mem_common;
c191a7a0 4430 case OpES:
d29b9d7e 4431 op->type = OP_IMM;
c191a7a0
AK		 4432 op->val = VCPU_SREG_ES;
4433 break;
4434 case OpCS:
d29b9d7e 4435 op->type = OP_IMM;
c191a7a0
AK		 4436 op->val = VCPU_SREG_CS;
4437 break;
4438 case OpSS:
d29b9d7e 4439 op->type = OP_IMM;
c191a7a0
AK		 4440 op->val = VCPU_SREG_SS;
4441 break;
4442 case OpDS:
d29b9d7e 4443 op->type = OP_IMM;
c191a7a0
AK		 4444 op->val = VCPU_SREG_DS;
4445 break;
4446 case OpFS:
d29b9d7e 4447 op->type = OP_IMM;
c191a7a0
AK		 4448 op->val = VCPU_SREG_FS;
4449 break;
4450 case OpGS:
d29b9d7e 4451 op->type = OP_IMM;
c191a7a0
AK		 4452 op->val = VCPU_SREG_GS;
4453 break;
a9945549
AK		 4454 case OpImplicit:
4455 /* Special instructions do their own operand decoding. */
4456 default:
4457 op->type = OP_NONE; /* Disable writeback. */
4458 break;
4459 }
4460
4461done:
4462 return rc;
4463}
4464
ef5d75cc 4465int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4466{
dde7e6d1
AK		 4467 int rc = X86EMUL_CONTINUE;
4468 int mode = ctxt->mode;
46561646 4469 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4470 bool op_prefix = false;
573e80fe 4471 bool has_seg_override = false;
46561646 4472 struct opcode opcode;
dde7e6d1 4473
f09ed83e
AK		 4474 ctxt->memop.type = OP_NONE;
4475 ctxt->memopp = NULL;
9dac77fa 4476 ctxt->_eip = ctxt->eip;
17052f16
PB		 4477 ctxt->fetch.ptr = ctxt->fetch.data;
4478 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4479 ctxt->opcode_len = 1;
dc25e89e 4480 if (insn_len > 0)
9dac77fa 4481 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4482 else {
9506d57d 4483 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4484 if (rc != X86EMUL_CONTINUE)
4485 return rc;
4486 }
dde7e6d1
AK		 4487
4488 switch (mode) {
4489 case X86EMUL_MODE_REAL:
4490 case X86EMUL_MODE_VM86:
4491 case X86EMUL_MODE_PROT16:
4492 def_op_bytes = def_ad_bytes = 2;
4493 break;
4494 case X86EMUL_MODE_PROT32:
4495 def_op_bytes = def_ad_bytes = 4;
4496 break;
4497#ifdef CONFIG_X86_64
4498 case X86EMUL_MODE_PROT64:
4499 def_op_bytes = 4;
4500 def_ad_bytes = 8;
4501 break;
4502#endif
4503 default:
1d2887e2 4504 return EMULATION_FAILED;
dde7e6d1
AK		 4505 }
4506
9dac77fa
AK		 4507 ctxt->op_bytes = def_op_bytes;
4508 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4509
4510 /* Legacy prefixes. */
4511 for (;;) {
e85a1085 4512 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4513 case 0x66: /* operand-size override */
0d7cdee8 4514 op_prefix = true;
dde7e6d1 4515 /* switch between 2/4 bytes */
9dac77fa 4516 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4517 break;
4518 case 0x67: /* address-size override */
4519 if (mode == X86EMUL_MODE_PROT64)
4520 /* switch between 4/8 bytes */
9dac77fa 4521 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4522 else
4523 /* switch between 2/4 bytes */
9dac77fa 4524 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4525 break;
4526 case 0x26: /* ES override */
4527 case 0x2e: /* CS override */
4528 case 0x36: /* SS override */
4529 case 0x3e: /* DS override */
573e80fe
BD		 4530 has_seg_override = true;
4531 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4532 break;
4533 case 0x64: /* FS override */
4534 case 0x65: /* GS override */
573e80fe
BD		 4535 has_seg_override = true;
4536 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4537 break;
4538 case 0x40 ... 0x4f: /* REX */
4539 if (mode != X86EMUL_MODE_PROT64)
4540 goto done_prefixes;
9dac77fa 4541 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4542 continue;
4543 case 0xf0: /* LOCK */
9dac77fa 4544 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4545 break;
4546 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4547 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4548 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4549 break;
4550 default:
4551 goto done_prefixes;
4552 }
4553
4554 /* Any legacy prefix after a REX prefix nullifies its effect. */
4555
9dac77fa 4556 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4557 }
4558
4559done_prefixes:
4560
4561 /* REX prefix. */
9dac77fa
AK		 4562 if (ctxt->rex_prefix & 8)
4563 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4564
4565 /* Opcode byte(s). */
9dac77fa 4566 opcode = opcode_table[ctxt->b];
d3ad6243 4567 /* Two-byte opcode? */
9dac77fa 4568 if (ctxt->b == 0x0f) {
1ce19dc1 4569 ctxt->opcode_len = 2;
e85a1085 4570 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4571 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4572
4573 /* 0F_38 opcode map */
4574 if (ctxt->b == 0x38) {
4575 ctxt->opcode_len = 3;
4576 ctxt->b = insn_fetch(u8, ctxt);
4577 opcode = opcode_map_0f_38[ctxt->b];
4578 }
dde7e6d1 4579 }
9dac77fa 4580 ctxt->d = opcode.flags;
dde7e6d1 4581
9f4260e7
TY		 4582 if (ctxt->d & ModRM)
4583 ctxt->modrm = insn_fetch(u8, ctxt);
4584
7fe864dc
NA		 4585 /* vex-prefix instructions are not implemented */
4586 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4587 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4588 ctxt->d = NotImpl;
4589 }
4590
9dac77fa
AK		 4591 while (ctxt->d & GroupMask) {
4592 switch (ctxt->d & GroupMask) {
46561646 4593 case Group:
9dac77fa 4594 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4595 opcode = opcode.u.group[goffset];
4596 break;
4597 case GroupDual:
9dac77fa
AK		 4598 goffset = (ctxt->modrm >> 3) & 7;
4599 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4600 opcode = opcode.u.gdual->mod3[goffset];
4601 else
4602 opcode = opcode.u.gdual->mod012[goffset];
4603 break;
4604 case RMExt:
9dac77fa 4605 goffset = ctxt->modrm & 7;
01de8b09 4606 opcode = opcode.u.group[goffset];
46561646
AK		 4607 break;
4608 case Prefix:
9dac77fa 4609 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4610 return EMULATION_FAILED;
9dac77fa 4611 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4612 switch (simd_prefix) {
4613 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4614 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4615 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4616 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4617 }
4618 break;
045a282c
GN		 4619 case Escape:
4620 if (ctxt->modrm > 0xbf)
4621 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4622 else
4623 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4624 break;
39f062ff
NA		 4625 case InstrDual:
4626 if ((ctxt->modrm >> 6) == 3)
4627 opcode = opcode.u.idual->mod3;
4628 else
4629 opcode = opcode.u.idual->mod012;
4630 break;
2276b511
NA		 4631 case ModeDual:
4632 if (ctxt->mode == X86EMUL_MODE_PROT64)
4633 opcode = opcode.u.mdual->mode64;
4634 else
4635 opcode = opcode.u.mdual->mode32;
4636 break;
46561646 4637 default:
1d2887e2 4638 return EMULATION_FAILED;
0d7cdee8 4639 }
46561646 4640
b1ea50b2 4641 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4642 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4643 }
4644
e24186e0
PB		 4645 /* Unrecognised? */
4646 if (ctxt->d == 0)
4647 return EMULATION_FAILED;
4648
9dac77fa 4649 ctxt->execute = opcode.u.execute;
dde7e6d1 4650
3a6095a0
NA		 4651 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4652 return EMULATION_FAILED;
4653
d40a6898 4654 if (unlikely(ctxt->d &
ed9aad21
NA		 4655 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4656 No16))) {
d40a6898
PB		 4657 /*
4658 * These are copied unconditionally here, and checked unconditionally
4659 * in x86_emulate_insn.
4660 */
4661 ctxt->check_perm = opcode.check_perm;
4662 ctxt->intercept = opcode.intercept;
dde7e6d1 4663
d40a6898
PB		 4664 if (ctxt->d & NotImpl)
4665 return EMULATION_FAILED;
d867162c 4666
58b7075d
NA		 4667 if (mode == X86EMUL_MODE_PROT64) {
4668 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4669 ctxt->op_bytes = 8;
4670 else if (ctxt->d & NearBranch)
4671 ctxt->op_bytes = 8;
4672 }
7f9b4b75 4673
d40a6898
PB		 4674 if (ctxt->d & Op3264) {
4675 if (mode == X86EMUL_MODE_PROT64)
4676 ctxt->op_bytes = 8;
4677 else
4678 ctxt->op_bytes = 4;
4679 }
4680
ed9aad21
NA		 4681 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4682 ctxt->op_bytes = 4;
4683
d40a6898
PB		 4684 if (ctxt->d & Sse)
4685 ctxt->op_bytes = 16;
4686 else if (ctxt->d & Mmx)
4687 ctxt->op_bytes = 8;
4688 }
1253791d 4689
dde7e6d1 4690 /* ModRM and SIB bytes. */
9dac77fa 4691 if (ctxt->d & ModRM) {
f09ed83e 4692 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4693 if (!has_seg_override) {
4694 has_seg_override = true;
4695 ctxt->seg_override = ctxt->modrm_seg;
4696 }
9dac77fa 4697 } else if (ctxt->d & MemAbs)
f09ed83e 4698 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4699 if (rc != X86EMUL_CONTINUE)
4700 goto done;
4701
573e80fe
BD		 4702 if (!has_seg_override)
4703 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4704
573e80fe 4705 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4706
dde7e6d1
AK		 4707 /*
4708 * Decode and fetch the source operand: register, memory
4709 * or immediate.
4710 */
0fe59128 4711 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4712 if (rc != X86EMUL_CONTINUE)
4713 goto done;
4714
dde7e6d1
AK		 4715 /*
4716 * Decode and fetch the second source operand: register, memory
4717 * or immediate.
4718 */
4dd6a57d 4719 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4720 if (rc != X86EMUL_CONTINUE)
4721 goto done;
4722
dde7e6d1 4723 /* Decode and fetch the destination operand: register or memory. */
a9945549 4724 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4725
41061cdb 4726 if (ctxt->rip_relative)
1c1c35ae
NA		 4727 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4728 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4729
a430c916 4730done:
1d2887e2 4731 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4732}
4733
1cb3f3ae
XG		 4734bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4735{
4736 return ctxt->d & PageTable;
4737}
4738
3e2f65d5
GN		 4739static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4740{
3e2f65d5
GN		 4741 /* The second termination condition only applies for REPE
4742 * and REPNE. Test if the repeat string operation prefix is
4743 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4744 * corresponding termination condition according to:
4745 * - if REPE/REPZ and ZF = 0 then done
4746 * - if REPNE/REPNZ and ZF = 1 then done
4747 */
9dac77fa
AK		 4748 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4749 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4750 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4751 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4752 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4753 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4754 return true;
4755
4756 return false;
4757}
4758
cbe2c9d3
AK		 4759static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4760{
4761 bool fault = false;
4762
4763 ctxt->ops->get_fpu(ctxt);
4764 asm volatile("1: fwait \n\t"
4765 "2: \n\t"
4766 ".pushsection .fixup,\"ax\" \n\t"
4767 "3: \n\t"
4768 "movb $1, %[fault] \n\t"
4769 "jmp 2b \n\t"
4770 ".popsection \n\t"
4771 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4772 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4773 ctxt->ops->put_fpu(ctxt);
4774
4775 if (unlikely(fault))
4776 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4777
4778 return X86EMUL_CONTINUE;
4779}
4780
4781static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4782 struct operand *op)
4783{
4784 if (op->type == OP_MM)
4785 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4786}
4787
e28bbd44
AK		 4788static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4789{
4790 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4791 if (!(ctxt->d & ByteOp))
4792 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4793 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4794 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4795 [fastop]"+S"(fop)
4796 : "c"(ctxt->src2.val));
e28bbd44 4797 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4798 if (!fop) /* exception is returned in fop variable */
4799 return emulate_de(ctxt);
e28bbd44
AK		 4800 return X86EMUL_CONTINUE;
4801}
dd856efa 4802
1498507a
BD		 4803void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4804{
573e80fe
BD		 4805 memset(&ctxt->rip_relative, 0,
4806 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4807
1498507a
BD		 4808 ctxt->io_read.pos = 0;
4809 ctxt->io_read.end = 0;
1498507a
BD		 4810 ctxt->mem_read.end = 0;
4811}
4812
7b105ca2 4813int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4814{
0225fb50 4815 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4816 int rc = X86EMUL_CONTINUE;
9dac77fa 4817 int saved_dst_type = ctxt->dst.type;
8b4caf66 4818
9dac77fa 4819 ctxt->mem_read.pos = 0;
310b5d30 4820
e24186e0
PB		 4821 /* LOCK prefix is allowed only with some instructions */
4822 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4823 rc = emulate_ud(ctxt);
1161624f
GN		 4824 goto done;
4825 }
4826
e24186e0 4827 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4828 rc = emulate_ud(ctxt);
d380a5e4
GN		 4829 goto done;
4830 }
4831
d40a6898
PB		 4832 if (unlikely(ctxt->d &
4833 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4834 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4835 (ctxt->d & Undefined)) {
4836 rc = emulate_ud(ctxt);
4837 goto done;
4838 }
1253791d 4839
d40a6898
PB		 4840 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4841 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4842 rc = emulate_ud(ctxt);
cbe2c9d3 4843 goto done;
d40a6898 4844 }
cbe2c9d3 4845
d40a6898
PB		 4846 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4847 rc = emulate_nm(ctxt);
c4f035c6 4848 goto done;
d40a6898 4849 }
c4f035c6 4850
d40a6898
PB		 4851 if (ctxt->d & Mmx) {
4852 rc = flush_pending_x87_faults(ctxt);
4853 if (rc != X86EMUL_CONTINUE)
4854 goto done;
4855 /*
4856 * Now that we know the fpu is exception safe, we can fetch
4857 * operands from it.
4858 */
4859 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4860 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4861 if (!(ctxt->d & Mov))
4862 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4863 }
e92805ac 4864
685bbf4a 4865 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4866 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4867 X86_ICPT_PRE_EXCEPT);
4868 if (rc != X86EMUL_CONTINUE)
4869 goto done;
4870 }
8ea7d6ae 4871
64a38292
NA		 4872 /* Instruction can only be executed in protected mode */
4873 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4874 rc = emulate_ud(ctxt);
4875 goto done;
4876 }
4877
d40a6898
PB		 4878 /* Privileged instruction can be executed only in CPL=0 */
4879 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4880 if (ctxt->d & PrivUD)
4881 rc = emulate_ud(ctxt);
4882 else
4883 rc = emulate_gp(ctxt, 0);
d09beabd 4884 goto done;
d40a6898 4885 }
d09beabd 4886
d40a6898 4887 /* Do instruction specific permission checks */
685bbf4a 4888 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4889 rc = ctxt->check_perm(ctxt);
4890 if (rc != X86EMUL_CONTINUE)
4891 goto done;
4892 }
4893
685bbf4a 4894 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4895 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4896 X86_ICPT_POST_EXCEPT);
4897 if (rc != X86EMUL_CONTINUE)
4898 goto done;
4899 }
4900
4901 if (ctxt->rep_prefix && (ctxt->d & String)) {
4902 /* All REP prefixes have the same first termination condition */
4903 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4904 ctxt->eip = ctxt->_eip;
4467c3f1 4905 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4906 goto done;
4907 }
b9fa9d6b 4908 }
b9fa9d6b
AK		 4909 }
4910
9dac77fa
AK		 4911 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4912 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4913 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4914 if (rc != X86EMUL_CONTINUE)
8b4caf66 4915 goto done;
9dac77fa 4916 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4917 }
4918
9dac77fa
AK		 4919 if (ctxt->src2.type == OP_MEM) {
4920 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4921 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4922 if (rc != X86EMUL_CONTINUE)
4923 goto done;
4924 }
4925
9dac77fa 4926 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4927 goto special_insn;
4928
4929
9dac77fa 4930 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4931 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4932 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4933 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 4934 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 4935 if (!(ctxt->d & NoWrite) &&
4936 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 4937 ctxt->exception.vector == PF_VECTOR)
4938 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 4939 goto done;
c205fb7d 4940 }
038e51de 4941 }
4ff6f8e6
PB		 4942 /* Copy full 64-bit value for CMPXCHG8B. */
4943 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 4944
018a98db
AK		 4945special_insn:
4946
685bbf4a 4947 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4948 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4949 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4950 if (rc != X86EMUL_CONTINUE)
4951 goto done;
4952 }
4953
b9a1ecb9
NA		 4954 if (ctxt->rep_prefix && (ctxt->d & String))
4955 ctxt->eflags |= EFLG_RF;
4956 else
4957 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4958
9dac77fa 4959 if (ctxt->execute) {
e28bbd44
AK		 4960 if (ctxt->d & Fastop) {
4961 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4962 rc = fastop(ctxt, fop);
4963 if (rc != X86EMUL_CONTINUE)
4964 goto done;
4965 goto writeback;
4966 }
9dac77fa 4967 rc = ctxt->execute(ctxt);
ef65c889
AK		 4968 if (rc != X86EMUL_CONTINUE)
4969 goto done;
4970 goto writeback;
4971 }
4972
1ce19dc1 4973 if (ctxt->opcode_len == 2)
6aa8b732 4974 goto twobyte_insn;
0bc5eedb
BP		 4975 else if (ctxt->opcode_len == 3)
4976 goto threebyte_insn;
6aa8b732 4977
9dac77fa 4978 switch (ctxt->b) {
b2833e3c 4979 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4980 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4981 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4982 break;
7e0b54b1 4983 case 0x8d: /* lea r16/r32, m */
9dac77fa 4984 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4985 break;
3d9e77df 4986 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4987 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4988 ctxt->dst.type = OP_NONE;
4989 else
4990 rc = em_xchg(ctxt);
e4f973ae 4991 break;
e8b6fa70 4992 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4993 switch (ctxt->op_bytes) {
4994 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4995 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4996 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4997 }
4998 break;
6e154e56 4999 case 0xcc: /* int3 */
5c5df76b
TY		 5000 rc = emulate_int(ctxt, 3);
5001 break;
6e154e56 5002 case 0xcd: /* int n */
9dac77fa 5003 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5004 break;
5005 case 0xce: /* into */
5c5df76b
TY		 5006 if (ctxt->eflags & EFLG_OF)
5007 rc = emulate_int(ctxt, 4);
6e154e56 5008 break;
1a52e051 5009 case 0xe9: /* jmp rel */
db5b0762 5010 case 0xeb: /* jmp rel short */
234f3ce4 5011 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5012 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5013 break;
111de5d6 5014 case 0xf4: /* hlt */
6c3287f7 5015 ctxt->ops->halt(ctxt);
19fdfa0d 5016 break;
111de5d6
AK		 5017 case 0xf5: /* cmc */
5018 /* complement carry flag from eflags reg */
5019 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 5020 break;
5021 case 0xf8: /* clc */
5022 ctxt->eflags &= ~EFLG_CF;
111de5d6 5023 break;
8744aa9a
MG		 5024 case 0xf9: /* stc */
5025 ctxt->eflags |= EFLG_CF;
5026 break;
fb4616f4
MG		 5027 case 0xfc: /* cld */
5028 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 5029 break;
5030 case 0xfd: /* std */
5031 ctxt->eflags |= EFLG_DF;
fb4616f4 5032 break;
91269b8f
AK		 5033 default:
5034 goto cannot_emulate;
6aa8b732 5035 }
018a98db 5036
7d9ddaed
AK		 5037 if (rc != X86EMUL_CONTINUE)
5038 goto done;
5039
018a98db 5040writeback:
fb32b1ed
AK		 5041 if (ctxt->d & SrcWrite) {
5042 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5043 rc = writeback(ctxt, &ctxt->src);
5044 if (rc != X86EMUL_CONTINUE)
5045 goto done;
5046 }
ee212297
NA		 5047 if (!(ctxt->d & NoWrite)) {
5048 rc = writeback(ctxt, &ctxt->dst);
5049 if (rc != X86EMUL_CONTINUE)
5050 goto done;
5051 }
018a98db 5052
5cd21917
GN		 5053 /*
5054 * restore dst type in case the decoding will be reused
5055 * (happens for string instruction )
5056 */
9dac77fa 5057 ctxt->dst.type = saved_dst_type;
5cd21917 5058
9dac77fa 5059 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5060 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5061
9dac77fa 5062 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5063 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5064
9dac77fa 5065 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5066 unsigned int count;
9dac77fa 5067 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5068 if ((ctxt->d & SrcMask) == SrcSI)
5069 count = ctxt->src.count;
5070 else
5071 count = ctxt->dst.count;
01485a22 5072 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5073
d2ddd1c4
GN		 5074 if (!string_insn_completed(ctxt)) {
5075 /*
5076 * Re-enter guest when pio read ahead buffer is empty
5077 * or, if it is not used, after each 1024 iteration.
5078 */
dd856efa 5079 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5080 (r->end == 0 || r->end != r->pos)) {
5081 /*
5082 * Reset read cache. Usually happens before
5083 * decode, but since instruction is restarted
5084 * we have to do it here.
5085 */
9dac77fa 5086 ctxt->mem_read.end = 0;
dd856efa 5087 writeback_registers(ctxt);
d2ddd1c4
GN		 5088 return EMULATION_RESTART;
5089 }
5090 goto done; /* skip rip writeback */
0fa6ccbd 5091 }
b9a1ecb9 5092 ctxt->eflags &= ~EFLG_RF;
5cd21917 5093 }
d2ddd1c4 5094
9dac77fa 5095 ctxt->eip = ctxt->_eip;
018a98db
AK		 5096
5097done:
e0ad0b47
PB		 5098 if (rc == X86EMUL_PROPAGATE_FAULT) {
5099 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5100 ctxt->have_exception = true;
e0ad0b47 5101 }
775fde86
JR		 5102 if (rc == X86EMUL_INTERCEPTED)
5103 return EMULATION_INTERCEPTED;
5104
dd856efa
AK		 5105 if (rc == X86EMUL_CONTINUE)
5106 writeback_registers(ctxt);
5107
d2ddd1c4 5108 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5109
5110twobyte_insn:
9dac77fa 5111 switch (ctxt->b) {
018a98db 5112 case 0x09: /* wbinvd */
cfb22375 5113 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5114 break;
5115 case 0x08: /* invd */
018a98db
AK		 5116 case 0x0d: /* GrpP (prefetch) */
5117 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5118 case 0x1f: /* nop */
018a98db
AK		 5119 break;
5120 case 0x20: /* mov cr, reg */
9dac77fa 5121 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5122 break;
6aa8b732 5123 case 0x21: /* mov from dr to reg */
9dac77fa 5124 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5125 break;
6aa8b732 5126 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5127 if (test_cc(ctxt->b, ctxt->eflags))
5128 ctxt->dst.val = ctxt->src.val;
b91aa14d 5129 else if (ctxt->op_bytes != 4)
9dac77fa 5130 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5131 break;
b2833e3c 5132 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5133 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5134 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5135 break;
ee45b58e 5136 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5137 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5138 break;
6aa8b732 5139 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5140 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5141 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5142 : (u16) ctxt->src.val;
6aa8b732 5143 break;
6aa8b732 5144 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5145 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5146 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5147 (s16) ctxt->src.val;
6aa8b732 5148 break;
91269b8f
AK		 5149 default:
5150 goto cannot_emulate;
6aa8b732 5151 }
7d9ddaed 5152
0bc5eedb
BP		 5153threebyte_insn:
5154
7d9ddaed
AK		 5155 if (rc != X86EMUL_CONTINUE)
5156 goto done;
5157
6aa8b732
AK		 5158 goto writeback;
5159
5160cannot_emulate:
a0c0ab2f 5161 return EMULATION_FAILED;
6aa8b732 5162}
dd856efa
AK		 5163
5164void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5165{
5166 invalidate_registers(ctxt);
5167}
5168
5169void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5170{
5171 writeback_registers(ctxt);
5172}
Linux kernel - Deliverables
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