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KVM: x86 emulator: convert single-operand MUL/IMUL to fastop
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 133#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
6aa8b732 164
820207c8
AK		 165#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
166
d0e53325
AK		 167#define X2(x...) x, x
168#define X3(x...) X2(x), x
169#define X4(x...) X2(x), X2(x)
170#define X5(x...) X4(x), x
171#define X6(x...) X4(x), X2(x)
172#define X7(x...) X4(x), X3(x)
173#define X8(x...) X4(x), X4(x)
174#define X16(x...) X8(x), X8(x)
83babbca 175
e28bbd44
AK		 176#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177#define FASTOP_SIZE 8
178
179/*
180 * fastop functions have a special calling convention:
181 *
017da7b6
AK		 182 * dst: rax (in/out)
183 * src: rdx (in/out)
e28bbd44
AK		 184 * src2: rcx (in)
185 * flags: rflags (in/out)
186 *
187 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
188 * different operand sizes can be reached by calculation, rather than a jump
189 * table (which would be bigger than the code).
190 *
191 * fastop functions are declared as taking a never-defined fastop parameter,
192 * so they can't be called from C directly.
193 */
194
195struct fastop;
196
d65b1dee 197struct opcode {
b1ea50b2
AK		 198 u64 flags : 56;
199 u64 intercept : 8;
120df890 200 union {
ef65c889 201 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 202 const struct opcode *group;
203 const struct group_dual *gdual;
204 const struct gprefix *gprefix;
045a282c 205 const struct escape *esc;
e28bbd44 206 void (*fastop)(struct fastop *fake);
120df890 207 } u;
d09beabd 208 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 209};
210
211struct group_dual {
212 struct opcode mod012[8];
213 struct opcode mod3[8];
d65b1dee
AK		 214};
215
0d7cdee8
AK		 216struct gprefix {
217 struct opcode pfx_no;
218 struct opcode pfx_66;
219 struct opcode pfx_f2;
220 struct opcode pfx_f3;
221};
222
045a282c
GN		 223struct escape {
224 struct opcode op[8];
225 struct opcode high[64];
226};
227
6aa8b732 228/* EFLAGS bit definitions. */
d4c6a154
GN		 229#define EFLG_ID (1<<21)
230#define EFLG_VIP (1<<20)
231#define EFLG_VIF (1<<19)
232#define EFLG_AC (1<<18)
b1d86143
AP		 233#define EFLG_VM (1<<17)
234#define EFLG_RF (1<<16)
d4c6a154
GN		 235#define EFLG_IOPL (3<<12)
236#define EFLG_NT (1<<14)
6aa8b732
AK		 237#define EFLG_OF (1<<11)
238#define EFLG_DF (1<<10)
b1d86143 239#define EFLG_IF (1<<9)
d4c6a154 240#define EFLG_TF (1<<8)
6aa8b732
AK		 241#define EFLG_SF (1<<7)
242#define EFLG_ZF (1<<6)
243#define EFLG_AF (1<<4)
244#define EFLG_PF (1<<2)
245#define EFLG_CF (1<<0)
246
62bd430e
MG		 247#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
248#define EFLG_RESERVED_ONE_MASK 2
249
dd856efa
AK		 250static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
251{
252 if (!(ctxt->regs_valid & (1 << nr))) {
253 ctxt->regs_valid |= 1 << nr;
254 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
255 }
256 return ctxt->_regs[nr];
257}
258
259static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
260{
261 ctxt->regs_valid |= 1 << nr;
262 ctxt->regs_dirty |= 1 << nr;
263 return &ctxt->_regs[nr];
264}
265
266static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 reg_read(ctxt, nr);
269 return reg_write(ctxt, nr);
270}
271
272static void writeback_registers(struct x86_emulate_ctxt *ctxt)
273{
274 unsigned reg;
275
276 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
277 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
278}
279
280static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
281{
282 ctxt->regs_dirty = 0;
283 ctxt->regs_valid = 0;
284}
285
6aa8b732
AK		 286/*
287 * Instruction emulation:
288 * Most instructions are emulated directly via a fragment of inline assembly
289 * code. This allows us to save/restore EFLAGS and thus very easily pick up
290 * any modified flags.
291 */
292
05b3e0c2 293#if defined(CONFIG_X86_64)
6aa8b732
AK		 294#define _LO32 "k" /* force 32-bit operand */
295#define _STK "%%rsp" /* stack pointer */
296#elif defined(__i386__)
297#define _LO32 "" /* force 32-bit operand */
298#define _STK "%%esp" /* stack pointer */
299#endif
300
301/*
302 * These EFLAGS bits are restored from saved value during emulation, and
303 * any changes are written back to the saved value after emulation.
304 */
305#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
306
307/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 308#define _PRE_EFLAGS(_sav, _msk, _tmp) \
309 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
310 "movl %"_sav",%"_LO32 _tmp"; " \
311 "push %"_tmp"; " \
312 "push %"_tmp"; " \
313 "movl %"_msk",%"_LO32 _tmp"; " \
314 "andl %"_LO32 _tmp",("_STK"); " \
315 "pushf; " \
316 "notl %"_LO32 _tmp"; " \
317 "andl %"_LO32 _tmp",("_STK"); " \
318 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
319 "pop %"_tmp"; " \
320 "orl %"_LO32 _tmp",("_STK"); " \
321 "popf; " \
322 "pop %"_sav"; "
6aa8b732
AK		 323
324/* After executing instruction: write-back necessary bits in EFLAGS. */
325#define _POST_EFLAGS(_sav, _msk, _tmp) \
326 /* _sav |= EFLAGS & _msk; */ \
327 "pushf; " \
328 "pop %"_tmp"; " \
329 "andl %"_msk",%"_LO32 _tmp"; " \
330 "orl %"_LO32 _tmp",%"_sav"; "
331
dda96d8f
AK		 332#ifdef CONFIG_X86_64
333#define ON64(x) x
334#else
335#define ON64(x)
336#endif
337
a31b9cea 338#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 339 do { \
340 __asm__ __volatile__ ( \
341 _PRE_EFLAGS("0", "4", "2") \
342 _op _suffix " %"_x"3,%1; " \
343 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 344 : "=m" ((ctxt)->eflags), \
345 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 346 "=&r" (_tmp) \
a31b9cea 347 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 348 } while (0)
6b7ad61f
AK		 349
350
6aa8b732 351/* Raw emulation: instruction has two explicit operands. */
a31b9cea 352#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 353 do { \
354 unsigned long _tmp; \
355 \
a31b9cea 356 switch ((ctxt)->dst.bytes) { \
6b7ad61f 357 case 2: \
a31b9cea 358 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 359 break; \
360 case 4: \
a31b9cea 361 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 362 break; \
363 case 8: \
a31b9cea 364 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 365 break; \
366 } \
6aa8b732
AK		 367 } while (0)
368
a31b9cea 369#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 370 do { \
6b7ad61f 371 unsigned long _tmp; \
a31b9cea 372 switch ((ctxt)->dst.bytes) { \
6aa8b732 373 case 1: \
a31b9cea 374 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 375 break; \
376 default: \
a31b9cea 377 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 378 _wx, _wy, _lx, _ly, _qx, _qy); \
379 break; \
380 } \
381 } while (0)
382
383/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 384#define emulate_2op_SrcB(ctxt, _op) \
385 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 386
387/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 388#define emulate_2op_SrcV(ctxt, _op) \
389 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 390
391/* Source operand is word, long or quad sized. */
a31b9cea
AK		 392#define emulate_2op_SrcV_nobyte(ctxt, _op) \
393 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 394
d175226a 395/* Instruction has three operands and one operand is stored in ECX register */
29053a60 396#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 397 do { \
398 unsigned long _tmp; \
761441b9
AK		 399 _type _clv = (ctxt)->src2.val; \
400 _type _srcv = (ctxt)->src.val; \
401 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 402 \
403 __asm__ __volatile__ ( \
404 _PRE_EFLAGS("0", "5", "2") \
405 _op _suffix " %4,%1 \n" \
406 _POST_EFLAGS("0", "5", "2") \
761441b9 407 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 408 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
409 ); \
410 \
761441b9
AK		 411 (ctxt)->src2.val = (unsigned long) _clv; \
412 (ctxt)->src2.val = (unsigned long) _srcv; \
413 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 414 } while (0)
415
761441b9 416#define emulate_2op_cl(ctxt, _op) \
7295261c 417 do { \
761441b9 418 switch ((ctxt)->dst.bytes) { \
7295261c 419 case 2: \
29053a60 420 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 421 break; \
422 case 4: \
29053a60 423 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 424 break; \
425 case 8: \
29053a60 426 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 427 break; \
428 } \
d175226a
GT		 429 } while (0)
430
d1eef45d 431#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 432 do { \
433 unsigned long _tmp; \
434 \
dda96d8f
AK		 435 __asm__ __volatile__ ( \
436 _PRE_EFLAGS("0", "3", "2") \
437 _op _suffix " %1; " \
438 _POST_EFLAGS("0", "3", "2") \
d1eef45d 439 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 440 "=&r" (_tmp) \
441 : "i" (EFLAGS_MASK)); \
442 } while (0)
443
444/* Instruction has only one explicit operand (no source operand). */
d1eef45d 445#define emulate_1op(ctxt, _op) \
dda96d8f 446 do { \
d1eef45d
AK		 447 switch ((ctxt)->dst.bytes) { \
448 case 1: __emulate_1op(ctxt, _op, "b"); break; \
449 case 2: __emulate_1op(ctxt, _op, "w"); break; \
450 case 4: __emulate_1op(ctxt, _op, "l"); break; \
451 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 452 } \
453 } while (0)
454
4d758349
AK		 455static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
456
b7d491e7
AK		 457#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
458#define FOP_RET "ret \n\t"
459
460#define FOP_START(op) \
461 extern void em_##op(struct fastop *fake); \
462 asm(".pushsection .text, \"ax\" \n\t" \
463 ".global em_" #op " \n\t" \
464 FOP_ALIGN \
465 "em_" #op ": \n\t"
466
467#define FOP_END \
468 ".popsection")
469
0bdea068
AK		 470#define FOPNOP() FOP_ALIGN FOP_RET
471
b7d491e7
AK		 472#define FOP1E(op, dst) \
473 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
474
475#define FASTOP1(op) \
476 FOP_START(op) \
477 FOP1E(op##b, al) \
478 FOP1E(op##w, ax) \
479 FOP1E(op##l, eax) \
480 ON64(FOP1E(op##q, rax)) \
481 FOP_END
482
b9fa409b
AK		 483/* 1-operand, using src2 (for MUL/DIV r/m) */
484#define FASTOP1SRC2(op, name) \
485 FOP_START(name) \
486 FOP1E(op, cl) \
487 FOP1E(op, cx) \
488 FOP1E(op, ecx) \
489 ON64(FOP1E(op, rcx)) \
490 FOP_END
491
f7857f35
AK		 492#define FOP2E(op, dst, src) \
493 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
494
495#define FASTOP2(op) \
496 FOP_START(op) \
017da7b6
AK		 497 FOP2E(op##b, al, dl) \
498 FOP2E(op##w, ax, dx) \
499 FOP2E(op##l, eax, edx) \
500 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 501 FOP_END
502
11c363ba
AK		 503/* 2 operand, word only */
504#define FASTOP2W(op) \
505 FOP_START(op) \
506 FOPNOP() \
017da7b6
AK		 507 FOP2E(op##w, ax, dx) \
508 FOP2E(op##l, eax, edx) \
509 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 510 FOP_END
511
007a3b54
AK		 512/* 2 operand, src is CL */
513#define FASTOP2CL(op) \
514 FOP_START(op) \
515 FOP2E(op##b, al, cl) \
516 FOP2E(op##w, ax, cl) \
517 FOP2E(op##l, eax, cl) \
518 ON64(FOP2E(op##q, rax, cl)) \
519 FOP_END
520
0bdea068
AK		 521#define FOP3E(op, dst, src, src2) \
522 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
523
524/* 3-operand, word-only, src2=cl */
525#define FASTOP3WCL(op) \
526 FOP_START(op) \
527 FOPNOP() \
017da7b6
AK		 528 FOP3E(op##w, ax, dx, cl) \
529 FOP3E(op##l, eax, edx, cl) \
530 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 531 FOP_END
532
9ae9feba
AK		 533/* Special case for SETcc - 1 instruction per cc */
534#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
535
536FOP_START(setcc)
537FOP_SETCC(seto)
538FOP_SETCC(setno)
539FOP_SETCC(setc)
540FOP_SETCC(setnc)
541FOP_SETCC(setz)
542FOP_SETCC(setnz)
543FOP_SETCC(setbe)
544FOP_SETCC(setnbe)
545FOP_SETCC(sets)
546FOP_SETCC(setns)
547FOP_SETCC(setp)
548FOP_SETCC(setnp)
549FOP_SETCC(setl)
550FOP_SETCC(setnl)
551FOP_SETCC(setle)
552FOP_SETCC(setnle)
553FOP_END;
554
326f578f
PB		 555FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
556FOP_END;
557
e8f2b1d6 558#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 559 do { \
560 unsigned long _tmp; \
ab2c5ce6
AK		 561 ulong *rax = &ctxt->dst.val; \
562 ulong *rdx = &ctxt->src.val; \
f6b3597b
AK		 563 \
564 __asm__ __volatile__ ( \
565 _PRE_EFLAGS("0", "5", "1") \
566 "1: \n\t" \
567 _op _suffix " %6; " \
568 "2: \n\t" \
569 _POST_EFLAGS("0", "5", "1") \
570 ".pushsection .fixup,\"ax\" \n\t" \
571 "3: movb $1, %4 \n\t" \
572 "jmp 2b \n\t" \
573 ".popsection \n\t" \
574 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 575 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
576 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
ab2c5ce6 577 : "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
f6b3597b
AK		 578 } while (0)
579
3f9f53b0 580/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 581#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 582 do { \
e8f2b1d6 583 switch((ctxt)->src.bytes) { \
7295261c 584 case 1: \
e8f2b1d6 585 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 586 break; \
587 case 2: \
e8f2b1d6 588 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 589 break; \
590 case 4: \
e8f2b1d6 591 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 592 break; \
593 case 8: ON64( \
e8f2b1d6 594 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 595 break; \
596 } \
597 } while (0)
598
8a76d7f2
JR		 599static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
600 enum x86_intercept intercept,
601 enum x86_intercept_stage stage)
602{
603 struct x86_instruction_info info = {
604 .intercept = intercept,
9dac77fa
AK		 605 .rep_prefix = ctxt->rep_prefix,
606 .modrm_mod = ctxt->modrm_mod,
607 .modrm_reg = ctxt->modrm_reg,
608 .modrm_rm = ctxt->modrm_rm,
609 .src_val = ctxt->src.val64,
610 .src_bytes = ctxt->src.bytes,
611 .dst_bytes = ctxt->dst.bytes,
612 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 613 .next_rip = ctxt->eip,
614 };
615
2953538e 616 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 617}
618
f47cfa31
AK		 619static void assign_masked(ulong *dest, ulong src, ulong mask)
620{
621 *dest = (*dest & ~mask) | (src & mask);
622}
623
9dac77fa 624static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 625{
9dac77fa 626 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 627}
628
f47cfa31
AK		 629static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
630{
631 u16 sel;
632 struct desc_struct ss;
633
634 if (ctxt->mode == X86EMUL_MODE_PROT64)
635 return ~0UL;
636 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
637 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
638}
639
612e89f0
AK		 640static int stack_size(struct x86_emulate_ctxt *ctxt)
641{
642 return (__fls(stack_mask(ctxt)) + 1) >> 3;
643}
644
6aa8b732 645/* Access/update address held in a register, based on addressing mode. */
e4706772 646static inline unsigned long
9dac77fa 647address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 648{
9dac77fa 649 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 650 return reg;
651 else
9dac77fa 652 return reg & ad_mask(ctxt);
e4706772
HH		 653}
654
655static inline unsigned long
9dac77fa 656register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 657{
9dac77fa 658 return address_mask(ctxt, reg);
e4706772
HH		 659}
660
5ad105e5
AK		 661static void masked_increment(ulong *reg, ulong mask, int inc)
662{
663 assign_masked(reg, *reg + inc, mask);
664}
665
7a957275 666static inline void
9dac77fa 667register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 668{
5ad105e5
AK		 669 ulong mask;
670
9dac77fa 671 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 672 mask = ~0UL;
7a957275 673 else
5ad105e5
AK		 674 mask = ad_mask(ctxt);
675 masked_increment(reg, mask, inc);
676}
677
678static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
679{
dd856efa 680 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 681}
6aa8b732 682
9dac77fa 683static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 684{
9dac77fa 685 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 686}
098c937b 687
56697687
AK		 688static u32 desc_limit_scaled(struct desc_struct *desc)
689{
690 u32 limit = get_desc_limit(desc);
691
692 return desc->g ? (limit << 12) | 0xfff : limit;
693}
694
9dac77fa 695static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 696{
9dac77fa
AK		 697 ctxt->has_seg_override = true;
698 ctxt->seg_override = seg;
7a5b56df
AK		 699}
700
7b105ca2 701static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 702{
703 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
704 return 0;
705
7b105ca2 706 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 707}
708
9dac77fa 709static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 710{
9dac77fa 711 if (!ctxt->has_seg_override)
7a5b56df
AK		 712 return 0;
713
9dac77fa 714 return ctxt->seg_override;
7a5b56df
AK		 715}
716
35d3d4a1
AK		 717static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
718 u32 error, bool valid)
54b8486f 719{
da9cb575
AK		 720 ctxt->exception.vector = vec;
721 ctxt->exception.error_code = error;
722 ctxt->exception.error_code_valid = valid;
35d3d4a1 723 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 724}
725
3b88e41a
JR		 726static int emulate_db(struct x86_emulate_ctxt *ctxt)
727{
728 return emulate_exception(ctxt, DB_VECTOR, 0, false);
729}
730
35d3d4a1 731static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 732{
35d3d4a1 733 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 734}
735
618ff15d
AK		 736static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
737{
738 return emulate_exception(ctxt, SS_VECTOR, err, true);
739}
740
35d3d4a1 741static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 742{
35d3d4a1 743 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 744}
745
35d3d4a1 746static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 747{
35d3d4a1 748 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 749}
750
34d1f490
AK		 751static int emulate_de(struct x86_emulate_ctxt *ctxt)
752{
35d3d4a1 753 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 754}
755
1253791d
AK		 756static int emulate_nm(struct x86_emulate_ctxt *ctxt)
757{
758 return emulate_exception(ctxt, NM_VECTOR, 0, false);
759}
760
1aa36616
AK		 761static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
762{
763 u16 selector;
764 struct desc_struct desc;
765
766 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
767 return selector;
768}
769
770static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
771 unsigned seg)
772{
773 u16 dummy;
774 u32 base3;
775 struct desc_struct desc;
776
777 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
778 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
779}
780
1c11b376
AK		 781/*
782 * x86 defines three classes of vector instructions: explicitly
783 * aligned, explicitly unaligned, and the rest, which change behaviour
784 * depending on whether they're AVX encoded or not.
785 *
786 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
787 * subject to the same check.
788 */
789static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
790{
791 if (likely(size < 16))
792 return false;
793
794 if (ctxt->d & Aligned)
795 return true;
796 else if (ctxt->d & Unaligned)
797 return false;
798 else if (ctxt->d & Avx)
799 return false;
800 else
801 return true;
802}
803
3d9b938e 804static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 805 struct segmented_address addr,
3d9b938e 806 unsigned size, bool write, bool fetch,
52fd8b44
AK		 807 ulong *linear)
808{
618ff15d
AK		 809 struct desc_struct desc;
810 bool usable;
52fd8b44 811 ulong la;
618ff15d 812 u32 lim;
1aa36616 813 u16 sel;
3a78a4f4 814 unsigned cpl;
52fd8b44 815
7b105ca2 816 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 817 switch (ctxt->mode) {
618ff15d
AK		 818 case X86EMUL_MODE_PROT64:
819 if (((signed long)la << 16) >> 16 != la)
820 return emulate_gp(ctxt, 0);
821 break;
822 default:
1aa36616
AK		 823 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
824 addr.seg);
618ff15d
AK		 825 if (!usable)
826 goto bad;
58b7825b
GN		 827 /* code segment in protected mode or read-only data segment */
828 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
829 || !(desc.type & 2)) && write)
618ff15d
AK		 830 goto bad;
831 /* unreadable code segment */
3d9b938e 832 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 833 goto bad;
834 lim = desc_limit_scaled(&desc);
835 if ((desc.type & 8) || !(desc.type & 4)) {
836 /* expand-up segment */
837 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
838 goto bad;
839 } else {
fc058680 840 /* expand-down segment */
618ff15d
AK		 841 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
842 goto bad;
843 lim = desc.d ? 0xffffffff : 0xffff;
844 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
845 goto bad;
846 }
717746e3 847 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 848 if (!(desc.type & 8)) {
849 /* data segment */
850 if (cpl > desc.dpl)
851 goto bad;
852 } else if ((desc.type & 8) && !(desc.type & 4)) {
853 /* nonconforming code segment */
854 if (cpl != desc.dpl)
855 goto bad;
856 } else if ((desc.type & 8) && (desc.type & 4)) {
857 /* conforming code segment */
858 if (cpl < desc.dpl)
859 goto bad;
860 }
861 break;
862 }
9dac77fa 863 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 864 la &= (u32)-1;
1c11b376
AK		 865 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
866 return emulate_gp(ctxt, 0);
52fd8b44
AK		 867 *linear = la;
868 return X86EMUL_CONTINUE;
618ff15d
AK		 869bad:
870 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 871 return emulate_ss(ctxt, sel);
618ff15d 872 else
0afbe2f8 873 return emulate_gp(ctxt, sel);
52fd8b44
AK		 874}
875
3d9b938e
NE		 876static int linearize(struct x86_emulate_ctxt *ctxt,
877 struct segmented_address addr,
878 unsigned size, bool write,
879 ulong *linear)
880{
881 return __linearize(ctxt, addr, size, write, false, linear);
882}
883
884
3ca3ac4d
AK		 885static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
886 struct segmented_address addr,
887 void *data,
888 unsigned size)
889{
9fa088f4
AK		 890 int rc;
891 ulong linear;
892
83b8795a 893 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 894 if (rc != X86EMUL_CONTINUE)
895 return rc;
0f65dd70 896 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 897}
898
807941b1
TY		 899/*
900 * Fetch the next byte of the instruction being emulated which is pointed to
901 * by ctxt->_eip, then increment ctxt->_eip.
902 *
903 * Also prefetch the remaining bytes of the instruction without crossing page
904 * boundary if they are not in fetch_cache yet.
905 */
906static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 907{
9dac77fa 908 struct fetch_cache *fc = &ctxt->fetch;
62266869 909 int rc;
2fb53ad8 910 int size, cur_size;
62266869 911
807941b1 912 if (ctxt->_eip == fc->end) {
3d9b938e 913 unsigned long linear;
807941b1
TY		 914 struct segmented_address addr = { .seg = VCPU_SREG_CS,
915 .ea = ctxt->_eip };
2fb53ad8 916 cur_size = fc->end - fc->start;
807941b1
TY		 917 size = min(15UL - cur_size,
918 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 919 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 920 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 921 return rc;
ef5d75cc
TY		 922 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
923 size, &ctxt->exception);
7d88bb48 924 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 925 return rc;
2fb53ad8 926 fc->end += size;
62266869 927 }
807941b1
TY		 928 *dest = fc->data[ctxt->_eip - fc->start];
929 ctxt->_eip++;
3e2815e9 930 return X86EMUL_CONTINUE;
62266869
AK		 931}
932
933static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 934 void *dest, unsigned size)
62266869 935{
3e2815e9 936 int rc;
62266869 937
eb3c79e6 938 /* x86 instructions are limited to 15 bytes. */
7d88bb48 939 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 940 return X86EMUL_UNHANDLEABLE;
62266869 941 while (size--) {
807941b1 942 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 943 if (rc != X86EMUL_CONTINUE)
62266869
AK		 944 return rc;
945 }
3e2815e9 946 return X86EMUL_CONTINUE;
62266869
AK		 947}
948
67cbc90d 949/* Fetch next part of the instruction being emulated. */
e85a1085 950#define insn_fetch(_type, _ctxt) \
67cbc90d 951({ unsigned long _x; \
e85a1085 952 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 953 if (rc != X86EMUL_CONTINUE) \
954 goto done; \
67cbc90d
TY		 955 (_type)_x; \
956})
957
807941b1
TY		 958#define insn_fetch_arr(_arr, _size, _ctxt) \
959({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 960 if (rc != X86EMUL_CONTINUE) \
961 goto done; \
67cbc90d
TY		 962})
963
1e3c5cb0
RR		 964/*
965 * Given the 'reg' portion of a ModRM byte, and a register block, return a
966 * pointer into the block that addresses the relevant register.
967 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
968 */
dd856efa 969static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 970 int highbyte_regs)
6aa8b732
AK		 971{
972 void *p;
973
6aa8b732 974 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 975 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
976 else
977 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 978 return p;
979}
980
981static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 982 struct segmented_address addr,
6aa8b732
AK		 983 u16 *size, unsigned long *address, int op_bytes)
984{
985 int rc;
986
987 if (op_bytes == 2)
988 op_bytes = 3;
989 *address = 0;
3ca3ac4d 990 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 991 if (rc != X86EMUL_CONTINUE)
6aa8b732 992 return rc;
30b31ab6 993 addr.ea += 2;
3ca3ac4d 994 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 995 return rc;
996}
997
34b77652
AK		 998FASTOP2(add);
999FASTOP2(or);
1000FASTOP2(adc);
1001FASTOP2(sbb);
1002FASTOP2(and);
1003FASTOP2(sub);
1004FASTOP2(xor);
1005FASTOP2(cmp);
1006FASTOP2(test);
1007
b9fa409b
AK		 1008FASTOP1SRC2(mul, mul_ex);
1009FASTOP1SRC2(imul, imul_ex);
1010
34b77652
AK		 1011FASTOP3WCL(shld);
1012FASTOP3WCL(shrd);
1013
1014FASTOP2W(imul);
1015
1016FASTOP1(not);
1017FASTOP1(neg);
1018FASTOP1(inc);
1019FASTOP1(dec);
1020
1021FASTOP2CL(rol);
1022FASTOP2CL(ror);
1023FASTOP2CL(rcl);
1024FASTOP2CL(rcr);
1025FASTOP2CL(shl);
1026FASTOP2CL(shr);
1027FASTOP2CL(sar);
1028
1029FASTOP2W(bsf);
1030FASTOP2W(bsr);
1031FASTOP2W(bt);
1032FASTOP2W(bts);
1033FASTOP2W(btr);
1034FASTOP2W(btc);
1035
9ae9feba 1036static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1037{
9ae9feba
AK		 1038 u8 rc;
1039 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1040
9ae9feba 1041 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1042 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1043 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1044 return rc;
bbe9abbd
NK		 1045}
1046
91ff3cb4
AK		 1047static void fetch_register_operand(struct operand *op)
1048{
1049 switch (op->bytes) {
1050 case 1:
1051 op->val = *(u8 *)op->addr.reg;
1052 break;
1053 case 2:
1054 op->val = *(u16 *)op->addr.reg;
1055 break;
1056 case 4:
1057 op->val = *(u32 *)op->addr.reg;
1058 break;
1059 case 8:
1060 op->val = *(u64 *)op->addr.reg;
1061 break;
1062 }
1063}
1064
1253791d
AK		 1065static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1066{
1067 ctxt->ops->get_fpu(ctxt);
1068 switch (reg) {
89a87c67
MK		 1069 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1070 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1071 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1072 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1073 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1074 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1075 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1076 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1077#ifdef CONFIG_X86_64
89a87c67
MK		 1078 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1079 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1080 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1081 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1082 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1083 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1084 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1085 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1086#endif
1087 default: BUG();
1088 }
1089 ctxt->ops->put_fpu(ctxt);
1090}
1091
1092static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1093 int reg)
1094{
1095 ctxt->ops->get_fpu(ctxt);
1096 switch (reg) {
89a87c67
MK		 1097 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1098 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1099 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1100 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1101 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1102 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1103 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1104 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1105#ifdef CONFIG_X86_64
89a87c67
MK		 1106 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1107 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1108 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1109 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1110 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1111 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1112 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1113 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1114#endif
1115 default: BUG();
1116 }
1117 ctxt->ops->put_fpu(ctxt);
1118}
1119
cbe2c9d3
AK		 1120static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1121{
1122 ctxt->ops->get_fpu(ctxt);
1123 switch (reg) {
1124 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1125 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1126 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1127 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1128 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1129 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1130 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1131 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1132 default: BUG();
1133 }
1134 ctxt->ops->put_fpu(ctxt);
1135}
1136
1137static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1138{
1139 ctxt->ops->get_fpu(ctxt);
1140 switch (reg) {
1141 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1142 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1143 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1144 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1145 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1146 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1147 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1148 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1149 default: BUG();
1150 }
1151 ctxt->ops->put_fpu(ctxt);
1152}
1153
045a282c
GN		 1154static int em_fninit(struct x86_emulate_ctxt *ctxt)
1155{
1156 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1157 return emulate_nm(ctxt);
1158
1159 ctxt->ops->get_fpu(ctxt);
1160 asm volatile("fninit");
1161 ctxt->ops->put_fpu(ctxt);
1162 return X86EMUL_CONTINUE;
1163}
1164
1165static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1166{
1167 u16 fcw;
1168
1169 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1170 return emulate_nm(ctxt);
1171
1172 ctxt->ops->get_fpu(ctxt);
1173 asm volatile("fnstcw %0": "+m"(fcw));
1174 ctxt->ops->put_fpu(ctxt);
1175
1176 /* force 2 byte destination */
1177 ctxt->dst.bytes = 2;
1178 ctxt->dst.val = fcw;
1179
1180 return X86EMUL_CONTINUE;
1181}
1182
1183static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1184{
1185 u16 fsw;
1186
1187 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1188 return emulate_nm(ctxt);
1189
1190 ctxt->ops->get_fpu(ctxt);
1191 asm volatile("fnstsw %0": "+m"(fsw));
1192 ctxt->ops->put_fpu(ctxt);
1193
1194 /* force 2 byte destination */
1195 ctxt->dst.bytes = 2;
1196 ctxt->dst.val = fsw;
1197
1198 return X86EMUL_CONTINUE;
1199}
1200
1253791d 1201static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1202 struct operand *op)
3c118e24 1203{
9dac77fa
AK		 1204 unsigned reg = ctxt->modrm_reg;
1205 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1206
9dac77fa
AK		 1207 if (!(ctxt->d & ModRM))
1208 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1209
9dac77fa 1210 if (ctxt->d & Sse) {
1253791d
AK		 1211 op->type = OP_XMM;
1212 op->bytes = 16;
1213 op->addr.xmm = reg;
1214 read_sse_reg(ctxt, &op->vec_val, reg);
1215 return;
1216 }
cbe2c9d3
AK		 1217 if (ctxt->d & Mmx) {
1218 reg &= 7;
1219 op->type = OP_MM;
1220 op->bytes = 8;
1221 op->addr.mm = reg;
1222 return;
1223 }
1253791d 1224
3c118e24 1225 op->type = OP_REG;
2adb5ad9 1226 if (ctxt->d & ByteOp) {
dd856efa 1227 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1228 op->bytes = 1;
1229 } else {
dd856efa 1230 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1231 op->bytes = ctxt->op_bytes;
3c118e24 1232 }
91ff3cb4 1233 fetch_register_operand(op);
3c118e24
AK		 1234 op->orig_val = op->val;
1235}
1236
a6e3407b
AK		 1237static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1238{
1239 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1240 ctxt->modrm_seg = VCPU_SREG_SS;
1241}
1242
1c73ef66 1243static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1244 struct operand *op)
1c73ef66 1245{
1c73ef66 1246 u8 sib;
f5b4edcd 1247 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1248 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1249 ulong modrm_ea = 0;
1c73ef66 1250
9dac77fa
AK		 1251 if (ctxt->rex_prefix) {
1252 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1253 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1254 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1255 }
1256
9dac77fa
AK		 1257 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1258 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1259 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1260 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1261
9dac77fa 1262 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1263 op->type = OP_REG;
9dac77fa 1264 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1265 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1266 if (ctxt->d & Sse) {
1253791d
AK		 1267 op->type = OP_XMM;
1268 op->bytes = 16;
9dac77fa
AK		 1269 op->addr.xmm = ctxt->modrm_rm;
1270 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1271 return rc;
1272 }
cbe2c9d3
AK		 1273 if (ctxt->d & Mmx) {
1274 op->type = OP_MM;
1275 op->bytes = 8;
1276 op->addr.xmm = ctxt->modrm_rm & 7;
1277 return rc;
1278 }
2dbd0dd7 1279 fetch_register_operand(op);
1c73ef66
AK		 1280 return rc;
1281 }
1282
2dbd0dd7
AK		 1283 op->type = OP_MEM;
1284
9dac77fa 1285 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1286 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1287 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1288 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1289 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1290
1291 /* 16-bit ModR/M decode. */
9dac77fa 1292 switch (ctxt->modrm_mod) {
1c73ef66 1293 case 0:
9dac77fa 1294 if (ctxt->modrm_rm == 6)
e85a1085 1295 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1296 break;
1297 case 1:
e85a1085 1298 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1299 break;
1300 case 2:
e85a1085 1301 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1302 break;
1303 }
9dac77fa 1304 switch (ctxt->modrm_rm) {
1c73ef66 1305 case 0:
2dbd0dd7 1306 modrm_ea += bx + si;
1c73ef66
AK		 1307 break;
1308 case 1:
2dbd0dd7 1309 modrm_ea += bx + di;
1c73ef66
AK		 1310 break;
1311 case 2:
2dbd0dd7 1312 modrm_ea += bp + si;
1c73ef66
AK		 1313 break;
1314 case 3:
2dbd0dd7 1315 modrm_ea += bp + di;
1c73ef66
AK		 1316 break;
1317 case 4:
2dbd0dd7 1318 modrm_ea += si;
1c73ef66
AK		 1319 break;
1320 case 5:
2dbd0dd7 1321 modrm_ea += di;
1c73ef66
AK		 1322 break;
1323 case 6:
9dac77fa 1324 if (ctxt->modrm_mod != 0)
2dbd0dd7 1325 modrm_ea += bp;
1c73ef66
AK		 1326 break;
1327 case 7:
2dbd0dd7 1328 modrm_ea += bx;
1c73ef66
AK		 1329 break;
1330 }
9dac77fa
AK		 1331 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1332 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1333 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1334 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1335 } else {
1336 /* 32/64-bit ModR/M decode. */
9dac77fa 1337 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1338 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1339 index_reg |= (sib >> 3) & 7;
1340 base_reg |= sib & 7;
1341 scale = sib >> 6;
1342
9dac77fa 1343 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1344 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1345 else {
dd856efa 1346 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1347 adjust_modrm_seg(ctxt, base_reg);
1348 }
dc71d0f1 1349 if (index_reg != 4)
dd856efa 1350 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1351 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1352 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1353 ctxt->rip_relative = 1;
a6e3407b
AK		 1354 } else {
1355 base_reg = ctxt->modrm_rm;
dd856efa 1356 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1357 adjust_modrm_seg(ctxt, base_reg);
1358 }
9dac77fa 1359 switch (ctxt->modrm_mod) {
1c73ef66 1360 case 0:
9dac77fa 1361 if (ctxt->modrm_rm == 5)
e85a1085 1362 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1363 break;
1364 case 1:
e85a1085 1365 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1366 break;
1367 case 2:
e85a1085 1368 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1369 break;
1370 }
1371 }
90de84f5 1372 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1373done:
1374 return rc;
1375}
1376
1377static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1378 struct operand *op)
1c73ef66 1379{
3e2815e9 1380 int rc = X86EMUL_CONTINUE;
1c73ef66 1381
2dbd0dd7 1382 op->type = OP_MEM;
9dac77fa 1383 switch (ctxt->ad_bytes) {
1c73ef66 1384 case 2:
e85a1085 1385 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1386 break;
1387 case 4:
e85a1085 1388 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1389 break;
1390 case 8:
e85a1085 1391 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1392 break;
1393 }
1394done:
1395 return rc;
1396}
1397
9dac77fa 1398static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1399{
7129eeca 1400 long sv = 0, mask;
35c843c4 1401
9dac77fa
AK		 1402 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1403 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1404
9dac77fa
AK		 1405 if (ctxt->src.bytes == 2)
1406 sv = (s16)ctxt->src.val & (s16)mask;
1407 else if (ctxt->src.bytes == 4)
1408 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1409
9dac77fa 1410 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1411 }
ba7ff2b7
WY		 1412
1413 /* only subword offset */
9dac77fa 1414 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1415}
1416
dde7e6d1 1417static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1418 unsigned long addr, void *dest, unsigned size)
6aa8b732 1419{
dde7e6d1 1420 int rc;
9dac77fa 1421 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1422
f23b070e
XG		 1423 if (mc->pos < mc->end)
1424 goto read_cached;
6aa8b732 1425
f23b070e
XG		 1426 WARN_ON((mc->end + size) >= sizeof(mc->data));
1427
1428 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1429 &ctxt->exception);
1430 if (rc != X86EMUL_CONTINUE)
1431 return rc;
1432
1433 mc->end += size;
1434
1435read_cached:
1436 memcpy(dest, mc->data + mc->pos, size);
1437 mc->pos += size;
dde7e6d1
AK		 1438 return X86EMUL_CONTINUE;
1439}
6aa8b732 1440
3ca3ac4d
AK		 1441static int segmented_read(struct x86_emulate_ctxt *ctxt,
1442 struct segmented_address addr,
1443 void *data,
1444 unsigned size)
1445{
9fa088f4
AK		 1446 int rc;
1447 ulong linear;
1448
83b8795a 1449 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1450 if (rc != X86EMUL_CONTINUE)
1451 return rc;
7b105ca2 1452 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1453}
1454
1455static int segmented_write(struct x86_emulate_ctxt *ctxt,
1456 struct segmented_address addr,
1457 const void *data,
1458 unsigned size)
1459{
9fa088f4
AK		 1460 int rc;
1461 ulong linear;
1462
83b8795a 1463 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1464 if (rc != X86EMUL_CONTINUE)
1465 return rc;
0f65dd70
AK		 1466 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1467 &ctxt->exception);
3ca3ac4d
AK		 1468}
1469
1470static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1471 struct segmented_address addr,
1472 const void *orig_data, const void *data,
1473 unsigned size)
1474{
9fa088f4
AK		 1475 int rc;
1476 ulong linear;
1477
83b8795a 1478 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1479 if (rc != X86EMUL_CONTINUE)
1480 return rc;
0f65dd70
AK		 1481 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1482 size, &ctxt->exception);
3ca3ac4d
AK		 1483}
1484
dde7e6d1 1485static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1486 unsigned int size, unsigned short port,
1487 void *dest)
1488{
9dac77fa 1489 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1490
dde7e6d1 1491 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1492 unsigned int in_page, n;
9dac77fa 1493 unsigned int count = ctxt->rep_prefix ?
dd856efa 1494 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1495 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1496 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1497 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1498 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1499 count);
1500 if (n == 0)
1501 n = 1;
1502 rc->pos = rc->end = 0;
7b105ca2 1503 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1504 return 0;
1505 rc->end = n * size;
6aa8b732
AK		 1506 }
1507
b3356bf0
GN		 1508 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1509 ctxt->dst.data = rc->data + rc->pos;
1510 ctxt->dst.type = OP_MEM_STR;
1511 ctxt->dst.count = (rc->end - rc->pos) / size;
1512 rc->pos = rc->end;
1513 } else {
1514 memcpy(dest, rc->data + rc->pos, size);
1515 rc->pos += size;
1516 }
dde7e6d1
AK		 1517 return 1;
1518}
6aa8b732 1519
7f3d35fd
KW		 1520static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1521 u16 index, struct desc_struct *desc)
1522{
1523 struct desc_ptr dt;
1524 ulong addr;
1525
1526 ctxt->ops->get_idt(ctxt, &dt);
1527
1528 if (dt.size < index * 8 + 7)
1529 return emulate_gp(ctxt, index << 3 | 0x2);
1530
1531 addr = dt.address + index * 8;
1532 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1533 &ctxt->exception);
1534}
1535
dde7e6d1 1536static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1537 u16 selector, struct desc_ptr *dt)
1538{
0225fb50 1539 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1540
dde7e6d1
AK		 1541 if (selector & 1 << 2) {
1542 struct desc_struct desc;
1aa36616
AK		 1543 u16 sel;
1544
dde7e6d1 1545 memset (dt, 0, sizeof *dt);
1aa36616 1546 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1547 return;
e09d082c 1548
dde7e6d1
AK		 1549 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1550 dt->address = get_desc_base(&desc);
1551 } else
4bff1e86 1552 ops->get_gdt(ctxt, dt);
dde7e6d1 1553}
120df890 1554
dde7e6d1
AK		 1555/* allowed just for 8 bytes segments */
1556static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1557 u16 selector, struct desc_struct *desc,
1558 ulong *desc_addr_p)
dde7e6d1
AK		 1559{
1560 struct desc_ptr dt;
1561 u16 index = selector >> 3;
dde7e6d1 1562 ulong addr;
120df890 1563
7b105ca2 1564 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1565
35d3d4a1
AK		 1566 if (dt.size < index * 8 + 7)
1567 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1568
e919464b 1569 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1570 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1571 &ctxt->exception);
dde7e6d1 1572}
ef65c889 1573
dde7e6d1
AK		 1574/* allowed just for 8 bytes segments */
1575static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1576 u16 selector, struct desc_struct *desc)
1577{
1578 struct desc_ptr dt;
1579 u16 index = selector >> 3;
dde7e6d1 1580 ulong addr;
6aa8b732 1581
7b105ca2 1582 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1583
35d3d4a1
AK		 1584 if (dt.size < index * 8 + 7)
1585 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1586
dde7e6d1 1587 addr = dt.address + index * 8;
7b105ca2
TY		 1588 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1589 &ctxt->exception);
dde7e6d1 1590}
c7e75a3d 1591
5601d05b 1592/* Does not support long mode */
dde7e6d1 1593static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1594 u16 selector, int seg)
1595{
869be99c 1596 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1597 u8 dpl, rpl, cpl;
1598 unsigned err_vec = GP_VECTOR;
1599 u32 err_code = 0;
1600 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1601 ulong desc_addr;
dde7e6d1 1602 int ret;
03ebebeb 1603 u16 dummy;
69f55cb1 1604
dde7e6d1 1605 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1606
f8da94e9
KW		 1607 if (ctxt->mode == X86EMUL_MODE_REAL) {
1608 /* set real mode segment descriptor (keep limit etc. for
1609 * unreal mode) */
03ebebeb 1610 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1611 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1612 goto load;
f8da94e9
KW		 1613 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1614 /* VM86 needs a clean new segment descriptor */
1615 set_desc_base(&seg_desc, selector << 4);
1616 set_desc_limit(&seg_desc, 0xffff);
1617 seg_desc.type = 3;
1618 seg_desc.p = 1;
1619 seg_desc.s = 1;
1620 seg_desc.dpl = 3;
1621 goto load;
dde7e6d1
AK		 1622 }
1623
79d5b4c3
AK		 1624 rpl = selector & 3;
1625 cpl = ctxt->ops->cpl(ctxt);
1626
1627 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1628 if ((seg == VCPU_SREG_CS
1629 || (seg == VCPU_SREG_SS
1630 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1631 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1632 && null_selector)
1633 goto exception;
1634
1635 /* TR should be in GDT only */
1636 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1637 goto exception;
1638
1639 if (null_selector) /* for NULL selector skip all following checks */
1640 goto load;
1641
e919464b 1642 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1643 if (ret != X86EMUL_CONTINUE)
1644 return ret;
1645
1646 err_code = selector & 0xfffc;
1647 err_vec = GP_VECTOR;
1648
fc058680 1649 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1650 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1651 goto exception;
1652
1653 if (!seg_desc.p) {
1654 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1655 goto exception;
1656 }
1657
dde7e6d1 1658 dpl = seg_desc.dpl;
dde7e6d1
AK		 1659
1660 switch (seg) {
1661 case VCPU_SREG_SS:
1662 /*
1663 * segment is not a writable data segment or segment
1664 * selector's RPL != CPL or segment selector's RPL != CPL
1665 */
1666 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1667 goto exception;
6aa8b732 1668 break;
dde7e6d1
AK		 1669 case VCPU_SREG_CS:
1670 if (!(seg_desc.type & 8))
1671 goto exception;
1672
1673 if (seg_desc.type & 4) {
1674 /* conforming */
1675 if (dpl > cpl)
1676 goto exception;
1677 } else {
1678 /* nonconforming */
1679 if (rpl > cpl || dpl != cpl)
1680 goto exception;
1681 }
1682 /* CS(RPL) <- CPL */
1683 selector = (selector & 0xfffc) | cpl;
6aa8b732 1684 break;
dde7e6d1
AK		 1685 case VCPU_SREG_TR:
1686 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1687 goto exception;
869be99c
AK		 1688 old_desc = seg_desc;
1689 seg_desc.type |= 2; /* busy */
1690 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1691 sizeof(seg_desc), &ctxt->exception);
1692 if (ret != X86EMUL_CONTINUE)
1693 return ret;
dde7e6d1
AK		 1694 break;
1695 case VCPU_SREG_LDTR:
1696 if (seg_desc.s || seg_desc.type != 2)
1697 goto exception;
1698 break;
1699 default: /* DS, ES, FS, or GS */
4e62417b 1700 /*
dde7e6d1
AK		 1701 * segment is not a data or readable code segment or
1702 * ((segment is a data or nonconforming code segment)
1703 * and (both RPL and CPL > DPL))
4e62417b 1704 */
dde7e6d1
AK		 1705 if ((seg_desc.type & 0xa) == 0x8 ||
1706 (((seg_desc.type & 0xc) != 0xc) &&
1707 (rpl > dpl && cpl > dpl)))
1708 goto exception;
6aa8b732 1709 break;
dde7e6d1
AK		 1710 }
1711
1712 if (seg_desc.s) {
1713 /* mark segment as accessed */
1714 seg_desc.type |= 1;
7b105ca2 1715 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1716 if (ret != X86EMUL_CONTINUE)
1717 return ret;
1718 }
1719load:
7b105ca2 1720 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1721 return X86EMUL_CONTINUE;
1722exception:
1723 emulate_exception(ctxt, err_vec, err_code, true);
1724 return X86EMUL_PROPAGATE_FAULT;
1725}
1726
31be40b3
WY		 1727static void write_register_operand(struct operand *op)
1728{
1729 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1730 switch (op->bytes) {
1731 case 1:
1732 *(u8 *)op->addr.reg = (u8)op->val;
1733 break;
1734 case 2:
1735 *(u16 *)op->addr.reg = (u16)op->val;
1736 break;
1737 case 4:
1738 *op->addr.reg = (u32)op->val;
1739 break; /* 64b: zero-extend */
1740 case 8:
1741 *op->addr.reg = op->val;
1742 break;
1743 }
1744}
1745
fb32b1ed 1746static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1747{
1748 int rc;
dde7e6d1 1749
fb32b1ed 1750 switch (op->type) {
dde7e6d1 1751 case OP_REG:
fb32b1ed 1752 write_register_operand(op);
6aa8b732 1753 break;
dde7e6d1 1754 case OP_MEM:
9dac77fa 1755 if (ctxt->lock_prefix)
3ca3ac4d 1756 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1757 op->addr.mem,
1758 &op->orig_val,
1759 &op->val,
1760 op->bytes);
341de7e3 1761 else
3ca3ac4d 1762 rc = segmented_write(ctxt,
fb32b1ed
AK		 1763 op->addr.mem,
1764 &op->val,
1765 op->bytes);
dde7e6d1
AK		 1766 if (rc != X86EMUL_CONTINUE)
1767 return rc;
a682e354 1768 break;
b3356bf0
GN		 1769 case OP_MEM_STR:
1770 rc = segmented_write(ctxt,
fb32b1ed
AK		 1771 op->addr.mem,
1772 op->data,
1773 op->bytes * op->count);
b3356bf0
GN		 1774 if (rc != X86EMUL_CONTINUE)
1775 return rc;
1776 break;
1253791d 1777 case OP_XMM:
fb32b1ed 1778 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1779 break;
cbe2c9d3 1780 case OP_MM:
fb32b1ed 1781 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1782 break;
dde7e6d1
AK		 1783 case OP_NONE:
1784 /* no writeback */
414e6277 1785 break;
dde7e6d1 1786 default:
414e6277 1787 break;
6aa8b732 1788 }
dde7e6d1
AK		 1789 return X86EMUL_CONTINUE;
1790}
6aa8b732 1791
51ddff50 1792static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1793{
4179bb02 1794 struct segmented_address addr;
0dc8d10f 1795
5ad105e5 1796 rsp_increment(ctxt, -bytes);
dd856efa 1797 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1798 addr.seg = VCPU_SREG_SS;
1799
51ddff50
AK		 1800 return segmented_write(ctxt, addr, data, bytes);
1801}
1802
1803static int em_push(struct x86_emulate_ctxt *ctxt)
1804{
4179bb02 1805 /* Disable writeback. */
9dac77fa 1806 ctxt->dst.type = OP_NONE;
51ddff50 1807 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1808}
69f55cb1 1809
dde7e6d1 1810static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1811 void *dest, int len)
1812{
dde7e6d1 1813 int rc;
90de84f5 1814 struct segmented_address addr;
8b4caf66 1815
dd856efa 1816 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1817 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1818 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1819 if (rc != X86EMUL_CONTINUE)
1820 return rc;
1821
5ad105e5 1822 rsp_increment(ctxt, len);
dde7e6d1 1823 return rc;
8b4caf66
LV		 1824}
1825
c54fe504
TY		 1826static int em_pop(struct x86_emulate_ctxt *ctxt)
1827{
9dac77fa 1828 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1829}
1830
dde7e6d1 1831static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1832 void *dest, int len)
9de41573
GN		 1833{
1834 int rc;
dde7e6d1
AK		 1835 unsigned long val, change_mask;
1836 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1837 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1838
3b9be3bf 1839 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1840 if (rc != X86EMUL_CONTINUE)
1841 return rc;
9de41573 1842
dde7e6d1
AK		 1843 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1844 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1845
dde7e6d1
AK		 1846 switch(ctxt->mode) {
1847 case X86EMUL_MODE_PROT64:
1848 case X86EMUL_MODE_PROT32:
1849 case X86EMUL_MODE_PROT16:
1850 if (cpl == 0)
1851 change_mask |= EFLG_IOPL;
1852 if (cpl <= iopl)
1853 change_mask |= EFLG_IF;
1854 break;
1855 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1856 if (iopl < 3)
1857 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1858 change_mask |= EFLG_IF;
1859 break;
1860 default: /* real mode */
1861 change_mask |= (EFLG_IOPL | EFLG_IF);
1862 break;
9de41573 1863 }
dde7e6d1
AK		 1864
1865 *(unsigned long *)dest =
1866 (ctxt->eflags & ~change_mask) | (val & change_mask);
1867
1868 return rc;
9de41573
GN		 1869}
1870
62aaa2f0
TY		 1871static int em_popf(struct x86_emulate_ctxt *ctxt)
1872{
9dac77fa
AK		 1873 ctxt->dst.type = OP_REG;
1874 ctxt->dst.addr.reg = &ctxt->eflags;
1875 ctxt->dst.bytes = ctxt->op_bytes;
1876 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1877}
1878
612e89f0
AK		 1879static int em_enter(struct x86_emulate_ctxt *ctxt)
1880{
1881 int rc;
1882 unsigned frame_size = ctxt->src.val;
1883 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1884 ulong rbp;
612e89f0
AK		 1885
1886 if (nesting_level)
1887 return X86EMUL_UNHANDLEABLE;
1888
dd856efa
AK		 1889 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1890 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1891 if (rc != X86EMUL_CONTINUE)
1892 return rc;
dd856efa 1893 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1894 stack_mask(ctxt));
dd856efa
AK		 1895 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1896 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1897 stack_mask(ctxt));
1898 return X86EMUL_CONTINUE;
1899}
1900
f47cfa31
AK		 1901static int em_leave(struct x86_emulate_ctxt *ctxt)
1902{
dd856efa 1903 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1904 stack_mask(ctxt));
dd856efa 1905 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1906}
1907
1cd196ea 1908static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1909{
1cd196ea
AK		 1910 int seg = ctxt->src2.val;
1911
9dac77fa 1912 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1913
4487b3b4 1914 return em_push(ctxt);
7b262e90
GN		 1915}
1916
1cd196ea 1917static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1918{
1cd196ea 1919 int seg = ctxt->src2.val;
dde7e6d1
AK		 1920 unsigned long selector;
1921 int rc;
38ba30ba 1922
9dac77fa 1923 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1924 if (rc != X86EMUL_CONTINUE)
1925 return rc;
1926
7b105ca2 1927 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1928 return rc;
38ba30ba
GN		 1929}
1930
b96a7fad 1931static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1932{
dd856efa 1933 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1934 int rc = X86EMUL_CONTINUE;
1935 int reg = VCPU_REGS_RAX;
38ba30ba 1936
dde7e6d1
AK		 1937 while (reg <= VCPU_REGS_RDI) {
1938 (reg == VCPU_REGS_RSP) ?
dd856efa 1939 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1940
4487b3b4 1941 rc = em_push(ctxt);
dde7e6d1
AK		 1942 if (rc != X86EMUL_CONTINUE)
1943 return rc;
38ba30ba 1944
dde7e6d1 1945 ++reg;
38ba30ba 1946 }
38ba30ba 1947
dde7e6d1 1948 return rc;
38ba30ba
GN		 1949}
1950
62aaa2f0
TY		 1951static int em_pushf(struct x86_emulate_ctxt *ctxt)
1952{
9dac77fa 1953 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1954 return em_push(ctxt);
1955}
1956
b96a7fad 1957static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1958{
dde7e6d1
AK		 1959 int rc = X86EMUL_CONTINUE;
1960 int reg = VCPU_REGS_RDI;
38ba30ba 1961
dde7e6d1
AK		 1962 while (reg >= VCPU_REGS_RAX) {
1963 if (reg == VCPU_REGS_RSP) {
5ad105e5 1964 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1965 --reg;
1966 }
38ba30ba 1967
dd856efa 1968 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1969 if (rc != X86EMUL_CONTINUE)
1970 break;
1971 --reg;
38ba30ba 1972 }
dde7e6d1 1973 return rc;
38ba30ba
GN		 1974}
1975
dd856efa 1976static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1977{
0225fb50 1978 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1979 int rc;
6e154e56
MG		 1980 struct desc_ptr dt;
1981 gva_t cs_addr;
1982 gva_t eip_addr;
1983 u16 cs, eip;
6e154e56
MG		 1984
1985 /* TODO: Add limit checks */
9dac77fa 1986 ctxt->src.val = ctxt->eflags;
4487b3b4 1987 rc = em_push(ctxt);
5c56e1cf
AK		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
6e154e56
MG		 1990
1991 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1992
9dac77fa 1993 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1994 rc = em_push(ctxt);
5c56e1cf
AK		 1995 if (rc != X86EMUL_CONTINUE)
1996 return rc;
6e154e56 1997
9dac77fa 1998 ctxt->src.val = ctxt->_eip;
4487b3b4 1999 rc = em_push(ctxt);
5c56e1cf
AK		 2000 if (rc != X86EMUL_CONTINUE)
2001 return rc;
2002
4bff1e86 2003 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2004
2005 eip_addr = dt.address + (irq << 2);
2006 cs_addr = dt.address + (irq << 2) + 2;
2007
0f65dd70 2008 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 2009 if (rc != X86EMUL_CONTINUE)
2010 return rc;
2011
0f65dd70 2012 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 2013 if (rc != X86EMUL_CONTINUE)
2014 return rc;
2015
7b105ca2 2016 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2017 if (rc != X86EMUL_CONTINUE)
2018 return rc;
2019
9dac77fa 2020 ctxt->_eip = eip;
6e154e56
MG		 2021
2022 return rc;
2023}
2024
dd856efa
AK		 2025int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2026{
2027 int rc;
2028
2029 invalidate_registers(ctxt);
2030 rc = __emulate_int_real(ctxt, irq);
2031 if (rc == X86EMUL_CONTINUE)
2032 writeback_registers(ctxt);
2033 return rc;
2034}
2035
7b105ca2 2036static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2037{
2038 switch(ctxt->mode) {
2039 case X86EMUL_MODE_REAL:
dd856efa 2040 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2041 case X86EMUL_MODE_VM86:
2042 case X86EMUL_MODE_PROT16:
2043 case X86EMUL_MODE_PROT32:
2044 case X86EMUL_MODE_PROT64:
2045 default:
2046 /* Protected mode interrupts unimplemented yet */
2047 return X86EMUL_UNHANDLEABLE;
2048 }
2049}
2050
7b105ca2 2051static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2052{
dde7e6d1
AK		 2053 int rc = X86EMUL_CONTINUE;
2054 unsigned long temp_eip = 0;
2055 unsigned long temp_eflags = 0;
2056 unsigned long cs = 0;
2057 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2058 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2059 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2060 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2061
dde7e6d1 2062 /* TODO: Add stack limit check */
38ba30ba 2063
9dac77fa 2064 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2065
dde7e6d1
AK		 2066 if (rc != X86EMUL_CONTINUE)
2067 return rc;
38ba30ba 2068
35d3d4a1
AK		 2069 if (temp_eip & ~0xffff)
2070 return emulate_gp(ctxt, 0);
38ba30ba 2071
9dac77fa 2072 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2073
dde7e6d1
AK		 2074 if (rc != X86EMUL_CONTINUE)
2075 return rc;
38ba30ba 2076
9dac77fa 2077 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2078
dde7e6d1
AK		 2079 if (rc != X86EMUL_CONTINUE)
2080 return rc;
38ba30ba 2081
7b105ca2 2082 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2083
dde7e6d1
AK		 2084 if (rc != X86EMUL_CONTINUE)
2085 return rc;
38ba30ba 2086
9dac77fa 2087 ctxt->_eip = temp_eip;
38ba30ba 2088
38ba30ba 2089
9dac77fa 2090 if (ctxt->op_bytes == 4)
dde7e6d1 2091 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2092 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2093 ctxt->eflags &= ~0xffff;
2094 ctxt->eflags |= temp_eflags;
38ba30ba 2095 }
dde7e6d1
AK		 2096
2097 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2098 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2099
2100 return rc;
38ba30ba
GN		 2101}
2102
e01991e7 2103static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2104{
dde7e6d1
AK		 2105 switch(ctxt->mode) {
2106 case X86EMUL_MODE_REAL:
7b105ca2 2107 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2108 case X86EMUL_MODE_VM86:
2109 case X86EMUL_MODE_PROT16:
2110 case X86EMUL_MODE_PROT32:
2111 case X86EMUL_MODE_PROT64:
c37eda13 2112 default:
dde7e6d1
AK		 2113 /* iret from protected mode unimplemented yet */
2114 return X86EMUL_UNHANDLEABLE;
c37eda13 2115 }
c37eda13
WY		 2116}
2117
d2f62766
TY		 2118static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2119{
d2f62766
TY		 2120 int rc;
2121 unsigned short sel;
2122
9dac77fa 2123 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2124
7b105ca2 2125 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2126 if (rc != X86EMUL_CONTINUE)
2127 return rc;
2128
9dac77fa
AK		 2129 ctxt->_eip = 0;
2130 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2131 return X86EMUL_CONTINUE;
2132}
2133
3329ece1 2134static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2135{
34d1f490 2136 u8 de = 0;
8cdbd2c9 2137
3329ece1
AK		 2138 emulate_1op_rax_rdx(ctxt, "div", de);
2139 if (de)
2140 return emulate_de(ctxt);
2141 return X86EMUL_CONTINUE;
2142}
2143
2144static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2145{
2146 u8 de = 0;
2147
2148 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2149 if (de)
2150 return emulate_de(ctxt);
8c5eee30 2151 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2152}
2153
51187683 2154static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2155{
4179bb02 2156 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2157
9dac77fa 2158 switch (ctxt->modrm_reg) {
d19292e4
MG		 2159 case 2: /* call near abs */ {
2160 long int old_eip;
9dac77fa
AK		 2161 old_eip = ctxt->_eip;
2162 ctxt->_eip = ctxt->src.val;
2163 ctxt->src.val = old_eip;
4487b3b4 2164 rc = em_push(ctxt);
d19292e4
MG		 2165 break;
2166 }
8cdbd2c9 2167 case 4: /* jmp abs */
9dac77fa 2168 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2169 break;
d2f62766
TY		 2170 case 5: /* jmp far */
2171 rc = em_jmp_far(ctxt);
2172 break;
8cdbd2c9 2173 case 6: /* push */
4487b3b4 2174 rc = em_push(ctxt);
8cdbd2c9 2175 break;
8cdbd2c9 2176 }
4179bb02 2177 return rc;
8cdbd2c9
LV		 2178}
2179
e0dac408 2180static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2181{
9dac77fa 2182 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2183
dd856efa
AK		 2184 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2185 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2186 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2187 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2188 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2189 } else {
dd856efa
AK		 2190 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2191 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2192
05f086f8 2193 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2194 }
1b30eaa8 2195 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2196}
2197
ebda02c2
TY		 2198static int em_ret(struct x86_emulate_ctxt *ctxt)
2199{
9dac77fa
AK		 2200 ctxt->dst.type = OP_REG;
2201 ctxt->dst.addr.reg = &ctxt->_eip;
2202 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2203 return em_pop(ctxt);
2204}
2205
e01991e7 2206static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2207{
a77ab5ea
AK		 2208 int rc;
2209 unsigned long cs;
2210
9dac77fa 2211 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2212 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2213 return rc;
9dac77fa
AK		 2214 if (ctxt->op_bytes == 4)
2215 ctxt->_eip = (u32)ctxt->_eip;
2216 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2217 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2218 return rc;
7b105ca2 2219 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2220 return rc;
2221}
2222
e940b5c2
TY		 2223static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2224{
2225 /* Save real source value, then compare EAX against destination. */
2226 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2227 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2228 fastop(ctxt, em_cmp);
e940b5c2
TY		 2229
2230 if (ctxt->eflags & EFLG_ZF) {
2231 /* Success: write back to memory. */
2232 ctxt->dst.val = ctxt->src.orig_val;
2233 } else {
2234 /* Failure: write the value we saw to EAX. */
2235 ctxt->dst.type = OP_REG;
dd856efa 2236 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2237 }
2238 return X86EMUL_CONTINUE;
2239}
2240
d4b4325f 2241static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2242{
d4b4325f 2243 int seg = ctxt->src2.val;
09b5f4d3
WY		 2244 unsigned short sel;
2245 int rc;
2246
9dac77fa 2247 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2248
7b105ca2 2249 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2250 if (rc != X86EMUL_CONTINUE)
2251 return rc;
2252
9dac77fa 2253 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2254 return rc;
2255}
2256
7b105ca2 2257static void
e66bb2cc 2258setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2259 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2260{
e66bb2cc 2261 cs->l = 0; /* will be adjusted later */
79168fd1 2262 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2263 cs->g = 1; /* 4kb granularity */
79168fd1 2264 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2265 cs->type = 0x0b; /* Read, Execute, Accessed */
2266 cs->s = 1;
2267 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2268 cs->p = 1;
2269 cs->d = 1;
99245b50 2270 cs->avl = 0;
e66bb2cc 2271
79168fd1
GN		 2272 set_desc_base(ss, 0); /* flat segment */
2273 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2274 ss->g = 1; /* 4kb granularity */
2275 ss->s = 1;
2276 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2277 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2278 ss->dpl = 0;
79168fd1 2279 ss->p = 1;
99245b50
GN		 2280 ss->l = 0;
2281 ss->avl = 0;
e66bb2cc
AP		 2282}
2283
1a18a69b
AK		 2284static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2285{
2286 u32 eax, ebx, ecx, edx;
2287
2288 eax = ecx = 0;
0017f93a
AK		 2289 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2290 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2291 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2292 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2293}
2294
c2226fc9
SB		 2295static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2296{
0225fb50 2297 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2298 u32 eax, ebx, ecx, edx;
2299
2300 /*
2301 * syscall should always be enabled in longmode - so only become
2302 * vendor specific (cpuid) if other modes are active...
2303 */
2304 if (ctxt->mode == X86EMUL_MODE_PROT64)
2305 return true;
2306
2307 eax = 0x00000000;
2308 ecx = 0x00000000;
0017f93a
AK		 2309 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2310 /*
2311 * Intel ("GenuineIntel")
2312 * remark: Intel CPUs only support "syscall" in 64bit
2313 * longmode. Also an 64bit guest with a
2314 * 32bit compat-app running will #UD !! While this
2315 * behaviour can be fixed (by emulating) into AMD
2316 * response - CPUs of AMD can't behave like Intel.
2317 */
2318 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2319 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2320 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2321 return false;
2322
2323 /* AMD ("AuthenticAMD") */
2324 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2325 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2326 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2327 return true;
2328
2329 /* AMD ("AMDisbetter!") */
2330 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2331 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2332 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2333 return true;
c2226fc9
SB		 2334
2335 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2336 return false;
2337}
2338
e01991e7 2339static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2340{
0225fb50 2341 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2342 struct desc_struct cs, ss;
e66bb2cc 2343 u64 msr_data;
79168fd1 2344 u16 cs_sel, ss_sel;
c2ad2bb3 2345 u64 efer = 0;
e66bb2cc
AP		 2346
2347 /* syscall is not available in real mode */
2e901c4c 2348 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2349 ctxt->mode == X86EMUL_MODE_VM86)
2350 return emulate_ud(ctxt);
e66bb2cc 2351
c2226fc9
SB		 2352 if (!(em_syscall_is_enabled(ctxt)))
2353 return emulate_ud(ctxt);
2354
c2ad2bb3 2355 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2356 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2357
c2226fc9
SB		 2358 if (!(efer & EFER_SCE))
2359 return emulate_ud(ctxt);
2360
717746e3 2361 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2362 msr_data >>= 32;
79168fd1
GN		 2363 cs_sel = (u16)(msr_data & 0xfffc);
2364 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2365
c2ad2bb3 2366 if (efer & EFER_LMA) {
79168fd1 2367 cs.d = 0;
e66bb2cc
AP		 2368 cs.l = 1;
2369 }
1aa36616
AK		 2370 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2371 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2372
dd856efa 2373 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2374 if (efer & EFER_LMA) {
e66bb2cc 2375#ifdef CONFIG_X86_64
dd856efa 2376 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2377
717746e3 2378 ops->get_msr(ctxt,
3fb1b5db
GN		 2379 ctxt->mode == X86EMUL_MODE_PROT64 ?
2380 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2381 ctxt->_eip = msr_data;
e66bb2cc 2382
717746e3 2383 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2384 ctxt->eflags &= ~(msr_data | EFLG_RF);
2385#endif
2386 } else {
2387 /* legacy mode */
717746e3 2388 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2389 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2390
2391 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2392 }
2393
e54cfa97 2394 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2395}
2396
e01991e7 2397static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2398{
0225fb50 2399 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2400 struct desc_struct cs, ss;
8c604352 2401 u64 msr_data;
79168fd1 2402 u16 cs_sel, ss_sel;
c2ad2bb3 2403 u64 efer = 0;
8c604352 2404
7b105ca2 2405 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2406 /* inject #GP if in real mode */
35d3d4a1
AK		 2407 if (ctxt->mode == X86EMUL_MODE_REAL)
2408 return emulate_gp(ctxt, 0);
8c604352 2409
1a18a69b
AK		 2410 /*
2411 * Not recognized on AMD in compat mode (but is recognized in legacy
2412 * mode).
2413 */
2414 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2415 && !vendor_intel(ctxt))
2416 return emulate_ud(ctxt);
2417
8c604352
AP		 2418 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2419 * Therefore, we inject an #UD.
2420 */
35d3d4a1
AK		 2421 if (ctxt->mode == X86EMUL_MODE_PROT64)
2422 return emulate_ud(ctxt);
8c604352 2423
7b105ca2 2424 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2425
717746e3 2426 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2427 switch (ctxt->mode) {
2428 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2429 if ((msr_data & 0xfffc) == 0x0)
2430 return emulate_gp(ctxt, 0);
8c604352
AP		 2431 break;
2432 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2433 if (msr_data == 0x0)
2434 return emulate_gp(ctxt, 0);
8c604352 2435 break;
9d1b39a9
GN		 2436 default:
2437 break;
8c604352
AP		 2438 }
2439
2440 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2441 cs_sel = (u16)msr_data;
2442 cs_sel &= ~SELECTOR_RPL_MASK;
2443 ss_sel = cs_sel + 8;
2444 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2445 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2446 cs.d = 0;
8c604352
AP		 2447 cs.l = 1;
2448 }
2449
1aa36616
AK		 2450 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2451 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2452
717746e3 2453 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2454 ctxt->_eip = msr_data;
8c604352 2455
717746e3 2456 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2457 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2458
e54cfa97 2459 return X86EMUL_CONTINUE;
8c604352
AP		 2460}
2461
e01991e7 2462static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2463{
0225fb50 2464 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2465 struct desc_struct cs, ss;
4668f050
AP		 2466 u64 msr_data;
2467 int usermode;
1249b96e 2468 u16 cs_sel = 0, ss_sel = 0;
4668f050 2469
a0044755
GN		 2470 /* inject #GP if in real mode or Virtual 8086 mode */
2471 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2472 ctxt->mode == X86EMUL_MODE_VM86)
2473 return emulate_gp(ctxt, 0);
4668f050 2474
7b105ca2 2475 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2476
9dac77fa 2477 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2478 usermode = X86EMUL_MODE_PROT64;
2479 else
2480 usermode = X86EMUL_MODE_PROT32;
2481
2482 cs.dpl = 3;
2483 ss.dpl = 3;
717746e3 2484 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2485 switch (usermode) {
2486 case X86EMUL_MODE_PROT32:
79168fd1 2487 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2488 if ((msr_data & 0xfffc) == 0x0)
2489 return emulate_gp(ctxt, 0);
79168fd1 2490 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2491 break;
2492 case X86EMUL_MODE_PROT64:
79168fd1 2493 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2494 if (msr_data == 0x0)
2495 return emulate_gp(ctxt, 0);
79168fd1
GN		 2496 ss_sel = cs_sel + 8;
2497 cs.d = 0;
4668f050
AP		 2498 cs.l = 1;
2499 break;
2500 }
79168fd1
GN		 2501 cs_sel |= SELECTOR_RPL_MASK;
2502 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2503
1aa36616
AK		 2504 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2505 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2506
dd856efa
AK		 2507 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2508 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2509
e54cfa97 2510 return X86EMUL_CONTINUE;
4668f050
AP		 2511}
2512
7b105ca2 2513static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2514{
2515 int iopl;
2516 if (ctxt->mode == X86EMUL_MODE_REAL)
2517 return false;
2518 if (ctxt->mode == X86EMUL_MODE_VM86)
2519 return true;
2520 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2521 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2522}
2523
2524static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2525 u16 port, u16 len)
2526{
0225fb50 2527 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2528 struct desc_struct tr_seg;
5601d05b 2529 u32 base3;
f850e2e6 2530 int r;
1aa36616 2531 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2532 unsigned mask = (1 << len) - 1;
5601d05b 2533 unsigned long base;
f850e2e6 2534
1aa36616 2535 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2536 if (!tr_seg.p)
f850e2e6 2537 return false;
79168fd1 2538 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2539 return false;
5601d05b
GN		 2540 base = get_desc_base(&tr_seg);
2541#ifdef CONFIG_X86_64
2542 base |= ((u64)base3) << 32;
2543#endif
0f65dd70 2544 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2545 if (r != X86EMUL_CONTINUE)
2546 return false;
79168fd1 2547 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2548 return false;
0f65dd70 2549 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2550 if (r != X86EMUL_CONTINUE)
2551 return false;
2552 if ((perm >> bit_idx) & mask)
2553 return false;
2554 return true;
2555}
2556
2557static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2558 u16 port, u16 len)
2559{
4fc40f07
GN		 2560 if (ctxt->perm_ok)
2561 return true;
2562
7b105ca2
TY		 2563 if (emulator_bad_iopl(ctxt))
2564 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2565 return false;
4fc40f07
GN		 2566
2567 ctxt->perm_ok = true;
2568
f850e2e6
GN		 2569 return true;
2570}
2571
38ba30ba 2572static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2573 struct tss_segment_16 *tss)
2574{
9dac77fa 2575 tss->ip = ctxt->_eip;
38ba30ba 2576 tss->flag = ctxt->eflags;
dd856efa
AK		 2577 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2578 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2579 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2580 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2581 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2582 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2583 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2584 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2585
1aa36616
AK		 2586 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2587 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2588 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2589 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2590 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2591}
2592
2593static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2594 struct tss_segment_16 *tss)
2595{
38ba30ba
GN		 2596 int ret;
2597
9dac77fa 2598 ctxt->_eip = tss->ip;
38ba30ba 2599 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2600 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2601 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2602 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2603 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2604 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2605 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2606 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2607 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2608
2609 /*
2610 * SDM says that segment selectors are loaded before segment
2611 * descriptors
2612 */
1aa36616
AK		 2613 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2614 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2615 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2616 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2617 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2618
2619 /*
fc058680 2620 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2621 * it is handled in a context of new task
2622 */
7b105ca2 2623 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
7b105ca2 2626 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
7b105ca2 2629 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
7b105ca2 2632 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2633 if (ret != X86EMUL_CONTINUE)
2634 return ret;
7b105ca2 2635 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2636 if (ret != X86EMUL_CONTINUE)
2637 return ret;
2638
2639 return X86EMUL_CONTINUE;
2640}
2641
2642static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2643 u16 tss_selector, u16 old_tss_sel,
2644 ulong old_tss_base, struct desc_struct *new_desc)
2645{
0225fb50 2646 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2647 struct tss_segment_16 tss_seg;
2648 int ret;
bcc55cba 2649 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2650
0f65dd70 2651 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2652 &ctxt->exception);
db297e3d 2653 if (ret != X86EMUL_CONTINUE)
38ba30ba 2654 /* FIXME: need to provide precise fault address */
38ba30ba 2655 return ret;
38ba30ba 2656
7b105ca2 2657 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2658
0f65dd70 2659 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2660 &ctxt->exception);
db297e3d 2661 if (ret != X86EMUL_CONTINUE)
38ba30ba 2662 /* FIXME: need to provide precise fault address */
38ba30ba 2663 return ret;
38ba30ba 2664
0f65dd70 2665 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2666 &ctxt->exception);
db297e3d 2667 if (ret != X86EMUL_CONTINUE)
38ba30ba 2668 /* FIXME: need to provide precise fault address */
38ba30ba 2669 return ret;
38ba30ba
GN		 2670
2671 if (old_tss_sel != 0xffff) {
2672 tss_seg.prev_task_link = old_tss_sel;
2673
0f65dd70 2674 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2675 &tss_seg.prev_task_link,
2676 sizeof tss_seg.prev_task_link,
0f65dd70 2677 &ctxt->exception);
db297e3d 2678 if (ret != X86EMUL_CONTINUE)
38ba30ba 2679 /* FIXME: need to provide precise fault address */
38ba30ba 2680 return ret;
38ba30ba
GN		 2681 }
2682
7b105ca2 2683 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2684}
2685
2686static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2687 struct tss_segment_32 *tss)
2688{
7b105ca2 2689 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2690 tss->eip = ctxt->_eip;
38ba30ba 2691 tss->eflags = ctxt->eflags;
dd856efa
AK		 2692 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2693 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2694 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2695 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2696 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2697 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2698 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2699 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2700
1aa36616
AK		 2701 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2702 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2703 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2704 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2705 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2706 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2707 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2708}
2709
2710static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2711 struct tss_segment_32 *tss)
2712{
38ba30ba
GN		 2713 int ret;
2714
7b105ca2 2715 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2716 return emulate_gp(ctxt, 0);
9dac77fa 2717 ctxt->_eip = tss->eip;
38ba30ba 2718 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2719
2720 /* General purpose registers */
dd856efa
AK		 2721 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2722 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2723 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2724 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2725 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2726 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2727 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2728 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2729
2730 /*
2731 * SDM says that segment selectors are loaded before segment
2732 * descriptors
2733 */
1aa36616
AK		 2734 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2735 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2736 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2737 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2738 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2739 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2740 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2741
4cee4798
KW		 2742 /*
2743 * If we're switching between Protected Mode and VM86, we need to make
2744 * sure to update the mode before loading the segment descriptors so
2745 * that the selectors are interpreted correctly.
2746 *
2747 * Need to get rflags to the vcpu struct immediately because it
2748 * influences the CPL which is checked at least when loading the segment
2749 * descriptors and when pushing an error code to the new kernel stack.
2750 *
2751 * TODO Introduce a separate ctxt->ops->set_cpl callback
2752 */
2753 if (ctxt->eflags & X86_EFLAGS_VM)
2754 ctxt->mode = X86EMUL_MODE_VM86;
2755 else
2756 ctxt->mode = X86EMUL_MODE_PROT32;
2757
2758 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2759
38ba30ba
GN		 2760 /*
2761 * Now load segment descriptors. If fault happenes at this stage
2762 * it is handled in a context of new task
2763 */
7b105ca2 2764 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2765 if (ret != X86EMUL_CONTINUE)
2766 return ret;
7b105ca2 2767 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2768 if (ret != X86EMUL_CONTINUE)
2769 return ret;
7b105ca2 2770 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2771 if (ret != X86EMUL_CONTINUE)
2772 return ret;
7b105ca2 2773 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2774 if (ret != X86EMUL_CONTINUE)
2775 return ret;
7b105ca2 2776 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2777 if (ret != X86EMUL_CONTINUE)
2778 return ret;
7b105ca2 2779 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2780 if (ret != X86EMUL_CONTINUE)
2781 return ret;
7b105ca2 2782 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2783 if (ret != X86EMUL_CONTINUE)
2784 return ret;
2785
2786 return X86EMUL_CONTINUE;
2787}
2788
2789static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2790 u16 tss_selector, u16 old_tss_sel,
2791 ulong old_tss_base, struct desc_struct *new_desc)
2792{
0225fb50 2793 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2794 struct tss_segment_32 tss_seg;
2795 int ret;
bcc55cba 2796 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2797
0f65dd70 2798 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2799 &ctxt->exception);
db297e3d 2800 if (ret != X86EMUL_CONTINUE)
38ba30ba 2801 /* FIXME: need to provide precise fault address */
38ba30ba 2802 return ret;
38ba30ba 2803
7b105ca2 2804 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2805
0f65dd70 2806 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2807 &ctxt->exception);
db297e3d 2808 if (ret != X86EMUL_CONTINUE)
38ba30ba 2809 /* FIXME: need to provide precise fault address */
38ba30ba 2810 return ret;
38ba30ba 2811
0f65dd70 2812 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2813 &ctxt->exception);
db297e3d 2814 if (ret != X86EMUL_CONTINUE)
38ba30ba 2815 /* FIXME: need to provide precise fault address */
38ba30ba 2816 return ret;
38ba30ba
GN		 2817
2818 if (old_tss_sel != 0xffff) {
2819 tss_seg.prev_task_link = old_tss_sel;
2820
0f65dd70 2821 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2822 &tss_seg.prev_task_link,
2823 sizeof tss_seg.prev_task_link,
0f65dd70 2824 &ctxt->exception);
db297e3d 2825 if (ret != X86EMUL_CONTINUE)
38ba30ba 2826 /* FIXME: need to provide precise fault address */
38ba30ba 2827 return ret;
38ba30ba
GN		 2828 }
2829
7b105ca2 2830 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2831}
2832
2833static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2834 u16 tss_selector, int idt_index, int reason,
e269fb21 2835 bool has_error_code, u32 error_code)
38ba30ba 2836{
0225fb50 2837 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2838 struct desc_struct curr_tss_desc, next_tss_desc;
2839 int ret;
1aa36616 2840 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2841 ulong old_tss_base =
4bff1e86 2842 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2843 u32 desc_limit;
e919464b 2844 ulong desc_addr;
38ba30ba
GN		 2845
2846 /* FIXME: old_tss_base == ~0 ? */
2847
e919464b 2848 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2849 if (ret != X86EMUL_CONTINUE)
2850 return ret;
e919464b 2851 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2852 if (ret != X86EMUL_CONTINUE)
2853 return ret;
2854
2855 /* FIXME: check that next_tss_desc is tss */
2856
7f3d35fd
KW		 2857 /*
2858 * Check privileges. The three cases are task switch caused by...
2859 *
2860 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2861 * 2. Exception/IRQ/iret: No check is performed
fc058680 2862 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2863 */
2864 if (reason == TASK_SWITCH_GATE) {
2865 if (idt_index != -1) {
2866 /* Software interrupts */
2867 struct desc_struct task_gate_desc;
2868 int dpl;
2869
2870 ret = read_interrupt_descriptor(ctxt, idt_index,
2871 &task_gate_desc);
2872 if (ret != X86EMUL_CONTINUE)
2873 return ret;
2874
2875 dpl = task_gate_desc.dpl;
2876 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2877 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2878 }
2879 } else if (reason != TASK_SWITCH_IRET) {
2880 int dpl = next_tss_desc.dpl;
2881 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2882 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2883 }
2884
7f3d35fd 2885
ceffb459
GN		 2886 desc_limit = desc_limit_scaled(&next_tss_desc);
2887 if (!next_tss_desc.p ||
2888 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2889 desc_limit < 0x2b)) {
54b8486f 2890 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2891 return X86EMUL_PROPAGATE_FAULT;
2892 }
2893
2894 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2895 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2896 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2897 }
2898
2899 if (reason == TASK_SWITCH_IRET)
2900 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2901
2902 /* set back link to prev task only if NT bit is set in eflags
fc058680 2903 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2904 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2905 old_tss_sel = 0xffff;
2906
2907 if (next_tss_desc.type & 8)
7b105ca2 2908 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2909 old_tss_base, &next_tss_desc);
2910 else
7b105ca2 2911 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2912 old_tss_base, &next_tss_desc);
0760d448
JK		 2913 if (ret != X86EMUL_CONTINUE)
2914 return ret;
38ba30ba
GN		 2915
2916 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2917 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2918
2919 if (reason != TASK_SWITCH_IRET) {
2920 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2921 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2922 }
2923
717746e3 2924 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2925 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2926
e269fb21 2927 if (has_error_code) {
9dac77fa
AK		 2928 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2929 ctxt->lock_prefix = 0;
2930 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2931 ret = em_push(ctxt);
e269fb21
JK		 2932 }
2933
38ba30ba
GN		 2934 return ret;
2935}
2936
2937int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2938 u16 tss_selector, int idt_index, int reason,
e269fb21 2939 bool has_error_code, u32 error_code)
38ba30ba 2940{
38ba30ba
GN		 2941 int rc;
2942
dd856efa 2943 invalidate_registers(ctxt);
9dac77fa
AK		 2944 ctxt->_eip = ctxt->eip;
2945 ctxt->dst.type = OP_NONE;
38ba30ba 2946
7f3d35fd 2947 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2948 has_error_code, error_code);
38ba30ba 2949
dd856efa 2950 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2951 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2952 writeback_registers(ctxt);
2953 }
38ba30ba 2954
a0c0ab2f 2955 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2956}
2957
f3bd64c6
GN		 2958static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2959 struct operand *op)
a682e354 2960{
b3356bf0 2961 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2962
dd856efa
AK		 2963 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2964 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2965}
2966
7af04fc0
AK		 2967static int em_das(struct x86_emulate_ctxt *ctxt)
2968{
7af04fc0
AK		 2969 u8 al, old_al;
2970 bool af, cf, old_cf;
2971
2972 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2973 al = ctxt->dst.val;
7af04fc0
AK		 2974
2975 old_al = al;
2976 old_cf = cf;
2977 cf = false;
2978 af = ctxt->eflags & X86_EFLAGS_AF;
2979 if ((al & 0x0f) > 9 || af) {
2980 al -= 6;
2981 cf = old_cf | (al >= 250);
2982 af = true;
2983 } else {
2984 af = false;
2985 }
2986 if (old_al > 0x99 || old_cf) {
2987 al -= 0x60;
2988 cf = true;
2989 }
2990
9dac77fa 2991 ctxt->dst.val = al;
7af04fc0 2992 /* Set PF, ZF, SF */
9dac77fa
AK		 2993 ctxt->src.type = OP_IMM;
2994 ctxt->src.val = 0;
2995 ctxt->src.bytes = 1;
158de57f 2996 fastop(ctxt, em_or);
7af04fc0
AK		 2997 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2998 if (cf)
2999 ctxt->eflags |= X86_EFLAGS_CF;
3000 if (af)
3001 ctxt->eflags |= X86_EFLAGS_AF;
3002 return X86EMUL_CONTINUE;
3003}
3004
a035d5c6
PB		 3005static int em_aam(struct x86_emulate_ctxt *ctxt)
3006{
3007 u8 al, ah;
3008
3009 if (ctxt->src.val == 0)
3010 return emulate_de(ctxt);
3011
3012 al = ctxt->dst.val & 0xff;
3013 ah = al / ctxt->src.val;
3014 al %= ctxt->src.val;
3015
3016 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3017
3018 /* Set PF, ZF, SF */
3019 ctxt->src.type = OP_IMM;
3020 ctxt->src.val = 0;
3021 ctxt->src.bytes = 1;
3022 fastop(ctxt, em_or);
3023
3024 return X86EMUL_CONTINUE;
3025}
3026
7f662273
GN		 3027static int em_aad(struct x86_emulate_ctxt *ctxt)
3028{
3029 u8 al = ctxt->dst.val & 0xff;
3030 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3031
3032 al = (al + (ah * ctxt->src.val)) & 0xff;
3033
3034 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3035
f583c29b
GN		 3036 /* Set PF, ZF, SF */
3037 ctxt->src.type = OP_IMM;
3038 ctxt->src.val = 0;
3039 ctxt->src.bytes = 1;
3040 fastop(ctxt, em_or);
7f662273
GN		 3041
3042 return X86EMUL_CONTINUE;
3043}
3044
d4ddafcd
TY		 3045static int em_call(struct x86_emulate_ctxt *ctxt)
3046{
3047 long rel = ctxt->src.val;
3048
3049 ctxt->src.val = (unsigned long)ctxt->_eip;
3050 jmp_rel(ctxt, rel);
3051 return em_push(ctxt);
3052}
3053
0ef753b8
AK		 3054static int em_call_far(struct x86_emulate_ctxt *ctxt)
3055{
0ef753b8
AK		 3056 u16 sel, old_cs;
3057 ulong old_eip;
3058 int rc;
3059
1aa36616 3060 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3061 old_eip = ctxt->_eip;
0ef753b8 3062
9dac77fa 3063 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3064 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3065 return X86EMUL_CONTINUE;
3066
9dac77fa
AK		 3067 ctxt->_eip = 0;
3068 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3069
9dac77fa 3070 ctxt->src.val = old_cs;
4487b3b4 3071 rc = em_push(ctxt);
0ef753b8
AK		 3072 if (rc != X86EMUL_CONTINUE)
3073 return rc;
3074
9dac77fa 3075 ctxt->src.val = old_eip;
4487b3b4 3076 return em_push(ctxt);
0ef753b8
AK		 3077}
3078
40ece7c7
AK		 3079static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3080{
40ece7c7
AK		 3081 int rc;
3082
9dac77fa
AK		 3083 ctxt->dst.type = OP_REG;
3084 ctxt->dst.addr.reg = &ctxt->_eip;
3085 ctxt->dst.bytes = ctxt->op_bytes;
3086 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3087 if (rc != X86EMUL_CONTINUE)
3088 return rc;
5ad105e5 3089 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3090 return X86EMUL_CONTINUE;
3091}
3092
e4f973ae
TY		 3093static int em_xchg(struct x86_emulate_ctxt *ctxt)
3094{
e4f973ae 3095 /* Write back the register source. */
9dac77fa
AK		 3096 ctxt->src.val = ctxt->dst.val;
3097 write_register_operand(&ctxt->src);
e4f973ae
TY		 3098
3099 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3100 ctxt->dst.val = ctxt->src.orig_val;
3101 ctxt->lock_prefix = 1;
e4f973ae
TY		 3102 return X86EMUL_CONTINUE;
3103}
3104
5c82aa29
AK		 3105static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3106{
9dac77fa 3107 ctxt->dst.val = ctxt->src2.val;
4d758349 3108 return fastop(ctxt, em_imul);
5c82aa29
AK		 3109}
3110
61429142
AK		 3111static int em_cwd(struct x86_emulate_ctxt *ctxt)
3112{
9dac77fa
AK		 3113 ctxt->dst.type = OP_REG;
3114 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3115 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3116 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3117
3118 return X86EMUL_CONTINUE;
3119}
3120
48bb5d3c
AK		 3121static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3122{
48bb5d3c
AK		 3123 u64 tsc = 0;
3124
717746e3 3125 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3126 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3127 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3128 return X86EMUL_CONTINUE;
3129}
3130
222d21aa
AK		 3131static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3132{
3133 u64 pmc;
3134
dd856efa 3135 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3136 return emulate_gp(ctxt, 0);
dd856efa
AK		 3137 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3138 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3139 return X86EMUL_CONTINUE;
3140}
3141
b9eac5f4
AK		 3142static int em_mov(struct x86_emulate_ctxt *ctxt)
3143{
49597d81 3144 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3145 return X86EMUL_CONTINUE;
3146}
3147
bc00f8d2
TY		 3148static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3149{
3150 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3151 return emulate_gp(ctxt, 0);
3152
3153 /* Disable writeback. */
3154 ctxt->dst.type = OP_NONE;
3155 return X86EMUL_CONTINUE;
3156}
3157
3158static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3159{
3160 unsigned long val;
3161
3162 if (ctxt->mode == X86EMUL_MODE_PROT64)
3163 val = ctxt->src.val & ~0ULL;
3164 else
3165 val = ctxt->src.val & ~0U;
3166
3167 /* #UD condition is already handled. */
3168 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3169 return emulate_gp(ctxt, 0);
3170
3171 /* Disable writeback. */
3172 ctxt->dst.type = OP_NONE;
3173 return X86EMUL_CONTINUE;
3174}
3175
e1e210b0
TY		 3176static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3177{
3178 u64 msr_data;
3179
dd856efa
AK		 3180 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3181 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3182 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3183 return emulate_gp(ctxt, 0);
3184
3185 return X86EMUL_CONTINUE;
3186}
3187
3188static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3189{
3190 u64 msr_data;
3191
dd856efa 3192 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3193 return emulate_gp(ctxt, 0);
3194
dd856efa
AK		 3195 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3196 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3197 return X86EMUL_CONTINUE;
3198}
3199
1bd5f469
TY		 3200static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3201{
9dac77fa 3202 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3203 return emulate_ud(ctxt);
3204
9dac77fa 3205 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3206 return X86EMUL_CONTINUE;
3207}
3208
3209static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3210{
9dac77fa 3211 u16 sel = ctxt->src.val;
1bd5f469 3212
9dac77fa 3213 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3214 return emulate_ud(ctxt);
3215
9dac77fa 3216 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3217 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3218
3219 /* Disable writeback. */
9dac77fa
AK		 3220 ctxt->dst.type = OP_NONE;
3221 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3222}
3223
a14e579f
AK		 3224static int em_lldt(struct x86_emulate_ctxt *ctxt)
3225{
3226 u16 sel = ctxt->src.val;
3227
3228 /* Disable writeback. */
3229 ctxt->dst.type = OP_NONE;
3230 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3231}
3232
80890006
AK		 3233static int em_ltr(struct x86_emulate_ctxt *ctxt)
3234{
3235 u16 sel = ctxt->src.val;
3236
3237 /* Disable writeback. */
3238 ctxt->dst.type = OP_NONE;
3239 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3240}
3241
38503911
AK		 3242static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3243{
9fa088f4
AK		 3244 int rc;
3245 ulong linear;
3246
9dac77fa 3247 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3248 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3249 ctxt->ops->invlpg(ctxt, linear);
38503911 3250 /* Disable writeback. */
9dac77fa 3251 ctxt->dst.type = OP_NONE;
38503911
AK		 3252 return X86EMUL_CONTINUE;
3253}
3254
2d04a05b
AK		 3255static int em_clts(struct x86_emulate_ctxt *ctxt)
3256{
3257 ulong cr0;
3258
3259 cr0 = ctxt->ops->get_cr(ctxt, 0);
3260 cr0 &= ~X86_CR0_TS;
3261 ctxt->ops->set_cr(ctxt, 0, cr0);
3262 return X86EMUL_CONTINUE;
3263}
3264
26d05cc7
AK		 3265static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3266{
26d05cc7
AK		 3267 int rc;
3268
9dac77fa 3269 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3270 return X86EMUL_UNHANDLEABLE;
3271
3272 rc = ctxt->ops->fix_hypercall(ctxt);
3273 if (rc != X86EMUL_CONTINUE)
3274 return rc;
3275
3276 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3277 ctxt->_eip = ctxt->eip;
26d05cc7 3278 /* Disable writeback. */
9dac77fa 3279 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3280 return X86EMUL_CONTINUE;
3281}
3282
96051572
AK		 3283static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3284 void (*get)(struct x86_emulate_ctxt *ctxt,
3285 struct desc_ptr *ptr))
3286{
3287 struct desc_ptr desc_ptr;
3288
3289 if (ctxt->mode == X86EMUL_MODE_PROT64)
3290 ctxt->op_bytes = 8;
3291 get(ctxt, &desc_ptr);
3292 if (ctxt->op_bytes == 2) {
3293 ctxt->op_bytes = 4;
3294 desc_ptr.address &= 0x00ffffff;
3295 }
3296 /* Disable writeback. */
3297 ctxt->dst.type = OP_NONE;
3298 return segmented_write(ctxt, ctxt->dst.addr.mem,
3299 &desc_ptr, 2 + ctxt->op_bytes);
3300}
3301
3302static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3303{
3304 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3305}
3306
3307static int em_sidt(struct x86_emulate_ctxt *ctxt)
3308{
3309 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3310}
3311
26d05cc7
AK		 3312static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3313{
26d05cc7
AK		 3314 struct desc_ptr desc_ptr;
3315 int rc;
3316
510425ff
AK		 3317 if (ctxt->mode == X86EMUL_MODE_PROT64)
3318 ctxt->op_bytes = 8;
9dac77fa 3319 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3320 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3321 ctxt->op_bytes);
26d05cc7
AK		 3322 if (rc != X86EMUL_CONTINUE)
3323 return rc;
3324 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3325 /* Disable writeback. */
9dac77fa 3326 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3327 return X86EMUL_CONTINUE;
3328}
3329
5ef39c71 3330static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3331{
26d05cc7
AK		 3332 int rc;
3333
5ef39c71
AK		 3334 rc = ctxt->ops->fix_hypercall(ctxt);
3335
26d05cc7 3336 /* Disable writeback. */
9dac77fa 3337 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3338 return rc;
3339}
3340
3341static int em_lidt(struct x86_emulate_ctxt *ctxt)
3342{
26d05cc7
AK		 3343 struct desc_ptr desc_ptr;
3344 int rc;
3345
510425ff
AK		 3346 if (ctxt->mode == X86EMUL_MODE_PROT64)
3347 ctxt->op_bytes = 8;
9dac77fa 3348 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3349 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3350 ctxt->op_bytes);
26d05cc7
AK		 3351 if (rc != X86EMUL_CONTINUE)
3352 return rc;
3353 ctxt->ops->set_idt(ctxt, &desc_ptr);
3354 /* Disable writeback. */
9dac77fa 3355 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3356 return X86EMUL_CONTINUE;
3357}
3358
3359static int em_smsw(struct x86_emulate_ctxt *ctxt)
3360{
9dac77fa
AK		 3361 ctxt->dst.bytes = 2;
3362 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3363 return X86EMUL_CONTINUE;
3364}
3365
3366static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3367{
26d05cc7 3368 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3369 | (ctxt->src.val & 0x0f));
3370 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3371 return X86EMUL_CONTINUE;
3372}
3373
d06e03ad
TY		 3374static int em_loop(struct x86_emulate_ctxt *ctxt)
3375{
dd856efa
AK		 3376 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3377 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3378 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3379 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3380
3381 return X86EMUL_CONTINUE;
3382}
3383
3384static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3385{
dd856efa 3386 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3387 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3388
3389 return X86EMUL_CONTINUE;
3390}
3391
d7841a4b
TY		 3392static int em_in(struct x86_emulate_ctxt *ctxt)
3393{
3394 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3395 &ctxt->dst.val))
3396 return X86EMUL_IO_NEEDED;
3397
3398 return X86EMUL_CONTINUE;
3399}
3400
3401static int em_out(struct x86_emulate_ctxt *ctxt)
3402{
3403 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3404 &ctxt->src.val, 1);
3405 /* Disable writeback. */
3406 ctxt->dst.type = OP_NONE;
3407 return X86EMUL_CONTINUE;
3408}
3409
f411e6cd
TY		 3410static int em_cli(struct x86_emulate_ctxt *ctxt)
3411{
3412 if (emulator_bad_iopl(ctxt))
3413 return emulate_gp(ctxt, 0);
3414
3415 ctxt->eflags &= ~X86_EFLAGS_IF;
3416 return X86EMUL_CONTINUE;
3417}
3418
3419static int em_sti(struct x86_emulate_ctxt *ctxt)
3420{
3421 if (emulator_bad_iopl(ctxt))
3422 return emulate_gp(ctxt, 0);
3423
3424 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3425 ctxt->eflags |= X86_EFLAGS_IF;
3426 return X86EMUL_CONTINUE;
3427}
3428
6d6eede4
AK		 3429static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3430{
3431 u32 eax, ebx, ecx, edx;
3432
dd856efa
AK		 3433 eax = reg_read(ctxt, VCPU_REGS_RAX);
3434 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3435 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3436 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3437 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3438 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3439 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3440 return X86EMUL_CONTINUE;
3441}
3442
2dd7caa0
AK		 3443static int em_lahf(struct x86_emulate_ctxt *ctxt)
3444{
dd856efa
AK		 3445 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3446 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3447 return X86EMUL_CONTINUE;
3448}
3449
9299836e
AK		 3450static int em_bswap(struct x86_emulate_ctxt *ctxt)
3451{
3452 switch (ctxt->op_bytes) {
3453#ifdef CONFIG_X86_64
3454 case 8:
3455 asm("bswap %0" : "+r"(ctxt->dst.val));
3456 break;
3457#endif
3458 default:
3459 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3460 break;
3461 }
3462 return X86EMUL_CONTINUE;
3463}
3464
cfec82cb
JR		 3465static bool valid_cr(int nr)
3466{
3467 switch (nr) {
3468 case 0:
3469 case 2 ... 4:
3470 case 8:
3471 return true;
3472 default:
3473 return false;
3474 }
3475}
3476
3477static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3478{
9dac77fa 3479 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3480 return emulate_ud(ctxt);
3481
3482 return X86EMUL_CONTINUE;
3483}
3484
3485static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3486{
9dac77fa
AK		 3487 u64 new_val = ctxt->src.val64;
3488 int cr = ctxt->modrm_reg;
c2ad2bb3 3489 u64 efer = 0;
cfec82cb
JR		 3490
3491 static u64 cr_reserved_bits[] = {
3492 0xffffffff00000000ULL,
3493 0, 0, 0, /* CR3 checked later */
3494 CR4_RESERVED_BITS,
3495 0, 0, 0,
3496 CR8_RESERVED_BITS,
3497 };
3498
3499 if (!valid_cr(cr))
3500 return emulate_ud(ctxt);
3501
3502 if (new_val & cr_reserved_bits[cr])
3503 return emulate_gp(ctxt, 0);
3504
3505 switch (cr) {
3506 case 0: {
c2ad2bb3 3507 u64 cr4;
cfec82cb
JR		 3508 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3509 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3510 return emulate_gp(ctxt, 0);
3511
717746e3
AK		 3512 cr4 = ctxt->ops->get_cr(ctxt, 4);
3513 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3514
3515 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3516 !(cr4 & X86_CR4_PAE))
3517 return emulate_gp(ctxt, 0);
3518
3519 break;
3520 }
3521 case 3: {
3522 u64 rsvd = 0;
3523
c2ad2bb3
AK		 3524 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3525 if (efer & EFER_LMA)
cfec82cb 3526 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3527 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3528 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3529 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3530 rsvd = CR3_NONPAE_RESERVED_BITS;
3531
3532 if (new_val & rsvd)
3533 return emulate_gp(ctxt, 0);
3534
3535 break;
3536 }
3537 case 4: {
717746e3 3538 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3539
3540 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3541 return emulate_gp(ctxt, 0);
3542
3543 break;
3544 }
3545 }
3546
3547 return X86EMUL_CONTINUE;
3548}
3549
3b88e41a
JR		 3550static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3551{
3552 unsigned long dr7;
3553
717746e3 3554 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3555
3556 /* Check if DR7.Global_Enable is set */
3557 return dr7 & (1 << 13);
3558}
3559
3560static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3561{
9dac77fa 3562 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3563 u64 cr4;
3564
3565 if (dr > 7)
3566 return emulate_ud(ctxt);
3567
717746e3 3568 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3569 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3570 return emulate_ud(ctxt);
3571
3572 if (check_dr7_gd(ctxt))
3573 return emulate_db(ctxt);
3574
3575 return X86EMUL_CONTINUE;
3576}
3577
3578static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3579{
9dac77fa
AK		 3580 u64 new_val = ctxt->src.val64;
3581 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3582
3583 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3584 return emulate_gp(ctxt, 0);
3585
3586 return check_dr_read(ctxt);
3587}
3588
01de8b09
JR		 3589static int check_svme(struct x86_emulate_ctxt *ctxt)
3590{
3591 u64 efer;
3592
717746e3 3593 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3594
3595 if (!(efer & EFER_SVME))
3596 return emulate_ud(ctxt);
3597
3598 return X86EMUL_CONTINUE;
3599}
3600
3601static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3602{
dd856efa 3603 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3604
3605 /* Valid physical address? */
d4224449 3606 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3607 return emulate_gp(ctxt, 0);
3608
3609 return check_svme(ctxt);
3610}
3611
d7eb8203
JR		 3612static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3613{
717746e3 3614 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3615
717746e3 3616 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3617 return emulate_ud(ctxt);
3618
3619 return X86EMUL_CONTINUE;
3620}
3621
8061252e
JR		 3622static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3623{
717746e3 3624 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3625 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3626
717746e3 3627 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3628 (rcx > 3))
3629 return emulate_gp(ctxt, 0);
3630
3631 return X86EMUL_CONTINUE;
3632}
3633
f6511935
JR		 3634static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3635{
9dac77fa
AK		 3636 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3637 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3638 return emulate_gp(ctxt, 0);
3639
3640 return X86EMUL_CONTINUE;
3641}
3642
3643static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3644{
9dac77fa
AK		 3645 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3646 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3647 return emulate_gp(ctxt, 0);
3648
3649 return X86EMUL_CONTINUE;
3650}
3651
73fba5f4 3652#define D(_y) { .flags = (_y) }
c4f035c6 3653#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3654#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3655 .check_perm = (_p) }
0b789eee 3656#define N D(NotImpl)
01de8b09 3657#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3658#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3659#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3660#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3661#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3662#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3663#define II(_f, _e, _i) \
3664 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3665#define IIP(_f, _e, _i, _p) \
3666 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3667 .check_perm = (_p) }
aa97bb48 3668#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3669
8d8f4e9f 3670#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3671#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3672#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3673#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3674#define I2bvIP(_f, _e, _i, _p) \
3675 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3676
fb864fbc
AK		 3677#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3678 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3679 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3680
fd0a0d82 3681static const struct opcode group7_rm1[] = {
1c2545be
TY		 3682 DI(SrcNone | Priv, monitor),
3683 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3684 N, N, N, N, N, N,
3685};
3686
fd0a0d82 3687static const struct opcode group7_rm3[] = {
1c2545be
TY		 3688 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3689 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3690 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3691 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3692 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3693 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3694 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3695 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3696};
6230f7fc 3697
fd0a0d82 3698static const struct opcode group7_rm7[] = {
d7eb8203 3699 N,
1c2545be 3700 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3701 N, N, N, N, N, N,
3702};
d67fc27a 3703
fd0a0d82 3704static const struct opcode group1[] = {
fb864fbc
AK		 3705 F(Lock, em_add),
3706 F(Lock | PageTable, em_or),
3707 F(Lock, em_adc),
3708 F(Lock, em_sbb),
3709 F(Lock | PageTable, em_and),
3710 F(Lock, em_sub),
3711 F(Lock, em_xor),
3712 F(NoWrite, em_cmp),
73fba5f4
AK		 3713};
3714
fd0a0d82 3715static const struct opcode group1A[] = {
1c2545be 3716 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3717};
3718
007a3b54
AK		 3719static const struct opcode group2[] = {
3720 F(DstMem | ModRM, em_rol),
3721 F(DstMem | ModRM, em_ror),
3722 F(DstMem | ModRM, em_rcl),
3723 F(DstMem | ModRM, em_rcr),
3724 F(DstMem | ModRM, em_shl),
3725 F(DstMem | ModRM, em_shr),
3726 F(DstMem | ModRM, em_shl),
3727 F(DstMem | ModRM, em_sar),
3728};
3729
fd0a0d82 3730static const struct opcode group3[] = {
fb864fbc
AK		 3731 F(DstMem | SrcImm | NoWrite, em_test),
3732 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3733 F(DstMem | SrcNone | Lock, em_not),
3734 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3735 F(DstXacc | Src2Mem, em_mul_ex),
3736 F(DstXacc | Src2Mem, em_imul_ex),
ab2c5ce6
AK		 3737 I(DstXacc | Src2Mem, em_div_ex),
3738 I(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3739};
3740
fd0a0d82 3741static const struct opcode group4[] = {
95413dc4
AK		 3742 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3743 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3744 N, N, N, N, N, N,
3745};
3746
fd0a0d82 3747static const struct opcode group5[] = {
95413dc4
AK		 3748 F(DstMem | SrcNone | Lock, em_inc),
3749 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3750 I(SrcMem | Stack, em_grp45),
3751 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3752 I(SrcMem | Stack, em_grp45),
3753 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3754 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3755};
3756
fd0a0d82 3757static const struct opcode group6[] = {
1c2545be
TY		 3758 DI(Prot, sldt),
3759 DI(Prot, str),
a14e579f 3760 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3761 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3762 N, N, N, N,
3763};
3764
fd0a0d82 3765static const struct group_dual group7 = { {
96051572
AK		 3766 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3767 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3768 II(SrcMem | Priv, em_lgdt, lgdt),
3769 II(SrcMem | Priv, em_lidt, lidt),
3770 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3771 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3772 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3773}, {
1c2545be 3774 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3775 EXT(0, group7_rm1),
01de8b09 3776 N, EXT(0, group7_rm3),
1c2545be
TY		 3777 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3778 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3779 EXT(0, group7_rm7),
73fba5f4
AK		 3780} };
3781
fd0a0d82 3782static const struct opcode group8[] = {
73fba5f4 3783 N, N, N, N,
11c363ba
AK		 3784 F(DstMem | SrcImmByte | NoWrite, em_bt),
3785 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3786 F(DstMem | SrcImmByte | Lock, em_btr),
3787 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3788};
3789
fd0a0d82 3790static const struct group_dual group9 = { {
1c2545be 3791 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3792}, {
3793 N, N, N, N, N, N, N, N,
3794} };
3795
fd0a0d82 3796static const struct opcode group11[] = {
1c2545be 3797 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3798 X7(D(Undefined)),
a4d4a7c1
AK		 3799};
3800
fd0a0d82 3801static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3802 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3803};
3804
fd0a0d82 3805static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3806 I(0, em_mov), N, N, N,
3807};
3808
045a282c
GN		 3809static const struct escape escape_d9 = { {
3810 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3811}, {
3812 /* 0xC0 - 0xC7 */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xC8 - 0xCF */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xD0 - 0xC7 */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xD8 - 0xDF */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xE0 - 0xE7 */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xE8 - 0xEF */
3823 N, N, N, N, N, N, N, N,
3824 /* 0xF0 - 0xF7 */
3825 N, N, N, N, N, N, N, N,
3826 /* 0xF8 - 0xFF */
3827 N, N, N, N, N, N, N, N,
3828} };
3829
3830static const struct escape escape_db = { {
3831 N, N, N, N, N, N, N, N,
3832}, {
3833 /* 0xC0 - 0xC7 */
3834 N, N, N, N, N, N, N, N,
3835 /* 0xC8 - 0xCF */
3836 N, N, N, N, N, N, N, N,
3837 /* 0xD0 - 0xC7 */
3838 N, N, N, N, N, N, N, N,
3839 /* 0xD8 - 0xDF */
3840 N, N, N, N, N, N, N, N,
3841 /* 0xE0 - 0xE7 */
3842 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3843 /* 0xE8 - 0xEF */
3844 N, N, N, N, N, N, N, N,
3845 /* 0xF0 - 0xF7 */
3846 N, N, N, N, N, N, N, N,
3847 /* 0xF8 - 0xFF */
3848 N, N, N, N, N, N, N, N,
3849} };
3850
3851static const struct escape escape_dd = { {
3852 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3853}, {
3854 /* 0xC0 - 0xC7 */
3855 N, N, N, N, N, N, N, N,
3856 /* 0xC8 - 0xCF */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xD0 - 0xC7 */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xD8 - 0xDF */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xE0 - 0xE7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xE8 - 0xEF */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xF0 - 0xF7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xF8 - 0xFF */
3869 N, N, N, N, N, N, N, N,
3870} };
3871
fd0a0d82 3872static const struct opcode opcode_table[256] = {
73fba5f4 3873 /* 0x00 - 0x07 */
fb864fbc 3874 F6ALU(Lock, em_add),
1cd196ea
AK		 3875 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3876 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3877 /* 0x08 - 0x0F */
fb864fbc 3878 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3879 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3880 N,
73fba5f4 3881 /* 0x10 - 0x17 */
fb864fbc 3882 F6ALU(Lock, em_adc),
1cd196ea
AK		 3883 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3884 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3885 /* 0x18 - 0x1F */
fb864fbc 3886 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3887 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3888 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3889 /* 0x20 - 0x27 */
fb864fbc 3890 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3891 /* 0x28 - 0x2F */
fb864fbc 3892 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3893 /* 0x30 - 0x37 */
fb864fbc 3894 F6ALU(Lock, em_xor), N, N,
73fba5f4 3895 /* 0x38 - 0x3F */
fb864fbc 3896 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3897 /* 0x40 - 0x4F */
95413dc4 3898 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3899 /* 0x50 - 0x57 */
63540382 3900 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3901 /* 0x58 - 0x5F */
c54fe504 3902 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3903 /* 0x60 - 0x67 */
b96a7fad
TY		 3904 I(ImplicitOps | Stack | No64, em_pusha),
3905 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3906 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3907 N, N, N, N,
3908 /* 0x68 - 0x6F */
d46164db
AK		 3909 I(SrcImm | Mov | Stack, em_push),
3910 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3911 I(SrcImmByte | Mov | Stack, em_push),
3912 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3913 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3914 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3915 /* 0x70 - 0x7F */
3916 X16(D(SrcImmByte)),
3917 /* 0x80 - 0x87 */
1c2545be
TY		 3918 G(ByteOp | DstMem | SrcImm, group1),
3919 G(DstMem | SrcImm, group1),
3920 G(ByteOp | DstMem | SrcImm | No64, group1),
3921 G(DstMem | SrcImmByte, group1),
fb864fbc 3922 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3923 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3924 /* 0x88 - 0x8F */
d5ae7ce8 3925 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3926 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3927 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3928 D(ModRM | SrcMem | NoAccess | DstReg),
3929 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3930 G(0, group1A),
73fba5f4 3931 /* 0x90 - 0x97 */
bf608f88 3932 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3933 /* 0x98 - 0x9F */
61429142 3934 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3935 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3936 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3937 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3938 /* 0xA0 - 0xA7 */
b9eac5f4 3939 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3940 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3941 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3942 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3943 /* 0xA8 - 0xAF */
fb864fbc 3944 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3945 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3946 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3947 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3948 /* 0xB0 - 0xB7 */
b9eac5f4 3949 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3950 /* 0xB8 - 0xBF */
5e2c6883 3951 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3952 /* 0xC0 - 0xC7 */
007a3b54 3953 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3954 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3955 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3956 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3957 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3958 G(ByteOp, group11), G(0, group11),
73fba5f4 3959 /* 0xC8 - 0xCF */
612e89f0
AK		 3960 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3961 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3962 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3963 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3964 /* 0xD0 - 0xD7 */
007a3b54
AK		 3965 G(Src2One | ByteOp, group2), G(Src2One, group2),
3966 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3967 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3968 I(DstAcc | SrcImmUByte | No64, em_aad),
3969 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3970 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3971 /* 0xD8 - 0xDF */
045a282c 3972 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3973 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3974 X3(I(SrcImmByte, em_loop)),
3975 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3976 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3977 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3978 /* 0xE8 - 0xEF */
d4ddafcd 3979 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3980 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3981 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3982 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3983 /* 0xF0 - 0xF7 */
bf608f88 3984 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3985 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3986 G(ByteOp, group3), G(0, group3),
73fba5f4 3987 /* 0xF8 - 0xFF */
f411e6cd
TY		 3988 D(ImplicitOps), D(ImplicitOps),
3989 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3990 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3991};
3992
fd0a0d82 3993static const struct opcode twobyte_table[256] = {
73fba5f4 3994 /* 0x00 - 0x0F */
dee6bb70 3995 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3996 N, I(ImplicitOps | VendorSpecific, em_syscall),
3997 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3998 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3999 N, D(ImplicitOps | ModRM), N, N,
4000 /* 0x10 - 0x1F */
4001 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
4002 /* 0x20 - 0x2F */
cfec82cb 4003 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 4004 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4005 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4006 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4007 N, N, N, N,
3e114eb4
AK		 4008 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4009 N, N, N, N,
73fba5f4 4010 /* 0x30 - 0x3F */
e1e210b0 4011 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4012 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4013 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4014 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4015 I(ImplicitOps | VendorSpecific, em_sysenter),
4016 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4017 N, N,
73fba5f4
AK		 4018 N, N, N, N, N, N, N, N,
4019 /* 0x40 - 0x4F */
4020 X16(D(DstReg | SrcMem | ModRM | Mov)),
4021 /* 0x50 - 0x5F */
4022 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4023 /* 0x60 - 0x6F */
aa97bb48
AK		 4024 N, N, N, N,
4025 N, N, N, N,
4026 N, N, N, N,
4027 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4028 /* 0x70 - 0x7F */
aa97bb48
AK		 4029 N, N, N, N,
4030 N, N, N, N,
4031 N, N, N, N,
4032 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4033 /* 0x80 - 0x8F */
4034 X16(D(SrcImm)),
4035 /* 0x90 - 0x9F */
ee45b58e 4036 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4037 /* 0xA0 - 0xA7 */
1cd196ea 4038 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4039 II(ImplicitOps, em_cpuid, cpuid),
4040 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4041 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4042 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4043 /* 0xA8 - 0xAF */
1cd196ea 4044 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4045 DI(ImplicitOps, rsm),
11c363ba 4046 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4047 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4048 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4049 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4050 /* 0xB0 - 0xB7 */
e940b5c2 4051 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4052 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4053 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4054 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4055 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4056 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4057 /* 0xB8 - 0xBF */
4058 N, N,
ce7faab2 4059 G(BitOp, group8),
11c363ba
AK		 4060 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4061 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4062 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4063 /* 0xC0 - 0xC7 */
739ae406 4064 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4065 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4066 N, N, N, GD(0, &group9),
9299836e
AK		 4067 /* 0xC8 - 0xCF */
4068 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4069 /* 0xD0 - 0xDF */
4070 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4071 /* 0xE0 - 0xEF */
4072 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4073 /* 0xF0 - 0xFF */
4074 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4075};
4076
4077#undef D
4078#undef N
4079#undef G
4080#undef GD
4081#undef I
aa97bb48 4082#undef GP
01de8b09 4083#undef EXT
73fba5f4 4084
8d8f4e9f 4085#undef D2bv
f6511935 4086#undef D2bvIP
8d8f4e9f 4087#undef I2bv
d7841a4b 4088#undef I2bvIP
d67fc27a 4089#undef I6ALU
8d8f4e9f 4090
9dac77fa 4091static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4092{
4093 unsigned size;
4094
9dac77fa 4095 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4096 if (size == 8)
4097 size = 4;
4098 return size;
4099}
4100
4101static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4102 unsigned size, bool sign_extension)
4103{
39f21ee5
AK		 4104 int rc = X86EMUL_CONTINUE;
4105
4106 op->type = OP_IMM;
4107 op->bytes = size;
9dac77fa 4108 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4109 /* NB. Immediates are sign-extended as necessary. */
4110 switch (op->bytes) {
4111 case 1:
e85a1085 4112 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4113 break;
4114 case 2:
e85a1085 4115 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4116 break;
4117 case 4:
e85a1085 4118 op->val = insn_fetch(s32, ctxt);
39f21ee5 4119 break;
5e2c6883
NA		 4120 case 8:
4121 op->val = insn_fetch(s64, ctxt);
4122 break;
39f21ee5
AK		 4123 }
4124 if (!sign_extension) {
4125 switch (op->bytes) {
4126 case 1:
4127 op->val &= 0xff;
4128 break;
4129 case 2:
4130 op->val &= 0xffff;
4131 break;
4132 case 4:
4133 op->val &= 0xffffffff;
4134 break;
4135 }
4136 }
4137done:
4138 return rc;
4139}
4140
a9945549
AK		 4141static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4142 unsigned d)
4143{
4144 int rc = X86EMUL_CONTINUE;
4145
4146 switch (d) {
4147 case OpReg:
2adb5ad9 4148 decode_register_operand(ctxt, op);
a9945549
AK		 4149 break;
4150 case OpImmUByte:
608aabe3 4151 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4152 break;
4153 case OpMem:
41ddf978 4154 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4155 mem_common:
4156 *op = ctxt->memop;
4157 ctxt->memopp = op;
4158 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4159 fetch_bit_operand(ctxt);
4160 op->orig_val = op->val;
4161 break;
41ddf978
AK		 4162 case OpMem64:
4163 ctxt->memop.bytes = 8;
4164 goto mem_common;
a9945549
AK		 4165 case OpAcc:
4166 op->type = OP_REG;
4167 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4168 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4169 fetch_register_operand(op);
4170 op->orig_val = op->val;
4171 break;
820207c8
AK		 4172 case OpAccLo:
4173 op->type = OP_REG;
4174 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4175 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4176 fetch_register_operand(op);
4177 op->orig_val = op->val;
4178 break;
4179 case OpAccHi:
4180 if (ctxt->d & ByteOp) {
4181 op->type = OP_NONE;
4182 break;
4183 }
4184 op->type = OP_REG;
4185 op->bytes = ctxt->op_bytes;
4186 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4187 fetch_register_operand(op);
4188 op->orig_val = op->val;
4189 break;
a9945549
AK		 4190 case OpDI:
4191 op->type = OP_MEM;
4192 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4193 op->addr.mem.ea =
dd856efa 4194 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4195 op->addr.mem.seg = VCPU_SREG_ES;
4196 op->val = 0;
b3356bf0 4197 op->count = 1;
a9945549
AK		 4198 break;
4199 case OpDX:
4200 op->type = OP_REG;
4201 op->bytes = 2;
dd856efa 4202 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4203 fetch_register_operand(op);
4204 break;
4dd6a57d
AK		 4205 case OpCL:
4206 op->bytes = 1;
dd856efa 4207 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4208 break;
4209 case OpImmByte:
4210 rc = decode_imm(ctxt, op, 1, true);
4211 break;
4212 case OpOne:
4213 op->bytes = 1;
4214 op->val = 1;
4215 break;
4216 case OpImm:
4217 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4218 break;
5e2c6883
NA		 4219 case OpImm64:
4220 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4221 break;
28867cee
AK		 4222 case OpMem8:
4223 ctxt->memop.bytes = 1;
660696d1
GN		 4224 if (ctxt->memop.type == OP_REG) {
4225 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4226 fetch_register_operand(&ctxt->memop);
4227 }
28867cee 4228 goto mem_common;
0fe59128
AK		 4229 case OpMem16:
4230 ctxt->memop.bytes = 2;
4231 goto mem_common;
4232 case OpMem32:
4233 ctxt->memop.bytes = 4;
4234 goto mem_common;
4235 case OpImmU16:
4236 rc = decode_imm(ctxt, op, 2, false);
4237 break;
4238 case OpImmU:
4239 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4240 break;
4241 case OpSI:
4242 op->type = OP_MEM;
4243 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4244 op->addr.mem.ea =
dd856efa 4245 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4246 op->addr.mem.seg = seg_override(ctxt);
4247 op->val = 0;
b3356bf0 4248 op->count = 1;
0fe59128 4249 break;
7fa57952
PB		 4250 case OpXLat:
4251 op->type = OP_MEM;
4252 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4253 op->addr.mem.ea =
4254 register_address(ctxt,
4255 reg_read(ctxt, VCPU_REGS_RBX) +
4256 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4257 op->addr.mem.seg = seg_override(ctxt);
4258 op->val = 0;
4259 break;
0fe59128
AK		 4260 case OpImmFAddr:
4261 op->type = OP_IMM;
4262 op->addr.mem.ea = ctxt->_eip;
4263 op->bytes = ctxt->op_bytes + 2;
4264 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4265 break;
4266 case OpMemFAddr:
4267 ctxt->memop.bytes = ctxt->op_bytes + 2;
4268 goto mem_common;
c191a7a0
AK		 4269 case OpES:
4270 op->val = VCPU_SREG_ES;
4271 break;
4272 case OpCS:
4273 op->val = VCPU_SREG_CS;
4274 break;
4275 case OpSS:
4276 op->val = VCPU_SREG_SS;
4277 break;
4278 case OpDS:
4279 op->val = VCPU_SREG_DS;
4280 break;
4281 case OpFS:
4282 op->val = VCPU_SREG_FS;
4283 break;
4284 case OpGS:
4285 op->val = VCPU_SREG_GS;
4286 break;
a9945549
AK		 4287 case OpImplicit:
4288 /* Special instructions do their own operand decoding. */
4289 default:
4290 op->type = OP_NONE; /* Disable writeback. */
4291 break;
4292 }
4293
4294done:
4295 return rc;
4296}
4297
ef5d75cc 4298int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4299{
dde7e6d1
AK		 4300 int rc = X86EMUL_CONTINUE;
4301 int mode = ctxt->mode;
46561646 4302 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4303 bool op_prefix = false;
46561646 4304 struct opcode opcode;
dde7e6d1 4305
f09ed83e
AK		 4306 ctxt->memop.type = OP_NONE;
4307 ctxt->memopp = NULL;
9dac77fa
AK		 4308 ctxt->_eip = ctxt->eip;
4309 ctxt->fetch.start = ctxt->_eip;
4310 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4311 if (insn_len > 0)
9dac77fa 4312 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4313
4314 switch (mode) {
4315 case X86EMUL_MODE_REAL:
4316 case X86EMUL_MODE_VM86:
4317 case X86EMUL_MODE_PROT16:
4318 def_op_bytes = def_ad_bytes = 2;
4319 break;
4320 case X86EMUL_MODE_PROT32:
4321 def_op_bytes = def_ad_bytes = 4;
4322 break;
4323#ifdef CONFIG_X86_64
4324 case X86EMUL_MODE_PROT64:
4325 def_op_bytes = 4;
4326 def_ad_bytes = 8;
4327 break;
4328#endif
4329 default:
1d2887e2 4330 return EMULATION_FAILED;
dde7e6d1
AK		 4331 }
4332
9dac77fa
AK		 4333 ctxt->op_bytes = def_op_bytes;
4334 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4335
4336 /* Legacy prefixes. */
4337 for (;;) {
e85a1085 4338 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4339 case 0x66: /* operand-size override */
0d7cdee8 4340 op_prefix = true;
dde7e6d1 4341 /* switch between 2/4 bytes */
9dac77fa 4342 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4343 break;
4344 case 0x67: /* address-size override */
4345 if (mode == X86EMUL_MODE_PROT64)
4346 /* switch between 4/8 bytes */
9dac77fa 4347 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4348 else
4349 /* switch between 2/4 bytes */
9dac77fa 4350 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4351 break;
4352 case 0x26: /* ES override */
4353 case 0x2e: /* CS override */
4354 case 0x36: /* SS override */
4355 case 0x3e: /* DS override */
9dac77fa 4356 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4357 break;
4358 case 0x64: /* FS override */
4359 case 0x65: /* GS override */
9dac77fa 4360 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4361 break;
4362 case 0x40 ... 0x4f: /* REX */
4363 if (mode != X86EMUL_MODE_PROT64)
4364 goto done_prefixes;
9dac77fa 4365 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4366 continue;
4367 case 0xf0: /* LOCK */
9dac77fa 4368 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4369 break;
4370 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4371 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4372 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4373 break;
4374 default:
4375 goto done_prefixes;
4376 }
4377
4378 /* Any legacy prefix after a REX prefix nullifies its effect. */
4379
9dac77fa 4380 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4381 }
4382
4383done_prefixes:
4384
4385 /* REX prefix. */
9dac77fa
AK		 4386 if (ctxt->rex_prefix & 8)
4387 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4388
4389 /* Opcode byte(s). */
9dac77fa 4390 opcode = opcode_table[ctxt->b];
d3ad6243 4391 /* Two-byte opcode? */
9dac77fa
AK		 4392 if (ctxt->b == 0x0f) {
4393 ctxt->twobyte = 1;
e85a1085 4394 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4395 opcode = twobyte_table[ctxt->b];
dde7e6d1 4396 }
9dac77fa 4397 ctxt->d = opcode.flags;
dde7e6d1 4398
9f4260e7
TY		 4399 if (ctxt->d & ModRM)
4400 ctxt->modrm = insn_fetch(u8, ctxt);
4401
9dac77fa
AK		 4402 while (ctxt->d & GroupMask) {
4403 switch (ctxt->d & GroupMask) {
46561646 4404 case Group:
9dac77fa 4405 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4406 opcode = opcode.u.group[goffset];
4407 break;
4408 case GroupDual:
9dac77fa
AK		 4409 goffset = (ctxt->modrm >> 3) & 7;
4410 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4411 opcode = opcode.u.gdual->mod3[goffset];
4412 else
4413 opcode = opcode.u.gdual->mod012[goffset];
4414 break;
4415 case RMExt:
9dac77fa 4416 goffset = ctxt->modrm & 7;
01de8b09 4417 opcode = opcode.u.group[goffset];
46561646
AK		 4418 break;
4419 case Prefix:
9dac77fa 4420 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4421 return EMULATION_FAILED;
9dac77fa 4422 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4423 switch (simd_prefix) {
4424 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4425 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4426 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4427 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4428 }
4429 break;
045a282c
GN		 4430 case Escape:
4431 if (ctxt->modrm > 0xbf)
4432 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4433 else
4434 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4435 break;
46561646 4436 default:
1d2887e2 4437 return EMULATION_FAILED;
0d7cdee8 4438 }
46561646 4439
b1ea50b2 4440 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4441 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4442 }
4443
9dac77fa
AK		 4444 ctxt->execute = opcode.u.execute;
4445 ctxt->check_perm = opcode.check_perm;
4446 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4447
4448 /* Unrecognised? */
1146a78b 4449 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4450 return EMULATION_FAILED;
dde7e6d1 4451
9dac77fa 4452 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4453 return EMULATION_FAILED;
d867162c 4454
9dac77fa
AK		 4455 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4456 ctxt->op_bytes = 8;
dde7e6d1 4457
9dac77fa 4458 if (ctxt->d & Op3264) {
7f9b4b75 4459 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4460 ctxt->op_bytes = 8;
7f9b4b75 4461 else
9dac77fa 4462 ctxt->op_bytes = 4;
7f9b4b75
AK		 4463 }
4464
9dac77fa
AK		 4465 if (ctxt->d & Sse)
4466 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4467 else if (ctxt->d & Mmx)
4468 ctxt->op_bytes = 8;
1253791d 4469
dde7e6d1 4470 /* ModRM and SIB bytes. */
9dac77fa 4471 if (ctxt->d & ModRM) {
f09ed83e 4472 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4473 if (!ctxt->has_seg_override)
4474 set_seg_override(ctxt, ctxt->modrm_seg);
4475 } else if (ctxt->d & MemAbs)
f09ed83e 4476 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4477 if (rc != X86EMUL_CONTINUE)
4478 goto done;
4479
9dac77fa
AK		 4480 if (!ctxt->has_seg_override)
4481 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4482
f09ed83e 4483 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4484
f09ed83e
AK		 4485 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4486 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4487
dde7e6d1
AK		 4488 /*
4489 * Decode and fetch the source operand: register, memory
4490 * or immediate.
4491 */
0fe59128 4492 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4493 if (rc != X86EMUL_CONTINUE)
4494 goto done;
4495
dde7e6d1
AK		 4496 /*
4497 * Decode and fetch the second source operand: register, memory
4498 * or immediate.
4499 */
4dd6a57d 4500 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4501 if (rc != X86EMUL_CONTINUE)
4502 goto done;
4503
dde7e6d1 4504 /* Decode and fetch the destination operand: register or memory. */
a9945549 4505 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4506
4507done:
f09ed83e
AK		 4508 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4509 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4510
1d2887e2 4511 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4512}
4513
1cb3f3ae
XG		 4514bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4515{
4516 return ctxt->d & PageTable;
4517}
4518
3e2f65d5
GN		 4519static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4520{
3e2f65d5
GN		 4521 /* The second termination condition only applies for REPE
4522 * and REPNE. Test if the repeat string operation prefix is
4523 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4524 * corresponding termination condition according to:
4525 * - if REPE/REPZ and ZF = 0 then done
4526 * - if REPNE/REPNZ and ZF = 1 then done
4527 */
9dac77fa
AK		 4528 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4529 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4530 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4531 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4532 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4533 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4534 return true;
4535
4536 return false;
4537}
4538
cbe2c9d3
AK		 4539static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4540{
4541 bool fault = false;
4542
4543 ctxt->ops->get_fpu(ctxt);
4544 asm volatile("1: fwait \n\t"
4545 "2: \n\t"
4546 ".pushsection .fixup,\"ax\" \n\t"
4547 "3: \n\t"
4548 "movb $1, %[fault] \n\t"
4549 "jmp 2b \n\t"
4550 ".popsection \n\t"
4551 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4552 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4553 ctxt->ops->put_fpu(ctxt);
4554
4555 if (unlikely(fault))
4556 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4557
4558 return X86EMUL_CONTINUE;
4559}
4560
4561static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4562 struct operand *op)
4563{
4564 if (op->type == OP_MM)
4565 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4566}
4567
e28bbd44
AK		 4568static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4569{
4570 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4571 if (!(ctxt->d & ByteOp))
4572 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4573 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
017da7b6 4574 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags)
e28bbd44
AK		 4575 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4576 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4577 return X86EMUL_CONTINUE;
4578}
dd856efa 4579
7b105ca2 4580int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4581{
0225fb50 4582 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4583 int rc = X86EMUL_CONTINUE;
9dac77fa 4584 int saved_dst_type = ctxt->dst.type;
8b4caf66 4585
9dac77fa 4586 ctxt->mem_read.pos = 0;
310b5d30 4587
1146a78b
GN		 4588 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4589 (ctxt->d & Undefined)) {
35d3d4a1 4590 rc = emulate_ud(ctxt);
1161624f
GN		 4591 goto done;
4592 }
4593
d380a5e4 4594 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4595 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4596 rc = emulate_ud(ctxt);
d380a5e4
GN		 4597 goto done;
4598 }
4599
9dac77fa 4600 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4601 rc = emulate_ud(ctxt);
081bca0e
AK		 4602 goto done;
4603 }
4604
cbe2c9d3
AK		 4605 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4606 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4607 rc = emulate_ud(ctxt);
4608 goto done;
4609 }
4610
cbe2c9d3 4611 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4612 rc = emulate_nm(ctxt);
4613 goto done;
4614 }
4615
cbe2c9d3
AK		 4616 if (ctxt->d & Mmx) {
4617 rc = flush_pending_x87_faults(ctxt);
4618 if (rc != X86EMUL_CONTINUE)
4619 goto done;
4620 /*
4621 * Now that we know the fpu is exception safe, we can fetch
4622 * operands from it.
4623 */
4624 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4625 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4626 if (!(ctxt->d & Mov))
4627 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4628 }
4629
9dac77fa
AK		 4630 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4631 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4632 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4633 if (rc != X86EMUL_CONTINUE)
4634 goto done;
4635 }
4636
e92805ac 4637 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4638 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4639 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4640 goto done;
4641 }
4642
8ea7d6ae 4643 /* Instruction can only be executed in protected mode */
9d1b39a9 4644 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4645 rc = emulate_ud(ctxt);
4646 goto done;
4647 }
4648
d09beabd 4649 /* Do instruction specific permission checks */
9dac77fa
AK		 4650 if (ctxt->check_perm) {
4651 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4652 if (rc != X86EMUL_CONTINUE)
4653 goto done;
4654 }
4655
9dac77fa
AK		 4656 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4657 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4658 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4659 if (rc != X86EMUL_CONTINUE)
4660 goto done;
4661 }
4662
9dac77fa 4663 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4664 /* All REP prefixes have the same first termination condition */
dd856efa 4665 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4666 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4667 goto done;
4668 }
b9fa9d6b
AK		 4669 }
4670
9dac77fa
AK		 4671 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4672 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4673 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4674 if (rc != X86EMUL_CONTINUE)
8b4caf66 4675 goto done;
9dac77fa 4676 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4677 }
4678
9dac77fa
AK		 4679 if (ctxt->src2.type == OP_MEM) {
4680 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4681 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4682 if (rc != X86EMUL_CONTINUE)
4683 goto done;
4684 }
4685
9dac77fa 4686 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4687 goto special_insn;
4688
4689
9dac77fa 4690 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4691 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4692 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4693 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4694 if (rc != X86EMUL_CONTINUE)
4695 goto done;
038e51de 4696 }
9dac77fa 4697 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4698
018a98db
AK		 4699special_insn:
4700
9dac77fa
AK		 4701 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4702 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4703 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4704 if (rc != X86EMUL_CONTINUE)
4705 goto done;
4706 }
4707
9dac77fa 4708 if (ctxt->execute) {
e28bbd44
AK		 4709 if (ctxt->d & Fastop) {
4710 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4711 rc = fastop(ctxt, fop);
4712 if (rc != X86EMUL_CONTINUE)
4713 goto done;
4714 goto writeback;
4715 }
9dac77fa 4716 rc = ctxt->execute(ctxt);
ef65c889
AK		 4717 if (rc != X86EMUL_CONTINUE)
4718 goto done;
4719 goto writeback;
4720 }
4721
9dac77fa 4722 if (ctxt->twobyte)
6aa8b732
AK		 4723 goto twobyte_insn;
4724
9dac77fa 4725 switch (ctxt->b) {
6aa8b732 4726 case 0x63: /* movsxd */
8b4caf66 4727 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4728 goto cannot_emulate;
9dac77fa 4729 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4730 break;
b2833e3c 4731 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4732 if (test_cc(ctxt->b, ctxt->eflags))
4733 jmp_rel(ctxt, ctxt->src.val);
018a98db 4734 break;
7e0b54b1 4735 case 0x8d: /* lea r16/r32, m */
9dac77fa 4736 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4737 break;
3d9e77df 4738 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4739 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4740 break;
e4f973ae
TY		 4741 rc = em_xchg(ctxt);
4742 break;
e8b6fa70 4743 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4744 switch (ctxt->op_bytes) {
4745 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4746 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4747 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4748 }
4749 break;
6e154e56 4750 case 0xcc: /* int3 */
5c5df76b
TY		 4751 rc = emulate_int(ctxt, 3);
4752 break;
6e154e56 4753 case 0xcd: /* int n */
9dac77fa 4754 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4755 break;
4756 case 0xce: /* into */
5c5df76b
TY		 4757 if (ctxt->eflags & EFLG_OF)
4758 rc = emulate_int(ctxt, 4);
6e154e56 4759 break;
1a52e051 4760 case 0xe9: /* jmp rel */
db5b0762 4761 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4762 jmp_rel(ctxt, ctxt->src.val);
4763 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4764 break;
111de5d6 4765 case 0xf4: /* hlt */
6c3287f7 4766 ctxt->ops->halt(ctxt);
19fdfa0d 4767 break;
111de5d6
AK		 4768 case 0xf5: /* cmc */
4769 /* complement carry flag from eflags reg */
4770 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4771 break;
4772 case 0xf8: /* clc */
4773 ctxt->eflags &= ~EFLG_CF;
111de5d6 4774 break;
8744aa9a
MG		 4775 case 0xf9: /* stc */
4776 ctxt->eflags |= EFLG_CF;
4777 break;
fb4616f4
MG		 4778 case 0xfc: /* cld */
4779 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4780 break;
4781 case 0xfd: /* std */
4782 ctxt->eflags |= EFLG_DF;
fb4616f4 4783 break;
91269b8f
AK		 4784 default:
4785 goto cannot_emulate;
6aa8b732 4786 }
018a98db 4787
7d9ddaed
AK		 4788 if (rc != X86EMUL_CONTINUE)
4789 goto done;
4790
018a98db 4791writeback:
fb32b1ed
AK		 4792 if (!(ctxt->d & NoWrite)) {
4793 rc = writeback(ctxt, &ctxt->dst);
4794 if (rc != X86EMUL_CONTINUE)
4795 goto done;
4796 }
4797 if (ctxt->d & SrcWrite) {
4798 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4799 rc = writeback(ctxt, &ctxt->src);
4800 if (rc != X86EMUL_CONTINUE)
4801 goto done;
4802 }
018a98db 4803
5cd21917
GN		 4804 /*
4805 * restore dst type in case the decoding will be reused
4806 * (happens for string instruction )
4807 */
9dac77fa 4808 ctxt->dst.type = saved_dst_type;
5cd21917 4809
9dac77fa 4810 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4811 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4812
9dac77fa 4813 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4814 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4815
9dac77fa 4816 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4817 unsigned int count;
9dac77fa 4818 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4819 if ((ctxt->d & SrcMask) == SrcSI)
4820 count = ctxt->src.count;
4821 else
4822 count = ctxt->dst.count;
4823 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4824 -count);
3e2f65d5 4825
d2ddd1c4
GN		 4826 if (!string_insn_completed(ctxt)) {
4827 /*
4828 * Re-enter guest when pio read ahead buffer is empty
4829 * or, if it is not used, after each 1024 iteration.
4830 */
dd856efa 4831 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4832 (r->end == 0 || r->end != r->pos)) {
4833 /*
4834 * Reset read cache. Usually happens before
4835 * decode, but since instruction is restarted
4836 * we have to do it here.
4837 */
9dac77fa 4838 ctxt->mem_read.end = 0;
dd856efa 4839 writeback_registers(ctxt);
d2ddd1c4
GN		 4840 return EMULATION_RESTART;
4841 }
4842 goto done; /* skip rip writeback */
0fa6ccbd 4843 }
5cd21917 4844 }
d2ddd1c4 4845
9dac77fa 4846 ctxt->eip = ctxt->_eip;
018a98db
AK		 4847
4848done:
da9cb575
AK		 4849 if (rc == X86EMUL_PROPAGATE_FAULT)
4850 ctxt->have_exception = true;
775fde86
JR		 4851 if (rc == X86EMUL_INTERCEPTED)
4852 return EMULATION_INTERCEPTED;
4853
dd856efa
AK		 4854 if (rc == X86EMUL_CONTINUE)
4855 writeback_registers(ctxt);
4856
d2ddd1c4 4857 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4858
4859twobyte_insn:
9dac77fa 4860 switch (ctxt->b) {
018a98db 4861 case 0x09: /* wbinvd */
cfb22375 4862 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4863 break;
4864 case 0x08: /* invd */
018a98db
AK		 4865 case 0x0d: /* GrpP (prefetch) */
4866 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4867 break;
4868 case 0x20: /* mov cr, reg */
9dac77fa 4869 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4870 break;
6aa8b732 4871 case 0x21: /* mov from dr to reg */
9dac77fa 4872 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4873 break;
6aa8b732 4874 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4875 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4876 if (!test_cc(ctxt->b, ctxt->eflags))
4877 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4878 break;
b2833e3c 4879 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4880 if (test_cc(ctxt->b, ctxt->eflags))
4881 jmp_rel(ctxt, ctxt->src.val);
018a98db 4882 break;
ee45b58e 4883 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4884 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4885 break;
2a7c5b8b
GC		 4886 case 0xae: /* clflush */
4887 break;
6aa8b732 4888 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4889 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4890 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4891 : (u16) ctxt->src.val;
6aa8b732 4892 break;
6aa8b732 4893 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4894 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4895 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4896 (s16) ctxt->src.val;
6aa8b732 4897 break;
92f738a5 4898 case 0xc0 ... 0xc1: /* xadd */
158de57f 4899 fastop(ctxt, em_add);
92f738a5 4900 /* Write back the register source. */
9dac77fa
AK		 4901 ctxt->src.val = ctxt->dst.orig_val;
4902 write_register_operand(&ctxt->src);
92f738a5 4903 break;
a012e65a 4904 case 0xc3: /* movnti */
9dac77fa
AK		 4905 ctxt->dst.bytes = ctxt->op_bytes;
4906 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4907 (u64) ctxt->src.val;
a012e65a 4908 break;
91269b8f
AK		 4909 default:
4910 goto cannot_emulate;
6aa8b732 4911 }
7d9ddaed
AK		 4912
4913 if (rc != X86EMUL_CONTINUE)
4914 goto done;
4915
6aa8b732
AK		 4916 goto writeback;
4917
4918cannot_emulate:
a0c0ab2f 4919 return EMULATION_FAILED;
6aa8b732 4920}
dd856efa
AK		 4921
4922void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4923{
4924 invalidate_registers(ctxt);
4925}
4926
4927void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4928{
4929 writeback_registers(ctxt);
4930}
Linux kernel - Deliverables
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