Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
6aa8b732 AK |
31 | /* |
32 | * Opcode effective-address decode tables. | |
33 | * Note that we only emulate instructions that have at least one memory | |
34 | * operand (excluding implicit stack references). We assume that stack | |
35 | * references and instruction fetches will never occur in special memory | |
36 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
37 | * not be handled. | |
38 | */ | |
39 | ||
40 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 41 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 42 | /* Destination operand type. */ |
ab85b12b AK |
43 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
44 | #define DstReg (2<<1) /* Register operand. */ | |
45 | #define DstMem (3<<1) /* Memory operand. */ | |
46 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
47 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
48 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 49 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 50 | #define DstMask (7<<1) |
6aa8b732 | 51 | /* Source operand type. */ |
9c9fddd0 | 52 | #define SrcNone (0<<4) /* No source operand. */ |
9c9fddd0 GT |
53 | #define SrcReg (1<<4) /* Register operand. */ |
54 | #define SrcMem (2<<4) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<4) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 59 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 60 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 61 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 62 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
63 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
64 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 65 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
b250e605 | 66 | #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */ |
341de7e3 | 67 | #define SrcMask (0xf<<4) |
6aa8b732 | 68 | /* Generic ModRM decode. */ |
341de7e3 | 69 | #define ModRM (1<<8) |
6aa8b732 | 70 | /* Destination is only written; never read. */ |
341de7e3 GN |
71 | #define Mov (1<<9) |
72 | #define BitOp (1<<10) | |
73 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
74 | #define String (1<<12) /* String instruction (rep capable) */ |
75 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
76 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
77 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
d8769fed | 78 | /* Misc flags */ |
5a506b12 | 79 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 80 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 81 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 82 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 83 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 84 | #define No64 (1<<28) |
0dc8d10f GT |
85 | /* Source 2 operand type */ |
86 | #define Src2None (0<<29) | |
87 | #define Src2CL (1<<29) | |
88 | #define Src2ImmByte (2<<29) | |
89 | #define Src2One (3<<29) | |
7db41eb7 | 90 | #define Src2Imm (4<<29) |
0dc8d10f | 91 | #define Src2Mask (7<<29) |
6aa8b732 | 92 | |
d0e53325 AK |
93 | #define X2(x...) x, x |
94 | #define X3(x...) X2(x), x | |
95 | #define X4(x...) X2(x), X2(x) | |
96 | #define X5(x...) X4(x), x | |
97 | #define X6(x...) X4(x), X2(x) | |
98 | #define X7(x...) X4(x), X3(x) | |
99 | #define X8(x...) X4(x), X4(x) | |
100 | #define X16(x...) X8(x), X8(x) | |
83babbca | 101 | |
d65b1dee AK |
102 | struct opcode { |
103 | u32 flags; | |
120df890 | 104 | union { |
ef65c889 | 105 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
106 | struct opcode *group; |
107 | struct group_dual *gdual; | |
108 | } u; | |
109 | }; | |
110 | ||
111 | struct group_dual { | |
112 | struct opcode mod012[8]; | |
113 | struct opcode mod3[8]; | |
d65b1dee AK |
114 | }; |
115 | ||
6aa8b732 | 116 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
117 | #define EFLG_ID (1<<21) |
118 | #define EFLG_VIP (1<<20) | |
119 | #define EFLG_VIF (1<<19) | |
120 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
121 | #define EFLG_VM (1<<17) |
122 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
123 | #define EFLG_IOPL (3<<12) |
124 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
125 | #define EFLG_OF (1<<11) |
126 | #define EFLG_DF (1<<10) | |
b1d86143 | 127 | #define EFLG_IF (1<<9) |
d4c6a154 | 128 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
129 | #define EFLG_SF (1<<7) |
130 | #define EFLG_ZF (1<<6) | |
131 | #define EFLG_AF (1<<4) | |
132 | #define EFLG_PF (1<<2) | |
133 | #define EFLG_CF (1<<0) | |
134 | ||
62bd430e MG |
135 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
136 | #define EFLG_RESERVED_ONE_MASK 2 | |
137 | ||
6aa8b732 AK |
138 | /* |
139 | * Instruction emulation: | |
140 | * Most instructions are emulated directly via a fragment of inline assembly | |
141 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
142 | * any modified flags. | |
143 | */ | |
144 | ||
05b3e0c2 | 145 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
146 | #define _LO32 "k" /* force 32-bit operand */ |
147 | #define _STK "%%rsp" /* stack pointer */ | |
148 | #elif defined(__i386__) | |
149 | #define _LO32 "" /* force 32-bit operand */ | |
150 | #define _STK "%%esp" /* stack pointer */ | |
151 | #endif | |
152 | ||
153 | /* | |
154 | * These EFLAGS bits are restored from saved value during emulation, and | |
155 | * any changes are written back to the saved value after emulation. | |
156 | */ | |
157 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
158 | ||
159 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
160 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
161 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
162 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
163 | "push %"_tmp"; " \ | |
164 | "push %"_tmp"; " \ | |
165 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
166 | "andl %"_LO32 _tmp",("_STK"); " \ | |
167 | "pushf; " \ | |
168 | "notl %"_LO32 _tmp"; " \ | |
169 | "andl %"_LO32 _tmp",("_STK"); " \ | |
170 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
171 | "pop %"_tmp"; " \ | |
172 | "orl %"_LO32 _tmp",("_STK"); " \ | |
173 | "popf; " \ | |
174 | "pop %"_sav"; " | |
6aa8b732 AK |
175 | |
176 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
177 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
178 | /* _sav |= EFLAGS & _msk; */ \ | |
179 | "pushf; " \ | |
180 | "pop %"_tmp"; " \ | |
181 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
182 | "orl %"_LO32 _tmp",%"_sav"; " | |
183 | ||
dda96d8f AK |
184 | #ifdef CONFIG_X86_64 |
185 | #define ON64(x) x | |
186 | #else | |
187 | #define ON64(x) | |
188 | #endif | |
189 | ||
b3b3d25a | 190 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
191 | do { \ |
192 | __asm__ __volatile__ ( \ | |
193 | _PRE_EFLAGS("0", "4", "2") \ | |
194 | _op _suffix " %"_x"3,%1; " \ | |
195 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 196 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
197 | "=&r" (_tmp) \ |
198 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 199 | } while (0) |
6b7ad61f AK |
200 | |
201 | ||
6aa8b732 AK |
202 | /* Raw emulation: instruction has two explicit operands. */ |
203 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
204 | do { \ |
205 | unsigned long _tmp; \ | |
206 | \ | |
207 | switch ((_dst).bytes) { \ | |
208 | case 2: \ | |
b3b3d25a | 209 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
210 | break; \ |
211 | case 4: \ | |
b3b3d25a | 212 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
213 | break; \ |
214 | case 8: \ | |
b3b3d25a | 215 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
216 | break; \ |
217 | } \ | |
6aa8b732 AK |
218 | } while (0) |
219 | ||
220 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
221 | do { \ | |
6b7ad61f | 222 | unsigned long _tmp; \ |
d77c26fc | 223 | switch ((_dst).bytes) { \ |
6aa8b732 | 224 | case 1: \ |
b3b3d25a | 225 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
226 | break; \ |
227 | default: \ | |
228 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
229 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
230 | break; \ | |
231 | } \ | |
232 | } while (0) | |
233 | ||
234 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
235 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
236 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
237 | "b", "c", "b", "c", "b", "c", "b", "c") | |
238 | ||
239 | /* Source operand is byte, word, long or quad sized. */ | |
240 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
241 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
242 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
243 | ||
244 | /* Source operand is word, long or quad sized. */ | |
245 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
246 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
247 | "w", "r", _LO32, "r", "", "r") | |
248 | ||
d175226a GT |
249 | /* Instruction has three operands and one operand is stored in ECX register */ |
250 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
251 | do { \ | |
252 | unsigned long _tmp; \ | |
253 | _type _clv = (_cl).val; \ | |
254 | _type _srcv = (_src).val; \ | |
255 | _type _dstv = (_dst).val; \ | |
256 | \ | |
257 | __asm__ __volatile__ ( \ | |
258 | _PRE_EFLAGS("0", "5", "2") \ | |
259 | _op _suffix " %4,%1 \n" \ | |
260 | _POST_EFLAGS("0", "5", "2") \ | |
261 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
262 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
263 | ); \ | |
264 | \ | |
265 | (_cl).val = (unsigned long) _clv; \ | |
266 | (_src).val = (unsigned long) _srcv; \ | |
267 | (_dst).val = (unsigned long) _dstv; \ | |
268 | } while (0) | |
269 | ||
270 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
271 | do { \ | |
272 | switch ((_dst).bytes) { \ | |
273 | case 2: \ | |
274 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
275 | "w", unsigned short); \ | |
276 | break; \ | |
277 | case 4: \ | |
278 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
279 | "l", unsigned int); \ | |
280 | break; \ | |
281 | case 8: \ | |
282 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
283 | "q", unsigned long)); \ | |
284 | break; \ | |
285 | } \ | |
286 | } while (0) | |
287 | ||
dda96d8f | 288 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
289 | do { \ |
290 | unsigned long _tmp; \ | |
291 | \ | |
dda96d8f AK |
292 | __asm__ __volatile__ ( \ |
293 | _PRE_EFLAGS("0", "3", "2") \ | |
294 | _op _suffix " %1; " \ | |
295 | _POST_EFLAGS("0", "3", "2") \ | |
296 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
297 | "=&r" (_tmp) \ | |
298 | : "i" (EFLAGS_MASK)); \ | |
299 | } while (0) | |
300 | ||
301 | /* Instruction has only one explicit operand (no source operand). */ | |
302 | #define emulate_1op(_op, _dst, _eflags) \ | |
303 | do { \ | |
d77c26fc | 304 | switch ((_dst).bytes) { \ |
dda96d8f AK |
305 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
306 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
307 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
308 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
309 | } \ |
310 | } while (0) | |
311 | ||
3f9f53b0 MG |
312 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
313 | do { \ | |
314 | unsigned long _tmp; \ | |
315 | \ | |
316 | __asm__ __volatile__ ( \ | |
317 | _PRE_EFLAGS("0", "4", "1") \ | |
318 | _op _suffix " %5; " \ | |
319 | _POST_EFLAGS("0", "4", "1") \ | |
320 | : "=m" (_eflags), "=&r" (_tmp), \ | |
321 | "+a" (_rax), "+d" (_rdx) \ | |
322 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
323 | "a" (_rax), "d" (_rdx)); \ | |
324 | } while (0) | |
325 | ||
f6b3597b AK |
326 | #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \ |
327 | do { \ | |
328 | unsigned long _tmp; \ | |
329 | \ | |
330 | __asm__ __volatile__ ( \ | |
331 | _PRE_EFLAGS("0", "5", "1") \ | |
332 | "1: \n\t" \ | |
333 | _op _suffix " %6; " \ | |
334 | "2: \n\t" \ | |
335 | _POST_EFLAGS("0", "5", "1") \ | |
336 | ".pushsection .fixup,\"ax\" \n\t" \ | |
337 | "3: movb $1, %4 \n\t" \ | |
338 | "jmp 2b \n\t" \ | |
339 | ".popsection \n\t" \ | |
340 | _ASM_EXTABLE(1b, 3b) \ | |
341 | : "=m" (_eflags), "=&r" (_tmp), \ | |
342 | "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \ | |
343 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
344 | "a" (_rax), "d" (_rdx)); \ | |
345 | } while (0) | |
346 | ||
3f9f53b0 MG |
347 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
348 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
349 | do { \ | |
350 | switch((_src).bytes) { \ | |
351 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
352 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
353 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
354 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
355 | } \ | |
356 | } while (0) | |
357 | ||
f6b3597b AK |
358 | #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \ |
359 | do { \ | |
360 | switch((_src).bytes) { \ | |
361 | case 1: \ | |
362 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
363 | _eflags, "b", _ex); \ | |
364 | break; \ | |
365 | case 2: \ | |
366 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
367 | _eflags, "w", _ex); \ | |
368 | break; \ | |
369 | case 4: \ | |
370 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
371 | _eflags, "l", _ex); \ | |
372 | break; \ | |
373 | case 8: ON64( \ | |
374 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
375 | _eflags, "q", _ex)); \ | |
376 | break; \ | |
377 | } \ | |
378 | } while (0) | |
379 | ||
6aa8b732 AK |
380 | /* Fetch next part of the instruction being emulated. */ |
381 | #define insn_fetch(_type, _size, _eip) \ | |
382 | ({ unsigned long _x; \ | |
62266869 | 383 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 384 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
385 | goto done; \ |
386 | (_eip) += (_size); \ | |
387 | (_type)_x; \ | |
388 | }) | |
389 | ||
414e6277 GN |
390 | #define insn_fetch_arr(_arr, _size, _eip) \ |
391 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
392 | if (rc != X86EMUL_CONTINUE) \ | |
393 | goto done; \ | |
394 | (_eip) += (_size); \ | |
395 | }) | |
396 | ||
ddcb2885 HH |
397 | static inline unsigned long ad_mask(struct decode_cache *c) |
398 | { | |
399 | return (1UL << (c->ad_bytes << 3)) - 1; | |
400 | } | |
401 | ||
6aa8b732 | 402 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
403 | static inline unsigned long |
404 | address_mask(struct decode_cache *c, unsigned long reg) | |
405 | { | |
406 | if (c->ad_bytes == sizeof(unsigned long)) | |
407 | return reg; | |
408 | else | |
409 | return reg & ad_mask(c); | |
410 | } | |
411 | ||
412 | static inline unsigned long | |
90de84f5 | 413 | register_address(struct decode_cache *c, unsigned long reg) |
e4706772 | 414 | { |
90de84f5 | 415 | return address_mask(c, reg); |
e4706772 HH |
416 | } |
417 | ||
7a957275 HH |
418 | static inline void |
419 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
420 | { | |
421 | if (c->ad_bytes == sizeof(unsigned long)) | |
422 | *reg += inc; | |
423 | else | |
424 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
425 | } | |
6aa8b732 | 426 | |
7a957275 HH |
427 | static inline void jmp_rel(struct decode_cache *c, int rel) |
428 | { | |
429 | register_address_increment(c, &c->eip, rel); | |
430 | } | |
098c937b | 431 | |
7a5b56df AK |
432 | static void set_seg_override(struct decode_cache *c, int seg) |
433 | { | |
434 | c->has_seg_override = true; | |
435 | c->seg_override = seg; | |
436 | } | |
437 | ||
79168fd1 GN |
438 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
439 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
440 | { |
441 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
442 | return 0; | |
443 | ||
79168fd1 | 444 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
445 | } |
446 | ||
90de84f5 AK |
447 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt, |
448 | struct x86_emulate_ops *ops, | |
449 | struct decode_cache *c) | |
7a5b56df AK |
450 | { |
451 | if (!c->has_seg_override) | |
452 | return 0; | |
453 | ||
90de84f5 | 454 | return c->seg_override; |
7a5b56df AK |
455 | } |
456 | ||
90de84f5 AK |
457 | static ulong linear(struct x86_emulate_ctxt *ctxt, |
458 | struct segmented_address addr) | |
7a5b56df | 459 | { |
90de84f5 AK |
460 | struct decode_cache *c = &ctxt->decode; |
461 | ulong la; | |
7a5b56df | 462 | |
90de84f5 AK |
463 | la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea; |
464 | if (c->ad_bytes != 8) | |
465 | la &= (u32)-1; | |
466 | return la; | |
7a5b56df AK |
467 | } |
468 | ||
54b8486f GN |
469 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
470 | u32 error, bool valid) | |
471 | { | |
da9cb575 AK |
472 | ctxt->exception.vector = vec; |
473 | ctxt->exception.error_code = error; | |
474 | ctxt->exception.error_code_valid = valid; | |
54b8486f GN |
475 | } |
476 | ||
477 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
478 | { | |
479 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
480 | } | |
481 | ||
8df25a32 | 482 | static void emulate_pf(struct x86_emulate_ctxt *ctxt) |
54b8486f | 483 | { |
8df25a32 | 484 | emulate_exception(ctxt, PF_VECTOR, 0, true); |
54b8486f GN |
485 | } |
486 | ||
487 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
488 | { | |
489 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
490 | } | |
491 | ||
492 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
493 | { | |
494 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
495 | } | |
496 | ||
34d1f490 AK |
497 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
498 | { | |
499 | emulate_exception(ctxt, DE_VECTOR, 0, false); | |
500 | return X86EMUL_PROPAGATE_FAULT; | |
501 | } | |
502 | ||
62266869 AK |
503 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
504 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 505 | unsigned long eip, u8 *dest) |
62266869 AK |
506 | { |
507 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
508 | int rc; | |
2fb53ad8 | 509 | int size, cur_size; |
62266869 | 510 | |
2fb53ad8 AK |
511 | if (eip == fc->end) { |
512 | cur_size = fc->end - fc->start; | |
513 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
514 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
bcc55cba | 515 | size, ctxt->vcpu, &ctxt->exception); |
3e2815e9 | 516 | if (rc != X86EMUL_CONTINUE) |
62266869 | 517 | return rc; |
2fb53ad8 | 518 | fc->end += size; |
62266869 | 519 | } |
2fb53ad8 | 520 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 521 | return X86EMUL_CONTINUE; |
62266869 AK |
522 | } |
523 | ||
524 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
525 | struct x86_emulate_ops *ops, | |
526 | unsigned long eip, void *dest, unsigned size) | |
527 | { | |
3e2815e9 | 528 | int rc; |
62266869 | 529 | |
eb3c79e6 | 530 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 531 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 532 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
533 | while (size--) { |
534 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 535 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
536 | return rc; |
537 | } | |
3e2815e9 | 538 | return X86EMUL_CONTINUE; |
62266869 AK |
539 | } |
540 | ||
1e3c5cb0 RR |
541 | /* |
542 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
543 | * pointer into the block that addresses the relevant register. | |
544 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
545 | */ | |
546 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
547 | int highbyte_regs) | |
6aa8b732 AK |
548 | { |
549 | void *p; | |
550 | ||
551 | p = ®s[modrm_reg]; | |
552 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
553 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
554 | return p; | |
555 | } | |
556 | ||
557 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
558 | struct x86_emulate_ops *ops, | |
90de84f5 | 559 | struct segmented_address addr, |
6aa8b732 AK |
560 | u16 *size, unsigned long *address, int op_bytes) |
561 | { | |
562 | int rc; | |
563 | ||
564 | if (op_bytes == 2) | |
565 | op_bytes = 3; | |
566 | *address = 0; | |
90de84f5 | 567 | rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2, |
bcc55cba | 568 | ctxt->vcpu, &ctxt->exception); |
1b30eaa8 | 569 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 570 | return rc; |
30b31ab6 AK |
571 | addr.ea += 2; |
572 | rc = ops->read_std(linear(ctxt, addr), address, op_bytes, | |
bcc55cba | 573 | ctxt->vcpu, &ctxt->exception); |
6aa8b732 AK |
574 | return rc; |
575 | } | |
576 | ||
bbe9abbd NK |
577 | static int test_cc(unsigned int condition, unsigned int flags) |
578 | { | |
579 | int rc = 0; | |
580 | ||
581 | switch ((condition & 15) >> 1) { | |
582 | case 0: /* o */ | |
583 | rc |= (flags & EFLG_OF); | |
584 | break; | |
585 | case 1: /* b/c/nae */ | |
586 | rc |= (flags & EFLG_CF); | |
587 | break; | |
588 | case 2: /* z/e */ | |
589 | rc |= (flags & EFLG_ZF); | |
590 | break; | |
591 | case 3: /* be/na */ | |
592 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
593 | break; | |
594 | case 4: /* s */ | |
595 | rc |= (flags & EFLG_SF); | |
596 | break; | |
597 | case 5: /* p/pe */ | |
598 | rc |= (flags & EFLG_PF); | |
599 | break; | |
600 | case 7: /* le/ng */ | |
601 | rc |= (flags & EFLG_ZF); | |
602 | /* fall through */ | |
603 | case 6: /* l/nge */ | |
604 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
605 | break; | |
606 | } | |
607 | ||
608 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
609 | return (!!rc ^ (condition & 1)); | |
610 | } | |
611 | ||
91ff3cb4 AK |
612 | static void fetch_register_operand(struct operand *op) |
613 | { | |
614 | switch (op->bytes) { | |
615 | case 1: | |
616 | op->val = *(u8 *)op->addr.reg; | |
617 | break; | |
618 | case 2: | |
619 | op->val = *(u16 *)op->addr.reg; | |
620 | break; | |
621 | case 4: | |
622 | op->val = *(u32 *)op->addr.reg; | |
623 | break; | |
624 | case 8: | |
625 | op->val = *(u64 *)op->addr.reg; | |
626 | break; | |
627 | } | |
628 | } | |
629 | ||
3c118e24 AK |
630 | static void decode_register_operand(struct operand *op, |
631 | struct decode_cache *c, | |
3c118e24 AK |
632 | int inhibit_bytereg) |
633 | { | |
33615aa9 | 634 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 635 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
636 | |
637 | if (!(c->d & ModRM)) | |
638 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
639 | op->type = OP_REG; |
640 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 641 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
642 | op->bytes = 1; |
643 | } else { | |
1a6440ae | 644 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 645 | op->bytes = c->op_bytes; |
3c118e24 | 646 | } |
91ff3cb4 | 647 | fetch_register_operand(op); |
3c118e24 AK |
648 | op->orig_val = op->val; |
649 | } | |
650 | ||
1c73ef66 | 651 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
652 | struct x86_emulate_ops *ops, |
653 | struct operand *op) | |
1c73ef66 AK |
654 | { |
655 | struct decode_cache *c = &ctxt->decode; | |
656 | u8 sib; | |
f5b4edcd | 657 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 658 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 659 | ulong modrm_ea = 0; |
1c73ef66 AK |
660 | |
661 | if (c->rex_prefix) { | |
662 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
663 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
664 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
665 | } | |
666 | ||
667 | c->modrm = insn_fetch(u8, 1, c->eip); | |
668 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
669 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
670 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 671 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
672 | |
673 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
674 | op->type = OP_REG; |
675 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
676 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 677 | c->regs, c->d & ByteOp); |
2dbd0dd7 | 678 | fetch_register_operand(op); |
1c73ef66 AK |
679 | return rc; |
680 | } | |
681 | ||
2dbd0dd7 AK |
682 | op->type = OP_MEM; |
683 | ||
1c73ef66 AK |
684 | if (c->ad_bytes == 2) { |
685 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
686 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
687 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
688 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
689 | ||
690 | /* 16-bit ModR/M decode. */ | |
691 | switch (c->modrm_mod) { | |
692 | case 0: | |
693 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 694 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
695 | break; |
696 | case 1: | |
2dbd0dd7 | 697 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
698 | break; |
699 | case 2: | |
2dbd0dd7 | 700 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
701 | break; |
702 | } | |
703 | switch (c->modrm_rm) { | |
704 | case 0: | |
2dbd0dd7 | 705 | modrm_ea += bx + si; |
1c73ef66 AK |
706 | break; |
707 | case 1: | |
2dbd0dd7 | 708 | modrm_ea += bx + di; |
1c73ef66 AK |
709 | break; |
710 | case 2: | |
2dbd0dd7 | 711 | modrm_ea += bp + si; |
1c73ef66 AK |
712 | break; |
713 | case 3: | |
2dbd0dd7 | 714 | modrm_ea += bp + di; |
1c73ef66 AK |
715 | break; |
716 | case 4: | |
2dbd0dd7 | 717 | modrm_ea += si; |
1c73ef66 AK |
718 | break; |
719 | case 5: | |
2dbd0dd7 | 720 | modrm_ea += di; |
1c73ef66 AK |
721 | break; |
722 | case 6: | |
723 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 724 | modrm_ea += bp; |
1c73ef66 AK |
725 | break; |
726 | case 7: | |
2dbd0dd7 | 727 | modrm_ea += bx; |
1c73ef66 AK |
728 | break; |
729 | } | |
730 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
731 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 732 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 733 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
734 | } else { |
735 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 736 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
737 | sib = insn_fetch(u8, 1, c->eip); |
738 | index_reg |= (sib >> 3) & 7; | |
739 | base_reg |= sib & 7; | |
740 | scale = sib >> 6; | |
741 | ||
dc71d0f1 | 742 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 743 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 744 | else |
2dbd0dd7 | 745 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 746 | if (index_reg != 4) |
2dbd0dd7 | 747 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
748 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
749 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 750 | c->rip_relative = 1; |
84411d85 | 751 | } else |
2dbd0dd7 | 752 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
753 | switch (c->modrm_mod) { |
754 | case 0: | |
755 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 756 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
757 | break; |
758 | case 1: | |
2dbd0dd7 | 759 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
760 | break; |
761 | case 2: | |
2dbd0dd7 | 762 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
763 | break; |
764 | } | |
765 | } | |
90de84f5 | 766 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
767 | done: |
768 | return rc; | |
769 | } | |
770 | ||
771 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
772 | struct x86_emulate_ops *ops, |
773 | struct operand *op) | |
1c73ef66 AK |
774 | { |
775 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 776 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 777 | |
2dbd0dd7 | 778 | op->type = OP_MEM; |
1c73ef66 AK |
779 | switch (c->ad_bytes) { |
780 | case 2: | |
90de84f5 | 781 | op->addr.mem.ea = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
782 | break; |
783 | case 4: | |
90de84f5 | 784 | op->addr.mem.ea = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
785 | break; |
786 | case 8: | |
90de84f5 | 787 | op->addr.mem.ea = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
788 | break; |
789 | } | |
790 | done: | |
791 | return rc; | |
792 | } | |
793 | ||
35c843c4 WY |
794 | static void fetch_bit_operand(struct decode_cache *c) |
795 | { | |
7129eeca | 796 | long sv = 0, mask; |
35c843c4 | 797 | |
3885f18f | 798 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
799 | mask = ~(c->dst.bytes * 8 - 1); |
800 | ||
801 | if (c->src.bytes == 2) | |
802 | sv = (s16)c->src.val & (s16)mask; | |
803 | else if (c->src.bytes == 4) | |
804 | sv = (s32)c->src.val & (s32)mask; | |
805 | ||
90de84f5 | 806 | c->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 807 | } |
ba7ff2b7 WY |
808 | |
809 | /* only subword offset */ | |
810 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
811 | } |
812 | ||
dde7e6d1 AK |
813 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
814 | struct x86_emulate_ops *ops, | |
815 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 816 | { |
dde7e6d1 AK |
817 | int rc; |
818 | struct read_cache *mc = &ctxt->decode.mem_read; | |
6aa8b732 | 819 | |
dde7e6d1 AK |
820 | while (size) { |
821 | int n = min(size, 8u); | |
822 | size -= n; | |
823 | if (mc->pos < mc->end) | |
824 | goto read_cached; | |
5cd21917 | 825 | |
bcc55cba AK |
826 | rc = ops->read_emulated(addr, mc->data + mc->end, n, |
827 | &ctxt->exception, ctxt->vcpu); | |
dde7e6d1 AK |
828 | if (rc != X86EMUL_CONTINUE) |
829 | return rc; | |
830 | mc->end += n; | |
6aa8b732 | 831 | |
dde7e6d1 AK |
832 | read_cached: |
833 | memcpy(dest, mc->data + mc->pos, n); | |
834 | mc->pos += n; | |
835 | dest += n; | |
836 | addr += n; | |
6aa8b732 | 837 | } |
dde7e6d1 AK |
838 | return X86EMUL_CONTINUE; |
839 | } | |
6aa8b732 | 840 | |
dde7e6d1 AK |
841 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
842 | struct x86_emulate_ops *ops, | |
843 | unsigned int size, unsigned short port, | |
844 | void *dest) | |
845 | { | |
846 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 847 | |
dde7e6d1 AK |
848 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
849 | struct decode_cache *c = &ctxt->decode; | |
850 | unsigned int in_page, n; | |
851 | unsigned int count = c->rep_prefix ? | |
852 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
853 | in_page = (ctxt->eflags & EFLG_DF) ? | |
854 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
855 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
856 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
857 | count); | |
858 | if (n == 0) | |
859 | n = 1; | |
860 | rc->pos = rc->end = 0; | |
861 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
862 | return 0; | |
863 | rc->end = n * size; | |
6aa8b732 AK |
864 | } |
865 | ||
dde7e6d1 AK |
866 | memcpy(dest, rc->data + rc->pos, size); |
867 | rc->pos += size; | |
868 | return 1; | |
869 | } | |
6aa8b732 | 870 | |
dde7e6d1 AK |
871 | static u32 desc_limit_scaled(struct desc_struct *desc) |
872 | { | |
873 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 874 | |
dde7e6d1 AK |
875 | return desc->g ? (limit << 12) | 0xfff : limit; |
876 | } | |
6aa8b732 | 877 | |
dde7e6d1 AK |
878 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
879 | struct x86_emulate_ops *ops, | |
880 | u16 selector, struct desc_ptr *dt) | |
881 | { | |
882 | if (selector & 1 << 2) { | |
883 | struct desc_struct desc; | |
884 | memset (dt, 0, sizeof *dt); | |
885 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
886 | return; | |
e09d082c | 887 | |
dde7e6d1 AK |
888 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
889 | dt->address = get_desc_base(&desc); | |
890 | } else | |
891 | ops->get_gdt(dt, ctxt->vcpu); | |
892 | } | |
120df890 | 893 | |
dde7e6d1 AK |
894 | /* allowed just for 8 bytes segments */ |
895 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
896 | struct x86_emulate_ops *ops, | |
897 | u16 selector, struct desc_struct *desc) | |
898 | { | |
899 | struct desc_ptr dt; | |
900 | u16 index = selector >> 3; | |
901 | int ret; | |
dde7e6d1 | 902 | ulong addr; |
120df890 | 903 | |
dde7e6d1 | 904 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 905 | |
dde7e6d1 AK |
906 | if (dt.size < index * 8 + 7) { |
907 | emulate_gp(ctxt, selector & 0xfffc); | |
908 | return X86EMUL_PROPAGATE_FAULT; | |
e09d082c | 909 | } |
dde7e6d1 | 910 | addr = dt.address + index * 8; |
bcc55cba AK |
911 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, |
912 | &ctxt->exception); | |
e09d082c | 913 | |
dde7e6d1 AK |
914 | return ret; |
915 | } | |
ef65c889 | 916 | |
dde7e6d1 AK |
917 | /* allowed just for 8 bytes segments */ |
918 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
919 | struct x86_emulate_ops *ops, | |
920 | u16 selector, struct desc_struct *desc) | |
921 | { | |
922 | struct desc_ptr dt; | |
923 | u16 index = selector >> 3; | |
dde7e6d1 AK |
924 | ulong addr; |
925 | int ret; | |
6aa8b732 | 926 | |
dde7e6d1 | 927 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 928 | |
dde7e6d1 AK |
929 | if (dt.size < index * 8 + 7) { |
930 | emulate_gp(ctxt, selector & 0xfffc); | |
931 | return X86EMUL_PROPAGATE_FAULT; | |
932 | } | |
6aa8b732 | 933 | |
dde7e6d1 | 934 | addr = dt.address + index * 8; |
bcc55cba AK |
935 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, |
936 | &ctxt->exception); | |
c7e75a3d | 937 | |
dde7e6d1 AK |
938 | return ret; |
939 | } | |
c7e75a3d | 940 | |
dde7e6d1 AK |
941 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
942 | struct x86_emulate_ops *ops, | |
943 | u16 selector, int seg) | |
944 | { | |
945 | struct desc_struct seg_desc; | |
946 | u8 dpl, rpl, cpl; | |
947 | unsigned err_vec = GP_VECTOR; | |
948 | u32 err_code = 0; | |
949 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
950 | int ret; | |
69f55cb1 | 951 | |
dde7e6d1 | 952 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 953 | |
dde7e6d1 AK |
954 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
955 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
956 | /* set real mode segment descriptor */ | |
957 | set_desc_base(&seg_desc, selector << 4); | |
958 | set_desc_limit(&seg_desc, 0xffff); | |
959 | seg_desc.type = 3; | |
960 | seg_desc.p = 1; | |
961 | seg_desc.s = 1; | |
962 | goto load; | |
963 | } | |
964 | ||
965 | /* NULL selector is not valid for TR, CS and SS */ | |
966 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
967 | && null_selector) | |
968 | goto exception; | |
969 | ||
970 | /* TR should be in GDT only */ | |
971 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
972 | goto exception; | |
973 | ||
974 | if (null_selector) /* for NULL selector skip all following checks */ | |
975 | goto load; | |
976 | ||
977 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
978 | if (ret != X86EMUL_CONTINUE) | |
979 | return ret; | |
980 | ||
981 | err_code = selector & 0xfffc; | |
982 | err_vec = GP_VECTOR; | |
983 | ||
984 | /* can't load system descriptor into segment selecor */ | |
985 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
986 | goto exception; | |
987 | ||
988 | if (!seg_desc.p) { | |
989 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
990 | goto exception; | |
991 | } | |
992 | ||
993 | rpl = selector & 3; | |
994 | dpl = seg_desc.dpl; | |
995 | cpl = ops->cpl(ctxt->vcpu); | |
996 | ||
997 | switch (seg) { | |
998 | case VCPU_SREG_SS: | |
999 | /* | |
1000 | * segment is not a writable data segment or segment | |
1001 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1002 | */ | |
1003 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1004 | goto exception; | |
6aa8b732 | 1005 | break; |
dde7e6d1 AK |
1006 | case VCPU_SREG_CS: |
1007 | if (!(seg_desc.type & 8)) | |
1008 | goto exception; | |
1009 | ||
1010 | if (seg_desc.type & 4) { | |
1011 | /* conforming */ | |
1012 | if (dpl > cpl) | |
1013 | goto exception; | |
1014 | } else { | |
1015 | /* nonconforming */ | |
1016 | if (rpl > cpl || dpl != cpl) | |
1017 | goto exception; | |
1018 | } | |
1019 | /* CS(RPL) <- CPL */ | |
1020 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1021 | break; |
dde7e6d1 AK |
1022 | case VCPU_SREG_TR: |
1023 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1024 | goto exception; | |
1025 | break; | |
1026 | case VCPU_SREG_LDTR: | |
1027 | if (seg_desc.s || seg_desc.type != 2) | |
1028 | goto exception; | |
1029 | break; | |
1030 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1031 | /* |
dde7e6d1 AK |
1032 | * segment is not a data or readable code segment or |
1033 | * ((segment is a data or nonconforming code segment) | |
1034 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1035 | */ |
dde7e6d1 AK |
1036 | if ((seg_desc.type & 0xa) == 0x8 || |
1037 | (((seg_desc.type & 0xc) != 0xc) && | |
1038 | (rpl > dpl && cpl > dpl))) | |
1039 | goto exception; | |
6aa8b732 | 1040 | break; |
dde7e6d1 AK |
1041 | } |
1042 | ||
1043 | if (seg_desc.s) { | |
1044 | /* mark segment as accessed */ | |
1045 | seg_desc.type |= 1; | |
1046 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1047 | if (ret != X86EMUL_CONTINUE) | |
1048 | return ret; | |
1049 | } | |
1050 | load: | |
1051 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1052 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1053 | return X86EMUL_CONTINUE; | |
1054 | exception: | |
1055 | emulate_exception(ctxt, err_vec, err_code, true); | |
1056 | return X86EMUL_PROPAGATE_FAULT; | |
1057 | } | |
1058 | ||
31be40b3 WY |
1059 | static void write_register_operand(struct operand *op) |
1060 | { | |
1061 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1062 | switch (op->bytes) { | |
1063 | case 1: | |
1064 | *(u8 *)op->addr.reg = (u8)op->val; | |
1065 | break; | |
1066 | case 2: | |
1067 | *(u16 *)op->addr.reg = (u16)op->val; | |
1068 | break; | |
1069 | case 4: | |
1070 | *op->addr.reg = (u32)op->val; | |
1071 | break; /* 64b: zero-extend */ | |
1072 | case 8: | |
1073 | *op->addr.reg = op->val; | |
1074 | break; | |
1075 | } | |
1076 | } | |
1077 | ||
dde7e6d1 AK |
1078 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1079 | struct x86_emulate_ops *ops) | |
1080 | { | |
1081 | int rc; | |
1082 | struct decode_cache *c = &ctxt->decode; | |
dde7e6d1 AK |
1083 | |
1084 | switch (c->dst.type) { | |
1085 | case OP_REG: | |
31be40b3 | 1086 | write_register_operand(&c->dst); |
6aa8b732 | 1087 | break; |
dde7e6d1 AK |
1088 | case OP_MEM: |
1089 | if (c->lock_prefix) | |
1090 | rc = ops->cmpxchg_emulated( | |
90de84f5 | 1091 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1092 | &c->dst.orig_val, |
1093 | &c->dst.val, | |
1094 | c->dst.bytes, | |
bcc55cba | 1095 | &ctxt->exception, |
dde7e6d1 | 1096 | ctxt->vcpu); |
341de7e3 | 1097 | else |
dde7e6d1 | 1098 | rc = ops->write_emulated( |
90de84f5 | 1099 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1100 | &c->dst.val, |
1101 | c->dst.bytes, | |
bcc55cba | 1102 | &ctxt->exception, |
dde7e6d1 | 1103 | ctxt->vcpu); |
dde7e6d1 AK |
1104 | if (rc != X86EMUL_CONTINUE) |
1105 | return rc; | |
a682e354 | 1106 | break; |
dde7e6d1 AK |
1107 | case OP_NONE: |
1108 | /* no writeback */ | |
414e6277 | 1109 | break; |
dde7e6d1 | 1110 | default: |
414e6277 | 1111 | break; |
6aa8b732 | 1112 | } |
dde7e6d1 AK |
1113 | return X86EMUL_CONTINUE; |
1114 | } | |
6aa8b732 | 1115 | |
dde7e6d1 AK |
1116 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1117 | struct x86_emulate_ops *ops) | |
1118 | { | |
1119 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1120 | |
dde7e6d1 AK |
1121 | c->dst.type = OP_MEM; |
1122 | c->dst.bytes = c->op_bytes; | |
1123 | c->dst.val = c->src.val; | |
1124 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
90de84f5 AK |
1125 | c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1126 | c->dst.addr.mem.seg = VCPU_SREG_SS; | |
dde7e6d1 | 1127 | } |
69f55cb1 | 1128 | |
dde7e6d1 AK |
1129 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1130 | struct x86_emulate_ops *ops, | |
1131 | void *dest, int len) | |
1132 | { | |
1133 | struct decode_cache *c = &ctxt->decode; | |
1134 | int rc; | |
90de84f5 | 1135 | struct segmented_address addr; |
8b4caf66 | 1136 | |
90de84f5 AK |
1137 | addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1138 | addr.seg = VCPU_SREG_SS; | |
1139 | rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len); | |
dde7e6d1 AK |
1140 | if (rc != X86EMUL_CONTINUE) |
1141 | return rc; | |
1142 | ||
1143 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1144 | return rc; | |
8b4caf66 LV |
1145 | } |
1146 | ||
dde7e6d1 AK |
1147 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1148 | struct x86_emulate_ops *ops, | |
1149 | void *dest, int len) | |
9de41573 GN |
1150 | { |
1151 | int rc; | |
dde7e6d1 AK |
1152 | unsigned long val, change_mask; |
1153 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1154 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1155 | |
dde7e6d1 AK |
1156 | rc = emulate_pop(ctxt, ops, &val, len); |
1157 | if (rc != X86EMUL_CONTINUE) | |
1158 | return rc; | |
9de41573 | 1159 | |
dde7e6d1 AK |
1160 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1161 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1162 | |
dde7e6d1 AK |
1163 | switch(ctxt->mode) { |
1164 | case X86EMUL_MODE_PROT64: | |
1165 | case X86EMUL_MODE_PROT32: | |
1166 | case X86EMUL_MODE_PROT16: | |
1167 | if (cpl == 0) | |
1168 | change_mask |= EFLG_IOPL; | |
1169 | if (cpl <= iopl) | |
1170 | change_mask |= EFLG_IF; | |
1171 | break; | |
1172 | case X86EMUL_MODE_VM86: | |
1173 | if (iopl < 3) { | |
1174 | emulate_gp(ctxt, 0); | |
1175 | return X86EMUL_PROPAGATE_FAULT; | |
1176 | } | |
1177 | change_mask |= EFLG_IF; | |
1178 | break; | |
1179 | default: /* real mode */ | |
1180 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1181 | break; | |
9de41573 | 1182 | } |
dde7e6d1 AK |
1183 | |
1184 | *(unsigned long *)dest = | |
1185 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1186 | ||
d47f00a6 JR |
1187 | if (rc == X86EMUL_PROPAGATE_FAULT) |
1188 | emulate_pf(ctxt); | |
1189 | ||
dde7e6d1 | 1190 | return rc; |
9de41573 GN |
1191 | } |
1192 | ||
dde7e6d1 AK |
1193 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1194 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1195 | { |
dde7e6d1 | 1196 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1197 | |
dde7e6d1 | 1198 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1199 | |
dde7e6d1 | 1200 | emulate_push(ctxt, ops); |
7b262e90 GN |
1201 | } |
1202 | ||
dde7e6d1 AK |
1203 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1204 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1205 | { |
dde7e6d1 AK |
1206 | struct decode_cache *c = &ctxt->decode; |
1207 | unsigned long selector; | |
1208 | int rc; | |
38ba30ba | 1209 | |
dde7e6d1 AK |
1210 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1211 | if (rc != X86EMUL_CONTINUE) | |
1212 | return rc; | |
1213 | ||
1214 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1215 | return rc; | |
38ba30ba GN |
1216 | } |
1217 | ||
dde7e6d1 AK |
1218 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1219 | struct x86_emulate_ops *ops) | |
38ba30ba | 1220 | { |
dde7e6d1 AK |
1221 | struct decode_cache *c = &ctxt->decode; |
1222 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1223 | int rc = X86EMUL_CONTINUE; | |
1224 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1225 | |
dde7e6d1 AK |
1226 | while (reg <= VCPU_REGS_RDI) { |
1227 | (reg == VCPU_REGS_RSP) ? | |
1228 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1229 | |
dde7e6d1 | 1230 | emulate_push(ctxt, ops); |
38ba30ba | 1231 | |
dde7e6d1 AK |
1232 | rc = writeback(ctxt, ops); |
1233 | if (rc != X86EMUL_CONTINUE) | |
1234 | return rc; | |
38ba30ba | 1235 | |
dde7e6d1 | 1236 | ++reg; |
38ba30ba | 1237 | } |
38ba30ba | 1238 | |
dde7e6d1 AK |
1239 | /* Disable writeback. */ |
1240 | c->dst.type = OP_NONE; | |
1241 | ||
1242 | return rc; | |
38ba30ba GN |
1243 | } |
1244 | ||
dde7e6d1 AK |
1245 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1246 | struct x86_emulate_ops *ops) | |
38ba30ba | 1247 | { |
dde7e6d1 AK |
1248 | struct decode_cache *c = &ctxt->decode; |
1249 | int rc = X86EMUL_CONTINUE; | |
1250 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1251 | |
dde7e6d1 AK |
1252 | while (reg >= VCPU_REGS_RAX) { |
1253 | if (reg == VCPU_REGS_RSP) { | |
1254 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1255 | c->op_bytes); | |
1256 | --reg; | |
1257 | } | |
38ba30ba | 1258 | |
dde7e6d1 AK |
1259 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1260 | if (rc != X86EMUL_CONTINUE) | |
1261 | break; | |
1262 | --reg; | |
38ba30ba | 1263 | } |
dde7e6d1 | 1264 | return rc; |
38ba30ba GN |
1265 | } |
1266 | ||
6e154e56 MG |
1267 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1268 | struct x86_emulate_ops *ops, int irq) | |
1269 | { | |
1270 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1271 | int rc; |
6e154e56 MG |
1272 | struct desc_ptr dt; |
1273 | gva_t cs_addr; | |
1274 | gva_t eip_addr; | |
1275 | u16 cs, eip; | |
6e154e56 MG |
1276 | |
1277 | /* TODO: Add limit checks */ | |
1278 | c->src.val = ctxt->eflags; | |
1279 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1280 | rc = writeback(ctxt, ops); |
1281 | if (rc != X86EMUL_CONTINUE) | |
1282 | return rc; | |
6e154e56 MG |
1283 | |
1284 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1285 | ||
1286 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1287 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1288 | rc = writeback(ctxt, ops); |
1289 | if (rc != X86EMUL_CONTINUE) | |
1290 | return rc; | |
6e154e56 MG |
1291 | |
1292 | c->src.val = c->eip; | |
1293 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1294 | rc = writeback(ctxt, ops); |
1295 | if (rc != X86EMUL_CONTINUE) | |
1296 | return rc; | |
1297 | ||
1298 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1299 | |
1300 | ops->get_idt(&dt, ctxt->vcpu); | |
1301 | ||
1302 | eip_addr = dt.address + (irq << 2); | |
1303 | cs_addr = dt.address + (irq << 2) + 2; | |
1304 | ||
bcc55cba | 1305 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1306 | if (rc != X86EMUL_CONTINUE) |
1307 | return rc; | |
1308 | ||
bcc55cba | 1309 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1310 | if (rc != X86EMUL_CONTINUE) |
1311 | return rc; | |
1312 | ||
1313 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1314 | if (rc != X86EMUL_CONTINUE) | |
1315 | return rc; | |
1316 | ||
1317 | c->eip = eip; | |
1318 | ||
1319 | return rc; | |
1320 | } | |
1321 | ||
1322 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1323 | struct x86_emulate_ops *ops, int irq) | |
1324 | { | |
1325 | switch(ctxt->mode) { | |
1326 | case X86EMUL_MODE_REAL: | |
1327 | return emulate_int_real(ctxt, ops, irq); | |
1328 | case X86EMUL_MODE_VM86: | |
1329 | case X86EMUL_MODE_PROT16: | |
1330 | case X86EMUL_MODE_PROT32: | |
1331 | case X86EMUL_MODE_PROT64: | |
1332 | default: | |
1333 | /* Protected mode interrupts unimplemented yet */ | |
1334 | return X86EMUL_UNHANDLEABLE; | |
1335 | } | |
1336 | } | |
1337 | ||
dde7e6d1 AK |
1338 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1339 | struct x86_emulate_ops *ops) | |
38ba30ba | 1340 | { |
dde7e6d1 AK |
1341 | struct decode_cache *c = &ctxt->decode; |
1342 | int rc = X86EMUL_CONTINUE; | |
1343 | unsigned long temp_eip = 0; | |
1344 | unsigned long temp_eflags = 0; | |
1345 | unsigned long cs = 0; | |
1346 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1347 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1348 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1349 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1350 | |
dde7e6d1 | 1351 | /* TODO: Add stack limit check */ |
38ba30ba | 1352 | |
dde7e6d1 | 1353 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1354 | |
dde7e6d1 AK |
1355 | if (rc != X86EMUL_CONTINUE) |
1356 | return rc; | |
38ba30ba | 1357 | |
dde7e6d1 AK |
1358 | if (temp_eip & ~0xffff) { |
1359 | emulate_gp(ctxt, 0); | |
1360 | return X86EMUL_PROPAGATE_FAULT; | |
1361 | } | |
38ba30ba | 1362 | |
dde7e6d1 | 1363 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1364 | |
dde7e6d1 AK |
1365 | if (rc != X86EMUL_CONTINUE) |
1366 | return rc; | |
38ba30ba | 1367 | |
dde7e6d1 | 1368 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1369 | |
dde7e6d1 AK |
1370 | if (rc != X86EMUL_CONTINUE) |
1371 | return rc; | |
38ba30ba | 1372 | |
dde7e6d1 | 1373 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1374 | |
dde7e6d1 AK |
1375 | if (rc != X86EMUL_CONTINUE) |
1376 | return rc; | |
38ba30ba | 1377 | |
dde7e6d1 | 1378 | c->eip = temp_eip; |
38ba30ba | 1379 | |
38ba30ba | 1380 | |
dde7e6d1 AK |
1381 | if (c->op_bytes == 4) |
1382 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1383 | else if (c->op_bytes == 2) { | |
1384 | ctxt->eflags &= ~0xffff; | |
1385 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1386 | } |
dde7e6d1 AK |
1387 | |
1388 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1389 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1390 | ||
1391 | return rc; | |
38ba30ba GN |
1392 | } |
1393 | ||
dde7e6d1 AK |
1394 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1395 | struct x86_emulate_ops* ops) | |
c37eda13 | 1396 | { |
dde7e6d1 AK |
1397 | switch(ctxt->mode) { |
1398 | case X86EMUL_MODE_REAL: | |
1399 | return emulate_iret_real(ctxt, ops); | |
1400 | case X86EMUL_MODE_VM86: | |
1401 | case X86EMUL_MODE_PROT16: | |
1402 | case X86EMUL_MODE_PROT32: | |
1403 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1404 | default: |
dde7e6d1 AK |
1405 | /* iret from protected mode unimplemented yet */ |
1406 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1407 | } |
c37eda13 WY |
1408 | } |
1409 | ||
dde7e6d1 | 1410 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1411 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1412 | { |
1413 | struct decode_cache *c = &ctxt->decode; | |
1414 | ||
dde7e6d1 | 1415 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1416 | } |
1417 | ||
dde7e6d1 | 1418 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1419 | { |
05f086f8 | 1420 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1421 | switch (c->modrm_reg) { |
1422 | case 0: /* rol */ | |
05f086f8 | 1423 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1424 | break; |
1425 | case 1: /* ror */ | |
05f086f8 | 1426 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1427 | break; |
1428 | case 2: /* rcl */ | |
05f086f8 | 1429 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1430 | break; |
1431 | case 3: /* rcr */ | |
05f086f8 | 1432 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1433 | break; |
1434 | case 4: /* sal/shl */ | |
1435 | case 6: /* sal/shl */ | |
05f086f8 | 1436 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1437 | break; |
1438 | case 5: /* shr */ | |
05f086f8 | 1439 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1440 | break; |
1441 | case 7: /* sar */ | |
05f086f8 | 1442 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1443 | break; |
1444 | } | |
1445 | } | |
1446 | ||
1447 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1448 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1449 | { |
1450 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1451 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1452 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
34d1f490 | 1453 | u8 de = 0; |
8cdbd2c9 LV |
1454 | |
1455 | switch (c->modrm_reg) { | |
1456 | case 0 ... 1: /* test */ | |
05f086f8 | 1457 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1458 | break; |
1459 | case 2: /* not */ | |
1460 | c->dst.val = ~c->dst.val; | |
1461 | break; | |
1462 | case 3: /* neg */ | |
05f086f8 | 1463 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1464 | break; |
3f9f53b0 MG |
1465 | case 4: /* mul */ |
1466 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1467 | break; | |
1468 | case 5: /* imul */ | |
1469 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1470 | break; | |
1471 | case 6: /* div */ | |
34d1f490 AK |
1472 | emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx, |
1473 | ctxt->eflags, de); | |
3f9f53b0 MG |
1474 | break; |
1475 | case 7: /* idiv */ | |
34d1f490 AK |
1476 | emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx, |
1477 | ctxt->eflags, de); | |
3f9f53b0 | 1478 | break; |
8cdbd2c9 | 1479 | default: |
8c5eee30 | 1480 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1481 | } |
34d1f490 AK |
1482 | if (de) |
1483 | return emulate_de(ctxt); | |
8c5eee30 | 1484 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1485 | } |
1486 | ||
1487 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1488 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1489 | { |
1490 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1491 | |
1492 | switch (c->modrm_reg) { | |
1493 | case 0: /* inc */ | |
05f086f8 | 1494 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1495 | break; |
1496 | case 1: /* dec */ | |
05f086f8 | 1497 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1498 | break; |
d19292e4 MG |
1499 | case 2: /* call near abs */ { |
1500 | long int old_eip; | |
1501 | old_eip = c->eip; | |
1502 | c->eip = c->src.val; | |
1503 | c->src.val = old_eip; | |
79168fd1 | 1504 | emulate_push(ctxt, ops); |
d19292e4 MG |
1505 | break; |
1506 | } | |
8cdbd2c9 | 1507 | case 4: /* jmp abs */ |
fd60754e | 1508 | c->eip = c->src.val; |
8cdbd2c9 LV |
1509 | break; |
1510 | case 6: /* push */ | |
79168fd1 | 1511 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1512 | break; |
8cdbd2c9 | 1513 | } |
1b30eaa8 | 1514 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1515 | } |
1516 | ||
1517 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1518 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1519 | { |
1520 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1521 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1522 | |
1523 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1524 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1525 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1526 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1527 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1528 | } else { |
16518d5a AK |
1529 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1530 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1531 | |
05f086f8 | 1532 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1533 | } |
1b30eaa8 | 1534 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1535 | } |
1536 | ||
a77ab5ea AK |
1537 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1538 | struct x86_emulate_ops *ops) | |
1539 | { | |
1540 | struct decode_cache *c = &ctxt->decode; | |
1541 | int rc; | |
1542 | unsigned long cs; | |
1543 | ||
1544 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1545 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1546 | return rc; |
1547 | if (c->op_bytes == 4) | |
1548 | c->eip = (u32)c->eip; | |
1549 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1550 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1551 | return rc; |
2e873022 | 1552 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1553 | return rc; |
1554 | } | |
1555 | ||
09b5f4d3 WY |
1556 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, |
1557 | struct x86_emulate_ops *ops, int seg) | |
1558 | { | |
1559 | struct decode_cache *c = &ctxt->decode; | |
1560 | unsigned short sel; | |
1561 | int rc; | |
1562 | ||
1563 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
1564 | ||
1565 | rc = load_segment_descriptor(ctxt, ops, sel, seg); | |
1566 | if (rc != X86EMUL_CONTINUE) | |
1567 | return rc; | |
1568 | ||
1569 | c->dst.val = c->src.val; | |
1570 | return rc; | |
1571 | } | |
1572 | ||
e66bb2cc AP |
1573 | static inline void |
1574 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1575 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1576 | struct desc_struct *ss) | |
e66bb2cc | 1577 | { |
79168fd1 GN |
1578 | memset(cs, 0, sizeof(struct desc_struct)); |
1579 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1580 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1581 | |
1582 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1583 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1584 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1585 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1586 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1587 | cs->s = 1; | |
1588 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1589 | cs->p = 1; |
1590 | cs->d = 1; | |
e66bb2cc | 1591 | |
79168fd1 GN |
1592 | set_desc_base(ss, 0); /* flat segment */ |
1593 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1594 | ss->g = 1; /* 4kb granularity */ |
1595 | ss->s = 1; | |
1596 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1597 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1598 | ss->dpl = 0; |
79168fd1 | 1599 | ss->p = 1; |
e66bb2cc AP |
1600 | } |
1601 | ||
1602 | static int | |
3fb1b5db | 1603 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1604 | { |
1605 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1606 | struct desc_struct cs, ss; |
e66bb2cc | 1607 | u64 msr_data; |
79168fd1 | 1608 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1609 | |
1610 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1611 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1612 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1613 | emulate_ud(ctxt); |
2e901c4c GN |
1614 | return X86EMUL_PROPAGATE_FAULT; |
1615 | } | |
e66bb2cc | 1616 | |
79168fd1 | 1617 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1618 | |
3fb1b5db | 1619 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1620 | msr_data >>= 32; |
79168fd1 GN |
1621 | cs_sel = (u16)(msr_data & 0xfffc); |
1622 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1623 | |
1624 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1625 | cs.d = 0; |
e66bb2cc AP |
1626 | cs.l = 1; |
1627 | } | |
79168fd1 GN |
1628 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1629 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1630 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1631 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1632 | |
1633 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1634 | if (is_long_mode(ctxt->vcpu)) { | |
1635 | #ifdef CONFIG_X86_64 | |
1636 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1637 | ||
3fb1b5db GN |
1638 | ops->get_msr(ctxt->vcpu, |
1639 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1640 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1641 | c->eip = msr_data; |
1642 | ||
3fb1b5db | 1643 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1644 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1645 | #endif | |
1646 | } else { | |
1647 | /* legacy mode */ | |
3fb1b5db | 1648 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1649 | c->eip = (u32)msr_data; |
1650 | ||
1651 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1652 | } | |
1653 | ||
e54cfa97 | 1654 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1655 | } |
1656 | ||
8c604352 | 1657 | static int |
3fb1b5db | 1658 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1659 | { |
1660 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1661 | struct desc_struct cs, ss; |
8c604352 | 1662 | u64 msr_data; |
79168fd1 | 1663 | u16 cs_sel, ss_sel; |
8c604352 | 1664 | |
a0044755 GN |
1665 | /* inject #GP if in real mode */ |
1666 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 1667 | emulate_gp(ctxt, 0); |
2e901c4c | 1668 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1669 | } |
1670 | ||
1671 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1672 | * Therefore, we inject an #UD. | |
1673 | */ | |
2e901c4c | 1674 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 1675 | emulate_ud(ctxt); |
2e901c4c GN |
1676 | return X86EMUL_PROPAGATE_FAULT; |
1677 | } | |
8c604352 | 1678 | |
79168fd1 | 1679 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1680 | |
3fb1b5db | 1681 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1682 | switch (ctxt->mode) { |
1683 | case X86EMUL_MODE_PROT32: | |
1684 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 1685 | emulate_gp(ctxt, 0); |
e54cfa97 | 1686 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1687 | } |
1688 | break; | |
1689 | case X86EMUL_MODE_PROT64: | |
1690 | if (msr_data == 0x0) { | |
54b8486f | 1691 | emulate_gp(ctxt, 0); |
e54cfa97 | 1692 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1693 | } |
1694 | break; | |
1695 | } | |
1696 | ||
1697 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1698 | cs_sel = (u16)msr_data; |
1699 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1700 | ss_sel = cs_sel + 8; | |
1701 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1702 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1703 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1704 | cs.d = 0; |
8c604352 AP |
1705 | cs.l = 1; |
1706 | } | |
1707 | ||
79168fd1 GN |
1708 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1709 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1710 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1711 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 1712 | |
3fb1b5db | 1713 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1714 | c->eip = msr_data; |
1715 | ||
3fb1b5db | 1716 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1717 | c->regs[VCPU_REGS_RSP] = msr_data; |
1718 | ||
e54cfa97 | 1719 | return X86EMUL_CONTINUE; |
8c604352 AP |
1720 | } |
1721 | ||
4668f050 | 1722 | static int |
3fb1b5db | 1723 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1724 | { |
1725 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1726 | struct desc_struct cs, ss; |
4668f050 AP |
1727 | u64 msr_data; |
1728 | int usermode; | |
79168fd1 | 1729 | u16 cs_sel, ss_sel; |
4668f050 | 1730 | |
a0044755 GN |
1731 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1732 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1733 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1734 | emulate_gp(ctxt, 0); |
2e901c4c | 1735 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1736 | } |
1737 | ||
79168fd1 | 1738 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1739 | |
1740 | if ((c->rex_prefix & 0x8) != 0x0) | |
1741 | usermode = X86EMUL_MODE_PROT64; | |
1742 | else | |
1743 | usermode = X86EMUL_MODE_PROT32; | |
1744 | ||
1745 | cs.dpl = 3; | |
1746 | ss.dpl = 3; | |
3fb1b5db | 1747 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1748 | switch (usermode) { |
1749 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1750 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 1751 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 1752 | emulate_gp(ctxt, 0); |
e54cfa97 | 1753 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1754 | } |
79168fd1 | 1755 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1756 | break; |
1757 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1758 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 1759 | if (msr_data == 0x0) { |
54b8486f | 1760 | emulate_gp(ctxt, 0); |
e54cfa97 | 1761 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1762 | } |
79168fd1 GN |
1763 | ss_sel = cs_sel + 8; |
1764 | cs.d = 0; | |
4668f050 AP |
1765 | cs.l = 1; |
1766 | break; | |
1767 | } | |
79168fd1 GN |
1768 | cs_sel |= SELECTOR_RPL_MASK; |
1769 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1770 | |
79168fd1 GN |
1771 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1772 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1773 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1774 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 1775 | |
bdb475a3 GN |
1776 | c->eip = c->regs[VCPU_REGS_RDX]; |
1777 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1778 | |
e54cfa97 | 1779 | return X86EMUL_CONTINUE; |
4668f050 AP |
1780 | } |
1781 | ||
9c537244 GN |
1782 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1783 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1784 | { |
1785 | int iopl; | |
1786 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1787 | return false; | |
1788 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1789 | return true; | |
1790 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1791 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1792 | } |
1793 | ||
1794 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1795 | struct x86_emulate_ops *ops, | |
1796 | u16 port, u16 len) | |
1797 | { | |
79168fd1 | 1798 | struct desc_struct tr_seg; |
f850e2e6 GN |
1799 | int r; |
1800 | u16 io_bitmap_ptr; | |
1801 | u8 perm, bit_idx = port & 0x7; | |
1802 | unsigned mask = (1 << len) - 1; | |
1803 | ||
79168fd1 GN |
1804 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
1805 | if (!tr_seg.p) | |
f850e2e6 | 1806 | return false; |
79168fd1 | 1807 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1808 | return false; |
79168fd1 GN |
1809 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
1810 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
1811 | if (r != X86EMUL_CONTINUE) |
1812 | return false; | |
79168fd1 | 1813 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1814 | return false; |
79168fd1 GN |
1815 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
1816 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1817 | if (r != X86EMUL_CONTINUE) |
1818 | return false; | |
1819 | if ((perm >> bit_idx) & mask) | |
1820 | return false; | |
1821 | return true; | |
1822 | } | |
1823 | ||
1824 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1825 | struct x86_emulate_ops *ops, | |
1826 | u16 port, u16 len) | |
1827 | { | |
4fc40f07 GN |
1828 | if (ctxt->perm_ok) |
1829 | return true; | |
1830 | ||
9c537244 | 1831 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1832 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1833 | return false; | |
4fc40f07 GN |
1834 | |
1835 | ctxt->perm_ok = true; | |
1836 | ||
f850e2e6 GN |
1837 | return true; |
1838 | } | |
1839 | ||
38ba30ba GN |
1840 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1841 | struct x86_emulate_ops *ops, | |
1842 | struct tss_segment_16 *tss) | |
1843 | { | |
1844 | struct decode_cache *c = &ctxt->decode; | |
1845 | ||
1846 | tss->ip = c->eip; | |
1847 | tss->flag = ctxt->eflags; | |
1848 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1849 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1850 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1851 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1852 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1853 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1854 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1855 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1856 | ||
1857 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1858 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1859 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1860 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1861 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1862 | } | |
1863 | ||
1864 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1865 | struct x86_emulate_ops *ops, | |
1866 | struct tss_segment_16 *tss) | |
1867 | { | |
1868 | struct decode_cache *c = &ctxt->decode; | |
1869 | int ret; | |
1870 | ||
1871 | c->eip = tss->ip; | |
1872 | ctxt->eflags = tss->flag | 2; | |
1873 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1874 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1875 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1876 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1877 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1878 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1879 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1880 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1881 | ||
1882 | /* | |
1883 | * SDM says that segment selectors are loaded before segment | |
1884 | * descriptors | |
1885 | */ | |
1886 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1887 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1888 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1889 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1890 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1891 | ||
1892 | /* | |
1893 | * Now load segment descriptors. If fault happenes at this stage | |
1894 | * it is handled in a context of new task | |
1895 | */ | |
1896 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1897 | if (ret != X86EMUL_CONTINUE) | |
1898 | return ret; | |
1899 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1900 | if (ret != X86EMUL_CONTINUE) | |
1901 | return ret; | |
1902 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1903 | if (ret != X86EMUL_CONTINUE) | |
1904 | return ret; | |
1905 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1906 | if (ret != X86EMUL_CONTINUE) | |
1907 | return ret; | |
1908 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1909 | if (ret != X86EMUL_CONTINUE) | |
1910 | return ret; | |
1911 | ||
1912 | return X86EMUL_CONTINUE; | |
1913 | } | |
1914 | ||
1915 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1916 | struct x86_emulate_ops *ops, | |
1917 | u16 tss_selector, u16 old_tss_sel, | |
1918 | ulong old_tss_base, struct desc_struct *new_desc) | |
1919 | { | |
1920 | struct tss_segment_16 tss_seg; | |
1921 | int ret; | |
bcc55cba | 1922 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
1923 | |
1924 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
1925 | &ctxt->exception); |
1926 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 1927 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 1928 | return ret; |
38ba30ba GN |
1929 | |
1930 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1931 | ||
1932 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
1933 | &ctxt->exception); |
1934 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 1935 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 1936 | return ret; |
38ba30ba GN |
1937 | |
1938 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
1939 | &ctxt->exception); |
1940 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 1941 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 1942 | return ret; |
38ba30ba GN |
1943 | |
1944 | if (old_tss_sel != 0xffff) { | |
1945 | tss_seg.prev_task_link = old_tss_sel; | |
1946 | ||
1947 | ret = ops->write_std(new_tss_base, | |
1948 | &tss_seg.prev_task_link, | |
1949 | sizeof tss_seg.prev_task_link, | |
bcc55cba AK |
1950 | ctxt->vcpu, &ctxt->exception); |
1951 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 1952 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 1953 | return ret; |
38ba30ba GN |
1954 | } |
1955 | ||
1956 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
1957 | } | |
1958 | ||
1959 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
1960 | struct x86_emulate_ops *ops, | |
1961 | struct tss_segment_32 *tss) | |
1962 | { | |
1963 | struct decode_cache *c = &ctxt->decode; | |
1964 | ||
1965 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
1966 | tss->eip = c->eip; | |
1967 | tss->eflags = ctxt->eflags; | |
1968 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
1969 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
1970 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
1971 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
1972 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
1973 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
1974 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
1975 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
1976 | ||
1977 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1978 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1979 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1980 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1981 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
1982 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
1983 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1984 | } | |
1985 | ||
1986 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
1987 | struct x86_emulate_ops *ops, | |
1988 | struct tss_segment_32 *tss) | |
1989 | { | |
1990 | struct decode_cache *c = &ctxt->decode; | |
1991 | int ret; | |
1992 | ||
0f12244f | 1993 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 1994 | emulate_gp(ctxt, 0); |
0f12244f GN |
1995 | return X86EMUL_PROPAGATE_FAULT; |
1996 | } | |
38ba30ba GN |
1997 | c->eip = tss->eip; |
1998 | ctxt->eflags = tss->eflags | 2; | |
1999 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2000 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2001 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2002 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2003 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2004 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2005 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2006 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2007 | ||
2008 | /* | |
2009 | * SDM says that segment selectors are loaded before segment | |
2010 | * descriptors | |
2011 | */ | |
2012 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2013 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2014 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2015 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2016 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2017 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2018 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2019 | ||
2020 | /* | |
2021 | * Now load segment descriptors. If fault happenes at this stage | |
2022 | * it is handled in a context of new task | |
2023 | */ | |
2024 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2025 | if (ret != X86EMUL_CONTINUE) | |
2026 | return ret; | |
2027 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2028 | if (ret != X86EMUL_CONTINUE) | |
2029 | return ret; | |
2030 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2031 | if (ret != X86EMUL_CONTINUE) | |
2032 | return ret; | |
2033 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2034 | if (ret != X86EMUL_CONTINUE) | |
2035 | return ret; | |
2036 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2037 | if (ret != X86EMUL_CONTINUE) | |
2038 | return ret; | |
2039 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2040 | if (ret != X86EMUL_CONTINUE) | |
2041 | return ret; | |
2042 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2043 | if (ret != X86EMUL_CONTINUE) | |
2044 | return ret; | |
2045 | ||
2046 | return X86EMUL_CONTINUE; | |
2047 | } | |
2048 | ||
2049 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2050 | struct x86_emulate_ops *ops, | |
2051 | u16 tss_selector, u16 old_tss_sel, | |
2052 | ulong old_tss_base, struct desc_struct *new_desc) | |
2053 | { | |
2054 | struct tss_segment_32 tss_seg; | |
2055 | int ret; | |
bcc55cba | 2056 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2057 | |
2058 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
2059 | &ctxt->exception); |
2060 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 2061 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2062 | return ret; |
38ba30ba GN |
2063 | |
2064 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2065 | ||
2066 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
2067 | &ctxt->exception); |
2068 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 2069 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2070 | return ret; |
38ba30ba GN |
2071 | |
2072 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba AK |
2073 | &ctxt->exception); |
2074 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 2075 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2076 | return ret; |
38ba30ba GN |
2077 | |
2078 | if (old_tss_sel != 0xffff) { | |
2079 | tss_seg.prev_task_link = old_tss_sel; | |
2080 | ||
2081 | ret = ops->write_std(new_tss_base, | |
2082 | &tss_seg.prev_task_link, | |
2083 | sizeof tss_seg.prev_task_link, | |
bcc55cba AK |
2084 | ctxt->vcpu, &ctxt->exception); |
2085 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
38ba30ba | 2086 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2087 | return ret; |
38ba30ba GN |
2088 | } |
2089 | ||
2090 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2091 | } | |
2092 | ||
2093 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2094 | struct x86_emulate_ops *ops, |
2095 | u16 tss_selector, int reason, | |
2096 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2097 | { |
2098 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2099 | int ret; | |
2100 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2101 | ulong old_tss_base = | |
5951c442 | 2102 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2103 | u32 desc_limit; |
38ba30ba GN |
2104 | |
2105 | /* FIXME: old_tss_base == ~0 ? */ | |
2106 | ||
2107 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2108 | if (ret != X86EMUL_CONTINUE) | |
2109 | return ret; | |
2110 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2111 | if (ret != X86EMUL_CONTINUE) | |
2112 | return ret; | |
2113 | ||
2114 | /* FIXME: check that next_tss_desc is tss */ | |
2115 | ||
2116 | if (reason != TASK_SWITCH_IRET) { | |
2117 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2118 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2119 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2120 | return X86EMUL_PROPAGATE_FAULT; |
2121 | } | |
2122 | } | |
2123 | ||
ceffb459 GN |
2124 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2125 | if (!next_tss_desc.p || | |
2126 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2127 | desc_limit < 0x2b)) { | |
54b8486f | 2128 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2129 | return X86EMUL_PROPAGATE_FAULT; |
2130 | } | |
2131 | ||
2132 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2133 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2134 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2135 | &curr_tss_desc); | |
2136 | } | |
2137 | ||
2138 | if (reason == TASK_SWITCH_IRET) | |
2139 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2140 | ||
2141 | /* set back link to prev task only if NT bit is set in eflags | |
2142 | note that old_tss_sel is not used afetr this point */ | |
2143 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2144 | old_tss_sel = 0xffff; | |
2145 | ||
2146 | if (next_tss_desc.type & 8) | |
2147 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2148 | old_tss_base, &next_tss_desc); | |
2149 | else | |
2150 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2151 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2152 | if (ret != X86EMUL_CONTINUE) |
2153 | return ret; | |
38ba30ba GN |
2154 | |
2155 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2156 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2157 | ||
2158 | if (reason != TASK_SWITCH_IRET) { | |
2159 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2160 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2161 | &next_tss_desc); | |
2162 | } | |
2163 | ||
2164 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2165 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2166 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2167 | ||
e269fb21 JK |
2168 | if (has_error_code) { |
2169 | struct decode_cache *c = &ctxt->decode; | |
2170 | ||
2171 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2172 | c->lock_prefix = 0; | |
2173 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2174 | emulate_push(ctxt, ops); |
e269fb21 JK |
2175 | } |
2176 | ||
38ba30ba GN |
2177 | return ret; |
2178 | } | |
2179 | ||
2180 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2181 | u16 tss_selector, int reason, |
2182 | bool has_error_code, u32 error_code) | |
38ba30ba | 2183 | { |
9aabc88f | 2184 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2185 | struct decode_cache *c = &ctxt->decode; |
2186 | int rc; | |
2187 | ||
38ba30ba | 2188 | c->eip = ctxt->eip; |
e269fb21 | 2189 | c->dst.type = OP_NONE; |
38ba30ba | 2190 | |
e269fb21 JK |
2191 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2192 | has_error_code, error_code); | |
38ba30ba GN |
2193 | |
2194 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2195 | rc = writeback(ctxt, ops); |
95c55886 GN |
2196 | if (rc == X86EMUL_CONTINUE) |
2197 | ctxt->eip = c->eip; | |
38ba30ba GN |
2198 | } |
2199 | ||
19d04437 | 2200 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2201 | } |
2202 | ||
90de84f5 | 2203 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2204 | int reg, struct operand *op) |
a682e354 GN |
2205 | { |
2206 | struct decode_cache *c = &ctxt->decode; | |
2207 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2208 | ||
d9271123 | 2209 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
90de84f5 AK |
2210 | op->addr.mem.ea = register_address(c, c->regs[reg]); |
2211 | op->addr.mem.seg = seg; | |
a682e354 GN |
2212 | } |
2213 | ||
63540382 AK |
2214 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2215 | { | |
2216 | emulate_push(ctxt, ctxt->ops); | |
2217 | return X86EMUL_CONTINUE; | |
2218 | } | |
2219 | ||
7af04fc0 AK |
2220 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2221 | { | |
2222 | struct decode_cache *c = &ctxt->decode; | |
2223 | u8 al, old_al; | |
2224 | bool af, cf, old_cf; | |
2225 | ||
2226 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2227 | al = c->dst.val; | |
2228 | ||
2229 | old_al = al; | |
2230 | old_cf = cf; | |
2231 | cf = false; | |
2232 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2233 | if ((al & 0x0f) > 9 || af) { | |
2234 | al -= 6; | |
2235 | cf = old_cf | (al >= 250); | |
2236 | af = true; | |
2237 | } else { | |
2238 | af = false; | |
2239 | } | |
2240 | if (old_al > 0x99 || old_cf) { | |
2241 | al -= 0x60; | |
2242 | cf = true; | |
2243 | } | |
2244 | ||
2245 | c->dst.val = al; | |
2246 | /* Set PF, ZF, SF */ | |
2247 | c->src.type = OP_IMM; | |
2248 | c->src.val = 0; | |
2249 | c->src.bytes = 1; | |
2250 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2251 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2252 | if (cf) | |
2253 | ctxt->eflags |= X86_EFLAGS_CF; | |
2254 | if (af) | |
2255 | ctxt->eflags |= X86_EFLAGS_AF; | |
2256 | return X86EMUL_CONTINUE; | |
2257 | } | |
2258 | ||
0ef753b8 AK |
2259 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2260 | { | |
2261 | struct decode_cache *c = &ctxt->decode; | |
2262 | u16 sel, old_cs; | |
2263 | ulong old_eip; | |
2264 | int rc; | |
2265 | ||
2266 | old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2267 | old_eip = c->eip; | |
2268 | ||
2269 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
2270 | if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS)) | |
2271 | return X86EMUL_CONTINUE; | |
2272 | ||
2273 | c->eip = 0; | |
2274 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
2275 | ||
2276 | c->src.val = old_cs; | |
2277 | emulate_push(ctxt, ctxt->ops); | |
2278 | rc = writeback(ctxt, ctxt->ops); | |
2279 | if (rc != X86EMUL_CONTINUE) | |
2280 | return rc; | |
2281 | ||
2282 | c->src.val = old_eip; | |
2283 | emulate_push(ctxt, ctxt->ops); | |
2284 | rc = writeback(ctxt, ctxt->ops); | |
2285 | if (rc != X86EMUL_CONTINUE) | |
2286 | return rc; | |
2287 | ||
2288 | c->dst.type = OP_NONE; | |
2289 | ||
2290 | return X86EMUL_CONTINUE; | |
2291 | } | |
2292 | ||
40ece7c7 AK |
2293 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2294 | { | |
2295 | struct decode_cache *c = &ctxt->decode; | |
2296 | int rc; | |
2297 | ||
2298 | c->dst.type = OP_REG; | |
2299 | c->dst.addr.reg = &c->eip; | |
2300 | c->dst.bytes = c->op_bytes; | |
2301 | rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes); | |
2302 | if (rc != X86EMUL_CONTINUE) | |
2303 | return rc; | |
2304 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val); | |
2305 | return X86EMUL_CONTINUE; | |
2306 | } | |
2307 | ||
5c82aa29 | 2308 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 AK |
2309 | { |
2310 | struct decode_cache *c = &ctxt->decode; | |
2311 | ||
f3a1b9f4 AK |
2312 | emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags); |
2313 | return X86EMUL_CONTINUE; | |
2314 | } | |
2315 | ||
5c82aa29 AK |
2316 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2317 | { | |
2318 | struct decode_cache *c = &ctxt->decode; | |
2319 | ||
2320 | c->dst.val = c->src2.val; | |
2321 | return em_imul(ctxt); | |
2322 | } | |
2323 | ||
61429142 AK |
2324 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2325 | { | |
2326 | struct decode_cache *c = &ctxt->decode; | |
2327 | ||
2328 | c->dst.type = OP_REG; | |
2329 | c->dst.bytes = c->src.bytes; | |
2330 | c->dst.addr.reg = &c->regs[VCPU_REGS_RDX]; | |
2331 | c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1); | |
2332 | ||
2333 | return X86EMUL_CONTINUE; | |
2334 | } | |
2335 | ||
48bb5d3c AK |
2336 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2337 | { | |
2338 | unsigned cpl = ctxt->ops->cpl(ctxt->vcpu); | |
2339 | struct decode_cache *c = &ctxt->decode; | |
2340 | u64 tsc = 0; | |
2341 | ||
2342 | if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) { | |
2343 | emulate_gp(ctxt, 0); | |
2344 | return X86EMUL_PROPAGATE_FAULT; | |
2345 | } | |
2346 | ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc); | |
2347 | c->regs[VCPU_REGS_RAX] = (u32)tsc; | |
2348 | c->regs[VCPU_REGS_RDX] = tsc >> 32; | |
2349 | return X86EMUL_CONTINUE; | |
2350 | } | |
2351 | ||
b9eac5f4 AK |
2352 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2353 | { | |
2354 | struct decode_cache *c = &ctxt->decode; | |
2355 | c->dst.val = c->src.val; | |
2356 | return X86EMUL_CONTINUE; | |
2357 | } | |
2358 | ||
73fba5f4 AK |
2359 | #define D(_y) { .flags = (_y) } |
2360 | #define N D(0) | |
2361 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2362 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2363 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
2364 | ||
8d8f4e9f AK |
2365 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
2366 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) | |
2367 | ||
6230f7fc AK |
2368 | #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \ |
2369 | D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \ | |
2370 | D2bv(((_f) & ~Lock) | DstAcc | SrcImm) | |
2371 | ||
2372 | ||
73fba5f4 AK |
2373 | static struct opcode group1[] = { |
2374 | X7(D(Lock)), N | |
2375 | }; | |
2376 | ||
2377 | static struct opcode group1A[] = { | |
2378 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2379 | }; | |
2380 | ||
2381 | static struct opcode group3[] = { | |
2382 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2383 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2384 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2385 | }; |
2386 | ||
2387 | static struct opcode group4[] = { | |
2388 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2389 | N, N, N, N, N, N, | |
2390 | }; | |
2391 | ||
2392 | static struct opcode group5[] = { | |
2393 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
2394 | D(SrcMem | ModRM | Stack), |
2395 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
2396 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
2397 | D(SrcMem | ModRM | Stack), N, | |
2398 | }; | |
2399 | ||
2400 | static struct group_dual group7 = { { | |
2401 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2402 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2403 | D(SrcMem16 | ModRM | Mov | Priv), |
2404 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 AK |
2405 | }, { |
2406 | D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv), | |
2407 | D(SrcNone | ModRM | DstMem | Mov), N, | |
2408 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2409 | } }; | |
2410 | ||
2411 | static struct opcode group8[] = { | |
2412 | N, N, N, N, | |
2413 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2414 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2415 | }; | |
2416 | ||
2417 | static struct group_dual group9 = { { | |
2418 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2419 | }, { | |
2420 | N, N, N, N, N, N, N, N, | |
2421 | } }; | |
2422 | ||
a4d4a7c1 AK |
2423 | static struct opcode group11[] = { |
2424 | I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)), | |
2425 | }; | |
2426 | ||
73fba5f4 AK |
2427 | static struct opcode opcode_table[256] = { |
2428 | /* 0x00 - 0x07 */ | |
6230f7fc | 2429 | D6ALU(Lock), |
73fba5f4 AK |
2430 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2431 | /* 0x08 - 0x0F */ | |
6230f7fc | 2432 | D6ALU(Lock), |
73fba5f4 AK |
2433 | D(ImplicitOps | Stack | No64), N, |
2434 | /* 0x10 - 0x17 */ | |
6230f7fc | 2435 | D6ALU(Lock), |
73fba5f4 AK |
2436 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2437 | /* 0x18 - 0x1F */ | |
6230f7fc | 2438 | D6ALU(Lock), |
73fba5f4 AK |
2439 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2440 | /* 0x20 - 0x27 */ | |
6230f7fc | 2441 | D6ALU(Lock), N, N, |
73fba5f4 | 2442 | /* 0x28 - 0x2F */ |
6230f7fc | 2443 | D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 2444 | /* 0x30 - 0x37 */ |
6230f7fc | 2445 | D6ALU(Lock), N, N, |
73fba5f4 | 2446 | /* 0x38 - 0x3F */ |
6230f7fc | 2447 | D6ALU(0), N, N, |
73fba5f4 AK |
2448 | /* 0x40 - 0x4F */ |
2449 | X16(D(DstReg)), | |
2450 | /* 0x50 - 0x57 */ | |
63540382 | 2451 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2452 | /* 0x58 - 0x5F */ |
2453 | X8(D(DstReg | Stack)), | |
2454 | /* 0x60 - 0x67 */ | |
2455 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2456 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2457 | N, N, N, N, | |
2458 | /* 0x68 - 0x6F */ | |
d46164db AK |
2459 | I(SrcImm | Mov | Stack, em_push), |
2460 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
2461 | I(SrcImmByte | Mov | Stack, em_push), |
2462 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
48fe67b5 AK |
2463 | D2bv(DstDI | Mov | String), /* insb, insw/insd */ |
2464 | D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
2465 | /* 0x70 - 0x7F */ |
2466 | X16(D(SrcImmByte)), | |
2467 | /* 0x80 - 0x87 */ | |
2468 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2469 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2470 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2471 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
76e8e68d | 2472 | D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock), |
73fba5f4 | 2473 | /* 0x88 - 0x8F */ |
b9eac5f4 AK |
2474 | I2bv(DstMem | SrcReg | ModRM | Mov, em_mov), |
2475 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), | |
342fc630 | 2476 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2477 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2478 | /* 0x90 - 0x97 */ | |
3d9e77df | 2479 | X8(D(SrcAcc | DstReg)), |
73fba5f4 | 2480 | /* 0x98 - 0x9F */ |
61429142 | 2481 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 2482 | I(SrcImmFAddr | No64, em_call_far), N, |
73fba5f4 AK |
2483 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, |
2484 | /* 0xA0 - 0xA7 */ | |
b9eac5f4 AK |
2485 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
2486 | I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov), | |
2487 | I2bv(SrcSI | DstDI | Mov | String, em_mov), | |
2488 | D2bv(SrcSI | DstDI | String), | |
73fba5f4 | 2489 | /* 0xA8 - 0xAF */ |
50748613 | 2490 | D2bv(DstAcc | SrcImm), |
b9eac5f4 AK |
2491 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
2492 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
48fe67b5 | 2493 | D2bv(SrcAcc | DstDI | String), |
73fba5f4 | 2494 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 2495 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2496 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 2497 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2498 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 2499 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 AK |
2500 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
2501 | D(ImplicitOps | Stack), | |
09b5f4d3 | 2502 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
a4d4a7c1 | 2503 | G(ByteOp, group11), G(0, group11), |
73fba5f4 AK |
2504 | /* 0xC8 - 0xCF */ |
2505 | N, N, N, D(ImplicitOps | Stack), | |
2506 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2507 | /* 0xD0 - 0xD7 */ | |
d2c6c7ad | 2508 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
2509 | N, N, N, N, |
2510 | /* 0xD8 - 0xDF */ | |
2511 | N, N, N, N, N, N, N, N, | |
2512 | /* 0xE0 - 0xE7 */ | |
e4abac67 | 2513 | X4(D(SrcImmByte)), |
d269e396 | 2514 | D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte), |
73fba5f4 AK |
2515 | /* 0xE8 - 0xEF */ |
2516 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2517 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
d269e396 | 2518 | D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps), |
73fba5f4 AK |
2519 | /* 0xF0 - 0xF7 */ |
2520 | N, N, N, N, | |
2521 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2522 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2523 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2524 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2525 | }; | |
2526 | ||
2527 | static struct opcode twobyte_table[256] = { | |
2528 | /* 0x00 - 0x0F */ | |
2529 | N, GD(0, &group7), N, N, | |
2530 | N, D(ImplicitOps), D(ImplicitOps | Priv), N, | |
2531 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, | |
2532 | N, D(ImplicitOps | ModRM), N, N, | |
2533 | /* 0x10 - 0x1F */ | |
2534 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2535 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2536 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2537 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2538 | N, N, N, N, |
2539 | N, N, N, N, N, N, N, N, | |
2540 | /* 0x30 - 0x3F */ | |
48bb5d3c AK |
2541 | D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc), |
2542 | D(ImplicitOps | Priv), N, | |
73fba5f4 AK |
2543 | D(ImplicitOps), D(ImplicitOps | Priv), N, N, |
2544 | N, N, N, N, N, N, N, N, | |
2545 | /* 0x40 - 0x4F */ | |
2546 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2547 | /* 0x50 - 0x5F */ | |
2548 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2549 | /* 0x60 - 0x6F */ | |
2550 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2551 | /* 0x70 - 0x7F */ | |
2552 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2553 | /* 0x80 - 0x8F */ | |
2554 | X16(D(SrcImm)), | |
2555 | /* 0x90 - 0x9F */ | |
ee45b58e | 2556 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2557 | /* 0xA0 - 0xA7 */ |
2558 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2559 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2560 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2561 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2562 | /* 0xA8 - 0xAF */ | |
2563 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2564 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2565 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2566 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 2567 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 2568 | /* 0xB0 - 0xB7 */ |
739ae406 | 2569 | D2bv(DstMem | SrcReg | ModRM | Lock), |
09b5f4d3 WY |
2570 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
2571 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
2572 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
2573 | /* 0xB8 - 0xBF */ |
2574 | N, N, | |
ba7ff2b7 | 2575 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2576 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2577 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2578 | /* 0xC0 - 0xCF */ |
739ae406 | 2579 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 2580 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
2581 | N, N, N, GD(0, &group9), |
2582 | N, N, N, N, N, N, N, N, | |
2583 | /* 0xD0 - 0xDF */ | |
2584 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2585 | /* 0xE0 - 0xEF */ | |
2586 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2587 | /* 0xF0 - 0xFF */ | |
2588 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2589 | }; | |
2590 | ||
2591 | #undef D | |
2592 | #undef N | |
2593 | #undef G | |
2594 | #undef GD | |
2595 | #undef I | |
2596 | ||
8d8f4e9f AK |
2597 | #undef D2bv |
2598 | #undef I2bv | |
6230f7fc | 2599 | #undef D6ALU |
8d8f4e9f | 2600 | |
39f21ee5 AK |
2601 | static unsigned imm_size(struct decode_cache *c) |
2602 | { | |
2603 | unsigned size; | |
2604 | ||
2605 | size = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2606 | if (size == 8) | |
2607 | size = 4; | |
2608 | return size; | |
2609 | } | |
2610 | ||
2611 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
2612 | unsigned size, bool sign_extension) | |
2613 | { | |
2614 | struct decode_cache *c = &ctxt->decode; | |
2615 | struct x86_emulate_ops *ops = ctxt->ops; | |
2616 | int rc = X86EMUL_CONTINUE; | |
2617 | ||
2618 | op->type = OP_IMM; | |
2619 | op->bytes = size; | |
90de84f5 | 2620 | op->addr.mem.ea = c->eip; |
39f21ee5 AK |
2621 | /* NB. Immediates are sign-extended as necessary. */ |
2622 | switch (op->bytes) { | |
2623 | case 1: | |
2624 | op->val = insn_fetch(s8, 1, c->eip); | |
2625 | break; | |
2626 | case 2: | |
2627 | op->val = insn_fetch(s16, 2, c->eip); | |
2628 | break; | |
2629 | case 4: | |
2630 | op->val = insn_fetch(s32, 4, c->eip); | |
2631 | break; | |
2632 | } | |
2633 | if (!sign_extension) { | |
2634 | switch (op->bytes) { | |
2635 | case 1: | |
2636 | op->val &= 0xff; | |
2637 | break; | |
2638 | case 2: | |
2639 | op->val &= 0xffff; | |
2640 | break; | |
2641 | case 4: | |
2642 | op->val &= 0xffffffff; | |
2643 | break; | |
2644 | } | |
2645 | } | |
2646 | done: | |
2647 | return rc; | |
2648 | } | |
2649 | ||
dde7e6d1 AK |
2650 | int |
2651 | x86_decode_insn(struct x86_emulate_ctxt *ctxt) | |
2652 | { | |
2653 | struct x86_emulate_ops *ops = ctxt->ops; | |
2654 | struct decode_cache *c = &ctxt->decode; | |
2655 | int rc = X86EMUL_CONTINUE; | |
2656 | int mode = ctxt->mode; | |
2657 | int def_op_bytes, def_ad_bytes, dual, goffset; | |
2658 | struct opcode opcode, *g_mod012, *g_mod3; | |
2dbd0dd7 | 2659 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 | 2660 | |
dde7e6d1 AK |
2661 | c->eip = ctxt->eip; |
2662 | c->fetch.start = c->fetch.end = c->eip; | |
2663 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); | |
2664 | ||
2665 | switch (mode) { | |
2666 | case X86EMUL_MODE_REAL: | |
2667 | case X86EMUL_MODE_VM86: | |
2668 | case X86EMUL_MODE_PROT16: | |
2669 | def_op_bytes = def_ad_bytes = 2; | |
2670 | break; | |
2671 | case X86EMUL_MODE_PROT32: | |
2672 | def_op_bytes = def_ad_bytes = 4; | |
2673 | break; | |
2674 | #ifdef CONFIG_X86_64 | |
2675 | case X86EMUL_MODE_PROT64: | |
2676 | def_op_bytes = 4; | |
2677 | def_ad_bytes = 8; | |
2678 | break; | |
2679 | #endif | |
2680 | default: | |
2681 | return -1; | |
2682 | } | |
2683 | ||
2684 | c->op_bytes = def_op_bytes; | |
2685 | c->ad_bytes = def_ad_bytes; | |
2686 | ||
2687 | /* Legacy prefixes. */ | |
2688 | for (;;) { | |
2689 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2690 | case 0x66: /* operand-size override */ | |
2691 | /* switch between 2/4 bytes */ | |
2692 | c->op_bytes = def_op_bytes ^ 6; | |
2693 | break; | |
2694 | case 0x67: /* address-size override */ | |
2695 | if (mode == X86EMUL_MODE_PROT64) | |
2696 | /* switch between 4/8 bytes */ | |
2697 | c->ad_bytes = def_ad_bytes ^ 12; | |
2698 | else | |
2699 | /* switch between 2/4 bytes */ | |
2700 | c->ad_bytes = def_ad_bytes ^ 6; | |
2701 | break; | |
2702 | case 0x26: /* ES override */ | |
2703 | case 0x2e: /* CS override */ | |
2704 | case 0x36: /* SS override */ | |
2705 | case 0x3e: /* DS override */ | |
2706 | set_seg_override(c, (c->b >> 3) & 3); | |
2707 | break; | |
2708 | case 0x64: /* FS override */ | |
2709 | case 0x65: /* GS override */ | |
2710 | set_seg_override(c, c->b & 7); | |
2711 | break; | |
2712 | case 0x40 ... 0x4f: /* REX */ | |
2713 | if (mode != X86EMUL_MODE_PROT64) | |
2714 | goto done_prefixes; | |
2715 | c->rex_prefix = c->b; | |
2716 | continue; | |
2717 | case 0xf0: /* LOCK */ | |
2718 | c->lock_prefix = 1; | |
2719 | break; | |
2720 | case 0xf2: /* REPNE/REPNZ */ | |
2721 | c->rep_prefix = REPNE_PREFIX; | |
2722 | break; | |
2723 | case 0xf3: /* REP/REPE/REPZ */ | |
2724 | c->rep_prefix = REPE_PREFIX; | |
2725 | break; | |
2726 | default: | |
2727 | goto done_prefixes; | |
2728 | } | |
2729 | ||
2730 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2731 | ||
2732 | c->rex_prefix = 0; | |
2733 | } | |
2734 | ||
2735 | done_prefixes: | |
2736 | ||
2737 | /* REX prefix. */ | |
1e87e3ef AK |
2738 | if (c->rex_prefix & 8) |
2739 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2740 | |
2741 | /* Opcode byte(s). */ | |
2742 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2743 | /* Two-byte opcode? */ |
2744 | if (c->b == 0x0f) { | |
2745 | c->twobyte = 1; | |
2746 | c->b = insn_fetch(u8, 1, c->eip); | |
2747 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2748 | } |
2749 | c->d = opcode.flags; | |
2750 | ||
2751 | if (c->d & Group) { | |
2752 | dual = c->d & GroupDual; | |
2753 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2754 | --c->eip; | |
2755 | ||
2756 | if (c->d & GroupDual) { | |
2757 | g_mod012 = opcode.u.gdual->mod012; | |
2758 | g_mod3 = opcode.u.gdual->mod3; | |
2759 | } else | |
2760 | g_mod012 = g_mod3 = opcode.u.group; | |
2761 | ||
2762 | c->d &= ~(Group | GroupDual); | |
2763 | ||
2764 | goffset = (c->modrm >> 3) & 7; | |
2765 | ||
2766 | if ((c->modrm >> 6) == 3) | |
2767 | opcode = g_mod3[goffset]; | |
2768 | else | |
2769 | opcode = g_mod012[goffset]; | |
2770 | c->d |= opcode.flags; | |
2771 | } | |
2772 | ||
2773 | c->execute = opcode.u.execute; | |
2774 | ||
2775 | /* Unrecognised? */ | |
d53db5ef | 2776 | if (c->d == 0 || (c->d & Undefined)) |
dde7e6d1 | 2777 | return -1; |
dde7e6d1 AK |
2778 | |
2779 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) | |
2780 | c->op_bytes = 8; | |
2781 | ||
7f9b4b75 AK |
2782 | if (c->d & Op3264) { |
2783 | if (mode == X86EMUL_MODE_PROT64) | |
2784 | c->op_bytes = 8; | |
2785 | else | |
2786 | c->op_bytes = 4; | |
2787 | } | |
2788 | ||
dde7e6d1 | 2789 | /* ModRM and SIB bytes. */ |
09ee57cd | 2790 | if (c->d & ModRM) { |
2dbd0dd7 | 2791 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2792 | if (!c->has_seg_override) |
2793 | set_seg_override(c, c->modrm_seg); | |
2794 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2795 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2796 | if (rc != X86EMUL_CONTINUE) |
2797 | goto done; | |
2798 | ||
2799 | if (!c->has_seg_override) | |
2800 | set_seg_override(c, VCPU_SREG_DS); | |
2801 | ||
90de84f5 | 2802 | memop.addr.mem.seg = seg_override(ctxt, ops, c); |
dde7e6d1 | 2803 | |
2dbd0dd7 | 2804 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
90de84f5 | 2805 | memop.addr.mem.ea = (u32)memop.addr.mem.ea; |
dde7e6d1 | 2806 | |
2dbd0dd7 | 2807 | if (memop.type == OP_MEM && c->rip_relative) |
90de84f5 | 2808 | memop.addr.mem.ea += c->eip; |
dde7e6d1 AK |
2809 | |
2810 | /* | |
2811 | * Decode and fetch the source operand: register, memory | |
2812 | * or immediate. | |
2813 | */ | |
2814 | switch (c->d & SrcMask) { | |
2815 | case SrcNone: | |
2816 | break; | |
2817 | case SrcReg: | |
2818 | decode_register_operand(&c->src, c, 0); | |
2819 | break; | |
2820 | case SrcMem16: | |
2dbd0dd7 | 2821 | memop.bytes = 2; |
dde7e6d1 AK |
2822 | goto srcmem_common; |
2823 | case SrcMem32: | |
2dbd0dd7 | 2824 | memop.bytes = 4; |
dde7e6d1 AK |
2825 | goto srcmem_common; |
2826 | case SrcMem: | |
2dbd0dd7 | 2827 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2828 | c->op_bytes; |
dde7e6d1 | 2829 | srcmem_common: |
2dbd0dd7 | 2830 | c->src = memop; |
dde7e6d1 | 2831 | break; |
b250e605 | 2832 | case SrcImmU16: |
39f21ee5 AK |
2833 | rc = decode_imm(ctxt, &c->src, 2, false); |
2834 | break; | |
dde7e6d1 | 2835 | case SrcImm: |
39f21ee5 AK |
2836 | rc = decode_imm(ctxt, &c->src, imm_size(c), true); |
2837 | break; | |
dde7e6d1 | 2838 | case SrcImmU: |
39f21ee5 | 2839 | rc = decode_imm(ctxt, &c->src, imm_size(c), false); |
dde7e6d1 AK |
2840 | break; |
2841 | case SrcImmByte: | |
39f21ee5 AK |
2842 | rc = decode_imm(ctxt, &c->src, 1, true); |
2843 | break; | |
dde7e6d1 | 2844 | case SrcImmUByte: |
39f21ee5 | 2845 | rc = decode_imm(ctxt, &c->src, 1, false); |
dde7e6d1 AK |
2846 | break; |
2847 | case SrcAcc: | |
2848 | c->src.type = OP_REG; | |
2849 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2850 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2851 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2852 | break; |
2853 | case SrcOne: | |
2854 | c->src.bytes = 1; | |
2855 | c->src.val = 1; | |
2856 | break; | |
2857 | case SrcSI: | |
2858 | c->src.type = OP_MEM; | |
2859 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
2860 | c->src.addr.mem.ea = |
2861 | register_address(c, c->regs[VCPU_REGS_RSI]); | |
2862 | c->src.addr.mem.seg = seg_override(ctxt, ops, c), | |
dde7e6d1 AK |
2863 | c->src.val = 0; |
2864 | break; | |
2865 | case SrcImmFAddr: | |
2866 | c->src.type = OP_IMM; | |
90de84f5 | 2867 | c->src.addr.mem.ea = c->eip; |
dde7e6d1 AK |
2868 | c->src.bytes = c->op_bytes + 2; |
2869 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2870 | break; | |
2871 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2872 | memop.bytes = c->op_bytes + 2; |
2873 | goto srcmem_common; | |
dde7e6d1 AK |
2874 | break; |
2875 | } | |
2876 | ||
39f21ee5 AK |
2877 | if (rc != X86EMUL_CONTINUE) |
2878 | goto done; | |
2879 | ||
dde7e6d1 AK |
2880 | /* |
2881 | * Decode and fetch the second source operand: register, memory | |
2882 | * or immediate. | |
2883 | */ | |
2884 | switch (c->d & Src2Mask) { | |
2885 | case Src2None: | |
2886 | break; | |
2887 | case Src2CL: | |
2888 | c->src2.bytes = 1; | |
2889 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2890 | break; | |
2891 | case Src2ImmByte: | |
39f21ee5 | 2892 | rc = decode_imm(ctxt, &c->src2, 1, true); |
dde7e6d1 AK |
2893 | break; |
2894 | case Src2One: | |
2895 | c->src2.bytes = 1; | |
2896 | c->src2.val = 1; | |
2897 | break; | |
7db41eb7 AK |
2898 | case Src2Imm: |
2899 | rc = decode_imm(ctxt, &c->src2, imm_size(c), true); | |
2900 | break; | |
dde7e6d1 AK |
2901 | } |
2902 | ||
39f21ee5 AK |
2903 | if (rc != X86EMUL_CONTINUE) |
2904 | goto done; | |
2905 | ||
dde7e6d1 AK |
2906 | /* Decode and fetch the destination operand: register or memory. */ |
2907 | switch (c->d & DstMask) { | |
dde7e6d1 AK |
2908 | case DstReg: |
2909 | decode_register_operand(&c->dst, c, | |
2910 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); | |
2911 | break; | |
943858e2 WY |
2912 | case DstImmUByte: |
2913 | c->dst.type = OP_IMM; | |
90de84f5 | 2914 | c->dst.addr.mem.ea = c->eip; |
943858e2 WY |
2915 | c->dst.bytes = 1; |
2916 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
2917 | break; | |
dde7e6d1 AK |
2918 | case DstMem: |
2919 | case DstMem64: | |
2dbd0dd7 | 2920 | c->dst = memop; |
dde7e6d1 AK |
2921 | if ((c->d & DstMask) == DstMem64) |
2922 | c->dst.bytes = 8; | |
2923 | else | |
2924 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
2925 | if (c->d & BitOp) |
2926 | fetch_bit_operand(c); | |
2dbd0dd7 | 2927 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
2928 | break; |
2929 | case DstAcc: | |
2930 | c->dst.type = OP_REG; | |
2931 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2932 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2933 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
2934 | c->dst.orig_val = c->dst.val; |
2935 | break; | |
2936 | case DstDI: | |
2937 | c->dst.type = OP_MEM; | |
2938 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
2939 | c->dst.addr.mem.ea = |
2940 | register_address(c, c->regs[VCPU_REGS_RDI]); | |
2941 | c->dst.addr.mem.seg = VCPU_SREG_ES; | |
dde7e6d1 AK |
2942 | c->dst.val = 0; |
2943 | break; | |
36089fed WY |
2944 | case ImplicitOps: |
2945 | /* Special instructions do their own operand decoding. */ | |
2946 | default: | |
2947 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2948 | return 0; | |
dde7e6d1 AK |
2949 | } |
2950 | ||
2951 | done: | |
2952 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
2953 | } | |
2954 | ||
3e2f65d5 GN |
2955 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
2956 | { | |
2957 | struct decode_cache *c = &ctxt->decode; | |
2958 | ||
2959 | /* The second termination condition only applies for REPE | |
2960 | * and REPNE. Test if the repeat string operation prefix is | |
2961 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2962 | * corresponding termination condition according to: | |
2963 | * - if REPE/REPZ and ZF = 0 then done | |
2964 | * - if REPNE/REPNZ and ZF = 1 then done | |
2965 | */ | |
2966 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
2967 | (c->b == 0xae) || (c->b == 0xaf)) | |
2968 | && (((c->rep_prefix == REPE_PREFIX) && | |
2969 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
2970 | || ((c->rep_prefix == REPNE_PREFIX) && | |
2971 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
2972 | return true; | |
2973 | ||
2974 | return false; | |
2975 | } | |
2976 | ||
8b4caf66 | 2977 | int |
9aabc88f | 2978 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 2979 | { |
9aabc88f | 2980 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 2981 | u64 msr_data; |
8b4caf66 | 2982 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2983 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2984 | int saved_dst_type = c->dst.type; |
6e154e56 | 2985 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 2986 | |
9de41573 | 2987 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2988 | |
1161624f | 2989 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2990 | emulate_ud(ctxt); |
da9cb575 | 2991 | rc = X86EMUL_PROPAGATE_FAULT; |
1161624f GN |
2992 | goto done; |
2993 | } | |
2994 | ||
d380a5e4 | 2995 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2996 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2997 | emulate_ud(ctxt); |
da9cb575 | 2998 | rc = X86EMUL_PROPAGATE_FAULT; |
d380a5e4 GN |
2999 | goto done; |
3000 | } | |
3001 | ||
081bca0e AK |
3002 | if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) { |
3003 | emulate_ud(ctxt); | |
da9cb575 | 3004 | rc = X86EMUL_PROPAGATE_FAULT; |
081bca0e AK |
3005 | goto done; |
3006 | } | |
3007 | ||
e92805ac | 3008 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 3009 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 3010 | emulate_gp(ctxt, 0); |
da9cb575 | 3011 | rc = X86EMUL_PROPAGATE_FAULT; |
e92805ac GN |
3012 | goto done; |
3013 | } | |
3014 | ||
b9fa9d6b AK |
3015 | if (c->rep_prefix && (c->d & String)) { |
3016 | /* All REP prefixes have the same first termination condition */ | |
c73e197b | 3017 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
95c55886 | 3018 | ctxt->eip = c->eip; |
b9fa9d6b AK |
3019 | goto done; |
3020 | } | |
b9fa9d6b AK |
3021 | } |
3022 | ||
c483c02a | 3023 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
90de84f5 | 3024 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem), |
414e6277 | 3025 | c->src.valptr, c->src.bytes); |
b60d513c | 3026 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 3027 | goto done; |
16518d5a | 3028 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
3029 | } |
3030 | ||
e35b7b9c | 3031 | if (c->src2.type == OP_MEM) { |
90de84f5 | 3032 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem), |
9de41573 | 3033 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
3034 | if (rc != X86EMUL_CONTINUE) |
3035 | goto done; | |
3036 | } | |
3037 | ||
8b4caf66 LV |
3038 | if ((c->d & DstMask) == ImplicitOps) |
3039 | goto special_insn; | |
3040 | ||
3041 | ||
69f55cb1 GN |
3042 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
3043 | /* optimisation - avoid slow emulated read if Mov */ | |
90de84f5 | 3044 | rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem), |
9de41573 | 3045 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
3046 | if (rc != X86EMUL_CONTINUE) |
3047 | goto done; | |
038e51de | 3048 | } |
e4e03ded | 3049 | c->dst.orig_val = c->dst.val; |
038e51de | 3050 | |
018a98db AK |
3051 | special_insn: |
3052 | ||
ef65c889 AK |
3053 | if (c->execute) { |
3054 | rc = c->execute(ctxt); | |
3055 | if (rc != X86EMUL_CONTINUE) | |
3056 | goto done; | |
3057 | goto writeback; | |
3058 | } | |
3059 | ||
e4e03ded | 3060 | if (c->twobyte) |
6aa8b732 AK |
3061 | goto twobyte_insn; |
3062 | ||
e4e03ded | 3063 | switch (c->b) { |
6aa8b732 AK |
3064 | case 0x00 ... 0x05: |
3065 | add: /* add */ | |
05f086f8 | 3066 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3067 | break; |
0934ac9d | 3068 | case 0x06: /* push es */ |
79168fd1 | 3069 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
3070 | break; |
3071 | case 0x07: /* pop es */ | |
0934ac9d | 3072 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d | 3073 | break; |
6aa8b732 AK |
3074 | case 0x08 ... 0x0d: |
3075 | or: /* or */ | |
05f086f8 | 3076 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3077 | break; |
0934ac9d | 3078 | case 0x0e: /* push cs */ |
79168fd1 | 3079 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 3080 | break; |
6aa8b732 AK |
3081 | case 0x10 ... 0x15: |
3082 | adc: /* adc */ | |
05f086f8 | 3083 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3084 | break; |
0934ac9d | 3085 | case 0x16: /* push ss */ |
79168fd1 | 3086 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
3087 | break; |
3088 | case 0x17: /* pop ss */ | |
0934ac9d | 3089 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d | 3090 | break; |
6aa8b732 AK |
3091 | case 0x18 ... 0x1d: |
3092 | sbb: /* sbb */ | |
05f086f8 | 3093 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3094 | break; |
0934ac9d | 3095 | case 0x1e: /* push ds */ |
79168fd1 | 3096 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
3097 | break; |
3098 | case 0x1f: /* pop ds */ | |
0934ac9d | 3099 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d | 3100 | break; |
aa3a816b | 3101 | case 0x20 ... 0x25: |
6aa8b732 | 3102 | and: /* and */ |
05f086f8 | 3103 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3104 | break; |
3105 | case 0x28 ... 0x2d: | |
3106 | sub: /* sub */ | |
05f086f8 | 3107 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3108 | break; |
3109 | case 0x30 ... 0x35: | |
3110 | xor: /* xor */ | |
05f086f8 | 3111 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3112 | break; |
3113 | case 0x38 ... 0x3d: | |
3114 | cmp: /* cmp */ | |
05f086f8 | 3115 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3116 | break; |
33615aa9 AK |
3117 | case 0x40 ... 0x47: /* inc r16/r32 */ |
3118 | emulate_1op("inc", c->dst, ctxt->eflags); | |
3119 | break; | |
3120 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
3121 | emulate_1op("dec", c->dst, ctxt->eflags); | |
3122 | break; | |
33615aa9 AK |
3123 | case 0x58 ... 0x5f: /* pop reg */ |
3124 | pop_instruction: | |
350f69dc | 3125 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
33615aa9 | 3126 | break; |
abcf14b5 | 3127 | case 0x60: /* pusha */ |
c37eda13 | 3128 | rc = emulate_pusha(ctxt, ops); |
abcf14b5 MG |
3129 | break; |
3130 | case 0x61: /* popa */ | |
3131 | rc = emulate_popa(ctxt, ops); | |
abcf14b5 | 3132 | break; |
6aa8b732 | 3133 | case 0x63: /* movsxd */ |
8b4caf66 | 3134 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3135 | goto cannot_emulate; |
e4e03ded | 3136 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 3137 | break; |
018a98db AK |
3138 | case 0x6c: /* insb */ |
3139 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
3140 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3141 | goto do_io_in; | |
018a98db AK |
3142 | case 0x6e: /* outsb */ |
3143 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
3144 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
3145 | goto do_io_out; | |
7972995b | 3146 | break; |
b2833e3c | 3147 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 3148 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3149 | jmp_rel(c, c->src.val); |
018a98db | 3150 | break; |
6aa8b732 | 3151 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 3152 | switch (c->modrm_reg) { |
6aa8b732 AK |
3153 | case 0: |
3154 | goto add; | |
3155 | case 1: | |
3156 | goto or; | |
3157 | case 2: | |
3158 | goto adc; | |
3159 | case 3: | |
3160 | goto sbb; | |
3161 | case 4: | |
3162 | goto and; | |
3163 | case 5: | |
3164 | goto sub; | |
3165 | case 6: | |
3166 | goto xor; | |
3167 | case 7: | |
3168 | goto cmp; | |
3169 | } | |
3170 | break; | |
3171 | case 0x84 ... 0x85: | |
dfb507c4 | 3172 | test: |
05f086f8 | 3173 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3174 | break; |
3175 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 3176 | xchg: |
6aa8b732 | 3177 | /* Write back the register source. */ |
31be40b3 WY |
3178 | c->src.val = c->dst.val; |
3179 | write_register_operand(&c->src); | |
6aa8b732 AK |
3180 | /* |
3181 | * Write back the memory destination with implicit LOCK | |
3182 | * prefix. | |
3183 | */ | |
31be40b3 | 3184 | c->dst.val = c->src.orig_val; |
e4e03ded | 3185 | c->lock_prefix = 1; |
6aa8b732 | 3186 | break; |
79168fd1 GN |
3187 | case 0x8c: /* mov r/m, sreg */ |
3188 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3189 | emulate_ud(ctxt); |
da9cb575 | 3190 | rc = X86EMUL_PROPAGATE_FAULT; |
5e3ae6c5 | 3191 | goto done; |
38d5bc6d | 3192 | } |
79168fd1 | 3193 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3194 | break; |
7e0b54b1 | 3195 | case 0x8d: /* lea r16/r32, m */ |
90de84f5 | 3196 | c->dst.val = c->src.addr.mem.ea; |
7e0b54b1 | 3197 | break; |
4257198a GT |
3198 | case 0x8e: { /* mov seg, r/m16 */ |
3199 | uint16_t sel; | |
4257198a GT |
3200 | |
3201 | sel = c->src.val; | |
8b9f4414 | 3202 | |
c697518a GN |
3203 | if (c->modrm_reg == VCPU_SREG_CS || |
3204 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3205 | emulate_ud(ctxt); |
da9cb575 | 3206 | rc = X86EMUL_PROPAGATE_FAULT; |
8b9f4414 GN |
3207 | goto done; |
3208 | } | |
3209 | ||
310b5d30 | 3210 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3211 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3212 | |
2e873022 | 3213 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3214 | |
3215 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3216 | break; | |
3217 | } | |
6aa8b732 | 3218 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3219 | rc = emulate_grp1a(ctxt, ops); |
6aa8b732 | 3220 | break; |
3d9e77df AK |
3221 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3222 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3223 | break; |
b13354f8 | 3224 | goto xchg; |
e8b6fa70 WY |
3225 | case 0x98: /* cbw/cwde/cdqe */ |
3226 | switch (c->op_bytes) { | |
3227 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3228 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3229 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3230 | } | |
3231 | break; | |
fd2a7608 | 3232 | case 0x9c: /* pushf */ |
05f086f8 | 3233 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3234 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3235 | break; |
535eabcf | 3236 | case 0x9d: /* popf */ |
2b48cc75 | 3237 | c->dst.type = OP_REG; |
1a6440ae | 3238 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3239 | c->dst.bytes = c->op_bytes; |
d4c6a154 | 3240 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
d4c6a154 | 3241 | break; |
6aa8b732 | 3242 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3243 | c->dst.type = OP_NONE; /* Disable writeback. */ |
a682e354 | 3244 | goto cmp; |
dfb507c4 MG |
3245 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3246 | goto test; | |
6aa8b732 | 3247 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3248 | goto cmp; |
018a98db AK |
3249 | case 0xc0 ... 0xc1: |
3250 | emulate_grp2(ctxt); | |
3251 | break; | |
111de5d6 | 3252 | case 0xc3: /* ret */ |
cf5de4f8 | 3253 | c->dst.type = OP_REG; |
1a6440ae | 3254 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3255 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3256 | goto pop_instruction; |
09b5f4d3 WY |
3257 | case 0xc4: /* les */ |
3258 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES); | |
09b5f4d3 WY |
3259 | break; |
3260 | case 0xc5: /* lds */ | |
3261 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS); | |
09b5f4d3 | 3262 | break; |
a77ab5ea AK |
3263 | case 0xcb: /* ret far */ |
3264 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e | 3265 | break; |
6e154e56 MG |
3266 | case 0xcc: /* int3 */ |
3267 | irq = 3; | |
3268 | goto do_interrupt; | |
3269 | case 0xcd: /* int n */ | |
3270 | irq = c->src.val; | |
3271 | do_interrupt: | |
3272 | rc = emulate_int(ctxt, ops, irq); | |
6e154e56 MG |
3273 | break; |
3274 | case 0xce: /* into */ | |
3275 | if (ctxt->eflags & EFLG_OF) { | |
3276 | irq = 4; | |
3277 | goto do_interrupt; | |
3278 | } | |
3279 | break; | |
62bd430e MG |
3280 | case 0xcf: /* iret */ |
3281 | rc = emulate_iret(ctxt, ops); | |
a77ab5ea | 3282 | break; |
018a98db | 3283 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3284 | emulate_grp2(ctxt); |
3285 | break; | |
3286 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3287 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3288 | emulate_grp2(ctxt); | |
3289 | break; | |
f2f31845 WY |
3290 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3291 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3292 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3293 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3294 | jmp_rel(c, c->src.val); | |
3295 | break; | |
e4abac67 WY |
3296 | case 0xe3: /* jcxz/jecxz/jrcxz */ |
3297 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) | |
3298 | jmp_rel(c, c->src.val); | |
3299 | break; | |
a6a3034c MG |
3300 | case 0xe4: /* inb */ |
3301 | case 0xe5: /* in */ | |
cf8f70bf | 3302 | goto do_io_in; |
a6a3034c MG |
3303 | case 0xe6: /* outb */ |
3304 | case 0xe7: /* out */ | |
cf8f70bf | 3305 | goto do_io_out; |
1a52e051 | 3306 | case 0xe8: /* call (near) */ { |
d53c4777 | 3307 | long int rel = c->src.val; |
e4e03ded | 3308 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3309 | jmp_rel(c, rel); |
79168fd1 | 3310 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3311 | break; |
1a52e051 NK |
3312 | } |
3313 | case 0xe9: /* jmp rel */ | |
954cd36f | 3314 | goto jmp; |
414e6277 GN |
3315 | case 0xea: { /* jmp far */ |
3316 | unsigned short sel; | |
ea79849d | 3317 | jump_far: |
414e6277 GN |
3318 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3319 | ||
3320 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3321 | goto done; |
954cd36f | 3322 | |
414e6277 GN |
3323 | c->eip = 0; |
3324 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3325 | break; |
414e6277 | 3326 | } |
954cd36f GT |
3327 | case 0xeb: |
3328 | jmp: /* jmp rel short */ | |
7a957275 | 3329 | jmp_rel(c, c->src.val); |
a01af5ec | 3330 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3331 | break; |
a6a3034c MG |
3332 | case 0xec: /* in al,dx */ |
3333 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3334 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3335 | do_io_in: | |
3336 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3337 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3338 | emulate_gp(ctxt, 0); |
da9cb575 | 3339 | rc = X86EMUL_PROPAGATE_FAULT; |
cf8f70bf GN |
3340 | goto done; |
3341 | } | |
7b262e90 GN |
3342 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3343 | &c->dst.val)) | |
cf8f70bf GN |
3344 | goto done; /* IO is needed */ |
3345 | break; | |
ce7a0ad3 WY |
3346 | case 0xee: /* out dx,al */ |
3347 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3348 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3349 | do_io_out: |
41167be5 WY |
3350 | c->src.bytes = min(c->src.bytes, 4u); |
3351 | if (!emulator_io_permited(ctxt, ops, c->dst.val, | |
3352 | c->src.bytes)) { | |
54b8486f | 3353 | emulate_gp(ctxt, 0); |
da9cb575 | 3354 | rc = X86EMUL_PROPAGATE_FAULT; |
f850e2e6 GN |
3355 | goto done; |
3356 | } | |
41167be5 WY |
3357 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3358 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3359 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3360 | break; |
111de5d6 | 3361 | case 0xf4: /* hlt */ |
ad312c7c | 3362 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3363 | break; |
111de5d6 AK |
3364 | case 0xf5: /* cmc */ |
3365 | /* complement carry flag from eflags reg */ | |
3366 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3367 | break; |
018a98db | 3368 | case 0xf6 ... 0xf7: /* Grp3 */ |
34d1f490 | 3369 | rc = emulate_grp3(ctxt, ops); |
018a98db | 3370 | break; |
111de5d6 AK |
3371 | case 0xf8: /* clc */ |
3372 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3373 | break; |
8744aa9a MG |
3374 | case 0xf9: /* stc */ |
3375 | ctxt->eflags |= EFLG_CF; | |
3376 | break; | |
111de5d6 | 3377 | case 0xfa: /* cli */ |
07cbc6c1 | 3378 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3379 | emulate_gp(ctxt, 0); |
da9cb575 | 3380 | rc = X86EMUL_PROPAGATE_FAULT; |
07cbc6c1 | 3381 | goto done; |
36089fed | 3382 | } else |
f850e2e6 | 3383 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3384 | break; |
3385 | case 0xfb: /* sti */ | |
07cbc6c1 | 3386 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3387 | emulate_gp(ctxt, 0); |
da9cb575 | 3388 | rc = X86EMUL_PROPAGATE_FAULT; |
07cbc6c1 WY |
3389 | goto done; |
3390 | } else { | |
95cb2295 | 3391 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3392 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3393 | } |
111de5d6 | 3394 | break; |
fb4616f4 MG |
3395 | case 0xfc: /* cld */ |
3396 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3397 | break; |
3398 | case 0xfd: /* std */ | |
3399 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3400 | break; |
ea79849d GN |
3401 | case 0xfe: /* Grp4 */ |
3402 | grp45: | |
018a98db | 3403 | rc = emulate_grp45(ctxt, ops); |
018a98db | 3404 | break; |
ea79849d GN |
3405 | case 0xff: /* Grp5 */ |
3406 | if (c->modrm_reg == 5) | |
3407 | goto jump_far; | |
3408 | goto grp45; | |
91269b8f AK |
3409 | default: |
3410 | goto cannot_emulate; | |
6aa8b732 | 3411 | } |
018a98db | 3412 | |
7d9ddaed AK |
3413 | if (rc != X86EMUL_CONTINUE) |
3414 | goto done; | |
3415 | ||
018a98db AK |
3416 | writeback: |
3417 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3418 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3419 | goto done; |
3420 | ||
5cd21917 GN |
3421 | /* |
3422 | * restore dst type in case the decoding will be reused | |
3423 | * (happens for string instruction ) | |
3424 | */ | |
3425 | c->dst.type = saved_dst_type; | |
3426 | ||
a682e354 | 3427 | if ((c->d & SrcMask) == SrcSI) |
90de84f5 | 3428 | string_addr_inc(ctxt, seg_override(ctxt, ops, c), |
79168fd1 | 3429 | VCPU_REGS_RSI, &c->src); |
a682e354 GN |
3430 | |
3431 | if ((c->d & DstMask) == DstDI) | |
90de84f5 | 3432 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
79168fd1 | 3433 | &c->dst); |
d9271123 | 3434 | |
5cd21917 | 3435 | if (c->rep_prefix && (c->d & String)) { |
6e2fb2ca | 3436 | struct read_cache *r = &ctxt->decode.io_read; |
d9271123 | 3437 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
3e2f65d5 | 3438 | |
d2ddd1c4 GN |
3439 | if (!string_insn_completed(ctxt)) { |
3440 | /* | |
3441 | * Re-enter guest when pio read ahead buffer is empty | |
3442 | * or, if it is not used, after each 1024 iteration. | |
3443 | */ | |
3444 | if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) && | |
3445 | (r->end == 0 || r->end != r->pos)) { | |
3446 | /* | |
3447 | * Reset read cache. Usually happens before | |
3448 | * decode, but since instruction is restarted | |
3449 | * we have to do it here. | |
3450 | */ | |
3451 | ctxt->decode.mem_read.end = 0; | |
3452 | return EMULATION_RESTART; | |
3453 | } | |
3454 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 3455 | } |
5cd21917 | 3456 | } |
d2ddd1c4 GN |
3457 | |
3458 | ctxt->eip = c->eip; | |
018a98db AK |
3459 | |
3460 | done: | |
da9cb575 AK |
3461 | if (rc == X86EMUL_PROPAGATE_FAULT) |
3462 | ctxt->have_exception = true; | |
d2ddd1c4 | 3463 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
3464 | |
3465 | twobyte_insn: | |
e4e03ded | 3466 | switch (c->b) { |
6aa8b732 | 3467 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3468 | switch (c->modrm_reg) { |
6aa8b732 AK |
3469 | u16 size; |
3470 | unsigned long address; | |
3471 | ||
aca7f966 | 3472 | case 0: /* vmcall */ |
e4e03ded | 3473 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3474 | goto cannot_emulate; |
3475 | ||
7aa81cc0 | 3476 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3477 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3478 | goto done; |
3479 | ||
33e3885d | 3480 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3481 | c->eip = ctxt->eip; |
16286d08 AK |
3482 | /* Disable writeback. */ |
3483 | c->dst.type = OP_NONE; | |
aca7f966 | 3484 | break; |
6aa8b732 | 3485 | case 2: /* lgdt */ |
1a6440ae | 3486 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3487 | &size, &address, c->op_bytes); |
1b30eaa8 | 3488 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3489 | goto done; |
3490 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3491 | /* Disable writeback. */ |
3492 | c->dst.type = OP_NONE; | |
6aa8b732 | 3493 | break; |
aca7f966 | 3494 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3495 | if (c->modrm_mod == 3) { |
3496 | switch (c->modrm_rm) { | |
3497 | case 1: | |
3498 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
2b3d2a20 AK |
3499 | break; |
3500 | default: | |
3501 | goto cannot_emulate; | |
3502 | } | |
aca7f966 | 3503 | } else { |
1a6440ae | 3504 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3505 | &size, &address, |
e4e03ded | 3506 | c->op_bytes); |
1b30eaa8 | 3507 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3508 | goto done; |
3509 | realmode_lidt(ctxt->vcpu, size, address); | |
3510 | } | |
16286d08 AK |
3511 | /* Disable writeback. */ |
3512 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3513 | break; |
3514 | case 4: /* smsw */ | |
16286d08 | 3515 | c->dst.bytes = 2; |
52a46617 | 3516 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3517 | break; |
3518 | case 6: /* lmsw */ | |
9928ff60 | 3519 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3520 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3521 | c->dst.type = OP_NONE; |
6aa8b732 | 3522 | break; |
6e1e5ffe | 3523 | case 5: /* not defined */ |
54b8486f | 3524 | emulate_ud(ctxt); |
da9cb575 | 3525 | rc = X86EMUL_PROPAGATE_FAULT; |
6e1e5ffe | 3526 | goto done; |
6aa8b732 | 3527 | case 7: /* invlpg*/ |
90de84f5 AK |
3528 | emulate_invlpg(ctxt->vcpu, |
3529 | linear(ctxt, c->src.addr.mem)); | |
16286d08 AK |
3530 | /* Disable writeback. */ |
3531 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3532 | break; |
3533 | default: | |
3534 | goto cannot_emulate; | |
3535 | } | |
3536 | break; | |
e99f0507 | 3537 | case 0x05: /* syscall */ |
3fb1b5db | 3538 | rc = emulate_syscall(ctxt, ops); |
e99f0507 | 3539 | break; |
018a98db AK |
3540 | case 0x06: |
3541 | emulate_clts(ctxt->vcpu); | |
018a98db | 3542 | break; |
018a98db | 3543 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3544 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3545 | break; |
3546 | case 0x08: /* invd */ | |
018a98db AK |
3547 | case 0x0d: /* GrpP (prefetch) */ |
3548 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3549 | break; |
3550 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3551 | switch (c->modrm_reg) { |
3552 | case 1: | |
3553 | case 5 ... 7: | |
3554 | case 9 ... 15: | |
54b8486f | 3555 | emulate_ud(ctxt); |
da9cb575 | 3556 | rc = X86EMUL_PROPAGATE_FAULT; |
6aebfa6e GN |
3557 | goto done; |
3558 | } | |
1a0c7d44 | 3559 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3560 | break; |
6aa8b732 | 3561 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3562 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3563 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3564 | emulate_ud(ctxt); |
da9cb575 | 3565 | rc = X86EMUL_PROPAGATE_FAULT; |
1e470be5 GN |
3566 | goto done; |
3567 | } | |
b27f3856 | 3568 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3569 | break; |
018a98db | 3570 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3571 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3572 | emulate_gp(ctxt, 0); |
da9cb575 | 3573 | rc = X86EMUL_PROPAGATE_FAULT; |
0f12244f GN |
3574 | goto done; |
3575 | } | |
018a98db AK |
3576 | c->dst.type = OP_NONE; |
3577 | break; | |
6aa8b732 | 3578 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3579 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3580 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3581 | emulate_ud(ctxt); |
da9cb575 | 3582 | rc = X86EMUL_PROPAGATE_FAULT; |
1e470be5 GN |
3583 | goto done; |
3584 | } | |
35aa5375 | 3585 | |
b27f3856 | 3586 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3587 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3588 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3589 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3590 | emulate_gp(ctxt, 0); |
da9cb575 | 3591 | rc = X86EMUL_PROPAGATE_FAULT; |
338dbc97 GN |
3592 | goto done; |
3593 | } | |
3594 | ||
a01af5ec | 3595 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3596 | break; |
018a98db AK |
3597 | case 0x30: |
3598 | /* wrmsr */ | |
3599 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3600 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3601 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3602 | emulate_gp(ctxt, 0); |
da9cb575 | 3603 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 3604 | goto done; |
018a98db AK |
3605 | } |
3606 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3607 | break; |
3608 | case 0x32: | |
3609 | /* rdmsr */ | |
3fb1b5db | 3610 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3611 | emulate_gp(ctxt, 0); |
da9cb575 | 3612 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 3613 | goto done; |
018a98db AK |
3614 | } else { |
3615 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3616 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3617 | } | |
3618 | rc = X86EMUL_CONTINUE; | |
018a98db | 3619 | break; |
e99f0507 | 3620 | case 0x34: /* sysenter */ |
3fb1b5db | 3621 | rc = emulate_sysenter(ctxt, ops); |
e99f0507 AP |
3622 | break; |
3623 | case 0x35: /* sysexit */ | |
3fb1b5db | 3624 | rc = emulate_sysexit(ctxt, ops); |
e99f0507 | 3625 | break; |
6aa8b732 | 3626 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3627 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3628 | if (!test_cc(c->b, ctxt->eflags)) |
3629 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3630 | break; |
b2833e3c | 3631 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3632 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3633 | jmp_rel(c, c->src.val); |
018a98db | 3634 | break; |
ee45b58e WY |
3635 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
3636 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
3637 | break; | |
0934ac9d | 3638 | case 0xa0: /* push fs */ |
79168fd1 | 3639 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3640 | break; |
3641 | case 0xa1: /* pop fs */ | |
3642 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
0934ac9d | 3643 | break; |
7de75248 NK |
3644 | case 0xa3: |
3645 | bt: /* bt */ | |
e4f8e039 | 3646 | c->dst.type = OP_NONE; |
e4e03ded LV |
3647 | /* only subword offset */ |
3648 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3649 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3650 | break; |
9bf8ea42 GT |
3651 | case 0xa4: /* shld imm8, r, r/m */ |
3652 | case 0xa5: /* shld cl, r, r/m */ | |
3653 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3654 | break; | |
0934ac9d | 3655 | case 0xa8: /* push gs */ |
79168fd1 | 3656 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3657 | break; |
3658 | case 0xa9: /* pop gs */ | |
3659 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
0934ac9d | 3660 | break; |
7de75248 NK |
3661 | case 0xab: |
3662 | bts: /* bts */ | |
05f086f8 | 3663 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3664 | break; |
9bf8ea42 GT |
3665 | case 0xac: /* shrd imm8, r, r/m */ |
3666 | case 0xad: /* shrd cl, r, r/m */ | |
3667 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3668 | break; | |
2a7c5b8b GC |
3669 | case 0xae: /* clflush */ |
3670 | break; | |
6aa8b732 AK |
3671 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3672 | /* | |
3673 | * Save real source value, then compare EAX against | |
3674 | * destination. | |
3675 | */ | |
e4e03ded LV |
3676 | c->src.orig_val = c->src.val; |
3677 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3678 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3679 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3680 | /* Success: write back to memory. */ |
e4e03ded | 3681 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3682 | } else { |
3683 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3684 | c->dst.type = OP_REG; |
1a6440ae | 3685 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3686 | } |
3687 | break; | |
09b5f4d3 WY |
3688 | case 0xb2: /* lss */ |
3689 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS); | |
09b5f4d3 | 3690 | break; |
6aa8b732 AK |
3691 | case 0xb3: |
3692 | btr: /* btr */ | |
05f086f8 | 3693 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3694 | break; |
09b5f4d3 WY |
3695 | case 0xb4: /* lfs */ |
3696 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS); | |
09b5f4d3 WY |
3697 | break; |
3698 | case 0xb5: /* lgs */ | |
3699 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS); | |
09b5f4d3 | 3700 | break; |
6aa8b732 | 3701 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3702 | c->dst.bytes = c->op_bytes; |
3703 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3704 | : (u16) c->src.val; | |
6aa8b732 | 3705 | break; |
6aa8b732 | 3706 | case 0xba: /* Grp8 */ |
e4e03ded | 3707 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3708 | case 0: |
3709 | goto bt; | |
3710 | case 1: | |
3711 | goto bts; | |
3712 | case 2: | |
3713 | goto btr; | |
3714 | case 3: | |
3715 | goto btc; | |
3716 | } | |
3717 | break; | |
7de75248 NK |
3718 | case 0xbb: |
3719 | btc: /* btc */ | |
05f086f8 | 3720 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3721 | break; |
d9574a25 WY |
3722 | case 0xbc: { /* bsf */ |
3723 | u8 zf; | |
3724 | __asm__ ("bsf %2, %0; setz %1" | |
3725 | : "=r"(c->dst.val), "=q"(zf) | |
3726 | : "r"(c->src.val)); | |
3727 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3728 | if (zf) { | |
3729 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3730 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3731 | } | |
3732 | break; | |
3733 | } | |
3734 | case 0xbd: { /* bsr */ | |
3735 | u8 zf; | |
3736 | __asm__ ("bsr %2, %0; setz %1" | |
3737 | : "=r"(c->dst.val), "=q"(zf) | |
3738 | : "r"(c->src.val)); | |
3739 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3740 | if (zf) { | |
3741 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3742 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3743 | } | |
3744 | break; | |
3745 | } | |
6aa8b732 | 3746 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3747 | c->dst.bytes = c->op_bytes; |
3748 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3749 | (s16) c->src.val; | |
6aa8b732 | 3750 | break; |
92f738a5 WY |
3751 | case 0xc0 ... 0xc1: /* xadd */ |
3752 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
3753 | /* Write back the register source. */ | |
3754 | c->src.val = c->dst.orig_val; | |
3755 | write_register_operand(&c->src); | |
3756 | break; | |
a012e65a | 3757 | case 0xc3: /* movnti */ |
e4e03ded LV |
3758 | c->dst.bytes = c->op_bytes; |
3759 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3760 | (u64) c->src.val; | |
a012e65a | 3761 | break; |
6aa8b732 | 3762 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3763 | rc = emulate_grp9(ctxt, ops); |
8cdbd2c9 | 3764 | break; |
91269b8f AK |
3765 | default: |
3766 | goto cannot_emulate; | |
6aa8b732 | 3767 | } |
7d9ddaed AK |
3768 | |
3769 | if (rc != X86EMUL_CONTINUE) | |
3770 | goto done; | |
3771 | ||
6aa8b732 AK |
3772 | goto writeback; |
3773 | ||
3774 | cannot_emulate: | |
6aa8b732 AK |
3775 | return -1; |
3776 | } |