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KVM: VMX: Ensure that vmx_create_vcpu always returns proper error
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
0d7cdee8 78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
1253791d 79#define Sse (1<<17) /* SSE Vector instruction */
01de8b09 80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
d8769fed 81/* Misc flags */
8ea7d6ae 82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 83#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
7db41eb7 95#define Src2Imm (4<<29)
0dc8d10f 96#define Src2Mask (7<<29)
6aa8b732 97
d0e53325
AK		 98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
83babbca 106
d65b1dee
AK		 107struct opcode {
108 u32 flags;
c4f035c6 109 u8 intercept;
120df890 110 union {
ef65c889 111 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 112 struct opcode *group;
113 struct group_dual *gdual;
0d7cdee8 114 struct gprefix *gprefix;
120df890 115 } u;
d09beabd 116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
0d7cdee8
AK		 124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
6aa8b732 131/* EFLAGS bit definitions. */
d4c6a154
GN		 132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
b1d86143
AP		 136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
d4c6a154
GN		 138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
6aa8b732
AK		 140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
b1d86143 142#define EFLG_IF (1<<9)
d4c6a154 143#define EFLG_TF (1<<8)
6aa8b732
AK		 144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
62bd430e
MG		 150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
6aa8b732
AK		 153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
05b3e0c2 160#if defined(CONFIG_X86_64)
6aa8b732
AK		 161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
6aa8b732
AK		 190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
dda96d8f
AK		 199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
b3b3d25a 205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
fb2c2641 211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 214 } while (0)
6b7ad61f
AK		 215
216
6aa8b732
AK		 217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
b3b3d25a 224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 225 break; \
226 case 4: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 228 break; \
229 case 8: \
b3b3d25a 230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 231 break; \
232 } \
6aa8b732
AK		 233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
6b7ad61f 237 unsigned long _tmp; \
d77c26fc 238 switch ((_dst).bytes) { \
6aa8b732 239 case 1: \
b3b3d25a 240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
d175226a
GT		 264/* Instruction has three operands and one operand is stored in ECX register */
265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
dda96d8f 303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 304 do { \
305 unsigned long _tmp; \
306 \
dda96d8f
AK		 307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
d77c26fc 319 switch ((_dst).bytes) { \
dda96d8f
AK		 320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 324 } \
325 } while (0)
326
3f9f53b0
MG		 327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
f6b3597b
AK		 341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
3f9f53b0
MG		 362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
367 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
368 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
369 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
370 } \
371 } while (0)
372
f6b3597b
AK		 373#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
374 do { \
375 switch((_src).bytes) { \
376 case 1: \
377 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
378 _eflags, "b", _ex); \
379 break; \
380 case 2: \
381 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
382 _eflags, "w", _ex); \
383 break; \
384 case 4: \
385 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
386 _eflags, "l", _ex); \
387 break; \
388 case 8: ON64( \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "q", _ex)); \
391 break; \
392 } \
393 } while (0)
394
6aa8b732
AK		 395/* Fetch next part of the instruction being emulated. */
396#define insn_fetch(_type, _size, _eip) \
397({ unsigned long _x; \
62266869 398 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 399 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 400 goto done; \
401 (_eip) += (_size); \
402 (_type)_x; \
403})
404
414e6277
GN		 405#define insn_fetch_arr(_arr, _size, _eip) \
406({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
407 if (rc != X86EMUL_CONTINUE) \
408 goto done; \
409 (_eip) += (_size); \
410})
411
8a76d7f2
JR		 412static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415{
416 struct x86_instruction_info info = {
417 .intercept = intercept,
418 .rep_prefix = ctxt->decode.rep_prefix,
419 .modrm_mod = ctxt->decode.modrm_mod,
420 .modrm_reg = ctxt->decode.modrm_reg,
421 .modrm_rm = ctxt->decode.modrm_rm,
422 .src_val = ctxt->decode.src.val64,
423 .src_bytes = ctxt->decode.src.bytes,
424 .dst_bytes = ctxt->decode.dst.bytes,
425 .ad_bytes = ctxt->decode.ad_bytes,
426 .next_rip = ctxt->eip,
427 };
428
429 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
430}
431
ddcb2885
HH		 432static inline unsigned long ad_mask(struct decode_cache *c)
433{
434 return (1UL << (c->ad_bytes << 3)) - 1;
435}
436
6aa8b732 437/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 438static inline unsigned long
439address_mask(struct decode_cache *c, unsigned long reg)
440{
441 if (c->ad_bytes == sizeof(unsigned long))
442 return reg;
443 else
444 return reg & ad_mask(c);
445}
446
447static inline unsigned long
90de84f5 448register_address(struct decode_cache *c, unsigned long reg)
e4706772 449{
90de84f5 450 return address_mask(c, reg);
e4706772
HH		 451}
452
7a957275
HH		 453static inline void
454register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
455{
456 if (c->ad_bytes == sizeof(unsigned long))
457 *reg += inc;
458 else
459 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
460}
6aa8b732 461
7a957275
HH		 462static inline void jmp_rel(struct decode_cache *c, int rel)
463{
464 register_address_increment(c, &c->eip, rel);
465}
098c937b 466
56697687
AK		 467static u32 desc_limit_scaled(struct desc_struct *desc)
468{
469 u32 limit = get_desc_limit(desc);
470
471 return desc->g ? (limit << 12) | 0xfff : limit;
472}
473
7a5b56df
AK		 474static void set_seg_override(struct decode_cache *c, int seg)
475{
476 c->has_seg_override = true;
477 c->seg_override = seg;
478}
479
79168fd1
GN		 480static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
481 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 482{
483 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
484 return 0;
485
79168fd1 486 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 487}
488
90de84f5
AK		 489static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
490 struct x86_emulate_ops *ops,
491 struct decode_cache *c)
7a5b56df
AK		 492{
493 if (!c->has_seg_override)
494 return 0;
495
90de84f5 496 return c->seg_override;
7a5b56df
AK		 497}
498
35d3d4a1
AK		 499static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
500 u32 error, bool valid)
54b8486f 501{
da9cb575
AK		 502 ctxt->exception.vector = vec;
503 ctxt->exception.error_code = error;
504 ctxt->exception.error_code_valid = valid;
35d3d4a1 505 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 506}
507
3b88e41a
JR		 508static int emulate_db(struct x86_emulate_ctxt *ctxt)
509{
510 return emulate_exception(ctxt, DB_VECTOR, 0, false);
511}
512
35d3d4a1 513static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 514{
35d3d4a1 515 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 516}
517
618ff15d
AK		 518static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
519{
520 return emulate_exception(ctxt, SS_VECTOR, err, true);
521}
522
35d3d4a1 523static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 524{
35d3d4a1 525 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 526}
527
35d3d4a1 528static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 529{
35d3d4a1 530 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 531}
532
34d1f490
AK		 533static int emulate_de(struct x86_emulate_ctxt *ctxt)
534{
35d3d4a1 535 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 536}
537
1253791d
AK		 538static int emulate_nm(struct x86_emulate_ctxt *ctxt)
539{
540 return emulate_exception(ctxt, NM_VECTOR, 0, false);
541}
542
52fd8b44
AK		 543static int linearize(struct x86_emulate_ctxt *ctxt,
544 struct segmented_address addr,
545 unsigned size, bool write,
546 ulong *linear)
547{
548 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 549 struct desc_struct desc;
550 bool usable;
52fd8b44 551 ulong la;
618ff15d
AK		 552 u32 lim;
553 unsigned cpl, rpl;
52fd8b44
AK		 554
555 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 556 switch (ctxt->mode) {
557 case X86EMUL_MODE_REAL:
558 break;
559 case X86EMUL_MODE_PROT64:
560 if (((signed long)la << 16) >> 16 != la)
561 return emulate_gp(ctxt, 0);
562 break;
563 default:
564 usable = ctxt->ops->get_cached_descriptor(&desc, NULL, addr.seg,
565 ctxt->vcpu);
566 if (!usable)
567 goto bad;
568 /* code segment or read-only data segment */
569 if (((desc.type & 8) || !(desc.type & 2)) && write)
570 goto bad;
571 /* unreadable code segment */
572 if ((desc.type & 8) && !(desc.type & 2))
573 goto bad;
574 lim = desc_limit_scaled(&desc);
575 if ((desc.type & 8) || !(desc.type & 4)) {
576 /* expand-up segment */
577 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
578 goto bad;
579 } else {
580 /* exapand-down segment */
581 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
582 goto bad;
583 lim = desc.d ? 0xffffffff : 0xffff;
584 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
585 goto bad;
586 }
587 cpl = ctxt->ops->cpl(ctxt->vcpu);
588 rpl = ctxt->ops->get_segment_selector(addr.seg, ctxt->vcpu) & 3;
589 cpl = max(cpl, rpl);
590 if (!(desc.type & 8)) {
591 /* data segment */
592 if (cpl > desc.dpl)
593 goto bad;
594 } else if ((desc.type & 8) && !(desc.type & 4)) {
595 /* nonconforming code segment */
596 if (cpl != desc.dpl)
597 goto bad;
598 } else if ((desc.type & 8) && (desc.type & 4)) {
599 /* conforming code segment */
600 if (cpl < desc.dpl)
601 goto bad;
602 }
603 break;
604 }
52fd8b44
AK		 605 if (c->ad_bytes != 8)
606 la &= (u32)-1;
607 *linear = la;
608 return X86EMUL_CONTINUE;
618ff15d
AK		 609bad:
610 if (addr.seg == VCPU_SREG_SS)
611 return emulate_ss(ctxt, addr.seg);
612 else
613 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 614}
615
3ca3ac4d
AK		 616static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
617 struct segmented_address addr,
618 void *data,
619 unsigned size)
620{
9fa088f4
AK		 621 int rc;
622 ulong linear;
623
83b8795a 624 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 625 if (rc != X86EMUL_CONTINUE)
626 return rc;
627 return ctxt->ops->read_std(linear, data, size, ctxt->vcpu,
3ca3ac4d
AK		 628 &ctxt->exception);
629}
630
62266869
AK		 631static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
2fb53ad8 633 unsigned long eip, u8 *dest)
62266869
AK		 634{
635 struct fetch_cache *fc = &ctxt->decode.fetch;
636 int rc;
2fb53ad8 637 int size, cur_size;
62266869 638
2fb53ad8
AK		 639 if (eip == fc->end) {
640 cur_size = fc->end - fc->start;
641 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
642 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 643 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 644 if (rc != X86EMUL_CONTINUE)
62266869 645 return rc;
2fb53ad8 646 fc->end += size;
62266869 647 }
2fb53ad8 648 *dest = fc->data[eip - fc->start];
3e2815e9 649 return X86EMUL_CONTINUE;
62266869
AK		 650}
651
652static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops,
654 unsigned long eip, void *dest, unsigned size)
655{
3e2815e9 656 int rc;
62266869 657
eb3c79e6 658 /* x86 instructions are limited to 15 bytes. */
063db061 659 if (eip + size - ctxt->eip > 15)
eb3c79e6 660 return X86EMUL_UNHANDLEABLE;
62266869
AK		 661 while (size--) {
662 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 663 if (rc != X86EMUL_CONTINUE)
62266869
AK		 664 return rc;
665 }
3e2815e9 666 return X86EMUL_CONTINUE;
62266869
AK		 667}
668
1e3c5cb0
RR		 669/*
670 * Given the 'reg' portion of a ModRM byte, and a register block, return a
671 * pointer into the block that addresses the relevant register.
672 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
673 */
674static void *decode_register(u8 modrm_reg, unsigned long *regs,
675 int highbyte_regs)
6aa8b732
AK		 676{
677 void *p;
678
679 p = &regs[modrm_reg];
680 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
681 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
682 return p;
683}
684
685static int read_descriptor(struct x86_emulate_ctxt *ctxt,
686 struct x86_emulate_ops *ops,
90de84f5 687 struct segmented_address addr,
6aa8b732
AK		 688 u16 *size, unsigned long *address, int op_bytes)
689{
690 int rc;
691
692 if (op_bytes == 2)
693 op_bytes = 3;
694 *address = 0;
3ca3ac4d 695 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 696 if (rc != X86EMUL_CONTINUE)
6aa8b732 697 return rc;
30b31ab6 698 addr.ea += 2;
3ca3ac4d 699 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 700 return rc;
701}
702
bbe9abbd
NK		 703static int test_cc(unsigned int condition, unsigned int flags)
704{
705 int rc = 0;
706
707 switch ((condition & 15) >> 1) {
708 case 0: /* o */
709 rc |= (flags & EFLG_OF);
710 break;
711 case 1: /* b/c/nae */
712 rc |= (flags & EFLG_CF);
713 break;
714 case 2: /* z/e */
715 rc |= (flags & EFLG_ZF);
716 break;
717 case 3: /* be/na */
718 rc |= (flags & (EFLG_CF|EFLG_ZF));
719 break;
720 case 4: /* s */
721 rc |= (flags & EFLG_SF);
722 break;
723 case 5: /* p/pe */
724 rc |= (flags & EFLG_PF);
725 break;
726 case 7: /* le/ng */
727 rc |= (flags & EFLG_ZF);
728 /* fall through */
729 case 6: /* l/nge */
730 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
731 break;
732 }
733
734 /* Odd condition identifiers (lsb == 1) have inverted sense. */
735 return (!!rc ^ (condition & 1));
736}
737
91ff3cb4
AK		 738static void fetch_register_operand(struct operand *op)
739{
740 switch (op->bytes) {
741 case 1:
742 op->val = *(u8 *)op->addr.reg;
743 break;
744 case 2:
745 op->val = *(u16 *)op->addr.reg;
746 break;
747 case 4:
748 op->val = *(u32 *)op->addr.reg;
749 break;
750 case 8:
751 op->val = *(u64 *)op->addr.reg;
752 break;
753 }
754}
755
1253791d
AK		 756static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
757{
758 ctxt->ops->get_fpu(ctxt);
759 switch (reg) {
760 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
761 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
762 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
763 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
764 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
765 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
766 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
767 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
768#ifdef CONFIG_X86_64
769 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
770 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
771 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
772 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
773 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
774 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
775 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
776 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
777#endif
778 default: BUG();
779 }
780 ctxt->ops->put_fpu(ctxt);
781}
782
783static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
784 int reg)
785{
786 ctxt->ops->get_fpu(ctxt);
787 switch (reg) {
788 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
789 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
790 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
791 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
792 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
793 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
794 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
795 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
796#ifdef CONFIG_X86_64
797 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
798 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
799 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
800 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
801 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
802 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
803 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
804 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
805#endif
806 default: BUG();
807 }
808 ctxt->ops->put_fpu(ctxt);
809}
810
811static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
812 struct operand *op,
3c118e24 813 struct decode_cache *c,
3c118e24
AK		 814 int inhibit_bytereg)
815{
33615aa9 816 unsigned reg = c->modrm_reg;
9f1ef3f8 817 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 818
819 if (!(c->d & ModRM))
820 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 821
822 if (c->d & Sse) {
823 op->type = OP_XMM;
824 op->bytes = 16;
825 op->addr.xmm = reg;
826 read_sse_reg(ctxt, &op->vec_val, reg);
827 return;
828 }
829
3c118e24
AK		 830 op->type = OP_REG;
831 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 832 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 833 op->bytes = 1;
834 } else {
1a6440ae 835 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 836 op->bytes = c->op_bytes;
3c118e24 837 }
91ff3cb4 838 fetch_register_operand(op);
3c118e24
AK		 839 op->orig_val = op->val;
840}
841
1c73ef66 842static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 843 struct x86_emulate_ops *ops,
844 struct operand *op)
1c73ef66
AK		 845{
846 struct decode_cache *c = &ctxt->decode;
847 u8 sib;
f5b4edcd 848 int index_reg = 0, base_reg = 0, scale;
3e2815e9 849 int rc = X86EMUL_CONTINUE;
2dbd0dd7 850 ulong modrm_ea = 0;
1c73ef66
AK		 851
852 if (c->rex_prefix) {
853 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
854 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
855 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
856 }
857
858 c->modrm = insn_fetch(u8, 1, c->eip);
859 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
860 c->modrm_reg |= (c->modrm & 0x38) >> 3;
861 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 862 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 863
864 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 865 op->type = OP_REG;
866 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
867 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 868 c->regs, c->d & ByteOp);
1253791d
AK		 869 if (c->d & Sse) {
870 op->type = OP_XMM;
871 op->bytes = 16;
872 op->addr.xmm = c->modrm_rm;
873 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
874 return rc;
875 }
2dbd0dd7 876 fetch_register_operand(op);
1c73ef66
AK		 877 return rc;
878 }
879
2dbd0dd7
AK		 880 op->type = OP_MEM;
881
1c73ef66
AK		 882 if (c->ad_bytes == 2) {
883 unsigned bx = c->regs[VCPU_REGS_RBX];
884 unsigned bp = c->regs[VCPU_REGS_RBP];
885 unsigned si = c->regs[VCPU_REGS_RSI];
886 unsigned di = c->regs[VCPU_REGS_RDI];
887
888 /* 16-bit ModR/M decode. */
889 switch (c->modrm_mod) {
890 case 0:
891 if (c->modrm_rm == 6)
2dbd0dd7 892 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 893 break;
894 case 1:
2dbd0dd7 895 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 896 break;
897 case 2:
2dbd0dd7 898 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 899 break;
900 }
901 switch (c->modrm_rm) {
902 case 0:
2dbd0dd7 903 modrm_ea += bx + si;
1c73ef66
AK		 904 break;
905 case 1:
2dbd0dd7 906 modrm_ea += bx + di;
1c73ef66
AK		 907 break;
908 case 2:
2dbd0dd7 909 modrm_ea += bp + si;
1c73ef66
AK		 910 break;
911 case 3:
2dbd0dd7 912 modrm_ea += bp + di;
1c73ef66
AK		 913 break;
914 case 4:
2dbd0dd7 915 modrm_ea += si;
1c73ef66
AK		 916 break;
917 case 5:
2dbd0dd7 918 modrm_ea += di;
1c73ef66
AK		 919 break;
920 case 6:
921 if (c->modrm_mod != 0)
2dbd0dd7 922 modrm_ea += bp;
1c73ef66
AK		 923 break;
924 case 7:
2dbd0dd7 925 modrm_ea += bx;
1c73ef66
AK		 926 break;
927 }
928 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
929 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 930 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 931 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 932 } else {
933 /* 32/64-bit ModR/M decode. */
84411d85 934 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 935 sib = insn_fetch(u8, 1, c->eip);
936 index_reg |= (sib >> 3) & 7;
937 base_reg |= sib & 7;
938 scale = sib >> 6;
939
dc71d0f1 940 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 941 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 942 else
2dbd0dd7 943 modrm_ea += c->regs[base_reg];
dc71d0f1 944 if (index_reg != 4)
2dbd0dd7 945 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 946 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
947 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 948 c->rip_relative = 1;
84411d85 949 } else
2dbd0dd7 950 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 951 switch (c->modrm_mod) {
952 case 0:
953 if (c->modrm_rm == 5)
2dbd0dd7 954 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 955 break;
956 case 1:
2dbd0dd7 957 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 958 break;
959 case 2:
2dbd0dd7 960 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 961 break;
962 }
963 }
90de84f5 964 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 965done:
966 return rc;
967}
968
969static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 970 struct x86_emulate_ops *ops,
971 struct operand *op)
1c73ef66
AK		 972{
973 struct decode_cache *c = &ctxt->decode;
3e2815e9 974 int rc = X86EMUL_CONTINUE;
1c73ef66 975
2dbd0dd7 976 op->type = OP_MEM;
1c73ef66
AK		 977 switch (c->ad_bytes) {
978 case 2:
90de84f5 979 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 980 break;
981 case 4:
90de84f5 982 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 983 break;
984 case 8:
90de84f5 985 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 986 break;
987 }
988done:
989 return rc;
990}
991
35c843c4
WY		 992static void fetch_bit_operand(struct decode_cache *c)
993{
7129eeca 994 long sv = 0, mask;
35c843c4 995
3885f18f 996 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 997 mask = ~(c->dst.bytes * 8 - 1);
998
999 if (c->src.bytes == 2)
1000 sv = (s16)c->src.val & (s16)mask;
1001 else if (c->src.bytes == 4)
1002 sv = (s32)c->src.val & (s32)mask;
1003
90de84f5 1004 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1005 }
ba7ff2b7
WY		 1006
1007 /* only subword offset */
1008 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1009}
1010
dde7e6d1
AK		 1011static int read_emulated(struct x86_emulate_ctxt *ctxt,
1012 struct x86_emulate_ops *ops,
1013 unsigned long addr, void *dest, unsigned size)
6aa8b732 1014{
dde7e6d1
AK		 1015 int rc;
1016 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1017
dde7e6d1
AK		 1018 while (size) {
1019 int n = min(size, 8u);
1020 size -= n;
1021 if (mc->pos < mc->end)
1022 goto read_cached;
5cd21917 1023
bcc55cba
AK		 1024 rc = ops->read_emulated(addr, mc->data + mc->end, n,
1025 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 1026 if (rc != X86EMUL_CONTINUE)
1027 return rc;
1028 mc->end += n;
6aa8b732 1029
dde7e6d1
AK		 1030 read_cached:
1031 memcpy(dest, mc->data + mc->pos, n);
1032 mc->pos += n;
1033 dest += n;
1034 addr += n;
6aa8b732 1035 }
dde7e6d1
AK		 1036 return X86EMUL_CONTINUE;
1037}
6aa8b732 1038
3ca3ac4d
AK		 1039static int segmented_read(struct x86_emulate_ctxt *ctxt,
1040 struct segmented_address addr,
1041 void *data,
1042 unsigned size)
1043{
9fa088f4
AK		 1044 int rc;
1045 ulong linear;
1046
83b8795a 1047 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1048 if (rc != X86EMUL_CONTINUE)
1049 return rc;
1050 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1051}
1052
1053static int segmented_write(struct x86_emulate_ctxt *ctxt,
1054 struct segmented_address addr,
1055 const void *data,
1056 unsigned size)
1057{
9fa088f4
AK		 1058 int rc;
1059 ulong linear;
1060
83b8795a 1061 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1062 if (rc != X86EMUL_CONTINUE)
1063 return rc;
1064 return ctxt->ops->write_emulated(linear, data, size,
3ca3ac4d
AK		 1065 &ctxt->exception, ctxt->vcpu);
1066}
1067
1068static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1069 struct segmented_address addr,
1070 const void *orig_data, const void *data,
1071 unsigned size)
1072{
9fa088f4
AK		 1073 int rc;
1074 ulong linear;
1075
83b8795a 1076 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1077 if (rc != X86EMUL_CONTINUE)
1078 return rc;
1079 return ctxt->ops->cmpxchg_emulated(linear, orig_data, data,
3ca3ac4d
AK		 1080 size, &ctxt->exception, ctxt->vcpu);
1081}
1082
dde7e6d1
AK		 1083static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1084 struct x86_emulate_ops *ops,
1085 unsigned int size, unsigned short port,
1086 void *dest)
1087{
1088 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1089
dde7e6d1
AK		 1090 if (rc->pos == rc->end) { /* refill pio read ahead */
1091 struct decode_cache *c = &ctxt->decode;
1092 unsigned int in_page, n;
1093 unsigned int count = c->rep_prefix ?
1094 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1095 in_page = (ctxt->eflags & EFLG_DF) ?
1096 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1097 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1098 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1099 count);
1100 if (n == 0)
1101 n = 1;
1102 rc->pos = rc->end = 0;
1103 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1104 return 0;
1105 rc->end = n * size;
6aa8b732
AK		 1106 }
1107
dde7e6d1
AK		 1108 memcpy(dest, rc->data + rc->pos, size);
1109 rc->pos += size;
1110 return 1;
1111}
6aa8b732 1112
dde7e6d1
AK		 1113static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1114 struct x86_emulate_ops *ops,
1115 u16 selector, struct desc_ptr *dt)
1116{
1117 if (selector & 1 << 2) {
1118 struct desc_struct desc;
1119 memset (dt, 0, sizeof *dt);
5601d05b
GN		 1120 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
1121 ctxt->vcpu))
dde7e6d1 1122 return;
e09d082c 1123
dde7e6d1
AK		 1124 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1125 dt->address = get_desc_base(&desc);
1126 } else
1127 ops->get_gdt(dt, ctxt->vcpu);
1128}
120df890 1129
dde7e6d1
AK		 1130/* allowed just for 8 bytes segments */
1131static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1132 struct x86_emulate_ops *ops,
1133 u16 selector, struct desc_struct *desc)
1134{
1135 struct desc_ptr dt;
1136 u16 index = selector >> 3;
1137 int ret;
dde7e6d1 1138 ulong addr;
120df890 1139
dde7e6d1 1140 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1141
35d3d4a1
AK		 1142 if (dt.size < index * 8 + 7)
1143 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1144 addr = dt.address + index * 8;
bcc55cba
AK		 1145 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1146 &ctxt->exception);
e09d082c 1147
dde7e6d1
AK		 1148 return ret;
1149}
ef65c889 1150
dde7e6d1
AK		 1151/* allowed just for 8 bytes segments */
1152static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1153 struct x86_emulate_ops *ops,
1154 u16 selector, struct desc_struct *desc)
1155{
1156 struct desc_ptr dt;
1157 u16 index = selector >> 3;
dde7e6d1
AK		 1158 ulong addr;
1159 int ret;
6aa8b732 1160
dde7e6d1 1161 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1162
35d3d4a1
AK		 1163 if (dt.size < index * 8 + 7)
1164 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1165
dde7e6d1 1166 addr = dt.address + index * 8;
bcc55cba
AK		 1167 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1168 &ctxt->exception);
c7e75a3d 1169
dde7e6d1
AK		 1170 return ret;
1171}
c7e75a3d 1172
5601d05b 1173/* Does not support long mode */
dde7e6d1
AK		 1174static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1175 struct x86_emulate_ops *ops,
1176 u16 selector, int seg)
1177{
1178 struct desc_struct seg_desc;
1179 u8 dpl, rpl, cpl;
1180 unsigned err_vec = GP_VECTOR;
1181 u32 err_code = 0;
1182 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1183 int ret;
69f55cb1 1184
dde7e6d1 1185 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1186
dde7e6d1
AK		 1187 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1188 || ctxt->mode == X86EMUL_MODE_REAL) {
1189 /* set real mode segment descriptor */
1190 set_desc_base(&seg_desc, selector << 4);
1191 set_desc_limit(&seg_desc, 0xffff);
1192 seg_desc.type = 3;
1193 seg_desc.p = 1;
1194 seg_desc.s = 1;
1195 goto load;
1196 }
1197
1198 /* NULL selector is not valid for TR, CS and SS */
1199 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1200 && null_selector)
1201 goto exception;
1202
1203 /* TR should be in GDT only */
1204 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1205 goto exception;
1206
1207 if (null_selector) /* for NULL selector skip all following checks */
1208 goto load;
1209
1210 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1211 if (ret != X86EMUL_CONTINUE)
1212 return ret;
1213
1214 err_code = selector & 0xfffc;
1215 err_vec = GP_VECTOR;
1216
1217 /* can't load system descriptor into segment selecor */
1218 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1219 goto exception;
1220
1221 if (!seg_desc.p) {
1222 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1223 goto exception;
1224 }
1225
1226 rpl = selector & 3;
1227 dpl = seg_desc.dpl;
1228 cpl = ops->cpl(ctxt->vcpu);
1229
1230 switch (seg) {
1231 case VCPU_SREG_SS:
1232 /*
1233 * segment is not a writable data segment or segment
1234 * selector's RPL != CPL or segment selector's RPL != CPL
1235 */
1236 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1237 goto exception;
6aa8b732 1238 break;
dde7e6d1
AK		 1239 case VCPU_SREG_CS:
1240 if (!(seg_desc.type & 8))
1241 goto exception;
1242
1243 if (seg_desc.type & 4) {
1244 /* conforming */
1245 if (dpl > cpl)
1246 goto exception;
1247 } else {
1248 /* nonconforming */
1249 if (rpl > cpl || dpl != cpl)
1250 goto exception;
1251 }
1252 /* CS(RPL) <- CPL */
1253 selector = (selector & 0xfffc) | cpl;
6aa8b732 1254 break;
dde7e6d1
AK		 1255 case VCPU_SREG_TR:
1256 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1257 goto exception;
1258 break;
1259 case VCPU_SREG_LDTR:
1260 if (seg_desc.s || seg_desc.type != 2)
1261 goto exception;
1262 break;
1263 default: /* DS, ES, FS, or GS */
4e62417b 1264 /*
dde7e6d1
AK		 1265 * segment is not a data or readable code segment or
1266 * ((segment is a data or nonconforming code segment)
1267 * and (both RPL and CPL > DPL))
4e62417b 1268 */
dde7e6d1
AK		 1269 if ((seg_desc.type & 0xa) == 0x8 ||
1270 (((seg_desc.type & 0xc) != 0xc) &&
1271 (rpl > dpl && cpl > dpl)))
1272 goto exception;
6aa8b732 1273 break;
dde7e6d1
AK		 1274 }
1275
1276 if (seg_desc.s) {
1277 /* mark segment as accessed */
1278 seg_desc.type |= 1;
1279 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1280 if (ret != X86EMUL_CONTINUE)
1281 return ret;
1282 }
1283load:
1284 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1285 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1286 return X86EMUL_CONTINUE;
1287exception:
1288 emulate_exception(ctxt, err_vec, err_code, true);
1289 return X86EMUL_PROPAGATE_FAULT;
1290}
1291
31be40b3
WY		 1292static void write_register_operand(struct operand *op)
1293{
1294 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1295 switch (op->bytes) {
1296 case 1:
1297 *(u8 *)op->addr.reg = (u8)op->val;
1298 break;
1299 case 2:
1300 *(u16 *)op->addr.reg = (u16)op->val;
1301 break;
1302 case 4:
1303 *op->addr.reg = (u32)op->val;
1304 break; /* 64b: zero-extend */
1305 case 8:
1306 *op->addr.reg = op->val;
1307 break;
1308 }
1309}
1310
dde7e6d1
AK		 1311static inline int writeback(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops)
1313{
1314 int rc;
1315 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1316
1317 switch (c->dst.type) {
1318 case OP_REG:
31be40b3 1319 write_register_operand(&c->dst);
6aa8b732 1320 break;
dde7e6d1
AK		 1321 case OP_MEM:
1322 if (c->lock_prefix)
3ca3ac4d
AK		 1323 rc = segmented_cmpxchg(ctxt,
1324 c->dst.addr.mem,
1325 &c->dst.orig_val,
1326 &c->dst.val,
1327 c->dst.bytes);
341de7e3 1328 else
3ca3ac4d
AK		 1329 rc = segmented_write(ctxt,
1330 c->dst.addr.mem,
1331 &c->dst.val,
1332 c->dst.bytes);
dde7e6d1
AK		 1333 if (rc != X86EMUL_CONTINUE)
1334 return rc;
a682e354 1335 break;
1253791d
AK		 1336 case OP_XMM:
1337 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1338 break;
dde7e6d1
AK		 1339 case OP_NONE:
1340 /* no writeback */
414e6277 1341 break;
dde7e6d1 1342 default:
414e6277 1343 break;
6aa8b732 1344 }
dde7e6d1
AK		 1345 return X86EMUL_CONTINUE;
1346}
6aa8b732 1347
dde7e6d1
AK		 1348static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1349 struct x86_emulate_ops *ops)
1350{
1351 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1352
dde7e6d1
AK		 1353 c->dst.type = OP_MEM;
1354 c->dst.bytes = c->op_bytes;
1355 c->dst.val = c->src.val;
1356 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1357 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1358 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1359}
69f55cb1 1360
dde7e6d1
AK		 1361static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1362 struct x86_emulate_ops *ops,
1363 void *dest, int len)
1364{
1365 struct decode_cache *c = &ctxt->decode;
1366 int rc;
90de84f5 1367 struct segmented_address addr;
8b4caf66 1368
90de84f5
AK		 1369 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1370 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1371 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1372 if (rc != X86EMUL_CONTINUE)
1373 return rc;
1374
1375 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1376 return rc;
8b4caf66
LV		 1377}
1378
dde7e6d1
AK		 1379static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1380 struct x86_emulate_ops *ops,
1381 void *dest, int len)
9de41573
GN		 1382{
1383 int rc;
dde7e6d1
AK		 1384 unsigned long val, change_mask;
1385 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1386 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1387
dde7e6d1
AK		 1388 rc = emulate_pop(ctxt, ops, &val, len);
1389 if (rc != X86EMUL_CONTINUE)
1390 return rc;
9de41573 1391
dde7e6d1
AK		 1392 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1393 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1394
dde7e6d1
AK		 1395 switch(ctxt->mode) {
1396 case X86EMUL_MODE_PROT64:
1397 case X86EMUL_MODE_PROT32:
1398 case X86EMUL_MODE_PROT16:
1399 if (cpl == 0)
1400 change_mask |= EFLG_IOPL;
1401 if (cpl <= iopl)
1402 change_mask |= EFLG_IF;
1403 break;
1404 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1405 if (iopl < 3)
1406 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1407 change_mask |= EFLG_IF;
1408 break;
1409 default: /* real mode */
1410 change_mask |= (EFLG_IOPL | EFLG_IF);
1411 break;
9de41573 1412 }
dde7e6d1
AK		 1413
1414 *(unsigned long *)dest =
1415 (ctxt->eflags & ~change_mask) | (val & change_mask);
1416
1417 return rc;
9de41573
GN		 1418}
1419
dde7e6d1
AK		 1420static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1421 struct x86_emulate_ops *ops, int seg)
7b262e90 1422{
dde7e6d1 1423 struct decode_cache *c = &ctxt->decode;
7b262e90 1424
dde7e6d1 1425 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1426
dde7e6d1 1427 emulate_push(ctxt, ops);
7b262e90
GN		 1428}
1429
dde7e6d1
AK		 1430static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1431 struct x86_emulate_ops *ops, int seg)
38ba30ba 1432{
dde7e6d1
AK		 1433 struct decode_cache *c = &ctxt->decode;
1434 unsigned long selector;
1435 int rc;
38ba30ba 1436
dde7e6d1
AK		 1437 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
1440
1441 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1442 return rc;
38ba30ba
GN		 1443}
1444
dde7e6d1
AK		 1445static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1446 struct x86_emulate_ops *ops)
38ba30ba 1447{
dde7e6d1
AK		 1448 struct decode_cache *c = &ctxt->decode;
1449 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1450 int rc = X86EMUL_CONTINUE;
1451 int reg = VCPU_REGS_RAX;
38ba30ba 1452
dde7e6d1
AK		 1453 while (reg <= VCPU_REGS_RDI) {
1454 (reg == VCPU_REGS_RSP) ?
1455 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1456
dde7e6d1 1457 emulate_push(ctxt, ops);
38ba30ba 1458
dde7e6d1
AK		 1459 rc = writeback(ctxt, ops);
1460 if (rc != X86EMUL_CONTINUE)
1461 return rc;
38ba30ba 1462
dde7e6d1 1463 ++reg;
38ba30ba 1464 }
38ba30ba 1465
dde7e6d1
AK		 1466 /* Disable writeback. */
1467 c->dst.type = OP_NONE;
1468
1469 return rc;
38ba30ba
GN		 1470}
1471
dde7e6d1
AK		 1472static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1473 struct x86_emulate_ops *ops)
38ba30ba 1474{
dde7e6d1
AK		 1475 struct decode_cache *c = &ctxt->decode;
1476 int rc = X86EMUL_CONTINUE;
1477 int reg = VCPU_REGS_RDI;
38ba30ba 1478
dde7e6d1
AK		 1479 while (reg >= VCPU_REGS_RAX) {
1480 if (reg == VCPU_REGS_RSP) {
1481 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1482 c->op_bytes);
1483 --reg;
1484 }
38ba30ba 1485
dde7e6d1
AK		 1486 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1487 if (rc != X86EMUL_CONTINUE)
1488 break;
1489 --reg;
38ba30ba 1490 }
dde7e6d1 1491 return rc;
38ba30ba
GN		 1492}
1493
6e154e56
MG		 1494int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1495 struct x86_emulate_ops *ops, int irq)
1496{
1497 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1498 int rc;
6e154e56
MG		 1499 struct desc_ptr dt;
1500 gva_t cs_addr;
1501 gva_t eip_addr;
1502 u16 cs, eip;
6e154e56
MG		 1503
1504 /* TODO: Add limit checks */
1505 c->src.val = ctxt->eflags;
1506 emulate_push(ctxt, ops);
5c56e1cf
AK		 1507 rc = writeback(ctxt, ops);
1508 if (rc != X86EMUL_CONTINUE)
1509 return rc;
6e154e56
MG		 1510
1511 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1512
1513 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1514 emulate_push(ctxt, ops);
5c56e1cf
AK		 1515 rc = writeback(ctxt, ops);
1516 if (rc != X86EMUL_CONTINUE)
1517 return rc;
6e154e56
MG		 1518
1519 c->src.val = c->eip;
1520 emulate_push(ctxt, ops);
5c56e1cf
AK		 1521 rc = writeback(ctxt, ops);
1522 if (rc != X86EMUL_CONTINUE)
1523 return rc;
1524
1525 c->dst.type = OP_NONE;
6e154e56
MG		 1526
1527 ops->get_idt(&dt, ctxt->vcpu);
1528
1529 eip_addr = dt.address + (irq << 2);
1530 cs_addr = dt.address + (irq << 2) + 2;
1531
bcc55cba 1532 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1533 if (rc != X86EMUL_CONTINUE)
1534 return rc;
1535
bcc55cba 1536 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1537 if (rc != X86EMUL_CONTINUE)
1538 return rc;
1539
1540 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1541 if (rc != X86EMUL_CONTINUE)
1542 return rc;
1543
1544 c->eip = eip;
1545
1546 return rc;
1547}
1548
1549static int emulate_int(struct x86_emulate_ctxt *ctxt,
1550 struct x86_emulate_ops *ops, int irq)
1551{
1552 switch(ctxt->mode) {
1553 case X86EMUL_MODE_REAL:
1554 return emulate_int_real(ctxt, ops, irq);
1555 case X86EMUL_MODE_VM86:
1556 case X86EMUL_MODE_PROT16:
1557 case X86EMUL_MODE_PROT32:
1558 case X86EMUL_MODE_PROT64:
1559 default:
1560 /* Protected mode interrupts unimplemented yet */
1561 return X86EMUL_UNHANDLEABLE;
1562 }
1563}
1564
dde7e6d1
AK		 1565static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1566 struct x86_emulate_ops *ops)
38ba30ba 1567{
dde7e6d1
AK		 1568 struct decode_cache *c = &ctxt->decode;
1569 int rc = X86EMUL_CONTINUE;
1570 unsigned long temp_eip = 0;
1571 unsigned long temp_eflags = 0;
1572 unsigned long cs = 0;
1573 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1574 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1575 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1576 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1577
dde7e6d1 1578 /* TODO: Add stack limit check */
38ba30ba 1579
dde7e6d1 1580 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1581
dde7e6d1
AK		 1582 if (rc != X86EMUL_CONTINUE)
1583 return rc;
38ba30ba 1584
35d3d4a1
AK		 1585 if (temp_eip & ~0xffff)
1586 return emulate_gp(ctxt, 0);
38ba30ba 1587
dde7e6d1 1588 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1589
dde7e6d1
AK		 1590 if (rc != X86EMUL_CONTINUE)
1591 return rc;
38ba30ba 1592
dde7e6d1 1593 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1594
dde7e6d1
AK		 1595 if (rc != X86EMUL_CONTINUE)
1596 return rc;
38ba30ba 1597
dde7e6d1 1598 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1599
dde7e6d1
AK		 1600 if (rc != X86EMUL_CONTINUE)
1601 return rc;
38ba30ba 1602
dde7e6d1 1603 c->eip = temp_eip;
38ba30ba 1604
38ba30ba 1605
dde7e6d1
AK		 1606 if (c->op_bytes == 4)
1607 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1608 else if (c->op_bytes == 2) {
1609 ctxt->eflags &= ~0xffff;
1610 ctxt->eflags |= temp_eflags;
38ba30ba 1611 }
dde7e6d1
AK		 1612
1613 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1614 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1615
1616 return rc;
38ba30ba
GN		 1617}
1618
dde7e6d1
AK		 1619static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1620 struct x86_emulate_ops* ops)
c37eda13 1621{
dde7e6d1
AK		 1622 switch(ctxt->mode) {
1623 case X86EMUL_MODE_REAL:
1624 return emulate_iret_real(ctxt, ops);
1625 case X86EMUL_MODE_VM86:
1626 case X86EMUL_MODE_PROT16:
1627 case X86EMUL_MODE_PROT32:
1628 case X86EMUL_MODE_PROT64:
c37eda13 1629 default:
dde7e6d1
AK		 1630 /* iret from protected mode unimplemented yet */
1631 return X86EMUL_UNHANDLEABLE;
c37eda13 1632 }
c37eda13
WY		 1633}
1634
dde7e6d1 1635static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1636 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1637{
1638 struct decode_cache *c = &ctxt->decode;
1639
dde7e6d1 1640 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1641}
1642
dde7e6d1 1643static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1644{
05f086f8 1645 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1646 switch (c->modrm_reg) {
1647 case 0: /* rol */
05f086f8 1648 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1649 break;
1650 case 1: /* ror */
05f086f8 1651 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1652 break;
1653 case 2: /* rcl */
05f086f8 1654 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1655 break;
1656 case 3: /* rcr */
05f086f8 1657 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1658 break;
1659 case 4: /* sal/shl */
1660 case 6: /* sal/shl */
05f086f8 1661 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1662 break;
1663 case 5: /* shr */
05f086f8 1664 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1665 break;
1666 case 7: /* sar */
05f086f8 1667 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1668 break;
1669 }
1670}
1671
1672static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1673 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1674{
1675 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1676 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1677 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1678 u8 de = 0;
8cdbd2c9
LV		 1679
1680 switch (c->modrm_reg) {
1681 case 0 ... 1: /* test */
05f086f8 1682 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1683 break;
1684 case 2: /* not */
1685 c->dst.val = ~c->dst.val;
1686 break;
1687 case 3: /* neg */
05f086f8 1688 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1689 break;
3f9f53b0
MG		 1690 case 4: /* mul */
1691 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1692 break;
1693 case 5: /* imul */
1694 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1695 break;
1696 case 6: /* div */
34d1f490
AK		 1697 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1698 ctxt->eflags, de);
3f9f53b0
MG		 1699 break;
1700 case 7: /* idiv */
34d1f490
AK		 1701 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1702 ctxt->eflags, de);
3f9f53b0 1703 break;
8cdbd2c9 1704 default:
8c5eee30 1705 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1706 }
34d1f490
AK		 1707 if (de)
1708 return emulate_de(ctxt);
8c5eee30 1709 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1710}
1711
1712static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1713 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1714{
1715 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1716
1717 switch (c->modrm_reg) {
1718 case 0: /* inc */
05f086f8 1719 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1720 break;
1721 case 1: /* dec */
05f086f8 1722 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1723 break;
d19292e4
MG		 1724 case 2: /* call near abs */ {
1725 long int old_eip;
1726 old_eip = c->eip;
1727 c->eip = c->src.val;
1728 c->src.val = old_eip;
79168fd1 1729 emulate_push(ctxt, ops);
d19292e4
MG		 1730 break;
1731 }
8cdbd2c9 1732 case 4: /* jmp abs */
fd60754e 1733 c->eip = c->src.val;
8cdbd2c9
LV		 1734 break;
1735 case 6: /* push */
79168fd1 1736 emulate_push(ctxt, ops);
8cdbd2c9 1737 break;
8cdbd2c9 1738 }
1b30eaa8 1739 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1740}
1741
1742static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1743 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1744{
1745 struct decode_cache *c = &ctxt->decode;
16518d5a 1746 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1747
1748 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1749 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1750 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1751 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1752 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1753 } else {
16518d5a
AK		 1754 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1755 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1756
05f086f8 1757 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1758 }
1b30eaa8 1759 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1760}
1761
a77ab5ea
AK		 1762static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1763 struct x86_emulate_ops *ops)
1764{
1765 struct decode_cache *c = &ctxt->decode;
1766 int rc;
1767 unsigned long cs;
1768
1769 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1770 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1771 return rc;
1772 if (c->op_bytes == 4)
1773 c->eip = (u32)c->eip;
1774 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1775 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1776 return rc;
2e873022 1777 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1778 return rc;
1779}
1780
09b5f4d3
WY		 1781static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1782 struct x86_emulate_ops *ops, int seg)
1783{
1784 struct decode_cache *c = &ctxt->decode;
1785 unsigned short sel;
1786 int rc;
1787
1788 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1789
1790 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1791 if (rc != X86EMUL_CONTINUE)
1792 return rc;
1793
1794 c->dst.val = c->src.val;
1795 return rc;
1796}
1797
e66bb2cc
AP		 1798static inline void
1799setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1800 struct x86_emulate_ops *ops, struct desc_struct *cs,
1801 struct desc_struct *ss)
e66bb2cc 1802{
79168fd1 1803 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1804 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1805 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1806
1807 cs->l = 0; /* will be adjusted later */
79168fd1 1808 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1809 cs->g = 1; /* 4kb granularity */
79168fd1 1810 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1811 cs->type = 0x0b; /* Read, Execute, Accessed */
1812 cs->s = 1;
1813 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1814 cs->p = 1;
1815 cs->d = 1;
e66bb2cc 1816
79168fd1
GN		 1817 set_desc_base(ss, 0); /* flat segment */
1818 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1819 ss->g = 1; /* 4kb granularity */
1820 ss->s = 1;
1821 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1822 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1823 ss->dpl = 0;
79168fd1 1824 ss->p = 1;
e66bb2cc
AP		 1825}
1826
1827static int
3fb1b5db 1828emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1829{
1830 struct decode_cache *c = &ctxt->decode;
79168fd1 1831 struct desc_struct cs, ss;
e66bb2cc 1832 u64 msr_data;
79168fd1 1833 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1834
1835 /* syscall is not available in real mode */
2e901c4c 1836 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1837 ctxt->mode == X86EMUL_MODE_VM86)
1838 return emulate_ud(ctxt);
e66bb2cc 1839
79168fd1 1840 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1841
3fb1b5db 1842 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1843 msr_data >>= 32;
79168fd1
GN		 1844 cs_sel = (u16)(msr_data & 0xfffc);
1845 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1846
1847 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1848 cs.d = 0;
e66bb2cc
AP		 1849 cs.l = 1;
1850 }
5601d05b 1851 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1852 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1853 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1854 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1855
1856 c->regs[VCPU_REGS_RCX] = c->eip;
1857 if (is_long_mode(ctxt->vcpu)) {
1858#ifdef CONFIG_X86_64
1859 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1860
3fb1b5db
GN		 1861 ops->get_msr(ctxt->vcpu,
1862 ctxt->mode == X86EMUL_MODE_PROT64 ?
1863 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1864 c->eip = msr_data;
1865
3fb1b5db 1866 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1867 ctxt->eflags &= ~(msr_data | EFLG_RF);
1868#endif
1869 } else {
1870 /* legacy mode */
3fb1b5db 1871 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1872 c->eip = (u32)msr_data;
1873
1874 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1875 }
1876
e54cfa97 1877 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1878}
1879
8c604352 1880static int
3fb1b5db 1881emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1882{
1883 struct decode_cache *c = &ctxt->decode;
79168fd1 1884 struct desc_struct cs, ss;
8c604352 1885 u64 msr_data;
79168fd1 1886 u16 cs_sel, ss_sel;
8c604352 1887
a0044755 1888 /* inject #GP if in real mode */
35d3d4a1
AK		 1889 if (ctxt->mode == X86EMUL_MODE_REAL)
1890 return emulate_gp(ctxt, 0);
8c604352
AP		 1891
1892 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1893 * Therefore, we inject an #UD.
1894 */
35d3d4a1
AK		 1895 if (ctxt->mode == X86EMUL_MODE_PROT64)
1896 return emulate_ud(ctxt);
8c604352 1897
79168fd1 1898 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1899
3fb1b5db 1900 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1901 switch (ctxt->mode) {
1902 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1903 if ((msr_data & 0xfffc) == 0x0)
1904 return emulate_gp(ctxt, 0);
8c604352
AP		 1905 break;
1906 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1907 if (msr_data == 0x0)
1908 return emulate_gp(ctxt, 0);
8c604352
AP		 1909 break;
1910 }
1911
1912 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1913 cs_sel = (u16)msr_data;
1914 cs_sel &= ~SELECTOR_RPL_MASK;
1915 ss_sel = cs_sel + 8;
1916 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1917 if (ctxt->mode == X86EMUL_MODE_PROT64
1918 || is_long_mode(ctxt->vcpu)) {
79168fd1 1919 cs.d = 0;
8c604352
AP		 1920 cs.l = 1;
1921 }
1922
5601d05b 1923 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1924 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1925 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1926 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1927
3fb1b5db 1928 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1929 c->eip = msr_data;
1930
3fb1b5db 1931 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1932 c->regs[VCPU_REGS_RSP] = msr_data;
1933
e54cfa97 1934 return X86EMUL_CONTINUE;
8c604352
AP		 1935}
1936
4668f050 1937static int
3fb1b5db 1938emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1939{
1940 struct decode_cache *c = &ctxt->decode;
79168fd1 1941 struct desc_struct cs, ss;
4668f050
AP		 1942 u64 msr_data;
1943 int usermode;
79168fd1 1944 u16 cs_sel, ss_sel;
4668f050 1945
a0044755
GN		 1946 /* inject #GP if in real mode or Virtual 8086 mode */
1947 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1948 ctxt->mode == X86EMUL_MODE_VM86)
1949 return emulate_gp(ctxt, 0);
4668f050 1950
79168fd1 1951 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1952
1953 if ((c->rex_prefix & 0x8) != 0x0)
1954 usermode = X86EMUL_MODE_PROT64;
1955 else
1956 usermode = X86EMUL_MODE_PROT32;
1957
1958 cs.dpl = 3;
1959 ss.dpl = 3;
3fb1b5db 1960 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1961 switch (usermode) {
1962 case X86EMUL_MODE_PROT32:
79168fd1 1963 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1964 if ((msr_data & 0xfffc) == 0x0)
1965 return emulate_gp(ctxt, 0);
79168fd1 1966 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1967 break;
1968 case X86EMUL_MODE_PROT64:
79168fd1 1969 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1970 if (msr_data == 0x0)
1971 return emulate_gp(ctxt, 0);
79168fd1
GN		 1972 ss_sel = cs_sel + 8;
1973 cs.d = 0;
4668f050
AP		 1974 cs.l = 1;
1975 break;
1976 }
79168fd1
GN		 1977 cs_sel |= SELECTOR_RPL_MASK;
1978 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1979
5601d05b 1980 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1981 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1982 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1983 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1984
bdb475a3
GN		 1985 c->eip = c->regs[VCPU_REGS_RDX];
1986 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1987
e54cfa97 1988 return X86EMUL_CONTINUE;
4668f050
AP		 1989}
1990
9c537244
GN		 1991static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1992 struct x86_emulate_ops *ops)
f850e2e6
GN		 1993{
1994 int iopl;
1995 if (ctxt->mode == X86EMUL_MODE_REAL)
1996 return false;
1997 if (ctxt->mode == X86EMUL_MODE_VM86)
1998 return true;
1999 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2000 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2001}
2002
2003static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2004 struct x86_emulate_ops *ops,
2005 u16 port, u16 len)
2006{
79168fd1 2007 struct desc_struct tr_seg;
5601d05b 2008 u32 base3;
f850e2e6 2009 int r;
399a40c9 2010 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2011 unsigned mask = (1 << len) - 1;
5601d05b 2012 unsigned long base;
f850e2e6 2013
5601d05b 2014 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 2015 if (!tr_seg.p)
f850e2e6 2016 return false;
79168fd1 2017 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2018 return false;
5601d05b
GN		 2019 base = get_desc_base(&tr_seg);
2020#ifdef CONFIG_X86_64
2021 base |= ((u64)base3) << 32;
2022#endif
2023 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 2024 if (r != X86EMUL_CONTINUE)
2025 return false;
79168fd1 2026 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2027 return false;
399a40c9 2028 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
5601d05b 2029 NULL);
f850e2e6
GN		 2030 if (r != X86EMUL_CONTINUE)
2031 return false;
2032 if ((perm >> bit_idx) & mask)
2033 return false;
2034 return true;
2035}
2036
2037static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2038 struct x86_emulate_ops *ops,
2039 u16 port, u16 len)
2040{
4fc40f07
GN		 2041 if (ctxt->perm_ok)
2042 return true;
2043
9c537244 2044 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2045 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2046 return false;
4fc40f07
GN		 2047
2048 ctxt->perm_ok = true;
2049
f850e2e6
GN		 2050 return true;
2051}
2052
38ba30ba
GN		 2053static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2054 struct x86_emulate_ops *ops,
2055 struct tss_segment_16 *tss)
2056{
2057 struct decode_cache *c = &ctxt->decode;
2058
2059 tss->ip = c->eip;
2060 tss->flag = ctxt->eflags;
2061 tss->ax = c->regs[VCPU_REGS_RAX];
2062 tss->cx = c->regs[VCPU_REGS_RCX];
2063 tss->dx = c->regs[VCPU_REGS_RDX];
2064 tss->bx = c->regs[VCPU_REGS_RBX];
2065 tss->sp = c->regs[VCPU_REGS_RSP];
2066 tss->bp = c->regs[VCPU_REGS_RBP];
2067 tss->si = c->regs[VCPU_REGS_RSI];
2068 tss->di = c->regs[VCPU_REGS_RDI];
2069
2070 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2071 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2072 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2073 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2074 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2075}
2076
2077static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2078 struct x86_emulate_ops *ops,
2079 struct tss_segment_16 *tss)
2080{
2081 struct decode_cache *c = &ctxt->decode;
2082 int ret;
2083
2084 c->eip = tss->ip;
2085 ctxt->eflags = tss->flag | 2;
2086 c->regs[VCPU_REGS_RAX] = tss->ax;
2087 c->regs[VCPU_REGS_RCX] = tss->cx;
2088 c->regs[VCPU_REGS_RDX] = tss->dx;
2089 c->regs[VCPU_REGS_RBX] = tss->bx;
2090 c->regs[VCPU_REGS_RSP] = tss->sp;
2091 c->regs[VCPU_REGS_RBP] = tss->bp;
2092 c->regs[VCPU_REGS_RSI] = tss->si;
2093 c->regs[VCPU_REGS_RDI] = tss->di;
2094
2095 /*
2096 * SDM says that segment selectors are loaded before segment
2097 * descriptors
2098 */
2099 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2100 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2101 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2102 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2103 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2104
2105 /*
2106 * Now load segment descriptors. If fault happenes at this stage
2107 * it is handled in a context of new task
2108 */
2109 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2110 if (ret != X86EMUL_CONTINUE)
2111 return ret;
2112 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2113 if (ret != X86EMUL_CONTINUE)
2114 return ret;
2115 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2116 if (ret != X86EMUL_CONTINUE)
2117 return ret;
2118 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2119 if (ret != X86EMUL_CONTINUE)
2120 return ret;
2121 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2122 if (ret != X86EMUL_CONTINUE)
2123 return ret;
2124
2125 return X86EMUL_CONTINUE;
2126}
2127
2128static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2129 struct x86_emulate_ops *ops,
2130 u16 tss_selector, u16 old_tss_sel,
2131 ulong old_tss_base, struct desc_struct *new_desc)
2132{
2133 struct tss_segment_16 tss_seg;
2134 int ret;
bcc55cba 2135 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2136
2137 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2138 &ctxt->exception);
db297e3d 2139 if (ret != X86EMUL_CONTINUE)
38ba30ba 2140 /* FIXME: need to provide precise fault address */
38ba30ba 2141 return ret;
38ba30ba
GN		 2142
2143 save_state_to_tss16(ctxt, ops, &tss_seg);
2144
2145 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2146 &ctxt->exception);
db297e3d 2147 if (ret != X86EMUL_CONTINUE)
38ba30ba 2148 /* FIXME: need to provide precise fault address */
38ba30ba 2149 return ret;
38ba30ba
GN		 2150
2151 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2152 &ctxt->exception);
db297e3d 2153 if (ret != X86EMUL_CONTINUE)
38ba30ba 2154 /* FIXME: need to provide precise fault address */
38ba30ba 2155 return ret;
38ba30ba
GN		 2156
2157 if (old_tss_sel != 0xffff) {
2158 tss_seg.prev_task_link = old_tss_sel;
2159
2160 ret = ops->write_std(new_tss_base,
2161 &tss_seg.prev_task_link,
2162 sizeof tss_seg.prev_task_link,
bcc55cba 2163 ctxt->vcpu, &ctxt->exception);
db297e3d 2164 if (ret != X86EMUL_CONTINUE)
38ba30ba 2165 /* FIXME: need to provide precise fault address */
38ba30ba 2166 return ret;
38ba30ba
GN		 2167 }
2168
2169 return load_state_from_tss16(ctxt, ops, &tss_seg);
2170}
2171
2172static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2173 struct x86_emulate_ops *ops,
2174 struct tss_segment_32 *tss)
2175{
2176 struct decode_cache *c = &ctxt->decode;
2177
2178 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2179 tss->eip = c->eip;
2180 tss->eflags = ctxt->eflags;
2181 tss->eax = c->regs[VCPU_REGS_RAX];
2182 tss->ecx = c->regs[VCPU_REGS_RCX];
2183 tss->edx = c->regs[VCPU_REGS_RDX];
2184 tss->ebx = c->regs[VCPU_REGS_RBX];
2185 tss->esp = c->regs[VCPU_REGS_RSP];
2186 tss->ebp = c->regs[VCPU_REGS_RBP];
2187 tss->esi = c->regs[VCPU_REGS_RSI];
2188 tss->edi = c->regs[VCPU_REGS_RDI];
2189
2190 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2191 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2192 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2193 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2194 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2195 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2196 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2197}
2198
2199static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2200 struct x86_emulate_ops *ops,
2201 struct tss_segment_32 *tss)
2202{
2203 struct decode_cache *c = &ctxt->decode;
2204 int ret;
2205
35d3d4a1
AK		 2206 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2207 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2208 c->eip = tss->eip;
2209 ctxt->eflags = tss->eflags | 2;
2210 c->regs[VCPU_REGS_RAX] = tss->eax;
2211 c->regs[VCPU_REGS_RCX] = tss->ecx;
2212 c->regs[VCPU_REGS_RDX] = tss->edx;
2213 c->regs[VCPU_REGS_RBX] = tss->ebx;
2214 c->regs[VCPU_REGS_RSP] = tss->esp;
2215 c->regs[VCPU_REGS_RBP] = tss->ebp;
2216 c->regs[VCPU_REGS_RSI] = tss->esi;
2217 c->regs[VCPU_REGS_RDI] = tss->edi;
2218
2219 /*
2220 * SDM says that segment selectors are loaded before segment
2221 * descriptors
2222 */
2223 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2224 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2225 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2226 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2227 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2228 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2229 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2230
2231 /*
2232 * Now load segment descriptors. If fault happenes at this stage
2233 * it is handled in a context of new task
2234 */
2235 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2236 if (ret != X86EMUL_CONTINUE)
2237 return ret;
2238 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2239 if (ret != X86EMUL_CONTINUE)
2240 return ret;
2241 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2242 if (ret != X86EMUL_CONTINUE)
2243 return ret;
2244 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2245 if (ret != X86EMUL_CONTINUE)
2246 return ret;
2247 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2248 if (ret != X86EMUL_CONTINUE)
2249 return ret;
2250 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2251 if (ret != X86EMUL_CONTINUE)
2252 return ret;
2253 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2254 if (ret != X86EMUL_CONTINUE)
2255 return ret;
2256
2257 return X86EMUL_CONTINUE;
2258}
2259
2260static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2261 struct x86_emulate_ops *ops,
2262 u16 tss_selector, u16 old_tss_sel,
2263 ulong old_tss_base, struct desc_struct *new_desc)
2264{
2265 struct tss_segment_32 tss_seg;
2266 int ret;
bcc55cba 2267 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2268
2269 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2270 &ctxt->exception);
db297e3d 2271 if (ret != X86EMUL_CONTINUE)
38ba30ba 2272 /* FIXME: need to provide precise fault address */
38ba30ba 2273 return ret;
38ba30ba
GN		 2274
2275 save_state_to_tss32(ctxt, ops, &tss_seg);
2276
2277 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2278 &ctxt->exception);
db297e3d 2279 if (ret != X86EMUL_CONTINUE)
38ba30ba 2280 /* FIXME: need to provide precise fault address */
38ba30ba 2281 return ret;
38ba30ba
GN		 2282
2283 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2284 &ctxt->exception);
db297e3d 2285 if (ret != X86EMUL_CONTINUE)
38ba30ba 2286 /* FIXME: need to provide precise fault address */
38ba30ba 2287 return ret;
38ba30ba
GN		 2288
2289 if (old_tss_sel != 0xffff) {
2290 tss_seg.prev_task_link = old_tss_sel;
2291
2292 ret = ops->write_std(new_tss_base,
2293 &tss_seg.prev_task_link,
2294 sizeof tss_seg.prev_task_link,
bcc55cba 2295 ctxt->vcpu, &ctxt->exception);
db297e3d 2296 if (ret != X86EMUL_CONTINUE)
38ba30ba 2297 /* FIXME: need to provide precise fault address */
38ba30ba 2298 return ret;
38ba30ba
GN		 2299 }
2300
2301 return load_state_from_tss32(ctxt, ops, &tss_seg);
2302}
2303
2304static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2305 struct x86_emulate_ops *ops,
2306 u16 tss_selector, int reason,
2307 bool has_error_code, u32 error_code)
38ba30ba
GN		 2308{
2309 struct desc_struct curr_tss_desc, next_tss_desc;
2310 int ret;
2311 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2312 ulong old_tss_base =
5951c442 2313 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2314 u32 desc_limit;
38ba30ba
GN		 2315
2316 /* FIXME: old_tss_base == ~0 ? */
2317
2318 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2319 if (ret != X86EMUL_CONTINUE)
2320 return ret;
2321 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2322 if (ret != X86EMUL_CONTINUE)
2323 return ret;
2324
2325 /* FIXME: check that next_tss_desc is tss */
2326
2327 if (reason != TASK_SWITCH_IRET) {
2328 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2329 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2330 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2331 }
2332
ceffb459
GN		 2333 desc_limit = desc_limit_scaled(&next_tss_desc);
2334 if (!next_tss_desc.p ||
2335 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2336 desc_limit < 0x2b)) {
54b8486f 2337 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2338 return X86EMUL_PROPAGATE_FAULT;
2339 }
2340
2341 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2342 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2343 write_segment_descriptor(ctxt, ops, old_tss_sel,
2344 &curr_tss_desc);
2345 }
2346
2347 if (reason == TASK_SWITCH_IRET)
2348 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2349
2350 /* set back link to prev task only if NT bit is set in eflags
2351 note that old_tss_sel is not used afetr this point */
2352 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2353 old_tss_sel = 0xffff;
2354
2355 if (next_tss_desc.type & 8)
2356 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2357 old_tss_base, &next_tss_desc);
2358 else
2359 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2360 old_tss_base, &next_tss_desc);
0760d448
JK		 2361 if (ret != X86EMUL_CONTINUE)
2362 return ret;
38ba30ba
GN		 2363
2364 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2365 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2366
2367 if (reason != TASK_SWITCH_IRET) {
2368 next_tss_desc.type |= (1 << 1); /* set busy flag */
2369 write_segment_descriptor(ctxt, ops, tss_selector,
2370 &next_tss_desc);
2371 }
2372
2373 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2374 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2375 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2376
e269fb21
JK		 2377 if (has_error_code) {
2378 struct decode_cache *c = &ctxt->decode;
2379
2380 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2381 c->lock_prefix = 0;
2382 c->src.val = (unsigned long) error_code;
79168fd1 2383 emulate_push(ctxt, ops);
e269fb21
JK		 2384 }
2385
38ba30ba
GN		 2386 return ret;
2387}
2388
2389int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2390 u16 tss_selector, int reason,
2391 bool has_error_code, u32 error_code)
38ba30ba 2392{
9aabc88f 2393 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2394 struct decode_cache *c = &ctxt->decode;
2395 int rc;
2396
38ba30ba 2397 c->eip = ctxt->eip;
e269fb21 2398 c->dst.type = OP_NONE;
38ba30ba 2399
e269fb21
JK		 2400 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2401 has_error_code, error_code);
38ba30ba
GN		 2402
2403 if (rc == X86EMUL_CONTINUE) {
e269fb21 2404 rc = writeback(ctxt, ops);
95c55886
GN		 2405 if (rc == X86EMUL_CONTINUE)
2406 ctxt->eip = c->eip;
38ba30ba
GN		 2407 }
2408
a0c0ab2f 2409 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2410}
2411
90de84f5 2412static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2413 int reg, struct operand *op)
a682e354
GN		 2414{
2415 struct decode_cache *c = &ctxt->decode;
2416 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2417
d9271123 2418 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2419 op->addr.mem.ea = register_address(c, c->regs[reg]);
2420 op->addr.mem.seg = seg;
a682e354
GN		 2421}
2422
63540382
AK		 2423static int em_push(struct x86_emulate_ctxt *ctxt)
2424{
2425 emulate_push(ctxt, ctxt->ops);
2426 return X86EMUL_CONTINUE;
2427}
2428
7af04fc0
AK		 2429static int em_das(struct x86_emulate_ctxt *ctxt)
2430{
2431 struct decode_cache *c = &ctxt->decode;
2432 u8 al, old_al;
2433 bool af, cf, old_cf;
2434
2435 cf = ctxt->eflags & X86_EFLAGS_CF;
2436 al = c->dst.val;
2437
2438 old_al = al;
2439 old_cf = cf;
2440 cf = false;
2441 af = ctxt->eflags & X86_EFLAGS_AF;
2442 if ((al & 0x0f) > 9 || af) {
2443 al -= 6;
2444 cf = old_cf | (al >= 250);
2445 af = true;
2446 } else {
2447 af = false;
2448 }
2449 if (old_al > 0x99 || old_cf) {
2450 al -= 0x60;
2451 cf = true;
2452 }
2453
2454 c->dst.val = al;
2455 /* Set PF, ZF, SF */
2456 c->src.type = OP_IMM;
2457 c->src.val = 0;
2458 c->src.bytes = 1;
2459 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2460 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2461 if (cf)
2462 ctxt->eflags |= X86_EFLAGS_CF;
2463 if (af)
2464 ctxt->eflags |= X86_EFLAGS_AF;
2465 return X86EMUL_CONTINUE;
2466}
2467
0ef753b8
AK		 2468static int em_call_far(struct x86_emulate_ctxt *ctxt)
2469{
2470 struct decode_cache *c = &ctxt->decode;
2471 u16 sel, old_cs;
2472 ulong old_eip;
2473 int rc;
2474
2475 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2476 old_eip = c->eip;
2477
2478 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2479 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2480 return X86EMUL_CONTINUE;
2481
2482 c->eip = 0;
2483 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2484
2485 c->src.val = old_cs;
2486 emulate_push(ctxt, ctxt->ops);
2487 rc = writeback(ctxt, ctxt->ops);
2488 if (rc != X86EMUL_CONTINUE)
2489 return rc;
2490
2491 c->src.val = old_eip;
2492 emulate_push(ctxt, ctxt->ops);
2493 rc = writeback(ctxt, ctxt->ops);
2494 if (rc != X86EMUL_CONTINUE)
2495 return rc;
2496
2497 c->dst.type = OP_NONE;
2498
2499 return X86EMUL_CONTINUE;
2500}
2501
40ece7c7
AK		 2502static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2503{
2504 struct decode_cache *c = &ctxt->decode;
2505 int rc;
2506
2507 c->dst.type = OP_REG;
2508 c->dst.addr.reg = &c->eip;
2509 c->dst.bytes = c->op_bytes;
2510 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2511 if (rc != X86EMUL_CONTINUE)
2512 return rc;
2513 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2514 return X86EMUL_CONTINUE;
2515}
2516
5c82aa29 2517static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2518{
2519 struct decode_cache *c = &ctxt->decode;
2520
f3a1b9f4
AK		 2521 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2522 return X86EMUL_CONTINUE;
2523}
2524
5c82aa29
AK		 2525static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2526{
2527 struct decode_cache *c = &ctxt->decode;
2528
2529 c->dst.val = c->src2.val;
2530 return em_imul(ctxt);
2531}
2532
61429142
AK		 2533static int em_cwd(struct x86_emulate_ctxt *ctxt)
2534{
2535 struct decode_cache *c = &ctxt->decode;
2536
2537 c->dst.type = OP_REG;
2538 c->dst.bytes = c->src.bytes;
2539 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2540 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2541
2542 return X86EMUL_CONTINUE;
2543}
2544
48bb5d3c
AK		 2545static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2546{
48bb5d3c
AK		 2547 struct decode_cache *c = &ctxt->decode;
2548 u64 tsc = 0;
2549
48bb5d3c
AK		 2550 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2551 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2552 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2553 return X86EMUL_CONTINUE;
2554}
2555
b9eac5f4
AK		 2556static int em_mov(struct x86_emulate_ctxt *ctxt)
2557{
2558 struct decode_cache *c = &ctxt->decode;
2559 c->dst.val = c->src.val;
2560 return X86EMUL_CONTINUE;
2561}
2562
aa97bb48
AK		 2563static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2564{
2565 struct decode_cache *c = &ctxt->decode;
2566 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2567 return X86EMUL_CONTINUE;
2568}
2569
38503911
AK		 2570static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2571{
2572 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2573 int rc;
2574 ulong linear;
2575
83b8795a 2576 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4
AK		 2577 if (rc == X86EMUL_CONTINUE)
2578 emulate_invlpg(ctxt->vcpu, linear);
38503911
AK		 2579 /* Disable writeback. */
2580 c->dst.type = OP_NONE;
2581 return X86EMUL_CONTINUE;
2582}
2583
cfec82cb
JR		 2584static bool valid_cr(int nr)
2585{
2586 switch (nr) {
2587 case 0:
2588 case 2 ... 4:
2589 case 8:
2590 return true;
2591 default:
2592 return false;
2593 }
2594}
2595
2596static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2597{
2598 struct decode_cache *c = &ctxt->decode;
2599
2600 if (!valid_cr(c->modrm_reg))
2601 return emulate_ud(ctxt);
2602
2603 return X86EMUL_CONTINUE;
2604}
2605
2606static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2607{
2608 struct decode_cache *c = &ctxt->decode;
2609 u64 new_val = c->src.val64;
2610 int cr = c->modrm_reg;
2611
2612 static u64 cr_reserved_bits[] = {
2613 0xffffffff00000000ULL,
2614 0, 0, 0, /* CR3 checked later */
2615 CR4_RESERVED_BITS,
2616 0, 0, 0,
2617 CR8_RESERVED_BITS,
2618 };
2619
2620 if (!valid_cr(cr))
2621 return emulate_ud(ctxt);
2622
2623 if (new_val & cr_reserved_bits[cr])
2624 return emulate_gp(ctxt, 0);
2625
2626 switch (cr) {
2627 case 0: {
2628 u64 cr4, efer;
2629 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2630 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2631 return emulate_gp(ctxt, 0);
2632
2633 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2634 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2635
2636 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2637 !(cr4 & X86_CR4_PAE))
2638 return emulate_gp(ctxt, 0);
2639
2640 break;
2641 }
2642 case 3: {
2643 u64 rsvd = 0;
2644
2645 if (is_long_mode(ctxt->vcpu))
2646 rsvd = CR3_L_MODE_RESERVED_BITS;
2647 else if (is_pae(ctxt->vcpu))
2648 rsvd = CR3_PAE_RESERVED_BITS;
2649 else if (is_paging(ctxt->vcpu))
2650 rsvd = CR3_NONPAE_RESERVED_BITS;
2651
2652 if (new_val & rsvd)
2653 return emulate_gp(ctxt, 0);
2654
2655 break;
2656 }
2657 case 4: {
2658 u64 cr4, efer;
2659
2660 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2661 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2662
2663 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2664 return emulate_gp(ctxt, 0);
2665
2666 break;
2667 }
2668 }
2669
2670 return X86EMUL_CONTINUE;
2671}
2672
3b88e41a
JR		 2673static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2674{
2675 unsigned long dr7;
2676
2677 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2678
2679 /* Check if DR7.Global_Enable is set */
2680 return dr7 & (1 << 13);
2681}
2682
2683static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2684{
2685 struct decode_cache *c = &ctxt->decode;
2686 int dr = c->modrm_reg;
2687 u64 cr4;
2688
2689 if (dr > 7)
2690 return emulate_ud(ctxt);
2691
2692 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2693 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2694 return emulate_ud(ctxt);
2695
2696 if (check_dr7_gd(ctxt))
2697 return emulate_db(ctxt);
2698
2699 return X86EMUL_CONTINUE;
2700}
2701
2702static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2703{
2704 struct decode_cache *c = &ctxt->decode;
2705 u64 new_val = c->src.val64;
2706 int dr = c->modrm_reg;
2707
2708 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2709 return emulate_gp(ctxt, 0);
2710
2711 return check_dr_read(ctxt);
2712}
2713
01de8b09
JR		 2714static int check_svme(struct x86_emulate_ctxt *ctxt)
2715{
2716 u64 efer;
2717
2718 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2719
2720 if (!(efer & EFER_SVME))
2721 return emulate_ud(ctxt);
2722
2723 return X86EMUL_CONTINUE;
2724}
2725
2726static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2727{
2728 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2729
2730 /* Valid physical address? */
2731 if (rax & 0xffff000000000000)
2732 return emulate_gp(ctxt, 0);
2733
2734 return check_svme(ctxt);
2735}
2736
d7eb8203
JR		 2737static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2738{
2739 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2740
2741 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
2742 return emulate_ud(ctxt);
2743
2744 return X86EMUL_CONTINUE;
2745}
2746
8061252e
JR		 2747static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2748{
2749 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2750 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2751
2752 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
2753 (rcx > 3))
2754 return emulate_gp(ctxt, 0);
2755
2756 return X86EMUL_CONTINUE;
2757}
2758
f6511935
JR		 2759static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2760{
2761 struct decode_cache *c = &ctxt->decode;
2762
2763 c->dst.bytes = min(c->dst.bytes, 4u);
2764 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2765 return emulate_gp(ctxt, 0);
2766
2767 return X86EMUL_CONTINUE;
2768}
2769
2770static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2771{
2772 struct decode_cache *c = &ctxt->decode;
2773
2774 c->src.bytes = min(c->src.bytes, 4u);
2775 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2776 return emulate_gp(ctxt, 0);
2777
2778 return X86EMUL_CONTINUE;
2779}
2780
73fba5f4 2781#define D(_y) { .flags = (_y) }
c4f035c6 2782#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2783#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2784 .check_perm = (_p) }
73fba5f4 2785#define N D(0)
01de8b09 2786#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4
AK		 2787#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2788#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2789#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2790#define II(_f, _e, _i) \
2791 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2792#define IIP(_f, _e, _i, _p) \
2793 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2794 .check_perm = (_p) }
aa97bb48 2795#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2796
8d8f4e9f 2797#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2798#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2799#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2800
6230f7fc
AK		 2801#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2802 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2803 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2804
d7eb8203
JR		 2805static struct opcode group7_rm1[] = {
2806 DI(SrcNone | ModRM | Priv, monitor),
2807 DI(SrcNone | ModRM | Priv, mwait),
2808 N, N, N, N, N, N,
2809};
2810
01de8b09
JR		 2811static struct opcode group7_rm3[] = {
2812 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
bfeed29d 2813 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
01de8b09
JR		 2814 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2815 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2816 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2817 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2818 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2819 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2820};
6230f7fc 2821
d7eb8203
JR		 2822static struct opcode group7_rm7[] = {
2823 N,
2824 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2825 N, N, N, N, N, N,
2826};
73fba5f4
AK		 2827static struct opcode group1[] = {
2828 X7(D(Lock)), N
2829};
2830
2831static struct opcode group1A[] = {
2832 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2833};
2834
2835static struct opcode group3[] = {
2836 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2837 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2838 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2839};
2840
2841static struct opcode group4[] = {
2842 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2843 N, N, N, N, N, N,
2844};
2845
2846static struct opcode group5[] = {
2847 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2848 D(SrcMem | ModRM | Stack),
2849 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2850 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2851 D(SrcMem | ModRM | Stack), N,
2852};
2853
dee6bb70
JR		 2854static struct opcode group6[] = {
2855 DI(ModRM | Prot, sldt),
2856 DI(ModRM | Prot, str),
2857 DI(ModRM | Prot | Priv, lldt),
2858 DI(ModRM | Prot | Priv, ltr),
2859 N, N, N, N,
2860};
2861
73fba5f4 2862static struct group_dual group7 = { {
dee6bb70
JR		 2863 DI(ModRM | Mov | DstMem | Priv, sgdt),
2864 DI(ModRM | Mov | DstMem | Priv, sidt),
2865 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
3c6e276f
AK		 2866 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2867 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2868 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
73fba5f4 2869}, {
d7eb8203 2870 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
01de8b09 2871 N, EXT(0, group7_rm3),
3c6e276f 2872 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
d7eb8203 2873 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 2874} };
2875
2876static struct opcode group8[] = {
2877 N, N, N, N,
2878 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2879 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2880};
2881
2882static struct group_dual group9 = { {
2883 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2884}, {
2885 N, N, N, N, N, N, N, N,
2886} };
2887
a4d4a7c1
AK		 2888static struct opcode group11[] = {
2889 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2890};
2891
aa97bb48
AK		 2892static struct gprefix pfx_0f_6f_0f_7f = {
2893 N, N, N, I(Sse, em_movdqu),
2894};
2895
73fba5f4
AK		 2896static struct opcode opcode_table[256] = {
2897 /* 0x00 - 0x07 */
6230f7fc 2898 D6ALU(Lock),
73fba5f4
AK		 2899 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2900 /* 0x08 - 0x0F */
6230f7fc 2901 D6ALU(Lock),
73fba5f4
AK		 2902 D(ImplicitOps | Stack | No64), N,
2903 /* 0x10 - 0x17 */
6230f7fc 2904 D6ALU(Lock),
73fba5f4
AK		 2905 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2906 /* 0x18 - 0x1F */
6230f7fc 2907 D6ALU(Lock),
73fba5f4
AK		 2908 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2909 /* 0x20 - 0x27 */
6230f7fc 2910 D6ALU(Lock), N, N,
73fba5f4 2911 /* 0x28 - 0x2F */
6230f7fc 2912 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2913 /* 0x30 - 0x37 */
6230f7fc 2914 D6ALU(Lock), N, N,
73fba5f4 2915 /* 0x38 - 0x3F */
6230f7fc 2916 D6ALU(0), N, N,
73fba5f4
AK		 2917 /* 0x40 - 0x4F */
2918 X16(D(DstReg)),
2919 /* 0x50 - 0x57 */
63540382 2920 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2921 /* 0x58 - 0x5F */
2922 X8(D(DstReg | Stack)),
2923 /* 0x60 - 0x67 */
2924 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2925 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2926 N, N, N, N,
2927 /* 0x68 - 0x6F */
d46164db
AK		 2928 I(SrcImm | Mov | Stack, em_push),
2929 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2930 I(SrcImmByte | Mov | Stack, em_push),
2931 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 2932 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2933 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 2934 /* 0x70 - 0x7F */
2935 X16(D(SrcImmByte)),
2936 /* 0x80 - 0x87 */
2937 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2938 G(DstMem | SrcImm | ModRM | Group, group1),
2939 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2940 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2941 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2942 /* 0x88 - 0x8F */
b9eac5f4
AK		 2943 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2944 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2945 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2946 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2947 /* 0x90 - 0x97 */
bf608f88 2948 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 2949 /* 0x98 - 0x9F */
61429142 2950 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2951 I(SrcImmFAddr | No64, em_call_far), N,
3c6e276f 2952 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
73fba5f4 2953 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2954 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2955 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2956 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2957 D2bv(SrcSI | DstDI | String),
73fba5f4 2958 /* 0xA8 - 0xAF */
50748613 2959 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2960 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2961 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2962 D2bv(SrcAcc | DstDI | String),
73fba5f4 2963 /* 0xB0 - 0xB7 */
b9eac5f4 2964 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2965 /* 0xB8 - 0xBF */
b9eac5f4 2966 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2967 /* 0xC0 - 0xC7 */
d2c6c7ad 2968 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2969 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2970 D(ImplicitOps | Stack),
09b5f4d3 2971 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2972 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2973 /* 0xC8 - 0xCF */
2974 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 2975 D(ImplicitOps), DI(SrcImmByte, intn),
2976 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 2977 /* 0xD0 - 0xD7 */
d2c6c7ad 2978 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2979 N, N, N, N,
2980 /* 0xD8 - 0xDF */
2981 N, N, N, N, N, N, N, N,
2982 /* 0xE0 - 0xE7 */
e4abac67 2983 X4(D(SrcImmByte)),
f6511935
JR		 2984 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2985 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 2986 /* 0xE8 - 0xEF */
2987 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2988 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 2989 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2990 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 2991 /* 0xF0 - 0xF7 */
bf608f88 2992 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 2993 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2994 G(ByteOp, group3), G(0, group3),
73fba5f4 2995 /* 0xF8 - 0xFF */
8744aa9a 2996 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2997 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2998};
2999
3000static struct opcode twobyte_table[256] = {
3001 /* 0x00 - 0x0F */
dee6bb70 3002 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3003 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3004 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3005 N, D(ImplicitOps | ModRM), N, N,
3006 /* 0x10 - 0x1F */
3007 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3008 /* 0x20 - 0x2F */
cfec82cb 3009 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3010 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3011 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3012 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3013 N, N, N, N,
3014 N, N, N, N, N, N, N, N,
3015 /* 0x30 - 0x3F */
8061252e
JR		 3016 DI(ImplicitOps | Priv, wrmsr),
3017 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3018 DI(ImplicitOps | Priv, rdmsr),
3019 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3020 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3021 N, N,
73fba5f4
AK		 3022 N, N, N, N, N, N, N, N,
3023 /* 0x40 - 0x4F */
3024 X16(D(DstReg | SrcMem | ModRM | Mov)),
3025 /* 0x50 - 0x5F */
3026 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3027 /* 0x60 - 0x6F */
aa97bb48
AK		 3028 N, N, N, N,
3029 N, N, N, N,
3030 N, N, N, N,
3031 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3032 /* 0x70 - 0x7F */
aa97bb48
AK		 3033 N, N, N, N,
3034 N, N, N, N,
3035 N, N, N, N,
3036 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3037 /* 0x80 - 0x8F */
3038 X16(D(SrcImm)),
3039 /* 0x90 - 0x9F */
ee45b58e 3040 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3041 /* 0xA0 - 0xA7 */
3042 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3043 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3044 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3045 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3046 /* 0xA8 - 0xAF */
3047 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3048 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3049 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3050 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3051 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3052 /* 0xB0 - 0xB7 */
739ae406 3053 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3054 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3055 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3056 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3057 /* 0xB8 - 0xBF */
3058 N, N,
ba7ff2b7 3059 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3060 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3061 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3062 /* 0xC0 - 0xCF */
739ae406 3063 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3064 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3065 N, N, N, GD(0, &group9),
3066 N, N, N, N, N, N, N, N,
3067 /* 0xD0 - 0xDF */
3068 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3069 /* 0xE0 - 0xEF */
3070 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3071 /* 0xF0 - 0xFF */
3072 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3073};
3074
3075#undef D
3076#undef N
3077#undef G
3078#undef GD
3079#undef I
aa97bb48 3080#undef GP
01de8b09 3081#undef EXT
73fba5f4 3082
8d8f4e9f 3083#undef D2bv
f6511935 3084#undef D2bvIP
8d8f4e9f 3085#undef I2bv
6230f7fc 3086#undef D6ALU
8d8f4e9f 3087
39f21ee5
AK		 3088static unsigned imm_size(struct decode_cache *c)
3089{
3090 unsigned size;
3091
3092 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3093 if (size == 8)
3094 size = 4;
3095 return size;
3096}
3097
3098static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3099 unsigned size, bool sign_extension)
3100{
3101 struct decode_cache *c = &ctxt->decode;
3102 struct x86_emulate_ops *ops = ctxt->ops;
3103 int rc = X86EMUL_CONTINUE;
3104
3105 op->type = OP_IMM;
3106 op->bytes = size;
90de84f5 3107 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3108 /* NB. Immediates are sign-extended as necessary. */
3109 switch (op->bytes) {
3110 case 1:
3111 op->val = insn_fetch(s8, 1, c->eip);
3112 break;
3113 case 2:
3114 op->val = insn_fetch(s16, 2, c->eip);
3115 break;
3116 case 4:
3117 op->val = insn_fetch(s32, 4, c->eip);
3118 break;
3119 }
3120 if (!sign_extension) {
3121 switch (op->bytes) {
3122 case 1:
3123 op->val &= 0xff;
3124 break;
3125 case 2:
3126 op->val &= 0xffff;
3127 break;
3128 case 4:
3129 op->val &= 0xffffffff;
3130 break;
3131 }
3132 }
3133done:
3134 return rc;
3135}
3136
dde7e6d1 3137int
dc25e89e 3138x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3139{
3140 struct x86_emulate_ops *ops = ctxt->ops;
3141 struct decode_cache *c = &ctxt->decode;
3142 int rc = X86EMUL_CONTINUE;
3143 int mode = ctxt->mode;
0d7cdee8
AK		 3144 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3145 bool op_prefix = false;
dde7e6d1 3146 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 3147 struct operand memop = { .type = OP_NONE };
dde7e6d1 3148
dde7e6d1 3149 c->eip = ctxt->eip;
dc25e89e
AP		 3150 c->fetch.start = c->eip;
3151 c->fetch.end = c->fetch.start + insn_len;
3152 if (insn_len > 0)
3153 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3154 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
3155
3156 switch (mode) {
3157 case X86EMUL_MODE_REAL:
3158 case X86EMUL_MODE_VM86:
3159 case X86EMUL_MODE_PROT16:
3160 def_op_bytes = def_ad_bytes = 2;
3161 break;
3162 case X86EMUL_MODE_PROT32:
3163 def_op_bytes = def_ad_bytes = 4;
3164 break;
3165#ifdef CONFIG_X86_64
3166 case X86EMUL_MODE_PROT64:
3167 def_op_bytes = 4;
3168 def_ad_bytes = 8;
3169 break;
3170#endif
3171 default:
3172 return -1;
3173 }
3174
3175 c->op_bytes = def_op_bytes;
3176 c->ad_bytes = def_ad_bytes;
3177
3178 /* Legacy prefixes. */
3179 for (;;) {
3180 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3181 case 0x66: /* operand-size override */
0d7cdee8 3182 op_prefix = true;
dde7e6d1
AK		 3183 /* switch between 2/4 bytes */
3184 c->op_bytes = def_op_bytes ^ 6;
3185 break;
3186 case 0x67: /* address-size override */
3187 if (mode == X86EMUL_MODE_PROT64)
3188 /* switch between 4/8 bytes */
3189 c->ad_bytes = def_ad_bytes ^ 12;
3190 else
3191 /* switch between 2/4 bytes */
3192 c->ad_bytes = def_ad_bytes ^ 6;
3193 break;
3194 case 0x26: /* ES override */
3195 case 0x2e: /* CS override */
3196 case 0x36: /* SS override */
3197 case 0x3e: /* DS override */
3198 set_seg_override(c, (c->b >> 3) & 3);
3199 break;
3200 case 0x64: /* FS override */
3201 case 0x65: /* GS override */
3202 set_seg_override(c, c->b & 7);
3203 break;
3204 case 0x40 ... 0x4f: /* REX */
3205 if (mode != X86EMUL_MODE_PROT64)
3206 goto done_prefixes;
3207 c->rex_prefix = c->b;
3208 continue;
3209 case 0xf0: /* LOCK */
3210 c->lock_prefix = 1;
3211 break;
3212 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3213 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3214 c->rep_prefix = c->b;
dde7e6d1
AK		 3215 break;
3216 default:
3217 goto done_prefixes;
3218 }
3219
3220 /* Any legacy prefix after a REX prefix nullifies its effect. */
3221
3222 c->rex_prefix = 0;
3223 }
3224
3225done_prefixes:
3226
3227 /* REX prefix. */
1e87e3ef
AK		 3228 if (c->rex_prefix & 8)
3229 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3230
3231 /* Opcode byte(s). */
3232 opcode = opcode_table[c->b];
d3ad6243
WY		 3233 /* Two-byte opcode? */
3234 if (c->b == 0x0f) {
3235 c->twobyte = 1;
3236 c->b = insn_fetch(u8, 1, c->eip);
3237 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3238 }
3239 c->d = opcode.flags;
3240
3241 if (c->d & Group) {
3242 dual = c->d & GroupDual;
3243 c->modrm = insn_fetch(u8, 1, c->eip);
3244 --c->eip;
3245
3246 if (c->d & GroupDual) {
3247 g_mod012 = opcode.u.gdual->mod012;
3248 g_mod3 = opcode.u.gdual->mod3;
3249 } else
3250 g_mod012 = g_mod3 = opcode.u.group;
3251
3252 c->d &= ~(Group | GroupDual);
3253
3254 goffset = (c->modrm >> 3) & 7;
3255
3256 if ((c->modrm >> 6) == 3)
3257 opcode = g_mod3[goffset];
3258 else
3259 opcode = g_mod012[goffset];
01de8b09
JR		 3260
3261 if (opcode.flags & RMExt) {
3262 goffset = c->modrm & 7;
3263 opcode = opcode.u.group[goffset];
3264 }
3265
dde7e6d1
AK		 3266 c->d |= opcode.flags;
3267 }
3268
0d7cdee8
AK		 3269 if (c->d & Prefix) {
3270 if (c->rep_prefix && op_prefix)
3271 return X86EMUL_UNHANDLEABLE;
3272 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3273 switch (simd_prefix) {
3274 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3275 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3276 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3277 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3278 }
3279 c->d |= opcode.flags;
3280 }
3281
dde7e6d1 3282 c->execute = opcode.u.execute;
d09beabd 3283 c->check_perm = opcode.check_perm;
c4f035c6 3284 c->intercept = opcode.intercept;
dde7e6d1
AK		 3285
3286 /* Unrecognised? */
d53db5ef 3287 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3288 return -1;
dde7e6d1 3289
d867162c
AK		 3290 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3291 return -1;
3292
dde7e6d1
AK		 3293 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3294 c->op_bytes = 8;
3295
7f9b4b75
AK		 3296 if (c->d & Op3264) {
3297 if (mode == X86EMUL_MODE_PROT64)
3298 c->op_bytes = 8;
3299 else
3300 c->op_bytes = 4;
3301 }
3302
1253791d
AK		 3303 if (c->d & Sse)
3304 c->op_bytes = 16;
3305
dde7e6d1 3306 /* ModRM and SIB bytes. */
09ee57cd 3307 if (c->d & ModRM) {
2dbd0dd7 3308 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3309 if (!c->has_seg_override)
3310 set_seg_override(c, c->modrm_seg);
3311 } else if (c->d & MemAbs)
2dbd0dd7 3312 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3313 if (rc != X86EMUL_CONTINUE)
3314 goto done;
3315
3316 if (!c->has_seg_override)
3317 set_seg_override(c, VCPU_SREG_DS);
3318
90de84f5 3319 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3320
2dbd0dd7 3321 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3322 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3323
2dbd0dd7 3324 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3325 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3326
3327 /*
3328 * Decode and fetch the source operand: register, memory
3329 * or immediate.
3330 */
3331 switch (c->d & SrcMask) {
3332 case SrcNone:
3333 break;
3334 case SrcReg:
1253791d 3335 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3336 break;
3337 case SrcMem16:
2dbd0dd7 3338 memop.bytes = 2;
dde7e6d1
AK		 3339 goto srcmem_common;
3340 case SrcMem32:
2dbd0dd7 3341 memop.bytes = 4;
dde7e6d1
AK		 3342 goto srcmem_common;
3343 case SrcMem:
2dbd0dd7 3344 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3345 c->op_bytes;
dde7e6d1 3346 srcmem_common:
2dbd0dd7 3347 c->src = memop;
dde7e6d1 3348 break;
b250e605 3349 case SrcImmU16:
39f21ee5
AK		 3350 rc = decode_imm(ctxt, &c->src, 2, false);
3351 break;
dde7e6d1 3352 case SrcImm:
39f21ee5
AK		 3353 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3354 break;
dde7e6d1 3355 case SrcImmU:
39f21ee5 3356 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3357 break;
3358 case SrcImmByte:
39f21ee5
AK		 3359 rc = decode_imm(ctxt, &c->src, 1, true);
3360 break;
dde7e6d1 3361 case SrcImmUByte:
39f21ee5 3362 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3363 break;
3364 case SrcAcc:
3365 c->src.type = OP_REG;
3366 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3367 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3368 fetch_register_operand(&c->src);
dde7e6d1
AK		 3369 break;
3370 case SrcOne:
3371 c->src.bytes = 1;
3372 c->src.val = 1;
3373 break;
3374 case SrcSI:
3375 c->src.type = OP_MEM;
3376 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3377 c->src.addr.mem.ea =
3378 register_address(c, c->regs[VCPU_REGS_RSI]);
3379 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3380 c->src.val = 0;
3381 break;
3382 case SrcImmFAddr:
3383 c->src.type = OP_IMM;
90de84f5 3384 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3385 c->src.bytes = c->op_bytes + 2;
3386 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3387 break;
3388 case SrcMemFAddr:
2dbd0dd7
AK		 3389 memop.bytes = c->op_bytes + 2;
3390 goto srcmem_common;
dde7e6d1
AK		 3391 break;
3392 }
3393
39f21ee5
AK		 3394 if (rc != X86EMUL_CONTINUE)
3395 goto done;
3396
dde7e6d1
AK		 3397 /*
3398 * Decode and fetch the second source operand: register, memory
3399 * or immediate.
3400 */
3401 switch (c->d & Src2Mask) {
3402 case Src2None:
3403 break;
3404 case Src2CL:
3405 c->src2.bytes = 1;
3406 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3407 break;
3408 case Src2ImmByte:
39f21ee5 3409 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3410 break;
3411 case Src2One:
3412 c->src2.bytes = 1;
3413 c->src2.val = 1;
3414 break;
7db41eb7
AK		 3415 case Src2Imm:
3416 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3417 break;
dde7e6d1
AK		 3418 }
3419
39f21ee5
AK		 3420 if (rc != X86EMUL_CONTINUE)
3421 goto done;
3422
dde7e6d1
AK		 3423 /* Decode and fetch the destination operand: register or memory. */
3424 switch (c->d & DstMask) {
dde7e6d1 3425 case DstReg:
1253791d 3426 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3427 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3428 break;
943858e2
WY		 3429 case DstImmUByte:
3430 c->dst.type = OP_IMM;
90de84f5 3431 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3432 c->dst.bytes = 1;
3433 c->dst.val = insn_fetch(u8, 1, c->eip);
3434 break;
dde7e6d1
AK		 3435 case DstMem:
3436 case DstMem64:
2dbd0dd7 3437 c->dst = memop;
dde7e6d1
AK		 3438 if ((c->d & DstMask) == DstMem64)
3439 c->dst.bytes = 8;
3440 else
3441 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3442 if (c->d & BitOp)
3443 fetch_bit_operand(c);
2dbd0dd7 3444 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3445 break;
3446 case DstAcc:
3447 c->dst.type = OP_REG;
3448 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3449 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3450 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3451 c->dst.orig_val = c->dst.val;
3452 break;
3453 case DstDI:
3454 c->dst.type = OP_MEM;
3455 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3456 c->dst.addr.mem.ea =
3457 register_address(c, c->regs[VCPU_REGS_RDI]);
3458 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3459 c->dst.val = 0;
3460 break;
36089fed
WY		 3461 case ImplicitOps:
3462 /* Special instructions do their own operand decoding. */
3463 default:
3464 c->dst.type = OP_NONE; /* Disable writeback. */
3465 return 0;
dde7e6d1
AK		 3466 }
3467
3468done:
a0c0ab2f 3469 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3470}
3471
3e2f65d5
GN		 3472static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3473{
3474 struct decode_cache *c = &ctxt->decode;
3475
3476 /* The second termination condition only applies for REPE
3477 * and REPNE. Test if the repeat string operation prefix is
3478 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3479 * corresponding termination condition according to:
3480 * - if REPE/REPZ and ZF = 0 then done
3481 * - if REPNE/REPNZ and ZF = 1 then done
3482 */
3483 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3484 (c->b == 0xae) || (c->b == 0xaf))
3485 && (((c->rep_prefix == REPE_PREFIX) &&
3486 ((ctxt->eflags & EFLG_ZF) == 0))
3487 || ((c->rep_prefix == REPNE_PREFIX) &&
3488 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3489 return true;
3490
3491 return false;
3492}
3493
8b4caf66 3494int
9aabc88f 3495x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3496{
9aabc88f 3497 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3498 u64 msr_data;
8b4caf66 3499 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3500 int rc = X86EMUL_CONTINUE;
5cd21917 3501 int saved_dst_type = c->dst.type;
6e154e56 3502 int irq; /* Used for int 3, int, and into */
8b4caf66 3503
9de41573 3504 ctxt->decode.mem_read.pos = 0;
310b5d30 3505
1161624f 3506 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3507 rc = emulate_ud(ctxt);
1161624f
GN		 3508 goto done;
3509 }
3510
d380a5e4 3511 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3512 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3513 rc = emulate_ud(ctxt);
d380a5e4
GN		 3514 goto done;
3515 }
3516
081bca0e 3517 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3518 rc = emulate_ud(ctxt);
081bca0e
AK		 3519 goto done;
3520 }
3521
1253791d
AK		 3522 if ((c->d & Sse)
3523 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3524 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3525 rc = emulate_ud(ctxt);
3526 goto done;
3527 }
3528
3529 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3530 rc = emulate_nm(ctxt);
3531 goto done;
3532 }
3533
c4f035c6 3534 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3535 rc = emulator_check_intercept(ctxt, c->intercept,
3536 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3537 if (rc != X86EMUL_CONTINUE)
3538 goto done;
3539 }
3540
e92805ac 3541 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3542 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 3543 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3544 goto done;
3545 }
3546
8ea7d6ae
JR		 3547 /* Instruction can only be executed in protected mode */
3548 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3549 rc = emulate_ud(ctxt);
3550 goto done;
3551 }
3552
d09beabd
JR		 3553 /* Do instruction specific permission checks */
3554 if (c->check_perm) {
3555 rc = c->check_perm(ctxt);
3556 if (rc != X86EMUL_CONTINUE)
3557 goto done;
3558 }
3559
c4f035c6 3560 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3561 rc = emulator_check_intercept(ctxt, c->intercept,
3562 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3563 if (rc != X86EMUL_CONTINUE)
3564 goto done;
3565 }
3566
b9fa9d6b
AK		 3567 if (c->rep_prefix && (c->d & String)) {
3568 /* All REP prefixes have the same first termination condition */
c73e197b 3569 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3570 ctxt->eip = c->eip;
b9fa9d6b
AK		 3571 goto done;
3572 }
b9fa9d6b
AK		 3573 }
3574
c483c02a 3575 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3576 rc = segmented_read(ctxt, c->src.addr.mem,
3577 c->src.valptr, c->src.bytes);
b60d513c 3578 if (rc != X86EMUL_CONTINUE)
8b4caf66 3579 goto done;
16518d5a 3580 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3581 }
3582
e35b7b9c 3583 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3584 rc = segmented_read(ctxt, c->src2.addr.mem,
3585 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3586 if (rc != X86EMUL_CONTINUE)
3587 goto done;
3588 }
3589
8b4caf66
LV		 3590 if ((c->d & DstMask) == ImplicitOps)
3591 goto special_insn;
3592
3593
69f55cb1
GN		 3594 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3595 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3596 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3597 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3598 if (rc != X86EMUL_CONTINUE)
3599 goto done;
038e51de 3600 }
e4e03ded 3601 c->dst.orig_val = c->dst.val;
038e51de 3602
018a98db
AK		 3603special_insn:
3604
c4f035c6 3605 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3606 rc = emulator_check_intercept(ctxt, c->intercept,
3607 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3608 if (rc != X86EMUL_CONTINUE)
3609 goto done;
3610 }
3611
ef65c889
AK		 3612 if (c->execute) {
3613 rc = c->execute(ctxt);
3614 if (rc != X86EMUL_CONTINUE)
3615 goto done;
3616 goto writeback;
3617 }
3618
e4e03ded 3619 if (c->twobyte)
6aa8b732
AK		 3620 goto twobyte_insn;
3621
e4e03ded 3622 switch (c->b) {
6aa8b732
AK		 3623 case 0x00 ... 0x05:
3624 add: /* add */
05f086f8 3625 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3626 break;
0934ac9d 3627 case 0x06: /* push es */
79168fd1 3628 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3629 break;
3630 case 0x07: /* pop es */
0934ac9d 3631 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3632 break;
6aa8b732
AK		 3633 case 0x08 ... 0x0d:
3634 or: /* or */
05f086f8 3635 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3636 break;
0934ac9d 3637 case 0x0e: /* push cs */
79168fd1 3638 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3639 break;
6aa8b732
AK		 3640 case 0x10 ... 0x15:
3641 adc: /* adc */
05f086f8 3642 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3643 break;
0934ac9d 3644 case 0x16: /* push ss */
79168fd1 3645 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3646 break;
3647 case 0x17: /* pop ss */
0934ac9d 3648 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3649 break;
6aa8b732
AK		 3650 case 0x18 ... 0x1d:
3651 sbb: /* sbb */
05f086f8 3652 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3653 break;
0934ac9d 3654 case 0x1e: /* push ds */
79168fd1 3655 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3656 break;
3657 case 0x1f: /* pop ds */
0934ac9d 3658 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3659 break;
aa3a816b 3660 case 0x20 ... 0x25:
6aa8b732 3661 and: /* and */
05f086f8 3662 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3663 break;
3664 case 0x28 ... 0x2d:
3665 sub: /* sub */
05f086f8 3666 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3667 break;
3668 case 0x30 ... 0x35:
3669 xor: /* xor */
05f086f8 3670 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3671 break;
3672 case 0x38 ... 0x3d:
3673 cmp: /* cmp */
05f086f8 3674 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3675 break;
33615aa9
AK		 3676 case 0x40 ... 0x47: /* inc r16/r32 */
3677 emulate_1op("inc", c->dst, ctxt->eflags);
3678 break;
3679 case 0x48 ... 0x4f: /* dec r16/r32 */
3680 emulate_1op("dec", c->dst, ctxt->eflags);
3681 break;
33615aa9
AK		 3682 case 0x58 ... 0x5f: /* pop reg */
3683 pop_instruction:
350f69dc 3684 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3685 break;
abcf14b5 3686 case 0x60: /* pusha */
c37eda13 3687 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3688 break;
3689 case 0x61: /* popa */
3690 rc = emulate_popa(ctxt, ops);
abcf14b5 3691 break;
6aa8b732 3692 case 0x63: /* movsxd */
8b4caf66 3693 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3694 goto cannot_emulate;
e4e03ded 3695 c->dst.val = (s32) c->src.val;
6aa8b732 3696 break;
018a98db
AK		 3697 case 0x6c: /* insb */
3698 case 0x6d: /* insw/insd */
a13a63fa
WY		 3699 c->src.val = c->regs[VCPU_REGS_RDX];
3700 goto do_io_in;
018a98db
AK		 3701 case 0x6e: /* outsb */
3702 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3703 c->dst.val = c->regs[VCPU_REGS_RDX];
3704 goto do_io_out;
7972995b 3705 break;
b2833e3c 3706 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3707 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3708 jmp_rel(c, c->src.val);
018a98db 3709 break;
6aa8b732 3710 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3711 switch (c->modrm_reg) {
6aa8b732
AK		 3712 case 0:
3713 goto add;
3714 case 1:
3715 goto or;
3716 case 2:
3717 goto adc;
3718 case 3:
3719 goto sbb;
3720 case 4:
3721 goto and;
3722 case 5:
3723 goto sub;
3724 case 6:
3725 goto xor;
3726 case 7:
3727 goto cmp;
3728 }
3729 break;
3730 case 0x84 ... 0x85:
dfb507c4 3731 test:
05f086f8 3732 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3733 break;
3734 case 0x86 ... 0x87: /* xchg */
b13354f8 3735 xchg:
6aa8b732 3736 /* Write back the register source. */
31be40b3
WY		 3737 c->src.val = c->dst.val;
3738 write_register_operand(&c->src);
6aa8b732
AK		 3739 /*
3740 * Write back the memory destination with implicit LOCK
3741 * prefix.
3742 */
31be40b3 3743 c->dst.val = c->src.orig_val;
e4e03ded 3744 c->lock_prefix = 1;
6aa8b732 3745 break;
79168fd1
GN		 3746 case 0x8c: /* mov r/m, sreg */
3747 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3748 rc = emulate_ud(ctxt);
5e3ae6c5 3749 goto done;
38d5bc6d 3750 }
79168fd1 3751 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3752 break;
7e0b54b1 3753 case 0x8d: /* lea r16/r32, m */
90de84f5 3754 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3755 break;
4257198a
GT		 3756 case 0x8e: { /* mov seg, r/m16 */
3757 uint16_t sel;
4257198a
GT		 3758
3759 sel = c->src.val;
8b9f4414 3760
c697518a
GN		 3761 if (c->modrm_reg == VCPU_SREG_CS ||
3762 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3763 rc = emulate_ud(ctxt);
8b9f4414
GN		 3764 goto done;
3765 }
3766
310b5d30 3767 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3768 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3769
2e873022 3770 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3771
3772 c->dst.type = OP_NONE; /* Disable writeback. */
3773 break;
3774 }
6aa8b732 3775 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3776 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3777 break;
3d9e77df
AK		 3778 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3779 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3780 break;
b13354f8 3781 goto xchg;
e8b6fa70
WY		 3782 case 0x98: /* cbw/cwde/cdqe */
3783 switch (c->op_bytes) {
3784 case 2: c->dst.val = (s8)c->dst.val; break;
3785 case 4: c->dst.val = (s16)c->dst.val; break;
3786 case 8: c->dst.val = (s32)c->dst.val; break;
3787 }
3788 break;
fd2a7608 3789 case 0x9c: /* pushf */
05f086f8 3790 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3791 emulate_push(ctxt, ops);
8cdbd2c9 3792 break;
535eabcf 3793 case 0x9d: /* popf */
2b48cc75 3794 c->dst.type = OP_REG;
1a6440ae 3795 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3796 c->dst.bytes = c->op_bytes;
d4c6a154 3797 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3798 break;
6aa8b732 3799 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3800 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3801 goto cmp;
dfb507c4
MG		 3802 case 0xa8 ... 0xa9: /* test ax, imm */
3803 goto test;
6aa8b732 3804 case 0xae ... 0xaf: /* scas */
f6b33fc5 3805 goto cmp;
018a98db
AK		 3806 case 0xc0 ... 0xc1:
3807 emulate_grp2(ctxt);
3808 break;
111de5d6 3809 case 0xc3: /* ret */
cf5de4f8 3810 c->dst.type = OP_REG;
1a6440ae 3811 c->dst.addr.reg = &c->eip;
cf5de4f8 3812 c->dst.bytes = c->op_bytes;
111de5d6 3813 goto pop_instruction;
09b5f4d3
WY		 3814 case 0xc4: /* les */
3815 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3816 break;
3817 case 0xc5: /* lds */
3818 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3819 break;
a77ab5ea
AK		 3820 case 0xcb: /* ret far */
3821 rc = emulate_ret_far(ctxt, ops);
62bd430e 3822 break;
6e154e56
MG		 3823 case 0xcc: /* int3 */
3824 irq = 3;
3825 goto do_interrupt;
3826 case 0xcd: /* int n */
3827 irq = c->src.val;
3828 do_interrupt:
3829 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3830 break;
3831 case 0xce: /* into */
3832 if (ctxt->eflags & EFLG_OF) {
3833 irq = 4;
3834 goto do_interrupt;
3835 }
3836 break;
62bd430e
MG		 3837 case 0xcf: /* iret */
3838 rc = emulate_iret(ctxt, ops);
a77ab5ea 3839 break;
018a98db 3840 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3841 emulate_grp2(ctxt);
3842 break;
3843 case 0xd2 ... 0xd3: /* Grp2 */
3844 c->src.val = c->regs[VCPU_REGS_RCX];
3845 emulate_grp2(ctxt);
3846 break;
f2f31845
WY		 3847 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3848 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3849 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3850 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3851 jmp_rel(c, c->src.val);
3852 break;
e4abac67
WY		 3853 case 0xe3: /* jcxz/jecxz/jrcxz */
3854 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3855 jmp_rel(c, c->src.val);
3856 break;
a6a3034c
MG		 3857 case 0xe4: /* inb */
3858 case 0xe5: /* in */
cf8f70bf 3859 goto do_io_in;
a6a3034c
MG		 3860 case 0xe6: /* outb */
3861 case 0xe7: /* out */
cf8f70bf 3862 goto do_io_out;
1a52e051 3863 case 0xe8: /* call (near) */ {
d53c4777 3864 long int rel = c->src.val;
e4e03ded 3865 c->src.val = (unsigned long) c->eip;
7a957275 3866 jmp_rel(c, rel);
79168fd1 3867 emulate_push(ctxt, ops);
8cdbd2c9 3868 break;
1a52e051
NK		 3869 }
3870 case 0xe9: /* jmp rel */
954cd36f 3871 goto jmp;
414e6277
GN		 3872 case 0xea: { /* jmp far */
3873 unsigned short sel;
ea79849d 3874 jump_far:
414e6277
GN		 3875 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3876
3877 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3878 goto done;
954cd36f 3879
414e6277
GN		 3880 c->eip = 0;
3881 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3882 break;
414e6277 3883 }
954cd36f
GT		 3884 case 0xeb:
3885 jmp: /* jmp rel short */
7a957275 3886 jmp_rel(c, c->src.val);
a01af5ec 3887 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3888 break;
a6a3034c
MG		 3889 case 0xec: /* in al,dx */
3890 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3891 c->src.val = c->regs[VCPU_REGS_RDX];
3892 do_io_in:
7b262e90
GN		 3893 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3894 &c->dst.val))
cf8f70bf
GN		 3895 goto done; /* IO is needed */
3896 break;
ce7a0ad3
WY		 3897 case 0xee: /* out dx,al */
3898 case 0xef: /* out dx,(e/r)ax */
41167be5 3899 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3900 do_io_out:
41167be5
WY		 3901 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3902 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3903 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3904 break;
111de5d6 3905 case 0xf4: /* hlt */
ad312c7c 3906 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3907 break;
111de5d6
AK		 3908 case 0xf5: /* cmc */
3909 /* complement carry flag from eflags reg */
3910 ctxt->eflags ^= EFLG_CF;
111de5d6 3911 break;
018a98db 3912 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3913 rc = emulate_grp3(ctxt, ops);
018a98db 3914 break;
111de5d6
AK		 3915 case 0xf8: /* clc */
3916 ctxt->eflags &= ~EFLG_CF;
111de5d6 3917 break;
8744aa9a
MG		 3918 case 0xf9: /* stc */
3919 ctxt->eflags |= EFLG_CF;
3920 break;
111de5d6 3921 case 0xfa: /* cli */
07cbc6c1 3922 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3923 rc = emulate_gp(ctxt, 0);
07cbc6c1 3924 goto done;
36089fed 3925 } else
f850e2e6 3926 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3927 break;
3928 case 0xfb: /* sti */
07cbc6c1 3929 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3930 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3931 goto done;
3932 } else {
95cb2295 3933 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3934 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3935 }
111de5d6 3936 break;
fb4616f4
MG		 3937 case 0xfc: /* cld */
3938 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3939 break;
3940 case 0xfd: /* std */
3941 ctxt->eflags |= EFLG_DF;
fb4616f4 3942 break;
ea79849d
GN		 3943 case 0xfe: /* Grp4 */
3944 grp45:
018a98db 3945 rc = emulate_grp45(ctxt, ops);
018a98db 3946 break;
ea79849d
GN		 3947 case 0xff: /* Grp5 */
3948 if (c->modrm_reg == 5)
3949 goto jump_far;
3950 goto grp45;
91269b8f
AK		 3951 default:
3952 goto cannot_emulate;
6aa8b732 3953 }
018a98db 3954
7d9ddaed
AK		 3955 if (rc != X86EMUL_CONTINUE)
3956 goto done;
3957
018a98db
AK		 3958writeback:
3959 rc = writeback(ctxt, ops);
1b30eaa8 3960 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3961 goto done;
3962
5cd21917
GN		 3963 /*
3964 * restore dst type in case the decoding will be reused
3965 * (happens for string instruction )
3966 */
3967 c->dst.type = saved_dst_type;
3968
a682e354 3969 if ((c->d & SrcMask) == SrcSI)
90de84f5 3970 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3971 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3972
3973 if ((c->d & DstMask) == DstDI)
90de84f5 3974 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3975 &c->dst);
d9271123 3976
5cd21917 3977 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3978 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3979 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3980
d2ddd1c4
GN		 3981 if (!string_insn_completed(ctxt)) {
3982 /*
3983 * Re-enter guest when pio read ahead buffer is empty
3984 * or, if it is not used, after each 1024 iteration.
3985 */
3986 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3987 (r->end == 0 || r->end != r->pos)) {
3988 /*
3989 * Reset read cache. Usually happens before
3990 * decode, but since instruction is restarted
3991 * we have to do it here.
3992 */
3993 ctxt->decode.mem_read.end = 0;
3994 return EMULATION_RESTART;
3995 }
3996 goto done; /* skip rip writeback */
0fa6ccbd 3997 }
5cd21917 3998 }
d2ddd1c4
GN		 3999
4000 ctxt->eip = c->eip;
018a98db
AK		 4001
4002done:
da9cb575
AK		 4003 if (rc == X86EMUL_PROPAGATE_FAULT)
4004 ctxt->have_exception = true;
775fde86
JR		 4005 if (rc == X86EMUL_INTERCEPTED)
4006 return EMULATION_INTERCEPTED;
4007
d2ddd1c4 4008 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4009
4010twobyte_insn:
e4e03ded 4011 switch (c->b) {
6aa8b732 4012 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 4013 switch (c->modrm_reg) {
6aa8b732
AK		 4014 u16 size;
4015 unsigned long address;
4016
aca7f966 4017 case 0: /* vmcall */
e4e03ded 4018 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 4019 goto cannot_emulate;
4020
7aa81cc0 4021 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 4022 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 4023 goto done;
4024
33e3885d 4025 /* Let the processor re-execute the fixed hypercall */
063db061 4026 c->eip = ctxt->eip;
16286d08
AK		 4027 /* Disable writeback. */
4028 c->dst.type = OP_NONE;
aca7f966 4029 break;
6aa8b732 4030 case 2: /* lgdt */
1a6440ae 4031 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 4032 &size, &address, c->op_bytes);
1b30eaa8 4033 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 4034 goto done;
4035 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 4036 /* Disable writeback. */
4037 c->dst.type = OP_NONE;
6aa8b732 4038 break;
aca7f966 4039 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 4040 if (c->modrm_mod == 3) {
4041 switch (c->modrm_rm) {
4042 case 1:
4043 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 4044 break;
4045 default:
4046 goto cannot_emulate;
4047 }
aca7f966 4048 } else {
1a6440ae 4049 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 4050 &size, &address,
e4e03ded 4051 c->op_bytes);
1b30eaa8 4052 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 4053 goto done;
4054 realmode_lidt(ctxt->vcpu, size, address);
4055 }
16286d08
AK		 4056 /* Disable writeback. */
4057 c->dst.type = OP_NONE;
6aa8b732
AK		 4058 break;
4059 case 4: /* smsw */
16286d08 4060 c->dst.bytes = 2;
52a46617 4061 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 4062 break;
4063 case 6: /* lmsw */
9928ff60 4064 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 4065 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 4066 c->dst.type = OP_NONE;
6aa8b732 4067 break;
6e1e5ffe 4068 case 5: /* not defined */
54b8486f 4069 emulate_ud(ctxt);
da9cb575 4070 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 4071 goto done;
6aa8b732 4072 case 7: /* invlpg*/
38503911 4073 rc = em_invlpg(ctxt);
6aa8b732
AK		 4074 break;
4075 default:
4076 goto cannot_emulate;
4077 }
4078 break;
e99f0507 4079 case 0x05: /* syscall */
3fb1b5db 4080 rc = emulate_syscall(ctxt, ops);
e99f0507 4081 break;
018a98db
AK		 4082 case 0x06:
4083 emulate_clts(ctxt->vcpu);
018a98db 4084 break;
018a98db 4085 case 0x09: /* wbinvd */
f5f48ee1 4086 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 4087 break;
4088 case 0x08: /* invd */
018a98db
AK		 4089 case 0x0d: /* GrpP (prefetch) */
4090 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4091 break;
4092 case 0x20: /* mov cr, reg */
1a0c7d44 4093 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 4094 break;
6aa8b732 4095 case 0x21: /* mov from dr to reg */
b27f3856 4096 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 4097 break;
018a98db 4098 case 0x22: /* mov reg, cr */
1a0c7d44 4099 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 4100 emulate_gp(ctxt, 0);
da9cb575 4101 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4102 goto done;
4103 }
018a98db
AK		 4104 c->dst.type = OP_NONE;
4105 break;
6aa8b732 4106 case 0x23: /* mov from reg to dr */
b27f3856 4107 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 4108 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4109 ~0ULL : ~0U), ctxt->vcpu) < 0) {
4110 /* #UD condition is already handled by the code above */
54b8486f 4111 emulate_gp(ctxt, 0);
da9cb575 4112 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4113 goto done;
4114 }
4115
a01af5ec 4116 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4117 break;
018a98db
AK		 4118 case 0x30:
4119 /* wrmsr */
4120 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4121 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 4122 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4123 emulate_gp(ctxt, 0);
da9cb575 4124 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4125 goto done;
018a98db
AK		 4126 }
4127 rc = X86EMUL_CONTINUE;
018a98db
AK		 4128 break;
4129 case 0x32:
4130 /* rdmsr */
3fb1b5db 4131 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4132 emulate_gp(ctxt, 0);
da9cb575 4133 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4134 goto done;
018a98db
AK		 4135 } else {
4136 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4137 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4138 }
4139 rc = X86EMUL_CONTINUE;
018a98db 4140 break;
e99f0507 4141 case 0x34: /* sysenter */
3fb1b5db 4142 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4143 break;
4144 case 0x35: /* sysexit */
3fb1b5db 4145 rc = emulate_sysexit(ctxt, ops);
e99f0507 4146 break;
6aa8b732 4147 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4148 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4149 if (!test_cc(c->b, ctxt->eflags))
4150 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4151 break;
b2833e3c 4152 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4153 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4154 jmp_rel(c, c->src.val);
018a98db 4155 break;
ee45b58e
WY		 4156 case 0x90 ... 0x9f: /* setcc r/m8 */
4157 c->dst.val = test_cc(c->b, ctxt->eflags);
4158 break;
0934ac9d 4159 case 0xa0: /* push fs */
79168fd1 4160 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4161 break;
4162 case 0xa1: /* pop fs */
4163 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4164 break;
7de75248
NK		 4165 case 0xa3:
4166 bt: /* bt */
e4f8e039 4167 c->dst.type = OP_NONE;
e4e03ded
LV		 4168 /* only subword offset */
4169 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4170 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4171 break;
9bf8ea42
GT		 4172 case 0xa4: /* shld imm8, r, r/m */
4173 case 0xa5: /* shld cl, r, r/m */
4174 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4175 break;
0934ac9d 4176 case 0xa8: /* push gs */
79168fd1 4177 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4178 break;
4179 case 0xa9: /* pop gs */
4180 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4181 break;
7de75248
NK		 4182 case 0xab:
4183 bts: /* bts */
05f086f8 4184 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4185 break;
9bf8ea42
GT		 4186 case 0xac: /* shrd imm8, r, r/m */
4187 case 0xad: /* shrd cl, r, r/m */
4188 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4189 break;
2a7c5b8b
GC		 4190 case 0xae: /* clflush */
4191 break;
6aa8b732
AK		 4192 case 0xb0 ... 0xb1: /* cmpxchg */
4193 /*
4194 * Save real source value, then compare EAX against
4195 * destination.
4196 */
e4e03ded
LV		 4197 c->src.orig_val = c->src.val;
4198 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4199 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4200 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4201 /* Success: write back to memory. */
e4e03ded 4202 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4203 } else {
4204 /* Failure: write the value we saw to EAX. */
e4e03ded 4205 c->dst.type = OP_REG;
1a6440ae 4206 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4207 }
4208 break;
09b5f4d3
WY		 4209 case 0xb2: /* lss */
4210 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4211 break;
6aa8b732
AK		 4212 case 0xb3:
4213 btr: /* btr */
05f086f8 4214 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4215 break;
09b5f4d3
WY		 4216 case 0xb4: /* lfs */
4217 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4218 break;
4219 case 0xb5: /* lgs */
4220 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4221 break;
6aa8b732 4222 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4223 c->dst.bytes = c->op_bytes;
4224 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4225 : (u16) c->src.val;
6aa8b732 4226 break;
6aa8b732 4227 case 0xba: /* Grp8 */
e4e03ded 4228 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4229 case 0:
4230 goto bt;
4231 case 1:
4232 goto bts;
4233 case 2:
4234 goto btr;
4235 case 3:
4236 goto btc;
4237 }
4238 break;
7de75248
NK		 4239 case 0xbb:
4240 btc: /* btc */
05f086f8 4241 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4242 break;
d9574a25
WY		 4243 case 0xbc: { /* bsf */
4244 u8 zf;
4245 __asm__ ("bsf %2, %0; setz %1"
4246 : "=r"(c->dst.val), "=q"(zf)
4247 : "r"(c->src.val));
4248 ctxt->eflags &= ~X86_EFLAGS_ZF;
4249 if (zf) {
4250 ctxt->eflags |= X86_EFLAGS_ZF;
4251 c->dst.type = OP_NONE; /* Disable writeback. */
4252 }
4253 break;
4254 }
4255 case 0xbd: { /* bsr */
4256 u8 zf;
4257 __asm__ ("bsr %2, %0; setz %1"
4258 : "=r"(c->dst.val), "=q"(zf)
4259 : "r"(c->src.val));
4260 ctxt->eflags &= ~X86_EFLAGS_ZF;
4261 if (zf) {
4262 ctxt->eflags |= X86_EFLAGS_ZF;
4263 c->dst.type = OP_NONE; /* Disable writeback. */
4264 }
4265 break;
4266 }
6aa8b732 4267 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4268 c->dst.bytes = c->op_bytes;
4269 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4270 (s16) c->src.val;
6aa8b732 4271 break;
92f738a5
WY		 4272 case 0xc0 ... 0xc1: /* xadd */
4273 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4274 /* Write back the register source. */
4275 c->src.val = c->dst.orig_val;
4276 write_register_operand(&c->src);
4277 break;
a012e65a 4278 case 0xc3: /* movnti */
e4e03ded
LV		 4279 c->dst.bytes = c->op_bytes;
4280 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4281 (u64) c->src.val;
a012e65a 4282 break;
6aa8b732 4283 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4284 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4285 break;
91269b8f
AK		 4286 default:
4287 goto cannot_emulate;
6aa8b732 4288 }
7d9ddaed
AK		 4289
4290 if (rc != X86EMUL_CONTINUE)
4291 goto done;
4292
6aa8b732
AK		 4293 goto writeback;
4294
4295cannot_emulate:
a0c0ab2f 4296 return EMULATION_FAILED;
6aa8b732 4297}
Linux kernel - Deliverables
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