Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
6aa8b732 AK |
31 | /* |
32 | * Opcode effective-address decode tables. | |
33 | * Note that we only emulate instructions that have at least one memory | |
34 | * operand (excluding implicit stack references). We assume that stack | |
35 | * references and instruction fetches will never occur in special memory | |
36 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
37 | * not be handled. | |
38 | */ | |
39 | ||
40 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 41 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 42 | /* Destination operand type. */ |
ab85b12b AK |
43 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
44 | #define DstReg (2<<1) /* Register operand. */ | |
45 | #define DstMem (3<<1) /* Memory operand. */ | |
46 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
47 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
48 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 49 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 50 | #define DstMask (7<<1) |
6aa8b732 | 51 | /* Source operand type. */ |
9c9fddd0 | 52 | #define SrcNone (0<<4) /* No source operand. */ |
9c9fddd0 GT |
53 | #define SrcReg (1<<4) /* Register operand. */ |
54 | #define SrcMem (2<<4) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<4) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 59 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 60 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 61 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 62 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
63 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
64 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 65 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
b250e605 | 66 | #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */ |
341de7e3 | 67 | #define SrcMask (0xf<<4) |
6aa8b732 | 68 | /* Generic ModRM decode. */ |
341de7e3 | 69 | #define ModRM (1<<8) |
6aa8b732 | 70 | /* Destination is only written; never read. */ |
341de7e3 GN |
71 | #define Mov (1<<9) |
72 | #define BitOp (1<<10) | |
73 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
74 | #define String (1<<12) /* String instruction (rep capable) */ |
75 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
76 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
77 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
0d7cdee8 | 78 | #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */ |
1253791d | 79 | #define Sse (1<<17) /* SSE Vector instruction */ |
d8769fed | 80 | /* Misc flags */ |
d867162c | 81 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 82 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 83 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 84 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 85 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 86 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 87 | #define No64 (1<<28) |
0dc8d10f GT |
88 | /* Source 2 operand type */ |
89 | #define Src2None (0<<29) | |
90 | #define Src2CL (1<<29) | |
91 | #define Src2ImmByte (2<<29) | |
92 | #define Src2One (3<<29) | |
7db41eb7 | 93 | #define Src2Imm (4<<29) |
0dc8d10f | 94 | #define Src2Mask (7<<29) |
6aa8b732 | 95 | |
d0e53325 AK |
96 | #define X2(x...) x, x |
97 | #define X3(x...) X2(x), x | |
98 | #define X4(x...) X2(x), X2(x) | |
99 | #define X5(x...) X4(x), x | |
100 | #define X6(x...) X4(x), X2(x) | |
101 | #define X7(x...) X4(x), X3(x) | |
102 | #define X8(x...) X4(x), X4(x) | |
103 | #define X16(x...) X8(x), X8(x) | |
83babbca | 104 | |
d65b1dee AK |
105 | struct opcode { |
106 | u32 flags; | |
c4f035c6 | 107 | u8 intercept; |
120df890 | 108 | union { |
ef65c889 | 109 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
110 | struct opcode *group; |
111 | struct group_dual *gdual; | |
0d7cdee8 | 112 | struct gprefix *gprefix; |
120df890 AK |
113 | } u; |
114 | }; | |
115 | ||
116 | struct group_dual { | |
117 | struct opcode mod012[8]; | |
118 | struct opcode mod3[8]; | |
d65b1dee AK |
119 | }; |
120 | ||
0d7cdee8 AK |
121 | struct gprefix { |
122 | struct opcode pfx_no; | |
123 | struct opcode pfx_66; | |
124 | struct opcode pfx_f2; | |
125 | struct opcode pfx_f3; | |
126 | }; | |
127 | ||
6aa8b732 | 128 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
129 | #define EFLG_ID (1<<21) |
130 | #define EFLG_VIP (1<<20) | |
131 | #define EFLG_VIF (1<<19) | |
132 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
133 | #define EFLG_VM (1<<17) |
134 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
135 | #define EFLG_IOPL (3<<12) |
136 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
137 | #define EFLG_OF (1<<11) |
138 | #define EFLG_DF (1<<10) | |
b1d86143 | 139 | #define EFLG_IF (1<<9) |
d4c6a154 | 140 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
141 | #define EFLG_SF (1<<7) |
142 | #define EFLG_ZF (1<<6) | |
143 | #define EFLG_AF (1<<4) | |
144 | #define EFLG_PF (1<<2) | |
145 | #define EFLG_CF (1<<0) | |
146 | ||
62bd430e MG |
147 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
148 | #define EFLG_RESERVED_ONE_MASK 2 | |
149 | ||
6aa8b732 AK |
150 | /* |
151 | * Instruction emulation: | |
152 | * Most instructions are emulated directly via a fragment of inline assembly | |
153 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
154 | * any modified flags. | |
155 | */ | |
156 | ||
05b3e0c2 | 157 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
158 | #define _LO32 "k" /* force 32-bit operand */ |
159 | #define _STK "%%rsp" /* stack pointer */ | |
160 | #elif defined(__i386__) | |
161 | #define _LO32 "" /* force 32-bit operand */ | |
162 | #define _STK "%%esp" /* stack pointer */ | |
163 | #endif | |
164 | ||
165 | /* | |
166 | * These EFLAGS bits are restored from saved value during emulation, and | |
167 | * any changes are written back to the saved value after emulation. | |
168 | */ | |
169 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
170 | ||
171 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
172 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
173 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
174 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
175 | "push %"_tmp"; " \ | |
176 | "push %"_tmp"; " \ | |
177 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
178 | "andl %"_LO32 _tmp",("_STK"); " \ | |
179 | "pushf; " \ | |
180 | "notl %"_LO32 _tmp"; " \ | |
181 | "andl %"_LO32 _tmp",("_STK"); " \ | |
182 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
183 | "pop %"_tmp"; " \ | |
184 | "orl %"_LO32 _tmp",("_STK"); " \ | |
185 | "popf; " \ | |
186 | "pop %"_sav"; " | |
6aa8b732 AK |
187 | |
188 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
189 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
190 | /* _sav |= EFLAGS & _msk; */ \ | |
191 | "pushf; " \ | |
192 | "pop %"_tmp"; " \ | |
193 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
194 | "orl %"_LO32 _tmp",%"_sav"; " | |
195 | ||
dda96d8f AK |
196 | #ifdef CONFIG_X86_64 |
197 | #define ON64(x) x | |
198 | #else | |
199 | #define ON64(x) | |
200 | #endif | |
201 | ||
b3b3d25a | 202 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
203 | do { \ |
204 | __asm__ __volatile__ ( \ | |
205 | _PRE_EFLAGS("0", "4", "2") \ | |
206 | _op _suffix " %"_x"3,%1; " \ | |
207 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 208 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
209 | "=&r" (_tmp) \ |
210 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 211 | } while (0) |
6b7ad61f AK |
212 | |
213 | ||
6aa8b732 AK |
214 | /* Raw emulation: instruction has two explicit operands. */ |
215 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
216 | do { \ |
217 | unsigned long _tmp; \ | |
218 | \ | |
219 | switch ((_dst).bytes) { \ | |
220 | case 2: \ | |
b3b3d25a | 221 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
222 | break; \ |
223 | case 4: \ | |
b3b3d25a | 224 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
225 | break; \ |
226 | case 8: \ | |
b3b3d25a | 227 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
228 | break; \ |
229 | } \ | |
6aa8b732 AK |
230 | } while (0) |
231 | ||
232 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
233 | do { \ | |
6b7ad61f | 234 | unsigned long _tmp; \ |
d77c26fc | 235 | switch ((_dst).bytes) { \ |
6aa8b732 | 236 | case 1: \ |
b3b3d25a | 237 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
238 | break; \ |
239 | default: \ | |
240 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
241 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
242 | break; \ | |
243 | } \ | |
244 | } while (0) | |
245 | ||
246 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
247 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
248 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
249 | "b", "c", "b", "c", "b", "c", "b", "c") | |
250 | ||
251 | /* Source operand is byte, word, long or quad sized. */ | |
252 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
253 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
254 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
255 | ||
256 | /* Source operand is word, long or quad sized. */ | |
257 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
258 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
259 | "w", "r", _LO32, "r", "", "r") | |
260 | ||
d175226a GT |
261 | /* Instruction has three operands and one operand is stored in ECX register */ |
262 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
263 | do { \ | |
264 | unsigned long _tmp; \ | |
265 | _type _clv = (_cl).val; \ | |
266 | _type _srcv = (_src).val; \ | |
267 | _type _dstv = (_dst).val; \ | |
268 | \ | |
269 | __asm__ __volatile__ ( \ | |
270 | _PRE_EFLAGS("0", "5", "2") \ | |
271 | _op _suffix " %4,%1 \n" \ | |
272 | _POST_EFLAGS("0", "5", "2") \ | |
273 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
274 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
275 | ); \ | |
276 | \ | |
277 | (_cl).val = (unsigned long) _clv; \ | |
278 | (_src).val = (unsigned long) _srcv; \ | |
279 | (_dst).val = (unsigned long) _dstv; \ | |
280 | } while (0) | |
281 | ||
282 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
283 | do { \ | |
284 | switch ((_dst).bytes) { \ | |
285 | case 2: \ | |
286 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
287 | "w", unsigned short); \ | |
288 | break; \ | |
289 | case 4: \ | |
290 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
291 | "l", unsigned int); \ | |
292 | break; \ | |
293 | case 8: \ | |
294 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
295 | "q", unsigned long)); \ | |
296 | break; \ | |
297 | } \ | |
298 | } while (0) | |
299 | ||
dda96d8f | 300 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
301 | do { \ |
302 | unsigned long _tmp; \ | |
303 | \ | |
dda96d8f AK |
304 | __asm__ __volatile__ ( \ |
305 | _PRE_EFLAGS("0", "3", "2") \ | |
306 | _op _suffix " %1; " \ | |
307 | _POST_EFLAGS("0", "3", "2") \ | |
308 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
309 | "=&r" (_tmp) \ | |
310 | : "i" (EFLAGS_MASK)); \ | |
311 | } while (0) | |
312 | ||
313 | /* Instruction has only one explicit operand (no source operand). */ | |
314 | #define emulate_1op(_op, _dst, _eflags) \ | |
315 | do { \ | |
d77c26fc | 316 | switch ((_dst).bytes) { \ |
dda96d8f AK |
317 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
318 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
319 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
320 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
321 | } \ |
322 | } while (0) | |
323 | ||
3f9f53b0 MG |
324 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
325 | do { \ | |
326 | unsigned long _tmp; \ | |
327 | \ | |
328 | __asm__ __volatile__ ( \ | |
329 | _PRE_EFLAGS("0", "4", "1") \ | |
330 | _op _suffix " %5; " \ | |
331 | _POST_EFLAGS("0", "4", "1") \ | |
332 | : "=m" (_eflags), "=&r" (_tmp), \ | |
333 | "+a" (_rax), "+d" (_rdx) \ | |
334 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
335 | "a" (_rax), "d" (_rdx)); \ | |
336 | } while (0) | |
337 | ||
f6b3597b AK |
338 | #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \ |
339 | do { \ | |
340 | unsigned long _tmp; \ | |
341 | \ | |
342 | __asm__ __volatile__ ( \ | |
343 | _PRE_EFLAGS("0", "5", "1") \ | |
344 | "1: \n\t" \ | |
345 | _op _suffix " %6; " \ | |
346 | "2: \n\t" \ | |
347 | _POST_EFLAGS("0", "5", "1") \ | |
348 | ".pushsection .fixup,\"ax\" \n\t" \ | |
349 | "3: movb $1, %4 \n\t" \ | |
350 | "jmp 2b \n\t" \ | |
351 | ".popsection \n\t" \ | |
352 | _ASM_EXTABLE(1b, 3b) \ | |
353 | : "=m" (_eflags), "=&r" (_tmp), \ | |
354 | "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \ | |
355 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
356 | "a" (_rax), "d" (_rdx)); \ | |
357 | } while (0) | |
358 | ||
3f9f53b0 MG |
359 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
360 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
361 | do { \ | |
362 | switch((_src).bytes) { \ | |
363 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
364 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
365 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
366 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
367 | } \ | |
368 | } while (0) | |
369 | ||
f6b3597b AK |
370 | #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \ |
371 | do { \ | |
372 | switch((_src).bytes) { \ | |
373 | case 1: \ | |
374 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
375 | _eflags, "b", _ex); \ | |
376 | break; \ | |
377 | case 2: \ | |
378 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
379 | _eflags, "w", _ex); \ | |
380 | break; \ | |
381 | case 4: \ | |
382 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
383 | _eflags, "l", _ex); \ | |
384 | break; \ | |
385 | case 8: ON64( \ | |
386 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
387 | _eflags, "q", _ex)); \ | |
388 | break; \ | |
389 | } \ | |
390 | } while (0) | |
391 | ||
6aa8b732 AK |
392 | /* Fetch next part of the instruction being emulated. */ |
393 | #define insn_fetch(_type, _size, _eip) \ | |
394 | ({ unsigned long _x; \ | |
62266869 | 395 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 396 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
397 | goto done; \ |
398 | (_eip) += (_size); \ | |
399 | (_type)_x; \ | |
400 | }) | |
401 | ||
414e6277 GN |
402 | #define insn_fetch_arr(_arr, _size, _eip) \ |
403 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
404 | if (rc != X86EMUL_CONTINUE) \ | |
405 | goto done; \ | |
406 | (_eip) += (_size); \ | |
407 | }) | |
408 | ||
ddcb2885 HH |
409 | static inline unsigned long ad_mask(struct decode_cache *c) |
410 | { | |
411 | return (1UL << (c->ad_bytes << 3)) - 1; | |
412 | } | |
413 | ||
6aa8b732 | 414 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
415 | static inline unsigned long |
416 | address_mask(struct decode_cache *c, unsigned long reg) | |
417 | { | |
418 | if (c->ad_bytes == sizeof(unsigned long)) | |
419 | return reg; | |
420 | else | |
421 | return reg & ad_mask(c); | |
422 | } | |
423 | ||
424 | static inline unsigned long | |
90de84f5 | 425 | register_address(struct decode_cache *c, unsigned long reg) |
e4706772 | 426 | { |
90de84f5 | 427 | return address_mask(c, reg); |
e4706772 HH |
428 | } |
429 | ||
7a957275 HH |
430 | static inline void |
431 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
432 | { | |
433 | if (c->ad_bytes == sizeof(unsigned long)) | |
434 | *reg += inc; | |
435 | else | |
436 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
437 | } | |
6aa8b732 | 438 | |
7a957275 HH |
439 | static inline void jmp_rel(struct decode_cache *c, int rel) |
440 | { | |
441 | register_address_increment(c, &c->eip, rel); | |
442 | } | |
098c937b | 443 | |
7a5b56df AK |
444 | static void set_seg_override(struct decode_cache *c, int seg) |
445 | { | |
446 | c->has_seg_override = true; | |
447 | c->seg_override = seg; | |
448 | } | |
449 | ||
79168fd1 GN |
450 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
451 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
452 | { |
453 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
454 | return 0; | |
455 | ||
79168fd1 | 456 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
457 | } |
458 | ||
90de84f5 AK |
459 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt, |
460 | struct x86_emulate_ops *ops, | |
461 | struct decode_cache *c) | |
7a5b56df AK |
462 | { |
463 | if (!c->has_seg_override) | |
464 | return 0; | |
465 | ||
90de84f5 | 466 | return c->seg_override; |
7a5b56df AK |
467 | } |
468 | ||
90de84f5 AK |
469 | static ulong linear(struct x86_emulate_ctxt *ctxt, |
470 | struct segmented_address addr) | |
7a5b56df | 471 | { |
90de84f5 AK |
472 | struct decode_cache *c = &ctxt->decode; |
473 | ulong la; | |
7a5b56df | 474 | |
90de84f5 AK |
475 | la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea; |
476 | if (c->ad_bytes != 8) | |
477 | la &= (u32)-1; | |
478 | return la; | |
7a5b56df AK |
479 | } |
480 | ||
35d3d4a1 AK |
481 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
482 | u32 error, bool valid) | |
54b8486f | 483 | { |
da9cb575 AK |
484 | ctxt->exception.vector = vec; |
485 | ctxt->exception.error_code = error; | |
486 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 487 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
488 | } |
489 | ||
35d3d4a1 | 490 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 491 | { |
35d3d4a1 | 492 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
493 | } |
494 | ||
35d3d4a1 | 495 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 496 | { |
35d3d4a1 | 497 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
498 | } |
499 | ||
35d3d4a1 | 500 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 501 | { |
35d3d4a1 | 502 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
503 | } |
504 | ||
34d1f490 AK |
505 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
506 | { | |
35d3d4a1 | 507 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
508 | } |
509 | ||
1253791d AK |
510 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
511 | { | |
512 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
513 | } | |
514 | ||
62266869 AK |
515 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
516 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 517 | unsigned long eip, u8 *dest) |
62266869 AK |
518 | { |
519 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
520 | int rc; | |
2fb53ad8 | 521 | int size, cur_size; |
62266869 | 522 | |
2fb53ad8 AK |
523 | if (eip == fc->end) { |
524 | cur_size = fc->end - fc->start; | |
525 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
526 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
bcc55cba | 527 | size, ctxt->vcpu, &ctxt->exception); |
3e2815e9 | 528 | if (rc != X86EMUL_CONTINUE) |
62266869 | 529 | return rc; |
2fb53ad8 | 530 | fc->end += size; |
62266869 | 531 | } |
2fb53ad8 | 532 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 533 | return X86EMUL_CONTINUE; |
62266869 AK |
534 | } |
535 | ||
536 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
537 | struct x86_emulate_ops *ops, | |
538 | unsigned long eip, void *dest, unsigned size) | |
539 | { | |
3e2815e9 | 540 | int rc; |
62266869 | 541 | |
eb3c79e6 | 542 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 543 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 544 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
545 | while (size--) { |
546 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 547 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
548 | return rc; |
549 | } | |
3e2815e9 | 550 | return X86EMUL_CONTINUE; |
62266869 AK |
551 | } |
552 | ||
1e3c5cb0 RR |
553 | /* |
554 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
555 | * pointer into the block that addresses the relevant register. | |
556 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
557 | */ | |
558 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
559 | int highbyte_regs) | |
6aa8b732 AK |
560 | { |
561 | void *p; | |
562 | ||
563 | p = ®s[modrm_reg]; | |
564 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
565 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
566 | return p; | |
567 | } | |
568 | ||
569 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
570 | struct x86_emulate_ops *ops, | |
90de84f5 | 571 | struct segmented_address addr, |
6aa8b732 AK |
572 | u16 *size, unsigned long *address, int op_bytes) |
573 | { | |
574 | int rc; | |
575 | ||
576 | if (op_bytes == 2) | |
577 | op_bytes = 3; | |
578 | *address = 0; | |
90de84f5 | 579 | rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2, |
bcc55cba | 580 | ctxt->vcpu, &ctxt->exception); |
1b30eaa8 | 581 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 582 | return rc; |
30b31ab6 AK |
583 | addr.ea += 2; |
584 | rc = ops->read_std(linear(ctxt, addr), address, op_bytes, | |
bcc55cba | 585 | ctxt->vcpu, &ctxt->exception); |
6aa8b732 AK |
586 | return rc; |
587 | } | |
588 | ||
bbe9abbd NK |
589 | static int test_cc(unsigned int condition, unsigned int flags) |
590 | { | |
591 | int rc = 0; | |
592 | ||
593 | switch ((condition & 15) >> 1) { | |
594 | case 0: /* o */ | |
595 | rc |= (flags & EFLG_OF); | |
596 | break; | |
597 | case 1: /* b/c/nae */ | |
598 | rc |= (flags & EFLG_CF); | |
599 | break; | |
600 | case 2: /* z/e */ | |
601 | rc |= (flags & EFLG_ZF); | |
602 | break; | |
603 | case 3: /* be/na */ | |
604 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
605 | break; | |
606 | case 4: /* s */ | |
607 | rc |= (flags & EFLG_SF); | |
608 | break; | |
609 | case 5: /* p/pe */ | |
610 | rc |= (flags & EFLG_PF); | |
611 | break; | |
612 | case 7: /* le/ng */ | |
613 | rc |= (flags & EFLG_ZF); | |
614 | /* fall through */ | |
615 | case 6: /* l/nge */ | |
616 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
617 | break; | |
618 | } | |
619 | ||
620 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
621 | return (!!rc ^ (condition & 1)); | |
622 | } | |
623 | ||
91ff3cb4 AK |
624 | static void fetch_register_operand(struct operand *op) |
625 | { | |
626 | switch (op->bytes) { | |
627 | case 1: | |
628 | op->val = *(u8 *)op->addr.reg; | |
629 | break; | |
630 | case 2: | |
631 | op->val = *(u16 *)op->addr.reg; | |
632 | break; | |
633 | case 4: | |
634 | op->val = *(u32 *)op->addr.reg; | |
635 | break; | |
636 | case 8: | |
637 | op->val = *(u64 *)op->addr.reg; | |
638 | break; | |
639 | } | |
640 | } | |
641 | ||
1253791d AK |
642 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
643 | { | |
644 | ctxt->ops->get_fpu(ctxt); | |
645 | switch (reg) { | |
646 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
647 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
648 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
649 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
650 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
651 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
652 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
653 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
654 | #ifdef CONFIG_X86_64 | |
655 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
656 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
657 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
658 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
659 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
660 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
661 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
662 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
663 | #endif | |
664 | default: BUG(); | |
665 | } | |
666 | ctxt->ops->put_fpu(ctxt); | |
667 | } | |
668 | ||
669 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
670 | int reg) | |
671 | { | |
672 | ctxt->ops->get_fpu(ctxt); | |
673 | switch (reg) { | |
674 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
675 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
676 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
677 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
678 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
679 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
680 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
681 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
682 | #ifdef CONFIG_X86_64 | |
683 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
684 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
685 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
686 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
687 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
688 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
689 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
690 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
691 | #endif | |
692 | default: BUG(); | |
693 | } | |
694 | ctxt->ops->put_fpu(ctxt); | |
695 | } | |
696 | ||
697 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
698 | struct operand *op, | |
3c118e24 | 699 | struct decode_cache *c, |
3c118e24 AK |
700 | int inhibit_bytereg) |
701 | { | |
33615aa9 | 702 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 703 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
704 | |
705 | if (!(c->d & ModRM)) | |
706 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
1253791d AK |
707 | |
708 | if (c->d & Sse) { | |
709 | op->type = OP_XMM; | |
710 | op->bytes = 16; | |
711 | op->addr.xmm = reg; | |
712 | read_sse_reg(ctxt, &op->vec_val, reg); | |
713 | return; | |
714 | } | |
715 | ||
3c118e24 AK |
716 | op->type = OP_REG; |
717 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 718 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
719 | op->bytes = 1; |
720 | } else { | |
1a6440ae | 721 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 722 | op->bytes = c->op_bytes; |
3c118e24 | 723 | } |
91ff3cb4 | 724 | fetch_register_operand(op); |
3c118e24 AK |
725 | op->orig_val = op->val; |
726 | } | |
727 | ||
1c73ef66 | 728 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
729 | struct x86_emulate_ops *ops, |
730 | struct operand *op) | |
1c73ef66 AK |
731 | { |
732 | struct decode_cache *c = &ctxt->decode; | |
733 | u8 sib; | |
f5b4edcd | 734 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 735 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 736 | ulong modrm_ea = 0; |
1c73ef66 AK |
737 | |
738 | if (c->rex_prefix) { | |
739 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
740 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
741 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
742 | } | |
743 | ||
744 | c->modrm = insn_fetch(u8, 1, c->eip); | |
745 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
746 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
747 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 748 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
749 | |
750 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
751 | op->type = OP_REG; |
752 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
753 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 754 | c->regs, c->d & ByteOp); |
1253791d AK |
755 | if (c->d & Sse) { |
756 | op->type = OP_XMM; | |
757 | op->bytes = 16; | |
758 | op->addr.xmm = c->modrm_rm; | |
759 | read_sse_reg(ctxt, &op->vec_val, c->modrm_rm); | |
760 | return rc; | |
761 | } | |
2dbd0dd7 | 762 | fetch_register_operand(op); |
1c73ef66 AK |
763 | return rc; |
764 | } | |
765 | ||
2dbd0dd7 AK |
766 | op->type = OP_MEM; |
767 | ||
1c73ef66 AK |
768 | if (c->ad_bytes == 2) { |
769 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
770 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
771 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
772 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
773 | ||
774 | /* 16-bit ModR/M decode. */ | |
775 | switch (c->modrm_mod) { | |
776 | case 0: | |
777 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 778 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
779 | break; |
780 | case 1: | |
2dbd0dd7 | 781 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
782 | break; |
783 | case 2: | |
2dbd0dd7 | 784 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
785 | break; |
786 | } | |
787 | switch (c->modrm_rm) { | |
788 | case 0: | |
2dbd0dd7 | 789 | modrm_ea += bx + si; |
1c73ef66 AK |
790 | break; |
791 | case 1: | |
2dbd0dd7 | 792 | modrm_ea += bx + di; |
1c73ef66 AK |
793 | break; |
794 | case 2: | |
2dbd0dd7 | 795 | modrm_ea += bp + si; |
1c73ef66 AK |
796 | break; |
797 | case 3: | |
2dbd0dd7 | 798 | modrm_ea += bp + di; |
1c73ef66 AK |
799 | break; |
800 | case 4: | |
2dbd0dd7 | 801 | modrm_ea += si; |
1c73ef66 AK |
802 | break; |
803 | case 5: | |
2dbd0dd7 | 804 | modrm_ea += di; |
1c73ef66 AK |
805 | break; |
806 | case 6: | |
807 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 808 | modrm_ea += bp; |
1c73ef66 AK |
809 | break; |
810 | case 7: | |
2dbd0dd7 | 811 | modrm_ea += bx; |
1c73ef66 AK |
812 | break; |
813 | } | |
814 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
815 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 816 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 817 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
818 | } else { |
819 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 820 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
821 | sib = insn_fetch(u8, 1, c->eip); |
822 | index_reg |= (sib >> 3) & 7; | |
823 | base_reg |= sib & 7; | |
824 | scale = sib >> 6; | |
825 | ||
dc71d0f1 | 826 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 827 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 828 | else |
2dbd0dd7 | 829 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 830 | if (index_reg != 4) |
2dbd0dd7 | 831 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
832 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
833 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 834 | c->rip_relative = 1; |
84411d85 | 835 | } else |
2dbd0dd7 | 836 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
837 | switch (c->modrm_mod) { |
838 | case 0: | |
839 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 840 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
841 | break; |
842 | case 1: | |
2dbd0dd7 | 843 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
844 | break; |
845 | case 2: | |
2dbd0dd7 | 846 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
847 | break; |
848 | } | |
849 | } | |
90de84f5 | 850 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
851 | done: |
852 | return rc; | |
853 | } | |
854 | ||
855 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
856 | struct x86_emulate_ops *ops, |
857 | struct operand *op) | |
1c73ef66 AK |
858 | { |
859 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 860 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 861 | |
2dbd0dd7 | 862 | op->type = OP_MEM; |
1c73ef66 AK |
863 | switch (c->ad_bytes) { |
864 | case 2: | |
90de84f5 | 865 | op->addr.mem.ea = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
866 | break; |
867 | case 4: | |
90de84f5 | 868 | op->addr.mem.ea = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
869 | break; |
870 | case 8: | |
90de84f5 | 871 | op->addr.mem.ea = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
872 | break; |
873 | } | |
874 | done: | |
875 | return rc; | |
876 | } | |
877 | ||
35c843c4 WY |
878 | static void fetch_bit_operand(struct decode_cache *c) |
879 | { | |
7129eeca | 880 | long sv = 0, mask; |
35c843c4 | 881 | |
3885f18f | 882 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
883 | mask = ~(c->dst.bytes * 8 - 1); |
884 | ||
885 | if (c->src.bytes == 2) | |
886 | sv = (s16)c->src.val & (s16)mask; | |
887 | else if (c->src.bytes == 4) | |
888 | sv = (s32)c->src.val & (s32)mask; | |
889 | ||
90de84f5 | 890 | c->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 891 | } |
ba7ff2b7 WY |
892 | |
893 | /* only subword offset */ | |
894 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
895 | } |
896 | ||
dde7e6d1 AK |
897 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
898 | struct x86_emulate_ops *ops, | |
899 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 900 | { |
dde7e6d1 AK |
901 | int rc; |
902 | struct read_cache *mc = &ctxt->decode.mem_read; | |
6aa8b732 | 903 | |
dde7e6d1 AK |
904 | while (size) { |
905 | int n = min(size, 8u); | |
906 | size -= n; | |
907 | if (mc->pos < mc->end) | |
908 | goto read_cached; | |
5cd21917 | 909 | |
bcc55cba AK |
910 | rc = ops->read_emulated(addr, mc->data + mc->end, n, |
911 | &ctxt->exception, ctxt->vcpu); | |
dde7e6d1 AK |
912 | if (rc != X86EMUL_CONTINUE) |
913 | return rc; | |
914 | mc->end += n; | |
6aa8b732 | 915 | |
dde7e6d1 AK |
916 | read_cached: |
917 | memcpy(dest, mc->data + mc->pos, n); | |
918 | mc->pos += n; | |
919 | dest += n; | |
920 | addr += n; | |
6aa8b732 | 921 | } |
dde7e6d1 AK |
922 | return X86EMUL_CONTINUE; |
923 | } | |
6aa8b732 | 924 | |
dde7e6d1 AK |
925 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
926 | struct x86_emulate_ops *ops, | |
927 | unsigned int size, unsigned short port, | |
928 | void *dest) | |
929 | { | |
930 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 931 | |
dde7e6d1 AK |
932 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
933 | struct decode_cache *c = &ctxt->decode; | |
934 | unsigned int in_page, n; | |
935 | unsigned int count = c->rep_prefix ? | |
936 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
937 | in_page = (ctxt->eflags & EFLG_DF) ? | |
938 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
939 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
940 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
941 | count); | |
942 | if (n == 0) | |
943 | n = 1; | |
944 | rc->pos = rc->end = 0; | |
945 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
946 | return 0; | |
947 | rc->end = n * size; | |
6aa8b732 AK |
948 | } |
949 | ||
dde7e6d1 AK |
950 | memcpy(dest, rc->data + rc->pos, size); |
951 | rc->pos += size; | |
952 | return 1; | |
953 | } | |
6aa8b732 | 954 | |
dde7e6d1 AK |
955 | static u32 desc_limit_scaled(struct desc_struct *desc) |
956 | { | |
957 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 958 | |
dde7e6d1 AK |
959 | return desc->g ? (limit << 12) | 0xfff : limit; |
960 | } | |
6aa8b732 | 961 | |
dde7e6d1 AK |
962 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
963 | struct x86_emulate_ops *ops, | |
964 | u16 selector, struct desc_ptr *dt) | |
965 | { | |
966 | if (selector & 1 << 2) { | |
967 | struct desc_struct desc; | |
968 | memset (dt, 0, sizeof *dt); | |
5601d05b GN |
969 | if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR, |
970 | ctxt->vcpu)) | |
dde7e6d1 | 971 | return; |
e09d082c | 972 | |
dde7e6d1 AK |
973 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
974 | dt->address = get_desc_base(&desc); | |
975 | } else | |
976 | ops->get_gdt(dt, ctxt->vcpu); | |
977 | } | |
120df890 | 978 | |
dde7e6d1 AK |
979 | /* allowed just for 8 bytes segments */ |
980 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
981 | struct x86_emulate_ops *ops, | |
982 | u16 selector, struct desc_struct *desc) | |
983 | { | |
984 | struct desc_ptr dt; | |
985 | u16 index = selector >> 3; | |
986 | int ret; | |
dde7e6d1 | 987 | ulong addr; |
120df890 | 988 | |
dde7e6d1 | 989 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 990 | |
35d3d4a1 AK |
991 | if (dt.size < index * 8 + 7) |
992 | return emulate_gp(ctxt, selector & 0xfffc); | |
dde7e6d1 | 993 | addr = dt.address + index * 8; |
bcc55cba AK |
994 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, |
995 | &ctxt->exception); | |
e09d082c | 996 | |
dde7e6d1 AK |
997 | return ret; |
998 | } | |
ef65c889 | 999 | |
dde7e6d1 AK |
1000 | /* allowed just for 8 bytes segments */ |
1001 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1002 | struct x86_emulate_ops *ops, | |
1003 | u16 selector, struct desc_struct *desc) | |
1004 | { | |
1005 | struct desc_ptr dt; | |
1006 | u16 index = selector >> 3; | |
dde7e6d1 AK |
1007 | ulong addr; |
1008 | int ret; | |
6aa8b732 | 1009 | |
dde7e6d1 | 1010 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 1011 | |
35d3d4a1 AK |
1012 | if (dt.size < index * 8 + 7) |
1013 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1014 | |
dde7e6d1 | 1015 | addr = dt.address + index * 8; |
bcc55cba AK |
1016 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, |
1017 | &ctxt->exception); | |
c7e75a3d | 1018 | |
dde7e6d1 AK |
1019 | return ret; |
1020 | } | |
c7e75a3d | 1021 | |
5601d05b | 1022 | /* Does not support long mode */ |
dde7e6d1 AK |
1023 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
1024 | struct x86_emulate_ops *ops, | |
1025 | u16 selector, int seg) | |
1026 | { | |
1027 | struct desc_struct seg_desc; | |
1028 | u8 dpl, rpl, cpl; | |
1029 | unsigned err_vec = GP_VECTOR; | |
1030 | u32 err_code = 0; | |
1031 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1032 | int ret; | |
69f55cb1 | 1033 | |
dde7e6d1 | 1034 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1035 | |
dde7e6d1 AK |
1036 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1037 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1038 | /* set real mode segment descriptor */ | |
1039 | set_desc_base(&seg_desc, selector << 4); | |
1040 | set_desc_limit(&seg_desc, 0xffff); | |
1041 | seg_desc.type = 3; | |
1042 | seg_desc.p = 1; | |
1043 | seg_desc.s = 1; | |
1044 | goto load; | |
1045 | } | |
1046 | ||
1047 | /* NULL selector is not valid for TR, CS and SS */ | |
1048 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1049 | && null_selector) | |
1050 | goto exception; | |
1051 | ||
1052 | /* TR should be in GDT only */ | |
1053 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1054 | goto exception; | |
1055 | ||
1056 | if (null_selector) /* for NULL selector skip all following checks */ | |
1057 | goto load; | |
1058 | ||
1059 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1060 | if (ret != X86EMUL_CONTINUE) | |
1061 | return ret; | |
1062 | ||
1063 | err_code = selector & 0xfffc; | |
1064 | err_vec = GP_VECTOR; | |
1065 | ||
1066 | /* can't load system descriptor into segment selecor */ | |
1067 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1068 | goto exception; | |
1069 | ||
1070 | if (!seg_desc.p) { | |
1071 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1072 | goto exception; | |
1073 | } | |
1074 | ||
1075 | rpl = selector & 3; | |
1076 | dpl = seg_desc.dpl; | |
1077 | cpl = ops->cpl(ctxt->vcpu); | |
1078 | ||
1079 | switch (seg) { | |
1080 | case VCPU_SREG_SS: | |
1081 | /* | |
1082 | * segment is not a writable data segment or segment | |
1083 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1084 | */ | |
1085 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1086 | goto exception; | |
6aa8b732 | 1087 | break; |
dde7e6d1 AK |
1088 | case VCPU_SREG_CS: |
1089 | if (!(seg_desc.type & 8)) | |
1090 | goto exception; | |
1091 | ||
1092 | if (seg_desc.type & 4) { | |
1093 | /* conforming */ | |
1094 | if (dpl > cpl) | |
1095 | goto exception; | |
1096 | } else { | |
1097 | /* nonconforming */ | |
1098 | if (rpl > cpl || dpl != cpl) | |
1099 | goto exception; | |
1100 | } | |
1101 | /* CS(RPL) <- CPL */ | |
1102 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1103 | break; |
dde7e6d1 AK |
1104 | case VCPU_SREG_TR: |
1105 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1106 | goto exception; | |
1107 | break; | |
1108 | case VCPU_SREG_LDTR: | |
1109 | if (seg_desc.s || seg_desc.type != 2) | |
1110 | goto exception; | |
1111 | break; | |
1112 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1113 | /* |
dde7e6d1 AK |
1114 | * segment is not a data or readable code segment or |
1115 | * ((segment is a data or nonconforming code segment) | |
1116 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1117 | */ |
dde7e6d1 AK |
1118 | if ((seg_desc.type & 0xa) == 0x8 || |
1119 | (((seg_desc.type & 0xc) != 0xc) && | |
1120 | (rpl > dpl && cpl > dpl))) | |
1121 | goto exception; | |
6aa8b732 | 1122 | break; |
dde7e6d1 AK |
1123 | } |
1124 | ||
1125 | if (seg_desc.s) { | |
1126 | /* mark segment as accessed */ | |
1127 | seg_desc.type |= 1; | |
1128 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1129 | if (ret != X86EMUL_CONTINUE) | |
1130 | return ret; | |
1131 | } | |
1132 | load: | |
1133 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
5601d05b | 1134 | ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu); |
dde7e6d1 AK |
1135 | return X86EMUL_CONTINUE; |
1136 | exception: | |
1137 | emulate_exception(ctxt, err_vec, err_code, true); | |
1138 | return X86EMUL_PROPAGATE_FAULT; | |
1139 | } | |
1140 | ||
31be40b3 WY |
1141 | static void write_register_operand(struct operand *op) |
1142 | { | |
1143 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1144 | switch (op->bytes) { | |
1145 | case 1: | |
1146 | *(u8 *)op->addr.reg = (u8)op->val; | |
1147 | break; | |
1148 | case 2: | |
1149 | *(u16 *)op->addr.reg = (u16)op->val; | |
1150 | break; | |
1151 | case 4: | |
1152 | *op->addr.reg = (u32)op->val; | |
1153 | break; /* 64b: zero-extend */ | |
1154 | case 8: | |
1155 | *op->addr.reg = op->val; | |
1156 | break; | |
1157 | } | |
1158 | } | |
1159 | ||
dde7e6d1 AK |
1160 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1161 | struct x86_emulate_ops *ops) | |
1162 | { | |
1163 | int rc; | |
1164 | struct decode_cache *c = &ctxt->decode; | |
dde7e6d1 AK |
1165 | |
1166 | switch (c->dst.type) { | |
1167 | case OP_REG: | |
31be40b3 | 1168 | write_register_operand(&c->dst); |
6aa8b732 | 1169 | break; |
dde7e6d1 AK |
1170 | case OP_MEM: |
1171 | if (c->lock_prefix) | |
1172 | rc = ops->cmpxchg_emulated( | |
90de84f5 | 1173 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1174 | &c->dst.orig_val, |
1175 | &c->dst.val, | |
1176 | c->dst.bytes, | |
bcc55cba | 1177 | &ctxt->exception, |
dde7e6d1 | 1178 | ctxt->vcpu); |
341de7e3 | 1179 | else |
dde7e6d1 | 1180 | rc = ops->write_emulated( |
90de84f5 | 1181 | linear(ctxt, c->dst.addr.mem), |
dde7e6d1 AK |
1182 | &c->dst.val, |
1183 | c->dst.bytes, | |
bcc55cba | 1184 | &ctxt->exception, |
dde7e6d1 | 1185 | ctxt->vcpu); |
dde7e6d1 AK |
1186 | if (rc != X86EMUL_CONTINUE) |
1187 | return rc; | |
a682e354 | 1188 | break; |
1253791d AK |
1189 | case OP_XMM: |
1190 | write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm); | |
1191 | break; | |
dde7e6d1 AK |
1192 | case OP_NONE: |
1193 | /* no writeback */ | |
414e6277 | 1194 | break; |
dde7e6d1 | 1195 | default: |
414e6277 | 1196 | break; |
6aa8b732 | 1197 | } |
dde7e6d1 AK |
1198 | return X86EMUL_CONTINUE; |
1199 | } | |
6aa8b732 | 1200 | |
dde7e6d1 AK |
1201 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1202 | struct x86_emulate_ops *ops) | |
1203 | { | |
1204 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1205 | |
dde7e6d1 AK |
1206 | c->dst.type = OP_MEM; |
1207 | c->dst.bytes = c->op_bytes; | |
1208 | c->dst.val = c->src.val; | |
1209 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
90de84f5 AK |
1210 | c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1211 | c->dst.addr.mem.seg = VCPU_SREG_SS; | |
dde7e6d1 | 1212 | } |
69f55cb1 | 1213 | |
dde7e6d1 AK |
1214 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1215 | struct x86_emulate_ops *ops, | |
1216 | void *dest, int len) | |
1217 | { | |
1218 | struct decode_cache *c = &ctxt->decode; | |
1219 | int rc; | |
90de84f5 | 1220 | struct segmented_address addr; |
8b4caf66 | 1221 | |
90de84f5 AK |
1222 | addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1223 | addr.seg = VCPU_SREG_SS; | |
1224 | rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len); | |
dde7e6d1 AK |
1225 | if (rc != X86EMUL_CONTINUE) |
1226 | return rc; | |
1227 | ||
1228 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1229 | return rc; | |
8b4caf66 LV |
1230 | } |
1231 | ||
dde7e6d1 AK |
1232 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1233 | struct x86_emulate_ops *ops, | |
1234 | void *dest, int len) | |
9de41573 GN |
1235 | { |
1236 | int rc; | |
dde7e6d1 AK |
1237 | unsigned long val, change_mask; |
1238 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1239 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1240 | |
dde7e6d1 AK |
1241 | rc = emulate_pop(ctxt, ops, &val, len); |
1242 | if (rc != X86EMUL_CONTINUE) | |
1243 | return rc; | |
9de41573 | 1244 | |
dde7e6d1 AK |
1245 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1246 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1247 | |
dde7e6d1 AK |
1248 | switch(ctxt->mode) { |
1249 | case X86EMUL_MODE_PROT64: | |
1250 | case X86EMUL_MODE_PROT32: | |
1251 | case X86EMUL_MODE_PROT16: | |
1252 | if (cpl == 0) | |
1253 | change_mask |= EFLG_IOPL; | |
1254 | if (cpl <= iopl) | |
1255 | change_mask |= EFLG_IF; | |
1256 | break; | |
1257 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1258 | if (iopl < 3) |
1259 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1260 | change_mask |= EFLG_IF; |
1261 | break; | |
1262 | default: /* real mode */ | |
1263 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1264 | break; | |
9de41573 | 1265 | } |
dde7e6d1 AK |
1266 | |
1267 | *(unsigned long *)dest = | |
1268 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1269 | ||
1270 | return rc; | |
9de41573 GN |
1271 | } |
1272 | ||
dde7e6d1 AK |
1273 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1274 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1275 | { |
dde7e6d1 | 1276 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1277 | |
dde7e6d1 | 1278 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1279 | |
dde7e6d1 | 1280 | emulate_push(ctxt, ops); |
7b262e90 GN |
1281 | } |
1282 | ||
dde7e6d1 AK |
1283 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1284 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1285 | { |
dde7e6d1 AK |
1286 | struct decode_cache *c = &ctxt->decode; |
1287 | unsigned long selector; | |
1288 | int rc; | |
38ba30ba | 1289 | |
dde7e6d1 AK |
1290 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1291 | if (rc != X86EMUL_CONTINUE) | |
1292 | return rc; | |
1293 | ||
1294 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1295 | return rc; | |
38ba30ba GN |
1296 | } |
1297 | ||
dde7e6d1 AK |
1298 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1299 | struct x86_emulate_ops *ops) | |
38ba30ba | 1300 | { |
dde7e6d1 AK |
1301 | struct decode_cache *c = &ctxt->decode; |
1302 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1303 | int rc = X86EMUL_CONTINUE; | |
1304 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1305 | |
dde7e6d1 AK |
1306 | while (reg <= VCPU_REGS_RDI) { |
1307 | (reg == VCPU_REGS_RSP) ? | |
1308 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1309 | |
dde7e6d1 | 1310 | emulate_push(ctxt, ops); |
38ba30ba | 1311 | |
dde7e6d1 AK |
1312 | rc = writeback(ctxt, ops); |
1313 | if (rc != X86EMUL_CONTINUE) | |
1314 | return rc; | |
38ba30ba | 1315 | |
dde7e6d1 | 1316 | ++reg; |
38ba30ba | 1317 | } |
38ba30ba | 1318 | |
dde7e6d1 AK |
1319 | /* Disable writeback. */ |
1320 | c->dst.type = OP_NONE; | |
1321 | ||
1322 | return rc; | |
38ba30ba GN |
1323 | } |
1324 | ||
dde7e6d1 AK |
1325 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1326 | struct x86_emulate_ops *ops) | |
38ba30ba | 1327 | { |
dde7e6d1 AK |
1328 | struct decode_cache *c = &ctxt->decode; |
1329 | int rc = X86EMUL_CONTINUE; | |
1330 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1331 | |
dde7e6d1 AK |
1332 | while (reg >= VCPU_REGS_RAX) { |
1333 | if (reg == VCPU_REGS_RSP) { | |
1334 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1335 | c->op_bytes); | |
1336 | --reg; | |
1337 | } | |
38ba30ba | 1338 | |
dde7e6d1 AK |
1339 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1340 | if (rc != X86EMUL_CONTINUE) | |
1341 | break; | |
1342 | --reg; | |
38ba30ba | 1343 | } |
dde7e6d1 | 1344 | return rc; |
38ba30ba GN |
1345 | } |
1346 | ||
6e154e56 MG |
1347 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1348 | struct x86_emulate_ops *ops, int irq) | |
1349 | { | |
1350 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1351 | int rc; |
6e154e56 MG |
1352 | struct desc_ptr dt; |
1353 | gva_t cs_addr; | |
1354 | gva_t eip_addr; | |
1355 | u16 cs, eip; | |
6e154e56 MG |
1356 | |
1357 | /* TODO: Add limit checks */ | |
1358 | c->src.val = ctxt->eflags; | |
1359 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1360 | rc = writeback(ctxt, ops); |
1361 | if (rc != X86EMUL_CONTINUE) | |
1362 | return rc; | |
6e154e56 MG |
1363 | |
1364 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1365 | ||
1366 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1367 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1368 | rc = writeback(ctxt, ops); |
1369 | if (rc != X86EMUL_CONTINUE) | |
1370 | return rc; | |
6e154e56 MG |
1371 | |
1372 | c->src.val = c->eip; | |
1373 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1374 | rc = writeback(ctxt, ops); |
1375 | if (rc != X86EMUL_CONTINUE) | |
1376 | return rc; | |
1377 | ||
1378 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1379 | |
1380 | ops->get_idt(&dt, ctxt->vcpu); | |
1381 | ||
1382 | eip_addr = dt.address + (irq << 2); | |
1383 | cs_addr = dt.address + (irq << 2) + 2; | |
1384 | ||
bcc55cba | 1385 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1386 | if (rc != X86EMUL_CONTINUE) |
1387 | return rc; | |
1388 | ||
bcc55cba | 1389 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1390 | if (rc != X86EMUL_CONTINUE) |
1391 | return rc; | |
1392 | ||
1393 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1394 | if (rc != X86EMUL_CONTINUE) | |
1395 | return rc; | |
1396 | ||
1397 | c->eip = eip; | |
1398 | ||
1399 | return rc; | |
1400 | } | |
1401 | ||
1402 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1403 | struct x86_emulate_ops *ops, int irq) | |
1404 | { | |
1405 | switch(ctxt->mode) { | |
1406 | case X86EMUL_MODE_REAL: | |
1407 | return emulate_int_real(ctxt, ops, irq); | |
1408 | case X86EMUL_MODE_VM86: | |
1409 | case X86EMUL_MODE_PROT16: | |
1410 | case X86EMUL_MODE_PROT32: | |
1411 | case X86EMUL_MODE_PROT64: | |
1412 | default: | |
1413 | /* Protected mode interrupts unimplemented yet */ | |
1414 | return X86EMUL_UNHANDLEABLE; | |
1415 | } | |
1416 | } | |
1417 | ||
dde7e6d1 AK |
1418 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1419 | struct x86_emulate_ops *ops) | |
38ba30ba | 1420 | { |
dde7e6d1 AK |
1421 | struct decode_cache *c = &ctxt->decode; |
1422 | int rc = X86EMUL_CONTINUE; | |
1423 | unsigned long temp_eip = 0; | |
1424 | unsigned long temp_eflags = 0; | |
1425 | unsigned long cs = 0; | |
1426 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1427 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1428 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1429 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1430 | |
dde7e6d1 | 1431 | /* TODO: Add stack limit check */ |
38ba30ba | 1432 | |
dde7e6d1 | 1433 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1434 | |
dde7e6d1 AK |
1435 | if (rc != X86EMUL_CONTINUE) |
1436 | return rc; | |
38ba30ba | 1437 | |
35d3d4a1 AK |
1438 | if (temp_eip & ~0xffff) |
1439 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1440 | |
dde7e6d1 | 1441 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1442 | |
dde7e6d1 AK |
1443 | if (rc != X86EMUL_CONTINUE) |
1444 | return rc; | |
38ba30ba | 1445 | |
dde7e6d1 | 1446 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1447 | |
dde7e6d1 AK |
1448 | if (rc != X86EMUL_CONTINUE) |
1449 | return rc; | |
38ba30ba | 1450 | |
dde7e6d1 | 1451 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1452 | |
dde7e6d1 AK |
1453 | if (rc != X86EMUL_CONTINUE) |
1454 | return rc; | |
38ba30ba | 1455 | |
dde7e6d1 | 1456 | c->eip = temp_eip; |
38ba30ba | 1457 | |
38ba30ba | 1458 | |
dde7e6d1 AK |
1459 | if (c->op_bytes == 4) |
1460 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1461 | else if (c->op_bytes == 2) { | |
1462 | ctxt->eflags &= ~0xffff; | |
1463 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1464 | } |
dde7e6d1 AK |
1465 | |
1466 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1467 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1468 | ||
1469 | return rc; | |
38ba30ba GN |
1470 | } |
1471 | ||
dde7e6d1 AK |
1472 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1473 | struct x86_emulate_ops* ops) | |
c37eda13 | 1474 | { |
dde7e6d1 AK |
1475 | switch(ctxt->mode) { |
1476 | case X86EMUL_MODE_REAL: | |
1477 | return emulate_iret_real(ctxt, ops); | |
1478 | case X86EMUL_MODE_VM86: | |
1479 | case X86EMUL_MODE_PROT16: | |
1480 | case X86EMUL_MODE_PROT32: | |
1481 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1482 | default: |
dde7e6d1 AK |
1483 | /* iret from protected mode unimplemented yet */ |
1484 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1485 | } |
c37eda13 WY |
1486 | } |
1487 | ||
dde7e6d1 | 1488 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1489 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1490 | { |
1491 | struct decode_cache *c = &ctxt->decode; | |
1492 | ||
dde7e6d1 | 1493 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1494 | } |
1495 | ||
dde7e6d1 | 1496 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1497 | { |
05f086f8 | 1498 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1499 | switch (c->modrm_reg) { |
1500 | case 0: /* rol */ | |
05f086f8 | 1501 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1502 | break; |
1503 | case 1: /* ror */ | |
05f086f8 | 1504 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1505 | break; |
1506 | case 2: /* rcl */ | |
05f086f8 | 1507 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1508 | break; |
1509 | case 3: /* rcr */ | |
05f086f8 | 1510 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1511 | break; |
1512 | case 4: /* sal/shl */ | |
1513 | case 6: /* sal/shl */ | |
05f086f8 | 1514 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1515 | break; |
1516 | case 5: /* shr */ | |
05f086f8 | 1517 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1518 | break; |
1519 | case 7: /* sar */ | |
05f086f8 | 1520 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1521 | break; |
1522 | } | |
1523 | } | |
1524 | ||
1525 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1526 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1527 | { |
1528 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1529 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1530 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
34d1f490 | 1531 | u8 de = 0; |
8cdbd2c9 LV |
1532 | |
1533 | switch (c->modrm_reg) { | |
1534 | case 0 ... 1: /* test */ | |
05f086f8 | 1535 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1536 | break; |
1537 | case 2: /* not */ | |
1538 | c->dst.val = ~c->dst.val; | |
1539 | break; | |
1540 | case 3: /* neg */ | |
05f086f8 | 1541 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1542 | break; |
3f9f53b0 MG |
1543 | case 4: /* mul */ |
1544 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1545 | break; | |
1546 | case 5: /* imul */ | |
1547 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1548 | break; | |
1549 | case 6: /* div */ | |
34d1f490 AK |
1550 | emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx, |
1551 | ctxt->eflags, de); | |
3f9f53b0 MG |
1552 | break; |
1553 | case 7: /* idiv */ | |
34d1f490 AK |
1554 | emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx, |
1555 | ctxt->eflags, de); | |
3f9f53b0 | 1556 | break; |
8cdbd2c9 | 1557 | default: |
8c5eee30 | 1558 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1559 | } |
34d1f490 AK |
1560 | if (de) |
1561 | return emulate_de(ctxt); | |
8c5eee30 | 1562 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1563 | } |
1564 | ||
1565 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1566 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1567 | { |
1568 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1569 | |
1570 | switch (c->modrm_reg) { | |
1571 | case 0: /* inc */ | |
05f086f8 | 1572 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1573 | break; |
1574 | case 1: /* dec */ | |
05f086f8 | 1575 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1576 | break; |
d19292e4 MG |
1577 | case 2: /* call near abs */ { |
1578 | long int old_eip; | |
1579 | old_eip = c->eip; | |
1580 | c->eip = c->src.val; | |
1581 | c->src.val = old_eip; | |
79168fd1 | 1582 | emulate_push(ctxt, ops); |
d19292e4 MG |
1583 | break; |
1584 | } | |
8cdbd2c9 | 1585 | case 4: /* jmp abs */ |
fd60754e | 1586 | c->eip = c->src.val; |
8cdbd2c9 LV |
1587 | break; |
1588 | case 6: /* push */ | |
79168fd1 | 1589 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1590 | break; |
8cdbd2c9 | 1591 | } |
1b30eaa8 | 1592 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1593 | } |
1594 | ||
1595 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1596 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1597 | { |
1598 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1599 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1600 | |
1601 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1602 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1603 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1604 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1605 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1606 | } else { |
16518d5a AK |
1607 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1608 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1609 | |
05f086f8 | 1610 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1611 | } |
1b30eaa8 | 1612 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1613 | } |
1614 | ||
a77ab5ea AK |
1615 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1616 | struct x86_emulate_ops *ops) | |
1617 | { | |
1618 | struct decode_cache *c = &ctxt->decode; | |
1619 | int rc; | |
1620 | unsigned long cs; | |
1621 | ||
1622 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1623 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1624 | return rc; |
1625 | if (c->op_bytes == 4) | |
1626 | c->eip = (u32)c->eip; | |
1627 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1628 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1629 | return rc; |
2e873022 | 1630 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1631 | return rc; |
1632 | } | |
1633 | ||
09b5f4d3 WY |
1634 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, |
1635 | struct x86_emulate_ops *ops, int seg) | |
1636 | { | |
1637 | struct decode_cache *c = &ctxt->decode; | |
1638 | unsigned short sel; | |
1639 | int rc; | |
1640 | ||
1641 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
1642 | ||
1643 | rc = load_segment_descriptor(ctxt, ops, sel, seg); | |
1644 | if (rc != X86EMUL_CONTINUE) | |
1645 | return rc; | |
1646 | ||
1647 | c->dst.val = c->src.val; | |
1648 | return rc; | |
1649 | } | |
1650 | ||
e66bb2cc AP |
1651 | static inline void |
1652 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1653 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1654 | struct desc_struct *ss) | |
e66bb2cc | 1655 | { |
79168fd1 | 1656 | memset(cs, 0, sizeof(struct desc_struct)); |
5601d05b | 1657 | ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1658 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1659 | |
1660 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1661 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1662 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1663 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1664 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1665 | cs->s = 1; | |
1666 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1667 | cs->p = 1; |
1668 | cs->d = 1; | |
e66bb2cc | 1669 | |
79168fd1 GN |
1670 | set_desc_base(ss, 0); /* flat segment */ |
1671 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1672 | ss->g = 1; /* 4kb granularity */ |
1673 | ss->s = 1; | |
1674 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1675 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1676 | ss->dpl = 0; |
79168fd1 | 1677 | ss->p = 1; |
e66bb2cc AP |
1678 | } |
1679 | ||
1680 | static int | |
3fb1b5db | 1681 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1682 | { |
1683 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1684 | struct desc_struct cs, ss; |
e66bb2cc | 1685 | u64 msr_data; |
79168fd1 | 1686 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1687 | |
1688 | /* syscall is not available in real mode */ | |
2e901c4c | 1689 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
1690 | ctxt->mode == X86EMUL_MODE_VM86) |
1691 | return emulate_ud(ctxt); | |
e66bb2cc | 1692 | |
79168fd1 | 1693 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1694 | |
3fb1b5db | 1695 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1696 | msr_data >>= 32; |
79168fd1 GN |
1697 | cs_sel = (u16)(msr_data & 0xfffc); |
1698 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1699 | |
1700 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1701 | cs.d = 0; |
e66bb2cc AP |
1702 | cs.l = 1; |
1703 | } | |
5601d05b | 1704 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1705 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1706 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1707 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
e66bb2cc AP |
1708 | |
1709 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1710 | if (is_long_mode(ctxt->vcpu)) { | |
1711 | #ifdef CONFIG_X86_64 | |
1712 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1713 | ||
3fb1b5db GN |
1714 | ops->get_msr(ctxt->vcpu, |
1715 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1716 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1717 | c->eip = msr_data; |
1718 | ||
3fb1b5db | 1719 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1720 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1721 | #endif | |
1722 | } else { | |
1723 | /* legacy mode */ | |
3fb1b5db | 1724 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1725 | c->eip = (u32)msr_data; |
1726 | ||
1727 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1728 | } | |
1729 | ||
e54cfa97 | 1730 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1731 | } |
1732 | ||
8c604352 | 1733 | static int |
3fb1b5db | 1734 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1735 | { |
1736 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1737 | struct desc_struct cs, ss; |
8c604352 | 1738 | u64 msr_data; |
79168fd1 | 1739 | u16 cs_sel, ss_sel; |
8c604352 | 1740 | |
a0044755 | 1741 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
1742 | if (ctxt->mode == X86EMUL_MODE_REAL) |
1743 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1744 | |
1745 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1746 | * Therefore, we inject an #UD. | |
1747 | */ | |
35d3d4a1 AK |
1748 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
1749 | return emulate_ud(ctxt); | |
8c604352 | 1750 | |
79168fd1 | 1751 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1752 | |
3fb1b5db | 1753 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1754 | switch (ctxt->mode) { |
1755 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
1756 | if ((msr_data & 0xfffc) == 0x0) |
1757 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1758 | break; |
1759 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
1760 | if (msr_data == 0x0) |
1761 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1762 | break; |
1763 | } | |
1764 | ||
1765 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1766 | cs_sel = (u16)msr_data; |
1767 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1768 | ss_sel = cs_sel + 8; | |
1769 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1770 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1771 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1772 | cs.d = 0; |
8c604352 AP |
1773 | cs.l = 1; |
1774 | } | |
1775 | ||
5601d05b | 1776 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1777 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1778 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1779 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
8c604352 | 1780 | |
3fb1b5db | 1781 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1782 | c->eip = msr_data; |
1783 | ||
3fb1b5db | 1784 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1785 | c->regs[VCPU_REGS_RSP] = msr_data; |
1786 | ||
e54cfa97 | 1787 | return X86EMUL_CONTINUE; |
8c604352 AP |
1788 | } |
1789 | ||
4668f050 | 1790 | static int |
3fb1b5db | 1791 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1792 | { |
1793 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1794 | struct desc_struct cs, ss; |
4668f050 AP |
1795 | u64 msr_data; |
1796 | int usermode; | |
79168fd1 | 1797 | u16 cs_sel, ss_sel; |
4668f050 | 1798 | |
a0044755 GN |
1799 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1800 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
1801 | ctxt->mode == X86EMUL_MODE_VM86) |
1802 | return emulate_gp(ctxt, 0); | |
4668f050 | 1803 | |
79168fd1 | 1804 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1805 | |
1806 | if ((c->rex_prefix & 0x8) != 0x0) | |
1807 | usermode = X86EMUL_MODE_PROT64; | |
1808 | else | |
1809 | usermode = X86EMUL_MODE_PROT32; | |
1810 | ||
1811 | cs.dpl = 3; | |
1812 | ss.dpl = 3; | |
3fb1b5db | 1813 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1814 | switch (usermode) { |
1815 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1816 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
1817 | if ((msr_data & 0xfffc) == 0x0) |
1818 | return emulate_gp(ctxt, 0); | |
79168fd1 | 1819 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1820 | break; |
1821 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1822 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
1823 | if (msr_data == 0x0) |
1824 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
1825 | ss_sel = cs_sel + 8; |
1826 | cs.d = 0; | |
4668f050 AP |
1827 | cs.l = 1; |
1828 | break; | |
1829 | } | |
79168fd1 GN |
1830 | cs_sel |= SELECTOR_RPL_MASK; |
1831 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1832 | |
5601d05b | 1833 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1834 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1835 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1836 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
4668f050 | 1837 | |
bdb475a3 GN |
1838 | c->eip = c->regs[VCPU_REGS_RDX]; |
1839 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1840 | |
e54cfa97 | 1841 | return X86EMUL_CONTINUE; |
4668f050 AP |
1842 | } |
1843 | ||
9c537244 GN |
1844 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1845 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1846 | { |
1847 | int iopl; | |
1848 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1849 | return false; | |
1850 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1851 | return true; | |
1852 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1853 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1854 | } |
1855 | ||
1856 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1857 | struct x86_emulate_ops *ops, | |
1858 | u16 port, u16 len) | |
1859 | { | |
79168fd1 | 1860 | struct desc_struct tr_seg; |
5601d05b | 1861 | u32 base3; |
f850e2e6 | 1862 | int r; |
399a40c9 | 1863 | u16 io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 1864 | unsigned mask = (1 << len) - 1; |
5601d05b | 1865 | unsigned long base; |
f850e2e6 | 1866 | |
5601d05b | 1867 | ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu); |
79168fd1 | 1868 | if (!tr_seg.p) |
f850e2e6 | 1869 | return false; |
79168fd1 | 1870 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1871 | return false; |
5601d05b GN |
1872 | base = get_desc_base(&tr_seg); |
1873 | #ifdef CONFIG_X86_64 | |
1874 | base |= ((u64)base3) << 32; | |
1875 | #endif | |
1876 | r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1877 | if (r != X86EMUL_CONTINUE) |
1878 | return false; | |
79168fd1 | 1879 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1880 | return false; |
399a40c9 | 1881 | r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu, |
5601d05b | 1882 | NULL); |
f850e2e6 GN |
1883 | if (r != X86EMUL_CONTINUE) |
1884 | return false; | |
1885 | if ((perm >> bit_idx) & mask) | |
1886 | return false; | |
1887 | return true; | |
1888 | } | |
1889 | ||
1890 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1891 | struct x86_emulate_ops *ops, | |
1892 | u16 port, u16 len) | |
1893 | { | |
4fc40f07 GN |
1894 | if (ctxt->perm_ok) |
1895 | return true; | |
1896 | ||
9c537244 | 1897 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1898 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1899 | return false; | |
4fc40f07 GN |
1900 | |
1901 | ctxt->perm_ok = true; | |
1902 | ||
f850e2e6 GN |
1903 | return true; |
1904 | } | |
1905 | ||
38ba30ba GN |
1906 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1907 | struct x86_emulate_ops *ops, | |
1908 | struct tss_segment_16 *tss) | |
1909 | { | |
1910 | struct decode_cache *c = &ctxt->decode; | |
1911 | ||
1912 | tss->ip = c->eip; | |
1913 | tss->flag = ctxt->eflags; | |
1914 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1915 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1916 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1917 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1918 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1919 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1920 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1921 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1922 | ||
1923 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1924 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1925 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1926 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1927 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1928 | } | |
1929 | ||
1930 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1931 | struct x86_emulate_ops *ops, | |
1932 | struct tss_segment_16 *tss) | |
1933 | { | |
1934 | struct decode_cache *c = &ctxt->decode; | |
1935 | int ret; | |
1936 | ||
1937 | c->eip = tss->ip; | |
1938 | ctxt->eflags = tss->flag | 2; | |
1939 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1940 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1941 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1942 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1943 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1944 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1945 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1946 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1947 | ||
1948 | /* | |
1949 | * SDM says that segment selectors are loaded before segment | |
1950 | * descriptors | |
1951 | */ | |
1952 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1953 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1954 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1955 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1956 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1957 | ||
1958 | /* | |
1959 | * Now load segment descriptors. If fault happenes at this stage | |
1960 | * it is handled in a context of new task | |
1961 | */ | |
1962 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1963 | if (ret != X86EMUL_CONTINUE) | |
1964 | return ret; | |
1965 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1966 | if (ret != X86EMUL_CONTINUE) | |
1967 | return ret; | |
1968 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1969 | if (ret != X86EMUL_CONTINUE) | |
1970 | return ret; | |
1971 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1972 | if (ret != X86EMUL_CONTINUE) | |
1973 | return ret; | |
1974 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1975 | if (ret != X86EMUL_CONTINUE) | |
1976 | return ret; | |
1977 | ||
1978 | return X86EMUL_CONTINUE; | |
1979 | } | |
1980 | ||
1981 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1982 | struct x86_emulate_ops *ops, | |
1983 | u16 tss_selector, u16 old_tss_sel, | |
1984 | ulong old_tss_base, struct desc_struct *new_desc) | |
1985 | { | |
1986 | struct tss_segment_16 tss_seg; | |
1987 | int ret; | |
bcc55cba | 1988 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
1989 | |
1990 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 1991 | &ctxt->exception); |
db297e3d | 1992 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 1993 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 1994 | return ret; |
38ba30ba GN |
1995 | |
1996 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1997 | ||
1998 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 1999 | &ctxt->exception); |
db297e3d | 2000 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2001 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2002 | return ret; |
38ba30ba GN |
2003 | |
2004 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2005 | &ctxt->exception); |
db297e3d | 2006 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2007 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2008 | return ret; |
38ba30ba GN |
2009 | |
2010 | if (old_tss_sel != 0xffff) { | |
2011 | tss_seg.prev_task_link = old_tss_sel; | |
2012 | ||
2013 | ret = ops->write_std(new_tss_base, | |
2014 | &tss_seg.prev_task_link, | |
2015 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2016 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2017 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2018 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2019 | return ret; |
38ba30ba GN |
2020 | } |
2021 | ||
2022 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2023 | } | |
2024 | ||
2025 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2026 | struct x86_emulate_ops *ops, | |
2027 | struct tss_segment_32 *tss) | |
2028 | { | |
2029 | struct decode_cache *c = &ctxt->decode; | |
2030 | ||
2031 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2032 | tss->eip = c->eip; | |
2033 | tss->eflags = ctxt->eflags; | |
2034 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2035 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2036 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2037 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2038 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2039 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2040 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2041 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2042 | ||
2043 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2044 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2045 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2046 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2047 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2048 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2049 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2050 | } | |
2051 | ||
2052 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2053 | struct x86_emulate_ops *ops, | |
2054 | struct tss_segment_32 *tss) | |
2055 | { | |
2056 | struct decode_cache *c = &ctxt->decode; | |
2057 | int ret; | |
2058 | ||
35d3d4a1 AK |
2059 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) |
2060 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2061 | c->eip = tss->eip; |
2062 | ctxt->eflags = tss->eflags | 2; | |
2063 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2064 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2065 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2066 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2067 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2068 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2069 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2070 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2071 | ||
2072 | /* | |
2073 | * SDM says that segment selectors are loaded before segment | |
2074 | * descriptors | |
2075 | */ | |
2076 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2077 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2078 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2079 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2080 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2081 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2082 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2083 | ||
2084 | /* | |
2085 | * Now load segment descriptors. If fault happenes at this stage | |
2086 | * it is handled in a context of new task | |
2087 | */ | |
2088 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2089 | if (ret != X86EMUL_CONTINUE) | |
2090 | return ret; | |
2091 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2092 | if (ret != X86EMUL_CONTINUE) | |
2093 | return ret; | |
2094 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2095 | if (ret != X86EMUL_CONTINUE) | |
2096 | return ret; | |
2097 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2098 | if (ret != X86EMUL_CONTINUE) | |
2099 | return ret; | |
2100 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2101 | if (ret != X86EMUL_CONTINUE) | |
2102 | return ret; | |
2103 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2104 | if (ret != X86EMUL_CONTINUE) | |
2105 | return ret; | |
2106 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2107 | if (ret != X86EMUL_CONTINUE) | |
2108 | return ret; | |
2109 | ||
2110 | return X86EMUL_CONTINUE; | |
2111 | } | |
2112 | ||
2113 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2114 | struct x86_emulate_ops *ops, | |
2115 | u16 tss_selector, u16 old_tss_sel, | |
2116 | ulong old_tss_base, struct desc_struct *new_desc) | |
2117 | { | |
2118 | struct tss_segment_32 tss_seg; | |
2119 | int ret; | |
bcc55cba | 2120 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2121 | |
2122 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2123 | &ctxt->exception); |
db297e3d | 2124 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2125 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2126 | return ret; |
38ba30ba GN |
2127 | |
2128 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2129 | ||
2130 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2131 | &ctxt->exception); |
db297e3d | 2132 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2133 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2134 | return ret; |
38ba30ba GN |
2135 | |
2136 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2137 | &ctxt->exception); |
db297e3d | 2138 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2139 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2140 | return ret; |
38ba30ba GN |
2141 | |
2142 | if (old_tss_sel != 0xffff) { | |
2143 | tss_seg.prev_task_link = old_tss_sel; | |
2144 | ||
2145 | ret = ops->write_std(new_tss_base, | |
2146 | &tss_seg.prev_task_link, | |
2147 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2148 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2149 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2150 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2151 | return ret; |
38ba30ba GN |
2152 | } |
2153 | ||
2154 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2155 | } | |
2156 | ||
2157 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2158 | struct x86_emulate_ops *ops, |
2159 | u16 tss_selector, int reason, | |
2160 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2161 | { |
2162 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2163 | int ret; | |
2164 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2165 | ulong old_tss_base = | |
5951c442 | 2166 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2167 | u32 desc_limit; |
38ba30ba GN |
2168 | |
2169 | /* FIXME: old_tss_base == ~0 ? */ | |
2170 | ||
2171 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2172 | if (ret != X86EMUL_CONTINUE) | |
2173 | return ret; | |
2174 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2175 | if (ret != X86EMUL_CONTINUE) | |
2176 | return ret; | |
2177 | ||
2178 | /* FIXME: check that next_tss_desc is tss */ | |
2179 | ||
2180 | if (reason != TASK_SWITCH_IRET) { | |
2181 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
35d3d4a1 AK |
2182 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) |
2183 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2184 | } |
2185 | ||
ceffb459 GN |
2186 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2187 | if (!next_tss_desc.p || | |
2188 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2189 | desc_limit < 0x2b)) { | |
54b8486f | 2190 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2191 | return X86EMUL_PROPAGATE_FAULT; |
2192 | } | |
2193 | ||
2194 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2195 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2196 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2197 | &curr_tss_desc); | |
2198 | } | |
2199 | ||
2200 | if (reason == TASK_SWITCH_IRET) | |
2201 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2202 | ||
2203 | /* set back link to prev task only if NT bit is set in eflags | |
2204 | note that old_tss_sel is not used afetr this point */ | |
2205 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2206 | old_tss_sel = 0xffff; | |
2207 | ||
2208 | if (next_tss_desc.type & 8) | |
2209 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2210 | old_tss_base, &next_tss_desc); | |
2211 | else | |
2212 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2213 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2214 | if (ret != X86EMUL_CONTINUE) |
2215 | return ret; | |
38ba30ba GN |
2216 | |
2217 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2218 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2219 | ||
2220 | if (reason != TASK_SWITCH_IRET) { | |
2221 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2222 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2223 | &next_tss_desc); | |
2224 | } | |
2225 | ||
2226 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
5601d05b | 2227 | ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu); |
38ba30ba GN |
2228 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); |
2229 | ||
e269fb21 JK |
2230 | if (has_error_code) { |
2231 | struct decode_cache *c = &ctxt->decode; | |
2232 | ||
2233 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2234 | c->lock_prefix = 0; | |
2235 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2236 | emulate_push(ctxt, ops); |
e269fb21 JK |
2237 | } |
2238 | ||
38ba30ba GN |
2239 | return ret; |
2240 | } | |
2241 | ||
2242 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2243 | u16 tss_selector, int reason, |
2244 | bool has_error_code, u32 error_code) | |
38ba30ba | 2245 | { |
9aabc88f | 2246 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2247 | struct decode_cache *c = &ctxt->decode; |
2248 | int rc; | |
2249 | ||
38ba30ba | 2250 | c->eip = ctxt->eip; |
e269fb21 | 2251 | c->dst.type = OP_NONE; |
38ba30ba | 2252 | |
e269fb21 JK |
2253 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2254 | has_error_code, error_code); | |
38ba30ba GN |
2255 | |
2256 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2257 | rc = writeback(ctxt, ops); |
95c55886 GN |
2258 | if (rc == X86EMUL_CONTINUE) |
2259 | ctxt->eip = c->eip; | |
38ba30ba GN |
2260 | } |
2261 | ||
19d04437 | 2262 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2263 | } |
2264 | ||
90de84f5 | 2265 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2266 | int reg, struct operand *op) |
a682e354 GN |
2267 | { |
2268 | struct decode_cache *c = &ctxt->decode; | |
2269 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2270 | ||
d9271123 | 2271 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
90de84f5 AK |
2272 | op->addr.mem.ea = register_address(c, c->regs[reg]); |
2273 | op->addr.mem.seg = seg; | |
a682e354 GN |
2274 | } |
2275 | ||
63540382 AK |
2276 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2277 | { | |
2278 | emulate_push(ctxt, ctxt->ops); | |
2279 | return X86EMUL_CONTINUE; | |
2280 | } | |
2281 | ||
7af04fc0 AK |
2282 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2283 | { | |
2284 | struct decode_cache *c = &ctxt->decode; | |
2285 | u8 al, old_al; | |
2286 | bool af, cf, old_cf; | |
2287 | ||
2288 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2289 | al = c->dst.val; | |
2290 | ||
2291 | old_al = al; | |
2292 | old_cf = cf; | |
2293 | cf = false; | |
2294 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2295 | if ((al & 0x0f) > 9 || af) { | |
2296 | al -= 6; | |
2297 | cf = old_cf | (al >= 250); | |
2298 | af = true; | |
2299 | } else { | |
2300 | af = false; | |
2301 | } | |
2302 | if (old_al > 0x99 || old_cf) { | |
2303 | al -= 0x60; | |
2304 | cf = true; | |
2305 | } | |
2306 | ||
2307 | c->dst.val = al; | |
2308 | /* Set PF, ZF, SF */ | |
2309 | c->src.type = OP_IMM; | |
2310 | c->src.val = 0; | |
2311 | c->src.bytes = 1; | |
2312 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2313 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2314 | if (cf) | |
2315 | ctxt->eflags |= X86_EFLAGS_CF; | |
2316 | if (af) | |
2317 | ctxt->eflags |= X86_EFLAGS_AF; | |
2318 | return X86EMUL_CONTINUE; | |
2319 | } | |
2320 | ||
0ef753b8 AK |
2321 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2322 | { | |
2323 | struct decode_cache *c = &ctxt->decode; | |
2324 | u16 sel, old_cs; | |
2325 | ulong old_eip; | |
2326 | int rc; | |
2327 | ||
2328 | old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2329 | old_eip = c->eip; | |
2330 | ||
2331 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
2332 | if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS)) | |
2333 | return X86EMUL_CONTINUE; | |
2334 | ||
2335 | c->eip = 0; | |
2336 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
2337 | ||
2338 | c->src.val = old_cs; | |
2339 | emulate_push(ctxt, ctxt->ops); | |
2340 | rc = writeback(ctxt, ctxt->ops); | |
2341 | if (rc != X86EMUL_CONTINUE) | |
2342 | return rc; | |
2343 | ||
2344 | c->src.val = old_eip; | |
2345 | emulate_push(ctxt, ctxt->ops); | |
2346 | rc = writeback(ctxt, ctxt->ops); | |
2347 | if (rc != X86EMUL_CONTINUE) | |
2348 | return rc; | |
2349 | ||
2350 | c->dst.type = OP_NONE; | |
2351 | ||
2352 | return X86EMUL_CONTINUE; | |
2353 | } | |
2354 | ||
40ece7c7 AK |
2355 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2356 | { | |
2357 | struct decode_cache *c = &ctxt->decode; | |
2358 | int rc; | |
2359 | ||
2360 | c->dst.type = OP_REG; | |
2361 | c->dst.addr.reg = &c->eip; | |
2362 | c->dst.bytes = c->op_bytes; | |
2363 | rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes); | |
2364 | if (rc != X86EMUL_CONTINUE) | |
2365 | return rc; | |
2366 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val); | |
2367 | return X86EMUL_CONTINUE; | |
2368 | } | |
2369 | ||
5c82aa29 | 2370 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 AK |
2371 | { |
2372 | struct decode_cache *c = &ctxt->decode; | |
2373 | ||
f3a1b9f4 AK |
2374 | emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags); |
2375 | return X86EMUL_CONTINUE; | |
2376 | } | |
2377 | ||
5c82aa29 AK |
2378 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2379 | { | |
2380 | struct decode_cache *c = &ctxt->decode; | |
2381 | ||
2382 | c->dst.val = c->src2.val; | |
2383 | return em_imul(ctxt); | |
2384 | } | |
2385 | ||
61429142 AK |
2386 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2387 | { | |
2388 | struct decode_cache *c = &ctxt->decode; | |
2389 | ||
2390 | c->dst.type = OP_REG; | |
2391 | c->dst.bytes = c->src.bytes; | |
2392 | c->dst.addr.reg = &c->regs[VCPU_REGS_RDX]; | |
2393 | c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1); | |
2394 | ||
2395 | return X86EMUL_CONTINUE; | |
2396 | } | |
2397 | ||
48bb5d3c AK |
2398 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2399 | { | |
2400 | unsigned cpl = ctxt->ops->cpl(ctxt->vcpu); | |
2401 | struct decode_cache *c = &ctxt->decode; | |
2402 | u64 tsc = 0; | |
2403 | ||
35d3d4a1 AK |
2404 | if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) |
2405 | return emulate_gp(ctxt, 0); | |
48bb5d3c AK |
2406 | ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc); |
2407 | c->regs[VCPU_REGS_RAX] = (u32)tsc; | |
2408 | c->regs[VCPU_REGS_RDX] = tsc >> 32; | |
2409 | return X86EMUL_CONTINUE; | |
2410 | } | |
2411 | ||
b9eac5f4 AK |
2412 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2413 | { | |
2414 | struct decode_cache *c = &ctxt->decode; | |
2415 | c->dst.val = c->src.val; | |
2416 | return X86EMUL_CONTINUE; | |
2417 | } | |
2418 | ||
aa97bb48 AK |
2419 | static int em_movdqu(struct x86_emulate_ctxt *ctxt) |
2420 | { | |
2421 | struct decode_cache *c = &ctxt->decode; | |
2422 | memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes); | |
2423 | return X86EMUL_CONTINUE; | |
2424 | } | |
2425 | ||
73fba5f4 | 2426 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 2427 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
73fba5f4 AK |
2428 | #define N D(0) |
2429 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2430 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2431 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
c4f035c6 AK |
2432 | #define II(_f, _e, _i) \ |
2433 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
aa97bb48 | 2434 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 2435 | |
8d8f4e9f AK |
2436 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
2437 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) | |
2438 | ||
6230f7fc AK |
2439 | #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \ |
2440 | D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \ | |
2441 | D2bv(((_f) & ~Lock) | DstAcc | SrcImm) | |
2442 | ||
2443 | ||
73fba5f4 AK |
2444 | static struct opcode group1[] = { |
2445 | X7(D(Lock)), N | |
2446 | }; | |
2447 | ||
2448 | static struct opcode group1A[] = { | |
2449 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2450 | }; | |
2451 | ||
2452 | static struct opcode group3[] = { | |
2453 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2454 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2455 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2456 | }; |
2457 | ||
2458 | static struct opcode group4[] = { | |
2459 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2460 | N, N, N, N, N, N, | |
2461 | }; | |
2462 | ||
2463 | static struct opcode group5[] = { | |
2464 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
2465 | D(SrcMem | ModRM | Stack), |
2466 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
2467 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
2468 | D(SrcMem | ModRM | Stack), N, | |
2469 | }; | |
2470 | ||
2471 | static struct group_dual group7 = { { | |
2472 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2473 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2474 | D(SrcMem16 | ModRM | Mov | Priv), |
2475 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 | 2476 | }, { |
d867162c AK |
2477 | D(SrcNone | ModRM | Priv | VendorSpecific), N, |
2478 | N, D(SrcNone | ModRM | Priv | VendorSpecific), | |
73fba5f4 AK |
2479 | D(SrcNone | ModRM | DstMem | Mov), N, |
2480 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2481 | } }; | |
2482 | ||
2483 | static struct opcode group8[] = { | |
2484 | N, N, N, N, | |
2485 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2486 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2487 | }; | |
2488 | ||
2489 | static struct group_dual group9 = { { | |
2490 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2491 | }, { | |
2492 | N, N, N, N, N, N, N, N, | |
2493 | } }; | |
2494 | ||
a4d4a7c1 AK |
2495 | static struct opcode group11[] = { |
2496 | I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)), | |
2497 | }; | |
2498 | ||
aa97bb48 AK |
2499 | static struct gprefix pfx_0f_6f_0f_7f = { |
2500 | N, N, N, I(Sse, em_movdqu), | |
2501 | }; | |
2502 | ||
73fba5f4 AK |
2503 | static struct opcode opcode_table[256] = { |
2504 | /* 0x00 - 0x07 */ | |
6230f7fc | 2505 | D6ALU(Lock), |
73fba5f4 AK |
2506 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2507 | /* 0x08 - 0x0F */ | |
6230f7fc | 2508 | D6ALU(Lock), |
73fba5f4 AK |
2509 | D(ImplicitOps | Stack | No64), N, |
2510 | /* 0x10 - 0x17 */ | |
6230f7fc | 2511 | D6ALU(Lock), |
73fba5f4 AK |
2512 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2513 | /* 0x18 - 0x1F */ | |
6230f7fc | 2514 | D6ALU(Lock), |
73fba5f4 AK |
2515 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2516 | /* 0x20 - 0x27 */ | |
6230f7fc | 2517 | D6ALU(Lock), N, N, |
73fba5f4 | 2518 | /* 0x28 - 0x2F */ |
6230f7fc | 2519 | D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 2520 | /* 0x30 - 0x37 */ |
6230f7fc | 2521 | D6ALU(Lock), N, N, |
73fba5f4 | 2522 | /* 0x38 - 0x3F */ |
6230f7fc | 2523 | D6ALU(0), N, N, |
73fba5f4 AK |
2524 | /* 0x40 - 0x4F */ |
2525 | X16(D(DstReg)), | |
2526 | /* 0x50 - 0x57 */ | |
63540382 | 2527 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2528 | /* 0x58 - 0x5F */ |
2529 | X8(D(DstReg | Stack)), | |
2530 | /* 0x60 - 0x67 */ | |
2531 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2532 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2533 | N, N, N, N, | |
2534 | /* 0x68 - 0x6F */ | |
d46164db AK |
2535 | I(SrcImm | Mov | Stack, em_push), |
2536 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
2537 | I(SrcImmByte | Mov | Stack, em_push), |
2538 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
48fe67b5 AK |
2539 | D2bv(DstDI | Mov | String), /* insb, insw/insd */ |
2540 | D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
2541 | /* 0x70 - 0x7F */ |
2542 | X16(D(SrcImmByte)), | |
2543 | /* 0x80 - 0x87 */ | |
2544 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2545 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2546 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2547 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
76e8e68d | 2548 | D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock), |
73fba5f4 | 2549 | /* 0x88 - 0x8F */ |
b9eac5f4 AK |
2550 | I2bv(DstMem | SrcReg | ModRM | Mov, em_mov), |
2551 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), | |
342fc630 | 2552 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2553 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2554 | /* 0x90 - 0x97 */ | |
3d9e77df | 2555 | X8(D(SrcAcc | DstReg)), |
73fba5f4 | 2556 | /* 0x98 - 0x9F */ |
61429142 | 2557 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 2558 | I(SrcImmFAddr | No64, em_call_far), N, |
73fba5f4 AK |
2559 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, |
2560 | /* 0xA0 - 0xA7 */ | |
b9eac5f4 AK |
2561 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
2562 | I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov), | |
2563 | I2bv(SrcSI | DstDI | Mov | String, em_mov), | |
2564 | D2bv(SrcSI | DstDI | String), | |
73fba5f4 | 2565 | /* 0xA8 - 0xAF */ |
50748613 | 2566 | D2bv(DstAcc | SrcImm), |
b9eac5f4 AK |
2567 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
2568 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
48fe67b5 | 2569 | D2bv(SrcAcc | DstDI | String), |
73fba5f4 | 2570 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 2571 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2572 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 2573 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2574 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 2575 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 AK |
2576 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
2577 | D(ImplicitOps | Stack), | |
09b5f4d3 | 2578 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
a4d4a7c1 | 2579 | G(ByteOp, group11), G(0, group11), |
73fba5f4 AK |
2580 | /* 0xC8 - 0xCF */ |
2581 | N, N, N, D(ImplicitOps | Stack), | |
2582 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2583 | /* 0xD0 - 0xD7 */ | |
d2c6c7ad | 2584 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
2585 | N, N, N, N, |
2586 | /* 0xD8 - 0xDF */ | |
2587 | N, N, N, N, N, N, N, N, | |
2588 | /* 0xE0 - 0xE7 */ | |
e4abac67 | 2589 | X4(D(SrcImmByte)), |
d269e396 | 2590 | D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte), |
73fba5f4 AK |
2591 | /* 0xE8 - 0xEF */ |
2592 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2593 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
d269e396 | 2594 | D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps), |
73fba5f4 AK |
2595 | /* 0xF0 - 0xF7 */ |
2596 | N, N, N, N, | |
2597 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2598 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2599 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2600 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2601 | }; | |
2602 | ||
2603 | static struct opcode twobyte_table[256] = { | |
2604 | /* 0x00 - 0x0F */ | |
2605 | N, GD(0, &group7), N, N, | |
d867162c | 2606 | N, D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv), N, |
73fba5f4 AK |
2607 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, |
2608 | N, D(ImplicitOps | ModRM), N, N, | |
2609 | /* 0x10 - 0x1F */ | |
2610 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2611 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2612 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2613 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2614 | N, N, N, N, |
2615 | N, N, N, N, N, N, N, N, | |
2616 | /* 0x30 - 0x3F */ | |
48bb5d3c AK |
2617 | D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc), |
2618 | D(ImplicitOps | Priv), N, | |
d867162c AK |
2619 | D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific), |
2620 | N, N, | |
73fba5f4 AK |
2621 | N, N, N, N, N, N, N, N, |
2622 | /* 0x40 - 0x4F */ | |
2623 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2624 | /* 0x50 - 0x5F */ | |
2625 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2626 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
2627 | N, N, N, N, |
2628 | N, N, N, N, | |
2629 | N, N, N, N, | |
2630 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 2631 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
2632 | N, N, N, N, |
2633 | N, N, N, N, | |
2634 | N, N, N, N, | |
2635 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
2636 | /* 0x80 - 0x8F */ |
2637 | X16(D(SrcImm)), | |
2638 | /* 0x90 - 0x9F */ | |
ee45b58e | 2639 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2640 | /* 0xA0 - 0xA7 */ |
2641 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2642 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2643 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2644 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2645 | /* 0xA8 - 0xAF */ | |
2646 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2647 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2648 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2649 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 2650 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 2651 | /* 0xB0 - 0xB7 */ |
739ae406 | 2652 | D2bv(DstMem | SrcReg | ModRM | Lock), |
09b5f4d3 WY |
2653 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
2654 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
2655 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
2656 | /* 0xB8 - 0xBF */ |
2657 | N, N, | |
ba7ff2b7 | 2658 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2659 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2660 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2661 | /* 0xC0 - 0xCF */ |
739ae406 | 2662 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 2663 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
2664 | N, N, N, GD(0, &group9), |
2665 | N, N, N, N, N, N, N, N, | |
2666 | /* 0xD0 - 0xDF */ | |
2667 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2668 | /* 0xE0 - 0xEF */ | |
2669 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2670 | /* 0xF0 - 0xFF */ | |
2671 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2672 | }; | |
2673 | ||
2674 | #undef D | |
2675 | #undef N | |
2676 | #undef G | |
2677 | #undef GD | |
2678 | #undef I | |
aa97bb48 | 2679 | #undef GP |
73fba5f4 | 2680 | |
8d8f4e9f AK |
2681 | #undef D2bv |
2682 | #undef I2bv | |
6230f7fc | 2683 | #undef D6ALU |
8d8f4e9f | 2684 | |
39f21ee5 AK |
2685 | static unsigned imm_size(struct decode_cache *c) |
2686 | { | |
2687 | unsigned size; | |
2688 | ||
2689 | size = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2690 | if (size == 8) | |
2691 | size = 4; | |
2692 | return size; | |
2693 | } | |
2694 | ||
2695 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
2696 | unsigned size, bool sign_extension) | |
2697 | { | |
2698 | struct decode_cache *c = &ctxt->decode; | |
2699 | struct x86_emulate_ops *ops = ctxt->ops; | |
2700 | int rc = X86EMUL_CONTINUE; | |
2701 | ||
2702 | op->type = OP_IMM; | |
2703 | op->bytes = size; | |
90de84f5 | 2704 | op->addr.mem.ea = c->eip; |
39f21ee5 AK |
2705 | /* NB. Immediates are sign-extended as necessary. */ |
2706 | switch (op->bytes) { | |
2707 | case 1: | |
2708 | op->val = insn_fetch(s8, 1, c->eip); | |
2709 | break; | |
2710 | case 2: | |
2711 | op->val = insn_fetch(s16, 2, c->eip); | |
2712 | break; | |
2713 | case 4: | |
2714 | op->val = insn_fetch(s32, 4, c->eip); | |
2715 | break; | |
2716 | } | |
2717 | if (!sign_extension) { | |
2718 | switch (op->bytes) { | |
2719 | case 1: | |
2720 | op->val &= 0xff; | |
2721 | break; | |
2722 | case 2: | |
2723 | op->val &= 0xffff; | |
2724 | break; | |
2725 | case 4: | |
2726 | op->val &= 0xffffffff; | |
2727 | break; | |
2728 | } | |
2729 | } | |
2730 | done: | |
2731 | return rc; | |
2732 | } | |
2733 | ||
dde7e6d1 | 2734 | int |
dc25e89e | 2735 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 AK |
2736 | { |
2737 | struct x86_emulate_ops *ops = ctxt->ops; | |
2738 | struct decode_cache *c = &ctxt->decode; | |
2739 | int rc = X86EMUL_CONTINUE; | |
2740 | int mode = ctxt->mode; | |
0d7cdee8 AK |
2741 | int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix; |
2742 | bool op_prefix = false; | |
dde7e6d1 | 2743 | struct opcode opcode, *g_mod012, *g_mod3; |
2dbd0dd7 | 2744 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 | 2745 | |
dde7e6d1 | 2746 | c->eip = ctxt->eip; |
dc25e89e AP |
2747 | c->fetch.start = c->eip; |
2748 | c->fetch.end = c->fetch.start + insn_len; | |
2749 | if (insn_len > 0) | |
2750 | memcpy(c->fetch.data, insn, insn_len); | |
dde7e6d1 AK |
2751 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); |
2752 | ||
2753 | switch (mode) { | |
2754 | case X86EMUL_MODE_REAL: | |
2755 | case X86EMUL_MODE_VM86: | |
2756 | case X86EMUL_MODE_PROT16: | |
2757 | def_op_bytes = def_ad_bytes = 2; | |
2758 | break; | |
2759 | case X86EMUL_MODE_PROT32: | |
2760 | def_op_bytes = def_ad_bytes = 4; | |
2761 | break; | |
2762 | #ifdef CONFIG_X86_64 | |
2763 | case X86EMUL_MODE_PROT64: | |
2764 | def_op_bytes = 4; | |
2765 | def_ad_bytes = 8; | |
2766 | break; | |
2767 | #endif | |
2768 | default: | |
2769 | return -1; | |
2770 | } | |
2771 | ||
2772 | c->op_bytes = def_op_bytes; | |
2773 | c->ad_bytes = def_ad_bytes; | |
2774 | ||
2775 | /* Legacy prefixes. */ | |
2776 | for (;;) { | |
2777 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2778 | case 0x66: /* operand-size override */ | |
0d7cdee8 | 2779 | op_prefix = true; |
dde7e6d1 AK |
2780 | /* switch between 2/4 bytes */ |
2781 | c->op_bytes = def_op_bytes ^ 6; | |
2782 | break; | |
2783 | case 0x67: /* address-size override */ | |
2784 | if (mode == X86EMUL_MODE_PROT64) | |
2785 | /* switch between 4/8 bytes */ | |
2786 | c->ad_bytes = def_ad_bytes ^ 12; | |
2787 | else | |
2788 | /* switch between 2/4 bytes */ | |
2789 | c->ad_bytes = def_ad_bytes ^ 6; | |
2790 | break; | |
2791 | case 0x26: /* ES override */ | |
2792 | case 0x2e: /* CS override */ | |
2793 | case 0x36: /* SS override */ | |
2794 | case 0x3e: /* DS override */ | |
2795 | set_seg_override(c, (c->b >> 3) & 3); | |
2796 | break; | |
2797 | case 0x64: /* FS override */ | |
2798 | case 0x65: /* GS override */ | |
2799 | set_seg_override(c, c->b & 7); | |
2800 | break; | |
2801 | case 0x40 ... 0x4f: /* REX */ | |
2802 | if (mode != X86EMUL_MODE_PROT64) | |
2803 | goto done_prefixes; | |
2804 | c->rex_prefix = c->b; | |
2805 | continue; | |
2806 | case 0xf0: /* LOCK */ | |
2807 | c->lock_prefix = 1; | |
2808 | break; | |
2809 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 2810 | case 0xf3: /* REP/REPE/REPZ */ |
1d6b114f | 2811 | c->rep_prefix = c->b; |
dde7e6d1 AK |
2812 | break; |
2813 | default: | |
2814 | goto done_prefixes; | |
2815 | } | |
2816 | ||
2817 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2818 | ||
2819 | c->rex_prefix = 0; | |
2820 | } | |
2821 | ||
2822 | done_prefixes: | |
2823 | ||
2824 | /* REX prefix. */ | |
1e87e3ef AK |
2825 | if (c->rex_prefix & 8) |
2826 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2827 | |
2828 | /* Opcode byte(s). */ | |
2829 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2830 | /* Two-byte opcode? */ |
2831 | if (c->b == 0x0f) { | |
2832 | c->twobyte = 1; | |
2833 | c->b = insn_fetch(u8, 1, c->eip); | |
2834 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2835 | } |
2836 | c->d = opcode.flags; | |
2837 | ||
2838 | if (c->d & Group) { | |
2839 | dual = c->d & GroupDual; | |
2840 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2841 | --c->eip; | |
2842 | ||
2843 | if (c->d & GroupDual) { | |
2844 | g_mod012 = opcode.u.gdual->mod012; | |
2845 | g_mod3 = opcode.u.gdual->mod3; | |
2846 | } else | |
2847 | g_mod012 = g_mod3 = opcode.u.group; | |
2848 | ||
2849 | c->d &= ~(Group | GroupDual); | |
2850 | ||
2851 | goffset = (c->modrm >> 3) & 7; | |
2852 | ||
2853 | if ((c->modrm >> 6) == 3) | |
2854 | opcode = g_mod3[goffset]; | |
2855 | else | |
2856 | opcode = g_mod012[goffset]; | |
2857 | c->d |= opcode.flags; | |
2858 | } | |
2859 | ||
0d7cdee8 AK |
2860 | if (c->d & Prefix) { |
2861 | if (c->rep_prefix && op_prefix) | |
2862 | return X86EMUL_UNHANDLEABLE; | |
2863 | simd_prefix = op_prefix ? 0x66 : c->rep_prefix; | |
2864 | switch (simd_prefix) { | |
2865 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
2866 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
2867 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
2868 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
2869 | } | |
2870 | c->d |= opcode.flags; | |
2871 | } | |
2872 | ||
dde7e6d1 | 2873 | c->execute = opcode.u.execute; |
c4f035c6 | 2874 | c->intercept = opcode.intercept; |
dde7e6d1 AK |
2875 | |
2876 | /* Unrecognised? */ | |
d53db5ef | 2877 | if (c->d == 0 || (c->d & Undefined)) |
dde7e6d1 | 2878 | return -1; |
dde7e6d1 | 2879 | |
d867162c AK |
2880 | if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
2881 | return -1; | |
2882 | ||
dde7e6d1 AK |
2883 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
2884 | c->op_bytes = 8; | |
2885 | ||
7f9b4b75 AK |
2886 | if (c->d & Op3264) { |
2887 | if (mode == X86EMUL_MODE_PROT64) | |
2888 | c->op_bytes = 8; | |
2889 | else | |
2890 | c->op_bytes = 4; | |
2891 | } | |
2892 | ||
1253791d AK |
2893 | if (c->d & Sse) |
2894 | c->op_bytes = 16; | |
2895 | ||
dde7e6d1 | 2896 | /* ModRM and SIB bytes. */ |
09ee57cd | 2897 | if (c->d & ModRM) { |
2dbd0dd7 | 2898 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2899 | if (!c->has_seg_override) |
2900 | set_seg_override(c, c->modrm_seg); | |
2901 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2902 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2903 | if (rc != X86EMUL_CONTINUE) |
2904 | goto done; | |
2905 | ||
2906 | if (!c->has_seg_override) | |
2907 | set_seg_override(c, VCPU_SREG_DS); | |
2908 | ||
90de84f5 | 2909 | memop.addr.mem.seg = seg_override(ctxt, ops, c); |
dde7e6d1 | 2910 | |
2dbd0dd7 | 2911 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
90de84f5 | 2912 | memop.addr.mem.ea = (u32)memop.addr.mem.ea; |
dde7e6d1 | 2913 | |
2dbd0dd7 | 2914 | if (memop.type == OP_MEM && c->rip_relative) |
90de84f5 | 2915 | memop.addr.mem.ea += c->eip; |
dde7e6d1 AK |
2916 | |
2917 | /* | |
2918 | * Decode and fetch the source operand: register, memory | |
2919 | * or immediate. | |
2920 | */ | |
2921 | switch (c->d & SrcMask) { | |
2922 | case SrcNone: | |
2923 | break; | |
2924 | case SrcReg: | |
1253791d | 2925 | decode_register_operand(ctxt, &c->src, c, 0); |
dde7e6d1 AK |
2926 | break; |
2927 | case SrcMem16: | |
2dbd0dd7 | 2928 | memop.bytes = 2; |
dde7e6d1 AK |
2929 | goto srcmem_common; |
2930 | case SrcMem32: | |
2dbd0dd7 | 2931 | memop.bytes = 4; |
dde7e6d1 AK |
2932 | goto srcmem_common; |
2933 | case SrcMem: | |
2dbd0dd7 | 2934 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2935 | c->op_bytes; |
dde7e6d1 | 2936 | srcmem_common: |
2dbd0dd7 | 2937 | c->src = memop; |
dde7e6d1 | 2938 | break; |
b250e605 | 2939 | case SrcImmU16: |
39f21ee5 AK |
2940 | rc = decode_imm(ctxt, &c->src, 2, false); |
2941 | break; | |
dde7e6d1 | 2942 | case SrcImm: |
39f21ee5 AK |
2943 | rc = decode_imm(ctxt, &c->src, imm_size(c), true); |
2944 | break; | |
dde7e6d1 | 2945 | case SrcImmU: |
39f21ee5 | 2946 | rc = decode_imm(ctxt, &c->src, imm_size(c), false); |
dde7e6d1 AK |
2947 | break; |
2948 | case SrcImmByte: | |
39f21ee5 AK |
2949 | rc = decode_imm(ctxt, &c->src, 1, true); |
2950 | break; | |
dde7e6d1 | 2951 | case SrcImmUByte: |
39f21ee5 | 2952 | rc = decode_imm(ctxt, &c->src, 1, false); |
dde7e6d1 AK |
2953 | break; |
2954 | case SrcAcc: | |
2955 | c->src.type = OP_REG; | |
2956 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2957 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2958 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2959 | break; |
2960 | case SrcOne: | |
2961 | c->src.bytes = 1; | |
2962 | c->src.val = 1; | |
2963 | break; | |
2964 | case SrcSI: | |
2965 | c->src.type = OP_MEM; | |
2966 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
2967 | c->src.addr.mem.ea = |
2968 | register_address(c, c->regs[VCPU_REGS_RSI]); | |
2969 | c->src.addr.mem.seg = seg_override(ctxt, ops, c), | |
dde7e6d1 AK |
2970 | c->src.val = 0; |
2971 | break; | |
2972 | case SrcImmFAddr: | |
2973 | c->src.type = OP_IMM; | |
90de84f5 | 2974 | c->src.addr.mem.ea = c->eip; |
dde7e6d1 AK |
2975 | c->src.bytes = c->op_bytes + 2; |
2976 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2977 | break; | |
2978 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2979 | memop.bytes = c->op_bytes + 2; |
2980 | goto srcmem_common; | |
dde7e6d1 AK |
2981 | break; |
2982 | } | |
2983 | ||
39f21ee5 AK |
2984 | if (rc != X86EMUL_CONTINUE) |
2985 | goto done; | |
2986 | ||
dde7e6d1 AK |
2987 | /* |
2988 | * Decode and fetch the second source operand: register, memory | |
2989 | * or immediate. | |
2990 | */ | |
2991 | switch (c->d & Src2Mask) { | |
2992 | case Src2None: | |
2993 | break; | |
2994 | case Src2CL: | |
2995 | c->src2.bytes = 1; | |
2996 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2997 | break; | |
2998 | case Src2ImmByte: | |
39f21ee5 | 2999 | rc = decode_imm(ctxt, &c->src2, 1, true); |
dde7e6d1 AK |
3000 | break; |
3001 | case Src2One: | |
3002 | c->src2.bytes = 1; | |
3003 | c->src2.val = 1; | |
3004 | break; | |
7db41eb7 AK |
3005 | case Src2Imm: |
3006 | rc = decode_imm(ctxt, &c->src2, imm_size(c), true); | |
3007 | break; | |
dde7e6d1 AK |
3008 | } |
3009 | ||
39f21ee5 AK |
3010 | if (rc != X86EMUL_CONTINUE) |
3011 | goto done; | |
3012 | ||
dde7e6d1 AK |
3013 | /* Decode and fetch the destination operand: register or memory. */ |
3014 | switch (c->d & DstMask) { | |
dde7e6d1 | 3015 | case DstReg: |
1253791d | 3016 | decode_register_operand(ctxt, &c->dst, c, |
dde7e6d1 AK |
3017 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
3018 | break; | |
943858e2 WY |
3019 | case DstImmUByte: |
3020 | c->dst.type = OP_IMM; | |
90de84f5 | 3021 | c->dst.addr.mem.ea = c->eip; |
943858e2 WY |
3022 | c->dst.bytes = 1; |
3023 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
3024 | break; | |
dde7e6d1 AK |
3025 | case DstMem: |
3026 | case DstMem64: | |
2dbd0dd7 | 3027 | c->dst = memop; |
dde7e6d1 AK |
3028 | if ((c->d & DstMask) == DstMem64) |
3029 | c->dst.bytes = 8; | |
3030 | else | |
3031 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
3032 | if (c->d & BitOp) |
3033 | fetch_bit_operand(c); | |
2dbd0dd7 | 3034 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
3035 | break; |
3036 | case DstAcc: | |
3037 | c->dst.type = OP_REG; | |
3038 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 3039 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 3040 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
3041 | c->dst.orig_val = c->dst.val; |
3042 | break; | |
3043 | case DstDI: | |
3044 | c->dst.type = OP_MEM; | |
3045 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
3046 | c->dst.addr.mem.ea = |
3047 | register_address(c, c->regs[VCPU_REGS_RDI]); | |
3048 | c->dst.addr.mem.seg = VCPU_SREG_ES; | |
dde7e6d1 AK |
3049 | c->dst.val = 0; |
3050 | break; | |
36089fed WY |
3051 | case ImplicitOps: |
3052 | /* Special instructions do their own operand decoding. */ | |
3053 | default: | |
3054 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3055 | return 0; | |
dde7e6d1 AK |
3056 | } |
3057 | ||
3058 | done: | |
3059 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
3060 | } | |
3061 | ||
3e2f65d5 GN |
3062 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
3063 | { | |
3064 | struct decode_cache *c = &ctxt->decode; | |
3065 | ||
3066 | /* The second termination condition only applies for REPE | |
3067 | * and REPNE. Test if the repeat string operation prefix is | |
3068 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3069 | * corresponding termination condition according to: | |
3070 | * - if REPE/REPZ and ZF = 0 then done | |
3071 | * - if REPNE/REPNZ and ZF = 1 then done | |
3072 | */ | |
3073 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
3074 | (c->b == 0xae) || (c->b == 0xaf)) | |
3075 | && (((c->rep_prefix == REPE_PREFIX) && | |
3076 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
3077 | || ((c->rep_prefix == REPNE_PREFIX) && | |
3078 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
3079 | return true; | |
3080 | ||
3081 | return false; | |
3082 | } | |
3083 | ||
8b4caf66 | 3084 | int |
9aabc88f | 3085 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 3086 | { |
9aabc88f | 3087 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 3088 | u64 msr_data; |
8b4caf66 | 3089 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 3090 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 3091 | int saved_dst_type = c->dst.type; |
6e154e56 | 3092 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 3093 | |
9de41573 | 3094 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 3095 | |
1161624f | 3096 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
35d3d4a1 | 3097 | rc = emulate_ud(ctxt); |
1161624f GN |
3098 | goto done; |
3099 | } | |
3100 | ||
d380a5e4 | 3101 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 3102 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
35d3d4a1 | 3103 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
3104 | goto done; |
3105 | } | |
3106 | ||
081bca0e | 3107 | if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) { |
35d3d4a1 | 3108 | rc = emulate_ud(ctxt); |
081bca0e AK |
3109 | goto done; |
3110 | } | |
3111 | ||
1253791d AK |
3112 | if ((c->d & Sse) |
3113 | && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM) | |
3114 | || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) { | |
3115 | rc = emulate_ud(ctxt); | |
3116 | goto done; | |
3117 | } | |
3118 | ||
3119 | if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) { | |
3120 | rc = emulate_nm(ctxt); | |
3121 | goto done; | |
3122 | } | |
3123 | ||
c4f035c6 AK |
3124 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
3125 | rc = ops->intercept(ctxt, c->intercept, | |
3126 | X86_ICPT_PRE_EXCEPT); | |
3127 | if (rc != X86EMUL_CONTINUE) | |
3128 | goto done; | |
3129 | } | |
3130 | ||
e92805ac | 3131 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 3132 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
35d3d4a1 | 3133 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
3134 | goto done; |
3135 | } | |
3136 | ||
c4f035c6 AK |
3137 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
3138 | rc = ops->intercept(ctxt, c->intercept, | |
3139 | X86_ICPT_POST_EXCEPT); | |
3140 | if (rc != X86EMUL_CONTINUE) | |
3141 | goto done; | |
3142 | } | |
3143 | ||
b9fa9d6b AK |
3144 | if (c->rep_prefix && (c->d & String)) { |
3145 | /* All REP prefixes have the same first termination condition */ | |
c73e197b | 3146 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
95c55886 | 3147 | ctxt->eip = c->eip; |
b9fa9d6b AK |
3148 | goto done; |
3149 | } | |
b9fa9d6b AK |
3150 | } |
3151 | ||
c483c02a | 3152 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
90de84f5 | 3153 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem), |
414e6277 | 3154 | c->src.valptr, c->src.bytes); |
b60d513c | 3155 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 3156 | goto done; |
16518d5a | 3157 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
3158 | } |
3159 | ||
e35b7b9c | 3160 | if (c->src2.type == OP_MEM) { |
90de84f5 | 3161 | rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem), |
9de41573 | 3162 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
3163 | if (rc != X86EMUL_CONTINUE) |
3164 | goto done; | |
3165 | } | |
3166 | ||
8b4caf66 LV |
3167 | if ((c->d & DstMask) == ImplicitOps) |
3168 | goto special_insn; | |
3169 | ||
3170 | ||
69f55cb1 GN |
3171 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
3172 | /* optimisation - avoid slow emulated read if Mov */ | |
90de84f5 | 3173 | rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem), |
9de41573 | 3174 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
3175 | if (rc != X86EMUL_CONTINUE) |
3176 | goto done; | |
038e51de | 3177 | } |
e4e03ded | 3178 | c->dst.orig_val = c->dst.val; |
038e51de | 3179 | |
018a98db AK |
3180 | special_insn: |
3181 | ||
c4f035c6 AK |
3182 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
3183 | rc = ops->intercept(ctxt, c->intercept, | |
3184 | X86_ICPT_POST_MEMACCESS); | |
3185 | if (rc != X86EMUL_CONTINUE) | |
3186 | goto done; | |
3187 | } | |
3188 | ||
ef65c889 AK |
3189 | if (c->execute) { |
3190 | rc = c->execute(ctxt); | |
3191 | if (rc != X86EMUL_CONTINUE) | |
3192 | goto done; | |
3193 | goto writeback; | |
3194 | } | |
3195 | ||
e4e03ded | 3196 | if (c->twobyte) |
6aa8b732 AK |
3197 | goto twobyte_insn; |
3198 | ||
e4e03ded | 3199 | switch (c->b) { |
6aa8b732 AK |
3200 | case 0x00 ... 0x05: |
3201 | add: /* add */ | |
05f086f8 | 3202 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3203 | break; |
0934ac9d | 3204 | case 0x06: /* push es */ |
79168fd1 | 3205 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
3206 | break; |
3207 | case 0x07: /* pop es */ | |
0934ac9d | 3208 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d | 3209 | break; |
6aa8b732 AK |
3210 | case 0x08 ... 0x0d: |
3211 | or: /* or */ | |
05f086f8 | 3212 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3213 | break; |
0934ac9d | 3214 | case 0x0e: /* push cs */ |
79168fd1 | 3215 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 3216 | break; |
6aa8b732 AK |
3217 | case 0x10 ... 0x15: |
3218 | adc: /* adc */ | |
05f086f8 | 3219 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3220 | break; |
0934ac9d | 3221 | case 0x16: /* push ss */ |
79168fd1 | 3222 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
3223 | break; |
3224 | case 0x17: /* pop ss */ | |
0934ac9d | 3225 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d | 3226 | break; |
6aa8b732 AK |
3227 | case 0x18 ... 0x1d: |
3228 | sbb: /* sbb */ | |
05f086f8 | 3229 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3230 | break; |
0934ac9d | 3231 | case 0x1e: /* push ds */ |
79168fd1 | 3232 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
3233 | break; |
3234 | case 0x1f: /* pop ds */ | |
0934ac9d | 3235 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d | 3236 | break; |
aa3a816b | 3237 | case 0x20 ... 0x25: |
6aa8b732 | 3238 | and: /* and */ |
05f086f8 | 3239 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3240 | break; |
3241 | case 0x28 ... 0x2d: | |
3242 | sub: /* sub */ | |
05f086f8 | 3243 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3244 | break; |
3245 | case 0x30 ... 0x35: | |
3246 | xor: /* xor */ | |
05f086f8 | 3247 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3248 | break; |
3249 | case 0x38 ... 0x3d: | |
3250 | cmp: /* cmp */ | |
05f086f8 | 3251 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3252 | break; |
33615aa9 AK |
3253 | case 0x40 ... 0x47: /* inc r16/r32 */ |
3254 | emulate_1op("inc", c->dst, ctxt->eflags); | |
3255 | break; | |
3256 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
3257 | emulate_1op("dec", c->dst, ctxt->eflags); | |
3258 | break; | |
33615aa9 AK |
3259 | case 0x58 ... 0x5f: /* pop reg */ |
3260 | pop_instruction: | |
350f69dc | 3261 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
33615aa9 | 3262 | break; |
abcf14b5 | 3263 | case 0x60: /* pusha */ |
c37eda13 | 3264 | rc = emulate_pusha(ctxt, ops); |
abcf14b5 MG |
3265 | break; |
3266 | case 0x61: /* popa */ | |
3267 | rc = emulate_popa(ctxt, ops); | |
abcf14b5 | 3268 | break; |
6aa8b732 | 3269 | case 0x63: /* movsxd */ |
8b4caf66 | 3270 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3271 | goto cannot_emulate; |
e4e03ded | 3272 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 3273 | break; |
018a98db AK |
3274 | case 0x6c: /* insb */ |
3275 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
3276 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3277 | goto do_io_in; | |
018a98db AK |
3278 | case 0x6e: /* outsb */ |
3279 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
3280 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
3281 | goto do_io_out; | |
7972995b | 3282 | break; |
b2833e3c | 3283 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 3284 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3285 | jmp_rel(c, c->src.val); |
018a98db | 3286 | break; |
6aa8b732 | 3287 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 3288 | switch (c->modrm_reg) { |
6aa8b732 AK |
3289 | case 0: |
3290 | goto add; | |
3291 | case 1: | |
3292 | goto or; | |
3293 | case 2: | |
3294 | goto adc; | |
3295 | case 3: | |
3296 | goto sbb; | |
3297 | case 4: | |
3298 | goto and; | |
3299 | case 5: | |
3300 | goto sub; | |
3301 | case 6: | |
3302 | goto xor; | |
3303 | case 7: | |
3304 | goto cmp; | |
3305 | } | |
3306 | break; | |
3307 | case 0x84 ... 0x85: | |
dfb507c4 | 3308 | test: |
05f086f8 | 3309 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3310 | break; |
3311 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 3312 | xchg: |
6aa8b732 | 3313 | /* Write back the register source. */ |
31be40b3 WY |
3314 | c->src.val = c->dst.val; |
3315 | write_register_operand(&c->src); | |
6aa8b732 AK |
3316 | /* |
3317 | * Write back the memory destination with implicit LOCK | |
3318 | * prefix. | |
3319 | */ | |
31be40b3 | 3320 | c->dst.val = c->src.orig_val; |
e4e03ded | 3321 | c->lock_prefix = 1; |
6aa8b732 | 3322 | break; |
79168fd1 GN |
3323 | case 0x8c: /* mov r/m, sreg */ |
3324 | if (c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3325 | rc = emulate_ud(ctxt); |
5e3ae6c5 | 3326 | goto done; |
38d5bc6d | 3327 | } |
79168fd1 | 3328 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3329 | break; |
7e0b54b1 | 3330 | case 0x8d: /* lea r16/r32, m */ |
90de84f5 | 3331 | c->dst.val = c->src.addr.mem.ea; |
7e0b54b1 | 3332 | break; |
4257198a GT |
3333 | case 0x8e: { /* mov seg, r/m16 */ |
3334 | uint16_t sel; | |
4257198a GT |
3335 | |
3336 | sel = c->src.val; | |
8b9f4414 | 3337 | |
c697518a GN |
3338 | if (c->modrm_reg == VCPU_SREG_CS || |
3339 | c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3340 | rc = emulate_ud(ctxt); |
8b9f4414 GN |
3341 | goto done; |
3342 | } | |
3343 | ||
310b5d30 | 3344 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3345 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3346 | |
2e873022 | 3347 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3348 | |
3349 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3350 | break; | |
3351 | } | |
6aa8b732 | 3352 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3353 | rc = emulate_grp1a(ctxt, ops); |
6aa8b732 | 3354 | break; |
3d9e77df AK |
3355 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3356 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3357 | break; |
b13354f8 | 3358 | goto xchg; |
e8b6fa70 WY |
3359 | case 0x98: /* cbw/cwde/cdqe */ |
3360 | switch (c->op_bytes) { | |
3361 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3362 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3363 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3364 | } | |
3365 | break; | |
fd2a7608 | 3366 | case 0x9c: /* pushf */ |
05f086f8 | 3367 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3368 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3369 | break; |
535eabcf | 3370 | case 0x9d: /* popf */ |
2b48cc75 | 3371 | c->dst.type = OP_REG; |
1a6440ae | 3372 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3373 | c->dst.bytes = c->op_bytes; |
d4c6a154 | 3374 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
d4c6a154 | 3375 | break; |
6aa8b732 | 3376 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3377 | c->dst.type = OP_NONE; /* Disable writeback. */ |
a682e354 | 3378 | goto cmp; |
dfb507c4 MG |
3379 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3380 | goto test; | |
6aa8b732 | 3381 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3382 | goto cmp; |
018a98db AK |
3383 | case 0xc0 ... 0xc1: |
3384 | emulate_grp2(ctxt); | |
3385 | break; | |
111de5d6 | 3386 | case 0xc3: /* ret */ |
cf5de4f8 | 3387 | c->dst.type = OP_REG; |
1a6440ae | 3388 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3389 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3390 | goto pop_instruction; |
09b5f4d3 WY |
3391 | case 0xc4: /* les */ |
3392 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES); | |
09b5f4d3 WY |
3393 | break; |
3394 | case 0xc5: /* lds */ | |
3395 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS); | |
09b5f4d3 | 3396 | break; |
a77ab5ea AK |
3397 | case 0xcb: /* ret far */ |
3398 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e | 3399 | break; |
6e154e56 MG |
3400 | case 0xcc: /* int3 */ |
3401 | irq = 3; | |
3402 | goto do_interrupt; | |
3403 | case 0xcd: /* int n */ | |
3404 | irq = c->src.val; | |
3405 | do_interrupt: | |
3406 | rc = emulate_int(ctxt, ops, irq); | |
6e154e56 MG |
3407 | break; |
3408 | case 0xce: /* into */ | |
3409 | if (ctxt->eflags & EFLG_OF) { | |
3410 | irq = 4; | |
3411 | goto do_interrupt; | |
3412 | } | |
3413 | break; | |
62bd430e MG |
3414 | case 0xcf: /* iret */ |
3415 | rc = emulate_iret(ctxt, ops); | |
a77ab5ea | 3416 | break; |
018a98db | 3417 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3418 | emulate_grp2(ctxt); |
3419 | break; | |
3420 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3421 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3422 | emulate_grp2(ctxt); | |
3423 | break; | |
f2f31845 WY |
3424 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3425 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3426 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3427 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3428 | jmp_rel(c, c->src.val); | |
3429 | break; | |
e4abac67 WY |
3430 | case 0xe3: /* jcxz/jecxz/jrcxz */ |
3431 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) | |
3432 | jmp_rel(c, c->src.val); | |
3433 | break; | |
a6a3034c MG |
3434 | case 0xe4: /* inb */ |
3435 | case 0xe5: /* in */ | |
cf8f70bf | 3436 | goto do_io_in; |
a6a3034c MG |
3437 | case 0xe6: /* outb */ |
3438 | case 0xe7: /* out */ | |
cf8f70bf | 3439 | goto do_io_out; |
1a52e051 | 3440 | case 0xe8: /* call (near) */ { |
d53c4777 | 3441 | long int rel = c->src.val; |
e4e03ded | 3442 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3443 | jmp_rel(c, rel); |
79168fd1 | 3444 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3445 | break; |
1a52e051 NK |
3446 | } |
3447 | case 0xe9: /* jmp rel */ | |
954cd36f | 3448 | goto jmp; |
414e6277 GN |
3449 | case 0xea: { /* jmp far */ |
3450 | unsigned short sel; | |
ea79849d | 3451 | jump_far: |
414e6277 GN |
3452 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3453 | ||
3454 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3455 | goto done; |
954cd36f | 3456 | |
414e6277 GN |
3457 | c->eip = 0; |
3458 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3459 | break; |
414e6277 | 3460 | } |
954cd36f GT |
3461 | case 0xeb: |
3462 | jmp: /* jmp rel short */ | |
7a957275 | 3463 | jmp_rel(c, c->src.val); |
a01af5ec | 3464 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3465 | break; |
a6a3034c MG |
3466 | case 0xec: /* in al,dx */ |
3467 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3468 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3469 | do_io_in: | |
3470 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3471 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
35d3d4a1 | 3472 | rc = emulate_gp(ctxt, 0); |
cf8f70bf GN |
3473 | goto done; |
3474 | } | |
7b262e90 GN |
3475 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3476 | &c->dst.val)) | |
cf8f70bf GN |
3477 | goto done; /* IO is needed */ |
3478 | break; | |
ce7a0ad3 WY |
3479 | case 0xee: /* out dx,al */ |
3480 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3481 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3482 | do_io_out: |
41167be5 WY |
3483 | c->src.bytes = min(c->src.bytes, 4u); |
3484 | if (!emulator_io_permited(ctxt, ops, c->dst.val, | |
3485 | c->src.bytes)) { | |
35d3d4a1 | 3486 | rc = emulate_gp(ctxt, 0); |
f850e2e6 GN |
3487 | goto done; |
3488 | } | |
41167be5 WY |
3489 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3490 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3491 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3492 | break; |
111de5d6 | 3493 | case 0xf4: /* hlt */ |
ad312c7c | 3494 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3495 | break; |
111de5d6 AK |
3496 | case 0xf5: /* cmc */ |
3497 | /* complement carry flag from eflags reg */ | |
3498 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3499 | break; |
018a98db | 3500 | case 0xf6 ... 0xf7: /* Grp3 */ |
34d1f490 | 3501 | rc = emulate_grp3(ctxt, ops); |
018a98db | 3502 | break; |
111de5d6 AK |
3503 | case 0xf8: /* clc */ |
3504 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3505 | break; |
8744aa9a MG |
3506 | case 0xf9: /* stc */ |
3507 | ctxt->eflags |= EFLG_CF; | |
3508 | break; | |
111de5d6 | 3509 | case 0xfa: /* cli */ |
07cbc6c1 | 3510 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3511 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 | 3512 | goto done; |
36089fed | 3513 | } else |
f850e2e6 | 3514 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3515 | break; |
3516 | case 0xfb: /* sti */ | |
07cbc6c1 | 3517 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3518 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3519 | goto done; |
3520 | } else { | |
95cb2295 | 3521 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3522 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3523 | } |
111de5d6 | 3524 | break; |
fb4616f4 MG |
3525 | case 0xfc: /* cld */ |
3526 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3527 | break; |
3528 | case 0xfd: /* std */ | |
3529 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3530 | break; |
ea79849d GN |
3531 | case 0xfe: /* Grp4 */ |
3532 | grp45: | |
018a98db | 3533 | rc = emulate_grp45(ctxt, ops); |
018a98db | 3534 | break; |
ea79849d GN |
3535 | case 0xff: /* Grp5 */ |
3536 | if (c->modrm_reg == 5) | |
3537 | goto jump_far; | |
3538 | goto grp45; | |
91269b8f AK |
3539 | default: |
3540 | goto cannot_emulate; | |
6aa8b732 | 3541 | } |
018a98db | 3542 | |
7d9ddaed AK |
3543 | if (rc != X86EMUL_CONTINUE) |
3544 | goto done; | |
3545 | ||
018a98db AK |
3546 | writeback: |
3547 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3548 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3549 | goto done; |
3550 | ||
5cd21917 GN |
3551 | /* |
3552 | * restore dst type in case the decoding will be reused | |
3553 | * (happens for string instruction ) | |
3554 | */ | |
3555 | c->dst.type = saved_dst_type; | |
3556 | ||
a682e354 | 3557 | if ((c->d & SrcMask) == SrcSI) |
90de84f5 | 3558 | string_addr_inc(ctxt, seg_override(ctxt, ops, c), |
79168fd1 | 3559 | VCPU_REGS_RSI, &c->src); |
a682e354 GN |
3560 | |
3561 | if ((c->d & DstMask) == DstDI) | |
90de84f5 | 3562 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
79168fd1 | 3563 | &c->dst); |
d9271123 | 3564 | |
5cd21917 | 3565 | if (c->rep_prefix && (c->d & String)) { |
6e2fb2ca | 3566 | struct read_cache *r = &ctxt->decode.io_read; |
d9271123 | 3567 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
3e2f65d5 | 3568 | |
d2ddd1c4 GN |
3569 | if (!string_insn_completed(ctxt)) { |
3570 | /* | |
3571 | * Re-enter guest when pio read ahead buffer is empty | |
3572 | * or, if it is not used, after each 1024 iteration. | |
3573 | */ | |
3574 | if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) && | |
3575 | (r->end == 0 || r->end != r->pos)) { | |
3576 | /* | |
3577 | * Reset read cache. Usually happens before | |
3578 | * decode, but since instruction is restarted | |
3579 | * we have to do it here. | |
3580 | */ | |
3581 | ctxt->decode.mem_read.end = 0; | |
3582 | return EMULATION_RESTART; | |
3583 | } | |
3584 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 3585 | } |
5cd21917 | 3586 | } |
d2ddd1c4 GN |
3587 | |
3588 | ctxt->eip = c->eip; | |
018a98db AK |
3589 | |
3590 | done: | |
da9cb575 AK |
3591 | if (rc == X86EMUL_PROPAGATE_FAULT) |
3592 | ctxt->have_exception = true; | |
d2ddd1c4 | 3593 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
3594 | |
3595 | twobyte_insn: | |
e4e03ded | 3596 | switch (c->b) { |
6aa8b732 | 3597 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3598 | switch (c->modrm_reg) { |
6aa8b732 AK |
3599 | u16 size; |
3600 | unsigned long address; | |
3601 | ||
aca7f966 | 3602 | case 0: /* vmcall */ |
e4e03ded | 3603 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3604 | goto cannot_emulate; |
3605 | ||
7aa81cc0 | 3606 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3607 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3608 | goto done; |
3609 | ||
33e3885d | 3610 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3611 | c->eip = ctxt->eip; |
16286d08 AK |
3612 | /* Disable writeback. */ |
3613 | c->dst.type = OP_NONE; | |
aca7f966 | 3614 | break; |
6aa8b732 | 3615 | case 2: /* lgdt */ |
1a6440ae | 3616 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3617 | &size, &address, c->op_bytes); |
1b30eaa8 | 3618 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3619 | goto done; |
3620 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3621 | /* Disable writeback. */ |
3622 | c->dst.type = OP_NONE; | |
6aa8b732 | 3623 | break; |
aca7f966 | 3624 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3625 | if (c->modrm_mod == 3) { |
3626 | switch (c->modrm_rm) { | |
3627 | case 1: | |
3628 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
2b3d2a20 AK |
3629 | break; |
3630 | default: | |
3631 | goto cannot_emulate; | |
3632 | } | |
aca7f966 | 3633 | } else { |
1a6440ae | 3634 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3635 | &size, &address, |
e4e03ded | 3636 | c->op_bytes); |
1b30eaa8 | 3637 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3638 | goto done; |
3639 | realmode_lidt(ctxt->vcpu, size, address); | |
3640 | } | |
16286d08 AK |
3641 | /* Disable writeback. */ |
3642 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3643 | break; |
3644 | case 4: /* smsw */ | |
16286d08 | 3645 | c->dst.bytes = 2; |
52a46617 | 3646 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3647 | break; |
3648 | case 6: /* lmsw */ | |
9928ff60 | 3649 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3650 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3651 | c->dst.type = OP_NONE; |
6aa8b732 | 3652 | break; |
6e1e5ffe | 3653 | case 5: /* not defined */ |
54b8486f | 3654 | emulate_ud(ctxt); |
da9cb575 | 3655 | rc = X86EMUL_PROPAGATE_FAULT; |
6e1e5ffe | 3656 | goto done; |
6aa8b732 | 3657 | case 7: /* invlpg*/ |
90de84f5 AK |
3658 | emulate_invlpg(ctxt->vcpu, |
3659 | linear(ctxt, c->src.addr.mem)); | |
16286d08 AK |
3660 | /* Disable writeback. */ |
3661 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3662 | break; |
3663 | default: | |
3664 | goto cannot_emulate; | |
3665 | } | |
3666 | break; | |
e99f0507 | 3667 | case 0x05: /* syscall */ |
3fb1b5db | 3668 | rc = emulate_syscall(ctxt, ops); |
e99f0507 | 3669 | break; |
018a98db AK |
3670 | case 0x06: |
3671 | emulate_clts(ctxt->vcpu); | |
018a98db | 3672 | break; |
018a98db | 3673 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3674 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3675 | break; |
3676 | case 0x08: /* invd */ | |
018a98db AK |
3677 | case 0x0d: /* GrpP (prefetch) */ |
3678 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3679 | break; |
3680 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3681 | switch (c->modrm_reg) { |
3682 | case 1: | |
3683 | case 5 ... 7: | |
3684 | case 9 ... 15: | |
54b8486f | 3685 | emulate_ud(ctxt); |
da9cb575 | 3686 | rc = X86EMUL_PROPAGATE_FAULT; |
6aebfa6e GN |
3687 | goto done; |
3688 | } | |
1a0c7d44 | 3689 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3690 | break; |
6aa8b732 | 3691 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3692 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3693 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3694 | emulate_ud(ctxt); |
da9cb575 | 3695 | rc = X86EMUL_PROPAGATE_FAULT; |
1e470be5 GN |
3696 | goto done; |
3697 | } | |
b27f3856 | 3698 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3699 | break; |
018a98db | 3700 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3701 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3702 | emulate_gp(ctxt, 0); |
da9cb575 | 3703 | rc = X86EMUL_PROPAGATE_FAULT; |
0f12244f GN |
3704 | goto done; |
3705 | } | |
018a98db AK |
3706 | c->dst.type = OP_NONE; |
3707 | break; | |
6aa8b732 | 3708 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3709 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3710 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3711 | emulate_ud(ctxt); |
da9cb575 | 3712 | rc = X86EMUL_PROPAGATE_FAULT; |
1e470be5 GN |
3713 | goto done; |
3714 | } | |
35aa5375 | 3715 | |
b27f3856 | 3716 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3717 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3718 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3719 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3720 | emulate_gp(ctxt, 0); |
da9cb575 | 3721 | rc = X86EMUL_PROPAGATE_FAULT; |
338dbc97 GN |
3722 | goto done; |
3723 | } | |
3724 | ||
a01af5ec | 3725 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3726 | break; |
018a98db AK |
3727 | case 0x30: |
3728 | /* wrmsr */ | |
3729 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3730 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3731 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3732 | emulate_gp(ctxt, 0); |
da9cb575 | 3733 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 3734 | goto done; |
018a98db AK |
3735 | } |
3736 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3737 | break; |
3738 | case 0x32: | |
3739 | /* rdmsr */ | |
3fb1b5db | 3740 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3741 | emulate_gp(ctxt, 0); |
da9cb575 | 3742 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 3743 | goto done; |
018a98db AK |
3744 | } else { |
3745 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3746 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3747 | } | |
3748 | rc = X86EMUL_CONTINUE; | |
018a98db | 3749 | break; |
e99f0507 | 3750 | case 0x34: /* sysenter */ |
3fb1b5db | 3751 | rc = emulate_sysenter(ctxt, ops); |
e99f0507 AP |
3752 | break; |
3753 | case 0x35: /* sysexit */ | |
3fb1b5db | 3754 | rc = emulate_sysexit(ctxt, ops); |
e99f0507 | 3755 | break; |
6aa8b732 | 3756 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3757 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3758 | if (!test_cc(c->b, ctxt->eflags)) |
3759 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3760 | break; |
b2833e3c | 3761 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3762 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3763 | jmp_rel(c, c->src.val); |
018a98db | 3764 | break; |
ee45b58e WY |
3765 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
3766 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
3767 | break; | |
0934ac9d | 3768 | case 0xa0: /* push fs */ |
79168fd1 | 3769 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3770 | break; |
3771 | case 0xa1: /* pop fs */ | |
3772 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
0934ac9d | 3773 | break; |
7de75248 NK |
3774 | case 0xa3: |
3775 | bt: /* bt */ | |
e4f8e039 | 3776 | c->dst.type = OP_NONE; |
e4e03ded LV |
3777 | /* only subword offset */ |
3778 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3779 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3780 | break; |
9bf8ea42 GT |
3781 | case 0xa4: /* shld imm8, r, r/m */ |
3782 | case 0xa5: /* shld cl, r, r/m */ | |
3783 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3784 | break; | |
0934ac9d | 3785 | case 0xa8: /* push gs */ |
79168fd1 | 3786 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3787 | break; |
3788 | case 0xa9: /* pop gs */ | |
3789 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
0934ac9d | 3790 | break; |
7de75248 NK |
3791 | case 0xab: |
3792 | bts: /* bts */ | |
05f086f8 | 3793 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3794 | break; |
9bf8ea42 GT |
3795 | case 0xac: /* shrd imm8, r, r/m */ |
3796 | case 0xad: /* shrd cl, r, r/m */ | |
3797 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3798 | break; | |
2a7c5b8b GC |
3799 | case 0xae: /* clflush */ |
3800 | break; | |
6aa8b732 AK |
3801 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3802 | /* | |
3803 | * Save real source value, then compare EAX against | |
3804 | * destination. | |
3805 | */ | |
e4e03ded LV |
3806 | c->src.orig_val = c->src.val; |
3807 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3808 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3809 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3810 | /* Success: write back to memory. */ |
e4e03ded | 3811 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3812 | } else { |
3813 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3814 | c->dst.type = OP_REG; |
1a6440ae | 3815 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3816 | } |
3817 | break; | |
09b5f4d3 WY |
3818 | case 0xb2: /* lss */ |
3819 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS); | |
09b5f4d3 | 3820 | break; |
6aa8b732 AK |
3821 | case 0xb3: |
3822 | btr: /* btr */ | |
05f086f8 | 3823 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3824 | break; |
09b5f4d3 WY |
3825 | case 0xb4: /* lfs */ |
3826 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS); | |
09b5f4d3 WY |
3827 | break; |
3828 | case 0xb5: /* lgs */ | |
3829 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS); | |
09b5f4d3 | 3830 | break; |
6aa8b732 | 3831 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3832 | c->dst.bytes = c->op_bytes; |
3833 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3834 | : (u16) c->src.val; | |
6aa8b732 | 3835 | break; |
6aa8b732 | 3836 | case 0xba: /* Grp8 */ |
e4e03ded | 3837 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3838 | case 0: |
3839 | goto bt; | |
3840 | case 1: | |
3841 | goto bts; | |
3842 | case 2: | |
3843 | goto btr; | |
3844 | case 3: | |
3845 | goto btc; | |
3846 | } | |
3847 | break; | |
7de75248 NK |
3848 | case 0xbb: |
3849 | btc: /* btc */ | |
05f086f8 | 3850 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3851 | break; |
d9574a25 WY |
3852 | case 0xbc: { /* bsf */ |
3853 | u8 zf; | |
3854 | __asm__ ("bsf %2, %0; setz %1" | |
3855 | : "=r"(c->dst.val), "=q"(zf) | |
3856 | : "r"(c->src.val)); | |
3857 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3858 | if (zf) { | |
3859 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3860 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3861 | } | |
3862 | break; | |
3863 | } | |
3864 | case 0xbd: { /* bsr */ | |
3865 | u8 zf; | |
3866 | __asm__ ("bsr %2, %0; setz %1" | |
3867 | : "=r"(c->dst.val), "=q"(zf) | |
3868 | : "r"(c->src.val)); | |
3869 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3870 | if (zf) { | |
3871 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3872 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3873 | } | |
3874 | break; | |
3875 | } | |
6aa8b732 | 3876 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3877 | c->dst.bytes = c->op_bytes; |
3878 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3879 | (s16) c->src.val; | |
6aa8b732 | 3880 | break; |
92f738a5 WY |
3881 | case 0xc0 ... 0xc1: /* xadd */ |
3882 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
3883 | /* Write back the register source. */ | |
3884 | c->src.val = c->dst.orig_val; | |
3885 | write_register_operand(&c->src); | |
3886 | break; | |
a012e65a | 3887 | case 0xc3: /* movnti */ |
e4e03ded LV |
3888 | c->dst.bytes = c->op_bytes; |
3889 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3890 | (u64) c->src.val; | |
a012e65a | 3891 | break; |
6aa8b732 | 3892 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3893 | rc = emulate_grp9(ctxt, ops); |
8cdbd2c9 | 3894 | break; |
91269b8f AK |
3895 | default: |
3896 | goto cannot_emulate; | |
6aa8b732 | 3897 | } |
7d9ddaed AK |
3898 | |
3899 | if (rc != X86EMUL_CONTINUE) | |
3900 | goto done; | |
3901 | ||
6aa8b732 AK |
3902 | goto writeback; |
3903 | ||
3904 | cannot_emulate: | |
6aa8b732 AK |
3905 | return -1; |
3906 | } |