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Merge tag 'kvm-s390-20140721' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms39...
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
6aa8b732 169
820207c8 170#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 171
d0e53325
AK		 172#define X2(x...) x, x
173#define X3(x...) X2(x), x
174#define X4(x...) X2(x), X2(x)
175#define X5(x...) X4(x), x
176#define X6(x...) X4(x), X2(x)
177#define X7(x...) X4(x), X3(x)
178#define X8(x...) X4(x), X4(x)
179#define X16(x...) X8(x), X8(x)
83babbca 180
e28bbd44
AK		 181#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
182#define FASTOP_SIZE 8
183
184/*
185 * fastop functions have a special calling convention:
186 *
017da7b6
AK		 187 * dst: rax (in/out)
188 * src: rdx (in/out)
e28bbd44
AK		 189 * src2: rcx (in)
190 * flags: rflags (in/out)
b8c0b6ae 191 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 192 *
193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
194 * different operand sizes can be reached by calculation, rather than a jump
195 * table (which would be bigger than the code).
196 *
197 * fastop functions are declared as taking a never-defined fastop parameter,
198 * so they can't be called from C directly.
199 */
200
201struct fastop;
202
d65b1dee 203struct opcode {
b1ea50b2
AK		 204 u64 flags : 56;
205 u64 intercept : 8;
120df890 206 union {
ef65c889 207 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 208 const struct opcode *group;
209 const struct group_dual *gdual;
210 const struct gprefix *gprefix;
045a282c 211 const struct escape *esc;
e28bbd44 212 void (*fastop)(struct fastop *fake);
120df890 213 } u;
d09beabd 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 215};
216
217struct group_dual {
218 struct opcode mod012[8];
219 struct opcode mod3[8];
d65b1dee
AK		 220};
221
0d7cdee8
AK		 222struct gprefix {
223 struct opcode pfx_no;
224 struct opcode pfx_66;
225 struct opcode pfx_f2;
226 struct opcode pfx_f3;
227};
228
045a282c
GN		 229struct escape {
230 struct opcode op[8];
231 struct opcode high[64];
232};
233
6aa8b732 234/* EFLAGS bit definitions. */
d4c6a154
GN		 235#define EFLG_ID (1<<21)
236#define EFLG_VIP (1<<20)
237#define EFLG_VIF (1<<19)
238#define EFLG_AC (1<<18)
b1d86143
AP		 239#define EFLG_VM (1<<17)
240#define EFLG_RF (1<<16)
d4c6a154
GN		 241#define EFLG_IOPL (3<<12)
242#define EFLG_NT (1<<14)
6aa8b732
AK		 243#define EFLG_OF (1<<11)
244#define EFLG_DF (1<<10)
b1d86143 245#define EFLG_IF (1<<9)
d4c6a154 246#define EFLG_TF (1<<8)
6aa8b732
AK		 247#define EFLG_SF (1<<7)
248#define EFLG_ZF (1<<6)
249#define EFLG_AF (1<<4)
250#define EFLG_PF (1<<2)
251#define EFLG_CF (1<<0)
252
62bd430e
MG		 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254#define EFLG_RESERVED_ONE_MASK 2
255
dd856efa
AK		 256static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 if (!(ctxt->regs_valid & (1 << nr))) {
259 ctxt->regs_valid |= 1 << nr;
260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
261 }
262 return ctxt->_regs[nr];
263}
264
265static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->regs_dirty |= 1 << nr;
269 return &ctxt->_regs[nr];
270}
271
272static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 reg_read(ctxt, nr);
275 return reg_write(ctxt, nr);
276}
277
278static void writeback_registers(struct x86_emulate_ctxt *ctxt)
279{
280 unsigned reg;
281
282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
284}
285
286static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
287{
288 ctxt->regs_dirty = 0;
289 ctxt->regs_valid = 0;
290}
291
6aa8b732
AK		 292/*
293 * These EFLAGS bits are restored from saved value during emulation, and
294 * any changes are written back to the saved value after emulation.
295 */
296#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
4d758349
AK		 304static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
305
b7d491e7
AK		 306#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
307#define FOP_RET "ret \n\t"
308
309#define FOP_START(op) \
310 extern void em_##op(struct fastop *fake); \
311 asm(".pushsection .text, \"ax\" \n\t" \
312 ".global em_" #op " \n\t" \
313 FOP_ALIGN \
314 "em_" #op ": \n\t"
315
316#define FOP_END \
317 ".popsection")
318
0bdea068
AK		 319#define FOPNOP() FOP_ALIGN FOP_RET
320
b7d491e7 321#define FOP1E(op, dst) \
b8c0b6ae
AK		 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
323
324#define FOP1EEX(op, dst) \
325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 326
327#define FASTOP1(op) \
328 FOP_START(op) \
329 FOP1E(op##b, al) \
330 FOP1E(op##w, ax) \
331 FOP1E(op##l, eax) \
332 ON64(FOP1E(op##q, rax)) \
333 FOP_END
334
b9fa409b
AK		 335/* 1-operand, using src2 (for MUL/DIV r/m) */
336#define FASTOP1SRC2(op, name) \
337 FOP_START(name) \
338 FOP1E(op, cl) \
339 FOP1E(op, cx) \
340 FOP1E(op, ecx) \
341 ON64(FOP1E(op, rcx)) \
342 FOP_END
343
b8c0b6ae
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
345#define FASTOP1SRC2EX(op, name) \
346 FOP_START(name) \
347 FOP1EEX(op, cl) \
348 FOP1EEX(op, cx) \
349 FOP1EEX(op, ecx) \
350 ON64(FOP1EEX(op, rcx)) \
351 FOP_END
352
f7857f35
AK		 353#define FOP2E(op, dst, src) \
354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
355
356#define FASTOP2(op) \
357 FOP_START(op) \
017da7b6
AK		 358 FOP2E(op##b, al, dl) \
359 FOP2E(op##w, ax, dx) \
360 FOP2E(op##l, eax, edx) \
361 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 362 FOP_END
363
11c363ba
AK		 364/* 2 operand, word only */
365#define FASTOP2W(op) \
366 FOP_START(op) \
367 FOPNOP() \
017da7b6
AK		 368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 371 FOP_END
372
007a3b54
AK		 373/* 2 operand, src is CL */
374#define FASTOP2CL(op) \
375 FOP_START(op) \
376 FOP2E(op##b, al, cl) \
377 FOP2E(op##w, ax, cl) \
378 FOP2E(op##l, eax, cl) \
379 ON64(FOP2E(op##q, rax, cl)) \
380 FOP_END
381
0bdea068
AK		 382#define FOP3E(op, dst, src, src2) \
383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
384
385/* 3-operand, word-only, src2=cl */
386#define FASTOP3WCL(op) \
387 FOP_START(op) \
388 FOPNOP() \
017da7b6
AK		 389 FOP3E(op##w, ax, dx, cl) \
390 FOP3E(op##l, eax, edx, cl) \
391 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 392 FOP_END
393
9ae9feba
AK		 394/* Special case for SETcc - 1 instruction per cc */
395#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
396
b8c0b6ae
AK		 397asm(".global kvm_fastop_exception \n"
398 "kvm_fastop_exception: xor %esi, %esi; ret");
399
9ae9feba
AK		 400FOP_START(setcc)
401FOP_SETCC(seto)
402FOP_SETCC(setno)
403FOP_SETCC(setc)
404FOP_SETCC(setnc)
405FOP_SETCC(setz)
406FOP_SETCC(setnz)
407FOP_SETCC(setbe)
408FOP_SETCC(setnbe)
409FOP_SETCC(sets)
410FOP_SETCC(setns)
411FOP_SETCC(setp)
412FOP_SETCC(setnp)
413FOP_SETCC(setl)
414FOP_SETCC(setnl)
415FOP_SETCC(setle)
416FOP_SETCC(setnle)
417FOP_END;
418
326f578f
PB		 419FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
420FOP_END;
421
8a76d7f2
JR		 422static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
423 enum x86_intercept intercept,
424 enum x86_intercept_stage stage)
425{
426 struct x86_instruction_info info = {
427 .intercept = intercept,
9dac77fa
AK		 428 .rep_prefix = ctxt->rep_prefix,
429 .modrm_mod = ctxt->modrm_mod,
430 .modrm_reg = ctxt->modrm_reg,
431 .modrm_rm = ctxt->modrm_rm,
432 .src_val = ctxt->src.val64,
6cbc5f5a 433 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 434 .src_bytes = ctxt->src.bytes,
435 .dst_bytes = ctxt->dst.bytes,
436 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 437 .next_rip = ctxt->eip,
438 };
439
2953538e 440 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 441}
442
f47cfa31
AK		 443static void assign_masked(ulong *dest, ulong src, ulong mask)
444{
445 *dest = (*dest & ~mask) | (src & mask);
446}
447
9dac77fa 448static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 449{
9dac77fa 450 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 451}
452
f47cfa31
AK		 453static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
454{
455 u16 sel;
456 struct desc_struct ss;
457
458 if (ctxt->mode == X86EMUL_MODE_PROT64)
459 return ~0UL;
460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
462}
463
612e89f0
AK		 464static int stack_size(struct x86_emulate_ctxt *ctxt)
465{
466 return (__fls(stack_mask(ctxt)) + 1) >> 3;
467}
468
6aa8b732 469/* Access/update address held in a register, based on addressing mode. */
e4706772 470static inline unsigned long
9dac77fa 471address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 472{
9dac77fa 473 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 474 return reg;
475 else
9dac77fa 476 return reg & ad_mask(ctxt);
e4706772
HH		 477}
478
479static inline unsigned long
9dac77fa 480register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 481{
9dac77fa 482 return address_mask(ctxt, reg);
e4706772
HH		 483}
484
5ad105e5
AK		 485static void masked_increment(ulong *reg, ulong mask, int inc)
486{
487 assign_masked(reg, *reg + inc, mask);
488}
489
7a957275 490static inline void
9dac77fa 491register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 492{
5ad105e5
AK		 493 ulong mask;
494
9dac77fa 495 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 496 mask = ~0UL;
7a957275 497 else
5ad105e5
AK		 498 mask = ad_mask(ctxt);
499 masked_increment(reg, mask, inc);
500}
501
502static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
503{
dd856efa 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 505}
6aa8b732 506
9dac77fa 507static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 508{
9dac77fa 509 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 510}
098c937b 511
56697687
AK		 512static u32 desc_limit_scaled(struct desc_struct *desc)
513{
514 u32 limit = get_desc_limit(desc);
515
516 return desc->g ? (limit << 12) | 0xfff : limit;
517}
518
7b105ca2 519static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 520{
521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
522 return 0;
523
7b105ca2 524 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 525}
526
35d3d4a1
AK		 527static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
528 u32 error, bool valid)
54b8486f 529{
da9cb575
AK		 530 ctxt->exception.vector = vec;
531 ctxt->exception.error_code = error;
532 ctxt->exception.error_code_valid = valid;
35d3d4a1 533 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 534}
535
3b88e41a
JR		 536static int emulate_db(struct x86_emulate_ctxt *ctxt)
537{
538 return emulate_exception(ctxt, DB_VECTOR, 0, false);
539}
540
35d3d4a1 541static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 542{
35d3d4a1 543 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 544}
545
618ff15d
AK		 546static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
547{
548 return emulate_exception(ctxt, SS_VECTOR, err, true);
549}
550
35d3d4a1 551static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 552{
35d3d4a1 553 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 554}
555
35d3d4a1 556static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 557{
35d3d4a1 558 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 559}
560
34d1f490
AK		 561static int emulate_de(struct x86_emulate_ctxt *ctxt)
562{
35d3d4a1 563 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 564}
565
1253791d
AK		 566static int emulate_nm(struct x86_emulate_ctxt *ctxt)
567{
568 return emulate_exception(ctxt, NM_VECTOR, 0, false);
569}
570
1aa36616
AK		 571static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
572{
573 u16 selector;
574 struct desc_struct desc;
575
576 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
577 return selector;
578}
579
580static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
581 unsigned seg)
582{
583 u16 dummy;
584 u32 base3;
585 struct desc_struct desc;
586
587 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
588 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
589}
590
1c11b376
AK		 591/*
592 * x86 defines three classes of vector instructions: explicitly
593 * aligned, explicitly unaligned, and the rest, which change behaviour
594 * depending on whether they're AVX encoded or not.
595 *
596 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
597 * subject to the same check.
598 */
599static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
600{
601 if (likely(size < 16))
602 return false;
603
604 if (ctxt->d & Aligned)
605 return true;
606 else if (ctxt->d & Unaligned)
607 return false;
608 else if (ctxt->d & Avx)
609 return false;
610 else
611 return true;
612}
613
3d9b938e 614static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 615 struct segmented_address addr,
3d9b938e 616 unsigned size, bool write, bool fetch,
52fd8b44
AK		 617 ulong *linear)
618{
618ff15d
AK		 619 struct desc_struct desc;
620 bool usable;
52fd8b44 621 ulong la;
618ff15d 622 u32 lim;
1aa36616 623 u16 sel;
3a78a4f4 624 unsigned cpl;
52fd8b44 625
7b105ca2 626 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 627 switch (ctxt->mode) {
618ff15d
AK		 628 case X86EMUL_MODE_PROT64:
629 if (((signed long)la << 16) >> 16 != la)
630 return emulate_gp(ctxt, 0);
631 break;
632 default:
1aa36616
AK		 633 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
634 addr.seg);
618ff15d
AK		 635 if (!usable)
636 goto bad;
58b7825b
GN		 637 /* code segment in protected mode or read-only data segment */
638 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
639 || !(desc.type & 2)) && write)
618ff15d
AK		 640 goto bad;
641 /* unreadable code segment */
3d9b938e 642 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 643 goto bad;
644 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 645 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
646 (ctxt->d & NoBigReal)) {
647 /* la is between zero and 0xffff */
648 if (la > 0xffff || (u32)(la + size - 1) > 0xffff)
649 goto bad;
650 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d
AK		 651 /* expand-up segment */
652 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
653 goto bad;
654 } else {
fc058680 655 /* expand-down segment */
618ff15d
AK		 656 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
657 goto bad;
658 lim = desc.d ? 0xffffffff : 0xffff;
659 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
660 goto bad;
661 }
717746e3 662 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 663 if (!(desc.type & 8)) {
664 /* data segment */
665 if (cpl > desc.dpl)
666 goto bad;
667 } else if ((desc.type & 8) && !(desc.type & 4)) {
668 /* nonconforming code segment */
669 if (cpl != desc.dpl)
670 goto bad;
671 } else if ((desc.type & 8) && (desc.type & 4)) {
672 /* conforming code segment */
673 if (cpl < desc.dpl)
674 goto bad;
675 }
676 break;
677 }
9dac77fa 678 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 679 la &= (u32)-1;
1c11b376
AK		 680 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
681 return emulate_gp(ctxt, 0);
52fd8b44
AK		 682 *linear = la;
683 return X86EMUL_CONTINUE;
618ff15d
AK		 684bad:
685 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 686 return emulate_ss(ctxt, sel);
618ff15d 687 else
0afbe2f8 688 return emulate_gp(ctxt, sel);
52fd8b44
AK		 689}
690
3d9b938e
NE		 691static int linearize(struct x86_emulate_ctxt *ctxt,
692 struct segmented_address addr,
693 unsigned size, bool write,
694 ulong *linear)
695{
696 return __linearize(ctxt, addr, size, write, false, linear);
697}
698
699
3ca3ac4d
AK		 700static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
701 struct segmented_address addr,
702 void *data,
703 unsigned size)
704{
9fa088f4
AK		 705 int rc;
706 ulong linear;
707
83b8795a 708 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 709 if (rc != X86EMUL_CONTINUE)
710 return rc;
0f65dd70 711 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 712}
713
807941b1 714/*
285ca9e9 715 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 716 * boundary if they are not in fetch_cache yet.
717 */
9506d57d 718static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 719{
62266869 720 int rc;
719d5a9b 721 unsigned size;
285ca9e9 722 unsigned long linear;
17052f16 723 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 724 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 725 .ea = ctxt->eip + cur_size };
726
719d5a9b
PB		 727 size = 15UL ^ cur_size;
728 rc = __linearize(ctxt, addr, size, false, true, &linear);
729 if (unlikely(rc != X86EMUL_CONTINUE))
730 return rc;
731
732 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 733
734 /*
735 * One instruction can only straddle two pages,
736 * and one has been loaded at the beginning of
737 * x86_decode_insn. So, if not enough bytes
738 * still, we must have hit the 15-byte boundary.
739 */
740 if (unlikely(size < op_size))
285ca9e9 741 return X86EMUL_UNHANDLEABLE;
17052f16 742 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 743 size, &ctxt->exception);
744 if (unlikely(rc != X86EMUL_CONTINUE))
745 return rc;
17052f16 746 ctxt->fetch.end += size;
3e2815e9 747 return X86EMUL_CONTINUE;
62266869
AK		 748}
749
9506d57d
PB		 750static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
751 unsigned size)
62266869 752{
17052f16 753 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 754 return __do_insn_fetch_bytes(ctxt, size);
755 else
756 return X86EMUL_CONTINUE;
62266869
AK		 757}
758
67cbc90d 759/* Fetch next part of the instruction being emulated. */
e85a1085 760#define insn_fetch(_type, _ctxt) \
9506d57d 761({ _type _x; \
9506d57d
PB		 762 \
763 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 764 if (rc != X86EMUL_CONTINUE) \
765 goto done; \
9506d57d 766 ctxt->_eip += sizeof(_type); \
17052f16
PB		 767 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
768 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 769 _x; \
67cbc90d
TY		 770})
771
807941b1 772#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 773({ \
9506d57d 774 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 775 if (rc != X86EMUL_CONTINUE) \
776 goto done; \
9506d57d 777 ctxt->_eip += (_size); \
17052f16
PB		 778 memcpy(_arr, ctxt->fetch.ptr, _size); \
779 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 780})
781
1e3c5cb0
RR		 782/*
783 * Given the 'reg' portion of a ModRM byte, and a register block, return a
784 * pointer into the block that addresses the relevant register.
785 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
786 */
dd856efa 787static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 788 int byteop)
6aa8b732
AK		 789{
790 void *p;
aa9ac1a6 791 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 792
6aa8b732 793 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 794 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
795 else
796 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 797 return p;
798}
799
800static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 801 struct segmented_address addr,
6aa8b732
AK		 802 u16 *size, unsigned long *address, int op_bytes)
803{
804 int rc;
805
806 if (op_bytes == 2)
807 op_bytes = 3;
808 *address = 0;
3ca3ac4d 809 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 810 if (rc != X86EMUL_CONTINUE)
6aa8b732 811 return rc;
30b31ab6 812 addr.ea += 2;
3ca3ac4d 813 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 814 return rc;
815}
816
34b77652
AK		 817FASTOP2(add);
818FASTOP2(or);
819FASTOP2(adc);
820FASTOP2(sbb);
821FASTOP2(and);
822FASTOP2(sub);
823FASTOP2(xor);
824FASTOP2(cmp);
825FASTOP2(test);
826
b9fa409b
AK		 827FASTOP1SRC2(mul, mul_ex);
828FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 829FASTOP1SRC2EX(div, div_ex);
830FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 831
34b77652
AK		 832FASTOP3WCL(shld);
833FASTOP3WCL(shrd);
834
835FASTOP2W(imul);
836
837FASTOP1(not);
838FASTOP1(neg);
839FASTOP1(inc);
840FASTOP1(dec);
841
842FASTOP2CL(rol);
843FASTOP2CL(ror);
844FASTOP2CL(rcl);
845FASTOP2CL(rcr);
846FASTOP2CL(shl);
847FASTOP2CL(shr);
848FASTOP2CL(sar);
849
850FASTOP2W(bsf);
851FASTOP2W(bsr);
852FASTOP2W(bt);
853FASTOP2W(bts);
854FASTOP2W(btr);
855FASTOP2W(btc);
856
e47a5f5f
AK		 857FASTOP2(xadd);
858
9ae9feba 859static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 860{
9ae9feba
AK		 861 u8 rc;
862 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 863
9ae9feba 864 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 865 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 866 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
867 return rc;
bbe9abbd
NK		 868}
869
91ff3cb4
AK		 870static void fetch_register_operand(struct operand *op)
871{
872 switch (op->bytes) {
873 case 1:
874 op->val = *(u8 *)op->addr.reg;
875 break;
876 case 2:
877 op->val = *(u16 *)op->addr.reg;
878 break;
879 case 4:
880 op->val = *(u32 *)op->addr.reg;
881 break;
882 case 8:
883 op->val = *(u64 *)op->addr.reg;
884 break;
885 }
886}
887
1253791d
AK		 888static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
889{
890 ctxt->ops->get_fpu(ctxt);
891 switch (reg) {
89a87c67
MK		 892 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
893 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
894 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
895 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
896 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
897 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
898 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
899 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 900#ifdef CONFIG_X86_64
89a87c67
MK		 901 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
902 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
903 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
904 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
905 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
906 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
907 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
908 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 909#endif
910 default: BUG();
911 }
912 ctxt->ops->put_fpu(ctxt);
913}
914
915static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
916 int reg)
917{
918 ctxt->ops->get_fpu(ctxt);
919 switch (reg) {
89a87c67
MK		 920 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
921 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
922 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
923 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
924 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
925 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
926 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
927 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 928#ifdef CONFIG_X86_64
89a87c67
MK		 929 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
930 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
931 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
932 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
933 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
934 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
935 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
936 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 937#endif
938 default: BUG();
939 }
940 ctxt->ops->put_fpu(ctxt);
941}
942
cbe2c9d3
AK		 943static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
944{
945 ctxt->ops->get_fpu(ctxt);
946 switch (reg) {
947 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
948 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
949 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
950 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
951 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
952 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
953 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
954 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
955 default: BUG();
956 }
957 ctxt->ops->put_fpu(ctxt);
958}
959
960static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
961{
962 ctxt->ops->get_fpu(ctxt);
963 switch (reg) {
964 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
965 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
966 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
967 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
968 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
969 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
970 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
971 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
972 default: BUG();
973 }
974 ctxt->ops->put_fpu(ctxt);
975}
976
045a282c
GN		 977static int em_fninit(struct x86_emulate_ctxt *ctxt)
978{
979 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
980 return emulate_nm(ctxt);
981
982 ctxt->ops->get_fpu(ctxt);
983 asm volatile("fninit");
984 ctxt->ops->put_fpu(ctxt);
985 return X86EMUL_CONTINUE;
986}
987
988static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
989{
990 u16 fcw;
991
992 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
993 return emulate_nm(ctxt);
994
995 ctxt->ops->get_fpu(ctxt);
996 asm volatile("fnstcw %0": "+m"(fcw));
997 ctxt->ops->put_fpu(ctxt);
998
999 /* force 2 byte destination */
1000 ctxt->dst.bytes = 2;
1001 ctxt->dst.val = fcw;
1002
1003 return X86EMUL_CONTINUE;
1004}
1005
1006static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1007{
1008 u16 fsw;
1009
1010 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1011 return emulate_nm(ctxt);
1012
1013 ctxt->ops->get_fpu(ctxt);
1014 asm volatile("fnstsw %0": "+m"(fsw));
1015 ctxt->ops->put_fpu(ctxt);
1016
1017 /* force 2 byte destination */
1018 ctxt->dst.bytes = 2;
1019 ctxt->dst.val = fsw;
1020
1021 return X86EMUL_CONTINUE;
1022}
1023
1253791d 1024static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1025 struct operand *op)
3c118e24 1026{
9dac77fa 1027 unsigned reg = ctxt->modrm_reg;
33615aa9 1028
9dac77fa
AK		 1029 if (!(ctxt->d & ModRM))
1030 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1031
9dac77fa 1032 if (ctxt->d & Sse) {
1253791d
AK		 1033 op->type = OP_XMM;
1034 op->bytes = 16;
1035 op->addr.xmm = reg;
1036 read_sse_reg(ctxt, &op->vec_val, reg);
1037 return;
1038 }
cbe2c9d3
AK		 1039 if (ctxt->d & Mmx) {
1040 reg &= 7;
1041 op->type = OP_MM;
1042 op->bytes = 8;
1043 op->addr.mm = reg;
1044 return;
1045 }
1253791d 1046
3c118e24 1047 op->type = OP_REG;
6d4d85ec
GN		 1048 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1049 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1050
91ff3cb4 1051 fetch_register_operand(op);
3c118e24
AK		 1052 op->orig_val = op->val;
1053}
1054
a6e3407b
AK		 1055static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1056{
1057 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1058 ctxt->modrm_seg = VCPU_SREG_SS;
1059}
1060
1c73ef66 1061static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1062 struct operand *op)
1c73ef66 1063{
1c73ef66 1064 u8 sib;
02357bdc 1065 int index_reg, base_reg, scale;
3e2815e9 1066 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1067 ulong modrm_ea = 0;
1c73ef66 1068
02357bdc
BD		 1069 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1070 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1071 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1072
02357bdc 1073 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1074 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1075 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1076 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1077
9b88ae99 1078 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1079 op->type = OP_REG;
9dac77fa 1080 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1081 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1082 ctxt->d & ByteOp);
9dac77fa 1083 if (ctxt->d & Sse) {
1253791d
AK		 1084 op->type = OP_XMM;
1085 op->bytes = 16;
9dac77fa
AK		 1086 op->addr.xmm = ctxt->modrm_rm;
1087 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1088 return rc;
1089 }
cbe2c9d3
AK		 1090 if (ctxt->d & Mmx) {
1091 op->type = OP_MM;
1092 op->bytes = 8;
bdc90722 1093 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1094 return rc;
1095 }
2dbd0dd7 1096 fetch_register_operand(op);
1c73ef66
AK		 1097 return rc;
1098 }
1099
2dbd0dd7
AK		 1100 op->type = OP_MEM;
1101
9dac77fa 1102 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1103 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1104 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1105 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1106 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1107
1108 /* 16-bit ModR/M decode. */
9dac77fa 1109 switch (ctxt->modrm_mod) {
1c73ef66 1110 case 0:
9dac77fa 1111 if (ctxt->modrm_rm == 6)
e85a1085 1112 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1113 break;
1114 case 1:
e85a1085 1115 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1116 break;
1117 case 2:
e85a1085 1118 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1119 break;
1120 }
9dac77fa 1121 switch (ctxt->modrm_rm) {
1c73ef66 1122 case 0:
2dbd0dd7 1123 modrm_ea += bx + si;
1c73ef66
AK		 1124 break;
1125 case 1:
2dbd0dd7 1126 modrm_ea += bx + di;
1c73ef66
AK		 1127 break;
1128 case 2:
2dbd0dd7 1129 modrm_ea += bp + si;
1c73ef66
AK		 1130 break;
1131 case 3:
2dbd0dd7 1132 modrm_ea += bp + di;
1c73ef66
AK		 1133 break;
1134 case 4:
2dbd0dd7 1135 modrm_ea += si;
1c73ef66
AK		 1136 break;
1137 case 5:
2dbd0dd7 1138 modrm_ea += di;
1c73ef66
AK		 1139 break;
1140 case 6:
9dac77fa 1141 if (ctxt->modrm_mod != 0)
2dbd0dd7 1142 modrm_ea += bp;
1c73ef66
AK		 1143 break;
1144 case 7:
2dbd0dd7 1145 modrm_ea += bx;
1c73ef66
AK		 1146 break;
1147 }
9dac77fa
AK		 1148 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1149 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1150 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1151 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1152 } else {
1153 /* 32/64-bit ModR/M decode. */
9dac77fa 1154 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1155 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1156 index_reg |= (sib >> 3) & 7;
1157 base_reg |= sib & 7;
1158 scale = sib >> 6;
1159
9dac77fa 1160 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1161 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1162 else {
dd856efa 1163 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1164 adjust_modrm_seg(ctxt, base_reg);
1165 }
dc71d0f1 1166 if (index_reg != 4)
dd856efa 1167 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1168 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1169 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1170 ctxt->rip_relative = 1;
a6e3407b
AK		 1171 } else {
1172 base_reg = ctxt->modrm_rm;
dd856efa 1173 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1174 adjust_modrm_seg(ctxt, base_reg);
1175 }
9dac77fa 1176 switch (ctxt->modrm_mod) {
1c73ef66 1177 case 0:
9dac77fa 1178 if (ctxt->modrm_rm == 5)
e85a1085 1179 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1180 break;
1181 case 1:
e85a1085 1182 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1183 break;
1184 case 2:
e85a1085 1185 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1186 break;
1187 }
1188 }
90de84f5 1189 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1190 if (ctxt->ad_bytes != 8)
1191 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1192
1c73ef66
AK		 1193done:
1194 return rc;
1195}
1196
1197static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1198 struct operand *op)
1c73ef66 1199{
3e2815e9 1200 int rc = X86EMUL_CONTINUE;
1c73ef66 1201
2dbd0dd7 1202 op->type = OP_MEM;
9dac77fa 1203 switch (ctxt->ad_bytes) {
1c73ef66 1204 case 2:
e85a1085 1205 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1206 break;
1207 case 4:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1209 break;
1210 case 8:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1212 break;
1213 }
1214done:
1215 return rc;
1216}
1217
9dac77fa 1218static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1219{
7129eeca 1220 long sv = 0, mask;
35c843c4 1221
9dac77fa 1222 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1223 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1224
9dac77fa
AK		 1225 if (ctxt->src.bytes == 2)
1226 sv = (s16)ctxt->src.val & (s16)mask;
1227 else if (ctxt->src.bytes == 4)
1228 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1229 else
1230 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1231
9dac77fa 1232 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1233 }
ba7ff2b7
WY		 1234
1235 /* only subword offset */
9dac77fa 1236 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1237}
1238
dde7e6d1 1239static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1240 unsigned long addr, void *dest, unsigned size)
6aa8b732 1241{
dde7e6d1 1242 int rc;
9dac77fa 1243 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1244
f23b070e
XG		 1245 if (mc->pos < mc->end)
1246 goto read_cached;
6aa8b732 1247
f23b070e
XG		 1248 WARN_ON((mc->end + size) >= sizeof(mc->data));
1249
1250 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1251 &ctxt->exception);
1252 if (rc != X86EMUL_CONTINUE)
1253 return rc;
1254
1255 mc->end += size;
1256
1257read_cached:
1258 memcpy(dest, mc->data + mc->pos, size);
1259 mc->pos += size;
dde7e6d1
AK		 1260 return X86EMUL_CONTINUE;
1261}
6aa8b732 1262
3ca3ac4d
AK		 1263static int segmented_read(struct x86_emulate_ctxt *ctxt,
1264 struct segmented_address addr,
1265 void *data,
1266 unsigned size)
1267{
9fa088f4
AK		 1268 int rc;
1269 ulong linear;
1270
83b8795a 1271 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1272 if (rc != X86EMUL_CONTINUE)
1273 return rc;
7b105ca2 1274 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1275}
1276
1277static int segmented_write(struct x86_emulate_ctxt *ctxt,
1278 struct segmented_address addr,
1279 const void *data,
1280 unsigned size)
1281{
9fa088f4
AK		 1282 int rc;
1283 ulong linear;
1284
83b8795a 1285 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1286 if (rc != X86EMUL_CONTINUE)
1287 return rc;
0f65dd70
AK		 1288 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1289 &ctxt->exception);
3ca3ac4d
AK		 1290}
1291
1292static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1293 struct segmented_address addr,
1294 const void *orig_data, const void *data,
1295 unsigned size)
1296{
9fa088f4
AK		 1297 int rc;
1298 ulong linear;
1299
83b8795a 1300 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1301 if (rc != X86EMUL_CONTINUE)
1302 return rc;
0f65dd70
AK		 1303 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1304 size, &ctxt->exception);
3ca3ac4d
AK		 1305}
1306
dde7e6d1 1307static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1308 unsigned int size, unsigned short port,
1309 void *dest)
1310{
9dac77fa 1311 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1312
dde7e6d1 1313 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1314 unsigned int in_page, n;
9dac77fa 1315 unsigned int count = ctxt->rep_prefix ?
dd856efa 1316 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1317 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1318 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1319 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1320 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1321 count);
1322 if (n == 0)
1323 n = 1;
1324 rc->pos = rc->end = 0;
7b105ca2 1325 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1326 return 0;
1327 rc->end = n * size;
6aa8b732
AK		 1328 }
1329
e6e39f04
NA		 1330 if (ctxt->rep_prefix && (ctxt->d & String) &&
1331 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1332 ctxt->dst.data = rc->data + rc->pos;
1333 ctxt->dst.type = OP_MEM_STR;
1334 ctxt->dst.count = (rc->end - rc->pos) / size;
1335 rc->pos = rc->end;
1336 } else {
1337 memcpy(dest, rc->data + rc->pos, size);
1338 rc->pos += size;
1339 }
dde7e6d1
AK		 1340 return 1;
1341}
6aa8b732 1342
7f3d35fd
KW		 1343static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1344 u16 index, struct desc_struct *desc)
1345{
1346 struct desc_ptr dt;
1347 ulong addr;
1348
1349 ctxt->ops->get_idt(ctxt, &dt);
1350
1351 if (dt.size < index * 8 + 7)
1352 return emulate_gp(ctxt, index << 3 | 0x2);
1353
1354 addr = dt.address + index * 8;
1355 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1356 &ctxt->exception);
1357}
1358
dde7e6d1 1359static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1360 u16 selector, struct desc_ptr *dt)
1361{
0225fb50 1362 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1363 u32 base3 = 0;
7b105ca2 1364
dde7e6d1
AK		 1365 if (selector & 1 << 2) {
1366 struct desc_struct desc;
1aa36616
AK		 1367 u16 sel;
1368
dde7e6d1 1369 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1370 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1371 VCPU_SREG_LDTR))
dde7e6d1 1372 return;
e09d082c 1373
dde7e6d1 1374 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1375 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1376 } else
4bff1e86 1377 ops->get_gdt(ctxt, dt);
dde7e6d1 1378}
120df890 1379
dde7e6d1
AK		 1380/* allowed just for 8 bytes segments */
1381static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1382 u16 selector, struct desc_struct *desc,
1383 ulong *desc_addr_p)
dde7e6d1
AK		 1384{
1385 struct desc_ptr dt;
1386 u16 index = selector >> 3;
dde7e6d1 1387 ulong addr;
120df890 1388
7b105ca2 1389 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1390
35d3d4a1
AK		 1391 if (dt.size < index * 8 + 7)
1392 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1393
e919464b 1394 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1395 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1396 &ctxt->exception);
dde7e6d1 1397}
ef65c889 1398
dde7e6d1
AK		 1399/* allowed just for 8 bytes segments */
1400static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1401 u16 selector, struct desc_struct *desc)
1402{
1403 struct desc_ptr dt;
1404 u16 index = selector >> 3;
dde7e6d1 1405 ulong addr;
6aa8b732 1406
7b105ca2 1407 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1408
35d3d4a1
AK		 1409 if (dt.size < index * 8 + 7)
1410 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1411
dde7e6d1 1412 addr = dt.address + index * 8;
7b105ca2
TY		 1413 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1414 &ctxt->exception);
dde7e6d1 1415}
c7e75a3d 1416
5601d05b 1417/* Does not support long mode */
2356aaeb 1418static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1419 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1420{
869be99c 1421 struct desc_struct seg_desc, old_desc;
2356aaeb 1422 u8 dpl, rpl;
dde7e6d1
AK		 1423 unsigned err_vec = GP_VECTOR;
1424 u32 err_code = 0;
1425 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1426 ulong desc_addr;
dde7e6d1 1427 int ret;
03ebebeb 1428 u16 dummy;
e37a75a1 1429 u32 base3 = 0;
69f55cb1 1430
dde7e6d1 1431 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1432
f8da94e9
KW		 1433 if (ctxt->mode == X86EMUL_MODE_REAL) {
1434 /* set real mode segment descriptor (keep limit etc. for
1435 * unreal mode) */
03ebebeb 1436 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1437 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1438 goto load;
f8da94e9
KW		 1439 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1440 /* VM86 needs a clean new segment descriptor */
1441 set_desc_base(&seg_desc, selector << 4);
1442 set_desc_limit(&seg_desc, 0xffff);
1443 seg_desc.type = 3;
1444 seg_desc.p = 1;
1445 seg_desc.s = 1;
1446 seg_desc.dpl = 3;
1447 goto load;
dde7e6d1
AK		 1448 }
1449
79d5b4c3 1450 rpl = selector & 3;
79d5b4c3
AK		 1451
1452 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1453 if ((seg == VCPU_SREG_CS
1454 || (seg == VCPU_SREG_SS
1455 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1456 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1457 && null_selector)
1458 goto exception;
1459
1460 /* TR should be in GDT only */
1461 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1462 goto exception;
1463
1464 if (null_selector) /* for NULL selector skip all following checks */
1465 goto load;
1466
e919464b 1467 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1468 if (ret != X86EMUL_CONTINUE)
1469 return ret;
1470
1471 err_code = selector & 0xfffc;
1472 err_vec = GP_VECTOR;
1473
fc058680 1474 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1475 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1476 goto exception;
1477
1478 if (!seg_desc.p) {
1479 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1480 goto exception;
1481 }
1482
dde7e6d1 1483 dpl = seg_desc.dpl;
dde7e6d1
AK		 1484
1485 switch (seg) {
1486 case VCPU_SREG_SS:
1487 /*
1488 * segment is not a writable data segment or segment
1489 * selector's RPL != CPL or segment selector's RPL != CPL
1490 */
1491 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1492 goto exception;
6aa8b732 1493 break;
dde7e6d1 1494 case VCPU_SREG_CS:
5045b468
PB		 1495 if (in_task_switch && rpl != dpl)
1496 goto exception;
1497
dde7e6d1
AK		 1498 if (!(seg_desc.type & 8))
1499 goto exception;
1500
1501 if (seg_desc.type & 4) {
1502 /* conforming */
1503 if (dpl > cpl)
1504 goto exception;
1505 } else {
1506 /* nonconforming */
1507 if (rpl > cpl || dpl != cpl)
1508 goto exception;
1509 }
1510 /* CS(RPL) <- CPL */
1511 selector = (selector & 0xfffc) | cpl;
6aa8b732 1512 break;
dde7e6d1
AK		 1513 case VCPU_SREG_TR:
1514 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1515 goto exception;
869be99c
AK		 1516 old_desc = seg_desc;
1517 seg_desc.type |= 2; /* busy */
1518 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1519 sizeof(seg_desc), &ctxt->exception);
1520 if (ret != X86EMUL_CONTINUE)
1521 return ret;
dde7e6d1
AK		 1522 break;
1523 case VCPU_SREG_LDTR:
1524 if (seg_desc.s || seg_desc.type != 2)
1525 goto exception;
1526 break;
1527 default: /* DS, ES, FS, or GS */
4e62417b 1528 /*
dde7e6d1
AK		 1529 * segment is not a data or readable code segment or
1530 * ((segment is a data or nonconforming code segment)
1531 * and (both RPL and CPL > DPL))
4e62417b 1532 */
dde7e6d1
AK		 1533 if ((seg_desc.type & 0xa) == 0x8 ||
1534 (((seg_desc.type & 0xc) != 0xc) &&
1535 (rpl > dpl && cpl > dpl)))
1536 goto exception;
6aa8b732 1537 break;
dde7e6d1
AK		 1538 }
1539
1540 if (seg_desc.s) {
1541 /* mark segment as accessed */
1542 seg_desc.type |= 1;
7b105ca2 1543 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1544 if (ret != X86EMUL_CONTINUE)
1545 return ret;
e37a75a1
NA		 1546 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1547 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1548 sizeof(base3), &ctxt->exception);
1549 if (ret != X86EMUL_CONTINUE)
1550 return ret;
dde7e6d1
AK		 1551 }
1552load:
e37a75a1 1553 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1554 return X86EMUL_CONTINUE;
1555exception:
1556 emulate_exception(ctxt, err_vec, err_code, true);
1557 return X86EMUL_PROPAGATE_FAULT;
1558}
1559
2356aaeb
PB		 1560static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1561 u16 selector, int seg)
1562{
1563 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1564 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1565}
1566
31be40b3
WY		 1567static void write_register_operand(struct operand *op)
1568{
1569 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1570 switch (op->bytes) {
1571 case 1:
1572 *(u8 *)op->addr.reg = (u8)op->val;
1573 break;
1574 case 2:
1575 *(u16 *)op->addr.reg = (u16)op->val;
1576 break;
1577 case 4:
1578 *op->addr.reg = (u32)op->val;
1579 break; /* 64b: zero-extend */
1580 case 8:
1581 *op->addr.reg = op->val;
1582 break;
1583 }
1584}
1585
fb32b1ed 1586static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1587{
fb32b1ed 1588 switch (op->type) {
dde7e6d1 1589 case OP_REG:
fb32b1ed 1590 write_register_operand(op);
6aa8b732 1591 break;
dde7e6d1 1592 case OP_MEM:
9dac77fa 1593 if (ctxt->lock_prefix)
f5f87dfb
PB		 1594 return segmented_cmpxchg(ctxt,
1595 op->addr.mem,
1596 &op->orig_val,
1597 &op->val,
1598 op->bytes);
1599 else
1600 return segmented_write(ctxt,
fb32b1ed 1601 op->addr.mem,
fb32b1ed
AK		 1602 &op->val,
1603 op->bytes);
a682e354 1604 break;
b3356bf0 1605 case OP_MEM_STR:
f5f87dfb
PB		 1606 return segmented_write(ctxt,
1607 op->addr.mem,
1608 op->data,
1609 op->bytes * op->count);
b3356bf0 1610 break;
1253791d 1611 case OP_XMM:
fb32b1ed 1612 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1613 break;
cbe2c9d3 1614 case OP_MM:
fb32b1ed 1615 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1616 break;
dde7e6d1
AK		 1617 case OP_NONE:
1618 /* no writeback */
414e6277 1619 break;
dde7e6d1 1620 default:
414e6277 1621 break;
6aa8b732 1622 }
dde7e6d1
AK		 1623 return X86EMUL_CONTINUE;
1624}
6aa8b732 1625
51ddff50 1626static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1627{
4179bb02 1628 struct segmented_address addr;
0dc8d10f 1629
5ad105e5 1630 rsp_increment(ctxt, -bytes);
dd856efa 1631 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1632 addr.seg = VCPU_SREG_SS;
1633
51ddff50
AK		 1634 return segmented_write(ctxt, addr, data, bytes);
1635}
1636
1637static int em_push(struct x86_emulate_ctxt *ctxt)
1638{
4179bb02 1639 /* Disable writeback. */
9dac77fa 1640 ctxt->dst.type = OP_NONE;
51ddff50 1641 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1642}
69f55cb1 1643
dde7e6d1 1644static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1645 void *dest, int len)
1646{
dde7e6d1 1647 int rc;
90de84f5 1648 struct segmented_address addr;
8b4caf66 1649
dd856efa 1650 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1651 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1652 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1653 if (rc != X86EMUL_CONTINUE)
1654 return rc;
1655
5ad105e5 1656 rsp_increment(ctxt, len);
dde7e6d1 1657 return rc;
8b4caf66
LV		 1658}
1659
c54fe504
TY		 1660static int em_pop(struct x86_emulate_ctxt *ctxt)
1661{
9dac77fa 1662 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1663}
1664
dde7e6d1 1665static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1666 void *dest, int len)
9de41573
GN		 1667{
1668 int rc;
dde7e6d1
AK		 1669 unsigned long val, change_mask;
1670 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1671 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1672
3b9be3bf 1673 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1674 if (rc != X86EMUL_CONTINUE)
1675 return rc;
9de41573 1676
dde7e6d1 1677 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1678 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1679
dde7e6d1
AK		 1680 switch(ctxt->mode) {
1681 case X86EMUL_MODE_PROT64:
1682 case X86EMUL_MODE_PROT32:
1683 case X86EMUL_MODE_PROT16:
1684 if (cpl == 0)
1685 change_mask |= EFLG_IOPL;
1686 if (cpl <= iopl)
1687 change_mask |= EFLG_IF;
1688 break;
1689 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1690 if (iopl < 3)
1691 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1692 change_mask |= EFLG_IF;
1693 break;
1694 default: /* real mode */
1695 change_mask |= (EFLG_IOPL | EFLG_IF);
1696 break;
9de41573 1697 }
dde7e6d1
AK		 1698
1699 *(unsigned long *)dest =
1700 (ctxt->eflags & ~change_mask) | (val & change_mask);
1701
1702 return rc;
9de41573
GN		 1703}
1704
62aaa2f0
TY		 1705static int em_popf(struct x86_emulate_ctxt *ctxt)
1706{
9dac77fa
AK		 1707 ctxt->dst.type = OP_REG;
1708 ctxt->dst.addr.reg = &ctxt->eflags;
1709 ctxt->dst.bytes = ctxt->op_bytes;
1710 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1711}
1712
612e89f0
AK		 1713static int em_enter(struct x86_emulate_ctxt *ctxt)
1714{
1715 int rc;
1716 unsigned frame_size = ctxt->src.val;
1717 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1718 ulong rbp;
612e89f0
AK		 1719
1720 if (nesting_level)
1721 return X86EMUL_UNHANDLEABLE;
1722
dd856efa
AK		 1723 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1724 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1725 if (rc != X86EMUL_CONTINUE)
1726 return rc;
dd856efa 1727 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1728 stack_mask(ctxt));
dd856efa
AK		 1729 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1730 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1731 stack_mask(ctxt));
1732 return X86EMUL_CONTINUE;
1733}
1734
f47cfa31
AK		 1735static int em_leave(struct x86_emulate_ctxt *ctxt)
1736{
dd856efa 1737 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1738 stack_mask(ctxt));
dd856efa 1739 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1740}
1741
1cd196ea 1742static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1743{
1cd196ea
AK		 1744 int seg = ctxt->src2.val;
1745
9dac77fa 1746 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1747
4487b3b4 1748 return em_push(ctxt);
7b262e90
GN		 1749}
1750
1cd196ea 1751static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1752{
1cd196ea 1753 int seg = ctxt->src2.val;
dde7e6d1
AK		 1754 unsigned long selector;
1755 int rc;
38ba30ba 1756
9dac77fa 1757 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
1760
a5457e7b
PB		 1761 if (ctxt->modrm_reg == VCPU_SREG_SS)
1762 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1763
7b105ca2 1764 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1765 return rc;
38ba30ba
GN		 1766}
1767
b96a7fad 1768static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1769{
dd856efa 1770 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1771 int rc = X86EMUL_CONTINUE;
1772 int reg = VCPU_REGS_RAX;
38ba30ba 1773
dde7e6d1
AK		 1774 while (reg <= VCPU_REGS_RDI) {
1775 (reg == VCPU_REGS_RSP) ?
dd856efa 1776 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1777
4487b3b4 1778 rc = em_push(ctxt);
dde7e6d1
AK		 1779 if (rc != X86EMUL_CONTINUE)
1780 return rc;
38ba30ba 1781
dde7e6d1 1782 ++reg;
38ba30ba 1783 }
38ba30ba 1784
dde7e6d1 1785 return rc;
38ba30ba
GN		 1786}
1787
62aaa2f0
TY		 1788static int em_pushf(struct x86_emulate_ctxt *ctxt)
1789{
9dac77fa 1790 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1791 return em_push(ctxt);
1792}
1793
b96a7fad 1794static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1795{
dde7e6d1
AK		 1796 int rc = X86EMUL_CONTINUE;
1797 int reg = VCPU_REGS_RDI;
38ba30ba 1798
dde7e6d1
AK		 1799 while (reg >= VCPU_REGS_RAX) {
1800 if (reg == VCPU_REGS_RSP) {
5ad105e5 1801 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1802 --reg;
1803 }
38ba30ba 1804
dd856efa 1805 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1806 if (rc != X86EMUL_CONTINUE)
1807 break;
1808 --reg;
38ba30ba 1809 }
dde7e6d1 1810 return rc;
38ba30ba
GN		 1811}
1812
dd856efa 1813static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1814{
0225fb50 1815 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1816 int rc;
6e154e56
MG		 1817 struct desc_ptr dt;
1818 gva_t cs_addr;
1819 gva_t eip_addr;
1820 u16 cs, eip;
6e154e56
MG		 1821
1822 /* TODO: Add limit checks */
9dac77fa 1823 ctxt->src.val = ctxt->eflags;
4487b3b4 1824 rc = em_push(ctxt);
5c56e1cf
AK		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
6e154e56
MG		 1827
1828 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1829
9dac77fa 1830 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1831 rc = em_push(ctxt);
5c56e1cf
AK		 1832 if (rc != X86EMUL_CONTINUE)
1833 return rc;
6e154e56 1834
9dac77fa 1835 ctxt->src.val = ctxt->_eip;
4487b3b4 1836 rc = em_push(ctxt);
5c56e1cf
AK		 1837 if (rc != X86EMUL_CONTINUE)
1838 return rc;
1839
4bff1e86 1840 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1841
1842 eip_addr = dt.address + (irq << 2);
1843 cs_addr = dt.address + (irq << 2) + 2;
1844
0f65dd70 1845 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
0f65dd70 1849 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1850 if (rc != X86EMUL_CONTINUE)
1851 return rc;
1852
7b105ca2 1853 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1854 if (rc != X86EMUL_CONTINUE)
1855 return rc;
1856
9dac77fa 1857 ctxt->_eip = eip;
6e154e56
MG		 1858
1859 return rc;
1860}
1861
dd856efa
AK		 1862int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1863{
1864 int rc;
1865
1866 invalidate_registers(ctxt);
1867 rc = __emulate_int_real(ctxt, irq);
1868 if (rc == X86EMUL_CONTINUE)
1869 writeback_registers(ctxt);
1870 return rc;
1871}
1872
7b105ca2 1873static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1874{
1875 switch(ctxt->mode) {
1876 case X86EMUL_MODE_REAL:
dd856efa 1877 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1878 case X86EMUL_MODE_VM86:
1879 case X86EMUL_MODE_PROT16:
1880 case X86EMUL_MODE_PROT32:
1881 case X86EMUL_MODE_PROT64:
1882 default:
1883 /* Protected mode interrupts unimplemented yet */
1884 return X86EMUL_UNHANDLEABLE;
1885 }
1886}
1887
7b105ca2 1888static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1889{
dde7e6d1
AK		 1890 int rc = X86EMUL_CONTINUE;
1891 unsigned long temp_eip = 0;
1892 unsigned long temp_eflags = 0;
1893 unsigned long cs = 0;
1894 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1895 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1896 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1897 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1898
dde7e6d1 1899 /* TODO: Add stack limit check */
38ba30ba 1900
9dac77fa 1901 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1902
dde7e6d1
AK		 1903 if (rc != X86EMUL_CONTINUE)
1904 return rc;
38ba30ba 1905
35d3d4a1
AK		 1906 if (temp_eip & ~0xffff)
1907 return emulate_gp(ctxt, 0);
38ba30ba 1908
9dac77fa 1909 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1910
dde7e6d1
AK		 1911 if (rc != X86EMUL_CONTINUE)
1912 return rc;
38ba30ba 1913
9dac77fa 1914 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1915
dde7e6d1
AK		 1916 if (rc != X86EMUL_CONTINUE)
1917 return rc;
38ba30ba 1918
7b105ca2 1919 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1920
dde7e6d1
AK		 1921 if (rc != X86EMUL_CONTINUE)
1922 return rc;
38ba30ba 1923
9dac77fa 1924 ctxt->_eip = temp_eip;
38ba30ba 1925
38ba30ba 1926
9dac77fa 1927 if (ctxt->op_bytes == 4)
dde7e6d1 1928 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1929 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1930 ctxt->eflags &= ~0xffff;
1931 ctxt->eflags |= temp_eflags;
38ba30ba 1932 }
dde7e6d1
AK		 1933
1934 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1935 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1936
1937 return rc;
38ba30ba
GN		 1938}
1939
e01991e7 1940static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1941{
dde7e6d1
AK		 1942 switch(ctxt->mode) {
1943 case X86EMUL_MODE_REAL:
7b105ca2 1944 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1945 case X86EMUL_MODE_VM86:
1946 case X86EMUL_MODE_PROT16:
1947 case X86EMUL_MODE_PROT32:
1948 case X86EMUL_MODE_PROT64:
c37eda13 1949 default:
dde7e6d1
AK		 1950 /* iret from protected mode unimplemented yet */
1951 return X86EMUL_UNHANDLEABLE;
c37eda13 1952 }
c37eda13
WY		 1953}
1954
d2f62766
TY		 1955static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1956{
d2f62766
TY		 1957 int rc;
1958 unsigned short sel;
1959
9dac77fa 1960 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1961
7b105ca2 1962 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1963 if (rc != X86EMUL_CONTINUE)
1964 return rc;
1965
9dac77fa
AK		 1966 ctxt->_eip = 0;
1967 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1968 return X86EMUL_CONTINUE;
1969}
1970
51187683 1971static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1972{
4179bb02 1973 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1974
9dac77fa 1975 switch (ctxt->modrm_reg) {
d19292e4
MG		 1976 case 2: /* call near abs */ {
1977 long int old_eip;
9dac77fa
AK		 1978 old_eip = ctxt->_eip;
1979 ctxt->_eip = ctxt->src.val;
1980 ctxt->src.val = old_eip;
4487b3b4 1981 rc = em_push(ctxt);
d19292e4
MG		 1982 break;
1983 }
8cdbd2c9 1984 case 4: /* jmp abs */
9dac77fa 1985 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1986 break;
d2f62766
TY		 1987 case 5: /* jmp far */
1988 rc = em_jmp_far(ctxt);
1989 break;
8cdbd2c9 1990 case 6: /* push */
4487b3b4 1991 rc = em_push(ctxt);
8cdbd2c9 1992 break;
8cdbd2c9 1993 }
4179bb02 1994 return rc;
8cdbd2c9
LV		 1995}
1996
e0dac408 1997static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1998{
9dac77fa 1999 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2000
aaa05f24
NA		 2001 if (ctxt->dst.bytes == 16)
2002 return X86EMUL_UNHANDLEABLE;
2003
dd856efa
AK		 2004 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2005 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2006 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2007 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2008 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2009 } else {
dd856efa
AK		 2010 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2011 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2012
05f086f8 2013 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2014 }
1b30eaa8 2015 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2016}
2017
ebda02c2
TY		 2018static int em_ret(struct x86_emulate_ctxt *ctxt)
2019{
9dac77fa
AK		 2020 ctxt->dst.type = OP_REG;
2021 ctxt->dst.addr.reg = &ctxt->_eip;
2022 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2023 return em_pop(ctxt);
2024}
2025
e01991e7 2026static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2027{
a77ab5ea
AK		 2028 int rc;
2029 unsigned long cs;
9e8919ae 2030 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2031
9dac77fa 2032 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2033 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2034 return rc;
9dac77fa
AK		 2035 if (ctxt->op_bytes == 4)
2036 ctxt->_eip = (u32)ctxt->_eip;
2037 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2038 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2039 return rc;
9e8919ae
NA		 2040 /* Outer-privilege level return is not implemented */
2041 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2042 return X86EMUL_UNHANDLEABLE;
7b105ca2 2043 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2044 return rc;
2045}
2046
3261107e
BR		 2047static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2048{
2049 int rc;
2050
2051 rc = em_ret_far(ctxt);
2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
2054 rsp_increment(ctxt, ctxt->src.val);
2055 return X86EMUL_CONTINUE;
2056}
2057
e940b5c2
TY		 2058static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2059{
2060 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2061 ctxt->dst.orig_val = ctxt->dst.val;
2062 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2063 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2064 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2065 fastop(ctxt, em_cmp);
e940b5c2
TY		 2066
2067 if (ctxt->eflags & EFLG_ZF) {
2068 /* Success: write back to memory. */
2069 ctxt->dst.val = ctxt->src.orig_val;
2070 } else {
2071 /* Failure: write the value we saw to EAX. */
2072 ctxt->dst.type = OP_REG;
dd856efa 2073 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2074 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2075 }
2076 return X86EMUL_CONTINUE;
2077}
2078
d4b4325f 2079static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2080{
d4b4325f 2081 int seg = ctxt->src2.val;
09b5f4d3
WY		 2082 unsigned short sel;
2083 int rc;
2084
9dac77fa 2085 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2086
7b105ca2 2087 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2088 if (rc != X86EMUL_CONTINUE)
2089 return rc;
2090
9dac77fa 2091 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2092 return rc;
2093}
2094
7b105ca2 2095static void
e66bb2cc 2096setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2097 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2098{
e66bb2cc 2099 cs->l = 0; /* will be adjusted later */
79168fd1 2100 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2101 cs->g = 1; /* 4kb granularity */
79168fd1 2102 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2103 cs->type = 0x0b; /* Read, Execute, Accessed */
2104 cs->s = 1;
2105 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2106 cs->p = 1;
2107 cs->d = 1;
99245b50 2108 cs->avl = 0;
e66bb2cc 2109
79168fd1
GN		 2110 set_desc_base(ss, 0); /* flat segment */
2111 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2112 ss->g = 1; /* 4kb granularity */
2113 ss->s = 1;
2114 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2115 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2116 ss->dpl = 0;
79168fd1 2117 ss->p = 1;
99245b50
GN		 2118 ss->l = 0;
2119 ss->avl = 0;
e66bb2cc
AP		 2120}
2121
1a18a69b
AK		 2122static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2123{
2124 u32 eax, ebx, ecx, edx;
2125
2126 eax = ecx = 0;
0017f93a
AK		 2127 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2128 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2129 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2130 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2131}
2132
c2226fc9
SB		 2133static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2134{
0225fb50 2135 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2136 u32 eax, ebx, ecx, edx;
2137
2138 /*
2139 * syscall should always be enabled in longmode - so only become
2140 * vendor specific (cpuid) if other modes are active...
2141 */
2142 if (ctxt->mode == X86EMUL_MODE_PROT64)
2143 return true;
2144
2145 eax = 0x00000000;
2146 ecx = 0x00000000;
0017f93a
AK		 2147 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2148 /*
2149 * Intel ("GenuineIntel")
2150 * remark: Intel CPUs only support "syscall" in 64bit
2151 * longmode. Also an 64bit guest with a
2152 * 32bit compat-app running will #UD !! While this
2153 * behaviour can be fixed (by emulating) into AMD
2154 * response - CPUs of AMD can't behave like Intel.
2155 */
2156 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2157 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2158 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2159 return false;
2160
2161 /* AMD ("AuthenticAMD") */
2162 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2163 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2164 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2165 return true;
2166
2167 /* AMD ("AMDisbetter!") */
2168 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2169 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2170 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2171 return true;
c2226fc9
SB		 2172
2173 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2174 return false;
2175}
2176
e01991e7 2177static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2178{
0225fb50 2179 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2180 struct desc_struct cs, ss;
e66bb2cc 2181 u64 msr_data;
79168fd1 2182 u16 cs_sel, ss_sel;
c2ad2bb3 2183 u64 efer = 0;
e66bb2cc
AP		 2184
2185 /* syscall is not available in real mode */
2e901c4c 2186 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2187 ctxt->mode == X86EMUL_MODE_VM86)
2188 return emulate_ud(ctxt);
e66bb2cc 2189
c2226fc9
SB		 2190 if (!(em_syscall_is_enabled(ctxt)))
2191 return emulate_ud(ctxt);
2192
c2ad2bb3 2193 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2194 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2195
c2226fc9
SB		 2196 if (!(efer & EFER_SCE))
2197 return emulate_ud(ctxt);
2198
717746e3 2199 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2200 msr_data >>= 32;
79168fd1
GN		 2201 cs_sel = (u16)(msr_data & 0xfffc);
2202 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2203
c2ad2bb3 2204 if (efer & EFER_LMA) {
79168fd1 2205 cs.d = 0;
e66bb2cc
AP		 2206 cs.l = 1;
2207 }
1aa36616
AK		 2208 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2209 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2210
dd856efa 2211 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2212 if (efer & EFER_LMA) {
e66bb2cc 2213#ifdef CONFIG_X86_64
6c6cb69b 2214 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2215
717746e3 2216 ops->get_msr(ctxt,
3fb1b5db
GN		 2217 ctxt->mode == X86EMUL_MODE_PROT64 ?
2218 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2219 ctxt->_eip = msr_data;
e66bb2cc 2220
717746e3 2221 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2222 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2223#endif
2224 } else {
2225 /* legacy mode */
717746e3 2226 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2227 ctxt->_eip = (u32)msr_data;
e66bb2cc 2228
6c6cb69b 2229 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2230 }
2231
e54cfa97 2232 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2233}
2234
e01991e7 2235static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2236{
0225fb50 2237 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2238 struct desc_struct cs, ss;
8c604352 2239 u64 msr_data;
79168fd1 2240 u16 cs_sel, ss_sel;
c2ad2bb3 2241 u64 efer = 0;
8c604352 2242
7b105ca2 2243 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2244 /* inject #GP if in real mode */
35d3d4a1
AK		 2245 if (ctxt->mode == X86EMUL_MODE_REAL)
2246 return emulate_gp(ctxt, 0);
8c604352 2247
1a18a69b
AK		 2248 /*
2249 * Not recognized on AMD in compat mode (but is recognized in legacy
2250 * mode).
2251 */
2252 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2253 && !vendor_intel(ctxt))
2254 return emulate_ud(ctxt);
2255
8c604352
AP		 2256 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2257 * Therefore, we inject an #UD.
2258 */
35d3d4a1
AK		 2259 if (ctxt->mode == X86EMUL_MODE_PROT64)
2260 return emulate_ud(ctxt);
8c604352 2261
7b105ca2 2262 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2263
717746e3 2264 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2265 switch (ctxt->mode) {
2266 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2267 if ((msr_data & 0xfffc) == 0x0)
2268 return emulate_gp(ctxt, 0);
8c604352
AP		 2269 break;
2270 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2271 if (msr_data == 0x0)
2272 return emulate_gp(ctxt, 0);
8c604352 2273 break;
9d1b39a9
GN		 2274 default:
2275 break;
8c604352
AP		 2276 }
2277
6c6cb69b 2278 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2279 cs_sel = (u16)msr_data;
2280 cs_sel &= ~SELECTOR_RPL_MASK;
2281 ss_sel = cs_sel + 8;
2282 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2283 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2284 cs.d = 0;
8c604352
AP		 2285 cs.l = 1;
2286 }
2287
1aa36616
AK		 2288 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2289 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2290
717746e3 2291 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2292 ctxt->_eip = msr_data;
8c604352 2293
717746e3 2294 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2295 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2296
e54cfa97 2297 return X86EMUL_CONTINUE;
8c604352
AP		 2298}
2299
e01991e7 2300static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2301{
0225fb50 2302 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2303 struct desc_struct cs, ss;
4668f050
AP		 2304 u64 msr_data;
2305 int usermode;
1249b96e 2306 u16 cs_sel = 0, ss_sel = 0;
4668f050 2307
a0044755
GN		 2308 /* inject #GP if in real mode or Virtual 8086 mode */
2309 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2310 ctxt->mode == X86EMUL_MODE_VM86)
2311 return emulate_gp(ctxt, 0);
4668f050 2312
7b105ca2 2313 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2314
9dac77fa 2315 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2316 usermode = X86EMUL_MODE_PROT64;
2317 else
2318 usermode = X86EMUL_MODE_PROT32;
2319
2320 cs.dpl = 3;
2321 ss.dpl = 3;
717746e3 2322 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2323 switch (usermode) {
2324 case X86EMUL_MODE_PROT32:
79168fd1 2325 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2326 if ((msr_data & 0xfffc) == 0x0)
2327 return emulate_gp(ctxt, 0);
79168fd1 2328 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2329 break;
2330 case X86EMUL_MODE_PROT64:
79168fd1 2331 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2332 if (msr_data == 0x0)
2333 return emulate_gp(ctxt, 0);
79168fd1
GN		 2334 ss_sel = cs_sel + 8;
2335 cs.d = 0;
4668f050
AP		 2336 cs.l = 1;
2337 break;
2338 }
79168fd1
GN		 2339 cs_sel |= SELECTOR_RPL_MASK;
2340 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2341
1aa36616
AK		 2342 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2343 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2344
dd856efa
AK		 2345 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2346 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2347
e54cfa97 2348 return X86EMUL_CONTINUE;
4668f050
AP		 2349}
2350
7b105ca2 2351static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2352{
2353 int iopl;
2354 if (ctxt->mode == X86EMUL_MODE_REAL)
2355 return false;
2356 if (ctxt->mode == X86EMUL_MODE_VM86)
2357 return true;
2358 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2359 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2360}
2361
2362static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2363 u16 port, u16 len)
2364{
0225fb50 2365 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2366 struct desc_struct tr_seg;
5601d05b 2367 u32 base3;
f850e2e6 2368 int r;
1aa36616 2369 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2370 unsigned mask = (1 << len) - 1;
5601d05b 2371 unsigned long base;
f850e2e6 2372
1aa36616 2373 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2374 if (!tr_seg.p)
f850e2e6 2375 return false;
79168fd1 2376 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2377 return false;
5601d05b
GN		 2378 base = get_desc_base(&tr_seg);
2379#ifdef CONFIG_X86_64
2380 base |= ((u64)base3) << 32;
2381#endif
0f65dd70 2382 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2383 if (r != X86EMUL_CONTINUE)
2384 return false;
79168fd1 2385 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2386 return false;
0f65dd70 2387 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2388 if (r != X86EMUL_CONTINUE)
2389 return false;
2390 if ((perm >> bit_idx) & mask)
2391 return false;
2392 return true;
2393}
2394
2395static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2396 u16 port, u16 len)
2397{
4fc40f07
GN		 2398 if (ctxt->perm_ok)
2399 return true;
2400
7b105ca2
TY		 2401 if (emulator_bad_iopl(ctxt))
2402 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2403 return false;
4fc40f07
GN		 2404
2405 ctxt->perm_ok = true;
2406
f850e2e6
GN		 2407 return true;
2408}
2409
38ba30ba 2410static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2411 struct tss_segment_16 *tss)
2412{
9dac77fa 2413 tss->ip = ctxt->_eip;
38ba30ba 2414 tss->flag = ctxt->eflags;
dd856efa
AK		 2415 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2416 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2417 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2418 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2419 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2420 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2421 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2422 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2423
1aa36616
AK		 2424 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2425 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2426 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2427 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2428 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2429}
2430
2431static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2432 struct tss_segment_16 *tss)
2433{
38ba30ba 2434 int ret;
2356aaeb 2435 u8 cpl;
38ba30ba 2436
9dac77fa 2437 ctxt->_eip = tss->ip;
38ba30ba 2438 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2439 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2440 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2441 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2442 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2443 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2444 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2445 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2446 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2447
2448 /*
2449 * SDM says that segment selectors are loaded before segment
2450 * descriptors
2451 */
1aa36616
AK		 2452 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2453 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2454 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2455 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2456 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2457
2356aaeb
PB		 2458 cpl = tss->cs & 3;
2459
38ba30ba 2460 /*
fc058680 2461 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2462 * it is handled in a context of new task
2463 */
5045b468 2464 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2465 if (ret != X86EMUL_CONTINUE)
2466 return ret;
5045b468 2467 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2468 if (ret != X86EMUL_CONTINUE)
2469 return ret;
5045b468 2470 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2471 if (ret != X86EMUL_CONTINUE)
2472 return ret;
5045b468 2473 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
5045b468 2476 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
2479
2480 return X86EMUL_CONTINUE;
2481}
2482
2483static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2484 u16 tss_selector, u16 old_tss_sel,
2485 ulong old_tss_base, struct desc_struct *new_desc)
2486{
0225fb50 2487 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2488 struct tss_segment_16 tss_seg;
2489 int ret;
bcc55cba 2490 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2491
0f65dd70 2492 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2493 &ctxt->exception);
db297e3d 2494 if (ret != X86EMUL_CONTINUE)
38ba30ba 2495 /* FIXME: need to provide precise fault address */
38ba30ba 2496 return ret;
38ba30ba 2497
7b105ca2 2498 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2499
0f65dd70 2500 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2501 &ctxt->exception);
db297e3d 2502 if (ret != X86EMUL_CONTINUE)
38ba30ba 2503 /* FIXME: need to provide precise fault address */
38ba30ba 2504 return ret;
38ba30ba 2505
0f65dd70 2506 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2507 &ctxt->exception);
db297e3d 2508 if (ret != X86EMUL_CONTINUE)
38ba30ba 2509 /* FIXME: need to provide precise fault address */
38ba30ba 2510 return ret;
38ba30ba
GN		 2511
2512 if (old_tss_sel != 0xffff) {
2513 tss_seg.prev_task_link = old_tss_sel;
2514
0f65dd70 2515 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2516 &tss_seg.prev_task_link,
2517 sizeof tss_seg.prev_task_link,
0f65dd70 2518 &ctxt->exception);
db297e3d 2519 if (ret != X86EMUL_CONTINUE)
38ba30ba 2520 /* FIXME: need to provide precise fault address */
38ba30ba 2521 return ret;
38ba30ba
GN		 2522 }
2523
7b105ca2 2524 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2525}
2526
2527static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2528 struct tss_segment_32 *tss)
2529{
5c7411e2 2530 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2531 tss->eip = ctxt->_eip;
38ba30ba 2532 tss->eflags = ctxt->eflags;
dd856efa
AK		 2533 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2534 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2535 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2536 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2537 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2538 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2539 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2540 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2541
1aa36616
AK		 2542 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2543 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2544 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2545 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2546 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2547 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2548}
2549
2550static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2551 struct tss_segment_32 *tss)
2552{
38ba30ba 2553 int ret;
2356aaeb 2554 u8 cpl;
38ba30ba 2555
7b105ca2 2556 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2557 return emulate_gp(ctxt, 0);
9dac77fa 2558 ctxt->_eip = tss->eip;
38ba30ba 2559 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2560
2561 /* General purpose registers */
dd856efa
AK		 2562 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2563 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2564 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2565 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2566 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2567 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2568 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2569 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2570
2571 /*
2572 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2573 * descriptors. This is important because CPL checks will
2574 * use CS.RPL.
38ba30ba 2575 */
1aa36616
AK		 2576 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2577 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2578 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2579 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2580 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2581 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2582 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2583
4cee4798
KW		 2584 /*
2585 * If we're switching between Protected Mode and VM86, we need to make
2586 * sure to update the mode before loading the segment descriptors so
2587 * that the selectors are interpreted correctly.
4cee4798 2588 */
2356aaeb 2589 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2590 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2591 cpl = 3;
2592 } else {
4cee4798 2593 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2594 cpl = tss->cs & 3;
2595 }
4cee4798 2596
38ba30ba
GN		 2597 /*
2598 * Now load segment descriptors. If fault happenes at this stage
2599 * it is handled in a context of new task
2600 */
5045b468 2601 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2602 if (ret != X86EMUL_CONTINUE)
2603 return ret;
5045b468 2604 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2605 if (ret != X86EMUL_CONTINUE)
2606 return ret;
5045b468 2607 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2608 if (ret != X86EMUL_CONTINUE)
2609 return ret;
5045b468 2610 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2611 if (ret != X86EMUL_CONTINUE)
2612 return ret;
5045b468 2613 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
5045b468 2616 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
5045b468 2619 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2620 if (ret != X86EMUL_CONTINUE)
2621 return ret;
2622
2623 return X86EMUL_CONTINUE;
2624}
2625
2626static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2627 u16 tss_selector, u16 old_tss_sel,
2628 ulong old_tss_base, struct desc_struct *new_desc)
2629{
0225fb50 2630 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2631 struct tss_segment_32 tss_seg;
2632 int ret;
bcc55cba 2633 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2634 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2635 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2636
0f65dd70 2637 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2638 &ctxt->exception);
db297e3d 2639 if (ret != X86EMUL_CONTINUE)
38ba30ba 2640 /* FIXME: need to provide precise fault address */
38ba30ba 2641 return ret;
38ba30ba 2642
7b105ca2 2643 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2644
5c7411e2
NA		 2645 /* Only GP registers and segment selectors are saved */
2646 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2647 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2648 if (ret != X86EMUL_CONTINUE)
38ba30ba 2649 /* FIXME: need to provide precise fault address */
38ba30ba 2650 return ret;
38ba30ba 2651
0f65dd70 2652 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2653 &ctxt->exception);
db297e3d 2654 if (ret != X86EMUL_CONTINUE)
38ba30ba 2655 /* FIXME: need to provide precise fault address */
38ba30ba 2656 return ret;
38ba30ba
GN		 2657
2658 if (old_tss_sel != 0xffff) {
2659 tss_seg.prev_task_link = old_tss_sel;
2660
0f65dd70 2661 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2662 &tss_seg.prev_task_link,
2663 sizeof tss_seg.prev_task_link,
0f65dd70 2664 &ctxt->exception);
db297e3d 2665 if (ret != X86EMUL_CONTINUE)
38ba30ba 2666 /* FIXME: need to provide precise fault address */
38ba30ba 2667 return ret;
38ba30ba
GN		 2668 }
2669
7b105ca2 2670 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2671}
2672
2673static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2674 u16 tss_selector, int idt_index, int reason,
e269fb21 2675 bool has_error_code, u32 error_code)
38ba30ba 2676{
0225fb50 2677 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2678 struct desc_struct curr_tss_desc, next_tss_desc;
2679 int ret;
1aa36616 2680 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2681 ulong old_tss_base =
4bff1e86 2682 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2683 u32 desc_limit;
e919464b 2684 ulong desc_addr;
38ba30ba
GN		 2685
2686 /* FIXME: old_tss_base == ~0 ? */
2687
e919464b 2688 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2689 if (ret != X86EMUL_CONTINUE)
2690 return ret;
e919464b 2691 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2692 if (ret != X86EMUL_CONTINUE)
2693 return ret;
2694
2695 /* FIXME: check that next_tss_desc is tss */
2696
7f3d35fd
KW		 2697 /*
2698 * Check privileges. The three cases are task switch caused by...
2699 *
2700 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2701 * 2. Exception/IRQ/iret: No check is performed
fc058680 2702 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2703 */
2704 if (reason == TASK_SWITCH_GATE) {
2705 if (idt_index != -1) {
2706 /* Software interrupts */
2707 struct desc_struct task_gate_desc;
2708 int dpl;
2709
2710 ret = read_interrupt_descriptor(ctxt, idt_index,
2711 &task_gate_desc);
2712 if (ret != X86EMUL_CONTINUE)
2713 return ret;
2714
2715 dpl = task_gate_desc.dpl;
2716 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2717 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2718 }
2719 } else if (reason != TASK_SWITCH_IRET) {
2720 int dpl = next_tss_desc.dpl;
2721 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2722 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2723 }
2724
7f3d35fd 2725
ceffb459
GN		 2726 desc_limit = desc_limit_scaled(&next_tss_desc);
2727 if (!next_tss_desc.p ||
2728 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2729 desc_limit < 0x2b)) {
54b8486f 2730 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2731 return X86EMUL_PROPAGATE_FAULT;
2732 }
2733
2734 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2735 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2736 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2737 }
2738
2739 if (reason == TASK_SWITCH_IRET)
2740 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2741
2742 /* set back link to prev task only if NT bit is set in eflags
fc058680 2743 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2744 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2745 old_tss_sel = 0xffff;
2746
2747 if (next_tss_desc.type & 8)
7b105ca2 2748 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2749 old_tss_base, &next_tss_desc);
2750 else
7b105ca2 2751 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2752 old_tss_base, &next_tss_desc);
0760d448
JK		 2753 if (ret != X86EMUL_CONTINUE)
2754 return ret;
38ba30ba
GN		 2755
2756 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2757 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2758
2759 if (reason != TASK_SWITCH_IRET) {
2760 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2761 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2762 }
2763
717746e3 2764 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2765 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2766
e269fb21 2767 if (has_error_code) {
9dac77fa
AK		 2768 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2769 ctxt->lock_prefix = 0;
2770 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2771 ret = em_push(ctxt);
e269fb21
JK		 2772 }
2773
38ba30ba
GN		 2774 return ret;
2775}
2776
2777int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2778 u16 tss_selector, int idt_index, int reason,
e269fb21 2779 bool has_error_code, u32 error_code)
38ba30ba 2780{
38ba30ba
GN		 2781 int rc;
2782
dd856efa 2783 invalidate_registers(ctxt);
9dac77fa
AK		 2784 ctxt->_eip = ctxt->eip;
2785 ctxt->dst.type = OP_NONE;
38ba30ba 2786
7f3d35fd 2787 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2788 has_error_code, error_code);
38ba30ba 2789
dd856efa 2790 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2791 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2792 writeback_registers(ctxt);
2793 }
38ba30ba 2794
a0c0ab2f 2795 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2796}
2797
f3bd64c6
GN		 2798static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2799 struct operand *op)
a682e354 2800{
b3356bf0 2801 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2802
dd856efa
AK		 2803 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2804 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2805}
2806
7af04fc0
AK		 2807static int em_das(struct x86_emulate_ctxt *ctxt)
2808{
7af04fc0
AK		 2809 u8 al, old_al;
2810 bool af, cf, old_cf;
2811
2812 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2813 al = ctxt->dst.val;
7af04fc0
AK		 2814
2815 old_al = al;
2816 old_cf = cf;
2817 cf = false;
2818 af = ctxt->eflags & X86_EFLAGS_AF;
2819 if ((al & 0x0f) > 9 || af) {
2820 al -= 6;
2821 cf = old_cf | (al >= 250);
2822 af = true;
2823 } else {
2824 af = false;
2825 }
2826 if (old_al > 0x99 || old_cf) {
2827 al -= 0x60;
2828 cf = true;
2829 }
2830
9dac77fa 2831 ctxt->dst.val = al;
7af04fc0 2832 /* Set PF, ZF, SF */
9dac77fa
AK		 2833 ctxt->src.type = OP_IMM;
2834 ctxt->src.val = 0;
2835 ctxt->src.bytes = 1;
158de57f 2836 fastop(ctxt, em_or);
7af04fc0
AK		 2837 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2838 if (cf)
2839 ctxt->eflags |= X86_EFLAGS_CF;
2840 if (af)
2841 ctxt->eflags |= X86_EFLAGS_AF;
2842 return X86EMUL_CONTINUE;
2843}
2844
a035d5c6
PB		 2845static int em_aam(struct x86_emulate_ctxt *ctxt)
2846{
2847 u8 al, ah;
2848
2849 if (ctxt->src.val == 0)
2850 return emulate_de(ctxt);
2851
2852 al = ctxt->dst.val & 0xff;
2853 ah = al / ctxt->src.val;
2854 al %= ctxt->src.val;
2855
2856 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2857
2858 /* Set PF, ZF, SF */
2859 ctxt->src.type = OP_IMM;
2860 ctxt->src.val = 0;
2861 ctxt->src.bytes = 1;
2862 fastop(ctxt, em_or);
2863
2864 return X86EMUL_CONTINUE;
2865}
2866
7f662273
GN		 2867static int em_aad(struct x86_emulate_ctxt *ctxt)
2868{
2869 u8 al = ctxt->dst.val & 0xff;
2870 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2871
2872 al = (al + (ah * ctxt->src.val)) & 0xff;
2873
2874 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2875
f583c29b
GN		 2876 /* Set PF, ZF, SF */
2877 ctxt->src.type = OP_IMM;
2878 ctxt->src.val = 0;
2879 ctxt->src.bytes = 1;
2880 fastop(ctxt, em_or);
7f662273
GN		 2881
2882 return X86EMUL_CONTINUE;
2883}
2884
d4ddafcd
TY		 2885static int em_call(struct x86_emulate_ctxt *ctxt)
2886{
2887 long rel = ctxt->src.val;
2888
2889 ctxt->src.val = (unsigned long)ctxt->_eip;
2890 jmp_rel(ctxt, rel);
2891 return em_push(ctxt);
2892}
2893
0ef753b8
AK		 2894static int em_call_far(struct x86_emulate_ctxt *ctxt)
2895{
0ef753b8
AK		 2896 u16 sel, old_cs;
2897 ulong old_eip;
2898 int rc;
2899
1aa36616 2900 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2901 old_eip = ctxt->_eip;
0ef753b8 2902
9dac77fa 2903 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2904 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2905 return X86EMUL_CONTINUE;
2906
9dac77fa
AK		 2907 ctxt->_eip = 0;
2908 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2909
9dac77fa 2910 ctxt->src.val = old_cs;
4487b3b4 2911 rc = em_push(ctxt);
0ef753b8
AK		 2912 if (rc != X86EMUL_CONTINUE)
2913 return rc;
2914
9dac77fa 2915 ctxt->src.val = old_eip;
4487b3b4 2916 return em_push(ctxt);
0ef753b8
AK		 2917}
2918
40ece7c7
AK		 2919static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2920{
40ece7c7
AK		 2921 int rc;
2922
9dac77fa
AK		 2923 ctxt->dst.type = OP_REG;
2924 ctxt->dst.addr.reg = &ctxt->_eip;
2925 ctxt->dst.bytes = ctxt->op_bytes;
2926 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2927 if (rc != X86EMUL_CONTINUE)
2928 return rc;
5ad105e5 2929 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2930 return X86EMUL_CONTINUE;
2931}
2932
e4f973ae
TY		 2933static int em_xchg(struct x86_emulate_ctxt *ctxt)
2934{
e4f973ae 2935 /* Write back the register source. */
9dac77fa
AK		 2936 ctxt->src.val = ctxt->dst.val;
2937 write_register_operand(&ctxt->src);
e4f973ae
TY		 2938
2939 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2940 ctxt->dst.val = ctxt->src.orig_val;
2941 ctxt->lock_prefix = 1;
e4f973ae
TY		 2942 return X86EMUL_CONTINUE;
2943}
2944
5c82aa29
AK		 2945static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2946{
9dac77fa 2947 ctxt->dst.val = ctxt->src2.val;
4d758349 2948 return fastop(ctxt, em_imul);
5c82aa29
AK		 2949}
2950
61429142
AK		 2951static int em_cwd(struct x86_emulate_ctxt *ctxt)
2952{
9dac77fa
AK		 2953 ctxt->dst.type = OP_REG;
2954 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2955 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2956 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2957
2958 return X86EMUL_CONTINUE;
2959}
2960
48bb5d3c
AK		 2961static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2962{
48bb5d3c
AK		 2963 u64 tsc = 0;
2964
717746e3 2965 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2966 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2967 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2968 return X86EMUL_CONTINUE;
2969}
2970
222d21aa
AK		 2971static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2972{
2973 u64 pmc;
2974
dd856efa 2975 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2976 return emulate_gp(ctxt, 0);
dd856efa
AK		 2977 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2978 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2979 return X86EMUL_CONTINUE;
2980}
2981
b9eac5f4
AK		 2982static int em_mov(struct x86_emulate_ctxt *ctxt)
2983{
54cfdb3e 2984 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2985 return X86EMUL_CONTINUE;
2986}
2987
84cffe49
BP		 2988#define FFL(x) bit(X86_FEATURE_##x)
2989
2990static int em_movbe(struct x86_emulate_ctxt *ctxt)
2991{
2992 u32 ebx, ecx, edx, eax = 1;
2993 u16 tmp;
2994
2995 /*
2996 * Check MOVBE is set in the guest-visible CPUID leaf.
2997 */
2998 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2999 if (!(ecx & FFL(MOVBE)))
3000 return emulate_ud(ctxt);
3001
3002 switch (ctxt->op_bytes) {
3003 case 2:
3004 /*
3005 * From MOVBE definition: "...When the operand size is 16 bits,
3006 * the upper word of the destination register remains unchanged
3007 * ..."
3008 *
3009 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3010 * rules so we have to do the operation almost per hand.
3011 */
3012 tmp = (u16)ctxt->src.val;
3013 ctxt->dst.val &= ~0xffffUL;
3014 ctxt->dst.val |= (unsigned long)swab16(tmp);
3015 break;
3016 case 4:
3017 ctxt->dst.val = swab32((u32)ctxt->src.val);
3018 break;
3019 case 8:
3020 ctxt->dst.val = swab64(ctxt->src.val);
3021 break;
3022 default:
3023 return X86EMUL_PROPAGATE_FAULT;
3024 }
3025 return X86EMUL_CONTINUE;
3026}
3027
bc00f8d2
TY		 3028static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3029{
3030 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3031 return emulate_gp(ctxt, 0);
3032
3033 /* Disable writeback. */
3034 ctxt->dst.type = OP_NONE;
3035 return X86EMUL_CONTINUE;
3036}
3037
3038static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3039{
3040 unsigned long val;
3041
3042 if (ctxt->mode == X86EMUL_MODE_PROT64)
3043 val = ctxt->src.val & ~0ULL;
3044 else
3045 val = ctxt->src.val & ~0U;
3046
3047 /* #UD condition is already handled. */
3048 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3049 return emulate_gp(ctxt, 0);
3050
3051 /* Disable writeback. */
3052 ctxt->dst.type = OP_NONE;
3053 return X86EMUL_CONTINUE;
3054}
3055
e1e210b0
TY		 3056static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3057{
3058 u64 msr_data;
3059
dd856efa
AK		 3060 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3061 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3062 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3063 return emulate_gp(ctxt, 0);
3064
3065 return X86EMUL_CONTINUE;
3066}
3067
3068static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3069{
3070 u64 msr_data;
3071
dd856efa 3072 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3073 return emulate_gp(ctxt, 0);
3074
dd856efa
AK		 3075 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3076 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3077 return X86EMUL_CONTINUE;
3078}
3079
1bd5f469
TY		 3080static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3081{
9dac77fa 3082 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3083 return emulate_ud(ctxt);
3084
9dac77fa 3085 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3086 return X86EMUL_CONTINUE;
3087}
3088
3089static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3090{
9dac77fa 3091 u16 sel = ctxt->src.val;
1bd5f469 3092
9dac77fa 3093 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3094 return emulate_ud(ctxt);
3095
9dac77fa 3096 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3097 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3098
3099 /* Disable writeback. */
9dac77fa
AK		 3100 ctxt->dst.type = OP_NONE;
3101 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3102}
3103
a14e579f
AK		 3104static int em_lldt(struct x86_emulate_ctxt *ctxt)
3105{
3106 u16 sel = ctxt->src.val;
3107
3108 /* Disable writeback. */
3109 ctxt->dst.type = OP_NONE;
3110 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3111}
3112
80890006
AK		 3113static int em_ltr(struct x86_emulate_ctxt *ctxt)
3114{
3115 u16 sel = ctxt->src.val;
3116
3117 /* Disable writeback. */
3118 ctxt->dst.type = OP_NONE;
3119 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3120}
3121
38503911
AK		 3122static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3123{
9fa088f4
AK		 3124 int rc;
3125 ulong linear;
3126
9dac77fa 3127 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3128 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3129 ctxt->ops->invlpg(ctxt, linear);
38503911 3130 /* Disable writeback. */
9dac77fa 3131 ctxt->dst.type = OP_NONE;
38503911
AK		 3132 return X86EMUL_CONTINUE;
3133}
3134
2d04a05b
AK		 3135static int em_clts(struct x86_emulate_ctxt *ctxt)
3136{
3137 ulong cr0;
3138
3139 cr0 = ctxt->ops->get_cr(ctxt, 0);
3140 cr0 &= ~X86_CR0_TS;
3141 ctxt->ops->set_cr(ctxt, 0, cr0);
3142 return X86EMUL_CONTINUE;
3143}
3144
26d05cc7
AK		 3145static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3146{
26d05cc7
AK		 3147 int rc;
3148
9dac77fa 3149 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3150 return X86EMUL_UNHANDLEABLE;
3151
3152 rc = ctxt->ops->fix_hypercall(ctxt);
3153 if (rc != X86EMUL_CONTINUE)
3154 return rc;
3155
3156 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3157 ctxt->_eip = ctxt->eip;
26d05cc7 3158 /* Disable writeback. */
9dac77fa 3159 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3160 return X86EMUL_CONTINUE;
3161}
3162
96051572
AK		 3163static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3164 void (*get)(struct x86_emulate_ctxt *ctxt,
3165 struct desc_ptr *ptr))
3166{
3167 struct desc_ptr desc_ptr;
3168
3169 if (ctxt->mode == X86EMUL_MODE_PROT64)
3170 ctxt->op_bytes = 8;
3171 get(ctxt, &desc_ptr);
3172 if (ctxt->op_bytes == 2) {
3173 ctxt->op_bytes = 4;
3174 desc_ptr.address &= 0x00ffffff;
3175 }
3176 /* Disable writeback. */
3177 ctxt->dst.type = OP_NONE;
3178 return segmented_write(ctxt, ctxt->dst.addr.mem,
3179 &desc_ptr, 2 + ctxt->op_bytes);
3180}
3181
3182static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3183{
3184 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3185}
3186
3187static int em_sidt(struct x86_emulate_ctxt *ctxt)
3188{
3189 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3190}
3191
26d05cc7
AK		 3192static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3193{
26d05cc7
AK		 3194 struct desc_ptr desc_ptr;
3195 int rc;
3196
510425ff
AK		 3197 if (ctxt->mode == X86EMUL_MODE_PROT64)
3198 ctxt->op_bytes = 8;
9dac77fa 3199 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3200 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3201 ctxt->op_bytes);
26d05cc7
AK		 3202 if (rc != X86EMUL_CONTINUE)
3203 return rc;
3204 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3205 /* Disable writeback. */
9dac77fa 3206 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3207 return X86EMUL_CONTINUE;
3208}
3209
5ef39c71 3210static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3211{
26d05cc7
AK		 3212 int rc;
3213
5ef39c71
AK		 3214 rc = ctxt->ops->fix_hypercall(ctxt);
3215
26d05cc7 3216 /* Disable writeback. */
9dac77fa 3217 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3218 return rc;
3219}
3220
3221static int em_lidt(struct x86_emulate_ctxt *ctxt)
3222{
26d05cc7
AK		 3223 struct desc_ptr desc_ptr;
3224 int rc;
3225
510425ff
AK		 3226 if (ctxt->mode == X86EMUL_MODE_PROT64)
3227 ctxt->op_bytes = 8;
9dac77fa 3228 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3229 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3230 ctxt->op_bytes);
26d05cc7
AK		 3231 if (rc != X86EMUL_CONTINUE)
3232 return rc;
3233 ctxt->ops->set_idt(ctxt, &desc_ptr);
3234 /* Disable writeback. */
9dac77fa 3235 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3236 return X86EMUL_CONTINUE;
3237}
3238
3239static int em_smsw(struct x86_emulate_ctxt *ctxt)
3240{
32e94d06
NA		 3241 if (ctxt->dst.type == OP_MEM)
3242 ctxt->dst.bytes = 2;
9dac77fa 3243 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3244 return X86EMUL_CONTINUE;
3245}
3246
3247static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3248{
26d05cc7 3249 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3250 | (ctxt->src.val & 0x0f));
3251 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3252 return X86EMUL_CONTINUE;
3253}
3254
d06e03ad
TY		 3255static int em_loop(struct x86_emulate_ctxt *ctxt)
3256{
dd856efa
AK		 3257 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3258 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3259 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3260 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3261
3262 return X86EMUL_CONTINUE;
3263}
3264
3265static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3266{
dd856efa 3267 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3268 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3269
3270 return X86EMUL_CONTINUE;
3271}
3272
d7841a4b
TY		 3273static int em_in(struct x86_emulate_ctxt *ctxt)
3274{
3275 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3276 &ctxt->dst.val))
3277 return X86EMUL_IO_NEEDED;
3278
3279 return X86EMUL_CONTINUE;
3280}
3281
3282static int em_out(struct x86_emulate_ctxt *ctxt)
3283{
3284 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3285 &ctxt->src.val, 1);
3286 /* Disable writeback. */
3287 ctxt->dst.type = OP_NONE;
3288 return X86EMUL_CONTINUE;
3289}
3290
f411e6cd
TY		 3291static int em_cli(struct x86_emulate_ctxt *ctxt)
3292{
3293 if (emulator_bad_iopl(ctxt))
3294 return emulate_gp(ctxt, 0);
3295
3296 ctxt->eflags &= ~X86_EFLAGS_IF;
3297 return X86EMUL_CONTINUE;
3298}
3299
3300static int em_sti(struct x86_emulate_ctxt *ctxt)
3301{
3302 if (emulator_bad_iopl(ctxt))
3303 return emulate_gp(ctxt, 0);
3304
3305 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3306 ctxt->eflags |= X86_EFLAGS_IF;
3307 return X86EMUL_CONTINUE;
3308}
3309
6d6eede4
AK		 3310static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3311{
3312 u32 eax, ebx, ecx, edx;
3313
dd856efa
AK		 3314 eax = reg_read(ctxt, VCPU_REGS_RAX);
3315 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3316 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3317 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3318 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3319 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3320 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3321 return X86EMUL_CONTINUE;
3322}
3323
98f73630
PB		 3324static int em_sahf(struct x86_emulate_ctxt *ctxt)
3325{
3326 u32 flags;
3327
3328 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3329 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3330
3331 ctxt->eflags &= ~0xffUL;
3332 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3333 return X86EMUL_CONTINUE;
3334}
3335
2dd7caa0
AK		 3336static int em_lahf(struct x86_emulate_ctxt *ctxt)
3337{
dd856efa
AK		 3338 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3339 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3340 return X86EMUL_CONTINUE;
3341}
3342
9299836e
AK		 3343static int em_bswap(struct x86_emulate_ctxt *ctxt)
3344{
3345 switch (ctxt->op_bytes) {
3346#ifdef CONFIG_X86_64
3347 case 8:
3348 asm("bswap %0" : "+r"(ctxt->dst.val));
3349 break;
3350#endif
3351 default:
3352 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3353 break;
3354 }
3355 return X86EMUL_CONTINUE;
3356}
3357
cfec82cb
JR		 3358static bool valid_cr(int nr)
3359{
3360 switch (nr) {
3361 case 0:
3362 case 2 ... 4:
3363 case 8:
3364 return true;
3365 default:
3366 return false;
3367 }
3368}
3369
3370static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3371{
9dac77fa 3372 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3373 return emulate_ud(ctxt);
3374
3375 return X86EMUL_CONTINUE;
3376}
3377
3378static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3379{
9dac77fa
AK		 3380 u64 new_val = ctxt->src.val64;
3381 int cr = ctxt->modrm_reg;
c2ad2bb3 3382 u64 efer = 0;
cfec82cb
JR		 3383
3384 static u64 cr_reserved_bits[] = {
3385 0xffffffff00000000ULL,
3386 0, 0, 0, /* CR3 checked later */
3387 CR4_RESERVED_BITS,
3388 0, 0, 0,
3389 CR8_RESERVED_BITS,
3390 };
3391
3392 if (!valid_cr(cr))
3393 return emulate_ud(ctxt);
3394
3395 if (new_val & cr_reserved_bits[cr])
3396 return emulate_gp(ctxt, 0);
3397
3398 switch (cr) {
3399 case 0: {
c2ad2bb3 3400 u64 cr4;
cfec82cb
JR		 3401 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3402 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3403 return emulate_gp(ctxt, 0);
3404
717746e3
AK		 3405 cr4 = ctxt->ops->get_cr(ctxt, 4);
3406 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3407
3408 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3409 !(cr4 & X86_CR4_PAE))
3410 return emulate_gp(ctxt, 0);
3411
3412 break;
3413 }
3414 case 3: {
3415 u64 rsvd = 0;
3416
c2ad2bb3
AK		 3417 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3418 if (efer & EFER_LMA)
cfec82cb 3419 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3420
3421 if (new_val & rsvd)
3422 return emulate_gp(ctxt, 0);
3423
3424 break;
3425 }
3426 case 4: {
717746e3 3427 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3428
3429 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3430 return emulate_gp(ctxt, 0);
3431
3432 break;
3433 }
3434 }
3435
3436 return X86EMUL_CONTINUE;
3437}
3438
3b88e41a
JR		 3439static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3440{
3441 unsigned long dr7;
3442
717746e3 3443 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3444
3445 /* Check if DR7.Global_Enable is set */
3446 return dr7 & (1 << 13);
3447}
3448
3449static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3450{
9dac77fa 3451 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3452 u64 cr4;
3453
3454 if (dr > 7)
3455 return emulate_ud(ctxt);
3456
717746e3 3457 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3458 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3459 return emulate_ud(ctxt);
3460
3461 if (check_dr7_gd(ctxt))
3462 return emulate_db(ctxt);
3463
3464 return X86EMUL_CONTINUE;
3465}
3466
3467static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3468{
9dac77fa
AK		 3469 u64 new_val = ctxt->src.val64;
3470 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3471
3472 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3473 return emulate_gp(ctxt, 0);
3474
3475 return check_dr_read(ctxt);
3476}
3477
01de8b09
JR		 3478static int check_svme(struct x86_emulate_ctxt *ctxt)
3479{
3480 u64 efer;
3481
717746e3 3482 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3483
3484 if (!(efer & EFER_SVME))
3485 return emulate_ud(ctxt);
3486
3487 return X86EMUL_CONTINUE;
3488}
3489
3490static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3491{
dd856efa 3492 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3493
3494 /* Valid physical address? */
d4224449 3495 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3496 return emulate_gp(ctxt, 0);
3497
3498 return check_svme(ctxt);
3499}
3500
d7eb8203
JR		 3501static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3502{
717746e3 3503 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3504
717746e3 3505 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3506 return emulate_ud(ctxt);
3507
3508 return X86EMUL_CONTINUE;
3509}
3510
8061252e
JR		 3511static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3512{
717746e3 3513 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3514 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3515
717746e3 3516 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3517 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3518 return emulate_gp(ctxt, 0);
3519
3520 return X86EMUL_CONTINUE;
3521}
3522
f6511935
JR		 3523static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3524{
9dac77fa
AK		 3525 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3526 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3527 return emulate_gp(ctxt, 0);
3528
3529 return X86EMUL_CONTINUE;
3530}
3531
3532static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3533{
9dac77fa
AK		 3534 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3535 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3536 return emulate_gp(ctxt, 0);
3537
3538 return X86EMUL_CONTINUE;
3539}
3540
73fba5f4 3541#define D(_y) { .flags = (_y) }
d40a6898
PB		 3542#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3543#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3544 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3545#define N D(NotImpl)
01de8b09 3546#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3547#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3548#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3549#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3550#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3551#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3552#define II(_f, _e, _i) \
d40a6898 3553 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3554#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3555 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3556 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3557#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3558
8d8f4e9f 3559#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3560#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3561#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3562#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3563#define I2bvIP(_f, _e, _i, _p) \
3564 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3565
fb864fbc
AK		 3566#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3567 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3568 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3569
fd0a0d82 3570static const struct opcode group7_rm1[] = {
1c2545be
TY		 3571 DI(SrcNone | Priv, monitor),
3572 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3573 N, N, N, N, N, N,
3574};
3575
fd0a0d82 3576static const struct opcode group7_rm3[] = {
1c2545be 3577 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3578 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3579 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3580 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3581 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3582 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3583 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3584 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3585};
6230f7fc 3586
fd0a0d82 3587static const struct opcode group7_rm7[] = {
d7eb8203 3588 N,
1c2545be 3589 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3590 N, N, N, N, N, N,
3591};
d67fc27a 3592
fd0a0d82 3593static const struct opcode group1[] = {
fb864fbc
AK		 3594 F(Lock, em_add),
3595 F(Lock | PageTable, em_or),
3596 F(Lock, em_adc),
3597 F(Lock, em_sbb),
3598 F(Lock | PageTable, em_and),
3599 F(Lock, em_sub),
3600 F(Lock, em_xor),
3601 F(NoWrite, em_cmp),
73fba5f4
AK		 3602};
3603
fd0a0d82 3604static const struct opcode group1A[] = {
1c2545be 3605 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3606};
3607
007a3b54
AK		 3608static const struct opcode group2[] = {
3609 F(DstMem | ModRM, em_rol),
3610 F(DstMem | ModRM, em_ror),
3611 F(DstMem | ModRM, em_rcl),
3612 F(DstMem | ModRM, em_rcr),
3613 F(DstMem | ModRM, em_shl),
3614 F(DstMem | ModRM, em_shr),
3615 F(DstMem | ModRM, em_shl),
3616 F(DstMem | ModRM, em_sar),
3617};
3618
fd0a0d82 3619static const struct opcode group3[] = {
fb864fbc
AK		 3620 F(DstMem | SrcImm | NoWrite, em_test),
3621 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3622 F(DstMem | SrcNone | Lock, em_not),
3623 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3624 F(DstXacc | Src2Mem, em_mul_ex),
3625 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3626 F(DstXacc | Src2Mem, em_div_ex),
3627 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3628};
3629
fd0a0d82 3630static const struct opcode group4[] = {
95413dc4
AK		 3631 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3632 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3633 N, N, N, N, N, N,
3634};
3635
fd0a0d82 3636static const struct opcode group5[] = {
95413dc4
AK		 3637 F(DstMem | SrcNone | Lock, em_inc),
3638 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3639 I(SrcMem | Stack, em_grp45),
3640 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3641 I(SrcMem | Stack, em_grp45),
3642 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3643 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3644};
3645
fd0a0d82 3646static const struct opcode group6[] = {
1c2545be
TY		 3647 DI(Prot, sldt),
3648 DI(Prot, str),
a14e579f 3649 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3650 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3651 N, N, N, N,
3652};
3653
fd0a0d82 3654static const struct group_dual group7 = { {
606b1c3e
NA		 3655 II(Mov | DstMem, em_sgdt, sgdt),
3656 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3657 II(SrcMem | Priv, em_lgdt, lgdt),
3658 II(SrcMem | Priv, em_lidt, lidt),
3659 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3660 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3661 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3662}, {
b51e974f 3663 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3664 EXT(0, group7_rm1),
01de8b09 3665 N, EXT(0, group7_rm3),
1c2545be
TY		 3666 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3667 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3668 EXT(0, group7_rm7),
73fba5f4
AK		 3669} };
3670
fd0a0d82 3671static const struct opcode group8[] = {
73fba5f4 3672 N, N, N, N,
11c363ba
AK		 3673 F(DstMem | SrcImmByte | NoWrite, em_bt),
3674 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3675 F(DstMem | SrcImmByte | Lock, em_btr),
3676 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3677};
3678
fd0a0d82 3679static const struct group_dual group9 = { {
1c2545be 3680 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3681}, {
3682 N, N, N, N, N, N, N, N,
3683} };
3684
fd0a0d82 3685static const struct opcode group11[] = {
1c2545be 3686 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3687 X7(D(Undefined)),
a4d4a7c1
AK		 3688};
3689
fd0a0d82 3690static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3691 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3692};
3693
fd0a0d82 3694static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3695 I(0, em_mov), N, N, N,
3696};
3697
27ce8258 3698static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3699 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3700};
3701
045a282c
GN		 3702static const struct escape escape_d9 = { {
3703 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3704}, {
3705 /* 0xC0 - 0xC7 */
3706 N, N, N, N, N, N, N, N,
3707 /* 0xC8 - 0xCF */
3708 N, N, N, N, N, N, N, N,
3709 /* 0xD0 - 0xC7 */
3710 N, N, N, N, N, N, N, N,
3711 /* 0xD8 - 0xDF */
3712 N, N, N, N, N, N, N, N,
3713 /* 0xE0 - 0xE7 */
3714 N, N, N, N, N, N, N, N,
3715 /* 0xE8 - 0xEF */
3716 N, N, N, N, N, N, N, N,
3717 /* 0xF0 - 0xF7 */
3718 N, N, N, N, N, N, N, N,
3719 /* 0xF8 - 0xFF */
3720 N, N, N, N, N, N, N, N,
3721} };
3722
3723static const struct escape escape_db = { {
3724 N, N, N, N, N, N, N, N,
3725}, {
3726 /* 0xC0 - 0xC7 */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xC8 - 0xCF */
3729 N, N, N, N, N, N, N, N,
3730 /* 0xD0 - 0xC7 */
3731 N, N, N, N, N, N, N, N,
3732 /* 0xD8 - 0xDF */
3733 N, N, N, N, N, N, N, N,
3734 /* 0xE0 - 0xE7 */
3735 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3736 /* 0xE8 - 0xEF */
3737 N, N, N, N, N, N, N, N,
3738 /* 0xF0 - 0xF7 */
3739 N, N, N, N, N, N, N, N,
3740 /* 0xF8 - 0xFF */
3741 N, N, N, N, N, N, N, N,
3742} };
3743
3744static const struct escape escape_dd = { {
3745 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3746}, {
3747 /* 0xC0 - 0xC7 */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xC8 - 0xCF */
3750 N, N, N, N, N, N, N, N,
3751 /* 0xD0 - 0xC7 */
3752 N, N, N, N, N, N, N, N,
3753 /* 0xD8 - 0xDF */
3754 N, N, N, N, N, N, N, N,
3755 /* 0xE0 - 0xE7 */
3756 N, N, N, N, N, N, N, N,
3757 /* 0xE8 - 0xEF */
3758 N, N, N, N, N, N, N, N,
3759 /* 0xF0 - 0xF7 */
3760 N, N, N, N, N, N, N, N,
3761 /* 0xF8 - 0xFF */
3762 N, N, N, N, N, N, N, N,
3763} };
3764
fd0a0d82 3765static const struct opcode opcode_table[256] = {
73fba5f4 3766 /* 0x00 - 0x07 */
fb864fbc 3767 F6ALU(Lock, em_add),
1cd196ea
AK		 3768 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3769 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3770 /* 0x08 - 0x0F */
fb864fbc 3771 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3772 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3773 N,
73fba5f4 3774 /* 0x10 - 0x17 */
fb864fbc 3775 F6ALU(Lock, em_adc),
1cd196ea
AK		 3776 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3777 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3778 /* 0x18 - 0x1F */
fb864fbc 3779 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3780 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3781 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3782 /* 0x20 - 0x27 */
fb864fbc 3783 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3784 /* 0x28 - 0x2F */
fb864fbc 3785 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3786 /* 0x30 - 0x37 */
fb864fbc 3787 F6ALU(Lock, em_xor), N, N,
73fba5f4 3788 /* 0x38 - 0x3F */
fb864fbc 3789 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3790 /* 0x40 - 0x4F */
95413dc4 3791 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3792 /* 0x50 - 0x57 */
63540382 3793 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3794 /* 0x58 - 0x5F */
c54fe504 3795 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3796 /* 0x60 - 0x67 */
b96a7fad
TY		 3797 I(ImplicitOps | Stack | No64, em_pusha),
3798 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3799 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3800 N, N, N, N,
3801 /* 0x68 - 0x6F */
d46164db
AK		 3802 I(SrcImm | Mov | Stack, em_push),
3803 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3804 I(SrcImmByte | Mov | Stack, em_push),
3805 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3806 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3807 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3808 /* 0x70 - 0x7F */
3809 X16(D(SrcImmByte)),
3810 /* 0x80 - 0x87 */
1c2545be
TY		 3811 G(ByteOp | DstMem | SrcImm, group1),
3812 G(DstMem | SrcImm, group1),
3813 G(ByteOp | DstMem | SrcImm | No64, group1),
3814 G(DstMem | SrcImmByte, group1),
fb864fbc 3815 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3816 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3817 /* 0x88 - 0x8F */
d5ae7ce8 3818 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3819 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3820 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3821 D(ModRM | SrcMem | NoAccess | DstReg),
3822 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3823 G(0, group1A),
73fba5f4 3824 /* 0x90 - 0x97 */
bf608f88 3825 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3826 /* 0x98 - 0x9F */
61429142 3827 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3828 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3829 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3830 II(ImplicitOps | Stack, em_popf, popf),
3831 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3832 /* 0xA0 - 0xA7 */
b9eac5f4 3833 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3834 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3835 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3836 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3837 /* 0xA8 - 0xAF */
fb864fbc 3838 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3839 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3840 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3841 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3842 /* 0xB0 - 0xB7 */
b9eac5f4 3843 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3844 /* 0xB8 - 0xBF */
5e2c6883 3845 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3846 /* 0xC0 - 0xC7 */
007a3b54 3847 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3848 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3849 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3850 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3851 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3852 G(ByteOp, group11), G(0, group11),
73fba5f4 3853 /* 0xC8 - 0xCF */
612e89f0 3854 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3855 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3856 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3857 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3858 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3859 /* 0xD0 - 0xD7 */
007a3b54
AK		 3860 G(Src2One | ByteOp, group2), G(Src2One, group2),
3861 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3862 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3863 I(DstAcc | SrcImmUByte | No64, em_aad),
3864 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3865 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3866 /* 0xD8 - 0xDF */
045a282c 3867 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3868 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3869 X3(I(SrcImmByte, em_loop)),
3870 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3871 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3872 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3873 /* 0xE8 - 0xEF */
d4ddafcd 3874 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3875 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3876 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3877 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3878 /* 0xF0 - 0xF7 */
bf608f88 3879 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3880 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3881 G(ByteOp, group3), G(0, group3),
73fba5f4 3882 /* 0xF8 - 0xFF */
f411e6cd
TY		 3883 D(ImplicitOps), D(ImplicitOps),
3884 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3885 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3886};
3887
fd0a0d82 3888static const struct opcode twobyte_table[256] = {
73fba5f4 3889 /* 0x00 - 0x0F */
dee6bb70 3890 G(0, group6), GD(0, &group7), N, N,
b51e974f 3891 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3892 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3893 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3894 N, D(ImplicitOps | ModRM), N, N,
3895 /* 0x10 - 0x1F */
103f98ea
PB		 3896 N, N, N, N, N, N, N, N,
3897 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3898 /* 0x20 - 0x2F */
9b88ae99
NA		 3899 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3900 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3901 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3902 check_cr_write),
3903 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3904 check_dr_write),
73fba5f4 3905 N, N, N, N,
27ce8258
IM		 3906 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3907 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3908 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3909 N, N, N, N,
73fba5f4 3910 /* 0x30 - 0x3F */
e1e210b0 3911 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3912 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3913 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3914 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3915 I(ImplicitOps | EmulateOnUD, em_sysenter),
3916 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3917 N, N,
73fba5f4
AK		 3918 N, N, N, N, N, N, N, N,
3919 /* 0x40 - 0x4F */
140bad89 3920 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3921 /* 0x50 - 0x5F */
3922 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3923 /* 0x60 - 0x6F */
aa97bb48
AK		 3924 N, N, N, N,
3925 N, N, N, N,
3926 N, N, N, N,
3927 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3928 /* 0x70 - 0x7F */
aa97bb48
AK		 3929 N, N, N, N,
3930 N, N, N, N,
3931 N, N, N, N,
3932 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3933 /* 0x80 - 0x8F */
3934 X16(D(SrcImm)),
3935 /* 0x90 - 0x9F */
ee45b58e 3936 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3937 /* 0xA0 - 0xA7 */
1cd196ea 3938 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3939 II(ImplicitOps, em_cpuid, cpuid),
3940 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3941 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3942 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3943 /* 0xA8 - 0xAF */
1cd196ea 3944 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3945 DI(ImplicitOps, rsm),
11c363ba 3946 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3947 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3948 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3949 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3950 /* 0xB0 - 0xB7 */
e940b5c2 3951 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3952 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3953 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3954 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3955 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3956 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3957 /* 0xB8 - 0xBF */
3958 N, N,
ce7faab2 3959 G(BitOp, group8),
11c363ba
AK		 3960 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3961 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3962 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3963 /* 0xC0 - 0xC7 */
e47a5f5f 3964 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3965 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3966 N, N, N, GD(0, &group9),
9299836e
AK		 3967 /* 0xC8 - 0xCF */
3968 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3969 /* 0xD0 - 0xDF */
3970 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3971 /* 0xE0 - 0xEF */
3972 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3973 /* 0xF0 - 0xFF */
3974 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3975};
3976
0bc5eedb 3977static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3978 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3979};
3980
3981static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3982 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3983};
3984
3985/*
3986 * Insns below are selected by the prefix which indexed by the third opcode
3987 * byte.
3988 */
3989static const struct opcode opcode_map_0f_38[256] = {
3990 /* 0x00 - 0x7f */
3991 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3992 /* 0x80 - 0xef */
3993 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3994 /* 0xf0 - 0xf1 */
3995 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3996 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3997 /* 0xf2 - 0xff */
3998 N, N, X4(N), X8(N)
0bc5eedb
BP		 3999};
4000
73fba5f4
AK		 4001#undef D
4002#undef N
4003#undef G
4004#undef GD
4005#undef I
aa97bb48 4006#undef GP
01de8b09 4007#undef EXT
73fba5f4 4008
8d8f4e9f 4009#undef D2bv
f6511935 4010#undef D2bvIP
8d8f4e9f 4011#undef I2bv
d7841a4b 4012#undef I2bvIP
d67fc27a 4013#undef I6ALU
8d8f4e9f 4014
9dac77fa 4015static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4016{
4017 unsigned size;
4018
9dac77fa 4019 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4020 if (size == 8)
4021 size = 4;
4022 return size;
4023}
4024
4025static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4026 unsigned size, bool sign_extension)
4027{
39f21ee5
AK		 4028 int rc = X86EMUL_CONTINUE;
4029
4030 op->type = OP_IMM;
4031 op->bytes = size;
9dac77fa 4032 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4033 /* NB. Immediates are sign-extended as necessary. */
4034 switch (op->bytes) {
4035 case 1:
e85a1085 4036 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4037 break;
4038 case 2:
e85a1085 4039 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4040 break;
4041 case 4:
e85a1085 4042 op->val = insn_fetch(s32, ctxt);
39f21ee5 4043 break;
5e2c6883
NA		 4044 case 8:
4045 op->val = insn_fetch(s64, ctxt);
4046 break;
39f21ee5
AK		 4047 }
4048 if (!sign_extension) {
4049 switch (op->bytes) {
4050 case 1:
4051 op->val &= 0xff;
4052 break;
4053 case 2:
4054 op->val &= 0xffff;
4055 break;
4056 case 4:
4057 op->val &= 0xffffffff;
4058 break;
4059 }
4060 }
4061done:
4062 return rc;
4063}
4064
a9945549
AK		 4065static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4066 unsigned d)
4067{
4068 int rc = X86EMUL_CONTINUE;
4069
4070 switch (d) {
4071 case OpReg:
2adb5ad9 4072 decode_register_operand(ctxt, op);
a9945549
AK		 4073 break;
4074 case OpImmUByte:
608aabe3 4075 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4076 break;
4077 case OpMem:
41ddf978 4078 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4079 mem_common:
4080 *op = ctxt->memop;
4081 ctxt->memopp = op;
96888977 4082 if (ctxt->d & BitOp)
a9945549
AK		 4083 fetch_bit_operand(ctxt);
4084 op->orig_val = op->val;
4085 break;
41ddf978 4086 case OpMem64:
aaa05f24 4087 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4088 goto mem_common;
a9945549
AK		 4089 case OpAcc:
4090 op->type = OP_REG;
4091 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4092 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4093 fetch_register_operand(op);
4094 op->orig_val = op->val;
4095 break;
820207c8
AK		 4096 case OpAccLo:
4097 op->type = OP_REG;
4098 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4099 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4100 fetch_register_operand(op);
4101 op->orig_val = op->val;
4102 break;
4103 case OpAccHi:
4104 if (ctxt->d & ByteOp) {
4105 op->type = OP_NONE;
4106 break;
4107 }
4108 op->type = OP_REG;
4109 op->bytes = ctxt->op_bytes;
4110 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4111 fetch_register_operand(op);
4112 op->orig_val = op->val;
4113 break;
a9945549
AK		 4114 case OpDI:
4115 op->type = OP_MEM;
4116 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4117 op->addr.mem.ea =
dd856efa 4118 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4119 op->addr.mem.seg = VCPU_SREG_ES;
4120 op->val = 0;
b3356bf0 4121 op->count = 1;
a9945549
AK		 4122 break;
4123 case OpDX:
4124 op->type = OP_REG;
4125 op->bytes = 2;
dd856efa 4126 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4127 fetch_register_operand(op);
4128 break;
4dd6a57d
AK		 4129 case OpCL:
4130 op->bytes = 1;
dd856efa 4131 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4132 break;
4133 case OpImmByte:
4134 rc = decode_imm(ctxt, op, 1, true);
4135 break;
4136 case OpOne:
4137 op->bytes = 1;
4138 op->val = 1;
4139 break;
4140 case OpImm:
4141 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4142 break;
5e2c6883
NA		 4143 case OpImm64:
4144 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4145 break;
28867cee
AK		 4146 case OpMem8:
4147 ctxt->memop.bytes = 1;
660696d1 4148 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4149 ctxt->memop.addr.reg = decode_register(ctxt,
4150 ctxt->modrm_rm, true);
660696d1
GN		 4151 fetch_register_operand(&ctxt->memop);
4152 }
28867cee 4153 goto mem_common;
0fe59128
AK		 4154 case OpMem16:
4155 ctxt->memop.bytes = 2;
4156 goto mem_common;
4157 case OpMem32:
4158 ctxt->memop.bytes = 4;
4159 goto mem_common;
4160 case OpImmU16:
4161 rc = decode_imm(ctxt, op, 2, false);
4162 break;
4163 case OpImmU:
4164 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4165 break;
4166 case OpSI:
4167 op->type = OP_MEM;
4168 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4169 op->addr.mem.ea =
dd856efa 4170 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4171 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4172 op->val = 0;
b3356bf0 4173 op->count = 1;
0fe59128 4174 break;
7fa57952
PB		 4175 case OpXLat:
4176 op->type = OP_MEM;
4177 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4178 op->addr.mem.ea =
4179 register_address(ctxt,
4180 reg_read(ctxt, VCPU_REGS_RBX) +
4181 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4182 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4183 op->val = 0;
4184 break;
0fe59128
AK		 4185 case OpImmFAddr:
4186 op->type = OP_IMM;
4187 op->addr.mem.ea = ctxt->_eip;
4188 op->bytes = ctxt->op_bytes + 2;
4189 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4190 break;
4191 case OpMemFAddr:
4192 ctxt->memop.bytes = ctxt->op_bytes + 2;
4193 goto mem_common;
c191a7a0
AK		 4194 case OpES:
4195 op->val = VCPU_SREG_ES;
4196 break;
4197 case OpCS:
4198 op->val = VCPU_SREG_CS;
4199 break;
4200 case OpSS:
4201 op->val = VCPU_SREG_SS;
4202 break;
4203 case OpDS:
4204 op->val = VCPU_SREG_DS;
4205 break;
4206 case OpFS:
4207 op->val = VCPU_SREG_FS;
4208 break;
4209 case OpGS:
4210 op->val = VCPU_SREG_GS;
4211 break;
a9945549
AK		 4212 case OpImplicit:
4213 /* Special instructions do their own operand decoding. */
4214 default:
4215 op->type = OP_NONE; /* Disable writeback. */
4216 break;
4217 }
4218
4219done:
4220 return rc;
4221}
4222
ef5d75cc 4223int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4224{
dde7e6d1
AK		 4225 int rc = X86EMUL_CONTINUE;
4226 int mode = ctxt->mode;
46561646 4227 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4228 bool op_prefix = false;
573e80fe 4229 bool has_seg_override = false;
46561646 4230 struct opcode opcode;
dde7e6d1 4231
f09ed83e
AK		 4232 ctxt->memop.type = OP_NONE;
4233 ctxt->memopp = NULL;
9dac77fa 4234 ctxt->_eip = ctxt->eip;
17052f16
PB		 4235 ctxt->fetch.ptr = ctxt->fetch.data;
4236 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4237 ctxt->opcode_len = 1;
dc25e89e 4238 if (insn_len > 0)
9dac77fa 4239 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4240 else {
9506d57d 4241 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4242 if (rc != X86EMUL_CONTINUE)
4243 return rc;
4244 }
dde7e6d1
AK		 4245
4246 switch (mode) {
4247 case X86EMUL_MODE_REAL:
4248 case X86EMUL_MODE_VM86:
4249 case X86EMUL_MODE_PROT16:
4250 def_op_bytes = def_ad_bytes = 2;
4251 break;
4252 case X86EMUL_MODE_PROT32:
4253 def_op_bytes = def_ad_bytes = 4;
4254 break;
4255#ifdef CONFIG_X86_64
4256 case X86EMUL_MODE_PROT64:
4257 def_op_bytes = 4;
4258 def_ad_bytes = 8;
4259 break;
4260#endif
4261 default:
1d2887e2 4262 return EMULATION_FAILED;
dde7e6d1
AK		 4263 }
4264
9dac77fa
AK		 4265 ctxt->op_bytes = def_op_bytes;
4266 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4267
4268 /* Legacy prefixes. */
4269 for (;;) {
e85a1085 4270 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4271 case 0x66: /* operand-size override */
0d7cdee8 4272 op_prefix = true;
dde7e6d1 4273 /* switch between 2/4 bytes */
9dac77fa 4274 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4275 break;
4276 case 0x67: /* address-size override */
4277 if (mode == X86EMUL_MODE_PROT64)
4278 /* switch between 4/8 bytes */
9dac77fa 4279 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4280 else
4281 /* switch between 2/4 bytes */
9dac77fa 4282 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4283 break;
4284 case 0x26: /* ES override */
4285 case 0x2e: /* CS override */
4286 case 0x36: /* SS override */
4287 case 0x3e: /* DS override */
573e80fe
BD		 4288 has_seg_override = true;
4289 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4290 break;
4291 case 0x64: /* FS override */
4292 case 0x65: /* GS override */
573e80fe
BD		 4293 has_seg_override = true;
4294 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4295 break;
4296 case 0x40 ... 0x4f: /* REX */
4297 if (mode != X86EMUL_MODE_PROT64)
4298 goto done_prefixes;
9dac77fa 4299 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4300 continue;
4301 case 0xf0: /* LOCK */
9dac77fa 4302 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4303 break;
4304 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4305 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4306 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4307 break;
4308 default:
4309 goto done_prefixes;
4310 }
4311
4312 /* Any legacy prefix after a REX prefix nullifies its effect. */
4313
9dac77fa 4314 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4315 }
4316
4317done_prefixes:
4318
4319 /* REX prefix. */
9dac77fa
AK		 4320 if (ctxt->rex_prefix & 8)
4321 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4322
4323 /* Opcode byte(s). */
9dac77fa 4324 opcode = opcode_table[ctxt->b];
d3ad6243 4325 /* Two-byte opcode? */
9dac77fa 4326 if (ctxt->b == 0x0f) {
1ce19dc1 4327 ctxt->opcode_len = 2;
e85a1085 4328 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4329 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4330
4331 /* 0F_38 opcode map */
4332 if (ctxt->b == 0x38) {
4333 ctxt->opcode_len = 3;
4334 ctxt->b = insn_fetch(u8, ctxt);
4335 opcode = opcode_map_0f_38[ctxt->b];
4336 }
dde7e6d1 4337 }
9dac77fa 4338 ctxt->d = opcode.flags;
dde7e6d1 4339
9f4260e7
TY		 4340 if (ctxt->d & ModRM)
4341 ctxt->modrm = insn_fetch(u8, ctxt);
4342
7fe864dc
NA		 4343 /* vex-prefix instructions are not implemented */
4344 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4345 (mode == X86EMUL_MODE_PROT64 ||
4346 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4347 ctxt->d = NotImpl;
4348 }
4349
9dac77fa
AK		 4350 while (ctxt->d & GroupMask) {
4351 switch (ctxt->d & GroupMask) {
46561646 4352 case Group:
9dac77fa 4353 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4354 opcode = opcode.u.group[goffset];
4355 break;
4356 case GroupDual:
9dac77fa
AK		 4357 goffset = (ctxt->modrm >> 3) & 7;
4358 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4359 opcode = opcode.u.gdual->mod3[goffset];
4360 else
4361 opcode = opcode.u.gdual->mod012[goffset];
4362 break;
4363 case RMExt:
9dac77fa 4364 goffset = ctxt->modrm & 7;
01de8b09 4365 opcode = opcode.u.group[goffset];
46561646
AK		 4366 break;
4367 case Prefix:
9dac77fa 4368 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4369 return EMULATION_FAILED;
9dac77fa 4370 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4371 switch (simd_prefix) {
4372 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4373 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4374 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4375 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4376 }
4377 break;
045a282c
GN		 4378 case Escape:
4379 if (ctxt->modrm > 0xbf)
4380 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4381 else
4382 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4383 break;
46561646 4384 default:
1d2887e2 4385 return EMULATION_FAILED;
0d7cdee8 4386 }
46561646 4387
b1ea50b2 4388 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4389 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4390 }
4391
e24186e0
PB		 4392 /* Unrecognised? */
4393 if (ctxt->d == 0)
4394 return EMULATION_FAILED;
4395
9dac77fa 4396 ctxt->execute = opcode.u.execute;
dde7e6d1 4397
d40a6898
PB		 4398 if (unlikely(ctxt->d &
4399 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4400 /*
4401 * These are copied unconditionally here, and checked unconditionally
4402 * in x86_emulate_insn.
4403 */
4404 ctxt->check_perm = opcode.check_perm;
4405 ctxt->intercept = opcode.intercept;
dde7e6d1 4406
d40a6898
PB		 4407 if (ctxt->d & NotImpl)
4408 return EMULATION_FAILED;
d867162c 4409
d40a6898
PB		 4410 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4411 return EMULATION_FAILED;
dde7e6d1 4412
d40a6898 4413 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4414 ctxt->op_bytes = 8;
7f9b4b75 4415
d40a6898
PB		 4416 if (ctxt->d & Op3264) {
4417 if (mode == X86EMUL_MODE_PROT64)
4418 ctxt->op_bytes = 8;
4419 else
4420 ctxt->op_bytes = 4;
4421 }
4422
4423 if (ctxt->d & Sse)
4424 ctxt->op_bytes = 16;
4425 else if (ctxt->d & Mmx)
4426 ctxt->op_bytes = 8;
4427 }
1253791d 4428
dde7e6d1 4429 /* ModRM and SIB bytes. */
9dac77fa 4430 if (ctxt->d & ModRM) {
f09ed83e 4431 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4432 if (!has_seg_override) {
4433 has_seg_override = true;
4434 ctxt->seg_override = ctxt->modrm_seg;
4435 }
9dac77fa 4436 } else if (ctxt->d & MemAbs)
f09ed83e 4437 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4438 if (rc != X86EMUL_CONTINUE)
4439 goto done;
4440
573e80fe
BD		 4441 if (!has_seg_override)
4442 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4443
573e80fe 4444 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4445
dde7e6d1
AK		 4446 /*
4447 * Decode and fetch the source operand: register, memory
4448 * or immediate.
4449 */
0fe59128 4450 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4451 if (rc != X86EMUL_CONTINUE)
4452 goto done;
4453
dde7e6d1
AK		 4454 /*
4455 * Decode and fetch the second source operand: register, memory
4456 * or immediate.
4457 */
4dd6a57d 4458 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4459 if (rc != X86EMUL_CONTINUE)
4460 goto done;
4461
dde7e6d1 4462 /* Decode and fetch the destination operand: register or memory. */
a9945549 4463 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4464
4465done:
41061cdb 4466 if (ctxt->rip_relative)
f09ed83e 4467 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4468
1d2887e2 4469 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4470}
4471
1cb3f3ae
XG		 4472bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4473{
4474 return ctxt->d & PageTable;
4475}
4476
3e2f65d5
GN		 4477static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4478{
3e2f65d5
GN		 4479 /* The second termination condition only applies for REPE
4480 * and REPNE. Test if the repeat string operation prefix is
4481 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4482 * corresponding termination condition according to:
4483 * - if REPE/REPZ and ZF = 0 then done
4484 * - if REPNE/REPNZ and ZF = 1 then done
4485 */
9dac77fa
AK		 4486 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4487 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4488 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4489 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4490 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4491 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4492 return true;
4493
4494 return false;
4495}
4496
cbe2c9d3
AK		 4497static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4498{
4499 bool fault = false;
4500
4501 ctxt->ops->get_fpu(ctxt);
4502 asm volatile("1: fwait \n\t"
4503 "2: \n\t"
4504 ".pushsection .fixup,\"ax\" \n\t"
4505 "3: \n\t"
4506 "movb $1, %[fault] \n\t"
4507 "jmp 2b \n\t"
4508 ".popsection \n\t"
4509 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4510 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4511 ctxt->ops->put_fpu(ctxt);
4512
4513 if (unlikely(fault))
4514 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4515
4516 return X86EMUL_CONTINUE;
4517}
4518
4519static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4520 struct operand *op)
4521{
4522 if (op->type == OP_MM)
4523 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4524}
4525
e28bbd44
AK		 4526static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4527{
4528 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4529 if (!(ctxt->d & ByteOp))
4530 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4531 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4532 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4533 [fastop]"+S"(fop)
4534 : "c"(ctxt->src2.val));
e28bbd44 4535 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4536 if (!fop) /* exception is returned in fop variable */
4537 return emulate_de(ctxt);
e28bbd44
AK		 4538 return X86EMUL_CONTINUE;
4539}
dd856efa 4540
1498507a
BD		 4541void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4542{
573e80fe
BD		 4543 memset(&ctxt->rip_relative, 0,
4544 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4545
1498507a
BD		 4546 ctxt->io_read.pos = 0;
4547 ctxt->io_read.end = 0;
1498507a
BD		 4548 ctxt->mem_read.end = 0;
4549}
4550
7b105ca2 4551int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4552{
0225fb50 4553 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4554 int rc = X86EMUL_CONTINUE;
9dac77fa 4555 int saved_dst_type = ctxt->dst.type;
8b4caf66 4556
9dac77fa 4557 ctxt->mem_read.pos = 0;
310b5d30 4558
e24186e0
PB		 4559 /* LOCK prefix is allowed only with some instructions */
4560 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4561 rc = emulate_ud(ctxt);
1161624f
GN		 4562 goto done;
4563 }
4564
e24186e0 4565 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4566 rc = emulate_ud(ctxt);
d380a5e4
GN		 4567 goto done;
4568 }
4569
d40a6898
PB		 4570 if (unlikely(ctxt->d &
4571 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4572 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4573 (ctxt->d & Undefined)) {
4574 rc = emulate_ud(ctxt);
4575 goto done;
4576 }
1253791d 4577
d40a6898
PB		 4578 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4579 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4580 rc = emulate_ud(ctxt);
cbe2c9d3 4581 goto done;
d40a6898 4582 }
cbe2c9d3 4583
d40a6898
PB		 4584 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4585 rc = emulate_nm(ctxt);
c4f035c6 4586 goto done;
d40a6898 4587 }
c4f035c6 4588
d40a6898
PB		 4589 if (ctxt->d & Mmx) {
4590 rc = flush_pending_x87_faults(ctxt);
4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593 /*
4594 * Now that we know the fpu is exception safe, we can fetch
4595 * operands from it.
4596 */
4597 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4598 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4599 if (!(ctxt->d & Mov))
4600 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4601 }
e92805ac 4602
685bbf4a 4603 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4604 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4605 X86_ICPT_PRE_EXCEPT);
4606 if (rc != X86EMUL_CONTINUE)
4607 goto done;
4608 }
8ea7d6ae 4609
d40a6898
PB		 4610 /* Privileged instruction can be executed only in CPL=0 */
4611 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4612 if (ctxt->d & PrivUD)
4613 rc = emulate_ud(ctxt);
4614 else
4615 rc = emulate_gp(ctxt, 0);
d09beabd 4616 goto done;
d40a6898 4617 }
d09beabd 4618
d40a6898
PB		 4619 /* Instruction can only be executed in protected mode */
4620 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4621 rc = emulate_ud(ctxt);
c4f035c6 4622 goto done;
d40a6898 4623 }
c4f035c6 4624
d40a6898 4625 /* Do instruction specific permission checks */
685bbf4a 4626 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4627 rc = ctxt->check_perm(ctxt);
4628 if (rc != X86EMUL_CONTINUE)
4629 goto done;
4630 }
4631
685bbf4a 4632 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4633 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4634 X86_ICPT_POST_EXCEPT);
4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637 }
4638
4639 if (ctxt->rep_prefix && (ctxt->d & String)) {
4640 /* All REP prefixes have the same first termination condition */
4641 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4642 ctxt->eip = ctxt->_eip;
4467c3f1 4643 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4644 goto done;
4645 }
b9fa9d6b 4646 }
b9fa9d6b
AK		 4647 }
4648
9dac77fa
AK		 4649 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4650 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4651 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4652 if (rc != X86EMUL_CONTINUE)
8b4caf66 4653 goto done;
9dac77fa 4654 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4655 }
4656
9dac77fa
AK		 4657 if (ctxt->src2.type == OP_MEM) {
4658 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4659 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4660 if (rc != X86EMUL_CONTINUE)
4661 goto done;
4662 }
4663
9dac77fa 4664 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4665 goto special_insn;
4666
4667
9dac77fa 4668 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4669 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4670 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4671 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4672 if (rc != X86EMUL_CONTINUE)
4673 goto done;
038e51de 4674 }
9dac77fa 4675 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4676
018a98db
AK		 4677special_insn:
4678
685bbf4a 4679 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4680 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4681 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4682 if (rc != X86EMUL_CONTINUE)
4683 goto done;
4684 }
4685
4467c3f1
NA		 4686 ctxt->eflags &= ~EFLG_RF;
4687
9dac77fa 4688 if (ctxt->execute) {
e28bbd44
AK		 4689 if (ctxt->d & Fastop) {
4690 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4691 rc = fastop(ctxt, fop);
4692 if (rc != X86EMUL_CONTINUE)
4693 goto done;
4694 goto writeback;
4695 }
9dac77fa 4696 rc = ctxt->execute(ctxt);
ef65c889
AK		 4697 if (rc != X86EMUL_CONTINUE)
4698 goto done;
4699 goto writeback;
4700 }
4701
1ce19dc1 4702 if (ctxt->opcode_len == 2)
6aa8b732 4703 goto twobyte_insn;
0bc5eedb
BP		 4704 else if (ctxt->opcode_len == 3)
4705 goto threebyte_insn;
6aa8b732 4706
9dac77fa 4707 switch (ctxt->b) {
6aa8b732 4708 case 0x63: /* movsxd */
8b4caf66 4709 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4710 goto cannot_emulate;
9dac77fa 4711 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4712 break;
b2833e3c 4713 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4714 if (test_cc(ctxt->b, ctxt->eflags))
4715 jmp_rel(ctxt, ctxt->src.val);
018a98db 4716 break;
7e0b54b1 4717 case 0x8d: /* lea r16/r32, m */
9dac77fa 4718 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4719 break;
3d9e77df 4720 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4721 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4722 ctxt->dst.type = OP_NONE;
4723 else
4724 rc = em_xchg(ctxt);
e4f973ae 4725 break;
e8b6fa70 4726 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4727 switch (ctxt->op_bytes) {
4728 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4729 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4730 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4731 }
4732 break;
6e154e56 4733 case 0xcc: /* int3 */
5c5df76b
TY		 4734 rc = emulate_int(ctxt, 3);
4735 break;
6e154e56 4736 case 0xcd: /* int n */
9dac77fa 4737 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4738 break;
4739 case 0xce: /* into */
5c5df76b
TY		 4740 if (ctxt->eflags & EFLG_OF)
4741 rc = emulate_int(ctxt, 4);
6e154e56 4742 break;
1a52e051 4743 case 0xe9: /* jmp rel */
db5b0762 4744 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4745 jmp_rel(ctxt, ctxt->src.val);
4746 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4747 break;
111de5d6 4748 case 0xf4: /* hlt */
6c3287f7 4749 ctxt->ops->halt(ctxt);
19fdfa0d 4750 break;
111de5d6
AK		 4751 case 0xf5: /* cmc */
4752 /* complement carry flag from eflags reg */
4753 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4754 break;
4755 case 0xf8: /* clc */
4756 ctxt->eflags &= ~EFLG_CF;
111de5d6 4757 break;
8744aa9a
MG		 4758 case 0xf9: /* stc */
4759 ctxt->eflags |= EFLG_CF;
4760 break;
fb4616f4
MG		 4761 case 0xfc: /* cld */
4762 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4763 break;
4764 case 0xfd: /* std */
4765 ctxt->eflags |= EFLG_DF;
fb4616f4 4766 break;
91269b8f
AK		 4767 default:
4768 goto cannot_emulate;
6aa8b732 4769 }
018a98db 4770
7d9ddaed
AK		 4771 if (rc != X86EMUL_CONTINUE)
4772 goto done;
4773
018a98db 4774writeback:
fb32b1ed
AK		 4775 if (ctxt->d & SrcWrite) {
4776 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4777 rc = writeback(ctxt, &ctxt->src);
4778 if (rc != X86EMUL_CONTINUE)
4779 goto done;
4780 }
ee212297
NA		 4781 if (!(ctxt->d & NoWrite)) {
4782 rc = writeback(ctxt, &ctxt->dst);
4783 if (rc != X86EMUL_CONTINUE)
4784 goto done;
4785 }
018a98db 4786
5cd21917
GN		 4787 /*
4788 * restore dst type in case the decoding will be reused
4789 * (happens for string instruction )
4790 */
9dac77fa 4791 ctxt->dst.type = saved_dst_type;
5cd21917 4792
9dac77fa 4793 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4794 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4795
9dac77fa 4796 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4797 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4798
9dac77fa 4799 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4800 unsigned int count;
9dac77fa 4801 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4802 if ((ctxt->d & SrcMask) == SrcSI)
4803 count = ctxt->src.count;
4804 else
4805 count = ctxt->dst.count;
4806 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4807 -count);
3e2f65d5 4808
d2ddd1c4
GN		 4809 if (!string_insn_completed(ctxt)) {
4810 /*
4811 * Re-enter guest when pio read ahead buffer is empty
4812 * or, if it is not used, after each 1024 iteration.
4813 */
dd856efa 4814 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4815 (r->end == 0 || r->end != r->pos)) {
4816 /*
4817 * Reset read cache. Usually happens before
4818 * decode, but since instruction is restarted
4819 * we have to do it here.
4820 */
9dac77fa 4821 ctxt->mem_read.end = 0;
dd856efa 4822 writeback_registers(ctxt);
d2ddd1c4
GN		 4823 return EMULATION_RESTART;
4824 }
4825 goto done; /* skip rip writeback */
0fa6ccbd 4826 }
5cd21917 4827 }
d2ddd1c4 4828
9dac77fa 4829 ctxt->eip = ctxt->_eip;
018a98db
AK		 4830
4831done:
da9cb575
AK		 4832 if (rc == X86EMUL_PROPAGATE_FAULT)
4833 ctxt->have_exception = true;
775fde86
JR		 4834 if (rc == X86EMUL_INTERCEPTED)
4835 return EMULATION_INTERCEPTED;
4836
dd856efa
AK		 4837 if (rc == X86EMUL_CONTINUE)
4838 writeback_registers(ctxt);
4839
d2ddd1c4 4840 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4841
4842twobyte_insn:
9dac77fa 4843 switch (ctxt->b) {
018a98db 4844 case 0x09: /* wbinvd */
cfb22375 4845 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4846 break;
4847 case 0x08: /* invd */
018a98db
AK		 4848 case 0x0d: /* GrpP (prefetch) */
4849 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4850 case 0x1f: /* nop */
018a98db
AK		 4851 break;
4852 case 0x20: /* mov cr, reg */
9dac77fa 4853 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4854 break;
6aa8b732 4855 case 0x21: /* mov from dr to reg */
9dac77fa 4856 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4857 break;
6aa8b732 4858 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4859 if (test_cc(ctxt->b, ctxt->eflags))
4860 ctxt->dst.val = ctxt->src.val;
4861 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4862 ctxt->op_bytes != 4)
9dac77fa 4863 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4864 break;
b2833e3c 4865 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4866 if (test_cc(ctxt->b, ctxt->eflags))
4867 jmp_rel(ctxt, ctxt->src.val);
018a98db 4868 break;
ee45b58e 4869 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4870 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4871 break;
2a7c5b8b
GC		 4872 case 0xae: /* clflush */
4873 break;
6aa8b732 4874 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4875 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4876 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4877 : (u16) ctxt->src.val;
6aa8b732 4878 break;
6aa8b732 4879 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4880 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4881 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4882 (s16) ctxt->src.val;
6aa8b732 4883 break;
a012e65a 4884 case 0xc3: /* movnti */
9dac77fa 4885 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4886 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4887 (u32) ctxt->src.val;
a012e65a 4888 break;
91269b8f
AK		 4889 default:
4890 goto cannot_emulate;
6aa8b732 4891 }
7d9ddaed 4892
0bc5eedb
BP		 4893threebyte_insn:
4894
7d9ddaed
AK		 4895 if (rc != X86EMUL_CONTINUE)
4896 goto done;
4897
6aa8b732
AK		 4898 goto writeback;
4899
4900cannot_emulate:
a0c0ab2f 4901 return EMULATION_FAILED;
6aa8b732 4902}
dd856efa
AK		 4903
4904void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4905{
4906 invalidate_registers(ctxt);
4907}
4908
4909void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4910{
4911 writeback_registers(ctxt);
4912}
Linux kernel - Deliverables
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