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KVM: x86 emulator: initialize memop
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
f47cfa31
AK		 436static void assign_masked(ulong *dest, ulong src, ulong mask)
437{
438 *dest = (*dest & ~mask) | (src & mask);
439}
440
9dac77fa 441static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 442{
9dac77fa 443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 444}
445
f47cfa31
AK		 446static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447{
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455}
456
6aa8b732 457/* Access/update address held in a register, based on addressing mode. */
e4706772 458static inline unsigned long
9dac77fa 459address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 460{
9dac77fa 461 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 462 return reg;
463 else
9dac77fa 464 return reg & ad_mask(ctxt);
e4706772
HH		 465}
466
467static inline unsigned long
9dac77fa 468register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 469{
9dac77fa 470 return address_mask(ctxt, reg);
e4706772
HH		 471}
472
7a957275 473static inline void
9dac77fa 474register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 475{
9dac77fa 476 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 477 *reg += inc;
478 else
9dac77fa 479 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 480}
6aa8b732 481
9dac77fa 482static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 483{
9dac77fa 484 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 485}
098c937b 486
56697687
AK		 487static u32 desc_limit_scaled(struct desc_struct *desc)
488{
489 u32 limit = get_desc_limit(desc);
490
491 return desc->g ? (limit << 12) | 0xfff : limit;
492}
493
9dac77fa 494static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 495{
9dac77fa
AK		 496 ctxt->has_seg_override = true;
497 ctxt->seg_override = seg;
7a5b56df
AK		 498}
499
7b105ca2 500static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 501{
502 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
503 return 0;
504
7b105ca2 505 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 506}
507
9dac77fa 508static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 509{
9dac77fa 510 if (!ctxt->has_seg_override)
7a5b56df
AK		 511 return 0;
512
9dac77fa 513 return ctxt->seg_override;
7a5b56df
AK		 514}
515
35d3d4a1
AK		 516static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
517 u32 error, bool valid)
54b8486f 518{
da9cb575
AK		 519 ctxt->exception.vector = vec;
520 ctxt->exception.error_code = error;
521 ctxt->exception.error_code_valid = valid;
35d3d4a1 522 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 523}
524
3b88e41a
JR		 525static int emulate_db(struct x86_emulate_ctxt *ctxt)
526{
527 return emulate_exception(ctxt, DB_VECTOR, 0, false);
528}
529
35d3d4a1 530static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 531{
35d3d4a1 532 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 533}
534
618ff15d
AK		 535static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
536{
537 return emulate_exception(ctxt, SS_VECTOR, err, true);
538}
539
35d3d4a1 540static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 543}
544
35d3d4a1 545static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 546{
35d3d4a1 547 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 548}
549
34d1f490
AK		 550static int emulate_de(struct x86_emulate_ctxt *ctxt)
551{
35d3d4a1 552 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 553}
554
1253791d
AK		 555static int emulate_nm(struct x86_emulate_ctxt *ctxt)
556{
557 return emulate_exception(ctxt, NM_VECTOR, 0, false);
558}
559
1aa36616
AK		 560static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
561{
562 u16 selector;
563 struct desc_struct desc;
564
565 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
566 return selector;
567}
568
569static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
570 unsigned seg)
571{
572 u16 dummy;
573 u32 base3;
574 struct desc_struct desc;
575
576 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
577 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
578}
579
1c11b376
AK		 580/*
581 * x86 defines three classes of vector instructions: explicitly
582 * aligned, explicitly unaligned, and the rest, which change behaviour
583 * depending on whether they're AVX encoded or not.
584 *
585 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
586 * subject to the same check.
587 */
588static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
589{
590 if (likely(size < 16))
591 return false;
592
593 if (ctxt->d & Aligned)
594 return true;
595 else if (ctxt->d & Unaligned)
596 return false;
597 else if (ctxt->d & Avx)
598 return false;
599 else
600 return true;
601}
602
3d9b938e 603static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 604 struct segmented_address addr,
3d9b938e 605 unsigned size, bool write, bool fetch,
52fd8b44
AK		 606 ulong *linear)
607{
618ff15d
AK		 608 struct desc_struct desc;
609 bool usable;
52fd8b44 610 ulong la;
618ff15d 611 u32 lim;
1aa36616 612 u16 sel;
618ff15d 613 unsigned cpl, rpl;
52fd8b44 614
7b105ca2 615 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 616 switch (ctxt->mode) {
617 case X86EMUL_MODE_REAL:
618 break;
619 case X86EMUL_MODE_PROT64:
620 if (((signed long)la << 16) >> 16 != la)
621 return emulate_gp(ctxt, 0);
622 break;
623 default:
1aa36616
AK		 624 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
625 addr.seg);
618ff15d
AK		 626 if (!usable)
627 goto bad;
628 /* code segment or read-only data segment */
629 if (((desc.type & 8) || !(desc.type & 2)) && write)
630 goto bad;
631 /* unreadable code segment */
3d9b938e 632 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 633 goto bad;
634 lim = desc_limit_scaled(&desc);
635 if ((desc.type & 8) || !(desc.type & 4)) {
636 /* expand-up segment */
637 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
638 goto bad;
639 } else {
640 /* exapand-down segment */
641 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
642 goto bad;
643 lim = desc.d ? 0xffffffff : 0xffff;
644 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
645 goto bad;
646 }
717746e3 647 cpl = ctxt->ops->cpl(ctxt);
1aa36616 648 rpl = sel & 3;
618ff15d
AK		 649 cpl = max(cpl, rpl);
650 if (!(desc.type & 8)) {
651 /* data segment */
652 if (cpl > desc.dpl)
653 goto bad;
654 } else if ((desc.type & 8) && !(desc.type & 4)) {
655 /* nonconforming code segment */
656 if (cpl != desc.dpl)
657 goto bad;
658 } else if ((desc.type & 8) && (desc.type & 4)) {
659 /* conforming code segment */
660 if (cpl < desc.dpl)
661 goto bad;
662 }
663 break;
664 }
9dac77fa 665 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 666 la &= (u32)-1;
1c11b376
AK		 667 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
668 return emulate_gp(ctxt, 0);
52fd8b44
AK		 669 *linear = la;
670 return X86EMUL_CONTINUE;
618ff15d
AK		 671bad:
672 if (addr.seg == VCPU_SREG_SS)
673 return emulate_ss(ctxt, addr.seg);
674 else
675 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 676}
677
3d9b938e
NE		 678static int linearize(struct x86_emulate_ctxt *ctxt,
679 struct segmented_address addr,
680 unsigned size, bool write,
681 ulong *linear)
682{
683 return __linearize(ctxt, addr, size, write, false, linear);
684}
685
686
3ca3ac4d
AK		 687static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
688 struct segmented_address addr,
689 void *data,
690 unsigned size)
691{
9fa088f4
AK		 692 int rc;
693 ulong linear;
694
83b8795a 695 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 696 if (rc != X86EMUL_CONTINUE)
697 return rc;
0f65dd70 698 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 699}
700
807941b1
TY		 701/*
702 * Fetch the next byte of the instruction being emulated which is pointed to
703 * by ctxt->_eip, then increment ctxt->_eip.
704 *
705 * Also prefetch the remaining bytes of the instruction without crossing page
706 * boundary if they are not in fetch_cache yet.
707 */
708static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 709{
9dac77fa 710 struct fetch_cache *fc = &ctxt->fetch;
62266869 711 int rc;
2fb53ad8 712 int size, cur_size;
62266869 713
807941b1 714 if (ctxt->_eip == fc->end) {
3d9b938e 715 unsigned long linear;
807941b1
TY		 716 struct segmented_address addr = { .seg = VCPU_SREG_CS,
717 .ea = ctxt->_eip };
2fb53ad8 718 cur_size = fc->end - fc->start;
807941b1
TY		 719 size = min(15UL - cur_size,
720 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 721 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 722 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 723 return rc;
ef5d75cc
TY		 724 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
725 size, &ctxt->exception);
7d88bb48 726 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 727 return rc;
2fb53ad8 728 fc->end += size;
62266869 729 }
807941b1
TY		 730 *dest = fc->data[ctxt->_eip - fc->start];
731 ctxt->_eip++;
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK		 733}
734
735static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 736 void *dest, unsigned size)
62266869 737{
3e2815e9 738 int rc;
62266869 739
eb3c79e6 740 /* x86 instructions are limited to 15 bytes. */
7d88bb48 741 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 742 return X86EMUL_UNHANDLEABLE;
62266869 743 while (size--) {
807941b1 744 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 745 if (rc != X86EMUL_CONTINUE)
62266869
AK		 746 return rc;
747 }
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK		 749}
750
67cbc90d 751/* Fetch next part of the instruction being emulated. */
e85a1085 752#define insn_fetch(_type, _ctxt) \
67cbc90d 753({ unsigned long _x; \
e85a1085 754 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 755 if (rc != X86EMUL_CONTINUE) \
756 goto done; \
67cbc90d
TY		 757 (_type)_x; \
758})
759
807941b1
TY		 760#define insn_fetch_arr(_arr, _size, _ctxt) \
761({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 762 if (rc != X86EMUL_CONTINUE) \
763 goto done; \
67cbc90d
TY		 764})
765
1e3c5cb0
RR		 766/*
767 * Given the 'reg' portion of a ModRM byte, and a register block, return a
768 * pointer into the block that addresses the relevant register.
769 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
770 */
771static void *decode_register(u8 modrm_reg, unsigned long *regs,
772 int highbyte_regs)
6aa8b732
AK		 773{
774 void *p;
775
776 p = &regs[modrm_reg];
777 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
778 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
779 return p;
780}
781
782static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 783 struct segmented_address addr,
6aa8b732
AK		 784 u16 *size, unsigned long *address, int op_bytes)
785{
786 int rc;
787
788 if (op_bytes == 2)
789 op_bytes = 3;
790 *address = 0;
3ca3ac4d 791 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 792 if (rc != X86EMUL_CONTINUE)
6aa8b732 793 return rc;
30b31ab6 794 addr.ea += 2;
3ca3ac4d 795 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 796 return rc;
797}
798
bbe9abbd
NK		 799static int test_cc(unsigned int condition, unsigned int flags)
800{
801 int rc = 0;
802
803 switch ((condition & 15) >> 1) {
804 case 0: /* o */
805 rc |= (flags & EFLG_OF);
806 break;
807 case 1: /* b/c/nae */
808 rc |= (flags & EFLG_CF);
809 break;
810 case 2: /* z/e */
811 rc |= (flags & EFLG_ZF);
812 break;
813 case 3: /* be/na */
814 rc |= (flags & (EFLG_CF|EFLG_ZF));
815 break;
816 case 4: /* s */
817 rc |= (flags & EFLG_SF);
818 break;
819 case 5: /* p/pe */
820 rc |= (flags & EFLG_PF);
821 break;
822 case 7: /* le/ng */
823 rc |= (flags & EFLG_ZF);
824 /* fall through */
825 case 6: /* l/nge */
826 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
827 break;
828 }
829
830 /* Odd condition identifiers (lsb == 1) have inverted sense. */
831 return (!!rc ^ (condition & 1));
832}
833
91ff3cb4
AK		 834static void fetch_register_operand(struct operand *op)
835{
836 switch (op->bytes) {
837 case 1:
838 op->val = *(u8 *)op->addr.reg;
839 break;
840 case 2:
841 op->val = *(u16 *)op->addr.reg;
842 break;
843 case 4:
844 op->val = *(u32 *)op->addr.reg;
845 break;
846 case 8:
847 op->val = *(u64 *)op->addr.reg;
848 break;
849 }
850}
851
1253791d
AK		 852static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
853{
854 ctxt->ops->get_fpu(ctxt);
855 switch (reg) {
856 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
857 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
858 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
859 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
860 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
861 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
862 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
863 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
864#ifdef CONFIG_X86_64
865 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
866 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
867 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
868 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
869 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
870 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
871 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
872 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
873#endif
874 default: BUG();
875 }
876 ctxt->ops->put_fpu(ctxt);
877}
878
879static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
880 int reg)
881{
882 ctxt->ops->get_fpu(ctxt);
883 switch (reg) {
884 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
885 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
886 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
887 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
888 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
889 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
890 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
891 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
892#ifdef CONFIG_X86_64
893 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
894 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
895 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
896 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
897 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
898 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
899 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
900 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
901#endif
902 default: BUG();
903 }
904 ctxt->ops->put_fpu(ctxt);
905}
906
cbe2c9d3
AK		 907static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
908{
909 ctxt->ops->get_fpu(ctxt);
910 switch (reg) {
911 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
912 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
913 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
914 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
915 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
916 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
917 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
918 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
919 default: BUG();
920 }
921 ctxt->ops->put_fpu(ctxt);
922}
923
924static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
925{
926 ctxt->ops->get_fpu(ctxt);
927 switch (reg) {
928 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
929 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
930 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
931 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
932 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
933 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
934 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
935 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
936 default: BUG();
937 }
938 ctxt->ops->put_fpu(ctxt);
939}
940
1253791d 941static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 942 struct operand *op)
3c118e24 943{
9dac77fa
AK		 944 unsigned reg = ctxt->modrm_reg;
945 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 946
9dac77fa
AK		 947 if (!(ctxt->d & ModRM))
948 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 949
9dac77fa 950 if (ctxt->d & Sse) {
1253791d
AK		 951 op->type = OP_XMM;
952 op->bytes = 16;
953 op->addr.xmm = reg;
954 read_sse_reg(ctxt, &op->vec_val, reg);
955 return;
956 }
cbe2c9d3
AK		 957 if (ctxt->d & Mmx) {
958 reg &= 7;
959 op->type = OP_MM;
960 op->bytes = 8;
961 op->addr.mm = reg;
962 return;
963 }
1253791d 964
3c118e24 965 op->type = OP_REG;
2adb5ad9 966 if (ctxt->d & ByteOp) {
9dac77fa 967 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 968 op->bytes = 1;
969 } else {
9dac77fa
AK		 970 op->addr.reg = decode_register(reg, ctxt->regs, 0);
971 op->bytes = ctxt->op_bytes;
3c118e24 972 }
91ff3cb4 973 fetch_register_operand(op);
3c118e24
AK		 974 op->orig_val = op->val;
975}
976
1c73ef66 977static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 978 struct operand *op)
1c73ef66 979{
1c73ef66 980 u8 sib;
f5b4edcd 981 int index_reg = 0, base_reg = 0, scale;
3e2815e9 982 int rc = X86EMUL_CONTINUE;
2dbd0dd7 983 ulong modrm_ea = 0;
1c73ef66 984
9dac77fa
AK		 985 if (ctxt->rex_prefix) {
986 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
987 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
988 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 989 }
990
9dac77fa
AK		 991 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
992 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
993 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
994 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 995
9dac77fa 996 if (ctxt->modrm_mod == 3) {
2dbd0dd7 997 op->type = OP_REG;
9dac77fa
AK		 998 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
999 op->addr.reg = decode_register(ctxt->modrm_rm,
1000 ctxt->regs, ctxt->d & ByteOp);
1001 if (ctxt->d & Sse) {
1253791d
AK		 1002 op->type = OP_XMM;
1003 op->bytes = 16;
9dac77fa
AK		 1004 op->addr.xmm = ctxt->modrm_rm;
1005 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1006 return rc;
1007 }
cbe2c9d3
AK		 1008 if (ctxt->d & Mmx) {
1009 op->type = OP_MM;
1010 op->bytes = 8;
1011 op->addr.xmm = ctxt->modrm_rm & 7;
1012 return rc;
1013 }
2dbd0dd7 1014 fetch_register_operand(op);
1c73ef66
AK		 1015 return rc;
1016 }
1017
2dbd0dd7
AK		 1018 op->type = OP_MEM;
1019
9dac77fa
AK		 1020 if (ctxt->ad_bytes == 2) {
1021 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1022 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1023 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1024 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1025
1026 /* 16-bit ModR/M decode. */
9dac77fa 1027 switch (ctxt->modrm_mod) {
1c73ef66 1028 case 0:
9dac77fa 1029 if (ctxt->modrm_rm == 6)
e85a1085 1030 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1031 break;
1032 case 1:
e85a1085 1033 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1034 break;
1035 case 2:
e85a1085 1036 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1037 break;
1038 }
9dac77fa 1039 switch (ctxt->modrm_rm) {
1c73ef66 1040 case 0:
2dbd0dd7 1041 modrm_ea += bx + si;
1c73ef66
AK		 1042 break;
1043 case 1:
2dbd0dd7 1044 modrm_ea += bx + di;
1c73ef66
AK		 1045 break;
1046 case 2:
2dbd0dd7 1047 modrm_ea += bp + si;
1c73ef66
AK		 1048 break;
1049 case 3:
2dbd0dd7 1050 modrm_ea += bp + di;
1c73ef66
AK		 1051 break;
1052 case 4:
2dbd0dd7 1053 modrm_ea += si;
1c73ef66
AK		 1054 break;
1055 case 5:
2dbd0dd7 1056 modrm_ea += di;
1c73ef66
AK		 1057 break;
1058 case 6:
9dac77fa 1059 if (ctxt->modrm_mod != 0)
2dbd0dd7 1060 modrm_ea += bp;
1c73ef66
AK		 1061 break;
1062 case 7:
2dbd0dd7 1063 modrm_ea += bx;
1c73ef66
AK		 1064 break;
1065 }
9dac77fa
AK		 1066 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1067 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1068 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1069 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1070 } else {
1071 /* 32/64-bit ModR/M decode. */
9dac77fa 1072 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1073 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1074 index_reg |= (sib >> 3) & 7;
1075 base_reg |= sib & 7;
1076 scale = sib >> 6;
1077
9dac77fa 1078 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1079 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 1080 else
9dac77fa 1081 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 1082 if (index_reg != 4)
9dac77fa
AK		 1083 modrm_ea += ctxt->regs[index_reg] << scale;
1084 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1085 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1086 ctxt->rip_relative = 1;
84411d85 1087 } else
9dac77fa
AK		 1088 modrm_ea += ctxt->regs[ctxt->modrm_rm];
1089 switch (ctxt->modrm_mod) {
1c73ef66 1090 case 0:
9dac77fa 1091 if (ctxt->modrm_rm == 5)
e85a1085 1092 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1093 break;
1094 case 1:
e85a1085 1095 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1096 break;
1097 case 2:
e85a1085 1098 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1099 break;
1100 }
1101 }
90de84f5 1102 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1103done:
1104 return rc;
1105}
1106
1107static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1108 struct operand *op)
1c73ef66 1109{
3e2815e9 1110 int rc = X86EMUL_CONTINUE;
1c73ef66 1111
2dbd0dd7 1112 op->type = OP_MEM;
9dac77fa 1113 switch (ctxt->ad_bytes) {
1c73ef66 1114 case 2:
e85a1085 1115 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1116 break;
1117 case 4:
e85a1085 1118 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1119 break;
1120 case 8:
e85a1085 1121 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1122 break;
1123 }
1124done:
1125 return rc;
1126}
1127
9dac77fa 1128static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1129{
7129eeca 1130 long sv = 0, mask;
35c843c4 1131
9dac77fa
AK		 1132 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1133 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1134
9dac77fa
AK		 1135 if (ctxt->src.bytes == 2)
1136 sv = (s16)ctxt->src.val & (s16)mask;
1137 else if (ctxt->src.bytes == 4)
1138 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1139
9dac77fa 1140 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1141 }
ba7ff2b7
WY		 1142
1143 /* only subword offset */
9dac77fa 1144 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1145}
1146
dde7e6d1 1147static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1148 unsigned long addr, void *dest, unsigned size)
6aa8b732 1149{
dde7e6d1 1150 int rc;
9dac77fa 1151 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1152
dde7e6d1
AK		 1153 while (size) {
1154 int n = min(size, 8u);
1155 size -= n;
1156 if (mc->pos < mc->end)
1157 goto read_cached;
5cd21917 1158
7b105ca2
TY		 1159 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1160 &ctxt->exception);
dde7e6d1
AK		 1161 if (rc != X86EMUL_CONTINUE)
1162 return rc;
1163 mc->end += n;
6aa8b732 1164
dde7e6d1
AK		 1165 read_cached:
1166 memcpy(dest, mc->data + mc->pos, n);
1167 mc->pos += n;
1168 dest += n;
1169 addr += n;
6aa8b732 1170 }
dde7e6d1
AK		 1171 return X86EMUL_CONTINUE;
1172}
6aa8b732 1173
3ca3ac4d
AK		 1174static int segmented_read(struct x86_emulate_ctxt *ctxt,
1175 struct segmented_address addr,
1176 void *data,
1177 unsigned size)
1178{
9fa088f4
AK		 1179 int rc;
1180 ulong linear;
1181
83b8795a 1182 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1183 if (rc != X86EMUL_CONTINUE)
1184 return rc;
7b105ca2 1185 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1186}
1187
1188static int segmented_write(struct x86_emulate_ctxt *ctxt,
1189 struct segmented_address addr,
1190 const void *data,
1191 unsigned size)
1192{
9fa088f4
AK		 1193 int rc;
1194 ulong linear;
1195
83b8795a 1196 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
0f65dd70
AK		 1199 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1200 &ctxt->exception);
3ca3ac4d
AK		 1201}
1202
1203static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1204 struct segmented_address addr,
1205 const void *orig_data, const void *data,
1206 unsigned size)
1207{
9fa088f4
AK		 1208 int rc;
1209 ulong linear;
1210
83b8795a 1211 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1212 if (rc != X86EMUL_CONTINUE)
1213 return rc;
0f65dd70
AK		 1214 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1215 size, &ctxt->exception);
3ca3ac4d
AK		 1216}
1217
dde7e6d1 1218static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1219 unsigned int size, unsigned short port,
1220 void *dest)
1221{
9dac77fa 1222 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1223
dde7e6d1 1224 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1225 unsigned int in_page, n;
9dac77fa
AK		 1226 unsigned int count = ctxt->rep_prefix ?
1227 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1228 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1229 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1230 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1231 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1232 count);
1233 if (n == 0)
1234 n = 1;
1235 rc->pos = rc->end = 0;
7b105ca2 1236 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1237 return 0;
1238 rc->end = n * size;
6aa8b732
AK		 1239 }
1240
dde7e6d1
AK		 1241 memcpy(dest, rc->data + rc->pos, size);
1242 rc->pos += size;
1243 return 1;
1244}
6aa8b732 1245
7f3d35fd
KW		 1246static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1247 u16 index, struct desc_struct *desc)
1248{
1249 struct desc_ptr dt;
1250 ulong addr;
1251
1252 ctxt->ops->get_idt(ctxt, &dt);
1253
1254 if (dt.size < index * 8 + 7)
1255 return emulate_gp(ctxt, index << 3 | 0x2);
1256
1257 addr = dt.address + index * 8;
1258 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1259 &ctxt->exception);
1260}
1261
dde7e6d1 1262static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1263 u16 selector, struct desc_ptr *dt)
1264{
7b105ca2
TY		 1265 struct x86_emulate_ops *ops = ctxt->ops;
1266
dde7e6d1
AK		 1267 if (selector & 1 << 2) {
1268 struct desc_struct desc;
1aa36616
AK		 1269 u16 sel;
1270
dde7e6d1 1271 memset (dt, 0, sizeof *dt);
1aa36616 1272 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1273 return;
e09d082c 1274
dde7e6d1
AK		 1275 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1276 dt->address = get_desc_base(&desc);
1277 } else
4bff1e86 1278 ops->get_gdt(ctxt, dt);
dde7e6d1 1279}
120df890 1280
dde7e6d1
AK		 1281/* allowed just for 8 bytes segments */
1282static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1283 u16 selector, struct desc_struct *desc)
1284{
1285 struct desc_ptr dt;
1286 u16 index = selector >> 3;
dde7e6d1 1287 ulong addr;
120df890 1288
7b105ca2 1289 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1290
35d3d4a1
AK		 1291 if (dt.size < index * 8 + 7)
1292 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1293
7b105ca2
TY		 1294 addr = dt.address + index * 8;
1295 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1296 &ctxt->exception);
dde7e6d1 1297}
ef65c889 1298
dde7e6d1
AK		 1299/* allowed just for 8 bytes segments */
1300static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1301 u16 selector, struct desc_struct *desc)
1302{
1303 struct desc_ptr dt;
1304 u16 index = selector >> 3;
dde7e6d1 1305 ulong addr;
6aa8b732 1306
7b105ca2 1307 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1308
35d3d4a1
AK		 1309 if (dt.size < index * 8 + 7)
1310 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1311
dde7e6d1 1312 addr = dt.address + index * 8;
7b105ca2
TY		 1313 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1314 &ctxt->exception);
dde7e6d1 1315}
c7e75a3d 1316
5601d05b 1317/* Does not support long mode */
dde7e6d1 1318static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1319 u16 selector, int seg)
1320{
1321 struct desc_struct seg_desc;
1322 u8 dpl, rpl, cpl;
1323 unsigned err_vec = GP_VECTOR;
1324 u32 err_code = 0;
1325 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1326 int ret;
69f55cb1 1327
dde7e6d1 1328 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1329
dde7e6d1
AK		 1330 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1331 || ctxt->mode == X86EMUL_MODE_REAL) {
1332 /* set real mode segment descriptor */
1333 set_desc_base(&seg_desc, selector << 4);
1334 set_desc_limit(&seg_desc, 0xffff);
1335 seg_desc.type = 3;
1336 seg_desc.p = 1;
1337 seg_desc.s = 1;
66b0ab8f
KW		 1338 if (ctxt->mode == X86EMUL_MODE_VM86)
1339 seg_desc.dpl = 3;
dde7e6d1
AK		 1340 goto load;
1341 }
1342
79d5b4c3
AK		 1343 rpl = selector & 3;
1344 cpl = ctxt->ops->cpl(ctxt);
1345
1346 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1347 if ((seg == VCPU_SREG_CS
1348 || (seg == VCPU_SREG_SS
1349 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1350 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1351 && null_selector)
1352 goto exception;
1353
1354 /* TR should be in GDT only */
1355 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1356 goto exception;
1357
1358 if (null_selector) /* for NULL selector skip all following checks */
1359 goto load;
1360
7b105ca2 1361 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1362 if (ret != X86EMUL_CONTINUE)
1363 return ret;
1364
1365 err_code = selector & 0xfffc;
1366 err_vec = GP_VECTOR;
1367
1368 /* can't load system descriptor into segment selecor */
1369 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1370 goto exception;
1371
1372 if (!seg_desc.p) {
1373 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1374 goto exception;
1375 }
1376
dde7e6d1 1377 dpl = seg_desc.dpl;
dde7e6d1
AK		 1378
1379 switch (seg) {
1380 case VCPU_SREG_SS:
1381 /*
1382 * segment is not a writable data segment or segment
1383 * selector's RPL != CPL or segment selector's RPL != CPL
1384 */
1385 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1386 goto exception;
6aa8b732 1387 break;
dde7e6d1
AK		 1388 case VCPU_SREG_CS:
1389 if (!(seg_desc.type & 8))
1390 goto exception;
1391
1392 if (seg_desc.type & 4) {
1393 /* conforming */
1394 if (dpl > cpl)
1395 goto exception;
1396 } else {
1397 /* nonconforming */
1398 if (rpl > cpl || dpl != cpl)
1399 goto exception;
1400 }
1401 /* CS(RPL) <- CPL */
1402 selector = (selector & 0xfffc) | cpl;
6aa8b732 1403 break;
dde7e6d1
AK		 1404 case VCPU_SREG_TR:
1405 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1406 goto exception;
1407 break;
1408 case VCPU_SREG_LDTR:
1409 if (seg_desc.s || seg_desc.type != 2)
1410 goto exception;
1411 break;
1412 default: /* DS, ES, FS, or GS */
4e62417b 1413 /*
dde7e6d1
AK		 1414 * segment is not a data or readable code segment or
1415 * ((segment is a data or nonconforming code segment)
1416 * and (both RPL and CPL > DPL))
4e62417b 1417 */
dde7e6d1
AK		 1418 if ((seg_desc.type & 0xa) == 0x8 ||
1419 (((seg_desc.type & 0xc) != 0xc) &&
1420 (rpl > dpl && cpl > dpl)))
1421 goto exception;
6aa8b732 1422 break;
dde7e6d1
AK		 1423 }
1424
1425 if (seg_desc.s) {
1426 /* mark segment as accessed */
1427 seg_desc.type |= 1;
7b105ca2 1428 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1429 if (ret != X86EMUL_CONTINUE)
1430 return ret;
1431 }
1432load:
7b105ca2 1433 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1434 return X86EMUL_CONTINUE;
1435exception:
1436 emulate_exception(ctxt, err_vec, err_code, true);
1437 return X86EMUL_PROPAGATE_FAULT;
1438}
1439
31be40b3
WY		 1440static void write_register_operand(struct operand *op)
1441{
1442 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1443 switch (op->bytes) {
1444 case 1:
1445 *(u8 *)op->addr.reg = (u8)op->val;
1446 break;
1447 case 2:
1448 *(u16 *)op->addr.reg = (u16)op->val;
1449 break;
1450 case 4:
1451 *op->addr.reg = (u32)op->val;
1452 break; /* 64b: zero-extend */
1453 case 8:
1454 *op->addr.reg = op->val;
1455 break;
1456 }
1457}
1458
adddcecf 1459static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1460{
1461 int rc;
dde7e6d1 1462
9dac77fa 1463 switch (ctxt->dst.type) {
dde7e6d1 1464 case OP_REG:
9dac77fa 1465 write_register_operand(&ctxt->dst);
6aa8b732 1466 break;
dde7e6d1 1467 case OP_MEM:
9dac77fa 1468 if (ctxt->lock_prefix)
3ca3ac4d 1469 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1470 ctxt->dst.addr.mem,
1471 &ctxt->dst.orig_val,
1472 &ctxt->dst.val,
1473 ctxt->dst.bytes);
341de7e3 1474 else
3ca3ac4d 1475 rc = segmented_write(ctxt,
9dac77fa
AK		 1476 ctxt->dst.addr.mem,
1477 &ctxt->dst.val,
1478 ctxt->dst.bytes);
dde7e6d1
AK		 1479 if (rc != X86EMUL_CONTINUE)
1480 return rc;
a682e354 1481 break;
1253791d 1482 case OP_XMM:
9dac77fa 1483 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1484 break;
cbe2c9d3
AK		 1485 case OP_MM:
1486 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1487 break;
dde7e6d1
AK		 1488 case OP_NONE:
1489 /* no writeback */
414e6277 1490 break;
dde7e6d1 1491 default:
414e6277 1492 break;
6aa8b732 1493 }
dde7e6d1
AK		 1494 return X86EMUL_CONTINUE;
1495}
6aa8b732 1496
4487b3b4 1497static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1498{
4179bb02 1499 struct segmented_address addr;
0dc8d10f 1500
9dac77fa
AK		 1501 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1502 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1503 addr.seg = VCPU_SREG_SS;
1504
1505 /* Disable writeback. */
9dac77fa
AK		 1506 ctxt->dst.type = OP_NONE;
1507 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1508}
69f55cb1 1509
dde7e6d1 1510static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1511 void *dest, int len)
1512{
dde7e6d1 1513 int rc;
90de84f5 1514 struct segmented_address addr;
8b4caf66 1515
9dac77fa 1516 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1517 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1518 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1519 if (rc != X86EMUL_CONTINUE)
1520 return rc;
1521
9dac77fa 1522 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1523 return rc;
8b4caf66
LV		 1524}
1525
c54fe504
TY		 1526static int em_pop(struct x86_emulate_ctxt *ctxt)
1527{
9dac77fa 1528 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1529}
1530
dde7e6d1 1531static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1532 void *dest, int len)
9de41573
GN		 1533{
1534 int rc;
dde7e6d1
AK		 1535 unsigned long val, change_mask;
1536 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1537 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1538
3b9be3bf 1539 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1540 if (rc != X86EMUL_CONTINUE)
1541 return rc;
9de41573 1542
dde7e6d1
AK		 1543 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1544 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1545
dde7e6d1
AK		 1546 switch(ctxt->mode) {
1547 case X86EMUL_MODE_PROT64:
1548 case X86EMUL_MODE_PROT32:
1549 case X86EMUL_MODE_PROT16:
1550 if (cpl == 0)
1551 change_mask |= EFLG_IOPL;
1552 if (cpl <= iopl)
1553 change_mask |= EFLG_IF;
1554 break;
1555 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1556 if (iopl < 3)
1557 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1558 change_mask |= EFLG_IF;
1559 break;
1560 default: /* real mode */
1561 change_mask |= (EFLG_IOPL | EFLG_IF);
1562 break;
9de41573 1563 }
dde7e6d1
AK		 1564
1565 *(unsigned long *)dest =
1566 (ctxt->eflags & ~change_mask) | (val & change_mask);
1567
1568 return rc;
9de41573
GN		 1569}
1570
62aaa2f0
TY		 1571static int em_popf(struct x86_emulate_ctxt *ctxt)
1572{
9dac77fa
AK		 1573 ctxt->dst.type = OP_REG;
1574 ctxt->dst.addr.reg = &ctxt->eflags;
1575 ctxt->dst.bytes = ctxt->op_bytes;
1576 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1577}
1578
f47cfa31
AK		 1579static int em_leave(struct x86_emulate_ctxt *ctxt)
1580{
1581 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1582 stack_mask(ctxt));
1583 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1584}
1585
1cd196ea 1586static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1587{
1cd196ea
AK		 1588 int seg = ctxt->src2.val;
1589
9dac77fa 1590 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1591
4487b3b4 1592 return em_push(ctxt);
7b262e90
GN		 1593}
1594
1cd196ea 1595static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1596{
1cd196ea 1597 int seg = ctxt->src2.val;
dde7e6d1
AK		 1598 unsigned long selector;
1599 int rc;
38ba30ba 1600
9dac77fa 1601 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1602 if (rc != X86EMUL_CONTINUE)
1603 return rc;
1604
7b105ca2 1605 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1606 return rc;
38ba30ba
GN		 1607}
1608
b96a7fad 1609static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1610{
9dac77fa 1611 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1612 int rc = X86EMUL_CONTINUE;
1613 int reg = VCPU_REGS_RAX;
38ba30ba 1614
dde7e6d1
AK		 1615 while (reg <= VCPU_REGS_RDI) {
1616 (reg == VCPU_REGS_RSP) ?
9dac77fa 1617 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1618
4487b3b4 1619 rc = em_push(ctxt);
dde7e6d1
AK		 1620 if (rc != X86EMUL_CONTINUE)
1621 return rc;
38ba30ba 1622
dde7e6d1 1623 ++reg;
38ba30ba 1624 }
38ba30ba 1625
dde7e6d1 1626 return rc;
38ba30ba
GN		 1627}
1628
62aaa2f0
TY		 1629static int em_pushf(struct x86_emulate_ctxt *ctxt)
1630{
9dac77fa 1631 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1632 return em_push(ctxt);
1633}
1634
b96a7fad 1635static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1636{
dde7e6d1
AK		 1637 int rc = X86EMUL_CONTINUE;
1638 int reg = VCPU_REGS_RDI;
38ba30ba 1639
dde7e6d1
AK		 1640 while (reg >= VCPU_REGS_RAX) {
1641 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1642 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1643 ctxt->op_bytes);
dde7e6d1
AK		 1644 --reg;
1645 }
38ba30ba 1646
9dac77fa 1647 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1648 if (rc != X86EMUL_CONTINUE)
1649 break;
1650 --reg;
38ba30ba 1651 }
dde7e6d1 1652 return rc;
38ba30ba
GN		 1653}
1654
7b105ca2 1655int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1656{
7b105ca2 1657 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1658 int rc;
6e154e56
MG		 1659 struct desc_ptr dt;
1660 gva_t cs_addr;
1661 gva_t eip_addr;
1662 u16 cs, eip;
6e154e56
MG		 1663
1664 /* TODO: Add limit checks */
9dac77fa 1665 ctxt->src.val = ctxt->eflags;
4487b3b4 1666 rc = em_push(ctxt);
5c56e1cf
AK		 1667 if (rc != X86EMUL_CONTINUE)
1668 return rc;
6e154e56
MG		 1669
1670 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1671
9dac77fa 1672 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1673 rc = em_push(ctxt);
5c56e1cf
AK		 1674 if (rc != X86EMUL_CONTINUE)
1675 return rc;
6e154e56 1676
9dac77fa 1677 ctxt->src.val = ctxt->_eip;
4487b3b4 1678 rc = em_push(ctxt);
5c56e1cf
AK		 1679 if (rc != X86EMUL_CONTINUE)
1680 return rc;
1681
4bff1e86 1682 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1683
1684 eip_addr = dt.address + (irq << 2);
1685 cs_addr = dt.address + (irq << 2) + 2;
1686
0f65dd70 1687 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1688 if (rc != X86EMUL_CONTINUE)
1689 return rc;
1690
0f65dd70 1691 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1692 if (rc != X86EMUL_CONTINUE)
1693 return rc;
1694
7b105ca2 1695 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1696 if (rc != X86EMUL_CONTINUE)
1697 return rc;
1698
9dac77fa 1699 ctxt->_eip = eip;
6e154e56
MG		 1700
1701 return rc;
1702}
1703
7b105ca2 1704static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1705{
1706 switch(ctxt->mode) {
1707 case X86EMUL_MODE_REAL:
7b105ca2 1708 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1709 case X86EMUL_MODE_VM86:
1710 case X86EMUL_MODE_PROT16:
1711 case X86EMUL_MODE_PROT32:
1712 case X86EMUL_MODE_PROT64:
1713 default:
1714 /* Protected mode interrupts unimplemented yet */
1715 return X86EMUL_UNHANDLEABLE;
1716 }
1717}
1718
7b105ca2 1719static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1720{
dde7e6d1
AK		 1721 int rc = X86EMUL_CONTINUE;
1722 unsigned long temp_eip = 0;
1723 unsigned long temp_eflags = 0;
1724 unsigned long cs = 0;
1725 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1726 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1727 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1728 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1729
dde7e6d1 1730 /* TODO: Add stack limit check */
38ba30ba 1731
9dac77fa 1732 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1733
dde7e6d1
AK		 1734 if (rc != X86EMUL_CONTINUE)
1735 return rc;
38ba30ba 1736
35d3d4a1
AK		 1737 if (temp_eip & ~0xffff)
1738 return emulate_gp(ctxt, 0);
38ba30ba 1739
9dac77fa 1740 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1741
dde7e6d1
AK		 1742 if (rc != X86EMUL_CONTINUE)
1743 return rc;
38ba30ba 1744
9dac77fa 1745 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1746
dde7e6d1
AK		 1747 if (rc != X86EMUL_CONTINUE)
1748 return rc;
38ba30ba 1749
7b105ca2 1750 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1751
dde7e6d1
AK		 1752 if (rc != X86EMUL_CONTINUE)
1753 return rc;
38ba30ba 1754
9dac77fa 1755 ctxt->_eip = temp_eip;
38ba30ba 1756
38ba30ba 1757
9dac77fa 1758 if (ctxt->op_bytes == 4)
dde7e6d1 1759 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1760 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1761 ctxt->eflags &= ~0xffff;
1762 ctxt->eflags |= temp_eflags;
38ba30ba 1763 }
dde7e6d1
AK		 1764
1765 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1766 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1767
1768 return rc;
38ba30ba
GN		 1769}
1770
e01991e7 1771static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1772{
dde7e6d1
AK		 1773 switch(ctxt->mode) {
1774 case X86EMUL_MODE_REAL:
7b105ca2 1775 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1776 case X86EMUL_MODE_VM86:
1777 case X86EMUL_MODE_PROT16:
1778 case X86EMUL_MODE_PROT32:
1779 case X86EMUL_MODE_PROT64:
c37eda13 1780 default:
dde7e6d1
AK		 1781 /* iret from protected mode unimplemented yet */
1782 return X86EMUL_UNHANDLEABLE;
c37eda13 1783 }
c37eda13
WY		 1784}
1785
d2f62766
TY		 1786static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1787{
d2f62766
TY		 1788 int rc;
1789 unsigned short sel;
1790
9dac77fa 1791 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1792
7b105ca2 1793 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1794 if (rc != X86EMUL_CONTINUE)
1795 return rc;
1796
9dac77fa
AK		 1797 ctxt->_eip = 0;
1798 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1799 return X86EMUL_CONTINUE;
1800}
1801
51187683 1802static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1803{
9dac77fa 1804 switch (ctxt->modrm_reg) {
8cdbd2c9 1805 case 0: /* rol */
a31b9cea 1806 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1807 break;
1808 case 1: /* ror */
a31b9cea 1809 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1810 break;
1811 case 2: /* rcl */
a31b9cea 1812 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1813 break;
1814 case 3: /* rcr */
a31b9cea 1815 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1816 break;
1817 case 4: /* sal/shl */
1818 case 6: /* sal/shl */
a31b9cea 1819 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1820 break;
1821 case 5: /* shr */
a31b9cea 1822 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1823 break;
1824 case 7: /* sar */
a31b9cea 1825 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1826 break;
1827 }
51187683 1828 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1829}
1830
3329ece1
AK		 1831static int em_not(struct x86_emulate_ctxt *ctxt)
1832{
1833 ctxt->dst.val = ~ctxt->dst.val;
1834 return X86EMUL_CONTINUE;
1835}
1836
1837static int em_neg(struct x86_emulate_ctxt *ctxt)
1838{
1839 emulate_1op(ctxt, "neg");
1840 return X86EMUL_CONTINUE;
1841}
1842
1843static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1844{
1845 u8 ex = 0;
1846
1847 emulate_1op_rax_rdx(ctxt, "mul", ex);
1848 return X86EMUL_CONTINUE;
1849}
1850
1851static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1852{
1853 u8 ex = 0;
1854
1855 emulate_1op_rax_rdx(ctxt, "imul", ex);
1856 return X86EMUL_CONTINUE;
1857}
1858
1859static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1860{
34d1f490 1861 u8 de = 0;
8cdbd2c9 1862
3329ece1
AK		 1863 emulate_1op_rax_rdx(ctxt, "div", de);
1864 if (de)
1865 return emulate_de(ctxt);
1866 return X86EMUL_CONTINUE;
1867}
1868
1869static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1870{
1871 u8 de = 0;
1872
1873 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1874 if (de)
1875 return emulate_de(ctxt);
8c5eee30 1876 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1877}
1878
51187683 1879static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1880{
4179bb02 1881 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1882
9dac77fa 1883 switch (ctxt->modrm_reg) {
8cdbd2c9 1884 case 0: /* inc */
d1eef45d 1885 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1886 break;
1887 case 1: /* dec */
d1eef45d 1888 emulate_1op(ctxt, "dec");
8cdbd2c9 1889 break;
d19292e4
MG		 1890 case 2: /* call near abs */ {
1891 long int old_eip;
9dac77fa
AK		 1892 old_eip = ctxt->_eip;
1893 ctxt->_eip = ctxt->src.val;
1894 ctxt->src.val = old_eip;
4487b3b4 1895 rc = em_push(ctxt);
d19292e4
MG		 1896 break;
1897 }
8cdbd2c9 1898 case 4: /* jmp abs */
9dac77fa 1899 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1900 break;
d2f62766
TY		 1901 case 5: /* jmp far */
1902 rc = em_jmp_far(ctxt);
1903 break;
8cdbd2c9 1904 case 6: /* push */
4487b3b4 1905 rc = em_push(ctxt);
8cdbd2c9 1906 break;
8cdbd2c9 1907 }
4179bb02 1908 return rc;
8cdbd2c9
LV		 1909}
1910
e0dac408 1911static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1912{
9dac77fa 1913 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1914
9dac77fa
AK		 1915 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1916 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1917 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1918 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1919 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1920 } else {
9dac77fa
AK		 1921 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1922 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1923
05f086f8 1924 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1925 }
1b30eaa8 1926 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1927}
1928
ebda02c2
TY		 1929static int em_ret(struct x86_emulate_ctxt *ctxt)
1930{
9dac77fa
AK		 1931 ctxt->dst.type = OP_REG;
1932 ctxt->dst.addr.reg = &ctxt->_eip;
1933 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1934 return em_pop(ctxt);
1935}
1936
e01991e7 1937static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1938{
a77ab5ea
AK		 1939 int rc;
1940 unsigned long cs;
1941
9dac77fa 1942 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1943 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1944 return rc;
9dac77fa
AK		 1945 if (ctxt->op_bytes == 4)
1946 ctxt->_eip = (u32)ctxt->_eip;
1947 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1948 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1949 return rc;
7b105ca2 1950 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1951 return rc;
1952}
1953
e940b5c2
TY		 1954static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1955{
1956 /* Save real source value, then compare EAX against destination. */
1957 ctxt->src.orig_val = ctxt->src.val;
1958 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1959 emulate_2op_SrcV(ctxt, "cmp");
1960
1961 if (ctxt->eflags & EFLG_ZF) {
1962 /* Success: write back to memory. */
1963 ctxt->dst.val = ctxt->src.orig_val;
1964 } else {
1965 /* Failure: write the value we saw to EAX. */
1966 ctxt->dst.type = OP_REG;
1967 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1968 }
1969 return X86EMUL_CONTINUE;
1970}
1971
d4b4325f 1972static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1973{
d4b4325f 1974 int seg = ctxt->src2.val;
09b5f4d3
WY		 1975 unsigned short sel;
1976 int rc;
1977
9dac77fa 1978 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1979
7b105ca2 1980 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1981 if (rc != X86EMUL_CONTINUE)
1982 return rc;
1983
9dac77fa 1984 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1985 return rc;
1986}
1987
7b105ca2 1988static void
e66bb2cc 1989setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1990 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1991{
1aa36616
AK		 1992 u16 selector;
1993
79168fd1 1994 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1995 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1996 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1997
1998 cs->l = 0; /* will be adjusted later */
79168fd1 1999 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2000 cs->g = 1; /* 4kb granularity */
79168fd1 2001 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2002 cs->type = 0x0b; /* Read, Execute, Accessed */
2003 cs->s = 1;
2004 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2005 cs->p = 1;
2006 cs->d = 1;
e66bb2cc 2007
79168fd1
GN		 2008 set_desc_base(ss, 0); /* flat segment */
2009 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2010 ss->g = 1; /* 4kb granularity */
2011 ss->s = 1;
2012 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2013 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2014 ss->dpl = 0;
79168fd1 2015 ss->p = 1;
e66bb2cc
AP		 2016}
2017
1a18a69b
AK		 2018static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2019{
2020 u32 eax, ebx, ecx, edx;
2021
2022 eax = ecx = 0;
0017f93a
AK		 2023 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2024 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2025 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2026 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2027}
2028
c2226fc9
SB		 2029static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2030{
2031 struct x86_emulate_ops *ops = ctxt->ops;
2032 u32 eax, ebx, ecx, edx;
2033
2034 /*
2035 * syscall should always be enabled in longmode - so only become
2036 * vendor specific (cpuid) if other modes are active...
2037 */
2038 if (ctxt->mode == X86EMUL_MODE_PROT64)
2039 return true;
2040
2041 eax = 0x00000000;
2042 ecx = 0x00000000;
0017f93a
AK		 2043 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2044 /*
2045 * Intel ("GenuineIntel")
2046 * remark: Intel CPUs only support "syscall" in 64bit
2047 * longmode. Also an 64bit guest with a
2048 * 32bit compat-app running will #UD !! While this
2049 * behaviour can be fixed (by emulating) into AMD
2050 * response - CPUs of AMD can't behave like Intel.
2051 */
2052 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2053 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2054 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2055 return false;
2056
2057 /* AMD ("AuthenticAMD") */
2058 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2059 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2060 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2061 return true;
2062
2063 /* AMD ("AMDisbetter!") */
2064 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2065 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2066 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2067 return true;
c2226fc9
SB		 2068
2069 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2070 return false;
2071}
2072
e01991e7 2073static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2074{
7b105ca2 2075 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2076 struct desc_struct cs, ss;
e66bb2cc 2077 u64 msr_data;
79168fd1 2078 u16 cs_sel, ss_sel;
c2ad2bb3 2079 u64 efer = 0;
e66bb2cc
AP		 2080
2081 /* syscall is not available in real mode */
2e901c4c 2082 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2083 ctxt->mode == X86EMUL_MODE_VM86)
2084 return emulate_ud(ctxt);
e66bb2cc 2085
c2226fc9
SB		 2086 if (!(em_syscall_is_enabled(ctxt)))
2087 return emulate_ud(ctxt);
2088
c2ad2bb3 2089 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2090 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2091
c2226fc9
SB		 2092 if (!(efer & EFER_SCE))
2093 return emulate_ud(ctxt);
2094
717746e3 2095 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2096 msr_data >>= 32;
79168fd1
GN		 2097 cs_sel = (u16)(msr_data & 0xfffc);
2098 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2099
c2ad2bb3 2100 if (efer & EFER_LMA) {
79168fd1 2101 cs.d = 0;
e66bb2cc
AP		 2102 cs.l = 1;
2103 }
1aa36616
AK		 2104 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2105 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2106
9dac77fa 2107 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2108 if (efer & EFER_LMA) {
e66bb2cc 2109#ifdef CONFIG_X86_64
9dac77fa 2110 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2111
717746e3 2112 ops->get_msr(ctxt,
3fb1b5db
GN		 2113 ctxt->mode == X86EMUL_MODE_PROT64 ?
2114 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2115 ctxt->_eip = msr_data;
e66bb2cc 2116
717746e3 2117 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2118 ctxt->eflags &= ~(msr_data | EFLG_RF);
2119#endif
2120 } else {
2121 /* legacy mode */
717746e3 2122 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2123 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2124
2125 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2126 }
2127
e54cfa97 2128 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2129}
2130
e01991e7 2131static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2132{
7b105ca2 2133 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2134 struct desc_struct cs, ss;
8c604352 2135 u64 msr_data;
79168fd1 2136 u16 cs_sel, ss_sel;
c2ad2bb3 2137 u64 efer = 0;
8c604352 2138
7b105ca2 2139 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2140 /* inject #GP if in real mode */
35d3d4a1
AK		 2141 if (ctxt->mode == X86EMUL_MODE_REAL)
2142 return emulate_gp(ctxt, 0);
8c604352 2143
1a18a69b
AK		 2144 /*
2145 * Not recognized on AMD in compat mode (but is recognized in legacy
2146 * mode).
2147 */
2148 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2149 && !vendor_intel(ctxt))
2150 return emulate_ud(ctxt);
2151
8c604352
AP		 2152 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2153 * Therefore, we inject an #UD.
2154 */
35d3d4a1
AK		 2155 if (ctxt->mode == X86EMUL_MODE_PROT64)
2156 return emulate_ud(ctxt);
8c604352 2157
7b105ca2 2158 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2159
717746e3 2160 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2161 switch (ctxt->mode) {
2162 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2163 if ((msr_data & 0xfffc) == 0x0)
2164 return emulate_gp(ctxt, 0);
8c604352
AP		 2165 break;
2166 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2167 if (msr_data == 0x0)
2168 return emulate_gp(ctxt, 0);
8c604352
AP		 2169 break;
2170 }
2171
2172 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2173 cs_sel = (u16)msr_data;
2174 cs_sel &= ~SELECTOR_RPL_MASK;
2175 ss_sel = cs_sel + 8;
2176 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2177 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2178 cs.d = 0;
8c604352
AP		 2179 cs.l = 1;
2180 }
2181
1aa36616
AK		 2182 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2183 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2184
717746e3 2185 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2186 ctxt->_eip = msr_data;
8c604352 2187
717746e3 2188 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2189 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2190
e54cfa97 2191 return X86EMUL_CONTINUE;
8c604352
AP		 2192}
2193
e01991e7 2194static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2195{
7b105ca2 2196 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2197 struct desc_struct cs, ss;
4668f050
AP		 2198 u64 msr_data;
2199 int usermode;
1249b96e 2200 u16 cs_sel = 0, ss_sel = 0;
4668f050 2201
a0044755
GN		 2202 /* inject #GP if in real mode or Virtual 8086 mode */
2203 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2204 ctxt->mode == X86EMUL_MODE_VM86)
2205 return emulate_gp(ctxt, 0);
4668f050 2206
7b105ca2 2207 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2208
9dac77fa 2209 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2210 usermode = X86EMUL_MODE_PROT64;
2211 else
2212 usermode = X86EMUL_MODE_PROT32;
2213
2214 cs.dpl = 3;
2215 ss.dpl = 3;
717746e3 2216 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2217 switch (usermode) {
2218 case X86EMUL_MODE_PROT32:
79168fd1 2219 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2220 if ((msr_data & 0xfffc) == 0x0)
2221 return emulate_gp(ctxt, 0);
79168fd1 2222 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2223 break;
2224 case X86EMUL_MODE_PROT64:
79168fd1 2225 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2226 if (msr_data == 0x0)
2227 return emulate_gp(ctxt, 0);
79168fd1
GN		 2228 ss_sel = cs_sel + 8;
2229 cs.d = 0;
4668f050
AP		 2230 cs.l = 1;
2231 break;
2232 }
79168fd1
GN		 2233 cs_sel |= SELECTOR_RPL_MASK;
2234 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2235
1aa36616
AK		 2236 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2237 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2238
9dac77fa
AK		 2239 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2240 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2241
e54cfa97 2242 return X86EMUL_CONTINUE;
4668f050
AP		 2243}
2244
7b105ca2 2245static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2246{
2247 int iopl;
2248 if (ctxt->mode == X86EMUL_MODE_REAL)
2249 return false;
2250 if (ctxt->mode == X86EMUL_MODE_VM86)
2251 return true;
2252 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2253 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2254}
2255
2256static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2257 u16 port, u16 len)
2258{
7b105ca2 2259 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2260 struct desc_struct tr_seg;
5601d05b 2261 u32 base3;
f850e2e6 2262 int r;
1aa36616 2263 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2264 unsigned mask = (1 << len) - 1;
5601d05b 2265 unsigned long base;
f850e2e6 2266
1aa36616 2267 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2268 if (!tr_seg.p)
f850e2e6 2269 return false;
79168fd1 2270 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2271 return false;
5601d05b
GN		 2272 base = get_desc_base(&tr_seg);
2273#ifdef CONFIG_X86_64
2274 base |= ((u64)base3) << 32;
2275#endif
0f65dd70 2276 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2277 if (r != X86EMUL_CONTINUE)
2278 return false;
79168fd1 2279 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2280 return false;
0f65dd70 2281 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2282 if (r != X86EMUL_CONTINUE)
2283 return false;
2284 if ((perm >> bit_idx) & mask)
2285 return false;
2286 return true;
2287}
2288
2289static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2290 u16 port, u16 len)
2291{
4fc40f07
GN		 2292 if (ctxt->perm_ok)
2293 return true;
2294
7b105ca2
TY		 2295 if (emulator_bad_iopl(ctxt))
2296 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2297 return false;
4fc40f07
GN		 2298
2299 ctxt->perm_ok = true;
2300
f850e2e6
GN		 2301 return true;
2302}
2303
38ba30ba 2304static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2305 struct tss_segment_16 *tss)
2306{
9dac77fa 2307 tss->ip = ctxt->_eip;
38ba30ba 2308 tss->flag = ctxt->eflags;
9dac77fa
AK		 2309 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2310 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2311 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2312 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2313 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2314 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2315 tss->si = ctxt->regs[VCPU_REGS_RSI];
2316 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2317
1aa36616
AK		 2318 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2319 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2320 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2321 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2322 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2323}
2324
2325static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2326 struct tss_segment_16 *tss)
2327{
38ba30ba
GN		 2328 int ret;
2329
9dac77fa 2330 ctxt->_eip = tss->ip;
38ba30ba 2331 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2332 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2333 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2334 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2335 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2336 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2337 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2338 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2339 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2340
2341 /*
2342 * SDM says that segment selectors are loaded before segment
2343 * descriptors
2344 */
1aa36616
AK		 2345 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2346 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2347 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2348 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2349 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2350
2351 /*
2352 * Now load segment descriptors. If fault happenes at this stage
2353 * it is handled in a context of new task
2354 */
7b105ca2 2355 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2356 if (ret != X86EMUL_CONTINUE)
2357 return ret;
7b105ca2 2358 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2359 if (ret != X86EMUL_CONTINUE)
2360 return ret;
7b105ca2 2361 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2362 if (ret != X86EMUL_CONTINUE)
2363 return ret;
7b105ca2 2364 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2365 if (ret != X86EMUL_CONTINUE)
2366 return ret;
7b105ca2 2367 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2368 if (ret != X86EMUL_CONTINUE)
2369 return ret;
2370
2371 return X86EMUL_CONTINUE;
2372}
2373
2374static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2375 u16 tss_selector, u16 old_tss_sel,
2376 ulong old_tss_base, struct desc_struct *new_desc)
2377{
7b105ca2 2378 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2379 struct tss_segment_16 tss_seg;
2380 int ret;
bcc55cba 2381 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2382
0f65dd70 2383 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2384 &ctxt->exception);
db297e3d 2385 if (ret != X86EMUL_CONTINUE)
38ba30ba 2386 /* FIXME: need to provide precise fault address */
38ba30ba 2387 return ret;
38ba30ba 2388
7b105ca2 2389 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2390
0f65dd70 2391 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2392 &ctxt->exception);
db297e3d 2393 if (ret != X86EMUL_CONTINUE)
38ba30ba 2394 /* FIXME: need to provide precise fault address */
38ba30ba 2395 return ret;
38ba30ba 2396
0f65dd70 2397 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2398 &ctxt->exception);
db297e3d 2399 if (ret != X86EMUL_CONTINUE)
38ba30ba 2400 /* FIXME: need to provide precise fault address */
38ba30ba 2401 return ret;
38ba30ba
GN		 2402
2403 if (old_tss_sel != 0xffff) {
2404 tss_seg.prev_task_link = old_tss_sel;
2405
0f65dd70 2406 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2407 &tss_seg.prev_task_link,
2408 sizeof tss_seg.prev_task_link,
0f65dd70 2409 &ctxt->exception);
db297e3d 2410 if (ret != X86EMUL_CONTINUE)
38ba30ba 2411 /* FIXME: need to provide precise fault address */
38ba30ba 2412 return ret;
38ba30ba
GN		 2413 }
2414
7b105ca2 2415 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2416}
2417
2418static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2419 struct tss_segment_32 *tss)
2420{
7b105ca2 2421 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2422 tss->eip = ctxt->_eip;
38ba30ba 2423 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2424 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2425 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2426 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2427 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2428 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2429 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2430 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2431 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2432
1aa36616
AK		 2433 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2434 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2435 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2436 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2437 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2438 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2439 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2440}
2441
2442static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2443 struct tss_segment_32 *tss)
2444{
38ba30ba
GN		 2445 int ret;
2446
7b105ca2 2447 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2448 return emulate_gp(ctxt, 0);
9dac77fa 2449 ctxt->_eip = tss->eip;
38ba30ba 2450 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2451
2452 /* General purpose registers */
9dac77fa
AK		 2453 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2454 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2455 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2456 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2457 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2458 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2459 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2460 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2461
2462 /*
2463 * SDM says that segment selectors are loaded before segment
2464 * descriptors
2465 */
1aa36616
AK		 2466 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2467 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2468 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2469 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2470 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2471 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2472 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2473
4cee4798
KW		 2474 /*
2475 * If we're switching between Protected Mode and VM86, we need to make
2476 * sure to update the mode before loading the segment descriptors so
2477 * that the selectors are interpreted correctly.
2478 *
2479 * Need to get rflags to the vcpu struct immediately because it
2480 * influences the CPL which is checked at least when loading the segment
2481 * descriptors and when pushing an error code to the new kernel stack.
2482 *
2483 * TODO Introduce a separate ctxt->ops->set_cpl callback
2484 */
2485 if (ctxt->eflags & X86_EFLAGS_VM)
2486 ctxt->mode = X86EMUL_MODE_VM86;
2487 else
2488 ctxt->mode = X86EMUL_MODE_PROT32;
2489
2490 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2491
38ba30ba
GN		 2492 /*
2493 * Now load segment descriptors. If fault happenes at this stage
2494 * it is handled in a context of new task
2495 */
7b105ca2 2496 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2497 if (ret != X86EMUL_CONTINUE)
2498 return ret;
7b105ca2 2499 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2500 if (ret != X86EMUL_CONTINUE)
2501 return ret;
7b105ca2 2502 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2503 if (ret != X86EMUL_CONTINUE)
2504 return ret;
7b105ca2 2505 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2506 if (ret != X86EMUL_CONTINUE)
2507 return ret;
7b105ca2 2508 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2509 if (ret != X86EMUL_CONTINUE)
2510 return ret;
7b105ca2 2511 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2512 if (ret != X86EMUL_CONTINUE)
2513 return ret;
7b105ca2 2514 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2515 if (ret != X86EMUL_CONTINUE)
2516 return ret;
2517
2518 return X86EMUL_CONTINUE;
2519}
2520
2521static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2522 u16 tss_selector, u16 old_tss_sel,
2523 ulong old_tss_base, struct desc_struct *new_desc)
2524{
7b105ca2 2525 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2526 struct tss_segment_32 tss_seg;
2527 int ret;
bcc55cba 2528 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2529
0f65dd70 2530 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2531 &ctxt->exception);
db297e3d 2532 if (ret != X86EMUL_CONTINUE)
38ba30ba 2533 /* FIXME: need to provide precise fault address */
38ba30ba 2534 return ret;
38ba30ba 2535
7b105ca2 2536 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2537
0f65dd70 2538 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2539 &ctxt->exception);
db297e3d 2540 if (ret != X86EMUL_CONTINUE)
38ba30ba 2541 /* FIXME: need to provide precise fault address */
38ba30ba 2542 return ret;
38ba30ba 2543
0f65dd70 2544 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2545 &ctxt->exception);
db297e3d 2546 if (ret != X86EMUL_CONTINUE)
38ba30ba 2547 /* FIXME: need to provide precise fault address */
38ba30ba 2548 return ret;
38ba30ba
GN		 2549
2550 if (old_tss_sel != 0xffff) {
2551 tss_seg.prev_task_link = old_tss_sel;
2552
0f65dd70 2553 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2554 &tss_seg.prev_task_link,
2555 sizeof tss_seg.prev_task_link,
0f65dd70 2556 &ctxt->exception);
db297e3d 2557 if (ret != X86EMUL_CONTINUE)
38ba30ba 2558 /* FIXME: need to provide precise fault address */
38ba30ba 2559 return ret;
38ba30ba
GN		 2560 }
2561
7b105ca2 2562 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2563}
2564
2565static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2566 u16 tss_selector, int idt_index, int reason,
e269fb21 2567 bool has_error_code, u32 error_code)
38ba30ba 2568{
7b105ca2 2569 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2570 struct desc_struct curr_tss_desc, next_tss_desc;
2571 int ret;
1aa36616 2572 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2573 ulong old_tss_base =
4bff1e86 2574 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2575 u32 desc_limit;
38ba30ba
GN		 2576
2577 /* FIXME: old_tss_base == ~0 ? */
2578
7b105ca2 2579 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
7b105ca2 2582 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2583 if (ret != X86EMUL_CONTINUE)
2584 return ret;
2585
2586 /* FIXME: check that next_tss_desc is tss */
2587
7f3d35fd
KW		 2588 /*
2589 * Check privileges. The three cases are task switch caused by...
2590 *
2591 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2592 * 2. Exception/IRQ/iret: No check is performed
2593 * 3. jmp/call to TSS: Check agains DPL of the TSS
2594 */
2595 if (reason == TASK_SWITCH_GATE) {
2596 if (idt_index != -1) {
2597 /* Software interrupts */
2598 struct desc_struct task_gate_desc;
2599 int dpl;
2600
2601 ret = read_interrupt_descriptor(ctxt, idt_index,
2602 &task_gate_desc);
2603 if (ret != X86EMUL_CONTINUE)
2604 return ret;
2605
2606 dpl = task_gate_desc.dpl;
2607 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2608 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2609 }
2610 } else if (reason != TASK_SWITCH_IRET) {
2611 int dpl = next_tss_desc.dpl;
2612 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2613 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2614 }
2615
7f3d35fd 2616
ceffb459
GN		 2617 desc_limit = desc_limit_scaled(&next_tss_desc);
2618 if (!next_tss_desc.p ||
2619 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2620 desc_limit < 0x2b)) {
54b8486f 2621 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2622 return X86EMUL_PROPAGATE_FAULT;
2623 }
2624
2625 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2626 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2627 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2628 }
2629
2630 if (reason == TASK_SWITCH_IRET)
2631 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2632
2633 /* set back link to prev task only if NT bit is set in eflags
2634 note that old_tss_sel is not used afetr this point */
2635 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2636 old_tss_sel = 0xffff;
2637
2638 if (next_tss_desc.type & 8)
7b105ca2 2639 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2640 old_tss_base, &next_tss_desc);
2641 else
7b105ca2 2642 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2643 old_tss_base, &next_tss_desc);
0760d448
JK		 2644 if (ret != X86EMUL_CONTINUE)
2645 return ret;
38ba30ba
GN		 2646
2647 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2648 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2649
2650 if (reason != TASK_SWITCH_IRET) {
2651 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2652 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2653 }
2654
717746e3 2655 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2656 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2657
e269fb21 2658 if (has_error_code) {
9dac77fa
AK		 2659 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2660 ctxt->lock_prefix = 0;
2661 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2662 ret = em_push(ctxt);
e269fb21
JK		 2663 }
2664
38ba30ba
GN		 2665 return ret;
2666}
2667
2668int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2669 u16 tss_selector, int idt_index, int reason,
e269fb21 2670 bool has_error_code, u32 error_code)
38ba30ba 2671{
38ba30ba
GN		 2672 int rc;
2673
9dac77fa
AK		 2674 ctxt->_eip = ctxt->eip;
2675 ctxt->dst.type = OP_NONE;
38ba30ba 2676
7f3d35fd 2677 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2678 has_error_code, error_code);
38ba30ba 2679
4179bb02 2680 if (rc == X86EMUL_CONTINUE)
9dac77fa 2681 ctxt->eip = ctxt->_eip;
38ba30ba 2682
a0c0ab2f 2683 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2684}
2685
90de84f5 2686static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2687 int reg, struct operand *op)
a682e354 2688{
a682e354
GN		 2689 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2690
9dac77fa
AK		 2691 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2692 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2693 op->addr.mem.seg = seg;
a682e354
GN		 2694}
2695
7af04fc0
AK		 2696static int em_das(struct x86_emulate_ctxt *ctxt)
2697{
7af04fc0
AK		 2698 u8 al, old_al;
2699 bool af, cf, old_cf;
2700
2701 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2702 al = ctxt->dst.val;
7af04fc0
AK		 2703
2704 old_al = al;
2705 old_cf = cf;
2706 cf = false;
2707 af = ctxt->eflags & X86_EFLAGS_AF;
2708 if ((al & 0x0f) > 9 || af) {
2709 al -= 6;
2710 cf = old_cf | (al >= 250);
2711 af = true;
2712 } else {
2713 af = false;
2714 }
2715 if (old_al > 0x99 || old_cf) {
2716 al -= 0x60;
2717 cf = true;
2718 }
2719
9dac77fa 2720 ctxt->dst.val = al;
7af04fc0 2721 /* Set PF, ZF, SF */
9dac77fa
AK		 2722 ctxt->src.type = OP_IMM;
2723 ctxt->src.val = 0;
2724 ctxt->src.bytes = 1;
a31b9cea 2725 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2726 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2727 if (cf)
2728 ctxt->eflags |= X86_EFLAGS_CF;
2729 if (af)
2730 ctxt->eflags |= X86_EFLAGS_AF;
2731 return X86EMUL_CONTINUE;
2732}
2733
d4ddafcd
TY		 2734static int em_call(struct x86_emulate_ctxt *ctxt)
2735{
2736 long rel = ctxt->src.val;
2737
2738 ctxt->src.val = (unsigned long)ctxt->_eip;
2739 jmp_rel(ctxt, rel);
2740 return em_push(ctxt);
2741}
2742
0ef753b8
AK		 2743static int em_call_far(struct x86_emulate_ctxt *ctxt)
2744{
0ef753b8
AK		 2745 u16 sel, old_cs;
2746 ulong old_eip;
2747 int rc;
2748
1aa36616 2749 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2750 old_eip = ctxt->_eip;
0ef753b8 2751
9dac77fa 2752 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2753 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2754 return X86EMUL_CONTINUE;
2755
9dac77fa
AK		 2756 ctxt->_eip = 0;
2757 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2758
9dac77fa 2759 ctxt->src.val = old_cs;
4487b3b4 2760 rc = em_push(ctxt);
0ef753b8
AK		 2761 if (rc != X86EMUL_CONTINUE)
2762 return rc;
2763
9dac77fa 2764 ctxt->src.val = old_eip;
4487b3b4 2765 return em_push(ctxt);
0ef753b8
AK		 2766}
2767
40ece7c7
AK		 2768static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2769{
40ece7c7
AK		 2770 int rc;
2771
9dac77fa
AK		 2772 ctxt->dst.type = OP_REG;
2773 ctxt->dst.addr.reg = &ctxt->_eip;
2774 ctxt->dst.bytes = ctxt->op_bytes;
2775 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2776 if (rc != X86EMUL_CONTINUE)
2777 return rc;
9dac77fa 2778 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2779 return X86EMUL_CONTINUE;
2780}
2781
d67fc27a
TY		 2782static int em_add(struct x86_emulate_ctxt *ctxt)
2783{
a31b9cea 2784 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2785 return X86EMUL_CONTINUE;
2786}
2787
2788static int em_or(struct x86_emulate_ctxt *ctxt)
2789{
a31b9cea 2790 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2791 return X86EMUL_CONTINUE;
2792}
2793
2794static int em_adc(struct x86_emulate_ctxt *ctxt)
2795{
a31b9cea 2796 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2797 return X86EMUL_CONTINUE;
2798}
2799
2800static int em_sbb(struct x86_emulate_ctxt *ctxt)
2801{
a31b9cea 2802 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2803 return X86EMUL_CONTINUE;
2804}
2805
2806static int em_and(struct x86_emulate_ctxt *ctxt)
2807{
a31b9cea 2808 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2809 return X86EMUL_CONTINUE;
2810}
2811
2812static int em_sub(struct x86_emulate_ctxt *ctxt)
2813{
a31b9cea 2814 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2815 return X86EMUL_CONTINUE;
2816}
2817
2818static int em_xor(struct x86_emulate_ctxt *ctxt)
2819{
a31b9cea 2820 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2821 return X86EMUL_CONTINUE;
2822}
2823
2824static int em_cmp(struct x86_emulate_ctxt *ctxt)
2825{
a31b9cea 2826 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2827 /* Disable writeback. */
9dac77fa 2828 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2829 return X86EMUL_CONTINUE;
2830}
2831
9f21ca59
TY		 2832static int em_test(struct x86_emulate_ctxt *ctxt)
2833{
a31b9cea 2834 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2835 /* Disable writeback. */
2836 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2837 return X86EMUL_CONTINUE;
2838}
2839
e4f973ae
TY		 2840static int em_xchg(struct x86_emulate_ctxt *ctxt)
2841{
e4f973ae 2842 /* Write back the register source. */
9dac77fa
AK		 2843 ctxt->src.val = ctxt->dst.val;
2844 write_register_operand(&ctxt->src);
e4f973ae
TY		 2845
2846 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2847 ctxt->dst.val = ctxt->src.orig_val;
2848 ctxt->lock_prefix = 1;
e4f973ae
TY		 2849 return X86EMUL_CONTINUE;
2850}
2851
5c82aa29 2852static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2853{
a31b9cea 2854 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2855 return X86EMUL_CONTINUE;
2856}
2857
5c82aa29
AK		 2858static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2859{
9dac77fa 2860 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2861 return em_imul(ctxt);
2862}
2863
61429142
AK		 2864static int em_cwd(struct x86_emulate_ctxt *ctxt)
2865{
9dac77fa
AK		 2866 ctxt->dst.type = OP_REG;
2867 ctxt->dst.bytes = ctxt->src.bytes;
2868 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2869 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2870
2871 return X86EMUL_CONTINUE;
2872}
2873
48bb5d3c
AK		 2874static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2875{
48bb5d3c
AK		 2876 u64 tsc = 0;
2877
717746e3 2878 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2879 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2880 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2881 return X86EMUL_CONTINUE;
2882}
2883
222d21aa
AK		 2884static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2885{
2886 u64 pmc;
2887
2888 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2889 return emulate_gp(ctxt, 0);
2890 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2891 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2892 return X86EMUL_CONTINUE;
2893}
2894
b9eac5f4
AK		 2895static int em_mov(struct x86_emulate_ctxt *ctxt)
2896{
49597d81 2897 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2898 return X86EMUL_CONTINUE;
2899}
2900
bc00f8d2
TY		 2901static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2902{
2903 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2904 return emulate_gp(ctxt, 0);
2905
2906 /* Disable writeback. */
2907 ctxt->dst.type = OP_NONE;
2908 return X86EMUL_CONTINUE;
2909}
2910
2911static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2912{
2913 unsigned long val;
2914
2915 if (ctxt->mode == X86EMUL_MODE_PROT64)
2916 val = ctxt->src.val & ~0ULL;
2917 else
2918 val = ctxt->src.val & ~0U;
2919
2920 /* #UD condition is already handled. */
2921 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2922 return emulate_gp(ctxt, 0);
2923
2924 /* Disable writeback. */
2925 ctxt->dst.type = OP_NONE;
2926 return X86EMUL_CONTINUE;
2927}
2928
e1e210b0
TY		 2929static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2930{
2931 u64 msr_data;
2932
2933 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2934 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2935 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2936 return emulate_gp(ctxt, 0);
2937
2938 return X86EMUL_CONTINUE;
2939}
2940
2941static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2942{
2943 u64 msr_data;
2944
2945 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2946 return emulate_gp(ctxt, 0);
2947
2948 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2949 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2950 return X86EMUL_CONTINUE;
2951}
2952
1bd5f469
TY		 2953static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2954{
9dac77fa 2955 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2956 return emulate_ud(ctxt);
2957
9dac77fa 2958 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2959 return X86EMUL_CONTINUE;
2960}
2961
2962static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2963{
9dac77fa 2964 u16 sel = ctxt->src.val;
1bd5f469 2965
9dac77fa 2966 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2967 return emulate_ud(ctxt);
2968
9dac77fa 2969 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2970 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2971
2972 /* Disable writeback. */
9dac77fa
AK		 2973 ctxt->dst.type = OP_NONE;
2974 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2975}
2976
38503911
AK		 2977static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2978{
9fa088f4
AK		 2979 int rc;
2980 ulong linear;
2981
9dac77fa 2982 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2983 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2984 ctxt->ops->invlpg(ctxt, linear);
38503911 2985 /* Disable writeback. */
9dac77fa 2986 ctxt->dst.type = OP_NONE;
38503911
AK		 2987 return X86EMUL_CONTINUE;
2988}
2989
2d04a05b
AK		 2990static int em_clts(struct x86_emulate_ctxt *ctxt)
2991{
2992 ulong cr0;
2993
2994 cr0 = ctxt->ops->get_cr(ctxt, 0);
2995 cr0 &= ~X86_CR0_TS;
2996 ctxt->ops->set_cr(ctxt, 0, cr0);
2997 return X86EMUL_CONTINUE;
2998}
2999
26d05cc7
AK		 3000static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3001{
26d05cc7
AK		 3002 int rc;
3003
9dac77fa 3004 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3005 return X86EMUL_UNHANDLEABLE;
3006
3007 rc = ctxt->ops->fix_hypercall(ctxt);
3008 if (rc != X86EMUL_CONTINUE)
3009 return rc;
3010
3011 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3012 ctxt->_eip = ctxt->eip;
26d05cc7 3013 /* Disable writeback. */
9dac77fa 3014 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3015 return X86EMUL_CONTINUE;
3016}
3017
3018static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3019{
26d05cc7
AK		 3020 struct desc_ptr desc_ptr;
3021 int rc;
3022
510425ff
AK		 3023 if (ctxt->mode == X86EMUL_MODE_PROT64)
3024 ctxt->op_bytes = 8;
9dac77fa 3025 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3026 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3027 ctxt->op_bytes);
26d05cc7
AK		 3028 if (rc != X86EMUL_CONTINUE)
3029 return rc;
3030 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3031 /* Disable writeback. */
9dac77fa 3032 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3033 return X86EMUL_CONTINUE;
3034}
3035
5ef39c71 3036static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3037{
26d05cc7
AK		 3038 int rc;
3039
5ef39c71
AK		 3040 rc = ctxt->ops->fix_hypercall(ctxt);
3041
26d05cc7 3042 /* Disable writeback. */
9dac77fa 3043 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3044 return rc;
3045}
3046
3047static int em_lidt(struct x86_emulate_ctxt *ctxt)
3048{
26d05cc7
AK		 3049 struct desc_ptr desc_ptr;
3050 int rc;
3051
510425ff
AK		 3052 if (ctxt->mode == X86EMUL_MODE_PROT64)
3053 ctxt->op_bytes = 8;
9dac77fa 3054 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3055 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3056 ctxt->op_bytes);
26d05cc7
AK		 3057 if (rc != X86EMUL_CONTINUE)
3058 return rc;
3059 ctxt->ops->set_idt(ctxt, &desc_ptr);
3060 /* Disable writeback. */
9dac77fa 3061 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3062 return X86EMUL_CONTINUE;
3063}
3064
3065static int em_smsw(struct x86_emulate_ctxt *ctxt)
3066{
9dac77fa
AK		 3067 ctxt->dst.bytes = 2;
3068 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3069 return X86EMUL_CONTINUE;
3070}
3071
3072static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3073{
26d05cc7 3074 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3075 | (ctxt->src.val & 0x0f));
3076 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3077 return X86EMUL_CONTINUE;
3078}
3079
d06e03ad
TY		 3080static int em_loop(struct x86_emulate_ctxt *ctxt)
3081{
9dac77fa
AK		 3082 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3083 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3084 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3085 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3086
3087 return X86EMUL_CONTINUE;
3088}
3089
3090static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3091{
9dac77fa
AK		 3092 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3093 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3094
3095 return X86EMUL_CONTINUE;
3096}
3097
d7841a4b
TY		 3098static int em_in(struct x86_emulate_ctxt *ctxt)
3099{
3100 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3101 &ctxt->dst.val))
3102 return X86EMUL_IO_NEEDED;
3103
3104 return X86EMUL_CONTINUE;
3105}
3106
3107static int em_out(struct x86_emulate_ctxt *ctxt)
3108{
3109 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3110 &ctxt->src.val, 1);
3111 /* Disable writeback. */
3112 ctxt->dst.type = OP_NONE;
3113 return X86EMUL_CONTINUE;
3114}
3115
f411e6cd
TY		 3116static int em_cli(struct x86_emulate_ctxt *ctxt)
3117{
3118 if (emulator_bad_iopl(ctxt))
3119 return emulate_gp(ctxt, 0);
3120
3121 ctxt->eflags &= ~X86_EFLAGS_IF;
3122 return X86EMUL_CONTINUE;
3123}
3124
3125static int em_sti(struct x86_emulate_ctxt *ctxt)
3126{
3127 if (emulator_bad_iopl(ctxt))
3128 return emulate_gp(ctxt, 0);
3129
3130 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3131 ctxt->eflags |= X86_EFLAGS_IF;
3132 return X86EMUL_CONTINUE;
3133}
3134
ce7faab2
TY		 3135static int em_bt(struct x86_emulate_ctxt *ctxt)
3136{
3137 /* Disable writeback. */
3138 ctxt->dst.type = OP_NONE;
3139 /* only subword offset */
3140 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3141
3142 emulate_2op_SrcV_nobyte(ctxt, "bt");
3143 return X86EMUL_CONTINUE;
3144}
3145
3146static int em_bts(struct x86_emulate_ctxt *ctxt)
3147{
3148 emulate_2op_SrcV_nobyte(ctxt, "bts");
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int em_btr(struct x86_emulate_ctxt *ctxt)
3153{
3154 emulate_2op_SrcV_nobyte(ctxt, "btr");
3155 return X86EMUL_CONTINUE;
3156}
3157
3158static int em_btc(struct x86_emulate_ctxt *ctxt)
3159{
3160 emulate_2op_SrcV_nobyte(ctxt, "btc");
3161 return X86EMUL_CONTINUE;
3162}
3163
ff227392
TY		 3164static int em_bsf(struct x86_emulate_ctxt *ctxt)
3165{
d54e4237 3166 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3167 return X86EMUL_CONTINUE;
3168}
3169
3170static int em_bsr(struct x86_emulate_ctxt *ctxt)
3171{
d54e4237 3172 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3173 return X86EMUL_CONTINUE;
3174}
3175
6d6eede4
AK		 3176static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3177{
3178 u32 eax, ebx, ecx, edx;
3179
3180 eax = ctxt->regs[VCPU_REGS_RAX];
3181 ecx = ctxt->regs[VCPU_REGS_RCX];
3182 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3183 ctxt->regs[VCPU_REGS_RAX] = eax;
3184 ctxt->regs[VCPU_REGS_RBX] = ebx;
3185 ctxt->regs[VCPU_REGS_RCX] = ecx;
3186 ctxt->regs[VCPU_REGS_RDX] = edx;
3187 return X86EMUL_CONTINUE;
3188}
3189
cfec82cb
JR		 3190static bool valid_cr(int nr)
3191{
3192 switch (nr) {
3193 case 0:
3194 case 2 ... 4:
3195 case 8:
3196 return true;
3197 default:
3198 return false;
3199 }
3200}
3201
3202static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3203{
9dac77fa 3204 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3205 return emulate_ud(ctxt);
3206
3207 return X86EMUL_CONTINUE;
3208}
3209
3210static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3211{
9dac77fa
AK		 3212 u64 new_val = ctxt->src.val64;
3213 int cr = ctxt->modrm_reg;
c2ad2bb3 3214 u64 efer = 0;
cfec82cb
JR		 3215
3216 static u64 cr_reserved_bits[] = {
3217 0xffffffff00000000ULL,
3218 0, 0, 0, /* CR3 checked later */
3219 CR4_RESERVED_BITS,
3220 0, 0, 0,
3221 CR8_RESERVED_BITS,
3222 };
3223
3224 if (!valid_cr(cr))
3225 return emulate_ud(ctxt);
3226
3227 if (new_val & cr_reserved_bits[cr])
3228 return emulate_gp(ctxt, 0);
3229
3230 switch (cr) {
3231 case 0: {
c2ad2bb3 3232 u64 cr4;
cfec82cb
JR		 3233 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3234 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3235 return emulate_gp(ctxt, 0);
3236
717746e3
AK		 3237 cr4 = ctxt->ops->get_cr(ctxt, 4);
3238 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3239
3240 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3241 !(cr4 & X86_CR4_PAE))
3242 return emulate_gp(ctxt, 0);
3243
3244 break;
3245 }
3246 case 3: {
3247 u64 rsvd = 0;
3248
c2ad2bb3
AK		 3249 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3250 if (efer & EFER_LMA)
cfec82cb 3251 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3252 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3253 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3254 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3255 rsvd = CR3_NONPAE_RESERVED_BITS;
3256
3257 if (new_val & rsvd)
3258 return emulate_gp(ctxt, 0);
3259
3260 break;
3261 }
3262 case 4: {
717746e3 3263 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3264
3265 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3266 return emulate_gp(ctxt, 0);
3267
3268 break;
3269 }
3270 }
3271
3272 return X86EMUL_CONTINUE;
3273}
3274
3b88e41a
JR		 3275static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3276{
3277 unsigned long dr7;
3278
717746e3 3279 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3280
3281 /* Check if DR7.Global_Enable is set */
3282 return dr7 & (1 << 13);
3283}
3284
3285static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3286{
9dac77fa 3287 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3288 u64 cr4;
3289
3290 if (dr > 7)
3291 return emulate_ud(ctxt);
3292
717746e3 3293 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3294 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3295 return emulate_ud(ctxt);
3296
3297 if (check_dr7_gd(ctxt))
3298 return emulate_db(ctxt);
3299
3300 return X86EMUL_CONTINUE;
3301}
3302
3303static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3304{
9dac77fa
AK		 3305 u64 new_val = ctxt->src.val64;
3306 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3307
3308 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3309 return emulate_gp(ctxt, 0);
3310
3311 return check_dr_read(ctxt);
3312}
3313
01de8b09
JR		 3314static int check_svme(struct x86_emulate_ctxt *ctxt)
3315{
3316 u64 efer;
3317
717746e3 3318 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3319
3320 if (!(efer & EFER_SVME))
3321 return emulate_ud(ctxt);
3322
3323 return X86EMUL_CONTINUE;
3324}
3325
3326static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3327{
9dac77fa 3328 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3329
3330 /* Valid physical address? */
d4224449 3331 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3332 return emulate_gp(ctxt, 0);
3333
3334 return check_svme(ctxt);
3335}
3336
d7eb8203
JR		 3337static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3338{
717746e3 3339 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3340
717746e3 3341 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3342 return emulate_ud(ctxt);
3343
3344 return X86EMUL_CONTINUE;
3345}
3346
8061252e
JR		 3347static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3348{
717746e3 3349 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3350 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3351
717746e3 3352 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3353 (rcx > 3))
3354 return emulate_gp(ctxt, 0);
3355
3356 return X86EMUL_CONTINUE;
3357}
3358
f6511935
JR		 3359static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3360{
9dac77fa
AK		 3361 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3362 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3363 return emulate_gp(ctxt, 0);
3364
3365 return X86EMUL_CONTINUE;
3366}
3367
3368static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3369{
9dac77fa
AK		 3370 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3371 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3372 return emulate_gp(ctxt, 0);
3373
3374 return X86EMUL_CONTINUE;
3375}
3376
73fba5f4 3377#define D(_y) { .flags = (_y) }
c4f035c6 3378#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3379#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3380 .check_perm = (_p) }
73fba5f4 3381#define N D(0)
01de8b09 3382#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3383#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3384#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3385#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3386#define II(_f, _e, _i) \
3387 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3388#define IIP(_f, _e, _i, _p) \
3389 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3390 .check_perm = (_p) }
aa97bb48 3391#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3392
8d8f4e9f 3393#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3394#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3395#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3396#define I2bvIP(_f, _e, _i, _p) \
3397 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3398
d67fc27a
TY		 3399#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3400 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3401 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3402
d7eb8203 3403static struct opcode group7_rm1[] = {
1c2545be
TY		 3404 DI(SrcNone | Priv, monitor),
3405 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3406 N, N, N, N, N, N,
3407};
3408
01de8b09 3409static struct opcode group7_rm3[] = {
1c2545be
TY		 3410 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3411 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3412 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3413 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3414 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3415 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3416 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3417 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3418};
6230f7fc 3419
d7eb8203
JR		 3420static struct opcode group7_rm7[] = {
3421 N,
1c2545be 3422 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3423 N, N, N, N, N, N,
3424};
d67fc27a 3425
73fba5f4 3426static struct opcode group1[] = {
d67fc27a 3427 I(Lock, em_add),
d5ae7ce8 3428 I(Lock | PageTable, em_or),
d67fc27a
TY		 3429 I(Lock, em_adc),
3430 I(Lock, em_sbb),
d5ae7ce8 3431 I(Lock | PageTable, em_and),
d67fc27a
TY		 3432 I(Lock, em_sub),
3433 I(Lock, em_xor),
3434 I(0, em_cmp),
73fba5f4
AK		 3435};
3436
3437static struct opcode group1A[] = {
1c2545be 3438 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3439};
3440
3441static struct opcode group3[] = {
1c2545be
TY		 3442 I(DstMem | SrcImm, em_test),
3443 I(DstMem | SrcImm, em_test),
3444 I(DstMem | SrcNone | Lock, em_not),
3445 I(DstMem | SrcNone | Lock, em_neg),
3446 I(SrcMem, em_mul_ex),
3447 I(SrcMem, em_imul_ex),
3448 I(SrcMem, em_div_ex),
3449 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3450};
3451
3452static struct opcode group4[] = {
1c2545be
TY		 3453 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3454 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3455 N, N, N, N, N, N,
3456};
3457
3458static struct opcode group5[] = {
1c2545be
TY		 3459 I(DstMem | SrcNone | Lock, em_grp45),
3460 I(DstMem | SrcNone | Lock, em_grp45),
3461 I(SrcMem | Stack, em_grp45),
3462 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3463 I(SrcMem | Stack, em_grp45),
3464 I(SrcMemFAddr | ImplicitOps, em_grp45),
3465 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3466};
3467
dee6bb70 3468static struct opcode group6[] = {
1c2545be
TY		 3469 DI(Prot, sldt),
3470 DI(Prot, str),
3471 DI(Prot | Priv, lldt),
3472 DI(Prot | Priv, ltr),
dee6bb70
JR		 3473 N, N, N, N,
3474};
3475
73fba5f4 3476static struct group_dual group7 = { {
1c2545be
TY		 3477 DI(Mov | DstMem | Priv, sgdt),
3478 DI(Mov | DstMem | Priv, sidt),
3479 II(SrcMem | Priv, em_lgdt, lgdt),
3480 II(SrcMem | Priv, em_lidt, lidt),
3481 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3482 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3483 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3484}, {
1c2545be 3485 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3486 EXT(0, group7_rm1),
01de8b09 3487 N, EXT(0, group7_rm3),
1c2545be
TY		 3488 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3489 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3490 EXT(0, group7_rm7),
73fba5f4
AK		 3491} };
3492
3493static struct opcode group8[] = {
3494 N, N, N, N,
1c2545be
TY		 3495 I(DstMem | SrcImmByte, em_bt),
3496 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3497 I(DstMem | SrcImmByte | Lock, em_btr),
3498 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3499};
3500
3501static struct group_dual group9 = { {
1c2545be 3502 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3503}, {
3504 N, N, N, N, N, N, N, N,
3505} };
3506
a4d4a7c1 3507static struct opcode group11[] = {
1c2545be 3508 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3509 X7(D(Undefined)),
a4d4a7c1
AK		 3510};
3511
aa97bb48 3512static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3513 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3514};
3515
3e114eb4
AK		 3516static struct gprefix pfx_vmovntpx = {
3517 I(0, em_mov), N, N, N,
3518};
3519
73fba5f4
AK		 3520static struct opcode opcode_table[256] = {
3521 /* 0x00 - 0x07 */
d67fc27a 3522 I6ALU(Lock, em_add),
1cd196ea
AK		 3523 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3524 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3525 /* 0x08 - 0x0F */
d5ae7ce8 3526 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3527 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3528 N,
73fba5f4 3529 /* 0x10 - 0x17 */
d67fc27a 3530 I6ALU(Lock, em_adc),
1cd196ea
AK		 3531 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3532 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3533 /* 0x18 - 0x1F */
d67fc27a 3534 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3535 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3536 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3537 /* 0x20 - 0x27 */
d5ae7ce8 3538 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3539 /* 0x28 - 0x2F */
d67fc27a 3540 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3541 /* 0x30 - 0x37 */
d67fc27a 3542 I6ALU(Lock, em_xor), N, N,
73fba5f4 3543 /* 0x38 - 0x3F */
d67fc27a 3544 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3545 /* 0x40 - 0x4F */
3546 X16(D(DstReg)),
3547 /* 0x50 - 0x57 */
63540382 3548 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3549 /* 0x58 - 0x5F */
c54fe504 3550 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3551 /* 0x60 - 0x67 */
b96a7fad
TY		 3552 I(ImplicitOps | Stack | No64, em_pusha),
3553 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3554 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3555 N, N, N, N,
3556 /* 0x68 - 0x6F */
d46164db
AK		 3557 I(SrcImm | Mov | Stack, em_push),
3558 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3559 I(SrcImmByte | Mov | Stack, em_push),
3560 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3561 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3562 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3563 /* 0x70 - 0x7F */
3564 X16(D(SrcImmByte)),
3565 /* 0x80 - 0x87 */
1c2545be
TY		 3566 G(ByteOp | DstMem | SrcImm, group1),
3567 G(DstMem | SrcImm, group1),
3568 G(ByteOp | DstMem | SrcImm | No64, group1),
3569 G(DstMem | SrcImmByte, group1),
9f21ca59 3570 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3571 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3572 /* 0x88 - 0x8F */
d5ae7ce8 3573 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3574 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3575 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3576 D(ModRM | SrcMem | NoAccess | DstReg),
3577 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3578 G(0, group1A),
73fba5f4 3579 /* 0x90 - 0x97 */
bf608f88 3580 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3581 /* 0x98 - 0x9F */
61429142 3582 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3583 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3584 II(ImplicitOps | Stack, em_pushf, pushf),
3585 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3586 /* 0xA0 - 0xA7 */
b9eac5f4 3587 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3588 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3589 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3590 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3591 /* 0xA8 - 0xAF */
9f21ca59 3592 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3593 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3594 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3595 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3596 /* 0xB0 - 0xB7 */
b9eac5f4 3597 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3598 /* 0xB8 - 0xBF */
b9eac5f4 3599 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3600 /* 0xC0 - 0xC7 */
d2c6c7ad 3601 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3602 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3603 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3604 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3605 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3606 G(ByteOp, group11), G(0, group11),
73fba5f4 3607 /* 0xC8 - 0xCF */
f47cfa31 3608 N, I(Stack, em_leave), N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3609 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3610 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3611 /* 0xD0 - 0xD7 */
d2c6c7ad 3612 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3613 N, N, N, N,
3614 /* 0xD8 - 0xDF */
3615 N, N, N, N, N, N, N, N,
3616 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3617 X3(I(SrcImmByte, em_loop)),
3618 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3619 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3620 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3621 /* 0xE8 - 0xEF */
d4ddafcd 3622 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3623 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3624 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3625 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3626 /* 0xF0 - 0xF7 */
bf608f88 3627 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3628 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3629 G(ByteOp, group3), G(0, group3),
73fba5f4 3630 /* 0xF8 - 0xFF */
f411e6cd
TY		 3631 D(ImplicitOps), D(ImplicitOps),
3632 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3633 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3634};
3635
3636static struct opcode twobyte_table[256] = {
3637 /* 0x00 - 0x0F */
dee6bb70 3638 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3639 N, I(ImplicitOps | VendorSpecific, em_syscall),
3640 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3641 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3642 N, D(ImplicitOps | ModRM), N, N,
3643 /* 0x10 - 0x1F */
3644 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3645 /* 0x20 - 0x2F */
cfec82cb 3646 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3647 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3648 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3649 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3650 N, N, N, N,
3e114eb4
AK		 3651 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3652 N, N, N, N,
73fba5f4 3653 /* 0x30 - 0x3F */
e1e210b0 3654 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3655 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3656 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3657 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3658 I(ImplicitOps | VendorSpecific, em_sysenter),
3659 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3660 N, N,
73fba5f4
AK		 3661 N, N, N, N, N, N, N, N,
3662 /* 0x40 - 0x4F */
3663 X16(D(DstReg | SrcMem | ModRM | Mov)),
3664 /* 0x50 - 0x5F */
3665 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3666 /* 0x60 - 0x6F */
aa97bb48
AK		 3667 N, N, N, N,
3668 N, N, N, N,
3669 N, N, N, N,
3670 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3671 /* 0x70 - 0x7F */
aa97bb48
AK		 3672 N, N, N, N,
3673 N, N, N, N,
3674 N, N, N, N,
3675 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3676 /* 0x80 - 0x8F */
3677 X16(D(SrcImm)),
3678 /* 0x90 - 0x9F */
ee45b58e 3679 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3680 /* 0xA0 - 0xA7 */
1cd196ea 3681 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3682 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3683 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3684 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3685 /* 0xA8 - 0xAF */
1cd196ea 3686 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3687 DI(ImplicitOps, rsm),
ce7faab2 3688 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3689 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3690 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3691 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3692 /* 0xB0 - 0xB7 */
e940b5c2 3693 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3694 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3695 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3696 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3697 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3698 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3699 /* 0xB8 - 0xBF */
3700 N, N,
ce7faab2
TY		 3701 G(BitOp, group8),
3702 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3703 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3704 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3705 /* 0xC0 - 0xCF */
739ae406 3706 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3707 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3708 N, N, N, GD(0, &group9),
3709 N, N, N, N, N, N, N, N,
3710 /* 0xD0 - 0xDF */
3711 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3712 /* 0xE0 - 0xEF */
3713 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3714 /* 0xF0 - 0xFF */
3715 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3716};
3717
3718#undef D
3719#undef N
3720#undef G
3721#undef GD
3722#undef I
aa97bb48 3723#undef GP
01de8b09 3724#undef EXT
73fba5f4 3725
8d8f4e9f 3726#undef D2bv
f6511935 3727#undef D2bvIP
8d8f4e9f 3728#undef I2bv
d7841a4b 3729#undef I2bvIP
d67fc27a 3730#undef I6ALU
8d8f4e9f 3731
9dac77fa 3732static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3733{
3734 unsigned size;
3735
9dac77fa 3736 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3737 if (size == 8)
3738 size = 4;
3739 return size;
3740}
3741
3742static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3743 unsigned size, bool sign_extension)
3744{
39f21ee5
AK		 3745 int rc = X86EMUL_CONTINUE;
3746
3747 op->type = OP_IMM;
3748 op->bytes = size;
9dac77fa 3749 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3750 /* NB. Immediates are sign-extended as necessary. */
3751 switch (op->bytes) {
3752 case 1:
e85a1085 3753 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3754 break;
3755 case 2:
e85a1085 3756 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3757 break;
3758 case 4:
e85a1085 3759 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3760 break;
3761 }
3762 if (!sign_extension) {
3763 switch (op->bytes) {
3764 case 1:
3765 op->val &= 0xff;
3766 break;
3767 case 2:
3768 op->val &= 0xffff;
3769 break;
3770 case 4:
3771 op->val &= 0xffffffff;
3772 break;
3773 }
3774 }
3775done:
3776 return rc;
3777}
3778
a9945549
AK		 3779static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3780 unsigned d)
3781{
3782 int rc = X86EMUL_CONTINUE;
3783
3784 switch (d) {
3785 case OpReg:
2adb5ad9 3786 decode_register_operand(ctxt, op);
a9945549
AK		 3787 break;
3788 case OpImmUByte:
608aabe3 3789 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3790 break;
3791 case OpMem:
41ddf978 3792 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3793 mem_common:
3794 *op = ctxt->memop;
3795 ctxt->memopp = op;
3796 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3797 fetch_bit_operand(ctxt);
3798 op->orig_val = op->val;
3799 break;
41ddf978
AK		 3800 case OpMem64:
3801 ctxt->memop.bytes = 8;
3802 goto mem_common;
a9945549
AK		 3803 case OpAcc:
3804 op->type = OP_REG;
3805 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3806 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3807 fetch_register_operand(op);
3808 op->orig_val = op->val;
3809 break;
3810 case OpDI:
3811 op->type = OP_MEM;
3812 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3813 op->addr.mem.ea =
3814 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3815 op->addr.mem.seg = VCPU_SREG_ES;
3816 op->val = 0;
3817 break;
3818 case OpDX:
3819 op->type = OP_REG;
3820 op->bytes = 2;
3821 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3822 fetch_register_operand(op);
3823 break;
4dd6a57d
AK		 3824 case OpCL:
3825 op->bytes = 1;
3826 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3827 break;
3828 case OpImmByte:
3829 rc = decode_imm(ctxt, op, 1, true);
3830 break;
3831 case OpOne:
3832 op->bytes = 1;
3833 op->val = 1;
3834 break;
3835 case OpImm:
3836 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3837 break;
28867cee
AK		 3838 case OpMem8:
3839 ctxt->memop.bytes = 1;
3840 goto mem_common;
0fe59128
AK		 3841 case OpMem16:
3842 ctxt->memop.bytes = 2;
3843 goto mem_common;
3844 case OpMem32:
3845 ctxt->memop.bytes = 4;
3846 goto mem_common;
3847 case OpImmU16:
3848 rc = decode_imm(ctxt, op, 2, false);
3849 break;
3850 case OpImmU:
3851 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3852 break;
3853 case OpSI:
3854 op->type = OP_MEM;
3855 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3856 op->addr.mem.ea =
3857 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3858 op->addr.mem.seg = seg_override(ctxt);
3859 op->val = 0;
3860 break;
3861 case OpImmFAddr:
3862 op->type = OP_IMM;
3863 op->addr.mem.ea = ctxt->_eip;
3864 op->bytes = ctxt->op_bytes + 2;
3865 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3866 break;
3867 case OpMemFAddr:
3868 ctxt->memop.bytes = ctxt->op_bytes + 2;
3869 goto mem_common;
c191a7a0
AK		 3870 case OpES:
3871 op->val = VCPU_SREG_ES;
3872 break;
3873 case OpCS:
3874 op->val = VCPU_SREG_CS;
3875 break;
3876 case OpSS:
3877 op->val = VCPU_SREG_SS;
3878 break;
3879 case OpDS:
3880 op->val = VCPU_SREG_DS;
3881 break;
3882 case OpFS:
3883 op->val = VCPU_SREG_FS;
3884 break;
3885 case OpGS:
3886 op->val = VCPU_SREG_GS;
3887 break;
a9945549
AK		 3888 case OpImplicit:
3889 /* Special instructions do their own operand decoding. */
3890 default:
3891 op->type = OP_NONE; /* Disable writeback. */
3892 break;
3893 }
3894
3895done:
3896 return rc;
3897}
3898
ef5d75cc 3899int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3900{
dde7e6d1
AK		 3901 int rc = X86EMUL_CONTINUE;
3902 int mode = ctxt->mode;
46561646 3903 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3904 bool op_prefix = false;
46561646 3905 struct opcode opcode;
dde7e6d1 3906
f09ed83e
AK		 3907 ctxt->memop.type = OP_NONE;
3908 ctxt->memopp = NULL;
9dac77fa
AK		 3909 ctxt->_eip = ctxt->eip;
3910 ctxt->fetch.start = ctxt->_eip;
3911 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3912 if (insn_len > 0)
9dac77fa 3913 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3914
3915 switch (mode) {
3916 case X86EMUL_MODE_REAL:
3917 case X86EMUL_MODE_VM86:
3918 case X86EMUL_MODE_PROT16:
3919 def_op_bytes = def_ad_bytes = 2;
3920 break;
3921 case X86EMUL_MODE_PROT32:
3922 def_op_bytes = def_ad_bytes = 4;
3923 break;
3924#ifdef CONFIG_X86_64
3925 case X86EMUL_MODE_PROT64:
3926 def_op_bytes = 4;
3927 def_ad_bytes = 8;
3928 break;
3929#endif
3930 default:
1d2887e2 3931 return EMULATION_FAILED;
dde7e6d1
AK		 3932 }
3933
9dac77fa
AK		 3934 ctxt->op_bytes = def_op_bytes;
3935 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3936
3937 /* Legacy prefixes. */
3938 for (;;) {
e85a1085 3939 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3940 case 0x66: /* operand-size override */
0d7cdee8 3941 op_prefix = true;
dde7e6d1 3942 /* switch between 2/4 bytes */
9dac77fa 3943 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3944 break;
3945 case 0x67: /* address-size override */
3946 if (mode == X86EMUL_MODE_PROT64)
3947 /* switch between 4/8 bytes */
9dac77fa 3948 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3949 else
3950 /* switch between 2/4 bytes */
9dac77fa 3951 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3952 break;
3953 case 0x26: /* ES override */
3954 case 0x2e: /* CS override */
3955 case 0x36: /* SS override */
3956 case 0x3e: /* DS override */
9dac77fa 3957 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3958 break;
3959 case 0x64: /* FS override */
3960 case 0x65: /* GS override */
9dac77fa 3961 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3962 break;
3963 case 0x40 ... 0x4f: /* REX */
3964 if (mode != X86EMUL_MODE_PROT64)
3965 goto done_prefixes;
9dac77fa 3966 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3967 continue;
3968 case 0xf0: /* LOCK */
9dac77fa 3969 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3970 break;
3971 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3972 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3973 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3974 break;
3975 default:
3976 goto done_prefixes;
3977 }
3978
3979 /* Any legacy prefix after a REX prefix nullifies its effect. */
3980
9dac77fa 3981 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3982 }
3983
3984done_prefixes:
3985
3986 /* REX prefix. */
9dac77fa
AK		 3987 if (ctxt->rex_prefix & 8)
3988 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3989
3990 /* Opcode byte(s). */
9dac77fa 3991 opcode = opcode_table[ctxt->b];
d3ad6243 3992 /* Two-byte opcode? */
9dac77fa
AK		 3993 if (ctxt->b == 0x0f) {
3994 ctxt->twobyte = 1;
e85a1085 3995 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3996 opcode = twobyte_table[ctxt->b];
dde7e6d1 3997 }
9dac77fa 3998 ctxt->d = opcode.flags;
dde7e6d1 3999
9f4260e7
TY		 4000 if (ctxt->d & ModRM)
4001 ctxt->modrm = insn_fetch(u8, ctxt);
4002
9dac77fa
AK		 4003 while (ctxt->d & GroupMask) {
4004 switch (ctxt->d & GroupMask) {
46561646 4005 case Group:
9dac77fa 4006 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4007 opcode = opcode.u.group[goffset];
4008 break;
4009 case GroupDual:
9dac77fa
AK		 4010 goffset = (ctxt->modrm >> 3) & 7;
4011 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4012 opcode = opcode.u.gdual->mod3[goffset];
4013 else
4014 opcode = opcode.u.gdual->mod012[goffset];
4015 break;
4016 case RMExt:
9dac77fa 4017 goffset = ctxt->modrm & 7;
01de8b09 4018 opcode = opcode.u.group[goffset];
46561646
AK		 4019 break;
4020 case Prefix:
9dac77fa 4021 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4022 return EMULATION_FAILED;
9dac77fa 4023 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4024 switch (simd_prefix) {
4025 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4026 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4027 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4028 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4029 }
4030 break;
4031 default:
1d2887e2 4032 return EMULATION_FAILED;
0d7cdee8 4033 }
46561646 4034
b1ea50b2 4035 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4036 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4037 }
4038
9dac77fa
AK		 4039 ctxt->execute = opcode.u.execute;
4040 ctxt->check_perm = opcode.check_perm;
4041 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4042
4043 /* Unrecognised? */
9dac77fa 4044 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4045 return EMULATION_FAILED;
dde7e6d1 4046
9dac77fa 4047 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4048 return EMULATION_FAILED;
d867162c 4049
9dac77fa
AK		 4050 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4051 ctxt->op_bytes = 8;
dde7e6d1 4052
9dac77fa 4053 if (ctxt->d & Op3264) {
7f9b4b75 4054 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4055 ctxt->op_bytes = 8;
7f9b4b75 4056 else
9dac77fa 4057 ctxt->op_bytes = 4;
7f9b4b75
AK		 4058 }
4059
9dac77fa
AK		 4060 if (ctxt->d & Sse)
4061 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4062 else if (ctxt->d & Mmx)
4063 ctxt->op_bytes = 8;
1253791d 4064
dde7e6d1 4065 /* ModRM and SIB bytes. */
9dac77fa 4066 if (ctxt->d & ModRM) {
f09ed83e 4067 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4068 if (!ctxt->has_seg_override)
4069 set_seg_override(ctxt, ctxt->modrm_seg);
4070 } else if (ctxt->d & MemAbs)
f09ed83e 4071 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4072 if (rc != X86EMUL_CONTINUE)
4073 goto done;
4074
9dac77fa
AK		 4075 if (!ctxt->has_seg_override)
4076 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4077
f09ed83e 4078 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4079
f09ed83e
AK		 4080 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4081 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4082
dde7e6d1
AK		 4083 /*
4084 * Decode and fetch the source operand: register, memory
4085 * or immediate.
4086 */
0fe59128 4087 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4088 if (rc != X86EMUL_CONTINUE)
4089 goto done;
4090
dde7e6d1
AK		 4091 /*
4092 * Decode and fetch the second source operand: register, memory
4093 * or immediate.
4094 */
4dd6a57d 4095 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4096 if (rc != X86EMUL_CONTINUE)
4097 goto done;
4098
dde7e6d1 4099 /* Decode and fetch the destination operand: register or memory. */
a9945549 4100 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4101
4102done:
f09ed83e
AK		 4103 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4104 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4105
1d2887e2 4106 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4107}
4108
1cb3f3ae
XG		 4109bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4110{
4111 return ctxt->d & PageTable;
4112}
4113
3e2f65d5
GN		 4114static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4115{
3e2f65d5
GN		 4116 /* The second termination condition only applies for REPE
4117 * and REPNE. Test if the repeat string operation prefix is
4118 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4119 * corresponding termination condition according to:
4120 * - if REPE/REPZ and ZF = 0 then done
4121 * - if REPNE/REPNZ and ZF = 1 then done
4122 */
9dac77fa
AK		 4123 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4124 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4125 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4126 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4127 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4128 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4129 return true;
4130
4131 return false;
4132}
4133
cbe2c9d3
AK		 4134static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4135{
4136 bool fault = false;
4137
4138 ctxt->ops->get_fpu(ctxt);
4139 asm volatile("1: fwait \n\t"
4140 "2: \n\t"
4141 ".pushsection .fixup,\"ax\" \n\t"
4142 "3: \n\t"
4143 "movb $1, %[fault] \n\t"
4144 "jmp 2b \n\t"
4145 ".popsection \n\t"
4146 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4147 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4148 ctxt->ops->put_fpu(ctxt);
4149
4150 if (unlikely(fault))
4151 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4152
4153 return X86EMUL_CONTINUE;
4154}
4155
4156static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4157 struct operand *op)
4158{
4159 if (op->type == OP_MM)
4160 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4161}
4162
7b105ca2 4163int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4164{
9aabc88f 4165 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4166 int rc = X86EMUL_CONTINUE;
9dac77fa 4167 int saved_dst_type = ctxt->dst.type;
8b4caf66 4168
9dac77fa 4169 ctxt->mem_read.pos = 0;
310b5d30 4170
9dac77fa 4171 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4172 rc = emulate_ud(ctxt);
1161624f
GN		 4173 goto done;
4174 }
4175
d380a5e4 4176 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4177 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4178 rc = emulate_ud(ctxt);
d380a5e4
GN		 4179 goto done;
4180 }
4181
9dac77fa 4182 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4183 rc = emulate_ud(ctxt);
081bca0e
AK		 4184 goto done;
4185 }
4186
cbe2c9d3
AK		 4187 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4188 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4189 rc = emulate_ud(ctxt);
4190 goto done;
4191 }
4192
cbe2c9d3 4193 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4194 rc = emulate_nm(ctxt);
4195 goto done;
4196 }
4197
cbe2c9d3
AK		 4198 if (ctxt->d & Mmx) {
4199 rc = flush_pending_x87_faults(ctxt);
4200 if (rc != X86EMUL_CONTINUE)
4201 goto done;
4202 /*
4203 * Now that we know the fpu is exception safe, we can fetch
4204 * operands from it.
4205 */
4206 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4207 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4208 if (!(ctxt->d & Mov))
4209 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4210 }
4211
9dac77fa
AK		 4212 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4213 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4214 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4215 if (rc != X86EMUL_CONTINUE)
4216 goto done;
4217 }
4218
e92805ac 4219 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4220 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4221 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4222 goto done;
4223 }
4224
8ea7d6ae 4225 /* Instruction can only be executed in protected mode */
9dac77fa 4226 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4227 rc = emulate_ud(ctxt);
4228 goto done;
4229 }
4230
d09beabd 4231 /* Do instruction specific permission checks */
9dac77fa
AK		 4232 if (ctxt->check_perm) {
4233 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4234 if (rc != X86EMUL_CONTINUE)
4235 goto done;
4236 }
4237
9dac77fa
AK		 4238 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4239 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4240 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4241 if (rc != X86EMUL_CONTINUE)
4242 goto done;
4243 }
4244
9dac77fa 4245 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4246 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4247 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4248 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4249 goto done;
4250 }
b9fa9d6b
AK		 4251 }
4252
9dac77fa
AK		 4253 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4254 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4255 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4256 if (rc != X86EMUL_CONTINUE)
8b4caf66 4257 goto done;
9dac77fa 4258 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4259 }
4260
9dac77fa
AK		 4261 if (ctxt->src2.type == OP_MEM) {
4262 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4263 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4264 if (rc != X86EMUL_CONTINUE)
4265 goto done;
4266 }
4267
9dac77fa 4268 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4269 goto special_insn;
4270
4271
9dac77fa 4272 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4273 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4274 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4275 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4276 if (rc != X86EMUL_CONTINUE)
4277 goto done;
038e51de 4278 }
9dac77fa 4279 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4280
018a98db
AK		 4281special_insn:
4282
9dac77fa
AK		 4283 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4284 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4285 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4286 if (rc != X86EMUL_CONTINUE)
4287 goto done;
4288 }
4289
9dac77fa
AK		 4290 if (ctxt->execute) {
4291 rc = ctxt->execute(ctxt);
ef65c889
AK		 4292 if (rc != X86EMUL_CONTINUE)
4293 goto done;
4294 goto writeback;
4295 }
4296
9dac77fa 4297 if (ctxt->twobyte)
6aa8b732
AK		 4298 goto twobyte_insn;
4299
9dac77fa 4300 switch (ctxt->b) {
33615aa9 4301 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4302 emulate_1op(ctxt, "inc");
33615aa9
AK		 4303 break;
4304 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4305 emulate_1op(ctxt, "dec");
33615aa9 4306 break;
6aa8b732 4307 case 0x63: /* movsxd */
8b4caf66 4308 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4309 goto cannot_emulate;
9dac77fa 4310 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4311 break;
b2833e3c 4312 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4313 if (test_cc(ctxt->b, ctxt->eflags))
4314 jmp_rel(ctxt, ctxt->src.val);
018a98db 4315 break;
7e0b54b1 4316 case 0x8d: /* lea r16/r32, m */
9dac77fa 4317 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4318 break;
3d9e77df 4319 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4320 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4321 break;
e4f973ae
TY		 4322 rc = em_xchg(ctxt);
4323 break;
e8b6fa70 4324 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4325 switch (ctxt->op_bytes) {
4326 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4327 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4328 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4329 }
4330 break;
018a98db 4331 case 0xc0 ... 0xc1:
51187683 4332 rc = em_grp2(ctxt);
018a98db 4333 break;
6e154e56 4334 case 0xcc: /* int3 */
5c5df76b
TY		 4335 rc = emulate_int(ctxt, 3);
4336 break;
6e154e56 4337 case 0xcd: /* int n */
9dac77fa 4338 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4339 break;
4340 case 0xce: /* into */
5c5df76b
TY		 4341 if (ctxt->eflags & EFLG_OF)
4342 rc = emulate_int(ctxt, 4);
6e154e56 4343 break;
018a98db 4344 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4345 rc = em_grp2(ctxt);
018a98db
AK		 4346 break;
4347 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4348 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4349 rc = em_grp2(ctxt);
018a98db 4350 break;
1a52e051 4351 case 0xe9: /* jmp rel */
db5b0762 4352 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4353 jmp_rel(ctxt, ctxt->src.val);
4354 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4355 break;
111de5d6 4356 case 0xf4: /* hlt */
6c3287f7 4357 ctxt->ops->halt(ctxt);
19fdfa0d 4358 break;
111de5d6
AK		 4359 case 0xf5: /* cmc */
4360 /* complement carry flag from eflags reg */
4361 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4362 break;
4363 case 0xf8: /* clc */
4364 ctxt->eflags &= ~EFLG_CF;
111de5d6 4365 break;
8744aa9a
MG		 4366 case 0xf9: /* stc */
4367 ctxt->eflags |= EFLG_CF;
4368 break;
fb4616f4
MG		 4369 case 0xfc: /* cld */
4370 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4371 break;
4372 case 0xfd: /* std */
4373 ctxt->eflags |= EFLG_DF;
fb4616f4 4374 break;
91269b8f
AK		 4375 default:
4376 goto cannot_emulate;
6aa8b732 4377 }
018a98db 4378
7d9ddaed
AK		 4379 if (rc != X86EMUL_CONTINUE)
4380 goto done;
4381
018a98db 4382writeback:
adddcecf 4383 rc = writeback(ctxt);
1b30eaa8 4384 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4385 goto done;
4386
5cd21917
GN		 4387 /*
4388 * restore dst type in case the decoding will be reused
4389 * (happens for string instruction )
4390 */
9dac77fa 4391 ctxt->dst.type = saved_dst_type;
5cd21917 4392
9dac77fa
AK		 4393 if ((ctxt->d & SrcMask) == SrcSI)
4394 string_addr_inc(ctxt, seg_override(ctxt),
4395 VCPU_REGS_RSI, &ctxt->src);
a682e354 4396
9dac77fa 4397 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4398 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4399 &ctxt->dst);
d9271123 4400
9dac77fa
AK		 4401 if (ctxt->rep_prefix && (ctxt->d & String)) {
4402 struct read_cache *r = &ctxt->io_read;
4403 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4404
d2ddd1c4
GN		 4405 if (!string_insn_completed(ctxt)) {
4406 /*
4407 * Re-enter guest when pio read ahead buffer is empty
4408 * or, if it is not used, after each 1024 iteration.
4409 */
9dac77fa 4410 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4411 (r->end == 0 || r->end != r->pos)) {
4412 /*
4413 * Reset read cache. Usually happens before
4414 * decode, but since instruction is restarted
4415 * we have to do it here.
4416 */
9dac77fa 4417 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4418 return EMULATION_RESTART;
4419 }
4420 goto done; /* skip rip writeback */
0fa6ccbd 4421 }
5cd21917 4422 }
d2ddd1c4 4423
9dac77fa 4424 ctxt->eip = ctxt->_eip;
018a98db
AK		 4425
4426done:
da9cb575
AK		 4427 if (rc == X86EMUL_PROPAGATE_FAULT)
4428 ctxt->have_exception = true;
775fde86
JR		 4429 if (rc == X86EMUL_INTERCEPTED)
4430 return EMULATION_INTERCEPTED;
4431
d2ddd1c4 4432 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4433
4434twobyte_insn:
9dac77fa 4435 switch (ctxt->b) {
018a98db 4436 case 0x09: /* wbinvd */
cfb22375 4437 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4438 break;
4439 case 0x08: /* invd */
018a98db
AK		 4440 case 0x0d: /* GrpP (prefetch) */
4441 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4442 break;
4443 case 0x20: /* mov cr, reg */
9dac77fa 4444 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4445 break;
6aa8b732 4446 case 0x21: /* mov from dr to reg */
9dac77fa 4447 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4448 break;
6aa8b732 4449 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4450 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4451 if (!test_cc(ctxt->b, ctxt->eflags))
4452 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4453 break;
b2833e3c 4454 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4455 if (test_cc(ctxt->b, ctxt->eflags))
4456 jmp_rel(ctxt, ctxt->src.val);
018a98db 4457 break;
ee45b58e 4458 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4459 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4460 break;
9bf8ea42
GT		 4461 case 0xa4: /* shld imm8, r, r/m */
4462 case 0xa5: /* shld cl, r, r/m */
761441b9 4463 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4464 break;
9bf8ea42
GT		 4465 case 0xac: /* shrd imm8, r, r/m */
4466 case 0xad: /* shrd cl, r, r/m */
761441b9 4467 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4468 break;
2a7c5b8b
GC		 4469 case 0xae: /* clflush */
4470 break;
6aa8b732 4471 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4472 ctxt->dst.bytes = ctxt->op_bytes;
4473 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4474 : (u16) ctxt->src.val;
6aa8b732 4475 break;
6aa8b732 4476 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4477 ctxt->dst.bytes = ctxt->op_bytes;
4478 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4479 (s16) ctxt->src.val;
6aa8b732 4480 break;
92f738a5 4481 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4482 emulate_2op_SrcV(ctxt, "add");
92f738a5 4483 /* Write back the register source. */
9dac77fa
AK		 4484 ctxt->src.val = ctxt->dst.orig_val;
4485 write_register_operand(&ctxt->src);
92f738a5 4486 break;
a012e65a 4487 case 0xc3: /* movnti */
9dac77fa
AK		 4488 ctxt->dst.bytes = ctxt->op_bytes;
4489 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4490 (u64) ctxt->src.val;
a012e65a 4491 break;
91269b8f
AK		 4492 default:
4493 goto cannot_emulate;
6aa8b732 4494 }
7d9ddaed
AK		 4495
4496 if (rc != X86EMUL_CONTINUE)
4497 goto done;
4498
6aa8b732
AK		 4499 goto writeback;
4500
4501cannot_emulate:
a0c0ab2f 4502 return EMULATION_FAILED;
6aa8b732 4503}
Linux kernel - Deliverables
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