Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
221d059d | 12 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
23 | #ifndef __KERNEL__ | |
24 | #include <stdio.h> | |
25 | #include <stdint.h> | |
26 | #include <public/xen.h> | |
d77c26fc | 27 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 28 | #else |
edf88417 | 29 | #include <linux/kvm_host.h> |
5fdbf976 | 30 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
31 | #define DPRINTF(x...) do {} while (0) |
32 | #endif | |
6aa8b732 | 33 | #include <linux/module.h> |
56e82318 | 34 | #include <asm/kvm_emulate.h> |
6aa8b732 | 35 | |
3eeb3288 | 36 | #include "x86.h" |
38ba30ba | 37 | #include "tss.h" |
e99f0507 | 38 | |
6aa8b732 AK |
39 | /* |
40 | * Opcode effective-address decode tables. | |
41 | * Note that we only emulate instructions that have at least one memory | |
42 | * operand (excluding implicit stack references). We assume that stack | |
43 | * references and instruction fetches will never occur in special memory | |
44 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
45 | * not be handled. | |
46 | */ | |
47 | ||
48 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 49 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 50 | /* Destination operand type. */ |
ab85b12b AK |
51 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
52 | #define DstReg (2<<1) /* Register operand. */ | |
53 | #define DstMem (3<<1) /* Memory operand. */ | |
54 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
55 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
56 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 57 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 58 | #define DstMask (7<<1) |
6aa8b732 | 59 | /* Source operand type. */ |
9c9fddd0 | 60 | #define SrcNone (0<<4) /* No source operand. */ |
9c9fddd0 GT |
61 | #define SrcReg (1<<4) /* Register operand. */ |
62 | #define SrcMem (2<<4) /* Memory operand. */ | |
63 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
64 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
65 | #define SrcImm (5<<4) /* Immediate operand. */ | |
66 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 67 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 68 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 69 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 70 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
71 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
72 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 73 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
b250e605 | 74 | #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */ |
341de7e3 | 75 | #define SrcMask (0xf<<4) |
6aa8b732 | 76 | /* Generic ModRM decode. */ |
341de7e3 | 77 | #define ModRM (1<<8) |
6aa8b732 | 78 | /* Destination is only written; never read. */ |
341de7e3 GN |
79 | #define Mov (1<<9) |
80 | #define BitOp (1<<10) | |
81 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
82 | #define String (1<<12) /* String instruction (rep capable) */ |
83 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
84 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
85 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
d8769fed | 86 | /* Misc flags */ |
5a506b12 | 87 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 88 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 89 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 90 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 91 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 92 | #define No64 (1<<28) |
0dc8d10f GT |
93 | /* Source 2 operand type */ |
94 | #define Src2None (0<<29) | |
95 | #define Src2CL (1<<29) | |
96 | #define Src2ImmByte (2<<29) | |
97 | #define Src2One (3<<29) | |
7db41eb7 | 98 | #define Src2Imm (4<<29) |
0dc8d10f | 99 | #define Src2Mask (7<<29) |
6aa8b732 | 100 | |
d0e53325 AK |
101 | #define X2(x...) x, x |
102 | #define X3(x...) X2(x), x | |
103 | #define X4(x...) X2(x), X2(x) | |
104 | #define X5(x...) X4(x), x | |
105 | #define X6(x...) X4(x), X2(x) | |
106 | #define X7(x...) X4(x), X3(x) | |
107 | #define X8(x...) X4(x), X4(x) | |
108 | #define X16(x...) X8(x), X8(x) | |
83babbca | 109 | |
d65b1dee AK |
110 | struct opcode { |
111 | u32 flags; | |
120df890 | 112 | union { |
ef65c889 | 113 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
114 | struct opcode *group; |
115 | struct group_dual *gdual; | |
116 | } u; | |
117 | }; | |
118 | ||
119 | struct group_dual { | |
120 | struct opcode mod012[8]; | |
121 | struct opcode mod3[8]; | |
d65b1dee AK |
122 | }; |
123 | ||
6aa8b732 | 124 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
125 | #define EFLG_ID (1<<21) |
126 | #define EFLG_VIP (1<<20) | |
127 | #define EFLG_VIF (1<<19) | |
128 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
129 | #define EFLG_VM (1<<17) |
130 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
131 | #define EFLG_IOPL (3<<12) |
132 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
133 | #define EFLG_OF (1<<11) |
134 | #define EFLG_DF (1<<10) | |
b1d86143 | 135 | #define EFLG_IF (1<<9) |
d4c6a154 | 136 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
137 | #define EFLG_SF (1<<7) |
138 | #define EFLG_ZF (1<<6) | |
139 | #define EFLG_AF (1<<4) | |
140 | #define EFLG_PF (1<<2) | |
141 | #define EFLG_CF (1<<0) | |
142 | ||
62bd430e MG |
143 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
144 | #define EFLG_RESERVED_ONE_MASK 2 | |
145 | ||
6aa8b732 AK |
146 | /* |
147 | * Instruction emulation: | |
148 | * Most instructions are emulated directly via a fragment of inline assembly | |
149 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
150 | * any modified flags. | |
151 | */ | |
152 | ||
05b3e0c2 | 153 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
154 | #define _LO32 "k" /* force 32-bit operand */ |
155 | #define _STK "%%rsp" /* stack pointer */ | |
156 | #elif defined(__i386__) | |
157 | #define _LO32 "" /* force 32-bit operand */ | |
158 | #define _STK "%%esp" /* stack pointer */ | |
159 | #endif | |
160 | ||
161 | /* | |
162 | * These EFLAGS bits are restored from saved value during emulation, and | |
163 | * any changes are written back to the saved value after emulation. | |
164 | */ | |
165 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
166 | ||
167 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
168 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
169 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
170 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
171 | "push %"_tmp"; " \ | |
172 | "push %"_tmp"; " \ | |
173 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
174 | "andl %"_LO32 _tmp",("_STK"); " \ | |
175 | "pushf; " \ | |
176 | "notl %"_LO32 _tmp"; " \ | |
177 | "andl %"_LO32 _tmp",("_STK"); " \ | |
178 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
179 | "pop %"_tmp"; " \ | |
180 | "orl %"_LO32 _tmp",("_STK"); " \ | |
181 | "popf; " \ | |
182 | "pop %"_sav"; " | |
6aa8b732 AK |
183 | |
184 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
185 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
186 | /* _sav |= EFLAGS & _msk; */ \ | |
187 | "pushf; " \ | |
188 | "pop %"_tmp"; " \ | |
189 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
190 | "orl %"_LO32 _tmp",%"_sav"; " | |
191 | ||
dda96d8f AK |
192 | #ifdef CONFIG_X86_64 |
193 | #define ON64(x) x | |
194 | #else | |
195 | #define ON64(x) | |
196 | #endif | |
197 | ||
b3b3d25a | 198 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
199 | do { \ |
200 | __asm__ __volatile__ ( \ | |
201 | _PRE_EFLAGS("0", "4", "2") \ | |
202 | _op _suffix " %"_x"3,%1; " \ | |
203 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 204 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
205 | "=&r" (_tmp) \ |
206 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 207 | } while (0) |
6b7ad61f AK |
208 | |
209 | ||
6aa8b732 AK |
210 | /* Raw emulation: instruction has two explicit operands. */ |
211 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
212 | do { \ |
213 | unsigned long _tmp; \ | |
214 | \ | |
215 | switch ((_dst).bytes) { \ | |
216 | case 2: \ | |
b3b3d25a | 217 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
218 | break; \ |
219 | case 4: \ | |
b3b3d25a | 220 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
221 | break; \ |
222 | case 8: \ | |
b3b3d25a | 223 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
224 | break; \ |
225 | } \ | |
6aa8b732 AK |
226 | } while (0) |
227 | ||
228 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
229 | do { \ | |
6b7ad61f | 230 | unsigned long _tmp; \ |
d77c26fc | 231 | switch ((_dst).bytes) { \ |
6aa8b732 | 232 | case 1: \ |
b3b3d25a | 233 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
234 | break; \ |
235 | default: \ | |
236 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
237 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
238 | break; \ | |
239 | } \ | |
240 | } while (0) | |
241 | ||
242 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
243 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
244 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
245 | "b", "c", "b", "c", "b", "c", "b", "c") | |
246 | ||
247 | /* Source operand is byte, word, long or quad sized. */ | |
248 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
249 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
250 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
251 | ||
252 | /* Source operand is word, long or quad sized. */ | |
253 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
254 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
255 | "w", "r", _LO32, "r", "", "r") | |
256 | ||
d175226a GT |
257 | /* Instruction has three operands and one operand is stored in ECX register */ |
258 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
259 | do { \ | |
260 | unsigned long _tmp; \ | |
261 | _type _clv = (_cl).val; \ | |
262 | _type _srcv = (_src).val; \ | |
263 | _type _dstv = (_dst).val; \ | |
264 | \ | |
265 | __asm__ __volatile__ ( \ | |
266 | _PRE_EFLAGS("0", "5", "2") \ | |
267 | _op _suffix " %4,%1 \n" \ | |
268 | _POST_EFLAGS("0", "5", "2") \ | |
269 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
270 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
271 | ); \ | |
272 | \ | |
273 | (_cl).val = (unsigned long) _clv; \ | |
274 | (_src).val = (unsigned long) _srcv; \ | |
275 | (_dst).val = (unsigned long) _dstv; \ | |
276 | } while (0) | |
277 | ||
278 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
279 | do { \ | |
280 | switch ((_dst).bytes) { \ | |
281 | case 2: \ | |
282 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
283 | "w", unsigned short); \ | |
284 | break; \ | |
285 | case 4: \ | |
286 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
287 | "l", unsigned int); \ | |
288 | break; \ | |
289 | case 8: \ | |
290 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
291 | "q", unsigned long)); \ | |
292 | break; \ | |
293 | } \ | |
294 | } while (0) | |
295 | ||
dda96d8f | 296 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
297 | do { \ |
298 | unsigned long _tmp; \ | |
299 | \ | |
dda96d8f AK |
300 | __asm__ __volatile__ ( \ |
301 | _PRE_EFLAGS("0", "3", "2") \ | |
302 | _op _suffix " %1; " \ | |
303 | _POST_EFLAGS("0", "3", "2") \ | |
304 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
305 | "=&r" (_tmp) \ | |
306 | : "i" (EFLAGS_MASK)); \ | |
307 | } while (0) | |
308 | ||
309 | /* Instruction has only one explicit operand (no source operand). */ | |
310 | #define emulate_1op(_op, _dst, _eflags) \ | |
311 | do { \ | |
d77c26fc | 312 | switch ((_dst).bytes) { \ |
dda96d8f AK |
313 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
314 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
315 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
316 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
317 | } \ |
318 | } while (0) | |
319 | ||
3f9f53b0 MG |
320 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
321 | do { \ | |
322 | unsigned long _tmp; \ | |
323 | \ | |
324 | __asm__ __volatile__ ( \ | |
325 | _PRE_EFLAGS("0", "4", "1") \ | |
326 | _op _suffix " %5; " \ | |
327 | _POST_EFLAGS("0", "4", "1") \ | |
328 | : "=m" (_eflags), "=&r" (_tmp), \ | |
329 | "+a" (_rax), "+d" (_rdx) \ | |
330 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
331 | "a" (_rax), "d" (_rdx)); \ | |
332 | } while (0) | |
333 | ||
334 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ | |
335 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
336 | do { \ | |
337 | switch((_src).bytes) { \ | |
338 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
339 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
340 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
341 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
342 | } \ | |
343 | } while (0) | |
344 | ||
6aa8b732 AK |
345 | /* Fetch next part of the instruction being emulated. */ |
346 | #define insn_fetch(_type, _size, _eip) \ | |
347 | ({ unsigned long _x; \ | |
62266869 | 348 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 349 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
350 | goto done; \ |
351 | (_eip) += (_size); \ | |
352 | (_type)_x; \ | |
353 | }) | |
354 | ||
414e6277 GN |
355 | #define insn_fetch_arr(_arr, _size, _eip) \ |
356 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
357 | if (rc != X86EMUL_CONTINUE) \ | |
358 | goto done; \ | |
359 | (_eip) += (_size); \ | |
360 | }) | |
361 | ||
ddcb2885 HH |
362 | static inline unsigned long ad_mask(struct decode_cache *c) |
363 | { | |
364 | return (1UL << (c->ad_bytes << 3)) - 1; | |
365 | } | |
366 | ||
6aa8b732 | 367 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
368 | static inline unsigned long |
369 | address_mask(struct decode_cache *c, unsigned long reg) | |
370 | { | |
371 | if (c->ad_bytes == sizeof(unsigned long)) | |
372 | return reg; | |
373 | else | |
374 | return reg & ad_mask(c); | |
375 | } | |
376 | ||
377 | static inline unsigned long | |
378 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
379 | { | |
380 | return base + address_mask(c, reg); | |
381 | } | |
382 | ||
7a957275 HH |
383 | static inline void |
384 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
385 | { | |
386 | if (c->ad_bytes == sizeof(unsigned long)) | |
387 | *reg += inc; | |
388 | else | |
389 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
390 | } | |
6aa8b732 | 391 | |
7a957275 HH |
392 | static inline void jmp_rel(struct decode_cache *c, int rel) |
393 | { | |
394 | register_address_increment(c, &c->eip, rel); | |
395 | } | |
098c937b | 396 | |
7a5b56df AK |
397 | static void set_seg_override(struct decode_cache *c, int seg) |
398 | { | |
399 | c->has_seg_override = true; | |
400 | c->seg_override = seg; | |
401 | } | |
402 | ||
79168fd1 GN |
403 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
404 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
405 | { |
406 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
407 | return 0; | |
408 | ||
79168fd1 | 409 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
410 | } |
411 | ||
412 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 413 | struct x86_emulate_ops *ops, |
7a5b56df AK |
414 | struct decode_cache *c) |
415 | { | |
416 | if (!c->has_seg_override) | |
417 | return 0; | |
418 | ||
79168fd1 | 419 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
420 | } |
421 | ||
79168fd1 GN |
422 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
423 | struct x86_emulate_ops *ops) | |
7a5b56df | 424 | { |
79168fd1 | 425 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
426 | } |
427 | ||
79168fd1 GN |
428 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
429 | struct x86_emulate_ops *ops) | |
7a5b56df | 430 | { |
79168fd1 | 431 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
432 | } |
433 | ||
54b8486f GN |
434 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
435 | u32 error, bool valid) | |
436 | { | |
437 | ctxt->exception = vec; | |
438 | ctxt->error_code = error; | |
439 | ctxt->error_code_valid = valid; | |
440 | ctxt->restart = false; | |
441 | } | |
442 | ||
443 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
444 | { | |
445 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
446 | } | |
447 | ||
448 | static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
449 | int err) | |
450 | { | |
451 | ctxt->cr2 = addr; | |
452 | emulate_exception(ctxt, PF_VECTOR, err, true); | |
453 | } | |
454 | ||
455 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
456 | { | |
457 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
458 | } | |
459 | ||
460 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
461 | { | |
462 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
463 | } | |
464 | ||
62266869 AK |
465 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
466 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 467 | unsigned long eip, u8 *dest) |
62266869 AK |
468 | { |
469 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
470 | int rc; | |
2fb53ad8 | 471 | int size, cur_size; |
62266869 | 472 | |
2fb53ad8 AK |
473 | if (eip == fc->end) { |
474 | cur_size = fc->end - fc->start; | |
475 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
476 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
477 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 478 | if (rc != X86EMUL_CONTINUE) |
62266869 | 479 | return rc; |
2fb53ad8 | 480 | fc->end += size; |
62266869 | 481 | } |
2fb53ad8 | 482 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 483 | return X86EMUL_CONTINUE; |
62266869 AK |
484 | } |
485 | ||
486 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
487 | struct x86_emulate_ops *ops, | |
488 | unsigned long eip, void *dest, unsigned size) | |
489 | { | |
3e2815e9 | 490 | int rc; |
62266869 | 491 | |
eb3c79e6 | 492 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 493 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 494 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
495 | while (size--) { |
496 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 497 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
498 | return rc; |
499 | } | |
3e2815e9 | 500 | return X86EMUL_CONTINUE; |
62266869 AK |
501 | } |
502 | ||
1e3c5cb0 RR |
503 | /* |
504 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
505 | * pointer into the block that addresses the relevant register. | |
506 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
507 | */ | |
508 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
509 | int highbyte_regs) | |
6aa8b732 AK |
510 | { |
511 | void *p; | |
512 | ||
513 | p = ®s[modrm_reg]; | |
514 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
515 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
516 | return p; | |
517 | } | |
518 | ||
519 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
520 | struct x86_emulate_ops *ops, | |
1a6440ae | 521 | ulong addr, |
6aa8b732 AK |
522 | u16 *size, unsigned long *address, int op_bytes) |
523 | { | |
524 | int rc; | |
525 | ||
526 | if (op_bytes == 2) | |
527 | op_bytes = 3; | |
528 | *address = 0; | |
1a6440ae | 529 | rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL); |
1b30eaa8 | 530 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 531 | return rc; |
1a6440ae | 532 | rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL); |
6aa8b732 AK |
533 | return rc; |
534 | } | |
535 | ||
bbe9abbd NK |
536 | static int test_cc(unsigned int condition, unsigned int flags) |
537 | { | |
538 | int rc = 0; | |
539 | ||
540 | switch ((condition & 15) >> 1) { | |
541 | case 0: /* o */ | |
542 | rc |= (flags & EFLG_OF); | |
543 | break; | |
544 | case 1: /* b/c/nae */ | |
545 | rc |= (flags & EFLG_CF); | |
546 | break; | |
547 | case 2: /* z/e */ | |
548 | rc |= (flags & EFLG_ZF); | |
549 | break; | |
550 | case 3: /* be/na */ | |
551 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
552 | break; | |
553 | case 4: /* s */ | |
554 | rc |= (flags & EFLG_SF); | |
555 | break; | |
556 | case 5: /* p/pe */ | |
557 | rc |= (flags & EFLG_PF); | |
558 | break; | |
559 | case 7: /* le/ng */ | |
560 | rc |= (flags & EFLG_ZF); | |
561 | /* fall through */ | |
562 | case 6: /* l/nge */ | |
563 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
564 | break; | |
565 | } | |
566 | ||
567 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
568 | return (!!rc ^ (condition & 1)); | |
569 | } | |
570 | ||
91ff3cb4 AK |
571 | static void fetch_register_operand(struct operand *op) |
572 | { | |
573 | switch (op->bytes) { | |
574 | case 1: | |
575 | op->val = *(u8 *)op->addr.reg; | |
576 | break; | |
577 | case 2: | |
578 | op->val = *(u16 *)op->addr.reg; | |
579 | break; | |
580 | case 4: | |
581 | op->val = *(u32 *)op->addr.reg; | |
582 | break; | |
583 | case 8: | |
584 | op->val = *(u64 *)op->addr.reg; | |
585 | break; | |
586 | } | |
587 | } | |
588 | ||
3c118e24 AK |
589 | static void decode_register_operand(struct operand *op, |
590 | struct decode_cache *c, | |
3c118e24 AK |
591 | int inhibit_bytereg) |
592 | { | |
33615aa9 | 593 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 594 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
595 | |
596 | if (!(c->d & ModRM)) | |
597 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
598 | op->type = OP_REG; |
599 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 600 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
601 | op->bytes = 1; |
602 | } else { | |
1a6440ae | 603 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 604 | op->bytes = c->op_bytes; |
3c118e24 | 605 | } |
91ff3cb4 | 606 | fetch_register_operand(op); |
3c118e24 AK |
607 | op->orig_val = op->val; |
608 | } | |
609 | ||
1c73ef66 | 610 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
611 | struct x86_emulate_ops *ops, |
612 | struct operand *op) | |
1c73ef66 AK |
613 | { |
614 | struct decode_cache *c = &ctxt->decode; | |
615 | u8 sib; | |
f5b4edcd | 616 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 617 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 618 | ulong modrm_ea = 0; |
1c73ef66 AK |
619 | |
620 | if (c->rex_prefix) { | |
621 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
622 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
623 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
624 | } | |
625 | ||
626 | c->modrm = insn_fetch(u8, 1, c->eip); | |
627 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
628 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
629 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 630 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
631 | |
632 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
633 | op->type = OP_REG; |
634 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
635 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 636 | c->regs, c->d & ByteOp); |
2dbd0dd7 | 637 | fetch_register_operand(op); |
1c73ef66 AK |
638 | return rc; |
639 | } | |
640 | ||
2dbd0dd7 AK |
641 | op->type = OP_MEM; |
642 | ||
1c73ef66 AK |
643 | if (c->ad_bytes == 2) { |
644 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
645 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
646 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
647 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
648 | ||
649 | /* 16-bit ModR/M decode. */ | |
650 | switch (c->modrm_mod) { | |
651 | case 0: | |
652 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 653 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
654 | break; |
655 | case 1: | |
2dbd0dd7 | 656 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
657 | break; |
658 | case 2: | |
2dbd0dd7 | 659 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
660 | break; |
661 | } | |
662 | switch (c->modrm_rm) { | |
663 | case 0: | |
2dbd0dd7 | 664 | modrm_ea += bx + si; |
1c73ef66 AK |
665 | break; |
666 | case 1: | |
2dbd0dd7 | 667 | modrm_ea += bx + di; |
1c73ef66 AK |
668 | break; |
669 | case 2: | |
2dbd0dd7 | 670 | modrm_ea += bp + si; |
1c73ef66 AK |
671 | break; |
672 | case 3: | |
2dbd0dd7 | 673 | modrm_ea += bp + di; |
1c73ef66 AK |
674 | break; |
675 | case 4: | |
2dbd0dd7 | 676 | modrm_ea += si; |
1c73ef66 AK |
677 | break; |
678 | case 5: | |
2dbd0dd7 | 679 | modrm_ea += di; |
1c73ef66 AK |
680 | break; |
681 | case 6: | |
682 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 683 | modrm_ea += bp; |
1c73ef66 AK |
684 | break; |
685 | case 7: | |
2dbd0dd7 | 686 | modrm_ea += bx; |
1c73ef66 AK |
687 | break; |
688 | } | |
689 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
690 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 691 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 692 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
693 | } else { |
694 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 695 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
696 | sib = insn_fetch(u8, 1, c->eip); |
697 | index_reg |= (sib >> 3) & 7; | |
698 | base_reg |= sib & 7; | |
699 | scale = sib >> 6; | |
700 | ||
dc71d0f1 | 701 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 702 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 703 | else |
2dbd0dd7 | 704 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 705 | if (index_reg != 4) |
2dbd0dd7 | 706 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
707 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
708 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 709 | c->rip_relative = 1; |
84411d85 | 710 | } else |
2dbd0dd7 | 711 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
712 | switch (c->modrm_mod) { |
713 | case 0: | |
714 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 715 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
716 | break; |
717 | case 1: | |
2dbd0dd7 | 718 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
719 | break; |
720 | case 2: | |
2dbd0dd7 | 721 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
722 | break; |
723 | } | |
724 | } | |
2dbd0dd7 | 725 | op->addr.mem = modrm_ea; |
1c73ef66 AK |
726 | done: |
727 | return rc; | |
728 | } | |
729 | ||
730 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
731 | struct x86_emulate_ops *ops, |
732 | struct operand *op) | |
1c73ef66 AK |
733 | { |
734 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 735 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 736 | |
2dbd0dd7 | 737 | op->type = OP_MEM; |
1c73ef66 AK |
738 | switch (c->ad_bytes) { |
739 | case 2: | |
2dbd0dd7 | 740 | op->addr.mem = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
741 | break; |
742 | case 4: | |
2dbd0dd7 | 743 | op->addr.mem = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
744 | break; |
745 | case 8: | |
2dbd0dd7 | 746 | op->addr.mem = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
747 | break; |
748 | } | |
749 | done: | |
750 | return rc; | |
751 | } | |
752 | ||
35c843c4 WY |
753 | static void fetch_bit_operand(struct decode_cache *c) |
754 | { | |
755 | long sv, mask; | |
756 | ||
3885f18f | 757 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
758 | mask = ~(c->dst.bytes * 8 - 1); |
759 | ||
760 | if (c->src.bytes == 2) | |
761 | sv = (s16)c->src.val & (s16)mask; | |
762 | else if (c->src.bytes == 4) | |
763 | sv = (s32)c->src.val & (s32)mask; | |
764 | ||
765 | c->dst.addr.mem += (sv >> 3); | |
766 | } | |
ba7ff2b7 WY |
767 | |
768 | /* only subword offset */ | |
769 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
770 | } |
771 | ||
dde7e6d1 AK |
772 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
773 | struct x86_emulate_ops *ops, | |
774 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 775 | { |
dde7e6d1 AK |
776 | int rc; |
777 | struct read_cache *mc = &ctxt->decode.mem_read; | |
778 | u32 err; | |
6aa8b732 | 779 | |
dde7e6d1 AK |
780 | while (size) { |
781 | int n = min(size, 8u); | |
782 | size -= n; | |
783 | if (mc->pos < mc->end) | |
784 | goto read_cached; | |
5cd21917 | 785 | |
dde7e6d1 AK |
786 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
787 | ctxt->vcpu); | |
788 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
789 | emulate_pf(ctxt, addr, err); | |
790 | if (rc != X86EMUL_CONTINUE) | |
791 | return rc; | |
792 | mc->end += n; | |
6aa8b732 | 793 | |
dde7e6d1 AK |
794 | read_cached: |
795 | memcpy(dest, mc->data + mc->pos, n); | |
796 | mc->pos += n; | |
797 | dest += n; | |
798 | addr += n; | |
6aa8b732 | 799 | } |
dde7e6d1 AK |
800 | return X86EMUL_CONTINUE; |
801 | } | |
6aa8b732 | 802 | |
dde7e6d1 AK |
803 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
804 | struct x86_emulate_ops *ops, | |
805 | unsigned int size, unsigned short port, | |
806 | void *dest) | |
807 | { | |
808 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 809 | |
dde7e6d1 AK |
810 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
811 | struct decode_cache *c = &ctxt->decode; | |
812 | unsigned int in_page, n; | |
813 | unsigned int count = c->rep_prefix ? | |
814 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
815 | in_page = (ctxt->eflags & EFLG_DF) ? | |
816 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
817 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
818 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
819 | count); | |
820 | if (n == 0) | |
821 | n = 1; | |
822 | rc->pos = rc->end = 0; | |
823 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
824 | return 0; | |
825 | rc->end = n * size; | |
6aa8b732 AK |
826 | } |
827 | ||
dde7e6d1 AK |
828 | memcpy(dest, rc->data + rc->pos, size); |
829 | rc->pos += size; | |
830 | return 1; | |
831 | } | |
6aa8b732 | 832 | |
dde7e6d1 AK |
833 | static u32 desc_limit_scaled(struct desc_struct *desc) |
834 | { | |
835 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 836 | |
dde7e6d1 AK |
837 | return desc->g ? (limit << 12) | 0xfff : limit; |
838 | } | |
6aa8b732 | 839 | |
dde7e6d1 AK |
840 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
841 | struct x86_emulate_ops *ops, | |
842 | u16 selector, struct desc_ptr *dt) | |
843 | { | |
844 | if (selector & 1 << 2) { | |
845 | struct desc_struct desc; | |
846 | memset (dt, 0, sizeof *dt); | |
847 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
848 | return; | |
e09d082c | 849 | |
dde7e6d1 AK |
850 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
851 | dt->address = get_desc_base(&desc); | |
852 | } else | |
853 | ops->get_gdt(dt, ctxt->vcpu); | |
854 | } | |
120df890 | 855 | |
dde7e6d1 AK |
856 | /* allowed just for 8 bytes segments */ |
857 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
858 | struct x86_emulate_ops *ops, | |
859 | u16 selector, struct desc_struct *desc) | |
860 | { | |
861 | struct desc_ptr dt; | |
862 | u16 index = selector >> 3; | |
863 | int ret; | |
864 | u32 err; | |
865 | ulong addr; | |
120df890 | 866 | |
dde7e6d1 | 867 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 868 | |
dde7e6d1 AK |
869 | if (dt.size < index * 8 + 7) { |
870 | emulate_gp(ctxt, selector & 0xfffc); | |
871 | return X86EMUL_PROPAGATE_FAULT; | |
e09d082c | 872 | } |
dde7e6d1 AK |
873 | addr = dt.address + index * 8; |
874 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
875 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
876 | emulate_pf(ctxt, addr, err); | |
e09d082c | 877 | |
dde7e6d1 AK |
878 | return ret; |
879 | } | |
ef65c889 | 880 | |
dde7e6d1 AK |
881 | /* allowed just for 8 bytes segments */ |
882 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
883 | struct x86_emulate_ops *ops, | |
884 | u16 selector, struct desc_struct *desc) | |
885 | { | |
886 | struct desc_ptr dt; | |
887 | u16 index = selector >> 3; | |
888 | u32 err; | |
889 | ulong addr; | |
890 | int ret; | |
6aa8b732 | 891 | |
dde7e6d1 | 892 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 893 | |
dde7e6d1 AK |
894 | if (dt.size < index * 8 + 7) { |
895 | emulate_gp(ctxt, selector & 0xfffc); | |
896 | return X86EMUL_PROPAGATE_FAULT; | |
897 | } | |
6aa8b732 | 898 | |
dde7e6d1 AK |
899 | addr = dt.address + index * 8; |
900 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
901 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
902 | emulate_pf(ctxt, addr, err); | |
c7e75a3d | 903 | |
dde7e6d1 AK |
904 | return ret; |
905 | } | |
c7e75a3d | 906 | |
dde7e6d1 AK |
907 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
908 | struct x86_emulate_ops *ops, | |
909 | u16 selector, int seg) | |
910 | { | |
911 | struct desc_struct seg_desc; | |
912 | u8 dpl, rpl, cpl; | |
913 | unsigned err_vec = GP_VECTOR; | |
914 | u32 err_code = 0; | |
915 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
916 | int ret; | |
69f55cb1 | 917 | |
dde7e6d1 | 918 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 919 | |
dde7e6d1 AK |
920 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
921 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
922 | /* set real mode segment descriptor */ | |
923 | set_desc_base(&seg_desc, selector << 4); | |
924 | set_desc_limit(&seg_desc, 0xffff); | |
925 | seg_desc.type = 3; | |
926 | seg_desc.p = 1; | |
927 | seg_desc.s = 1; | |
928 | goto load; | |
929 | } | |
930 | ||
931 | /* NULL selector is not valid for TR, CS and SS */ | |
932 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
933 | && null_selector) | |
934 | goto exception; | |
935 | ||
936 | /* TR should be in GDT only */ | |
937 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
938 | goto exception; | |
939 | ||
940 | if (null_selector) /* for NULL selector skip all following checks */ | |
941 | goto load; | |
942 | ||
943 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
944 | if (ret != X86EMUL_CONTINUE) | |
945 | return ret; | |
946 | ||
947 | err_code = selector & 0xfffc; | |
948 | err_vec = GP_VECTOR; | |
949 | ||
950 | /* can't load system descriptor into segment selecor */ | |
951 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
952 | goto exception; | |
953 | ||
954 | if (!seg_desc.p) { | |
955 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
956 | goto exception; | |
957 | } | |
958 | ||
959 | rpl = selector & 3; | |
960 | dpl = seg_desc.dpl; | |
961 | cpl = ops->cpl(ctxt->vcpu); | |
962 | ||
963 | switch (seg) { | |
964 | case VCPU_SREG_SS: | |
965 | /* | |
966 | * segment is not a writable data segment or segment | |
967 | * selector's RPL != CPL or segment selector's RPL != CPL | |
968 | */ | |
969 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
970 | goto exception; | |
6aa8b732 | 971 | break; |
dde7e6d1 AK |
972 | case VCPU_SREG_CS: |
973 | if (!(seg_desc.type & 8)) | |
974 | goto exception; | |
975 | ||
976 | if (seg_desc.type & 4) { | |
977 | /* conforming */ | |
978 | if (dpl > cpl) | |
979 | goto exception; | |
980 | } else { | |
981 | /* nonconforming */ | |
982 | if (rpl > cpl || dpl != cpl) | |
983 | goto exception; | |
984 | } | |
985 | /* CS(RPL) <- CPL */ | |
986 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 987 | break; |
dde7e6d1 AK |
988 | case VCPU_SREG_TR: |
989 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
990 | goto exception; | |
991 | break; | |
992 | case VCPU_SREG_LDTR: | |
993 | if (seg_desc.s || seg_desc.type != 2) | |
994 | goto exception; | |
995 | break; | |
996 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 997 | /* |
dde7e6d1 AK |
998 | * segment is not a data or readable code segment or |
999 | * ((segment is a data or nonconforming code segment) | |
1000 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1001 | */ |
dde7e6d1 AK |
1002 | if ((seg_desc.type & 0xa) == 0x8 || |
1003 | (((seg_desc.type & 0xc) != 0xc) && | |
1004 | (rpl > dpl && cpl > dpl))) | |
1005 | goto exception; | |
6aa8b732 | 1006 | break; |
dde7e6d1 AK |
1007 | } |
1008 | ||
1009 | if (seg_desc.s) { | |
1010 | /* mark segment as accessed */ | |
1011 | seg_desc.type |= 1; | |
1012 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1013 | if (ret != X86EMUL_CONTINUE) | |
1014 | return ret; | |
1015 | } | |
1016 | load: | |
1017 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1018 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1019 | return X86EMUL_CONTINUE; | |
1020 | exception: | |
1021 | emulate_exception(ctxt, err_vec, err_code, true); | |
1022 | return X86EMUL_PROPAGATE_FAULT; | |
1023 | } | |
1024 | ||
31be40b3 WY |
1025 | static void write_register_operand(struct operand *op) |
1026 | { | |
1027 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1028 | switch (op->bytes) { | |
1029 | case 1: | |
1030 | *(u8 *)op->addr.reg = (u8)op->val; | |
1031 | break; | |
1032 | case 2: | |
1033 | *(u16 *)op->addr.reg = (u16)op->val; | |
1034 | break; | |
1035 | case 4: | |
1036 | *op->addr.reg = (u32)op->val; | |
1037 | break; /* 64b: zero-extend */ | |
1038 | case 8: | |
1039 | *op->addr.reg = op->val; | |
1040 | break; | |
1041 | } | |
1042 | } | |
1043 | ||
dde7e6d1 AK |
1044 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1045 | struct x86_emulate_ops *ops) | |
1046 | { | |
1047 | int rc; | |
1048 | struct decode_cache *c = &ctxt->decode; | |
1049 | u32 err; | |
1050 | ||
1051 | switch (c->dst.type) { | |
1052 | case OP_REG: | |
31be40b3 | 1053 | write_register_operand(&c->dst); |
6aa8b732 | 1054 | break; |
dde7e6d1 AK |
1055 | case OP_MEM: |
1056 | if (c->lock_prefix) | |
1057 | rc = ops->cmpxchg_emulated( | |
1a6440ae | 1058 | c->dst.addr.mem, |
dde7e6d1 AK |
1059 | &c->dst.orig_val, |
1060 | &c->dst.val, | |
1061 | c->dst.bytes, | |
1062 | &err, | |
1063 | ctxt->vcpu); | |
341de7e3 | 1064 | else |
dde7e6d1 | 1065 | rc = ops->write_emulated( |
1a6440ae | 1066 | c->dst.addr.mem, |
dde7e6d1 AK |
1067 | &c->dst.val, |
1068 | c->dst.bytes, | |
1069 | &err, | |
1070 | ctxt->vcpu); | |
1071 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1a6440ae | 1072 | emulate_pf(ctxt, c->dst.addr.mem, err); |
dde7e6d1 AK |
1073 | if (rc != X86EMUL_CONTINUE) |
1074 | return rc; | |
a682e354 | 1075 | break; |
dde7e6d1 AK |
1076 | case OP_NONE: |
1077 | /* no writeback */ | |
414e6277 | 1078 | break; |
dde7e6d1 | 1079 | default: |
414e6277 | 1080 | break; |
6aa8b732 | 1081 | } |
dde7e6d1 AK |
1082 | return X86EMUL_CONTINUE; |
1083 | } | |
6aa8b732 | 1084 | |
dde7e6d1 AK |
1085 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1086 | struct x86_emulate_ops *ops) | |
1087 | { | |
1088 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1089 | |
dde7e6d1 AK |
1090 | c->dst.type = OP_MEM; |
1091 | c->dst.bytes = c->op_bytes; | |
1092 | c->dst.val = c->src.val; | |
1093 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
1a6440ae AK |
1094 | c->dst.addr.mem = register_address(c, ss_base(ctxt, ops), |
1095 | c->regs[VCPU_REGS_RSP]); | |
dde7e6d1 | 1096 | } |
69f55cb1 | 1097 | |
dde7e6d1 AK |
1098 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1099 | struct x86_emulate_ops *ops, | |
1100 | void *dest, int len) | |
1101 | { | |
1102 | struct decode_cache *c = &ctxt->decode; | |
1103 | int rc; | |
8b4caf66 | 1104 | |
dde7e6d1 AK |
1105 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
1106 | c->regs[VCPU_REGS_RSP]), | |
1107 | dest, len); | |
1108 | if (rc != X86EMUL_CONTINUE) | |
1109 | return rc; | |
1110 | ||
1111 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1112 | return rc; | |
8b4caf66 LV |
1113 | } |
1114 | ||
dde7e6d1 AK |
1115 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1116 | struct x86_emulate_ops *ops, | |
1117 | void *dest, int len) | |
9de41573 GN |
1118 | { |
1119 | int rc; | |
dde7e6d1 AK |
1120 | unsigned long val, change_mask; |
1121 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1122 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1123 | |
dde7e6d1 AK |
1124 | rc = emulate_pop(ctxt, ops, &val, len); |
1125 | if (rc != X86EMUL_CONTINUE) | |
1126 | return rc; | |
9de41573 | 1127 | |
dde7e6d1 AK |
1128 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1129 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1130 | |
dde7e6d1 AK |
1131 | switch(ctxt->mode) { |
1132 | case X86EMUL_MODE_PROT64: | |
1133 | case X86EMUL_MODE_PROT32: | |
1134 | case X86EMUL_MODE_PROT16: | |
1135 | if (cpl == 0) | |
1136 | change_mask |= EFLG_IOPL; | |
1137 | if (cpl <= iopl) | |
1138 | change_mask |= EFLG_IF; | |
1139 | break; | |
1140 | case X86EMUL_MODE_VM86: | |
1141 | if (iopl < 3) { | |
1142 | emulate_gp(ctxt, 0); | |
1143 | return X86EMUL_PROPAGATE_FAULT; | |
1144 | } | |
1145 | change_mask |= EFLG_IF; | |
1146 | break; | |
1147 | default: /* real mode */ | |
1148 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1149 | break; | |
9de41573 | 1150 | } |
dde7e6d1 AK |
1151 | |
1152 | *(unsigned long *)dest = | |
1153 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1154 | ||
1155 | return rc; | |
9de41573 GN |
1156 | } |
1157 | ||
dde7e6d1 AK |
1158 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1159 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1160 | { |
dde7e6d1 | 1161 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1162 | |
dde7e6d1 | 1163 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1164 | |
dde7e6d1 | 1165 | emulate_push(ctxt, ops); |
7b262e90 GN |
1166 | } |
1167 | ||
dde7e6d1 AK |
1168 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1169 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1170 | { |
dde7e6d1 AK |
1171 | struct decode_cache *c = &ctxt->decode; |
1172 | unsigned long selector; | |
1173 | int rc; | |
38ba30ba | 1174 | |
dde7e6d1 AK |
1175 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1176 | if (rc != X86EMUL_CONTINUE) | |
1177 | return rc; | |
1178 | ||
1179 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1180 | return rc; | |
38ba30ba GN |
1181 | } |
1182 | ||
dde7e6d1 AK |
1183 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1184 | struct x86_emulate_ops *ops) | |
38ba30ba | 1185 | { |
dde7e6d1 AK |
1186 | struct decode_cache *c = &ctxt->decode; |
1187 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1188 | int rc = X86EMUL_CONTINUE; | |
1189 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1190 | |
dde7e6d1 AK |
1191 | while (reg <= VCPU_REGS_RDI) { |
1192 | (reg == VCPU_REGS_RSP) ? | |
1193 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1194 | |
dde7e6d1 | 1195 | emulate_push(ctxt, ops); |
38ba30ba | 1196 | |
dde7e6d1 AK |
1197 | rc = writeback(ctxt, ops); |
1198 | if (rc != X86EMUL_CONTINUE) | |
1199 | return rc; | |
38ba30ba | 1200 | |
dde7e6d1 | 1201 | ++reg; |
38ba30ba | 1202 | } |
38ba30ba | 1203 | |
dde7e6d1 AK |
1204 | /* Disable writeback. */ |
1205 | c->dst.type = OP_NONE; | |
1206 | ||
1207 | return rc; | |
38ba30ba GN |
1208 | } |
1209 | ||
dde7e6d1 AK |
1210 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1211 | struct x86_emulate_ops *ops) | |
38ba30ba | 1212 | { |
dde7e6d1 AK |
1213 | struct decode_cache *c = &ctxt->decode; |
1214 | int rc = X86EMUL_CONTINUE; | |
1215 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1216 | |
dde7e6d1 AK |
1217 | while (reg >= VCPU_REGS_RAX) { |
1218 | if (reg == VCPU_REGS_RSP) { | |
1219 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1220 | c->op_bytes); | |
1221 | --reg; | |
1222 | } | |
38ba30ba | 1223 | |
dde7e6d1 AK |
1224 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1225 | if (rc != X86EMUL_CONTINUE) | |
1226 | break; | |
1227 | --reg; | |
38ba30ba | 1228 | } |
dde7e6d1 | 1229 | return rc; |
38ba30ba GN |
1230 | } |
1231 | ||
6e154e56 MG |
1232 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1233 | struct x86_emulate_ops *ops, int irq) | |
1234 | { | |
1235 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1236 | int rc; |
6e154e56 MG |
1237 | struct desc_ptr dt; |
1238 | gva_t cs_addr; | |
1239 | gva_t eip_addr; | |
1240 | u16 cs, eip; | |
1241 | u32 err; | |
1242 | ||
1243 | /* TODO: Add limit checks */ | |
1244 | c->src.val = ctxt->eflags; | |
1245 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1246 | rc = writeback(ctxt, ops); |
1247 | if (rc != X86EMUL_CONTINUE) | |
1248 | return rc; | |
6e154e56 MG |
1249 | |
1250 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1251 | ||
1252 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1253 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1254 | rc = writeback(ctxt, ops); |
1255 | if (rc != X86EMUL_CONTINUE) | |
1256 | return rc; | |
6e154e56 MG |
1257 | |
1258 | c->src.val = c->eip; | |
1259 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1260 | rc = writeback(ctxt, ops); |
1261 | if (rc != X86EMUL_CONTINUE) | |
1262 | return rc; | |
1263 | ||
1264 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1265 | |
1266 | ops->get_idt(&dt, ctxt->vcpu); | |
1267 | ||
1268 | eip_addr = dt.address + (irq << 2); | |
1269 | cs_addr = dt.address + (irq << 2) + 2; | |
1270 | ||
1271 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err); | |
1272 | if (rc != X86EMUL_CONTINUE) | |
1273 | return rc; | |
1274 | ||
1275 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err); | |
1276 | if (rc != X86EMUL_CONTINUE) | |
1277 | return rc; | |
1278 | ||
1279 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1280 | if (rc != X86EMUL_CONTINUE) | |
1281 | return rc; | |
1282 | ||
1283 | c->eip = eip; | |
1284 | ||
1285 | return rc; | |
1286 | } | |
1287 | ||
1288 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1289 | struct x86_emulate_ops *ops, int irq) | |
1290 | { | |
1291 | switch(ctxt->mode) { | |
1292 | case X86EMUL_MODE_REAL: | |
1293 | return emulate_int_real(ctxt, ops, irq); | |
1294 | case X86EMUL_MODE_VM86: | |
1295 | case X86EMUL_MODE_PROT16: | |
1296 | case X86EMUL_MODE_PROT32: | |
1297 | case X86EMUL_MODE_PROT64: | |
1298 | default: | |
1299 | /* Protected mode interrupts unimplemented yet */ | |
1300 | return X86EMUL_UNHANDLEABLE; | |
1301 | } | |
1302 | } | |
1303 | ||
dde7e6d1 AK |
1304 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1305 | struct x86_emulate_ops *ops) | |
38ba30ba | 1306 | { |
dde7e6d1 AK |
1307 | struct decode_cache *c = &ctxt->decode; |
1308 | int rc = X86EMUL_CONTINUE; | |
1309 | unsigned long temp_eip = 0; | |
1310 | unsigned long temp_eflags = 0; | |
1311 | unsigned long cs = 0; | |
1312 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1313 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1314 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1315 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1316 | |
dde7e6d1 | 1317 | /* TODO: Add stack limit check */ |
38ba30ba | 1318 | |
dde7e6d1 | 1319 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1320 | |
dde7e6d1 AK |
1321 | if (rc != X86EMUL_CONTINUE) |
1322 | return rc; | |
38ba30ba | 1323 | |
dde7e6d1 AK |
1324 | if (temp_eip & ~0xffff) { |
1325 | emulate_gp(ctxt, 0); | |
1326 | return X86EMUL_PROPAGATE_FAULT; | |
1327 | } | |
38ba30ba | 1328 | |
dde7e6d1 | 1329 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1330 | |
dde7e6d1 AK |
1331 | if (rc != X86EMUL_CONTINUE) |
1332 | return rc; | |
38ba30ba | 1333 | |
dde7e6d1 | 1334 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1335 | |
dde7e6d1 AK |
1336 | if (rc != X86EMUL_CONTINUE) |
1337 | return rc; | |
38ba30ba | 1338 | |
dde7e6d1 | 1339 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1340 | |
dde7e6d1 AK |
1341 | if (rc != X86EMUL_CONTINUE) |
1342 | return rc; | |
38ba30ba | 1343 | |
dde7e6d1 | 1344 | c->eip = temp_eip; |
38ba30ba | 1345 | |
38ba30ba | 1346 | |
dde7e6d1 AK |
1347 | if (c->op_bytes == 4) |
1348 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1349 | else if (c->op_bytes == 2) { | |
1350 | ctxt->eflags &= ~0xffff; | |
1351 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1352 | } |
dde7e6d1 AK |
1353 | |
1354 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1355 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1356 | ||
1357 | return rc; | |
38ba30ba GN |
1358 | } |
1359 | ||
dde7e6d1 AK |
1360 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1361 | struct x86_emulate_ops* ops) | |
c37eda13 | 1362 | { |
dde7e6d1 AK |
1363 | switch(ctxt->mode) { |
1364 | case X86EMUL_MODE_REAL: | |
1365 | return emulate_iret_real(ctxt, ops); | |
1366 | case X86EMUL_MODE_VM86: | |
1367 | case X86EMUL_MODE_PROT16: | |
1368 | case X86EMUL_MODE_PROT32: | |
1369 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1370 | default: |
dde7e6d1 AK |
1371 | /* iret from protected mode unimplemented yet */ |
1372 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1373 | } |
c37eda13 WY |
1374 | } |
1375 | ||
dde7e6d1 | 1376 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1377 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1378 | { |
1379 | struct decode_cache *c = &ctxt->decode; | |
1380 | ||
dde7e6d1 | 1381 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1382 | } |
1383 | ||
dde7e6d1 | 1384 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1385 | { |
05f086f8 | 1386 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1387 | switch (c->modrm_reg) { |
1388 | case 0: /* rol */ | |
05f086f8 | 1389 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1390 | break; |
1391 | case 1: /* ror */ | |
05f086f8 | 1392 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1393 | break; |
1394 | case 2: /* rcl */ | |
05f086f8 | 1395 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1396 | break; |
1397 | case 3: /* rcr */ | |
05f086f8 | 1398 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1399 | break; |
1400 | case 4: /* sal/shl */ | |
1401 | case 6: /* sal/shl */ | |
05f086f8 | 1402 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1403 | break; |
1404 | case 5: /* shr */ | |
05f086f8 | 1405 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1406 | break; |
1407 | case 7: /* sar */ | |
05f086f8 | 1408 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1409 | break; |
1410 | } | |
1411 | } | |
1412 | ||
1413 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1414 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1415 | { |
1416 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1417 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1418 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
8cdbd2c9 LV |
1419 | |
1420 | switch (c->modrm_reg) { | |
1421 | case 0 ... 1: /* test */ | |
05f086f8 | 1422 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1423 | break; |
1424 | case 2: /* not */ | |
1425 | c->dst.val = ~c->dst.val; | |
1426 | break; | |
1427 | case 3: /* neg */ | |
05f086f8 | 1428 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1429 | break; |
3f9f53b0 MG |
1430 | case 4: /* mul */ |
1431 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1432 | break; | |
1433 | case 5: /* imul */ | |
1434 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1435 | break; | |
1436 | case 6: /* div */ | |
1437 | emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags); | |
1438 | break; | |
1439 | case 7: /* idiv */ | |
1440 | emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags); | |
1441 | break; | |
8cdbd2c9 | 1442 | default: |
8c5eee30 | 1443 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1444 | } |
8c5eee30 | 1445 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1446 | } |
1447 | ||
1448 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1449 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1450 | { |
1451 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1452 | |
1453 | switch (c->modrm_reg) { | |
1454 | case 0: /* inc */ | |
05f086f8 | 1455 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1456 | break; |
1457 | case 1: /* dec */ | |
05f086f8 | 1458 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1459 | break; |
d19292e4 MG |
1460 | case 2: /* call near abs */ { |
1461 | long int old_eip; | |
1462 | old_eip = c->eip; | |
1463 | c->eip = c->src.val; | |
1464 | c->src.val = old_eip; | |
79168fd1 | 1465 | emulate_push(ctxt, ops); |
d19292e4 MG |
1466 | break; |
1467 | } | |
8cdbd2c9 | 1468 | case 4: /* jmp abs */ |
fd60754e | 1469 | c->eip = c->src.val; |
8cdbd2c9 LV |
1470 | break; |
1471 | case 6: /* push */ | |
79168fd1 | 1472 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1473 | break; |
8cdbd2c9 | 1474 | } |
1b30eaa8 | 1475 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1476 | } |
1477 | ||
1478 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1479 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1480 | { |
1481 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1482 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1483 | |
1484 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1485 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1486 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1487 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1488 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1489 | } else { |
16518d5a AK |
1490 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1491 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1492 | |
05f086f8 | 1493 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1494 | } |
1b30eaa8 | 1495 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1496 | } |
1497 | ||
a77ab5ea AK |
1498 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1499 | struct x86_emulate_ops *ops) | |
1500 | { | |
1501 | struct decode_cache *c = &ctxt->decode; | |
1502 | int rc; | |
1503 | unsigned long cs; | |
1504 | ||
1505 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1506 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1507 | return rc; |
1508 | if (c->op_bytes == 4) | |
1509 | c->eip = (u32)c->eip; | |
1510 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1511 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1512 | return rc; |
2e873022 | 1513 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1514 | return rc; |
1515 | } | |
1516 | ||
09b5f4d3 WY |
1517 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, |
1518 | struct x86_emulate_ops *ops, int seg) | |
1519 | { | |
1520 | struct decode_cache *c = &ctxt->decode; | |
1521 | unsigned short sel; | |
1522 | int rc; | |
1523 | ||
1524 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
1525 | ||
1526 | rc = load_segment_descriptor(ctxt, ops, sel, seg); | |
1527 | if (rc != X86EMUL_CONTINUE) | |
1528 | return rc; | |
1529 | ||
1530 | c->dst.val = c->src.val; | |
1531 | return rc; | |
1532 | } | |
1533 | ||
e66bb2cc AP |
1534 | static inline void |
1535 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1536 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1537 | struct desc_struct *ss) | |
e66bb2cc | 1538 | { |
79168fd1 GN |
1539 | memset(cs, 0, sizeof(struct desc_struct)); |
1540 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1541 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1542 | |
1543 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1544 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1545 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1546 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1547 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1548 | cs->s = 1; | |
1549 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1550 | cs->p = 1; |
1551 | cs->d = 1; | |
e66bb2cc | 1552 | |
79168fd1 GN |
1553 | set_desc_base(ss, 0); /* flat segment */ |
1554 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1555 | ss->g = 1; /* 4kb granularity */ |
1556 | ss->s = 1; | |
1557 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1558 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1559 | ss->dpl = 0; |
79168fd1 | 1560 | ss->p = 1; |
e66bb2cc AP |
1561 | } |
1562 | ||
1563 | static int | |
3fb1b5db | 1564 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1565 | { |
1566 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1567 | struct desc_struct cs, ss; |
e66bb2cc | 1568 | u64 msr_data; |
79168fd1 | 1569 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1570 | |
1571 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1572 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1573 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1574 | emulate_ud(ctxt); |
2e901c4c GN |
1575 | return X86EMUL_PROPAGATE_FAULT; |
1576 | } | |
e66bb2cc | 1577 | |
79168fd1 | 1578 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1579 | |
3fb1b5db | 1580 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1581 | msr_data >>= 32; |
79168fd1 GN |
1582 | cs_sel = (u16)(msr_data & 0xfffc); |
1583 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1584 | |
1585 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1586 | cs.d = 0; |
e66bb2cc AP |
1587 | cs.l = 1; |
1588 | } | |
79168fd1 GN |
1589 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1590 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1591 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1592 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1593 | |
1594 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1595 | if (is_long_mode(ctxt->vcpu)) { | |
1596 | #ifdef CONFIG_X86_64 | |
1597 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1598 | ||
3fb1b5db GN |
1599 | ops->get_msr(ctxt->vcpu, |
1600 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1601 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1602 | c->eip = msr_data; |
1603 | ||
3fb1b5db | 1604 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1605 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1606 | #endif | |
1607 | } else { | |
1608 | /* legacy mode */ | |
3fb1b5db | 1609 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1610 | c->eip = (u32)msr_data; |
1611 | ||
1612 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1613 | } | |
1614 | ||
e54cfa97 | 1615 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1616 | } |
1617 | ||
8c604352 | 1618 | static int |
3fb1b5db | 1619 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1620 | { |
1621 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1622 | struct desc_struct cs, ss; |
8c604352 | 1623 | u64 msr_data; |
79168fd1 | 1624 | u16 cs_sel, ss_sel; |
8c604352 | 1625 | |
a0044755 GN |
1626 | /* inject #GP if in real mode */ |
1627 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 1628 | emulate_gp(ctxt, 0); |
2e901c4c | 1629 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1630 | } |
1631 | ||
1632 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1633 | * Therefore, we inject an #UD. | |
1634 | */ | |
2e901c4c | 1635 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 1636 | emulate_ud(ctxt); |
2e901c4c GN |
1637 | return X86EMUL_PROPAGATE_FAULT; |
1638 | } | |
8c604352 | 1639 | |
79168fd1 | 1640 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1641 | |
3fb1b5db | 1642 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1643 | switch (ctxt->mode) { |
1644 | case X86EMUL_MODE_PROT32: | |
1645 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 1646 | emulate_gp(ctxt, 0); |
e54cfa97 | 1647 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1648 | } |
1649 | break; | |
1650 | case X86EMUL_MODE_PROT64: | |
1651 | if (msr_data == 0x0) { | |
54b8486f | 1652 | emulate_gp(ctxt, 0); |
e54cfa97 | 1653 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1654 | } |
1655 | break; | |
1656 | } | |
1657 | ||
1658 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1659 | cs_sel = (u16)msr_data; |
1660 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1661 | ss_sel = cs_sel + 8; | |
1662 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1663 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1664 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1665 | cs.d = 0; |
8c604352 AP |
1666 | cs.l = 1; |
1667 | } | |
1668 | ||
79168fd1 GN |
1669 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1670 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1671 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1672 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 1673 | |
3fb1b5db | 1674 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1675 | c->eip = msr_data; |
1676 | ||
3fb1b5db | 1677 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1678 | c->regs[VCPU_REGS_RSP] = msr_data; |
1679 | ||
e54cfa97 | 1680 | return X86EMUL_CONTINUE; |
8c604352 AP |
1681 | } |
1682 | ||
4668f050 | 1683 | static int |
3fb1b5db | 1684 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1685 | { |
1686 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1687 | struct desc_struct cs, ss; |
4668f050 AP |
1688 | u64 msr_data; |
1689 | int usermode; | |
79168fd1 | 1690 | u16 cs_sel, ss_sel; |
4668f050 | 1691 | |
a0044755 GN |
1692 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1693 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1694 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1695 | emulate_gp(ctxt, 0); |
2e901c4c | 1696 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1697 | } |
1698 | ||
79168fd1 | 1699 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1700 | |
1701 | if ((c->rex_prefix & 0x8) != 0x0) | |
1702 | usermode = X86EMUL_MODE_PROT64; | |
1703 | else | |
1704 | usermode = X86EMUL_MODE_PROT32; | |
1705 | ||
1706 | cs.dpl = 3; | |
1707 | ss.dpl = 3; | |
3fb1b5db | 1708 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1709 | switch (usermode) { |
1710 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1711 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 1712 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 1713 | emulate_gp(ctxt, 0); |
e54cfa97 | 1714 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1715 | } |
79168fd1 | 1716 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1717 | break; |
1718 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1719 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 1720 | if (msr_data == 0x0) { |
54b8486f | 1721 | emulate_gp(ctxt, 0); |
e54cfa97 | 1722 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 1723 | } |
79168fd1 GN |
1724 | ss_sel = cs_sel + 8; |
1725 | cs.d = 0; | |
4668f050 AP |
1726 | cs.l = 1; |
1727 | break; | |
1728 | } | |
79168fd1 GN |
1729 | cs_sel |= SELECTOR_RPL_MASK; |
1730 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1731 | |
79168fd1 GN |
1732 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1733 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1734 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1735 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 1736 | |
bdb475a3 GN |
1737 | c->eip = c->regs[VCPU_REGS_RDX]; |
1738 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1739 | |
e54cfa97 | 1740 | return X86EMUL_CONTINUE; |
4668f050 AP |
1741 | } |
1742 | ||
9c537244 GN |
1743 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1744 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1745 | { |
1746 | int iopl; | |
1747 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1748 | return false; | |
1749 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1750 | return true; | |
1751 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1752 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1753 | } |
1754 | ||
1755 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1756 | struct x86_emulate_ops *ops, | |
1757 | u16 port, u16 len) | |
1758 | { | |
79168fd1 | 1759 | struct desc_struct tr_seg; |
f850e2e6 GN |
1760 | int r; |
1761 | u16 io_bitmap_ptr; | |
1762 | u8 perm, bit_idx = port & 0x7; | |
1763 | unsigned mask = (1 << len) - 1; | |
1764 | ||
79168fd1 GN |
1765 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
1766 | if (!tr_seg.p) | |
f850e2e6 | 1767 | return false; |
79168fd1 | 1768 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1769 | return false; |
79168fd1 GN |
1770 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
1771 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
1772 | if (r != X86EMUL_CONTINUE) |
1773 | return false; | |
79168fd1 | 1774 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1775 | return false; |
79168fd1 GN |
1776 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
1777 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1778 | if (r != X86EMUL_CONTINUE) |
1779 | return false; | |
1780 | if ((perm >> bit_idx) & mask) | |
1781 | return false; | |
1782 | return true; | |
1783 | } | |
1784 | ||
1785 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1786 | struct x86_emulate_ops *ops, | |
1787 | u16 port, u16 len) | |
1788 | { | |
4fc40f07 GN |
1789 | if (ctxt->perm_ok) |
1790 | return true; | |
1791 | ||
9c537244 | 1792 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1793 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1794 | return false; | |
4fc40f07 GN |
1795 | |
1796 | ctxt->perm_ok = true; | |
1797 | ||
f850e2e6 GN |
1798 | return true; |
1799 | } | |
1800 | ||
38ba30ba GN |
1801 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1802 | struct x86_emulate_ops *ops, | |
1803 | struct tss_segment_16 *tss) | |
1804 | { | |
1805 | struct decode_cache *c = &ctxt->decode; | |
1806 | ||
1807 | tss->ip = c->eip; | |
1808 | tss->flag = ctxt->eflags; | |
1809 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1810 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1811 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1812 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1813 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1814 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1815 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1816 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1817 | ||
1818 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1819 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1820 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1821 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1822 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1823 | } | |
1824 | ||
1825 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1826 | struct x86_emulate_ops *ops, | |
1827 | struct tss_segment_16 *tss) | |
1828 | { | |
1829 | struct decode_cache *c = &ctxt->decode; | |
1830 | int ret; | |
1831 | ||
1832 | c->eip = tss->ip; | |
1833 | ctxt->eflags = tss->flag | 2; | |
1834 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1835 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1836 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1837 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
1838 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
1839 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
1840 | c->regs[VCPU_REGS_RSI] = tss->si; | |
1841 | c->regs[VCPU_REGS_RDI] = tss->di; | |
1842 | ||
1843 | /* | |
1844 | * SDM says that segment selectors are loaded before segment | |
1845 | * descriptors | |
1846 | */ | |
1847 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
1848 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1849 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1850 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1851 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1852 | ||
1853 | /* | |
1854 | * Now load segment descriptors. If fault happenes at this stage | |
1855 | * it is handled in a context of new task | |
1856 | */ | |
1857 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
1858 | if (ret != X86EMUL_CONTINUE) | |
1859 | return ret; | |
1860 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1861 | if (ret != X86EMUL_CONTINUE) | |
1862 | return ret; | |
1863 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
1864 | if (ret != X86EMUL_CONTINUE) | |
1865 | return ret; | |
1866 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
1867 | if (ret != X86EMUL_CONTINUE) | |
1868 | return ret; | |
1869 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
1870 | if (ret != X86EMUL_CONTINUE) | |
1871 | return ret; | |
1872 | ||
1873 | return X86EMUL_CONTINUE; | |
1874 | } | |
1875 | ||
1876 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
1877 | struct x86_emulate_ops *ops, | |
1878 | u16 tss_selector, u16 old_tss_sel, | |
1879 | ulong old_tss_base, struct desc_struct *new_desc) | |
1880 | { | |
1881 | struct tss_segment_16 tss_seg; | |
1882 | int ret; | |
1883 | u32 err, new_tss_base = get_desc_base(new_desc); | |
1884 | ||
1885 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1886 | &err); | |
1887 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1888 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1889 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1890 | return ret; |
1891 | } | |
1892 | ||
1893 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
1894 | ||
1895 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1896 | &err); | |
1897 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1898 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1899 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
1900 | return ret; |
1901 | } | |
1902 | ||
1903 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
1904 | &err); | |
1905 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1906 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1907 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1908 | return ret; |
1909 | } | |
1910 | ||
1911 | if (old_tss_sel != 0xffff) { | |
1912 | tss_seg.prev_task_link = old_tss_sel; | |
1913 | ||
1914 | ret = ops->write_std(new_tss_base, | |
1915 | &tss_seg.prev_task_link, | |
1916 | sizeof tss_seg.prev_task_link, | |
1917 | ctxt->vcpu, &err); | |
1918 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
1919 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 1920 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
1921 | return ret; |
1922 | } | |
1923 | } | |
1924 | ||
1925 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
1926 | } | |
1927 | ||
1928 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
1929 | struct x86_emulate_ops *ops, | |
1930 | struct tss_segment_32 *tss) | |
1931 | { | |
1932 | struct decode_cache *c = &ctxt->decode; | |
1933 | ||
1934 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
1935 | tss->eip = c->eip; | |
1936 | tss->eflags = ctxt->eflags; | |
1937 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
1938 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
1939 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
1940 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
1941 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
1942 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
1943 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
1944 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
1945 | ||
1946 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1947 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1948 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1949 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1950 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
1951 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
1952 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1953 | } | |
1954 | ||
1955 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
1956 | struct x86_emulate_ops *ops, | |
1957 | struct tss_segment_32 *tss) | |
1958 | { | |
1959 | struct decode_cache *c = &ctxt->decode; | |
1960 | int ret; | |
1961 | ||
0f12244f | 1962 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 1963 | emulate_gp(ctxt, 0); |
0f12244f GN |
1964 | return X86EMUL_PROPAGATE_FAULT; |
1965 | } | |
38ba30ba GN |
1966 | c->eip = tss->eip; |
1967 | ctxt->eflags = tss->eflags | 2; | |
1968 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
1969 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
1970 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
1971 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
1972 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
1973 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
1974 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
1975 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
1976 | ||
1977 | /* | |
1978 | * SDM says that segment selectors are loaded before segment | |
1979 | * descriptors | |
1980 | */ | |
1981 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
1982 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
1983 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
1984 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
1985 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
1986 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
1987 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
1988 | ||
1989 | /* | |
1990 | * Now load segment descriptors. If fault happenes at this stage | |
1991 | * it is handled in a context of new task | |
1992 | */ | |
1993 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
1994 | if (ret != X86EMUL_CONTINUE) | |
1995 | return ret; | |
1996 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
1997 | if (ret != X86EMUL_CONTINUE) | |
1998 | return ret; | |
1999 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2000 | if (ret != X86EMUL_CONTINUE) | |
2001 | return ret; | |
2002 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2003 | if (ret != X86EMUL_CONTINUE) | |
2004 | return ret; | |
2005 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2006 | if (ret != X86EMUL_CONTINUE) | |
2007 | return ret; | |
2008 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2009 | if (ret != X86EMUL_CONTINUE) | |
2010 | return ret; | |
2011 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2012 | if (ret != X86EMUL_CONTINUE) | |
2013 | return ret; | |
2014 | ||
2015 | return X86EMUL_CONTINUE; | |
2016 | } | |
2017 | ||
2018 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2019 | struct x86_emulate_ops *ops, | |
2020 | u16 tss_selector, u16 old_tss_sel, | |
2021 | ulong old_tss_base, struct desc_struct *new_desc) | |
2022 | { | |
2023 | struct tss_segment_32 tss_seg; | |
2024 | int ret; | |
2025 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2026 | ||
2027 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2028 | &err); | |
2029 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2030 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2031 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2032 | return ret; |
2033 | } | |
2034 | ||
2035 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2036 | ||
2037 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2038 | &err); | |
2039 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2040 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2041 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2042 | return ret; |
2043 | } | |
2044 | ||
2045 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2046 | &err); | |
2047 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2048 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2049 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2050 | return ret; |
2051 | } | |
2052 | ||
2053 | if (old_tss_sel != 0xffff) { | |
2054 | tss_seg.prev_task_link = old_tss_sel; | |
2055 | ||
2056 | ret = ops->write_std(new_tss_base, | |
2057 | &tss_seg.prev_task_link, | |
2058 | sizeof tss_seg.prev_task_link, | |
2059 | ctxt->vcpu, &err); | |
2060 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2061 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2062 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2063 | return ret; |
2064 | } | |
2065 | } | |
2066 | ||
2067 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2068 | } | |
2069 | ||
2070 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2071 | struct x86_emulate_ops *ops, |
2072 | u16 tss_selector, int reason, | |
2073 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2074 | { |
2075 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2076 | int ret; | |
2077 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2078 | ulong old_tss_base = | |
5951c442 | 2079 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2080 | u32 desc_limit; |
38ba30ba GN |
2081 | |
2082 | /* FIXME: old_tss_base == ~0 ? */ | |
2083 | ||
2084 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2085 | if (ret != X86EMUL_CONTINUE) | |
2086 | return ret; | |
2087 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2088 | if (ret != X86EMUL_CONTINUE) | |
2089 | return ret; | |
2090 | ||
2091 | /* FIXME: check that next_tss_desc is tss */ | |
2092 | ||
2093 | if (reason != TASK_SWITCH_IRET) { | |
2094 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2095 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2096 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2097 | return X86EMUL_PROPAGATE_FAULT; |
2098 | } | |
2099 | } | |
2100 | ||
ceffb459 GN |
2101 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2102 | if (!next_tss_desc.p || | |
2103 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2104 | desc_limit < 0x2b)) { | |
54b8486f | 2105 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2106 | return X86EMUL_PROPAGATE_FAULT; |
2107 | } | |
2108 | ||
2109 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2110 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2111 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2112 | &curr_tss_desc); | |
2113 | } | |
2114 | ||
2115 | if (reason == TASK_SWITCH_IRET) | |
2116 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2117 | ||
2118 | /* set back link to prev task only if NT bit is set in eflags | |
2119 | note that old_tss_sel is not used afetr this point */ | |
2120 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2121 | old_tss_sel = 0xffff; | |
2122 | ||
2123 | if (next_tss_desc.type & 8) | |
2124 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2125 | old_tss_base, &next_tss_desc); | |
2126 | else | |
2127 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2128 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2129 | if (ret != X86EMUL_CONTINUE) |
2130 | return ret; | |
38ba30ba GN |
2131 | |
2132 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2133 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2134 | ||
2135 | if (reason != TASK_SWITCH_IRET) { | |
2136 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2137 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2138 | &next_tss_desc); | |
2139 | } | |
2140 | ||
2141 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2142 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2143 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2144 | ||
e269fb21 JK |
2145 | if (has_error_code) { |
2146 | struct decode_cache *c = &ctxt->decode; | |
2147 | ||
2148 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2149 | c->lock_prefix = 0; | |
2150 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2151 | emulate_push(ctxt, ops); |
e269fb21 JK |
2152 | } |
2153 | ||
38ba30ba GN |
2154 | return ret; |
2155 | } | |
2156 | ||
2157 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2158 | u16 tss_selector, int reason, |
2159 | bool has_error_code, u32 error_code) | |
38ba30ba | 2160 | { |
9aabc88f | 2161 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2162 | struct decode_cache *c = &ctxt->decode; |
2163 | int rc; | |
2164 | ||
38ba30ba | 2165 | c->eip = ctxt->eip; |
e269fb21 | 2166 | c->dst.type = OP_NONE; |
38ba30ba | 2167 | |
e269fb21 JK |
2168 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2169 | has_error_code, error_code); | |
38ba30ba GN |
2170 | |
2171 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2172 | rc = writeback(ctxt, ops); |
95c55886 GN |
2173 | if (rc == X86EMUL_CONTINUE) |
2174 | ctxt->eip = c->eip; | |
38ba30ba GN |
2175 | } |
2176 | ||
19d04437 | 2177 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2178 | } |
2179 | ||
a682e354 | 2180 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2181 | int reg, struct operand *op) |
a682e354 GN |
2182 | { |
2183 | struct decode_cache *c = &ctxt->decode; | |
2184 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2185 | ||
d9271123 | 2186 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
1a6440ae | 2187 | op->addr.mem = register_address(c, base, c->regs[reg]); |
a682e354 GN |
2188 | } |
2189 | ||
63540382 AK |
2190 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2191 | { | |
2192 | emulate_push(ctxt, ctxt->ops); | |
2193 | return X86EMUL_CONTINUE; | |
2194 | } | |
2195 | ||
7af04fc0 AK |
2196 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2197 | { | |
2198 | struct decode_cache *c = &ctxt->decode; | |
2199 | u8 al, old_al; | |
2200 | bool af, cf, old_cf; | |
2201 | ||
2202 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2203 | al = c->dst.val; | |
2204 | ||
2205 | old_al = al; | |
2206 | old_cf = cf; | |
2207 | cf = false; | |
2208 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2209 | if ((al & 0x0f) > 9 || af) { | |
2210 | al -= 6; | |
2211 | cf = old_cf | (al >= 250); | |
2212 | af = true; | |
2213 | } else { | |
2214 | af = false; | |
2215 | } | |
2216 | if (old_al > 0x99 || old_cf) { | |
2217 | al -= 0x60; | |
2218 | cf = true; | |
2219 | } | |
2220 | ||
2221 | c->dst.val = al; | |
2222 | /* Set PF, ZF, SF */ | |
2223 | c->src.type = OP_IMM; | |
2224 | c->src.val = 0; | |
2225 | c->src.bytes = 1; | |
2226 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2227 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2228 | if (cf) | |
2229 | ctxt->eflags |= X86_EFLAGS_CF; | |
2230 | if (af) | |
2231 | ctxt->eflags |= X86_EFLAGS_AF; | |
2232 | return X86EMUL_CONTINUE; | |
2233 | } | |
2234 | ||
0ef753b8 AK |
2235 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2236 | { | |
2237 | struct decode_cache *c = &ctxt->decode; | |
2238 | u16 sel, old_cs; | |
2239 | ulong old_eip; | |
2240 | int rc; | |
2241 | ||
2242 | old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2243 | old_eip = c->eip; | |
2244 | ||
2245 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
2246 | if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS)) | |
2247 | return X86EMUL_CONTINUE; | |
2248 | ||
2249 | c->eip = 0; | |
2250 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
2251 | ||
2252 | c->src.val = old_cs; | |
2253 | emulate_push(ctxt, ctxt->ops); | |
2254 | rc = writeback(ctxt, ctxt->ops); | |
2255 | if (rc != X86EMUL_CONTINUE) | |
2256 | return rc; | |
2257 | ||
2258 | c->src.val = old_eip; | |
2259 | emulate_push(ctxt, ctxt->ops); | |
2260 | rc = writeback(ctxt, ctxt->ops); | |
2261 | if (rc != X86EMUL_CONTINUE) | |
2262 | return rc; | |
2263 | ||
2264 | c->dst.type = OP_NONE; | |
2265 | ||
2266 | return X86EMUL_CONTINUE; | |
2267 | } | |
2268 | ||
40ece7c7 AK |
2269 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2270 | { | |
2271 | struct decode_cache *c = &ctxt->decode; | |
2272 | int rc; | |
2273 | ||
2274 | c->dst.type = OP_REG; | |
2275 | c->dst.addr.reg = &c->eip; | |
2276 | c->dst.bytes = c->op_bytes; | |
2277 | rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes); | |
2278 | if (rc != X86EMUL_CONTINUE) | |
2279 | return rc; | |
2280 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val); | |
2281 | return X86EMUL_CONTINUE; | |
2282 | } | |
2283 | ||
5c82aa29 | 2284 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 AK |
2285 | { |
2286 | struct decode_cache *c = &ctxt->decode; | |
2287 | ||
f3a1b9f4 AK |
2288 | emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags); |
2289 | return X86EMUL_CONTINUE; | |
2290 | } | |
2291 | ||
5c82aa29 AK |
2292 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2293 | { | |
2294 | struct decode_cache *c = &ctxt->decode; | |
2295 | ||
2296 | c->dst.val = c->src2.val; | |
2297 | return em_imul(ctxt); | |
2298 | } | |
2299 | ||
61429142 AK |
2300 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2301 | { | |
2302 | struct decode_cache *c = &ctxt->decode; | |
2303 | ||
2304 | c->dst.type = OP_REG; | |
2305 | c->dst.bytes = c->src.bytes; | |
2306 | c->dst.addr.reg = &c->regs[VCPU_REGS_RDX]; | |
2307 | c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1); | |
2308 | ||
2309 | return X86EMUL_CONTINUE; | |
2310 | } | |
2311 | ||
48bb5d3c AK |
2312 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2313 | { | |
2314 | unsigned cpl = ctxt->ops->cpl(ctxt->vcpu); | |
2315 | struct decode_cache *c = &ctxt->decode; | |
2316 | u64 tsc = 0; | |
2317 | ||
2318 | if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) { | |
2319 | emulate_gp(ctxt, 0); | |
2320 | return X86EMUL_PROPAGATE_FAULT; | |
2321 | } | |
2322 | ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc); | |
2323 | c->regs[VCPU_REGS_RAX] = (u32)tsc; | |
2324 | c->regs[VCPU_REGS_RDX] = tsc >> 32; | |
2325 | return X86EMUL_CONTINUE; | |
2326 | } | |
2327 | ||
73fba5f4 AK |
2328 | #define D(_y) { .flags = (_y) } |
2329 | #define N D(0) | |
2330 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } | |
2331 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2332 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
2333 | ||
2334 | static struct opcode group1[] = { | |
2335 | X7(D(Lock)), N | |
2336 | }; | |
2337 | ||
2338 | static struct opcode group1A[] = { | |
2339 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2340 | }; | |
2341 | ||
2342 | static struct opcode group3[] = { | |
2343 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2344 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2345 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2346 | }; |
2347 | ||
2348 | static struct opcode group4[] = { | |
2349 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2350 | N, N, N, N, N, N, | |
2351 | }; | |
2352 | ||
2353 | static struct opcode group5[] = { | |
2354 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
2355 | D(SrcMem | ModRM | Stack), |
2356 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
2357 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
2358 | D(SrcMem | ModRM | Stack), N, | |
2359 | }; | |
2360 | ||
2361 | static struct group_dual group7 = { { | |
2362 | N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv), | |
2363 | D(SrcNone | ModRM | DstMem | Mov), N, | |
5a506b12 AK |
2364 | D(SrcMem16 | ModRM | Mov | Priv), |
2365 | D(SrcMem | ModRM | ByteOp | Priv | NoAccess), | |
73fba5f4 AK |
2366 | }, { |
2367 | D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv), | |
2368 | D(SrcNone | ModRM | DstMem | Mov), N, | |
2369 | D(SrcMem16 | ModRM | Mov | Priv), N, | |
2370 | } }; | |
2371 | ||
2372 | static struct opcode group8[] = { | |
2373 | N, N, N, N, | |
2374 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2375 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2376 | }; | |
2377 | ||
2378 | static struct group_dual group9 = { { | |
2379 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2380 | }, { | |
2381 | N, N, N, N, N, N, N, N, | |
2382 | } }; | |
2383 | ||
2384 | static struct opcode opcode_table[256] = { | |
2385 | /* 0x00 - 0x07 */ | |
2386 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2387 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2388 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2389 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2390 | /* 0x08 - 0x0F */ | |
2391 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2392 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2393 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2394 | D(ImplicitOps | Stack | No64), N, | |
2395 | /* 0x10 - 0x17 */ | |
2396 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2397 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2398 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2399 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2400 | /* 0x18 - 0x1F */ | |
2401 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2402 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2403 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2404 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2405 | /* 0x20 - 0x27 */ | |
2406 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2407 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2408 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2409 | /* 0x28 - 0x2F */ | |
2410 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2411 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
7af04fc0 AK |
2412 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), |
2413 | N, I(ByteOp | DstAcc | No64, em_das), | |
73fba5f4 AK |
2414 | /* 0x30 - 0x37 */ |
2415 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2416 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2417 | D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N, | |
2418 | /* 0x38 - 0x3F */ | |
2419 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2420 | D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), | |
2421 | D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm), | |
2422 | N, N, | |
2423 | /* 0x40 - 0x4F */ | |
2424 | X16(D(DstReg)), | |
2425 | /* 0x50 - 0x57 */ | |
63540382 | 2426 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2427 | /* 0x58 - 0x5F */ |
2428 | X8(D(DstReg | Stack)), | |
2429 | /* 0x60 - 0x67 */ | |
2430 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2431 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2432 | N, N, N, N, | |
2433 | /* 0x68 - 0x6F */ | |
d46164db AK |
2434 | I(SrcImm | Mov | Stack, em_push), |
2435 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
2436 | I(SrcImmByte | Mov | Stack, em_push), |
2437 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
73fba5f4 AK |
2438 | D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */ |
2439 | D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */ | |
2440 | /* 0x70 - 0x7F */ | |
2441 | X16(D(SrcImmByte)), | |
2442 | /* 0x80 - 0x87 */ | |
2443 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2444 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2445 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2446 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
2447 | D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM), | |
2448 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
2449 | /* 0x88 - 0x8F */ | |
2450 | D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov), | |
2451 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov), | |
342fc630 | 2452 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2453 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2454 | /* 0x90 - 0x97 */ | |
3d9e77df | 2455 | X8(D(SrcAcc | DstReg)), |
73fba5f4 | 2456 | /* 0x98 - 0x9F */ |
61429142 | 2457 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 2458 | I(SrcImmFAddr | No64, em_call_far), N, |
73fba5f4 AK |
2459 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N, |
2460 | /* 0xA0 - 0xA7 */ | |
2461 | D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs), | |
2462 | D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs), | |
2463 | D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String), | |
2464 | D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String), | |
2465 | /* 0xA8 - 0xAF */ | |
06cb7046 WY |
2466 | D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), |
2467 | D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String), | |
73fba5f4 | 2468 | D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String), |
f6b33fc5 | 2469 | D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String), |
73fba5f4 AK |
2470 | /* 0xB0 - 0xB7 */ |
2471 | X8(D(ByteOp | DstReg | SrcImm | Mov)), | |
2472 | /* 0xB8 - 0xBF */ | |
2473 | X8(D(DstReg | SrcImm | Mov)), | |
2474 | /* 0xC0 - 0xC7 */ | |
2475 | D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM), | |
40ece7c7 AK |
2476 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
2477 | D(ImplicitOps | Stack), | |
09b5f4d3 | 2478 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
73fba5f4 AK |
2479 | D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov), |
2480 | /* 0xC8 - 0xCF */ | |
2481 | N, N, N, D(ImplicitOps | Stack), | |
2482 | D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps), | |
2483 | /* 0xD0 - 0xD7 */ | |
c034da8b | 2484 | D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM), |
7077aec0 | 2485 | D(ByteOp | DstMem | ModRM), D(DstMem | ModRM), |
73fba5f4 AK |
2486 | N, N, N, N, |
2487 | /* 0xD8 - 0xDF */ | |
2488 | N, N, N, N, N, N, N, N, | |
2489 | /* 0xE0 - 0xE7 */ | |
e4abac67 | 2490 | X4(D(SrcImmByte)), |
73fba5f4 | 2491 | D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc), |
41167be5 | 2492 | D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte), |
73fba5f4 AK |
2493 | /* 0xE8 - 0xEF */ |
2494 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2495 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
2496 | D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc), | |
41167be5 | 2497 | D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps), |
73fba5f4 AK |
2498 | /* 0xF0 - 0xF7 */ |
2499 | N, N, N, N, | |
2500 | D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3), | |
2501 | /* 0xF8 - 0xFF */ | |
8744aa9a | 2502 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2503 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2504 | }; | |
2505 | ||
2506 | static struct opcode twobyte_table[256] = { | |
2507 | /* 0x00 - 0x0F */ | |
2508 | N, GD(0, &group7), N, N, | |
2509 | N, D(ImplicitOps), D(ImplicitOps | Priv), N, | |
2510 | D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N, | |
2511 | N, D(ImplicitOps | ModRM), N, N, | |
2512 | /* 0x10 - 0x1F */ | |
2513 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2514 | /* 0x20 - 0x2F */ | |
b27f3856 AK |
2515 | D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264), |
2516 | D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264), | |
73fba5f4 AK |
2517 | N, N, N, N, |
2518 | N, N, N, N, N, N, N, N, | |
2519 | /* 0x30 - 0x3F */ | |
48bb5d3c AK |
2520 | D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc), |
2521 | D(ImplicitOps | Priv), N, | |
73fba5f4 AK |
2522 | D(ImplicitOps), D(ImplicitOps | Priv), N, N, |
2523 | N, N, N, N, N, N, N, N, | |
2524 | /* 0x40 - 0x4F */ | |
2525 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2526 | /* 0x50 - 0x5F */ | |
2527 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2528 | /* 0x60 - 0x6F */ | |
2529 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2530 | /* 0x70 - 0x7F */ | |
2531 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2532 | /* 0x80 - 0x8F */ | |
2533 | X16(D(SrcImm)), | |
2534 | /* 0x90 - 0x9F */ | |
ee45b58e | 2535 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2536 | /* 0xA0 - 0xA7 */ |
2537 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2538 | N, D(DstMem | SrcReg | ModRM | BitOp), | |
2539 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2540 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2541 | /* 0xA8 - 0xAF */ | |
2542 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
2543 | N, D(DstMem | SrcReg | ModRM | BitOp | Lock), | |
2544 | D(DstMem | SrcReg | Src2ImmByte | ModRM), | |
2545 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 2546 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 AK |
2547 | /* 0xB0 - 0xB7 */ |
2548 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), | |
09b5f4d3 WY |
2549 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
2550 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
2551 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
2552 | /* 0xB8 - 0xBF */ |
2553 | N, N, | |
ba7ff2b7 | 2554 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2555 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2556 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2557 | /* 0xC0 - 0xCF */ |
92f738a5 WY |
2558 | D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock), |
2559 | N, D(DstMem | SrcReg | ModRM | Mov), | |
73fba5f4 AK |
2560 | N, N, N, GD(0, &group9), |
2561 | N, N, N, N, N, N, N, N, | |
2562 | /* 0xD0 - 0xDF */ | |
2563 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2564 | /* 0xE0 - 0xEF */ | |
2565 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2566 | /* 0xF0 - 0xFF */ | |
2567 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2568 | }; | |
2569 | ||
2570 | #undef D | |
2571 | #undef N | |
2572 | #undef G | |
2573 | #undef GD | |
2574 | #undef I | |
2575 | ||
39f21ee5 AK |
2576 | static unsigned imm_size(struct decode_cache *c) |
2577 | { | |
2578 | unsigned size; | |
2579 | ||
2580 | size = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2581 | if (size == 8) | |
2582 | size = 4; | |
2583 | return size; | |
2584 | } | |
2585 | ||
2586 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
2587 | unsigned size, bool sign_extension) | |
2588 | { | |
2589 | struct decode_cache *c = &ctxt->decode; | |
2590 | struct x86_emulate_ops *ops = ctxt->ops; | |
2591 | int rc = X86EMUL_CONTINUE; | |
2592 | ||
2593 | op->type = OP_IMM; | |
2594 | op->bytes = size; | |
2595 | op->addr.mem = c->eip; | |
2596 | /* NB. Immediates are sign-extended as necessary. */ | |
2597 | switch (op->bytes) { | |
2598 | case 1: | |
2599 | op->val = insn_fetch(s8, 1, c->eip); | |
2600 | break; | |
2601 | case 2: | |
2602 | op->val = insn_fetch(s16, 2, c->eip); | |
2603 | break; | |
2604 | case 4: | |
2605 | op->val = insn_fetch(s32, 4, c->eip); | |
2606 | break; | |
2607 | } | |
2608 | if (!sign_extension) { | |
2609 | switch (op->bytes) { | |
2610 | case 1: | |
2611 | op->val &= 0xff; | |
2612 | break; | |
2613 | case 2: | |
2614 | op->val &= 0xffff; | |
2615 | break; | |
2616 | case 4: | |
2617 | op->val &= 0xffffffff; | |
2618 | break; | |
2619 | } | |
2620 | } | |
2621 | done: | |
2622 | return rc; | |
2623 | } | |
2624 | ||
dde7e6d1 AK |
2625 | int |
2626 | x86_decode_insn(struct x86_emulate_ctxt *ctxt) | |
2627 | { | |
2628 | struct x86_emulate_ops *ops = ctxt->ops; | |
2629 | struct decode_cache *c = &ctxt->decode; | |
2630 | int rc = X86EMUL_CONTINUE; | |
2631 | int mode = ctxt->mode; | |
2632 | int def_op_bytes, def_ad_bytes, dual, goffset; | |
2633 | struct opcode opcode, *g_mod012, *g_mod3; | |
2dbd0dd7 | 2634 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 AK |
2635 | |
2636 | /* we cannot decode insn before we complete previous rep insn */ | |
2637 | WARN_ON(ctxt->restart); | |
2638 | ||
2639 | c->eip = ctxt->eip; | |
2640 | c->fetch.start = c->fetch.end = c->eip; | |
2641 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); | |
2642 | ||
2643 | switch (mode) { | |
2644 | case X86EMUL_MODE_REAL: | |
2645 | case X86EMUL_MODE_VM86: | |
2646 | case X86EMUL_MODE_PROT16: | |
2647 | def_op_bytes = def_ad_bytes = 2; | |
2648 | break; | |
2649 | case X86EMUL_MODE_PROT32: | |
2650 | def_op_bytes = def_ad_bytes = 4; | |
2651 | break; | |
2652 | #ifdef CONFIG_X86_64 | |
2653 | case X86EMUL_MODE_PROT64: | |
2654 | def_op_bytes = 4; | |
2655 | def_ad_bytes = 8; | |
2656 | break; | |
2657 | #endif | |
2658 | default: | |
2659 | return -1; | |
2660 | } | |
2661 | ||
2662 | c->op_bytes = def_op_bytes; | |
2663 | c->ad_bytes = def_ad_bytes; | |
2664 | ||
2665 | /* Legacy prefixes. */ | |
2666 | for (;;) { | |
2667 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
2668 | case 0x66: /* operand-size override */ | |
2669 | /* switch between 2/4 bytes */ | |
2670 | c->op_bytes = def_op_bytes ^ 6; | |
2671 | break; | |
2672 | case 0x67: /* address-size override */ | |
2673 | if (mode == X86EMUL_MODE_PROT64) | |
2674 | /* switch between 4/8 bytes */ | |
2675 | c->ad_bytes = def_ad_bytes ^ 12; | |
2676 | else | |
2677 | /* switch between 2/4 bytes */ | |
2678 | c->ad_bytes = def_ad_bytes ^ 6; | |
2679 | break; | |
2680 | case 0x26: /* ES override */ | |
2681 | case 0x2e: /* CS override */ | |
2682 | case 0x36: /* SS override */ | |
2683 | case 0x3e: /* DS override */ | |
2684 | set_seg_override(c, (c->b >> 3) & 3); | |
2685 | break; | |
2686 | case 0x64: /* FS override */ | |
2687 | case 0x65: /* GS override */ | |
2688 | set_seg_override(c, c->b & 7); | |
2689 | break; | |
2690 | case 0x40 ... 0x4f: /* REX */ | |
2691 | if (mode != X86EMUL_MODE_PROT64) | |
2692 | goto done_prefixes; | |
2693 | c->rex_prefix = c->b; | |
2694 | continue; | |
2695 | case 0xf0: /* LOCK */ | |
2696 | c->lock_prefix = 1; | |
2697 | break; | |
2698 | case 0xf2: /* REPNE/REPNZ */ | |
2699 | c->rep_prefix = REPNE_PREFIX; | |
2700 | break; | |
2701 | case 0xf3: /* REP/REPE/REPZ */ | |
2702 | c->rep_prefix = REPE_PREFIX; | |
2703 | break; | |
2704 | default: | |
2705 | goto done_prefixes; | |
2706 | } | |
2707 | ||
2708 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
2709 | ||
2710 | c->rex_prefix = 0; | |
2711 | } | |
2712 | ||
2713 | done_prefixes: | |
2714 | ||
2715 | /* REX prefix. */ | |
1e87e3ef AK |
2716 | if (c->rex_prefix & 8) |
2717 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
2718 | |
2719 | /* Opcode byte(s). */ | |
2720 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
2721 | /* Two-byte opcode? */ |
2722 | if (c->b == 0x0f) { | |
2723 | c->twobyte = 1; | |
2724 | c->b = insn_fetch(u8, 1, c->eip); | |
2725 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
2726 | } |
2727 | c->d = opcode.flags; | |
2728 | ||
2729 | if (c->d & Group) { | |
2730 | dual = c->d & GroupDual; | |
2731 | c->modrm = insn_fetch(u8, 1, c->eip); | |
2732 | --c->eip; | |
2733 | ||
2734 | if (c->d & GroupDual) { | |
2735 | g_mod012 = opcode.u.gdual->mod012; | |
2736 | g_mod3 = opcode.u.gdual->mod3; | |
2737 | } else | |
2738 | g_mod012 = g_mod3 = opcode.u.group; | |
2739 | ||
2740 | c->d &= ~(Group | GroupDual); | |
2741 | ||
2742 | goffset = (c->modrm >> 3) & 7; | |
2743 | ||
2744 | if ((c->modrm >> 6) == 3) | |
2745 | opcode = g_mod3[goffset]; | |
2746 | else | |
2747 | opcode = g_mod012[goffset]; | |
2748 | c->d |= opcode.flags; | |
2749 | } | |
2750 | ||
2751 | c->execute = opcode.u.execute; | |
2752 | ||
2753 | /* Unrecognised? */ | |
2754 | if (c->d == 0 || (c->d & Undefined)) { | |
2755 | DPRINTF("Cannot emulate %02x\n", c->b); | |
2756 | return -1; | |
2757 | } | |
2758 | ||
2759 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) | |
2760 | c->op_bytes = 8; | |
2761 | ||
7f9b4b75 AK |
2762 | if (c->d & Op3264) { |
2763 | if (mode == X86EMUL_MODE_PROT64) | |
2764 | c->op_bytes = 8; | |
2765 | else | |
2766 | c->op_bytes = 4; | |
2767 | } | |
2768 | ||
dde7e6d1 | 2769 | /* ModRM and SIB bytes. */ |
09ee57cd | 2770 | if (c->d & ModRM) { |
2dbd0dd7 | 2771 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
2772 | if (!c->has_seg_override) |
2773 | set_seg_override(c, c->modrm_seg); | |
2774 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 2775 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
2776 | if (rc != X86EMUL_CONTINUE) |
2777 | goto done; | |
2778 | ||
2779 | if (!c->has_seg_override) | |
2780 | set_seg_override(c, VCPU_SREG_DS); | |
2781 | ||
2dbd0dd7 AK |
2782 | if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d)) |
2783 | memop.addr.mem += seg_override_base(ctxt, ops, c); | |
dde7e6d1 | 2784 | |
2dbd0dd7 AK |
2785 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
2786 | memop.addr.mem = (u32)memop.addr.mem; | |
dde7e6d1 | 2787 | |
2dbd0dd7 AK |
2788 | if (memop.type == OP_MEM && c->rip_relative) |
2789 | memop.addr.mem += c->eip; | |
dde7e6d1 AK |
2790 | |
2791 | /* | |
2792 | * Decode and fetch the source operand: register, memory | |
2793 | * or immediate. | |
2794 | */ | |
2795 | switch (c->d & SrcMask) { | |
2796 | case SrcNone: | |
2797 | break; | |
2798 | case SrcReg: | |
2799 | decode_register_operand(&c->src, c, 0); | |
2800 | break; | |
2801 | case SrcMem16: | |
2dbd0dd7 | 2802 | memop.bytes = 2; |
dde7e6d1 AK |
2803 | goto srcmem_common; |
2804 | case SrcMem32: | |
2dbd0dd7 | 2805 | memop.bytes = 4; |
dde7e6d1 AK |
2806 | goto srcmem_common; |
2807 | case SrcMem: | |
2dbd0dd7 | 2808 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 2809 | c->op_bytes; |
dde7e6d1 | 2810 | srcmem_common: |
2dbd0dd7 | 2811 | c->src = memop; |
dde7e6d1 | 2812 | break; |
b250e605 | 2813 | case SrcImmU16: |
39f21ee5 AK |
2814 | rc = decode_imm(ctxt, &c->src, 2, false); |
2815 | break; | |
dde7e6d1 | 2816 | case SrcImm: |
39f21ee5 AK |
2817 | rc = decode_imm(ctxt, &c->src, imm_size(c), true); |
2818 | break; | |
dde7e6d1 | 2819 | case SrcImmU: |
39f21ee5 | 2820 | rc = decode_imm(ctxt, &c->src, imm_size(c), false); |
dde7e6d1 AK |
2821 | break; |
2822 | case SrcImmByte: | |
39f21ee5 AK |
2823 | rc = decode_imm(ctxt, &c->src, 1, true); |
2824 | break; | |
dde7e6d1 | 2825 | case SrcImmUByte: |
39f21ee5 | 2826 | rc = decode_imm(ctxt, &c->src, 1, false); |
dde7e6d1 AK |
2827 | break; |
2828 | case SrcAcc: | |
2829 | c->src.type = OP_REG; | |
2830 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2831 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2832 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
2833 | break; |
2834 | case SrcOne: | |
2835 | c->src.bytes = 1; | |
2836 | c->src.val = 1; | |
2837 | break; | |
2838 | case SrcSI: | |
2839 | c->src.type = OP_MEM; | |
2840 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2841 | c->src.addr.mem = |
dde7e6d1 AK |
2842 | register_address(c, seg_override_base(ctxt, ops, c), |
2843 | c->regs[VCPU_REGS_RSI]); | |
2844 | c->src.val = 0; | |
2845 | break; | |
2846 | case SrcImmFAddr: | |
2847 | c->src.type = OP_IMM; | |
1a6440ae | 2848 | c->src.addr.mem = c->eip; |
dde7e6d1 AK |
2849 | c->src.bytes = c->op_bytes + 2; |
2850 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
2851 | break; | |
2852 | case SrcMemFAddr: | |
2dbd0dd7 AK |
2853 | memop.bytes = c->op_bytes + 2; |
2854 | goto srcmem_common; | |
dde7e6d1 AK |
2855 | break; |
2856 | } | |
2857 | ||
39f21ee5 AK |
2858 | if (rc != X86EMUL_CONTINUE) |
2859 | goto done; | |
2860 | ||
dde7e6d1 AK |
2861 | /* |
2862 | * Decode and fetch the second source operand: register, memory | |
2863 | * or immediate. | |
2864 | */ | |
2865 | switch (c->d & Src2Mask) { | |
2866 | case Src2None: | |
2867 | break; | |
2868 | case Src2CL: | |
2869 | c->src2.bytes = 1; | |
2870 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
2871 | break; | |
2872 | case Src2ImmByte: | |
39f21ee5 | 2873 | rc = decode_imm(ctxt, &c->src2, 1, true); |
dde7e6d1 AK |
2874 | break; |
2875 | case Src2One: | |
2876 | c->src2.bytes = 1; | |
2877 | c->src2.val = 1; | |
2878 | break; | |
7db41eb7 AK |
2879 | case Src2Imm: |
2880 | rc = decode_imm(ctxt, &c->src2, imm_size(c), true); | |
2881 | break; | |
dde7e6d1 AK |
2882 | } |
2883 | ||
39f21ee5 AK |
2884 | if (rc != X86EMUL_CONTINUE) |
2885 | goto done; | |
2886 | ||
dde7e6d1 AK |
2887 | /* Decode and fetch the destination operand: register or memory. */ |
2888 | switch (c->d & DstMask) { | |
dde7e6d1 AK |
2889 | case DstReg: |
2890 | decode_register_operand(&c->dst, c, | |
2891 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); | |
2892 | break; | |
943858e2 WY |
2893 | case DstImmUByte: |
2894 | c->dst.type = OP_IMM; | |
2895 | c->dst.addr.mem = c->eip; | |
2896 | c->dst.bytes = 1; | |
2897 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
2898 | break; | |
dde7e6d1 AK |
2899 | case DstMem: |
2900 | case DstMem64: | |
2dbd0dd7 | 2901 | c->dst = memop; |
dde7e6d1 AK |
2902 | if ((c->d & DstMask) == DstMem64) |
2903 | c->dst.bytes = 8; | |
2904 | else | |
2905 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
2906 | if (c->d & BitOp) |
2907 | fetch_bit_operand(c); | |
2dbd0dd7 | 2908 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
2909 | break; |
2910 | case DstAcc: | |
2911 | c->dst.type = OP_REG; | |
2912 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2913 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 2914 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
2915 | c->dst.orig_val = c->dst.val; |
2916 | break; | |
2917 | case DstDI: | |
2918 | c->dst.type = OP_MEM; | |
2919 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 2920 | c->dst.addr.mem = |
dde7e6d1 AK |
2921 | register_address(c, es_base(ctxt, ops), |
2922 | c->regs[VCPU_REGS_RDI]); | |
2923 | c->dst.val = 0; | |
2924 | break; | |
36089fed WY |
2925 | case ImplicitOps: |
2926 | /* Special instructions do their own operand decoding. */ | |
2927 | default: | |
2928 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2929 | return 0; | |
dde7e6d1 AK |
2930 | } |
2931 | ||
2932 | done: | |
2933 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
2934 | } | |
2935 | ||
8b4caf66 | 2936 | int |
9aabc88f | 2937 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 2938 | { |
9aabc88f | 2939 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 2940 | u64 msr_data; |
8b4caf66 | 2941 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2942 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2943 | int saved_dst_type = c->dst.type; |
6e154e56 | 2944 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 2945 | |
9de41573 | 2946 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2947 | |
1161624f | 2948 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2949 | emulate_ud(ctxt); |
1161624f GN |
2950 | goto done; |
2951 | } | |
2952 | ||
d380a5e4 | 2953 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2954 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2955 | emulate_ud(ctxt); |
d380a5e4 GN |
2956 | goto done; |
2957 | } | |
2958 | ||
e92805ac | 2959 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2960 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 2961 | emulate_gp(ctxt, 0); |
e92805ac GN |
2962 | goto done; |
2963 | } | |
2964 | ||
b9fa9d6b | 2965 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2966 | ctxt->restart = true; |
b9fa9d6b | 2967 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2968 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 | 2969 | ctxt->restart = false; |
95c55886 | 2970 | ctxt->eip = c->eip; |
b9fa9d6b AK |
2971 | goto done; |
2972 | } | |
b9fa9d6b AK |
2973 | } |
2974 | ||
c483c02a | 2975 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
1a6440ae | 2976 | rc = read_emulated(ctxt, ops, c->src.addr.mem, |
414e6277 | 2977 | c->src.valptr, c->src.bytes); |
b60d513c | 2978 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 2979 | goto done; |
16518d5a | 2980 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
2981 | } |
2982 | ||
e35b7b9c | 2983 | if (c->src2.type == OP_MEM) { |
1a6440ae | 2984 | rc = read_emulated(ctxt, ops, c->src2.addr.mem, |
9de41573 | 2985 | &c->src2.val, c->src2.bytes); |
e35b7b9c GN |
2986 | if (rc != X86EMUL_CONTINUE) |
2987 | goto done; | |
2988 | } | |
2989 | ||
8b4caf66 LV |
2990 | if ((c->d & DstMask) == ImplicitOps) |
2991 | goto special_insn; | |
2992 | ||
2993 | ||
69f55cb1 GN |
2994 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2995 | /* optimisation - avoid slow emulated read if Mov */ | |
1a6440ae | 2996 | rc = read_emulated(ctxt, ops, c->dst.addr.mem, |
9de41573 | 2997 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
2998 | if (rc != X86EMUL_CONTINUE) |
2999 | goto done; | |
038e51de | 3000 | } |
e4e03ded | 3001 | c->dst.orig_val = c->dst.val; |
038e51de | 3002 | |
018a98db AK |
3003 | special_insn: |
3004 | ||
ef65c889 AK |
3005 | if (c->execute) { |
3006 | rc = c->execute(ctxt); | |
3007 | if (rc != X86EMUL_CONTINUE) | |
3008 | goto done; | |
3009 | goto writeback; | |
3010 | } | |
3011 | ||
e4e03ded | 3012 | if (c->twobyte) |
6aa8b732 AK |
3013 | goto twobyte_insn; |
3014 | ||
e4e03ded | 3015 | switch (c->b) { |
6aa8b732 AK |
3016 | case 0x00 ... 0x05: |
3017 | add: /* add */ | |
05f086f8 | 3018 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3019 | break; |
0934ac9d | 3020 | case 0x06: /* push es */ |
79168fd1 | 3021 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
3022 | break; |
3023 | case 0x07: /* pop es */ | |
0934ac9d | 3024 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 3025 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3026 | goto done; |
3027 | break; | |
6aa8b732 AK |
3028 | case 0x08 ... 0x0d: |
3029 | or: /* or */ | |
05f086f8 | 3030 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3031 | break; |
0934ac9d | 3032 | case 0x0e: /* push cs */ |
79168fd1 | 3033 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 3034 | break; |
6aa8b732 AK |
3035 | case 0x10 ... 0x15: |
3036 | adc: /* adc */ | |
05f086f8 | 3037 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3038 | break; |
0934ac9d | 3039 | case 0x16: /* push ss */ |
79168fd1 | 3040 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
3041 | break; |
3042 | case 0x17: /* pop ss */ | |
0934ac9d | 3043 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 3044 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3045 | goto done; |
3046 | break; | |
6aa8b732 AK |
3047 | case 0x18 ... 0x1d: |
3048 | sbb: /* sbb */ | |
05f086f8 | 3049 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3050 | break; |
0934ac9d | 3051 | case 0x1e: /* push ds */ |
79168fd1 | 3052 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
3053 | break; |
3054 | case 0x1f: /* pop ds */ | |
0934ac9d | 3055 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 3056 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3057 | goto done; |
3058 | break; | |
aa3a816b | 3059 | case 0x20 ... 0x25: |
6aa8b732 | 3060 | and: /* and */ |
05f086f8 | 3061 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3062 | break; |
3063 | case 0x28 ... 0x2d: | |
3064 | sub: /* sub */ | |
05f086f8 | 3065 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3066 | break; |
3067 | case 0x30 ... 0x35: | |
3068 | xor: /* xor */ | |
05f086f8 | 3069 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3070 | break; |
3071 | case 0x38 ... 0x3d: | |
3072 | cmp: /* cmp */ | |
05f086f8 | 3073 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3074 | break; |
33615aa9 AK |
3075 | case 0x40 ... 0x47: /* inc r16/r32 */ |
3076 | emulate_1op("inc", c->dst, ctxt->eflags); | |
3077 | break; | |
3078 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
3079 | emulate_1op("dec", c->dst, ctxt->eflags); | |
3080 | break; | |
33615aa9 AK |
3081 | case 0x58 ... 0x5f: /* pop reg */ |
3082 | pop_instruction: | |
350f69dc | 3083 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 3084 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 3085 | goto done; |
33615aa9 | 3086 | break; |
abcf14b5 | 3087 | case 0x60: /* pusha */ |
c37eda13 WY |
3088 | rc = emulate_pusha(ctxt, ops); |
3089 | if (rc != X86EMUL_CONTINUE) | |
3090 | goto done; | |
abcf14b5 MG |
3091 | break; |
3092 | case 0x61: /* popa */ | |
3093 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 3094 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
3095 | goto done; |
3096 | break; | |
6aa8b732 | 3097 | case 0x63: /* movsxd */ |
8b4caf66 | 3098 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3099 | goto cannot_emulate; |
e4e03ded | 3100 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 3101 | break; |
018a98db AK |
3102 | case 0x6c: /* insb */ |
3103 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
3104 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3105 | goto do_io_in; | |
018a98db AK |
3106 | case 0x6e: /* outsb */ |
3107 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
3108 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
3109 | goto do_io_out; | |
7972995b | 3110 | break; |
b2833e3c | 3111 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 3112 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3113 | jmp_rel(c, c->src.val); |
018a98db | 3114 | break; |
6aa8b732 | 3115 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 3116 | switch (c->modrm_reg) { |
6aa8b732 AK |
3117 | case 0: |
3118 | goto add; | |
3119 | case 1: | |
3120 | goto or; | |
3121 | case 2: | |
3122 | goto adc; | |
3123 | case 3: | |
3124 | goto sbb; | |
3125 | case 4: | |
3126 | goto and; | |
3127 | case 5: | |
3128 | goto sub; | |
3129 | case 6: | |
3130 | goto xor; | |
3131 | case 7: | |
3132 | goto cmp; | |
3133 | } | |
3134 | break; | |
3135 | case 0x84 ... 0x85: | |
dfb507c4 | 3136 | test: |
05f086f8 | 3137 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3138 | break; |
3139 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 3140 | xchg: |
6aa8b732 | 3141 | /* Write back the register source. */ |
31be40b3 WY |
3142 | c->src.val = c->dst.val; |
3143 | write_register_operand(&c->src); | |
6aa8b732 AK |
3144 | /* |
3145 | * Write back the memory destination with implicit LOCK | |
3146 | * prefix. | |
3147 | */ | |
31be40b3 | 3148 | c->dst.val = c->src.orig_val; |
e4e03ded | 3149 | c->lock_prefix = 1; |
6aa8b732 | 3150 | break; |
6aa8b732 | 3151 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 3152 | goto mov; |
79168fd1 GN |
3153 | case 0x8c: /* mov r/m, sreg */ |
3154 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3155 | emulate_ud(ctxt); |
5e3ae6c5 | 3156 | goto done; |
38d5bc6d | 3157 | } |
79168fd1 | 3158 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3159 | break; |
7e0b54b1 | 3160 | case 0x8d: /* lea r16/r32, m */ |
342fc630 | 3161 | c->dst.val = c->src.addr.mem; |
7e0b54b1 | 3162 | break; |
4257198a GT |
3163 | case 0x8e: { /* mov seg, r/m16 */ |
3164 | uint16_t sel; | |
4257198a GT |
3165 | |
3166 | sel = c->src.val; | |
8b9f4414 | 3167 | |
c697518a GN |
3168 | if (c->modrm_reg == VCPU_SREG_CS || |
3169 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 3170 | emulate_ud(ctxt); |
8b9f4414 GN |
3171 | goto done; |
3172 | } | |
3173 | ||
310b5d30 | 3174 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3175 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3176 | |
2e873022 | 3177 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3178 | |
3179 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3180 | break; | |
3181 | } | |
6aa8b732 | 3182 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3183 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 3184 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 3185 | goto done; |
6aa8b732 | 3186 | break; |
3d9e77df AK |
3187 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3188 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3189 | break; |
b13354f8 | 3190 | goto xchg; |
e8b6fa70 WY |
3191 | case 0x98: /* cbw/cwde/cdqe */ |
3192 | switch (c->op_bytes) { | |
3193 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3194 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3195 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3196 | } | |
3197 | break; | |
fd2a7608 | 3198 | case 0x9c: /* pushf */ |
05f086f8 | 3199 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3200 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3201 | break; |
535eabcf | 3202 | case 0x9d: /* popf */ |
2b48cc75 | 3203 | c->dst.type = OP_REG; |
1a6440ae | 3204 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3205 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
3206 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
3207 | if (rc != X86EMUL_CONTINUE) | |
3208 | goto done; | |
3209 | break; | |
5d55f299 | 3210 | case 0xa0 ... 0xa3: /* mov */ |
6aa8b732 | 3211 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 3212 | goto mov; |
6aa8b732 | 3213 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3214 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a6440ae | 3215 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem); |
a682e354 | 3216 | goto cmp; |
dfb507c4 MG |
3217 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3218 | goto test; | |
6aa8b732 | 3219 | case 0xaa ... 0xab: /* stos */ |
6aa8b732 | 3220 | case 0xac ... 0xad: /* lods */ |
a682e354 | 3221 | goto mov; |
6aa8b732 | 3222 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3223 | goto cmp; |
a5e2e82b | 3224 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 3225 | goto mov; |
018a98db AK |
3226 | case 0xc0 ... 0xc1: |
3227 | emulate_grp2(ctxt); | |
3228 | break; | |
111de5d6 | 3229 | case 0xc3: /* ret */ |
cf5de4f8 | 3230 | c->dst.type = OP_REG; |
1a6440ae | 3231 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3232 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3233 | goto pop_instruction; |
09b5f4d3 WY |
3234 | case 0xc4: /* les */ |
3235 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES); | |
3236 | if (rc != X86EMUL_CONTINUE) | |
3237 | goto done; | |
3238 | break; | |
3239 | case 0xc5: /* lds */ | |
3240 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS); | |
3241 | if (rc != X86EMUL_CONTINUE) | |
3242 | goto done; | |
3243 | break; | |
018a98db AK |
3244 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
3245 | mov: | |
3246 | c->dst.val = c->src.val; | |
3247 | break; | |
a77ab5ea AK |
3248 | case 0xcb: /* ret far */ |
3249 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e MG |
3250 | if (rc != X86EMUL_CONTINUE) |
3251 | goto done; | |
3252 | break; | |
6e154e56 MG |
3253 | case 0xcc: /* int3 */ |
3254 | irq = 3; | |
3255 | goto do_interrupt; | |
3256 | case 0xcd: /* int n */ | |
3257 | irq = c->src.val; | |
3258 | do_interrupt: | |
3259 | rc = emulate_int(ctxt, ops, irq); | |
3260 | if (rc != X86EMUL_CONTINUE) | |
3261 | goto done; | |
3262 | break; | |
3263 | case 0xce: /* into */ | |
3264 | if (ctxt->eflags & EFLG_OF) { | |
3265 | irq = 4; | |
3266 | goto do_interrupt; | |
3267 | } | |
3268 | break; | |
62bd430e MG |
3269 | case 0xcf: /* iret */ |
3270 | rc = emulate_iret(ctxt, ops); | |
3271 | ||
1b30eaa8 | 3272 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
3273 | goto done; |
3274 | break; | |
018a98db | 3275 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3276 | emulate_grp2(ctxt); |
3277 | break; | |
3278 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3279 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3280 | emulate_grp2(ctxt); | |
3281 | break; | |
f2f31845 WY |
3282 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3283 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3284 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3285 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3286 | jmp_rel(c, c->src.val); | |
3287 | break; | |
e4abac67 WY |
3288 | case 0xe3: /* jcxz/jecxz/jrcxz */ |
3289 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) | |
3290 | jmp_rel(c, c->src.val); | |
3291 | break; | |
a6a3034c MG |
3292 | case 0xe4: /* inb */ |
3293 | case 0xe5: /* in */ | |
cf8f70bf | 3294 | goto do_io_in; |
a6a3034c MG |
3295 | case 0xe6: /* outb */ |
3296 | case 0xe7: /* out */ | |
cf8f70bf | 3297 | goto do_io_out; |
1a52e051 | 3298 | case 0xe8: /* call (near) */ { |
d53c4777 | 3299 | long int rel = c->src.val; |
e4e03ded | 3300 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3301 | jmp_rel(c, rel); |
79168fd1 | 3302 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3303 | break; |
1a52e051 NK |
3304 | } |
3305 | case 0xe9: /* jmp rel */ | |
954cd36f | 3306 | goto jmp; |
414e6277 GN |
3307 | case 0xea: { /* jmp far */ |
3308 | unsigned short sel; | |
ea79849d | 3309 | jump_far: |
414e6277 GN |
3310 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3311 | ||
3312 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3313 | goto done; |
954cd36f | 3314 | |
414e6277 GN |
3315 | c->eip = 0; |
3316 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3317 | break; |
414e6277 | 3318 | } |
954cd36f GT |
3319 | case 0xeb: |
3320 | jmp: /* jmp rel short */ | |
7a957275 | 3321 | jmp_rel(c, c->src.val); |
a01af5ec | 3322 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3323 | break; |
a6a3034c MG |
3324 | case 0xec: /* in al,dx */ |
3325 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3326 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3327 | do_io_in: | |
3328 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3329 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3330 | emulate_gp(ctxt, 0); |
cf8f70bf GN |
3331 | goto done; |
3332 | } | |
7b262e90 GN |
3333 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3334 | &c->dst.val)) | |
cf8f70bf GN |
3335 | goto done; /* IO is needed */ |
3336 | break; | |
ce7a0ad3 WY |
3337 | case 0xee: /* out dx,al */ |
3338 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3339 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3340 | do_io_out: |
41167be5 WY |
3341 | c->src.bytes = min(c->src.bytes, 4u); |
3342 | if (!emulator_io_permited(ctxt, ops, c->dst.val, | |
3343 | c->src.bytes)) { | |
54b8486f | 3344 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
3345 | goto done; |
3346 | } | |
41167be5 WY |
3347 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3348 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3349 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3350 | break; |
111de5d6 | 3351 | case 0xf4: /* hlt */ |
ad312c7c | 3352 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3353 | break; |
111de5d6 AK |
3354 | case 0xf5: /* cmc */ |
3355 | /* complement carry flag from eflags reg */ | |
3356 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3357 | break; |
018a98db | 3358 | case 0xf6 ... 0xf7: /* Grp3 */ |
8c5eee30 | 3359 | if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE) |
aca06a83 | 3360 | goto cannot_emulate; |
018a98db | 3361 | break; |
111de5d6 AK |
3362 | case 0xf8: /* clc */ |
3363 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3364 | break; |
8744aa9a MG |
3365 | case 0xf9: /* stc */ |
3366 | ctxt->eflags |= EFLG_CF; | |
3367 | break; | |
111de5d6 | 3368 | case 0xfa: /* cli */ |
07cbc6c1 | 3369 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3370 | emulate_gp(ctxt, 0); |
07cbc6c1 | 3371 | goto done; |
36089fed | 3372 | } else |
f850e2e6 | 3373 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3374 | break; |
3375 | case 0xfb: /* sti */ | |
07cbc6c1 | 3376 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3377 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3378 | goto done; |
3379 | } else { | |
95cb2295 | 3380 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3381 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3382 | } |
111de5d6 | 3383 | break; |
fb4616f4 MG |
3384 | case 0xfc: /* cld */ |
3385 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3386 | break; |
3387 | case 0xfd: /* std */ | |
3388 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3389 | break; |
ea79849d GN |
3390 | case 0xfe: /* Grp4 */ |
3391 | grp45: | |
018a98db | 3392 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 3393 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3394 | goto done; |
3395 | break; | |
ea79849d GN |
3396 | case 0xff: /* Grp5 */ |
3397 | if (c->modrm_reg == 5) | |
3398 | goto jump_far; | |
3399 | goto grp45; | |
91269b8f AK |
3400 | default: |
3401 | goto cannot_emulate; | |
6aa8b732 | 3402 | } |
018a98db AK |
3403 | |
3404 | writeback: | |
3405 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3406 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3407 | goto done; |
3408 | ||
5cd21917 GN |
3409 | /* |
3410 | * restore dst type in case the decoding will be reused | |
3411 | * (happens for string instruction ) | |
3412 | */ | |
3413 | c->dst.type = saved_dst_type; | |
3414 | ||
a682e354 | 3415 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3416 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3417 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3418 | |
3419 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3420 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3421 | &c->dst); | |
d9271123 | 3422 | |
5cd21917 | 3423 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3424 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3425 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
0fa6ccbd AK |
3426 | /* The second termination condition only applies for REPE |
3427 | * and REPNE. Test if the repeat string operation prefix is | |
3428 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3429 | * corresponding termination condition according to: | |
3430 | * - if REPE/REPZ and ZF = 0 then done | |
3431 | * - if REPNE/REPNZ and ZF = 1 then done | |
3432 | */ | |
3433 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
3434 | (c->b == 0xae) || (c->b == 0xaf)) | |
3435 | && (((c->rep_prefix == REPE_PREFIX) && | |
3436 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
3437 | || ((c->rep_prefix == REPNE_PREFIX) && | |
3438 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
3439 | ctxt->restart = false; | |
7b262e90 GN |
3440 | /* |
3441 | * Re-enter guest when pio read ahead buffer is empty or, | |
3442 | * if it is not used, after each 1024 iteration. | |
3443 | */ | |
0fa6ccbd AK |
3444 | else if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || |
3445 | (rc->end != 0 && rc->end == rc->pos)) { | |
5cd21917 | 3446 | ctxt->restart = false; |
0fa6ccbd AK |
3447 | c->eip = ctxt->eip; |
3448 | } | |
5cd21917 | 3449 | } |
9de41573 GN |
3450 | /* |
3451 | * reset read cache here in case string instruction is restared | |
3452 | * without decoding | |
3453 | */ | |
3454 | ctxt->decode.mem_read.end = 0; | |
0fa6ccbd AK |
3455 | if (!ctxt->restart) |
3456 | ctxt->eip = c->eip; | |
018a98db AK |
3457 | |
3458 | done: | |
cb404fe0 | 3459 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3460 | |
3461 | twobyte_insn: | |
e4e03ded | 3462 | switch (c->b) { |
6aa8b732 | 3463 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3464 | switch (c->modrm_reg) { |
6aa8b732 AK |
3465 | u16 size; |
3466 | unsigned long address; | |
3467 | ||
aca7f966 | 3468 | case 0: /* vmcall */ |
e4e03ded | 3469 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3470 | goto cannot_emulate; |
3471 | ||
7aa81cc0 | 3472 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3473 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3474 | goto done; |
3475 | ||
33e3885d | 3476 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3477 | c->eip = ctxt->eip; |
16286d08 AK |
3478 | /* Disable writeback. */ |
3479 | c->dst.type = OP_NONE; | |
aca7f966 | 3480 | break; |
6aa8b732 | 3481 | case 2: /* lgdt */ |
1a6440ae | 3482 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3483 | &size, &address, c->op_bytes); |
1b30eaa8 | 3484 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3485 | goto done; |
3486 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3487 | /* Disable writeback. */ |
3488 | c->dst.type = OP_NONE; | |
6aa8b732 | 3489 | break; |
aca7f966 | 3490 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3491 | if (c->modrm_mod == 3) { |
3492 | switch (c->modrm_rm) { | |
3493 | case 1: | |
3494 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3495 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3496 | goto done; |
3497 | break; | |
3498 | default: | |
3499 | goto cannot_emulate; | |
3500 | } | |
aca7f966 | 3501 | } else { |
1a6440ae | 3502 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3503 | &size, &address, |
e4e03ded | 3504 | c->op_bytes); |
1b30eaa8 | 3505 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3506 | goto done; |
3507 | realmode_lidt(ctxt->vcpu, size, address); | |
3508 | } | |
16286d08 AK |
3509 | /* Disable writeback. */ |
3510 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3511 | break; |
3512 | case 4: /* smsw */ | |
16286d08 | 3513 | c->dst.bytes = 2; |
52a46617 | 3514 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3515 | break; |
3516 | case 6: /* lmsw */ | |
9928ff60 | 3517 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3518 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3519 | c->dst.type = OP_NONE; |
6aa8b732 | 3520 | break; |
6e1e5ffe | 3521 | case 5: /* not defined */ |
54b8486f | 3522 | emulate_ud(ctxt); |
6e1e5ffe | 3523 | goto done; |
6aa8b732 | 3524 | case 7: /* invlpg*/ |
1f6f0580 | 3525 | emulate_invlpg(ctxt->vcpu, c->src.addr.mem); |
16286d08 AK |
3526 | /* Disable writeback. */ |
3527 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3528 | break; |
3529 | default: | |
3530 | goto cannot_emulate; | |
3531 | } | |
3532 | break; | |
e99f0507 | 3533 | case 0x05: /* syscall */ |
3fb1b5db | 3534 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3535 | if (rc != X86EMUL_CONTINUE) |
3536 | goto done; | |
e66bb2cc AP |
3537 | else |
3538 | goto writeback; | |
e99f0507 | 3539 | break; |
018a98db AK |
3540 | case 0x06: |
3541 | emulate_clts(ctxt->vcpu); | |
018a98db | 3542 | break; |
018a98db | 3543 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3544 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3545 | break; |
3546 | case 0x08: /* invd */ | |
018a98db AK |
3547 | case 0x0d: /* GrpP (prefetch) */ |
3548 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3549 | break; |
3550 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3551 | switch (c->modrm_reg) { |
3552 | case 1: | |
3553 | case 5 ... 7: | |
3554 | case 9 ... 15: | |
54b8486f | 3555 | emulate_ud(ctxt); |
6aebfa6e GN |
3556 | goto done; |
3557 | } | |
1a0c7d44 | 3558 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3559 | break; |
6aa8b732 | 3560 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3561 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3562 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3563 | emulate_ud(ctxt); |
1e470be5 GN |
3564 | goto done; |
3565 | } | |
b27f3856 | 3566 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 3567 | break; |
018a98db | 3568 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 3569 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 3570 | emulate_gp(ctxt, 0); |
0f12244f GN |
3571 | goto done; |
3572 | } | |
018a98db AK |
3573 | c->dst.type = OP_NONE; |
3574 | break; | |
6aa8b732 | 3575 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3576 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3577 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3578 | emulate_ud(ctxt); |
1e470be5 GN |
3579 | goto done; |
3580 | } | |
35aa5375 | 3581 | |
b27f3856 | 3582 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
3583 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
3584 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3585 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3586 | emulate_gp(ctxt, 0); |
338dbc97 GN |
3587 | goto done; |
3588 | } | |
3589 | ||
a01af5ec | 3590 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3591 | break; |
018a98db AK |
3592 | case 0x30: |
3593 | /* wrmsr */ | |
3594 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3595 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3596 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3597 | emulate_gp(ctxt, 0); |
fd525365 | 3598 | goto done; |
018a98db AK |
3599 | } |
3600 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
3601 | break; |
3602 | case 0x32: | |
3603 | /* rdmsr */ | |
3fb1b5db | 3604 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3605 | emulate_gp(ctxt, 0); |
fd525365 | 3606 | goto done; |
018a98db AK |
3607 | } else { |
3608 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3609 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3610 | } | |
3611 | rc = X86EMUL_CONTINUE; | |
018a98db | 3612 | break; |
e99f0507 | 3613 | case 0x34: /* sysenter */ |
3fb1b5db | 3614 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3615 | if (rc != X86EMUL_CONTINUE) |
3616 | goto done; | |
8c604352 AP |
3617 | else |
3618 | goto writeback; | |
e99f0507 AP |
3619 | break; |
3620 | case 0x35: /* sysexit */ | |
3fb1b5db | 3621 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3622 | if (rc != X86EMUL_CONTINUE) |
3623 | goto done; | |
4668f050 AP |
3624 | else |
3625 | goto writeback; | |
e99f0507 | 3626 | break; |
6aa8b732 | 3627 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3628 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3629 | if (!test_cc(c->b, ctxt->eflags)) |
3630 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3631 | break; |
b2833e3c | 3632 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3633 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3634 | jmp_rel(c, c->src.val); |
018a98db | 3635 | break; |
ee45b58e WY |
3636 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
3637 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
3638 | break; | |
0934ac9d | 3639 | case 0xa0: /* push fs */ |
79168fd1 | 3640 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3641 | break; |
3642 | case 0xa1: /* pop fs */ | |
3643 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3644 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3645 | goto done; |
3646 | break; | |
7de75248 NK |
3647 | case 0xa3: |
3648 | bt: /* bt */ | |
e4f8e039 | 3649 | c->dst.type = OP_NONE; |
e4e03ded LV |
3650 | /* only subword offset */ |
3651 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3652 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3653 | break; |
9bf8ea42 GT |
3654 | case 0xa4: /* shld imm8, r, r/m */ |
3655 | case 0xa5: /* shld cl, r, r/m */ | |
3656 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3657 | break; | |
0934ac9d | 3658 | case 0xa8: /* push gs */ |
79168fd1 | 3659 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3660 | break; |
3661 | case 0xa9: /* pop gs */ | |
3662 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3663 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3664 | goto done; |
3665 | break; | |
7de75248 NK |
3666 | case 0xab: |
3667 | bts: /* bts */ | |
05f086f8 | 3668 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3669 | break; |
9bf8ea42 GT |
3670 | case 0xac: /* shrd imm8, r, r/m */ |
3671 | case 0xad: /* shrd cl, r, r/m */ | |
3672 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3673 | break; | |
2a7c5b8b GC |
3674 | case 0xae: /* clflush */ |
3675 | break; | |
6aa8b732 AK |
3676 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3677 | /* | |
3678 | * Save real source value, then compare EAX against | |
3679 | * destination. | |
3680 | */ | |
e4e03ded LV |
3681 | c->src.orig_val = c->src.val; |
3682 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3683 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3684 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3685 | /* Success: write back to memory. */ |
e4e03ded | 3686 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3687 | } else { |
3688 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 3689 | c->dst.type = OP_REG; |
1a6440ae | 3690 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
3691 | } |
3692 | break; | |
09b5f4d3 WY |
3693 | case 0xb2: /* lss */ |
3694 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS); | |
3695 | if (rc != X86EMUL_CONTINUE) | |
3696 | goto done; | |
3697 | break; | |
6aa8b732 AK |
3698 | case 0xb3: |
3699 | btr: /* btr */ | |
05f086f8 | 3700 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3701 | break; |
09b5f4d3 WY |
3702 | case 0xb4: /* lfs */ |
3703 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS); | |
3704 | if (rc != X86EMUL_CONTINUE) | |
3705 | goto done; | |
3706 | break; | |
3707 | case 0xb5: /* lgs */ | |
3708 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS); | |
3709 | if (rc != X86EMUL_CONTINUE) | |
3710 | goto done; | |
3711 | break; | |
6aa8b732 | 3712 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3713 | c->dst.bytes = c->op_bytes; |
3714 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3715 | : (u16) c->src.val; | |
6aa8b732 | 3716 | break; |
6aa8b732 | 3717 | case 0xba: /* Grp8 */ |
e4e03ded | 3718 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3719 | case 0: |
3720 | goto bt; | |
3721 | case 1: | |
3722 | goto bts; | |
3723 | case 2: | |
3724 | goto btr; | |
3725 | case 3: | |
3726 | goto btc; | |
3727 | } | |
3728 | break; | |
7de75248 NK |
3729 | case 0xbb: |
3730 | btc: /* btc */ | |
05f086f8 | 3731 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3732 | break; |
d9574a25 WY |
3733 | case 0xbc: { /* bsf */ |
3734 | u8 zf; | |
3735 | __asm__ ("bsf %2, %0; setz %1" | |
3736 | : "=r"(c->dst.val), "=q"(zf) | |
3737 | : "r"(c->src.val)); | |
3738 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3739 | if (zf) { | |
3740 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3741 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3742 | } | |
3743 | break; | |
3744 | } | |
3745 | case 0xbd: { /* bsr */ | |
3746 | u8 zf; | |
3747 | __asm__ ("bsr %2, %0; setz %1" | |
3748 | : "=r"(c->dst.val), "=q"(zf) | |
3749 | : "r"(c->src.val)); | |
3750 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3751 | if (zf) { | |
3752 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3753 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3754 | } | |
3755 | break; | |
3756 | } | |
6aa8b732 | 3757 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3758 | c->dst.bytes = c->op_bytes; |
3759 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3760 | (s16) c->src.val; | |
6aa8b732 | 3761 | break; |
92f738a5 WY |
3762 | case 0xc0 ... 0xc1: /* xadd */ |
3763 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
3764 | /* Write back the register source. */ | |
3765 | c->src.val = c->dst.orig_val; | |
3766 | write_register_operand(&c->src); | |
3767 | break; | |
a012e65a | 3768 | case 0xc3: /* movnti */ |
e4e03ded LV |
3769 | c->dst.bytes = c->op_bytes; |
3770 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3771 | (u64) c->src.val; | |
a012e65a | 3772 | break; |
6aa8b732 | 3773 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3774 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3775 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3776 | goto done; |
3777 | break; | |
91269b8f AK |
3778 | default: |
3779 | goto cannot_emulate; | |
6aa8b732 AK |
3780 | } |
3781 | goto writeback; | |
3782 | ||
3783 | cannot_emulate: | |
e4e03ded | 3784 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3785 | return -1; |
3786 | } |