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KVM: x86: latch INITs while in system management mode
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
3db176d5 28#include <asm/debugreg.h>
6aa8b732 29
3eeb3288 30#include "x86.h"
38ba30ba 31#include "tss.h"
e99f0507 32
a9945549
AK		 33/*
34 * Operand types
35 */
b1ea50b2
AK		 36#define OpNone 0ull
37#define OpImplicit 1ull /* No generic decode */
38#define OpReg 2ull /* Register */
39#define OpMem 3ull /* Memory */
40#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41#define OpDI 5ull /* ES:DI/EDI/RDI */
42#define OpMem64 6ull /* Memory, 64-bit */
43#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44#define OpDX 8ull /* DX register */
4dd6a57d
AK		 45#define OpCL 9ull /* CL register (for shifts) */
46#define OpImmByte 10ull /* 8-bit sign extended immediate */
47#define OpOne 11ull /* Implied 1 */
5e2c6883 48#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 49#define OpMem16 13ull /* Memory operand (16-bit). */
50#define OpMem32 14ull /* Memory operand (32-bit). */
51#define OpImmU 15ull /* Immediate operand, zero extended */
52#define OpSI 16ull /* SI/ESI/RSI */
53#define OpImmFAddr 17ull /* Immediate far address */
54#define OpMemFAddr 18ull /* Far address in memory */
55#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 56#define OpES 20ull /* ES */
57#define OpCS 21ull /* CS */
58#define OpSS 22ull /* SS */
59#define OpDS 23ull /* DS */
60#define OpFS 24ull /* FS */
61#define OpGS 25ull /* GS */
28867cee 62#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 63#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 64#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 65#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 67
68#define OpBits 5 /* Width of operand field */
b1ea50b2 69#define OpMask ((1ull << OpBits) - 1)
a9945549 70
6aa8b732
AK		 71/*
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
77 * not be handled.
78 */
79
80/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 81#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 82/* Destination operand type. */
a9945549
AK		 83#define DstShift 1
84#define ImplicitOps (OpImplicit << DstShift)
85#define DstReg (OpReg << DstShift)
86#define DstMem (OpMem << DstShift)
87#define DstAcc (OpAcc << DstShift)
88#define DstDI (OpDI << DstShift)
89#define DstMem64 (OpMem64 << DstShift)
16bebefe 90#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 91#define DstImmUByte (OpImmUByte << DstShift)
92#define DstDX (OpDX << DstShift)
820207c8 93#define DstAccLo (OpAccLo << DstShift)
a9945549 94#define DstMask (OpMask << DstShift)
6aa8b732 95/* Source operand type. */
0fe59128
AK		 96#define SrcShift 6
97#define SrcNone (OpNone << SrcShift)
98#define SrcReg (OpReg << SrcShift)
99#define SrcMem (OpMem << SrcShift)
100#define SrcMem16 (OpMem16 << SrcShift)
101#define SrcMem32 (OpMem32 << SrcShift)
102#define SrcImm (OpImm << SrcShift)
103#define SrcImmByte (OpImmByte << SrcShift)
104#define SrcOne (OpOne << SrcShift)
105#define SrcImmUByte (OpImmUByte << SrcShift)
106#define SrcImmU (OpImmU << SrcShift)
107#define SrcSI (OpSI << SrcShift)
7fa57952 108#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 109#define SrcImmFAddr (OpImmFAddr << SrcShift)
110#define SrcMemFAddr (OpMemFAddr << SrcShift)
111#define SrcAcc (OpAcc << SrcShift)
112#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 113#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 114#define SrcDX (OpDX << SrcShift)
28867cee 115#define SrcMem8 (OpMem8 << SrcShift)
820207c8 116#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 117#define SrcMask (OpMask << SrcShift)
221192bd
MT		 118#define BitOp (1<<11)
119#define MemAbs (1<<12) /* Memory operand is absolute displacement */
120#define String (1<<13) /* String instruction (rep capable) */
121#define Stack (1<<14) /* Stack instruction (push/pop) */
122#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 127#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 128#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 129#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 130#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 131/* Generic ModRM decode. */
132#define ModRM (1<<19)
133/* Destination is only written; never read. */
134#define Mov (1<<20)
d8769fed 135/* Misc flags */
8ea7d6ae 136#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 137#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 138#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 139#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 140#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 141#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 142#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 143#define No64 (1<<28)
d5ae7ce8 144#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 145#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 146/* Source 2 operand type */
0b789eee 147#define Src2Shift (31)
4dd6a57d 148#define Src2None (OpNone << Src2Shift)
ab2c5ce6 149#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 150#define Src2CL (OpCL << Src2Shift)
151#define Src2ImmByte (OpImmByte << Src2Shift)
152#define Src2One (OpOne << Src2Shift)
153#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 154#define Src2ES (OpES << Src2Shift)
155#define Src2CS (OpCS << Src2Shift)
156#define Src2SS (OpSS << Src2Shift)
157#define Src2DS (OpDS << Src2Shift)
158#define Src2FS (OpFS << Src2Shift)
159#define Src2GS (OpGS << Src2Shift)
4dd6a57d 160#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 161#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 165#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 166#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 167#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 168#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 169#define Intercept ((u64)1 << 48) /* Has valid intercept field */
170#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 171#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 172#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 173#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 174#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 175
820207c8 176#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 177
d0e53325
AK		 178#define X2(x...) x, x
179#define X3(x...) X2(x), x
180#define X4(x...) X2(x), X2(x)
181#define X5(x...) X4(x), x
182#define X6(x...) X4(x), X2(x)
183#define X7(x...) X4(x), X3(x)
184#define X8(x...) X4(x), X4(x)
185#define X16(x...) X8(x), X8(x)
83babbca 186
e28bbd44
AK		 187#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
188#define FASTOP_SIZE 8
189
190/*
191 * fastop functions have a special calling convention:
192 *
017da7b6
AK		 193 * dst: rax (in/out)
194 * src: rdx (in/out)
e28bbd44
AK		 195 * src2: rcx (in)
196 * flags: rflags (in/out)
b8c0b6ae 197 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 198 *
199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
200 * different operand sizes can be reached by calculation, rather than a jump
201 * table (which would be bigger than the code).
202 *
203 * fastop functions are declared as taking a never-defined fastop parameter,
204 * so they can't be called from C directly.
205 */
206
207struct fastop;
208
d65b1dee 209struct opcode {
b1ea50b2
AK		 210 u64 flags : 56;
211 u64 intercept : 8;
120df890 212 union {
ef65c889 213 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 214 const struct opcode *group;
215 const struct group_dual *gdual;
216 const struct gprefix *gprefix;
045a282c 217 const struct escape *esc;
39f062ff 218 const struct instr_dual *idual;
2276b511 219 const struct mode_dual *mdual;
e28bbd44 220 void (*fastop)(struct fastop *fake);
120df890 221 } u;
d09beabd 222 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 223};
224
225struct group_dual {
226 struct opcode mod012[8];
227 struct opcode mod3[8];
d65b1dee
AK		 228};
229
0d7cdee8
AK		 230struct gprefix {
231 struct opcode pfx_no;
232 struct opcode pfx_66;
233 struct opcode pfx_f2;
234 struct opcode pfx_f3;
235};
236
045a282c
GN		 237struct escape {
238 struct opcode op[8];
239 struct opcode high[64];
240};
241
39f062ff
NA		 242struct instr_dual {
243 struct opcode mod012;
244 struct opcode mod3;
245};
246
2276b511
NA		 247struct mode_dual {
248 struct opcode mode32;
249 struct opcode mode64;
250};
251
62bd430e 252#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 253
3dc4bc4f
NA		 254enum x86_transfer_type {
255 X86_TRANSFER_NONE,
256 X86_TRANSFER_CALL_JMP,
257 X86_TRANSFER_RET,
258 X86_TRANSFER_TASK_SWITCH,
259};
260
dd856efa
AK		 261static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 if (!(ctxt->regs_valid & (1 << nr))) {
264 ctxt->regs_valid |= 1 << nr;
265 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
266 }
267 return ctxt->_regs[nr];
268}
269
270static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 ctxt->regs_valid |= 1 << nr;
273 ctxt->regs_dirty |= 1 << nr;
274 return &ctxt->_regs[nr];
275}
276
277static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
278{
279 reg_read(ctxt, nr);
280 return reg_write(ctxt, nr);
281}
282
283static void writeback_registers(struct x86_emulate_ctxt *ctxt)
284{
285 unsigned reg;
286
287 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
288 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
289}
290
291static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
292{
293 ctxt->regs_dirty = 0;
294 ctxt->regs_valid = 0;
295}
296
6aa8b732
AK		 297/*
298 * These EFLAGS bits are restored from saved value during emulation, and
299 * any changes are written back to the saved value after emulation.
300 */
0efb0440
NA		 301#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
302 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 303
dda96d8f
AK		 304#ifdef CONFIG_X86_64
305#define ON64(x) x
306#else
307#define ON64(x)
308#endif
309
4d758349
AK		 310static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
311
b7d491e7
AK		 312#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
313#define FOP_RET "ret \n\t"
314
315#define FOP_START(op) \
316 extern void em_##op(struct fastop *fake); \
317 asm(".pushsection .text, \"ax\" \n\t" \
318 ".global em_" #op " \n\t" \
319 FOP_ALIGN \
320 "em_" #op ": \n\t"
321
322#define FOP_END \
323 ".popsection")
324
0bdea068
AK		 325#define FOPNOP() FOP_ALIGN FOP_RET
326
b7d491e7 327#define FOP1E(op, dst) \
b8c0b6ae
AK		 328 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
329
330#define FOP1EEX(op, dst) \
331 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 332
333#define FASTOP1(op) \
334 FOP_START(op) \
335 FOP1E(op##b, al) \
336 FOP1E(op##w, ax) \
337 FOP1E(op##l, eax) \
338 ON64(FOP1E(op##q, rax)) \
339 FOP_END
340
b9fa409b
AK		 341/* 1-operand, using src2 (for MUL/DIV r/m) */
342#define FASTOP1SRC2(op, name) \
343 FOP_START(name) \
344 FOP1E(op, cl) \
345 FOP1E(op, cx) \
346 FOP1E(op, ecx) \
347 ON64(FOP1E(op, rcx)) \
348 FOP_END
349
b8c0b6ae
AK		 350/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
351#define FASTOP1SRC2EX(op, name) \
352 FOP_START(name) \
353 FOP1EEX(op, cl) \
354 FOP1EEX(op, cx) \
355 FOP1EEX(op, ecx) \
356 ON64(FOP1EEX(op, rcx)) \
357 FOP_END
358
f7857f35
AK		 359#define FOP2E(op, dst, src) \
360 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
361
362#define FASTOP2(op) \
363 FOP_START(op) \
017da7b6
AK		 364 FOP2E(op##b, al, dl) \
365 FOP2E(op##w, ax, dx) \
366 FOP2E(op##l, eax, edx) \
367 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 368 FOP_END
369
11c363ba
AK		 370/* 2 operand, word only */
371#define FASTOP2W(op) \
372 FOP_START(op) \
373 FOPNOP() \
017da7b6
AK		 374 FOP2E(op##w, ax, dx) \
375 FOP2E(op##l, eax, edx) \
376 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 377 FOP_END
378
007a3b54
AK		 379/* 2 operand, src is CL */
380#define FASTOP2CL(op) \
381 FOP_START(op) \
382 FOP2E(op##b, al, cl) \
383 FOP2E(op##w, ax, cl) \
384 FOP2E(op##l, eax, cl) \
385 ON64(FOP2E(op##q, rax, cl)) \
386 FOP_END
387
5aca3722
NA		 388/* 2 operand, src and dest are reversed */
389#define FASTOP2R(op, name) \
390 FOP_START(name) \
391 FOP2E(op##b, dl, al) \
392 FOP2E(op##w, dx, ax) \
393 FOP2E(op##l, edx, eax) \
394 ON64(FOP2E(op##q, rdx, rax)) \
395 FOP_END
396
0bdea068
AK		 397#define FOP3E(op, dst, src, src2) \
398 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
399
400/* 3-operand, word-only, src2=cl */
401#define FASTOP3WCL(op) \
402 FOP_START(op) \
403 FOPNOP() \
017da7b6
AK		 404 FOP3E(op##w, ax, dx, cl) \
405 FOP3E(op##l, eax, edx, cl) \
406 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 407 FOP_END
408
9ae9feba
AK		 409/* Special case for SETcc - 1 instruction per cc */
410#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
411
b8c0b6ae
AK		 412asm(".global kvm_fastop_exception \n"
413 "kvm_fastop_exception: xor %esi, %esi; ret");
414
9ae9feba
AK		 415FOP_START(setcc)
416FOP_SETCC(seto)
417FOP_SETCC(setno)
418FOP_SETCC(setc)
419FOP_SETCC(setnc)
420FOP_SETCC(setz)
421FOP_SETCC(setnz)
422FOP_SETCC(setbe)
423FOP_SETCC(setnbe)
424FOP_SETCC(sets)
425FOP_SETCC(setns)
426FOP_SETCC(setp)
427FOP_SETCC(setnp)
428FOP_SETCC(setl)
429FOP_SETCC(setnl)
430FOP_SETCC(setle)
431FOP_SETCC(setnle)
432FOP_END;
433
326f578f
PB		 434FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
435FOP_END;
436
8a76d7f2
JR		 437static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
438 enum x86_intercept intercept,
439 enum x86_intercept_stage stage)
440{
441 struct x86_instruction_info info = {
442 .intercept = intercept,
9dac77fa
AK		 443 .rep_prefix = ctxt->rep_prefix,
444 .modrm_mod = ctxt->modrm_mod,
445 .modrm_reg = ctxt->modrm_reg,
446 .modrm_rm = ctxt->modrm_rm,
447 .src_val = ctxt->src.val64,
6cbc5f5a 448 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 449 .src_bytes = ctxt->src.bytes,
450 .dst_bytes = ctxt->dst.bytes,
451 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 452 .next_rip = ctxt->eip,
453 };
454
2953538e 455 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 456}
457
f47cfa31
AK		 458static void assign_masked(ulong *dest, ulong src, ulong mask)
459{
460 *dest = (*dest & ~mask) | (src & mask);
461}
462
6fd8e127
NA		 463static void assign_register(unsigned long *reg, u64 val, int bytes)
464{
465 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
466 switch (bytes) {
467 case 1:
468 *(u8 *)reg = (u8)val;
469 break;
470 case 2:
471 *(u16 *)reg = (u16)val;
472 break;
473 case 4:
474 *reg = (u32)val;
475 break; /* 64b: zero-extend */
476 case 8:
477 *reg = val;
478 break;
479 }
480}
481
9dac77fa 482static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 483{
9dac77fa 484 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 485}
486
f47cfa31
AK		 487static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
488{
489 u16 sel;
490 struct desc_struct ss;
491
492 if (ctxt->mode == X86EMUL_MODE_PROT64)
493 return ~0UL;
494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
496}
497
612e89f0
AK		 498static int stack_size(struct x86_emulate_ctxt *ctxt)
499{
500 return (__fls(stack_mask(ctxt)) + 1) >> 3;
501}
502
6aa8b732 503/* Access/update address held in a register, based on addressing mode. */
e4706772 504static inline unsigned long
9dac77fa 505address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 506{
9dac77fa 507 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 508 return reg;
509 else
9dac77fa 510 return reg & ad_mask(ctxt);
e4706772
HH		 511}
512
513static inline unsigned long
01485a22 514register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 515{
01485a22 516 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 517}
518
5ad105e5
AK		 519static void masked_increment(ulong *reg, ulong mask, int inc)
520{
521 assign_masked(reg, *reg + inc, mask);
522}
523
7a957275 524static inline void
01485a22 525register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 526{
ee122a71 527 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 528
ee122a71 529 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 530}
531
532static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
533{
dd856efa 534 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 535}
6aa8b732 536
56697687
AK		 537static u32 desc_limit_scaled(struct desc_struct *desc)
538{
539 u32 limit = get_desc_limit(desc);
540
541 return desc->g ? (limit << 12) | 0xfff : limit;
542}
543
7b105ca2 544static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 545{
546 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
547 return 0;
548
7b105ca2 549 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 550}
551
35d3d4a1
AK		 552static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
553 u32 error, bool valid)
54b8486f 554{
e0ad0b47 555 WARN_ON(vec > 0x1f);
da9cb575
AK		 556 ctxt->exception.vector = vec;
557 ctxt->exception.error_code = error;
558 ctxt->exception.error_code_valid = valid;
35d3d4a1 559 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 560}
561
3b88e41a
JR		 562static int emulate_db(struct x86_emulate_ctxt *ctxt)
563{
564 return emulate_exception(ctxt, DB_VECTOR, 0, false);
565}
566
35d3d4a1 567static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 568{
35d3d4a1 569 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 570}
571
618ff15d
AK		 572static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
573{
574 return emulate_exception(ctxt, SS_VECTOR, err, true);
575}
576
35d3d4a1 577static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 578{
35d3d4a1 579 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 580}
581
35d3d4a1 582static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 583{
35d3d4a1 584 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 585}
586
34d1f490
AK		 587static int emulate_de(struct x86_emulate_ctxt *ctxt)
588{
35d3d4a1 589 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 590}
591
1253791d
AK		 592static int emulate_nm(struct x86_emulate_ctxt *ctxt)
593{
594 return emulate_exception(ctxt, NM_VECTOR, 0, false);
595}
596
1aa36616
AK		 597static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
598{
599 u16 selector;
600 struct desc_struct desc;
601
602 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
603 return selector;
604}
605
606static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
607 unsigned seg)
608{
609 u16 dummy;
610 u32 base3;
611 struct desc_struct desc;
612
613 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
614 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
615}
616
1c11b376
AK		 617/*
618 * x86 defines three classes of vector instructions: explicitly
619 * aligned, explicitly unaligned, and the rest, which change behaviour
620 * depending on whether they're AVX encoded or not.
621 *
622 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
623 * subject to the same check.
624 */
625static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
626{
627 if (likely(size < 16))
628 return false;
629
630 if (ctxt->d & Aligned)
631 return true;
632 else if (ctxt->d & Unaligned)
633 return false;
634 else if (ctxt->d & Avx)
635 return false;
636 else
637 return true;
638}
639
d09155d2
PB		 640static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
641 struct segmented_address addr,
642 unsigned *max_size, unsigned size,
643 bool write, bool fetch,
d50eaa18 644 enum x86emul_mode mode, ulong *linear)
52fd8b44 645{
618ff15d
AK		 646 struct desc_struct desc;
647 bool usable;
52fd8b44 648 ulong la;
618ff15d 649 u32 lim;
1aa36616 650 u16 sel;
52fd8b44 651
7b105ca2 652 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 653 *max_size = 0;
d50eaa18 654 switch (mode) {
618ff15d 655 case X86EMUL_MODE_PROT64:
4be4de7e 656 if (is_noncanonical_address(la))
abc7d8a4 657 goto bad;
fd56e154
PB		 658
659 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
660 if (size > *max_size)
661 goto bad;
618ff15d
AK		 662 break;
663 default:
1aa36616
AK		 664 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
665 addr.seg);
618ff15d
AK		 666 if (!usable)
667 goto bad;
58b7825b
GN		 668 /* code segment in protected mode or read-only data segment */
669 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
670 || !(desc.type & 2)) && write)
618ff15d
AK		 671 goto bad;
672 /* unreadable code segment */
3d9b938e 673 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 674 goto bad;
675 lim = desc_limit_scaled(&desc);
997b0412 676 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 677 /* expand-down segment */
fd56e154 678 if (addr.ea <= lim)
618ff15d
AK		 679 goto bad;
680 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 681 }
997b0412
PB		 682 if (addr.ea > lim)
683 goto bad;
bac15531
NA		 684 if (lim == 0xffffffff)
685 *max_size = ~0u;
686 else {
687 *max_size = (u64)lim + 1 - addr.ea;
688 if (size > *max_size)
689 goto bad;
690 }
31ff6488 691 la &= (u32)-1;
618ff15d
AK		 692 break;
693 }
1c11b376
AK		 694 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
695 return emulate_gp(ctxt, 0);
52fd8b44
AK		 696 *linear = la;
697 return X86EMUL_CONTINUE;
618ff15d
AK		 698bad:
699 if (addr.seg == VCPU_SREG_SS)
3606189f 700 return emulate_ss(ctxt, 0);
618ff15d 701 else
3606189f 702 return emulate_gp(ctxt, 0);
52fd8b44
AK		 703}
704
3d9b938e
NE		 705static int linearize(struct x86_emulate_ctxt *ctxt,
706 struct segmented_address addr,
707 unsigned size, bool write,
708 ulong *linear)
709{
fd56e154 710 unsigned max_size;
d50eaa18
NA		 711 return __linearize(ctxt, addr, &max_size, size, write, false,
712 ctxt->mode, linear);
3d9b938e
NE		 713}
714
d50eaa18
NA		 715static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
716 enum x86emul_mode mode)
717{
718 ulong linear;
719 int rc;
720 unsigned max_size;
721 struct segmented_address addr = { .seg = VCPU_SREG_CS,
722 .ea = dst };
723
724 if (ctxt->op_bytes != sizeof(unsigned long))
725 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
726 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
727 if (rc == X86EMUL_CONTINUE)
728 ctxt->_eip = addr.ea;
729 return rc;
730}
731
732static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
733{
734 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 735}
736
d50eaa18
NA		 737static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
738 const struct desc_struct *cs_desc)
739{
740 enum x86emul_mode mode = ctxt->mode;
82268083 741 int rc;
d50eaa18
NA		 742
743#ifdef CONFIG_X86_64
82268083
NA		 744 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
745 if (cs_desc->l) {
746 u64 efer = 0;
d50eaa18 747
82268083
NA		 748 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
749 if (efer & EFER_LMA)
750 mode = X86EMUL_MODE_PROT64;
751 } else
752 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 753 }
754#endif
755 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
756 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 757 rc = assign_eip(ctxt, dst, mode);
758 if (rc == X86EMUL_CONTINUE)
759 ctxt->mode = mode;
760 return rc;
d50eaa18
NA		 761}
762
763static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
764{
765 return assign_eip_near(ctxt, ctxt->_eip + rel);
766}
3d9b938e 767
3ca3ac4d
AK		 768static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
769 struct segmented_address addr,
770 void *data,
771 unsigned size)
772{
9fa088f4
AK		 773 int rc;
774 ulong linear;
775
83b8795a 776 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 777 if (rc != X86EMUL_CONTINUE)
778 return rc;
0f65dd70 779 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 780}
781
807941b1 782/*
285ca9e9 783 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 784 * boundary if they are not in fetch_cache yet.
785 */
9506d57d 786static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 787{
62266869 788 int rc;
fd56e154 789 unsigned size, max_size;
285ca9e9 790 unsigned long linear;
17052f16 791 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 792 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 793 .ea = ctxt->eip + cur_size };
794
fd56e154
PB		 795 /*
796 * We do not know exactly how many bytes will be needed, and
797 * __linearize is expensive, so fetch as much as possible. We
798 * just have to avoid going beyond the 15 byte limit, the end
799 * of the segment, or the end of the page.
800 *
801 * __linearize is called with size 0 so that it does not do any
802 * boundary check itself. Instead, we use max_size to check
803 * against op_size.
804 */
d50eaa18
NA		 805 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
806 &linear);
719d5a9b
PB		 807 if (unlikely(rc != X86EMUL_CONTINUE))
808 return rc;
809
fd56e154 810 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 811 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 812
813 /*
814 * One instruction can only straddle two pages,
815 * and one has been loaded at the beginning of
816 * x86_decode_insn. So, if not enough bytes
817 * still, we must have hit the 15-byte boundary.
818 */
819 if (unlikely(size < op_size))
fd56e154
PB		 820 return emulate_gp(ctxt, 0);
821
17052f16 822 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 823 size, &ctxt->exception);
824 if (unlikely(rc != X86EMUL_CONTINUE))
825 return rc;
17052f16 826 ctxt->fetch.end += size;
3e2815e9 827 return X86EMUL_CONTINUE;
62266869
AK		 828}
829
9506d57d
PB		 830static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
831 unsigned size)
62266869 832{
08da44ae
NA		 833 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
834
835 if (unlikely(done_size < size))
836 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 837 else
838 return X86EMUL_CONTINUE;
62266869
AK		 839}
840
67cbc90d 841/* Fetch next part of the instruction being emulated. */
e85a1085 842#define insn_fetch(_type, _ctxt) \
9506d57d 843({ _type _x; \
9506d57d
PB		 844 \
845 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 846 if (rc != X86EMUL_CONTINUE) \
847 goto done; \
9506d57d 848 ctxt->_eip += sizeof(_type); \
17052f16
PB		 849 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
850 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 851 _x; \
67cbc90d
TY		 852})
853
807941b1 854#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 855({ \
9506d57d 856 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 857 if (rc != X86EMUL_CONTINUE) \
858 goto done; \
9506d57d 859 ctxt->_eip += (_size); \
17052f16
PB		 860 memcpy(_arr, ctxt->fetch.ptr, _size); \
861 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 862})
863
1e3c5cb0
RR		 864/*
865 * Given the 'reg' portion of a ModRM byte, and a register block, return a
866 * pointer into the block that addresses the relevant register.
867 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
868 */
dd856efa 869static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 870 int byteop)
6aa8b732
AK		 871{
872 void *p;
aa9ac1a6 873 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 874
6aa8b732 875 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 876 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
877 else
878 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 879 return p;
880}
881
882static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 883 struct segmented_address addr,
6aa8b732
AK		 884 u16 *size, unsigned long *address, int op_bytes)
885{
886 int rc;
887
888 if (op_bytes == 2)
889 op_bytes = 3;
890 *address = 0;
3ca3ac4d 891 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 892 if (rc != X86EMUL_CONTINUE)
6aa8b732 893 return rc;
30b31ab6 894 addr.ea += 2;
3ca3ac4d 895 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 896 return rc;
897}
898
34b77652
AK		 899FASTOP2(add);
900FASTOP2(or);
901FASTOP2(adc);
902FASTOP2(sbb);
903FASTOP2(and);
904FASTOP2(sub);
905FASTOP2(xor);
906FASTOP2(cmp);
907FASTOP2(test);
908
b9fa409b
AK		 909FASTOP1SRC2(mul, mul_ex);
910FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 911FASTOP1SRC2EX(div, div_ex);
912FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 913
34b77652
AK		 914FASTOP3WCL(shld);
915FASTOP3WCL(shrd);
916
917FASTOP2W(imul);
918
919FASTOP1(not);
920FASTOP1(neg);
921FASTOP1(inc);
922FASTOP1(dec);
923
924FASTOP2CL(rol);
925FASTOP2CL(ror);
926FASTOP2CL(rcl);
927FASTOP2CL(rcr);
928FASTOP2CL(shl);
929FASTOP2CL(shr);
930FASTOP2CL(sar);
931
932FASTOP2W(bsf);
933FASTOP2W(bsr);
934FASTOP2W(bt);
935FASTOP2W(bts);
936FASTOP2W(btr);
937FASTOP2W(btc);
938
e47a5f5f
AK		 939FASTOP2(xadd);
940
5aca3722
NA		 941FASTOP2R(cmp, cmp_r);
942
900efe20
NA		 943static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
944{
945 /* If src is zero, do not writeback, but update flags */
946 if (ctxt->src.val == 0)
947 ctxt->dst.type = OP_NONE;
948 return fastop(ctxt, em_bsf);
949}
950
951static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
952{
953 /* If src is zero, do not writeback, but update flags */
954 if (ctxt->src.val == 0)
955 ctxt->dst.type = OP_NONE;
956 return fastop(ctxt, em_bsr);
957}
958
9ae9feba 959static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 960{
9ae9feba
AK		 961 u8 rc;
962 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 963
9ae9feba 964 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 965 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 966 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
967 return rc;
bbe9abbd
NK		 968}
969
91ff3cb4
AK		 970static void fetch_register_operand(struct operand *op)
971{
972 switch (op->bytes) {
973 case 1:
974 op->val = *(u8 *)op->addr.reg;
975 break;
976 case 2:
977 op->val = *(u16 *)op->addr.reg;
978 break;
979 case 4:
980 op->val = *(u32 *)op->addr.reg;
981 break;
982 case 8:
983 op->val = *(u64 *)op->addr.reg;
984 break;
985 }
986}
987
1253791d
AK		 988static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
989{
990 ctxt->ops->get_fpu(ctxt);
991 switch (reg) {
89a87c67
MK		 992 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
993 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
994 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
995 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
996 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
997 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
998 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
999 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1000#ifdef CONFIG_X86_64
89a87c67
MK		 1001 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1002 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1003 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1004 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1005 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1006 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1007 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1008 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1009#endif
1010 default: BUG();
1011 }
1012 ctxt->ops->put_fpu(ctxt);
1013}
1014
1015static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1016 int reg)
1017{
1018 ctxt->ops->get_fpu(ctxt);
1019 switch (reg) {
89a87c67
MK		 1020 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1021 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1022 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1023 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1024 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1025 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1026 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1027 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1028#ifdef CONFIG_X86_64
89a87c67
MK		 1029 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1030 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1031 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1032 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1033 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1034 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1035 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1036 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1037#endif
1038 default: BUG();
1039 }
1040 ctxt->ops->put_fpu(ctxt);
1041}
1042
cbe2c9d3
AK		 1043static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1044{
1045 ctxt->ops->get_fpu(ctxt);
1046 switch (reg) {
1047 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1048 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1049 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1050 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1051 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1052 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1053 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1054 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1055 default: BUG();
1056 }
1057 ctxt->ops->put_fpu(ctxt);
1058}
1059
1060static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1061{
1062 ctxt->ops->get_fpu(ctxt);
1063 switch (reg) {
1064 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1065 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1066 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1067 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1068 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1069 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1070 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1071 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1072 default: BUG();
1073 }
1074 ctxt->ops->put_fpu(ctxt);
1075}
1076
045a282c
GN		 1077static int em_fninit(struct x86_emulate_ctxt *ctxt)
1078{
1079 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1080 return emulate_nm(ctxt);
1081
1082 ctxt->ops->get_fpu(ctxt);
1083 asm volatile("fninit");
1084 ctxt->ops->put_fpu(ctxt);
1085 return X86EMUL_CONTINUE;
1086}
1087
1088static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1089{
1090 u16 fcw;
1091
1092 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1093 return emulate_nm(ctxt);
1094
1095 ctxt->ops->get_fpu(ctxt);
1096 asm volatile("fnstcw %0": "+m"(fcw));
1097 ctxt->ops->put_fpu(ctxt);
1098
045a282c
GN		 1099 ctxt->dst.val = fcw;
1100
1101 return X86EMUL_CONTINUE;
1102}
1103
1104static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1105{
1106 u16 fsw;
1107
1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1109 return emulate_nm(ctxt);
1110
1111 ctxt->ops->get_fpu(ctxt);
1112 asm volatile("fnstsw %0": "+m"(fsw));
1113 ctxt->ops->put_fpu(ctxt);
1114
045a282c
GN		 1115 ctxt->dst.val = fsw;
1116
1117 return X86EMUL_CONTINUE;
1118}
1119
1253791d 1120static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1121 struct operand *op)
3c118e24 1122{
9dac77fa 1123 unsigned reg = ctxt->modrm_reg;
33615aa9 1124
9dac77fa
AK		 1125 if (!(ctxt->d & ModRM))
1126 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1127
9dac77fa 1128 if (ctxt->d & Sse) {
1253791d
AK		 1129 op->type = OP_XMM;
1130 op->bytes = 16;
1131 op->addr.xmm = reg;
1132 read_sse_reg(ctxt, &op->vec_val, reg);
1133 return;
1134 }
cbe2c9d3
AK		 1135 if (ctxt->d & Mmx) {
1136 reg &= 7;
1137 op->type = OP_MM;
1138 op->bytes = 8;
1139 op->addr.mm = reg;
1140 return;
1141 }
1253791d 1142
3c118e24 1143 op->type = OP_REG;
6d4d85ec
GN		 1144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1145 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1146
91ff3cb4 1147 fetch_register_operand(op);
3c118e24
AK		 1148 op->orig_val = op->val;
1149}
1150
a6e3407b
AK		 1151static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1152{
1153 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1154 ctxt->modrm_seg = VCPU_SREG_SS;
1155}
1156
1c73ef66 1157static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1158 struct operand *op)
1c73ef66 1159{
1c73ef66 1160 u8 sib;
02357bdc 1161 int index_reg, base_reg, scale;
3e2815e9 1162 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1163 ulong modrm_ea = 0;
1c73ef66 1164
02357bdc
BD		 1165 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1166 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1167 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1168
02357bdc 1169 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1170 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1171 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1172 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1173
9b88ae99 1174 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1175 op->type = OP_REG;
9dac77fa 1176 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1177 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1178 ctxt->d & ByteOp);
9dac77fa 1179 if (ctxt->d & Sse) {
1253791d
AK		 1180 op->type = OP_XMM;
1181 op->bytes = 16;
9dac77fa
AK		 1182 op->addr.xmm = ctxt->modrm_rm;
1183 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1184 return rc;
1185 }
cbe2c9d3
AK		 1186 if (ctxt->d & Mmx) {
1187 op->type = OP_MM;
1188 op->bytes = 8;
bdc90722 1189 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1190 return rc;
1191 }
2dbd0dd7 1192 fetch_register_operand(op);
1c73ef66
AK		 1193 return rc;
1194 }
1195
2dbd0dd7
AK		 1196 op->type = OP_MEM;
1197
9dac77fa 1198 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1199 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1200 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1201 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1202 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1203
1204 /* 16-bit ModR/M decode. */
9dac77fa 1205 switch (ctxt->modrm_mod) {
1c73ef66 1206 case 0:
9dac77fa 1207 if (ctxt->modrm_rm == 6)
e85a1085 1208 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1209 break;
1210 case 1:
e85a1085 1211 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1212 break;
1213 case 2:
e85a1085 1214 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1215 break;
1216 }
9dac77fa 1217 switch (ctxt->modrm_rm) {
1c73ef66 1218 case 0:
2dbd0dd7 1219 modrm_ea += bx + si;
1c73ef66
AK		 1220 break;
1221 case 1:
2dbd0dd7 1222 modrm_ea += bx + di;
1c73ef66
AK		 1223 break;
1224 case 2:
2dbd0dd7 1225 modrm_ea += bp + si;
1c73ef66
AK		 1226 break;
1227 case 3:
2dbd0dd7 1228 modrm_ea += bp + di;
1c73ef66
AK		 1229 break;
1230 case 4:
2dbd0dd7 1231 modrm_ea += si;
1c73ef66
AK		 1232 break;
1233 case 5:
2dbd0dd7 1234 modrm_ea += di;
1c73ef66
AK		 1235 break;
1236 case 6:
9dac77fa 1237 if (ctxt->modrm_mod != 0)
2dbd0dd7 1238 modrm_ea += bp;
1c73ef66
AK		 1239 break;
1240 case 7:
2dbd0dd7 1241 modrm_ea += bx;
1c73ef66
AK		 1242 break;
1243 }
9dac77fa
AK		 1244 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1245 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1246 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1247 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1248 } else {
1249 /* 32/64-bit ModR/M decode. */
9dac77fa 1250 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1251 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1252 index_reg |= (sib >> 3) & 7;
1253 base_reg |= sib & 7;
1254 scale = sib >> 6;
1255
9dac77fa 1256 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1257 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1258 else {
dd856efa 1259 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1260 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1261 /* Increment ESP on POP [ESP] */
1262 if ((ctxt->d & IncSP) &&
1263 base_reg == VCPU_REGS_RSP)
1264 modrm_ea += ctxt->op_bytes;
a6e3407b 1265 }
dc71d0f1 1266 if (index_reg != 4)
dd856efa 1267 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1268 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1269 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1270 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1271 ctxt->rip_relative = 1;
a6e3407b
AK		 1272 } else {
1273 base_reg = ctxt->modrm_rm;
dd856efa 1274 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1275 adjust_modrm_seg(ctxt, base_reg);
1276 }
9dac77fa 1277 switch (ctxt->modrm_mod) {
1c73ef66 1278 case 1:
e85a1085 1279 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1280 break;
1281 case 2:
e85a1085 1282 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1283 break;
1284 }
1285 }
90de84f5 1286 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1287 if (ctxt->ad_bytes != 8)
1288 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1289
1c73ef66
AK		 1290done:
1291 return rc;
1292}
1293
1294static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1295 struct operand *op)
1c73ef66 1296{
3e2815e9 1297 int rc = X86EMUL_CONTINUE;
1c73ef66 1298
2dbd0dd7 1299 op->type = OP_MEM;
9dac77fa 1300 switch (ctxt->ad_bytes) {
1c73ef66 1301 case 2:
e85a1085 1302 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1303 break;
1304 case 4:
e85a1085 1305 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1306 break;
1307 case 8:
e85a1085 1308 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1309 break;
1310 }
1311done:
1312 return rc;
1313}
1314
9dac77fa 1315static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1316{
7129eeca 1317 long sv = 0, mask;
35c843c4 1318
9dac77fa 1319 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1320 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1321
9dac77fa
AK		 1322 if (ctxt->src.bytes == 2)
1323 sv = (s16)ctxt->src.val & (s16)mask;
1324 else if (ctxt->src.bytes == 4)
1325 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1326 else
1327 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1328
1c1c35ae
NA		 1329 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1330 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1331 }
ba7ff2b7
WY		 1332
1333 /* only subword offset */
9dac77fa 1334 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1335}
1336
dde7e6d1 1337static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1338 unsigned long addr, void *dest, unsigned size)
6aa8b732 1339{
dde7e6d1 1340 int rc;
9dac77fa 1341 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1342
f23b070e
XG		 1343 if (mc->pos < mc->end)
1344 goto read_cached;
6aa8b732 1345
f23b070e
XG		 1346 WARN_ON((mc->end + size) >= sizeof(mc->data));
1347
1348 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1349 &ctxt->exception);
1350 if (rc != X86EMUL_CONTINUE)
1351 return rc;
1352
1353 mc->end += size;
1354
1355read_cached:
1356 memcpy(dest, mc->data + mc->pos, size);
1357 mc->pos += size;
dde7e6d1
AK		 1358 return X86EMUL_CONTINUE;
1359}
6aa8b732 1360
3ca3ac4d
AK		 1361static int segmented_read(struct x86_emulate_ctxt *ctxt,
1362 struct segmented_address addr,
1363 void *data,
1364 unsigned size)
1365{
9fa088f4
AK		 1366 int rc;
1367 ulong linear;
1368
83b8795a 1369 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1370 if (rc != X86EMUL_CONTINUE)
1371 return rc;
7b105ca2 1372 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1373}
1374
1375static int segmented_write(struct x86_emulate_ctxt *ctxt,
1376 struct segmented_address addr,
1377 const void *data,
1378 unsigned size)
1379{
9fa088f4
AK		 1380 int rc;
1381 ulong linear;
1382
83b8795a 1383 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1384 if (rc != X86EMUL_CONTINUE)
1385 return rc;
0f65dd70
AK		 1386 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1387 &ctxt->exception);
3ca3ac4d
AK		 1388}
1389
1390static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1391 struct segmented_address addr,
1392 const void *orig_data, const void *data,
1393 unsigned size)
1394{
9fa088f4
AK		 1395 int rc;
1396 ulong linear;
1397
83b8795a 1398 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1399 if (rc != X86EMUL_CONTINUE)
1400 return rc;
0f65dd70
AK		 1401 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1402 size, &ctxt->exception);
3ca3ac4d
AK		 1403}
1404
dde7e6d1 1405static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1406 unsigned int size, unsigned short port,
1407 void *dest)
1408{
9dac77fa 1409 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1410
dde7e6d1 1411 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1412 unsigned int in_page, n;
9dac77fa 1413 unsigned int count = ctxt->rep_prefix ?
dd856efa 1414 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1415 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1416 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1417 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1418 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1419 if (n == 0)
1420 n = 1;
1421 rc->pos = rc->end = 0;
7b105ca2 1422 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1423 return 0;
1424 rc->end = n * size;
6aa8b732
AK		 1425 }
1426
e6e39f04 1427 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1428 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1429 ctxt->dst.data = rc->data + rc->pos;
1430 ctxt->dst.type = OP_MEM_STR;
1431 ctxt->dst.count = (rc->end - rc->pos) / size;
1432 rc->pos = rc->end;
1433 } else {
1434 memcpy(dest, rc->data + rc->pos, size);
1435 rc->pos += size;
1436 }
dde7e6d1
AK		 1437 return 1;
1438}
6aa8b732 1439
7f3d35fd
KW		 1440static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1441 u16 index, struct desc_struct *desc)
1442{
1443 struct desc_ptr dt;
1444 ulong addr;
1445
1446 ctxt->ops->get_idt(ctxt, &dt);
1447
1448 if (dt.size < index * 8 + 7)
1449 return emulate_gp(ctxt, index << 3 | 0x2);
1450
1451 addr = dt.address + index * 8;
1452 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1453 &ctxt->exception);
1454}
1455
dde7e6d1 1456static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1457 u16 selector, struct desc_ptr *dt)
1458{
0225fb50 1459 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1460 u32 base3 = 0;
7b105ca2 1461
dde7e6d1
AK		 1462 if (selector & 1 << 2) {
1463 struct desc_struct desc;
1aa36616
AK		 1464 u16 sel;
1465
dde7e6d1 1466 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1467 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1468 VCPU_SREG_LDTR))
dde7e6d1 1469 return;
e09d082c 1470
dde7e6d1 1471 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1472 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1473 } else
4bff1e86 1474 ops->get_gdt(ctxt, dt);
dde7e6d1 1475}
120df890 1476
edccda7c
NA		 1477static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1478 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1479{
1480 struct desc_ptr dt;
1481 u16 index = selector >> 3;
dde7e6d1 1482 ulong addr;
120df890 1483
7b105ca2 1484 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1485
35d3d4a1
AK		 1486 if (dt.size < index * 8 + 7)
1487 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1488
edccda7c
NA		 1489 addr = dt.address + index * 8;
1490
1491#ifdef CONFIG_X86_64
1492 if (addr >> 32 != 0) {
1493 u64 efer = 0;
1494
1495 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1496 if (!(efer & EFER_LMA))
1497 addr &= (u32)-1;
1498 }
1499#endif
1500
1501 *desc_addr_p = addr;
1502 return X86EMUL_CONTINUE;
1503}
1504
1505/* allowed just for 8 bytes segments */
1506static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1507 u16 selector, struct desc_struct *desc,
1508 ulong *desc_addr_p)
1509{
1510 int rc;
1511
1512 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1513 if (rc != X86EMUL_CONTINUE)
1514 return rc;
1515
1516 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1517 &ctxt->exception);
dde7e6d1 1518}
ef65c889 1519
dde7e6d1
AK		 1520/* allowed just for 8 bytes segments */
1521static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1522 u16 selector, struct desc_struct *desc)
1523{
edccda7c 1524 int rc;
dde7e6d1 1525 ulong addr;
6aa8b732 1526
edccda7c
NA		 1527 rc = get_descriptor_ptr(ctxt, selector, &addr);
1528 if (rc != X86EMUL_CONTINUE)
1529 return rc;
6aa8b732 1530
7b105ca2
TY		 1531 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1532 &ctxt->exception);
dde7e6d1 1533}
c7e75a3d 1534
5601d05b 1535/* Does not support long mode */
2356aaeb 1536static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1537 u16 selector, int seg, u8 cpl,
3dc4bc4f 1538 enum x86_transfer_type transfer,
d1442d85 1539 struct desc_struct *desc)
dde7e6d1 1540{
869be99c 1541 struct desc_struct seg_desc, old_desc;
2356aaeb 1542 u8 dpl, rpl;
dde7e6d1
AK		 1543 unsigned err_vec = GP_VECTOR;
1544 u32 err_code = 0;
1545 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1546 ulong desc_addr;
dde7e6d1 1547 int ret;
03ebebeb 1548 u16 dummy;
e37a75a1 1549 u32 base3 = 0;
69f55cb1 1550
dde7e6d1 1551 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1552
f8da94e9
KW		 1553 if (ctxt->mode == X86EMUL_MODE_REAL) {
1554 /* set real mode segment descriptor (keep limit etc. for
1555 * unreal mode) */
03ebebeb 1556 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1557 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1558 goto load;
f8da94e9
KW		 1559 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1560 /* VM86 needs a clean new segment descriptor */
1561 set_desc_base(&seg_desc, selector << 4);
1562 set_desc_limit(&seg_desc, 0xffff);
1563 seg_desc.type = 3;
1564 seg_desc.p = 1;
1565 seg_desc.s = 1;
1566 seg_desc.dpl = 3;
1567 goto load;
dde7e6d1
AK		 1568 }
1569
79d5b4c3 1570 rpl = selector & 3;
79d5b4c3
AK		 1571
1572 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1573 if ((seg == VCPU_SREG_CS
1574 || (seg == VCPU_SREG_SS
1575 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1576 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1577 && null_selector)
1578 goto exception;
1579
1580 /* TR should be in GDT only */
1581 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1582 goto exception;
1583
1584 if (null_selector) /* for NULL selector skip all following checks */
1585 goto load;
1586
e919464b 1587 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1588 if (ret != X86EMUL_CONTINUE)
1589 return ret;
1590
1591 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1592 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1593 GP_VECTOR;
dde7e6d1 1594
fc058680 1595 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1596 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1597 if (transfer == X86_TRANSFER_CALL_JMP)
1598 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1599 goto exception;
3dc4bc4f 1600 }
dde7e6d1
AK		 1601
1602 if (!seg_desc.p) {
1603 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1604 goto exception;
1605 }
1606
dde7e6d1 1607 dpl = seg_desc.dpl;
dde7e6d1
AK		 1608
1609 switch (seg) {
1610 case VCPU_SREG_SS:
1611 /*
1612 * segment is not a writable data segment or segment
1613 * selector's RPL != CPL or segment selector's RPL != CPL
1614 */
1615 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1616 goto exception;
6aa8b732 1617 break;
dde7e6d1
AK		 1618 case VCPU_SREG_CS:
1619 if (!(seg_desc.type & 8))
1620 goto exception;
1621
1622 if (seg_desc.type & 4) {
1623 /* conforming */
1624 if (dpl > cpl)
1625 goto exception;
1626 } else {
1627 /* nonconforming */
1628 if (rpl > cpl || dpl != cpl)
1629 goto exception;
1630 }
040c8dc8
NA		 1631 /* in long-mode d/b must be clear if l is set */
1632 if (seg_desc.d && seg_desc.l) {
1633 u64 efer = 0;
1634
1635 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1636 if (efer & EFER_LMA)
1637 goto exception;
1638 }
1639
dde7e6d1
AK		 1640 /* CS(RPL) <- CPL */
1641 selector = (selector & 0xfffc) | cpl;
6aa8b732 1642 break;
dde7e6d1
AK		 1643 case VCPU_SREG_TR:
1644 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1645 goto exception;
869be99c
AK		 1646 old_desc = seg_desc;
1647 seg_desc.type |= 2; /* busy */
1648 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1649 sizeof(seg_desc), &ctxt->exception);
1650 if (ret != X86EMUL_CONTINUE)
1651 return ret;
dde7e6d1
AK		 1652 break;
1653 case VCPU_SREG_LDTR:
1654 if (seg_desc.s || seg_desc.type != 2)
1655 goto exception;
1656 break;
1657 default: /* DS, ES, FS, or GS */
4e62417b 1658 /*
dde7e6d1
AK		 1659 * segment is not a data or readable code segment or
1660 * ((segment is a data or nonconforming code segment)
1661 * and (both RPL and CPL > DPL))
4e62417b 1662 */
dde7e6d1
AK		 1663 if ((seg_desc.type & 0xa) == 0x8 ||
1664 (((seg_desc.type & 0xc) != 0xc) &&
1665 (rpl > dpl && cpl > dpl)))
1666 goto exception;
6aa8b732 1667 break;
dde7e6d1
AK		 1668 }
1669
1670 if (seg_desc.s) {
1671 /* mark segment as accessed */
e2cefa74
NA		 1672 if (!(seg_desc.type & 1)) {
1673 seg_desc.type |= 1;
1674 ret = write_segment_descriptor(ctxt, selector,
1675 &seg_desc);
1676 if (ret != X86EMUL_CONTINUE)
1677 return ret;
1678 }
e37a75a1
NA		 1679 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1680 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1681 sizeof(base3), &ctxt->exception);
1682 if (ret != X86EMUL_CONTINUE)
1683 return ret;
9a9abf6b
NA		 1684 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1685 ((u64)base3 << 32)))
1686 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1687 }
1688load:
e37a75a1 1689 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1690 if (desc)
1691 *desc = seg_desc;
dde7e6d1
AK		 1692 return X86EMUL_CONTINUE;
1693exception:
592f0858 1694 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1695}
1696
2356aaeb
PB		 1697static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1698 u16 selector, int seg)
1699{
1700 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1701 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1702 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1703}
1704
31be40b3
WY		 1705static void write_register_operand(struct operand *op)
1706{
6fd8e127 1707 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1708}
1709
fb32b1ed 1710static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1711{
fb32b1ed 1712 switch (op->type) {
dde7e6d1 1713 case OP_REG:
fb32b1ed 1714 write_register_operand(op);
6aa8b732 1715 break;
dde7e6d1 1716 case OP_MEM:
9dac77fa 1717 if (ctxt->lock_prefix)
f5f87dfb
PB		 1718 return segmented_cmpxchg(ctxt,
1719 op->addr.mem,
1720 &op->orig_val,
1721 &op->val,
1722 op->bytes);
1723 else
1724 return segmented_write(ctxt,
fb32b1ed 1725 op->addr.mem,
fb32b1ed
AK		 1726 &op->val,
1727 op->bytes);
a682e354 1728 break;
b3356bf0 1729 case OP_MEM_STR:
f5f87dfb
PB		 1730 return segmented_write(ctxt,
1731 op->addr.mem,
1732 op->data,
1733 op->bytes * op->count);
b3356bf0 1734 break;
1253791d 1735 case OP_XMM:
fb32b1ed 1736 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1737 break;
cbe2c9d3 1738 case OP_MM:
fb32b1ed 1739 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1740 break;
dde7e6d1
AK		 1741 case OP_NONE:
1742 /* no writeback */
414e6277 1743 break;
dde7e6d1 1744 default:
414e6277 1745 break;
6aa8b732 1746 }
dde7e6d1
AK		 1747 return X86EMUL_CONTINUE;
1748}
6aa8b732 1749
51ddff50 1750static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1751{
4179bb02 1752 struct segmented_address addr;
0dc8d10f 1753
5ad105e5 1754 rsp_increment(ctxt, -bytes);
dd856efa 1755 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1756 addr.seg = VCPU_SREG_SS;
1757
51ddff50
AK		 1758 return segmented_write(ctxt, addr, data, bytes);
1759}
1760
1761static int em_push(struct x86_emulate_ctxt *ctxt)
1762{
4179bb02 1763 /* Disable writeback. */
9dac77fa 1764 ctxt->dst.type = OP_NONE;
51ddff50 1765 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1766}
69f55cb1 1767
dde7e6d1 1768static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1769 void *dest, int len)
1770{
dde7e6d1 1771 int rc;
90de84f5 1772 struct segmented_address addr;
8b4caf66 1773
dd856efa 1774 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1775 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1776 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1777 if (rc != X86EMUL_CONTINUE)
1778 return rc;
1779
5ad105e5 1780 rsp_increment(ctxt, len);
dde7e6d1 1781 return rc;
8b4caf66
LV		 1782}
1783
c54fe504
TY		 1784static int em_pop(struct x86_emulate_ctxt *ctxt)
1785{
9dac77fa 1786 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1787}
1788
dde7e6d1 1789static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1790 void *dest, int len)
9de41573
GN		 1791{
1792 int rc;
dde7e6d1 1793 unsigned long val, change_mask;
0efb0440 1794 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1795 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1796
3b9be3bf 1797 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1798 if (rc != X86EMUL_CONTINUE)
1799 return rc;
9de41573 1800
0efb0440
NA		 1801 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1802 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1803 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1804 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1805
dde7e6d1
AK		 1806 switch(ctxt->mode) {
1807 case X86EMUL_MODE_PROT64:
1808 case X86EMUL_MODE_PROT32:
1809 case X86EMUL_MODE_PROT16:
1810 if (cpl == 0)
0efb0440 1811 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1812 if (cpl <= iopl)
0efb0440 1813 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1814 break;
1815 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1816 if (iopl < 3)
1817 return emulate_gp(ctxt, 0);
0efb0440 1818 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1819 break;
1820 default: /* real mode */
0efb0440 1821 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1822 break;
9de41573 1823 }
dde7e6d1
AK		 1824
1825 *(unsigned long *)dest =
1826 (ctxt->eflags & ~change_mask) | (val & change_mask);
1827
1828 return rc;
9de41573
GN		 1829}
1830
62aaa2f0
TY		 1831static int em_popf(struct x86_emulate_ctxt *ctxt)
1832{
9dac77fa
AK		 1833 ctxt->dst.type = OP_REG;
1834 ctxt->dst.addr.reg = &ctxt->eflags;
1835 ctxt->dst.bytes = ctxt->op_bytes;
1836 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1837}
1838
612e89f0
AK		 1839static int em_enter(struct x86_emulate_ctxt *ctxt)
1840{
1841 int rc;
1842 unsigned frame_size = ctxt->src.val;
1843 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1844 ulong rbp;
612e89f0
AK		 1845
1846 if (nesting_level)
1847 return X86EMUL_UNHANDLEABLE;
1848
dd856efa
AK		 1849 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1850 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1851 if (rc != X86EMUL_CONTINUE)
1852 return rc;
dd856efa 1853 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1854 stack_mask(ctxt));
dd856efa
AK		 1855 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1856 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1857 stack_mask(ctxt));
1858 return X86EMUL_CONTINUE;
1859}
1860
f47cfa31
AK		 1861static int em_leave(struct x86_emulate_ctxt *ctxt)
1862{
dd856efa 1863 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1864 stack_mask(ctxt));
dd856efa 1865 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1866}
1867
1cd196ea 1868static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1869{
1cd196ea
AK		 1870 int seg = ctxt->src2.val;
1871
9dac77fa 1872 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1873 if (ctxt->op_bytes == 4) {
1874 rsp_increment(ctxt, -2);
1875 ctxt->op_bytes = 2;
1876 }
7b262e90 1877
4487b3b4 1878 return em_push(ctxt);
7b262e90
GN		 1879}
1880
1cd196ea 1881static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1882{
1cd196ea 1883 int seg = ctxt->src2.val;
dde7e6d1
AK		 1884 unsigned long selector;
1885 int rc;
38ba30ba 1886
3313bc4e 1887 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1888 if (rc != X86EMUL_CONTINUE)
1889 return rc;
1890
a5457e7b
PB		 1891 if (ctxt->modrm_reg == VCPU_SREG_SS)
1892 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1893 if (ctxt->op_bytes > 2)
1894 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1895
7b105ca2 1896 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1897 return rc;
38ba30ba
GN		 1898}
1899
b96a7fad 1900static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1901{
dd856efa 1902 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1903 int rc = X86EMUL_CONTINUE;
1904 int reg = VCPU_REGS_RAX;
38ba30ba 1905
dde7e6d1
AK		 1906 while (reg <= VCPU_REGS_RDI) {
1907 (reg == VCPU_REGS_RSP) ?
dd856efa 1908 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1909
4487b3b4 1910 rc = em_push(ctxt);
dde7e6d1
AK		 1911 if (rc != X86EMUL_CONTINUE)
1912 return rc;
38ba30ba 1913
dde7e6d1 1914 ++reg;
38ba30ba 1915 }
38ba30ba 1916
dde7e6d1 1917 return rc;
38ba30ba
GN		 1918}
1919
62aaa2f0
TY		 1920static int em_pushf(struct x86_emulate_ctxt *ctxt)
1921{
0efb0440 1922 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 1923 return em_push(ctxt);
1924}
1925
b96a7fad 1926static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1927{
dde7e6d1
AK		 1928 int rc = X86EMUL_CONTINUE;
1929 int reg = VCPU_REGS_RDI;
6fd8e127 1930 u32 val;
38ba30ba 1931
dde7e6d1
AK		 1932 while (reg >= VCPU_REGS_RAX) {
1933 if (reg == VCPU_REGS_RSP) {
5ad105e5 1934 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1935 --reg;
1936 }
38ba30ba 1937
6fd8e127 1938 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 1939 if (rc != X86EMUL_CONTINUE)
1940 break;
6fd8e127 1941 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 1942 --reg;
38ba30ba 1943 }
dde7e6d1 1944 return rc;
38ba30ba
GN		 1945}
1946
dd856efa 1947static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1948{
0225fb50 1949 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1950 int rc;
6e154e56
MG		 1951 struct desc_ptr dt;
1952 gva_t cs_addr;
1953 gva_t eip_addr;
1954 u16 cs, eip;
6e154e56
MG		 1955
1956 /* TODO: Add limit checks */
9dac77fa 1957 ctxt->src.val = ctxt->eflags;
4487b3b4 1958 rc = em_push(ctxt);
5c56e1cf
AK		 1959 if (rc != X86EMUL_CONTINUE)
1960 return rc;
6e154e56 1961
0efb0440 1962 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 1963
9dac77fa 1964 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1965 rc = em_push(ctxt);
5c56e1cf
AK		 1966 if (rc != X86EMUL_CONTINUE)
1967 return rc;
6e154e56 1968
9dac77fa 1969 ctxt->src.val = ctxt->_eip;
4487b3b4 1970 rc = em_push(ctxt);
5c56e1cf
AK		 1971 if (rc != X86EMUL_CONTINUE)
1972 return rc;
1973
4bff1e86 1974 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1975
1976 eip_addr = dt.address + (irq << 2);
1977 cs_addr = dt.address + (irq << 2) + 2;
1978
0f65dd70 1979 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1980 if (rc != X86EMUL_CONTINUE)
1981 return rc;
1982
0f65dd70 1983 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
1986
7b105ca2 1987 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
1990
9dac77fa 1991 ctxt->_eip = eip;
6e154e56
MG		 1992
1993 return rc;
1994}
1995
dd856efa
AK		 1996int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1997{
1998 int rc;
1999
2000 invalidate_registers(ctxt);
2001 rc = __emulate_int_real(ctxt, irq);
2002 if (rc == X86EMUL_CONTINUE)
2003 writeback_registers(ctxt);
2004 return rc;
2005}
2006
7b105ca2 2007static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2008{
2009 switch(ctxt->mode) {
2010 case X86EMUL_MODE_REAL:
dd856efa 2011 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2012 case X86EMUL_MODE_VM86:
2013 case X86EMUL_MODE_PROT16:
2014 case X86EMUL_MODE_PROT32:
2015 case X86EMUL_MODE_PROT64:
2016 default:
2017 /* Protected mode interrupts unimplemented yet */
2018 return X86EMUL_UNHANDLEABLE;
2019 }
2020}
2021
7b105ca2 2022static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2023{
dde7e6d1
AK		 2024 int rc = X86EMUL_CONTINUE;
2025 unsigned long temp_eip = 0;
2026 unsigned long temp_eflags = 0;
2027 unsigned long cs = 0;
0efb0440
NA		 2028 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2029 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2030 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2031 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2032 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2033 X86_EFLAGS_FIXED;
0efb0440
NA		 2034 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2035 X86_EFLAGS_VIP;
38ba30ba 2036
dde7e6d1 2037 /* TODO: Add stack limit check */
38ba30ba 2038
9dac77fa 2039 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2040
dde7e6d1
AK		 2041 if (rc != X86EMUL_CONTINUE)
2042 return rc;
38ba30ba 2043
35d3d4a1
AK		 2044 if (temp_eip & ~0xffff)
2045 return emulate_gp(ctxt, 0);
38ba30ba 2046
9dac77fa 2047 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2048
dde7e6d1
AK		 2049 if (rc != X86EMUL_CONTINUE)
2050 return rc;
38ba30ba 2051
9dac77fa 2052 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2053
dde7e6d1
AK		 2054 if (rc != X86EMUL_CONTINUE)
2055 return rc;
38ba30ba 2056
7b105ca2 2057 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2058
dde7e6d1
AK		 2059 if (rc != X86EMUL_CONTINUE)
2060 return rc;
38ba30ba 2061
9dac77fa 2062 ctxt->_eip = temp_eip;
38ba30ba 2063
9dac77fa 2064 if (ctxt->op_bytes == 4)
dde7e6d1 2065 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2066 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2067 ctxt->eflags &= ~0xffff;
2068 ctxt->eflags |= temp_eflags;
38ba30ba 2069 }
dde7e6d1
AK		 2070
2071 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2072 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2073 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2074
2075 return rc;
38ba30ba
GN		 2076}
2077
e01991e7 2078static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2079{
dde7e6d1
AK		 2080 switch(ctxt->mode) {
2081 case X86EMUL_MODE_REAL:
7b105ca2 2082 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2083 case X86EMUL_MODE_VM86:
2084 case X86EMUL_MODE_PROT16:
2085 case X86EMUL_MODE_PROT32:
2086 case X86EMUL_MODE_PROT64:
c37eda13 2087 default:
dde7e6d1
AK		 2088 /* iret from protected mode unimplemented yet */
2089 return X86EMUL_UNHANDLEABLE;
c37eda13 2090 }
c37eda13
WY		 2091}
2092
d2f62766
TY		 2093static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2094{
d2f62766 2095 int rc;
d1442d85
NA		 2096 unsigned short sel, old_sel;
2097 struct desc_struct old_desc, new_desc;
2098 const struct x86_emulate_ops *ops = ctxt->ops;
2099 u8 cpl = ctxt->ops->cpl(ctxt);
2100
2101 /* Assignment of RIP may only fail in 64-bit mode */
2102 if (ctxt->mode == X86EMUL_MODE_PROT64)
2103 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2104 VCPU_SREG_CS);
d2f62766 2105
9dac77fa 2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2107
3dc4bc4f
NA		 2108 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2109 X86_TRANSFER_CALL_JMP,
d1442d85 2110 &new_desc);
d2f62766
TY		 2111 if (rc != X86EMUL_CONTINUE)
2112 return rc;
2113
d50eaa18 2114 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2115 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2116 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2117 /* assigning eip failed; restore the old cs */
2118 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2119 return rc;
2120 }
2121 return rc;
d2f62766
TY		 2122}
2123
f7784046 2124static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2125{
f7784046
NA		 2126 return assign_eip_near(ctxt, ctxt->src.val);
2127}
8cdbd2c9 2128
f7784046
NA		 2129static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2130{
2131 int rc;
2132 long int old_eip;
2133
2134 old_eip = ctxt->_eip;
2135 rc = assign_eip_near(ctxt, ctxt->src.val);
2136 if (rc != X86EMUL_CONTINUE)
2137 return rc;
2138 ctxt->src.val = old_eip;
2139 rc = em_push(ctxt);
4179bb02 2140 return rc;
8cdbd2c9
LV		 2141}
2142
e0dac408 2143static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2144{
9dac77fa 2145 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2146
aaa05f24
NA		 2147 if (ctxt->dst.bytes == 16)
2148 return X86EMUL_UNHANDLEABLE;
2149
dd856efa
AK		 2150 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2151 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2152 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2153 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2154 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2155 } else {
dd856efa
AK		 2156 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2157 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2158
0efb0440 2159 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2160 }
1b30eaa8 2161 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2162}
2163
ebda02c2
TY		 2164static int em_ret(struct x86_emulate_ctxt *ctxt)
2165{
234f3ce4
NA		 2166 int rc;
2167 unsigned long eip;
2168
2169 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2170 if (rc != X86EMUL_CONTINUE)
2171 return rc;
2172
2173 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2174}
2175
e01991e7 2176static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2177{
a77ab5ea 2178 int rc;
d1442d85
NA		 2179 unsigned long eip, cs;
2180 u16 old_cs;
9e8919ae 2181 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2182 struct desc_struct old_desc, new_desc;
2183 const struct x86_emulate_ops *ops = ctxt->ops;
2184
2185 if (ctxt->mode == X86EMUL_MODE_PROT64)
2186 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2187 VCPU_SREG_CS);
a77ab5ea 2188
d1442d85 2189 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2190 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2191 return rc;
9dac77fa 2192 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2193 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2194 return rc;
9e8919ae
NA		 2195 /* Outer-privilege level return is not implemented */
2196 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2197 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2198 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2199 X86_TRANSFER_RET,
d1442d85
NA		 2200 &new_desc);
2201 if (rc != X86EMUL_CONTINUE)
2202 return rc;
d50eaa18 2203 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2204 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2205 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2206 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2207 }
a77ab5ea
AK		 2208 return rc;
2209}
2210
3261107e
BR		 2211static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2212{
2213 int rc;
2214
2215 rc = em_ret_far(ctxt);
2216 if (rc != X86EMUL_CONTINUE)
2217 return rc;
2218 rsp_increment(ctxt, ctxt->src.val);
2219 return X86EMUL_CONTINUE;
2220}
2221
e940b5c2
TY		 2222static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2223{
2224 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2225 ctxt->dst.orig_val = ctxt->dst.val;
2226 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2227 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2228 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2229 fastop(ctxt, em_cmp);
e940b5c2 2230
0efb0440 2231 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2232 /* Success: write back to memory; no update of EAX */
2233 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2234 ctxt->dst.val = ctxt->src.orig_val;
2235 } else {
2236 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2237 ctxt->src.type = OP_REG;
2238 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2239 ctxt->src.val = ctxt->dst.orig_val;
2240 /* Create write-cycle to dest by writing the same value */
37c564f2 2241 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2242 }
2243 return X86EMUL_CONTINUE;
2244}
2245
d4b4325f 2246static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2247{
d4b4325f 2248 int seg = ctxt->src2.val;
09b5f4d3
WY		 2249 unsigned short sel;
2250 int rc;
2251
9dac77fa 2252 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2253
7b105ca2 2254 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2255 if (rc != X86EMUL_CONTINUE)
2256 return rc;
2257
9dac77fa 2258 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2259 return rc;
2260}
2261
64d60670
PB		 2262static int em_rsm(struct x86_emulate_ctxt *ctxt)
2263{
2264 if ((ctxt->emul_flags & X86EMUL_SMM_MASK) == 0)
2265 return emulate_ud(ctxt);
2266
2267 return X86EMUL_UNHANDLEABLE;
2268}
2269
7b105ca2 2270static void
e66bb2cc 2271setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2272 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2273{
e66bb2cc 2274 cs->l = 0; /* will be adjusted later */
79168fd1 2275 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2276 cs->g = 1; /* 4kb granularity */
79168fd1 2277 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2278 cs->type = 0x0b; /* Read, Execute, Accessed */
2279 cs->s = 1;
2280 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2281 cs->p = 1;
2282 cs->d = 1;
99245b50 2283 cs->avl = 0;
e66bb2cc 2284
79168fd1
GN		 2285 set_desc_base(ss, 0); /* flat segment */
2286 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2287 ss->g = 1; /* 4kb granularity */
2288 ss->s = 1;
2289 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2290 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2291 ss->dpl = 0;
79168fd1 2292 ss->p = 1;
99245b50
GN		 2293 ss->l = 0;
2294 ss->avl = 0;
e66bb2cc
AP		 2295}
2296
1a18a69b
AK		 2297static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2298{
2299 u32 eax, ebx, ecx, edx;
2300
2301 eax = ecx = 0;
0017f93a
AK		 2302 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2303 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2304 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2305 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2306}
2307
c2226fc9
SB		 2308static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2309{
0225fb50 2310 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2311 u32 eax, ebx, ecx, edx;
2312
2313 /*
2314 * syscall should always be enabled in longmode - so only become
2315 * vendor specific (cpuid) if other modes are active...
2316 */
2317 if (ctxt->mode == X86EMUL_MODE_PROT64)
2318 return true;
2319
2320 eax = 0x00000000;
2321 ecx = 0x00000000;
0017f93a
AK		 2322 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2323 /*
2324 * Intel ("GenuineIntel")
2325 * remark: Intel CPUs only support "syscall" in 64bit
2326 * longmode. Also an 64bit guest with a
2327 * 32bit compat-app running will #UD !! While this
2328 * behaviour can be fixed (by emulating) into AMD
2329 * response - CPUs of AMD can't behave like Intel.
2330 */
2331 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2332 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2333 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2334 return false;
2335
2336 /* AMD ("AuthenticAMD") */
2337 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2338 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2339 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2340 return true;
2341
2342 /* AMD ("AMDisbetter!") */
2343 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2344 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2345 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2346 return true;
c2226fc9
SB		 2347
2348 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2349 return false;
2350}
2351
e01991e7 2352static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2353{
0225fb50 2354 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2355 struct desc_struct cs, ss;
e66bb2cc 2356 u64 msr_data;
79168fd1 2357 u16 cs_sel, ss_sel;
c2ad2bb3 2358 u64 efer = 0;
e66bb2cc
AP		 2359
2360 /* syscall is not available in real mode */
2e901c4c 2361 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2362 ctxt->mode == X86EMUL_MODE_VM86)
2363 return emulate_ud(ctxt);
e66bb2cc 2364
c2226fc9
SB		 2365 if (!(em_syscall_is_enabled(ctxt)))
2366 return emulate_ud(ctxt);
2367
c2ad2bb3 2368 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2369 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2370
c2226fc9
SB		 2371 if (!(efer & EFER_SCE))
2372 return emulate_ud(ctxt);
2373
717746e3 2374 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2375 msr_data >>= 32;
79168fd1
GN		 2376 cs_sel = (u16)(msr_data & 0xfffc);
2377 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2378
c2ad2bb3 2379 if (efer & EFER_LMA) {
79168fd1 2380 cs.d = 0;
e66bb2cc
AP		 2381 cs.l = 1;
2382 }
1aa36616
AK		 2383 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2384 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2385
dd856efa 2386 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2387 if (efer & EFER_LMA) {
e66bb2cc 2388#ifdef CONFIG_X86_64
6c6cb69b 2389 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2390
717746e3 2391 ops->get_msr(ctxt,
3fb1b5db
GN		 2392 ctxt->mode == X86EMUL_MODE_PROT64 ?
2393 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2394 ctxt->_eip = msr_data;
e66bb2cc 2395
717746e3 2396 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2397 ctxt->eflags &= ~msr_data;
35fd68a3 2398 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2399#endif
2400 } else {
2401 /* legacy mode */
717746e3 2402 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2403 ctxt->_eip = (u32)msr_data;
e66bb2cc 2404
0efb0440 2405 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2406 }
2407
e54cfa97 2408 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2409}
2410
e01991e7 2411static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2412{
0225fb50 2413 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2414 struct desc_struct cs, ss;
8c604352 2415 u64 msr_data;
79168fd1 2416 u16 cs_sel, ss_sel;
c2ad2bb3 2417 u64 efer = 0;
8c604352 2418
7b105ca2 2419 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2420 /* inject #GP if in real mode */
35d3d4a1
AK		 2421 if (ctxt->mode == X86EMUL_MODE_REAL)
2422 return emulate_gp(ctxt, 0);
8c604352 2423
1a18a69b
AK		 2424 /*
2425 * Not recognized on AMD in compat mode (but is recognized in legacy
2426 * mode).
2427 */
f3747379 2428 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2429 && !vendor_intel(ctxt))
2430 return emulate_ud(ctxt);
2431
b2c9d43e 2432 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2433 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2434 return X86EMUL_UNHANDLEABLE;
8c604352 2435
7b105ca2 2436 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2437
717746e3 2438 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2439 if ((msr_data & 0xfffc) == 0x0)
2440 return emulate_gp(ctxt, 0);
8c604352 2441
0efb0440 2442 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2443 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2444 ss_sel = cs_sel + 8;
f3747379 2445 if (efer & EFER_LMA) {
79168fd1 2446 cs.d = 0;
8c604352
AP		 2447 cs.l = 1;
2448 }
2449
1aa36616
AK		 2450 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2451 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2452
717746e3 2453 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2454 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2455
717746e3 2456 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2457 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2458 (u32)msr_data;
8c604352 2459
e54cfa97 2460 return X86EMUL_CONTINUE;
8c604352
AP		 2461}
2462
e01991e7 2463static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2464{
0225fb50 2465 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2466 struct desc_struct cs, ss;
234f3ce4 2467 u64 msr_data, rcx, rdx;
4668f050 2468 int usermode;
1249b96e 2469 u16 cs_sel = 0, ss_sel = 0;
4668f050 2470
a0044755
GN		 2471 /* inject #GP if in real mode or Virtual 8086 mode */
2472 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2473 ctxt->mode == X86EMUL_MODE_VM86)
2474 return emulate_gp(ctxt, 0);
4668f050 2475
7b105ca2 2476 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2477
9dac77fa 2478 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2479 usermode = X86EMUL_MODE_PROT64;
2480 else
2481 usermode = X86EMUL_MODE_PROT32;
2482
234f3ce4
NA		 2483 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2484 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2485
4668f050
AP		 2486 cs.dpl = 3;
2487 ss.dpl = 3;
717746e3 2488 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2489 switch (usermode) {
2490 case X86EMUL_MODE_PROT32:
79168fd1 2491 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2492 if ((msr_data & 0xfffc) == 0x0)
2493 return emulate_gp(ctxt, 0);
79168fd1 2494 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2495 rcx = (u32)rcx;
2496 rdx = (u32)rdx;
4668f050
AP		 2497 break;
2498 case X86EMUL_MODE_PROT64:
79168fd1 2499 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2500 if (msr_data == 0x0)
2501 return emulate_gp(ctxt, 0);
79168fd1
GN		 2502 ss_sel = cs_sel + 8;
2503 cs.d = 0;
4668f050 2504 cs.l = 1;
234f3ce4
NA		 2505 if (is_noncanonical_address(rcx) ||
2506 is_noncanonical_address(rdx))
2507 return emulate_gp(ctxt, 0);
4668f050
AP		 2508 break;
2509 }
b32a9918
NA		 2510 cs_sel |= SEGMENT_RPL_MASK;
2511 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2512
1aa36616
AK		 2513 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2514 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2515
234f3ce4
NA		 2516 ctxt->_eip = rdx;
2517 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2518
e54cfa97 2519 return X86EMUL_CONTINUE;
4668f050
AP		 2520}
2521
7b105ca2 2522static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2523{
2524 int iopl;
2525 if (ctxt->mode == X86EMUL_MODE_REAL)
2526 return false;
2527 if (ctxt->mode == X86EMUL_MODE_VM86)
2528 return true;
0efb0440 2529 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2530 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2531}
2532
2533static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2534 u16 port, u16 len)
2535{
0225fb50 2536 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2537 struct desc_struct tr_seg;
5601d05b 2538 u32 base3;
f850e2e6 2539 int r;
1aa36616 2540 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2541 unsigned mask = (1 << len) - 1;
5601d05b 2542 unsigned long base;
f850e2e6 2543
1aa36616 2544 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2545 if (!tr_seg.p)
f850e2e6 2546 return false;
79168fd1 2547 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2548 return false;
5601d05b
GN		 2549 base = get_desc_base(&tr_seg);
2550#ifdef CONFIG_X86_64
2551 base |= ((u64)base3) << 32;
2552#endif
0f65dd70 2553 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2554 if (r != X86EMUL_CONTINUE)
2555 return false;
79168fd1 2556 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2557 return false;
0f65dd70 2558 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2559 if (r != X86EMUL_CONTINUE)
2560 return false;
2561 if ((perm >> bit_idx) & mask)
2562 return false;
2563 return true;
2564}
2565
2566static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2567 u16 port, u16 len)
2568{
4fc40f07
GN		 2569 if (ctxt->perm_ok)
2570 return true;
2571
7b105ca2
TY		 2572 if (emulator_bad_iopl(ctxt))
2573 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2574 return false;
4fc40f07
GN		 2575
2576 ctxt->perm_ok = true;
2577
f850e2e6
GN		 2578 return true;
2579}
2580
428e3d08
NA		 2581static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2582{
2583 /*
2584 * Intel CPUs mask the counter and pointers in quite strange
2585 * manner when ECX is zero due to REP-string optimizations.
2586 */
2587#ifdef CONFIG_X86_64
2588 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2589 return;
2590
2591 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2592
2593 switch (ctxt->b) {
2594 case 0xa4: /* movsb */
2595 case 0xa5: /* movsd/w */
2596 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2597 /* fall through */
2598 case 0xaa: /* stosb */
2599 case 0xab: /* stosd/w */
2600 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2601 }
2602#endif
2603}
2604
38ba30ba 2605static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2606 struct tss_segment_16 *tss)
2607{
9dac77fa 2608 tss->ip = ctxt->_eip;
38ba30ba 2609 tss->flag = ctxt->eflags;
dd856efa
AK		 2610 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2611 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2612 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2613 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2614 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2615 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2616 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2617 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2618
1aa36616
AK		 2619 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2620 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2621 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2622 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2623 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2624}
2625
2626static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2627 struct tss_segment_16 *tss)
2628{
38ba30ba 2629 int ret;
2356aaeb 2630 u8 cpl;
38ba30ba 2631
9dac77fa 2632 ctxt->_eip = tss->ip;
38ba30ba 2633 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2634 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2635 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2636 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2637 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2638 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2639 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2640 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2641 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2642
2643 /*
2644 * SDM says that segment selectors are loaded before segment
2645 * descriptors
2646 */
1aa36616
AK		 2647 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2648 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2649 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2650 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2651 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2652
2356aaeb
PB		 2653 cpl = tss->cs & 3;
2654
38ba30ba 2655 /*
fc058680 2656 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2657 * it is handled in a context of new task
2658 */
d1442d85 2659 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2660 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2661 if (ret != X86EMUL_CONTINUE)
2662 return ret;
d1442d85 2663 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2664 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2665 if (ret != X86EMUL_CONTINUE)
2666 return ret;
d1442d85 2667 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2668 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2669 if (ret != X86EMUL_CONTINUE)
2670 return ret;
d1442d85 2671 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2672 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2673 if (ret != X86EMUL_CONTINUE)
2674 return ret;
d1442d85 2675 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2676 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2677 if (ret != X86EMUL_CONTINUE)
2678 return ret;
2679
2680 return X86EMUL_CONTINUE;
2681}
2682
2683static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2684 u16 tss_selector, u16 old_tss_sel,
2685 ulong old_tss_base, struct desc_struct *new_desc)
2686{
0225fb50 2687 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2688 struct tss_segment_16 tss_seg;
2689 int ret;
bcc55cba 2690 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2691
0f65dd70 2692 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2693 &ctxt->exception);
db297e3d 2694 if (ret != X86EMUL_CONTINUE)
38ba30ba 2695 return ret;
38ba30ba 2696
7b105ca2 2697 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2698
0f65dd70 2699 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2700 &ctxt->exception);
db297e3d 2701 if (ret != X86EMUL_CONTINUE)
38ba30ba 2702 return ret;
38ba30ba 2703
0f65dd70 2704 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2705 &ctxt->exception);
db297e3d 2706 if (ret != X86EMUL_CONTINUE)
38ba30ba 2707 return ret;
38ba30ba
GN		 2708
2709 if (old_tss_sel != 0xffff) {
2710 tss_seg.prev_task_link = old_tss_sel;
2711
0f65dd70 2712 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2713 &tss_seg.prev_task_link,
2714 sizeof tss_seg.prev_task_link,
0f65dd70 2715 &ctxt->exception);
db297e3d 2716 if (ret != X86EMUL_CONTINUE)
38ba30ba 2717 return ret;
38ba30ba
GN		 2718 }
2719
7b105ca2 2720 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2721}
2722
2723static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2724 struct tss_segment_32 *tss)
2725{
5c7411e2 2726 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2727 tss->eip = ctxt->_eip;
38ba30ba 2728 tss->eflags = ctxt->eflags;
dd856efa
AK		 2729 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2730 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2731 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2732 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2733 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2734 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2735 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2736 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2737
1aa36616
AK		 2738 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2739 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2740 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2741 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2742 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2743 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2744}
2745
2746static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2747 struct tss_segment_32 *tss)
2748{
38ba30ba 2749 int ret;
2356aaeb 2750 u8 cpl;
38ba30ba 2751
7b105ca2 2752 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2753 return emulate_gp(ctxt, 0);
9dac77fa 2754 ctxt->_eip = tss->eip;
38ba30ba 2755 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2756
2757 /* General purpose registers */
dd856efa
AK		 2758 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2759 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2760 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2761 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2762 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2763 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2764 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2765 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2766
2767 /*
2768 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2769 * descriptors. This is important because CPL checks will
2770 * use CS.RPL.
38ba30ba 2771 */
1aa36616
AK		 2772 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2773 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2774 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2775 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2776 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2777 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2778 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2779
4cee4798
KW		 2780 /*
2781 * If we're switching between Protected Mode and VM86, we need to make
2782 * sure to update the mode before loading the segment descriptors so
2783 * that the selectors are interpreted correctly.
4cee4798 2784 */
2356aaeb 2785 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2786 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2787 cpl = 3;
2788 } else {
4cee4798 2789 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2790 cpl = tss->cs & 3;
2791 }
4cee4798 2792
38ba30ba
GN		 2793 /*
2794 * Now load segment descriptors. If fault happenes at this stage
2795 * it is handled in a context of new task
2796 */
d1442d85 2797 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2798 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2799 if (ret != X86EMUL_CONTINUE)
2800 return ret;
d1442d85 2801 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2802 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2803 if (ret != X86EMUL_CONTINUE)
2804 return ret;
d1442d85 2805 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2806 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2807 if (ret != X86EMUL_CONTINUE)
2808 return ret;
d1442d85 2809 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2810 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2811 if (ret != X86EMUL_CONTINUE)
2812 return ret;
d1442d85 2813 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2814 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2815 if (ret != X86EMUL_CONTINUE)
2816 return ret;
d1442d85 2817 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2818 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2819 if (ret != X86EMUL_CONTINUE)
2820 return ret;
d1442d85 2821 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2822 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 2823
2f729b10 2824 return ret;
38ba30ba
GN		 2825}
2826
2827static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2828 u16 tss_selector, u16 old_tss_sel,
2829 ulong old_tss_base, struct desc_struct *new_desc)
2830{
0225fb50 2831 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2832 struct tss_segment_32 tss_seg;
2833 int ret;
bcc55cba 2834 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2835 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2836 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2837
0f65dd70 2838 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2839 &ctxt->exception);
db297e3d 2840 if (ret != X86EMUL_CONTINUE)
38ba30ba 2841 return ret;
38ba30ba 2842
7b105ca2 2843 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2844
5c7411e2
NA		 2845 /* Only GP registers and segment selectors are saved */
2846 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2847 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2848 if (ret != X86EMUL_CONTINUE)
38ba30ba 2849 return ret;
38ba30ba 2850
0f65dd70 2851 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2852 &ctxt->exception);
db297e3d 2853 if (ret != X86EMUL_CONTINUE)
38ba30ba 2854 return ret;
38ba30ba
GN		 2855
2856 if (old_tss_sel != 0xffff) {
2857 tss_seg.prev_task_link = old_tss_sel;
2858
0f65dd70 2859 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2860 &tss_seg.prev_task_link,
2861 sizeof tss_seg.prev_task_link,
0f65dd70 2862 &ctxt->exception);
db297e3d 2863 if (ret != X86EMUL_CONTINUE)
38ba30ba 2864 return ret;
38ba30ba
GN		 2865 }
2866
7b105ca2 2867 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2868}
2869
2870static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2871 u16 tss_selector, int idt_index, int reason,
e269fb21 2872 bool has_error_code, u32 error_code)
38ba30ba 2873{
0225fb50 2874 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2875 struct desc_struct curr_tss_desc, next_tss_desc;
2876 int ret;
1aa36616 2877 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2878 ulong old_tss_base =
4bff1e86 2879 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2880 u32 desc_limit;
3db176d5 2881 ulong desc_addr, dr7;
38ba30ba
GN		 2882
2883 /* FIXME: old_tss_base == ~0 ? */
2884
e919464b 2885 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2886 if (ret != X86EMUL_CONTINUE)
2887 return ret;
e919464b 2888 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2889 if (ret != X86EMUL_CONTINUE)
2890 return ret;
2891
2892 /* FIXME: check that next_tss_desc is tss */
2893
7f3d35fd
KW		 2894 /*
2895 * Check privileges. The three cases are task switch caused by...
2896 *
2897 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2898 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2899 * 3. jmp/call to TSS/task-gate: No check is performed since the
2900 * hardware checks it before exiting.
7f3d35fd
KW		 2901 */
2902 if (reason == TASK_SWITCH_GATE) {
2903 if (idt_index != -1) {
2904 /* Software interrupts */
2905 struct desc_struct task_gate_desc;
2906 int dpl;
2907
2908 ret = read_interrupt_descriptor(ctxt, idt_index,
2909 &task_gate_desc);
2910 if (ret != X86EMUL_CONTINUE)
2911 return ret;
2912
2913 dpl = task_gate_desc.dpl;
2914 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2915 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2916 }
38ba30ba
GN		 2917 }
2918
ceffb459
GN		 2919 desc_limit = desc_limit_scaled(&next_tss_desc);
2920 if (!next_tss_desc.p ||
2921 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2922 desc_limit < 0x2b)) {
592f0858 2923 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2924 }
2925
2926 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2927 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2928 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2929 }
2930
2931 if (reason == TASK_SWITCH_IRET)
2932 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2933
2934 /* set back link to prev task only if NT bit is set in eflags
fc058680 2935 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2936 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2937 old_tss_sel = 0xffff;
2938
2939 if (next_tss_desc.type & 8)
7b105ca2 2940 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2941 old_tss_base, &next_tss_desc);
2942 else
7b105ca2 2943 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2944 old_tss_base, &next_tss_desc);
0760d448
JK		 2945 if (ret != X86EMUL_CONTINUE)
2946 return ret;
38ba30ba
GN		 2947
2948 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2949 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2950
2951 if (reason != TASK_SWITCH_IRET) {
2952 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2953 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2954 }
2955
717746e3 2956 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2957 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2958
e269fb21 2959 if (has_error_code) {
9dac77fa
AK		 2960 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2961 ctxt->lock_prefix = 0;
2962 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2963 ret = em_push(ctxt);
e269fb21
JK		 2964 }
2965
3db176d5
NA		 2966 ops->get_dr(ctxt, 7, &dr7);
2967 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
2968
38ba30ba
GN		 2969 return ret;
2970}
2971
2972int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2973 u16 tss_selector, int idt_index, int reason,
e269fb21 2974 bool has_error_code, u32 error_code)
38ba30ba 2975{
38ba30ba
GN		 2976 int rc;
2977
dd856efa 2978 invalidate_registers(ctxt);
9dac77fa
AK		 2979 ctxt->_eip = ctxt->eip;
2980 ctxt->dst.type = OP_NONE;
38ba30ba 2981
7f3d35fd 2982 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2983 has_error_code, error_code);
38ba30ba 2984
dd856efa 2985 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2986 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2987 writeback_registers(ctxt);
2988 }
38ba30ba 2989
a0c0ab2f 2990 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2991}
2992
f3bd64c6
GN		 2993static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2994 struct operand *op)
a682e354 2995{
0efb0440 2996 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 2997
01485a22
PB		 2998 register_address_increment(ctxt, reg, df * op->bytes);
2999 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3000}
3001
7af04fc0
AK		 3002static int em_das(struct x86_emulate_ctxt *ctxt)
3003{
7af04fc0
AK		 3004 u8 al, old_al;
3005 bool af, cf, old_cf;
3006
3007 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3008 al = ctxt->dst.val;
7af04fc0
AK		 3009
3010 old_al = al;
3011 old_cf = cf;
3012 cf = false;
3013 af = ctxt->eflags & X86_EFLAGS_AF;
3014 if ((al & 0x0f) > 9 || af) {
3015 al -= 6;
3016 cf = old_cf | (al >= 250);
3017 af = true;
3018 } else {
3019 af = false;
3020 }
3021 if (old_al > 0x99 || old_cf) {
3022 al -= 0x60;
3023 cf = true;
3024 }
3025
9dac77fa 3026 ctxt->dst.val = al;
7af04fc0 3027 /* Set PF, ZF, SF */
9dac77fa
AK		 3028 ctxt->src.type = OP_IMM;
3029 ctxt->src.val = 0;
3030 ctxt->src.bytes = 1;
158de57f 3031 fastop(ctxt, em_or);
7af04fc0
AK		 3032 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3033 if (cf)
3034 ctxt->eflags |= X86_EFLAGS_CF;
3035 if (af)
3036 ctxt->eflags |= X86_EFLAGS_AF;
3037 return X86EMUL_CONTINUE;
3038}
3039
a035d5c6
PB		 3040static int em_aam(struct x86_emulate_ctxt *ctxt)
3041{
3042 u8 al, ah;
3043
3044 if (ctxt->src.val == 0)
3045 return emulate_de(ctxt);
3046
3047 al = ctxt->dst.val & 0xff;
3048 ah = al / ctxt->src.val;
3049 al %= ctxt->src.val;
3050
3051 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3052
3053 /* Set PF, ZF, SF */
3054 ctxt->src.type = OP_IMM;
3055 ctxt->src.val = 0;
3056 ctxt->src.bytes = 1;
3057 fastop(ctxt, em_or);
3058
3059 return X86EMUL_CONTINUE;
3060}
3061
7f662273
GN		 3062static int em_aad(struct x86_emulate_ctxt *ctxt)
3063{
3064 u8 al = ctxt->dst.val & 0xff;
3065 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3066
3067 al = (al + (ah * ctxt->src.val)) & 0xff;
3068
3069 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3070
f583c29b
GN		 3071 /* Set PF, ZF, SF */
3072 ctxt->src.type = OP_IMM;
3073 ctxt->src.val = 0;
3074 ctxt->src.bytes = 1;
3075 fastop(ctxt, em_or);
7f662273
GN		 3076
3077 return X86EMUL_CONTINUE;
3078}
3079
d4ddafcd
TY		 3080static int em_call(struct x86_emulate_ctxt *ctxt)
3081{
234f3ce4 3082 int rc;
d4ddafcd
TY		 3083 long rel = ctxt->src.val;
3084
3085 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3086 rc = jmp_rel(ctxt, rel);
3087 if (rc != X86EMUL_CONTINUE)
3088 return rc;
d4ddafcd
TY		 3089 return em_push(ctxt);
3090}
3091
0ef753b8
AK		 3092static int em_call_far(struct x86_emulate_ctxt *ctxt)
3093{
0ef753b8
AK		 3094 u16 sel, old_cs;
3095 ulong old_eip;
3096 int rc;
d1442d85
NA		 3097 struct desc_struct old_desc, new_desc;
3098 const struct x86_emulate_ops *ops = ctxt->ops;
3099 int cpl = ctxt->ops->cpl(ctxt);
82268083 3100 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3101
9dac77fa 3102 old_eip = ctxt->_eip;
d1442d85 3103 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3104
9dac77fa 3105 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3106 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3107 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3108 if (rc != X86EMUL_CONTINUE)
80976dbb 3109 return rc;
0ef753b8 3110
d50eaa18 3111 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3112 if (rc != X86EMUL_CONTINUE)
3113 goto fail;
0ef753b8 3114
9dac77fa 3115 ctxt->src.val = old_cs;
4487b3b4 3116 rc = em_push(ctxt);
0ef753b8 3117 if (rc != X86EMUL_CONTINUE)
d1442d85 3118 goto fail;
0ef753b8 3119
9dac77fa 3120 ctxt->src.val = old_eip;
d1442d85
NA		 3121 rc = em_push(ctxt);
3122 /* If we failed, we tainted the memory, but the very least we should
3123 restore cs */
82268083
NA		 3124 if (rc != X86EMUL_CONTINUE) {
3125 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3126 goto fail;
82268083 3127 }
d1442d85
NA		 3128 return rc;
3129fail:
3130 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3131 ctxt->mode = prev_mode;
d1442d85
NA		 3132 return rc;
3133
0ef753b8
AK		 3134}
3135
40ece7c7
AK		 3136static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3137{
40ece7c7 3138 int rc;
234f3ce4 3139 unsigned long eip;
40ece7c7 3140
234f3ce4
NA		 3141 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3142 if (rc != X86EMUL_CONTINUE)
3143 return rc;
3144 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3145 if (rc != X86EMUL_CONTINUE)
3146 return rc;
5ad105e5 3147 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3148 return X86EMUL_CONTINUE;
3149}
3150
e4f973ae
TY		 3151static int em_xchg(struct x86_emulate_ctxt *ctxt)
3152{
e4f973ae 3153 /* Write back the register source. */
9dac77fa
AK		 3154 ctxt->src.val = ctxt->dst.val;
3155 write_register_operand(&ctxt->src);
e4f973ae
TY		 3156
3157 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3158 ctxt->dst.val = ctxt->src.orig_val;
3159 ctxt->lock_prefix = 1;
e4f973ae
TY		 3160 return X86EMUL_CONTINUE;
3161}
3162
5c82aa29
AK		 3163static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3164{
9dac77fa 3165 ctxt->dst.val = ctxt->src2.val;
4d758349 3166 return fastop(ctxt, em_imul);
5c82aa29
AK		 3167}
3168
61429142
AK		 3169static int em_cwd(struct x86_emulate_ctxt *ctxt)
3170{
9dac77fa
AK		 3171 ctxt->dst.type = OP_REG;
3172 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3173 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3174 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3175
3176 return X86EMUL_CONTINUE;
3177}
3178
48bb5d3c
AK		 3179static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3180{
48bb5d3c
AK		 3181 u64 tsc = 0;
3182
717746e3 3183 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3184 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3185 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3186 return X86EMUL_CONTINUE;
3187}
3188
222d21aa
AK		 3189static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3190{
3191 u64 pmc;
3192
dd856efa 3193 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3194 return emulate_gp(ctxt, 0);
dd856efa
AK		 3195 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3196 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3197 return X86EMUL_CONTINUE;
3198}
3199
b9eac5f4
AK		 3200static int em_mov(struct x86_emulate_ctxt *ctxt)
3201{
54cfdb3e 3202 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3203 return X86EMUL_CONTINUE;
3204}
3205
84cffe49
BP		 3206#define FFL(x) bit(X86_FEATURE_##x)
3207
3208static int em_movbe(struct x86_emulate_ctxt *ctxt)
3209{
3210 u32 ebx, ecx, edx, eax = 1;
3211 u16 tmp;
3212
3213 /*
3214 * Check MOVBE is set in the guest-visible CPUID leaf.
3215 */
3216 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3217 if (!(ecx & FFL(MOVBE)))
3218 return emulate_ud(ctxt);
3219
3220 switch (ctxt->op_bytes) {
3221 case 2:
3222 /*
3223 * From MOVBE definition: "...When the operand size is 16 bits,
3224 * the upper word of the destination register remains unchanged
3225 * ..."
3226 *
3227 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3228 * rules so we have to do the operation almost per hand.
3229 */
3230 tmp = (u16)ctxt->src.val;
3231 ctxt->dst.val &= ~0xffffUL;
3232 ctxt->dst.val |= (unsigned long)swab16(tmp);
3233 break;
3234 case 4:
3235 ctxt->dst.val = swab32((u32)ctxt->src.val);
3236 break;
3237 case 8:
3238 ctxt->dst.val = swab64(ctxt->src.val);
3239 break;
3240 default:
592f0858 3241 BUG();
84cffe49
BP		 3242 }
3243 return X86EMUL_CONTINUE;
3244}
3245
bc00f8d2
TY		 3246static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3247{
3248 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3249 return emulate_gp(ctxt, 0);
3250
3251 /* Disable writeback. */
3252 ctxt->dst.type = OP_NONE;
3253 return X86EMUL_CONTINUE;
3254}
3255
3256static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3257{
3258 unsigned long val;
3259
3260 if (ctxt->mode == X86EMUL_MODE_PROT64)
3261 val = ctxt->src.val & ~0ULL;
3262 else
3263 val = ctxt->src.val & ~0U;
3264
3265 /* #UD condition is already handled. */
3266 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3267 return emulate_gp(ctxt, 0);
3268
3269 /* Disable writeback. */
3270 ctxt->dst.type = OP_NONE;
3271 return X86EMUL_CONTINUE;
3272}
3273
e1e210b0
TY		 3274static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3275{
3276 u64 msr_data;
3277
dd856efa
AK		 3278 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3279 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3280 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3281 return emulate_gp(ctxt, 0);
3282
3283 return X86EMUL_CONTINUE;
3284}
3285
3286static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3287{
3288 u64 msr_data;
3289
dd856efa 3290 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3291 return emulate_gp(ctxt, 0);
3292
dd856efa
AK		 3293 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3294 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3295 return X86EMUL_CONTINUE;
3296}
3297
1bd5f469
TY		 3298static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3299{
9dac77fa 3300 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3301 return emulate_ud(ctxt);
3302
9dac77fa 3303 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3304 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3305 ctxt->dst.bytes = 2;
1bd5f469
TY		 3306 return X86EMUL_CONTINUE;
3307}
3308
3309static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3310{
9dac77fa 3311 u16 sel = ctxt->src.val;
1bd5f469 3312
9dac77fa 3313 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3314 return emulate_ud(ctxt);
3315
9dac77fa 3316 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3317 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3318
3319 /* Disable writeback. */
9dac77fa
AK		 3320 ctxt->dst.type = OP_NONE;
3321 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3322}
3323
a14e579f
AK		 3324static int em_lldt(struct x86_emulate_ctxt *ctxt)
3325{
3326 u16 sel = ctxt->src.val;
3327
3328 /* Disable writeback. */
3329 ctxt->dst.type = OP_NONE;
3330 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3331}
3332
80890006
AK		 3333static int em_ltr(struct x86_emulate_ctxt *ctxt)
3334{
3335 u16 sel = ctxt->src.val;
3336
3337 /* Disable writeback. */
3338 ctxt->dst.type = OP_NONE;
3339 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3340}
3341
38503911
AK		 3342static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3343{
9fa088f4
AK		 3344 int rc;
3345 ulong linear;
3346
9dac77fa 3347 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3348 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3349 ctxt->ops->invlpg(ctxt, linear);
38503911 3350 /* Disable writeback. */
9dac77fa 3351 ctxt->dst.type = OP_NONE;
38503911
AK		 3352 return X86EMUL_CONTINUE;
3353}
3354
2d04a05b
AK		 3355static int em_clts(struct x86_emulate_ctxt *ctxt)
3356{
3357 ulong cr0;
3358
3359 cr0 = ctxt->ops->get_cr(ctxt, 0);
3360 cr0 &= ~X86_CR0_TS;
3361 ctxt->ops->set_cr(ctxt, 0, cr0);
3362 return X86EMUL_CONTINUE;
3363}
3364
b34a8051 3365static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3366{
0f54a321 3367 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3368
26d05cc7
AK		 3369 if (rc != X86EMUL_CONTINUE)
3370 return rc;
3371
3372 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3373 ctxt->_eip = ctxt->eip;
26d05cc7 3374 /* Disable writeback. */
9dac77fa 3375 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3376 return X86EMUL_CONTINUE;
3377}
3378
96051572
AK		 3379static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3380 void (*get)(struct x86_emulate_ctxt *ctxt,
3381 struct desc_ptr *ptr))
3382{
3383 struct desc_ptr desc_ptr;
3384
3385 if (ctxt->mode == X86EMUL_MODE_PROT64)
3386 ctxt->op_bytes = 8;
3387 get(ctxt, &desc_ptr);
3388 if (ctxt->op_bytes == 2) {
3389 ctxt->op_bytes = 4;
3390 desc_ptr.address &= 0x00ffffff;
3391 }
3392 /* Disable writeback. */
3393 ctxt->dst.type = OP_NONE;
3394 return segmented_write(ctxt, ctxt->dst.addr.mem,
3395 &desc_ptr, 2 + ctxt->op_bytes);
3396}
3397
3398static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3399{
3400 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3401}
3402
3403static int em_sidt(struct x86_emulate_ctxt *ctxt)
3404{
3405 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3406}
3407
5b7f6a1e 3408static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3409{
26d05cc7
AK		 3410 struct desc_ptr desc_ptr;
3411 int rc;
3412
510425ff
AK		 3413 if (ctxt->mode == X86EMUL_MODE_PROT64)
3414 ctxt->op_bytes = 8;
9dac77fa 3415 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3416 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3417 ctxt->op_bytes);
26d05cc7
AK		 3418 if (rc != X86EMUL_CONTINUE)
3419 return rc;
9a9abf6b
NA		 3420 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3421 is_noncanonical_address(desc_ptr.address))
3422 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3423 if (lgdt)
3424 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3425 else
3426 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3427 /* Disable writeback. */
9dac77fa 3428 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3429 return X86EMUL_CONTINUE;
3430}
3431
5b7f6a1e
NA		 3432static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3433{
3434 return em_lgdt_lidt(ctxt, true);
3435}
3436
26d05cc7
AK		 3437static int em_lidt(struct x86_emulate_ctxt *ctxt)
3438{
5b7f6a1e 3439 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3440}
3441
3442static int em_smsw(struct x86_emulate_ctxt *ctxt)
3443{
32e94d06
NA		 3444 if (ctxt->dst.type == OP_MEM)
3445 ctxt->dst.bytes = 2;
9dac77fa 3446 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3447 return X86EMUL_CONTINUE;
3448}
3449
3450static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3451{
26d05cc7 3452 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3453 | (ctxt->src.val & 0x0f));
3454 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3455 return X86EMUL_CONTINUE;
3456}
3457
d06e03ad
TY		 3458static int em_loop(struct x86_emulate_ctxt *ctxt)
3459{
234f3ce4
NA		 3460 int rc = X86EMUL_CONTINUE;
3461
01485a22 3462 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3463 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3464 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3465 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3466
234f3ce4 3467 return rc;
d06e03ad
TY		 3468}
3469
3470static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3471{
234f3ce4
NA		 3472 int rc = X86EMUL_CONTINUE;
3473
dd856efa 3474 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3475 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3476
234f3ce4 3477 return rc;
d06e03ad
TY		 3478}
3479
d7841a4b
TY		 3480static int em_in(struct x86_emulate_ctxt *ctxt)
3481{
3482 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3483 &ctxt->dst.val))
3484 return X86EMUL_IO_NEEDED;
3485
3486 return X86EMUL_CONTINUE;
3487}
3488
3489static int em_out(struct x86_emulate_ctxt *ctxt)
3490{
3491 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3492 &ctxt->src.val, 1);
3493 /* Disable writeback. */
3494 ctxt->dst.type = OP_NONE;
3495 return X86EMUL_CONTINUE;
3496}
3497
f411e6cd
TY		 3498static int em_cli(struct x86_emulate_ctxt *ctxt)
3499{
3500 if (emulator_bad_iopl(ctxt))
3501 return emulate_gp(ctxt, 0);
3502
3503 ctxt->eflags &= ~X86_EFLAGS_IF;
3504 return X86EMUL_CONTINUE;
3505}
3506
3507static int em_sti(struct x86_emulate_ctxt *ctxt)
3508{
3509 if (emulator_bad_iopl(ctxt))
3510 return emulate_gp(ctxt, 0);
3511
3512 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3513 ctxt->eflags |= X86_EFLAGS_IF;
3514 return X86EMUL_CONTINUE;
3515}
3516
6d6eede4
AK		 3517static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3518{
3519 u32 eax, ebx, ecx, edx;
3520
dd856efa
AK		 3521 eax = reg_read(ctxt, VCPU_REGS_RAX);
3522 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3523 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3524 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3525 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3526 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3527 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3528 return X86EMUL_CONTINUE;
3529}
3530
98f73630
PB		 3531static int em_sahf(struct x86_emulate_ctxt *ctxt)
3532{
3533 u32 flags;
3534
0efb0440
NA		 3535 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3536 X86_EFLAGS_SF;
98f73630
PB		 3537 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3538
3539 ctxt->eflags &= ~0xffUL;
3540 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3541 return X86EMUL_CONTINUE;
3542}
3543
2dd7caa0
AK		 3544static int em_lahf(struct x86_emulate_ctxt *ctxt)
3545{
dd856efa
AK		 3546 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3547 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3548 return X86EMUL_CONTINUE;
3549}
3550
9299836e
AK		 3551static int em_bswap(struct x86_emulate_ctxt *ctxt)
3552{
3553 switch (ctxt->op_bytes) {
3554#ifdef CONFIG_X86_64
3555 case 8:
3556 asm("bswap %0" : "+r"(ctxt->dst.val));
3557 break;
3558#endif
3559 default:
3560 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3561 break;
3562 }
3563 return X86EMUL_CONTINUE;
3564}
3565
13e457e0
NA		 3566static int em_clflush(struct x86_emulate_ctxt *ctxt)
3567{
3568 /* emulating clflush regardless of cpuid */
3569 return X86EMUL_CONTINUE;
3570}
3571
2276b511
NA		 3572static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3573{
3574 ctxt->dst.val = (s32) ctxt->src.val;
3575 return X86EMUL_CONTINUE;
3576}
3577
cfec82cb
JR		 3578static bool valid_cr(int nr)
3579{
3580 switch (nr) {
3581 case 0:
3582 case 2 ... 4:
3583 case 8:
3584 return true;
3585 default:
3586 return false;
3587 }
3588}
3589
3590static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3591{
9dac77fa 3592 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3593 return emulate_ud(ctxt);
3594
3595 return X86EMUL_CONTINUE;
3596}
3597
3598static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3599{
9dac77fa
AK		 3600 u64 new_val = ctxt->src.val64;
3601 int cr = ctxt->modrm_reg;
c2ad2bb3 3602 u64 efer = 0;
cfec82cb
JR		 3603
3604 static u64 cr_reserved_bits[] = {
3605 0xffffffff00000000ULL,
3606 0, 0, 0, /* CR3 checked later */
3607 CR4_RESERVED_BITS,
3608 0, 0, 0,
3609 CR8_RESERVED_BITS,
3610 };
3611
3612 if (!valid_cr(cr))
3613 return emulate_ud(ctxt);
3614
3615 if (new_val & cr_reserved_bits[cr])
3616 return emulate_gp(ctxt, 0);
3617
3618 switch (cr) {
3619 case 0: {
c2ad2bb3 3620 u64 cr4;
cfec82cb
JR		 3621 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3622 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3623 return emulate_gp(ctxt, 0);
3624
717746e3
AK		 3625 cr4 = ctxt->ops->get_cr(ctxt, 4);
3626 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3627
3628 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3629 !(cr4 & X86_CR4_PAE))
3630 return emulate_gp(ctxt, 0);
3631
3632 break;
3633 }
3634 case 3: {
3635 u64 rsvd = 0;
3636
c2ad2bb3
AK		 3637 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3638 if (efer & EFER_LMA)
9d88fca7 3639 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3640
3641 if (new_val & rsvd)
3642 return emulate_gp(ctxt, 0);
3643
3644 break;
3645 }
3646 case 4: {
717746e3 3647 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3648
3649 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3650 return emulate_gp(ctxt, 0);
3651
3652 break;
3653 }
3654 }
3655
3656 return X86EMUL_CONTINUE;
3657}
3658
3b88e41a
JR		 3659static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3660{
3661 unsigned long dr7;
3662
717746e3 3663 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3664
3665 /* Check if DR7.Global_Enable is set */
3666 return dr7 & (1 << 13);
3667}
3668
3669static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3670{
9dac77fa 3671 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3672 u64 cr4;
3673
3674 if (dr > 7)
3675 return emulate_ud(ctxt);
3676
717746e3 3677 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3678 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3679 return emulate_ud(ctxt);
3680
6d2a0526
NA		 3681 if (check_dr7_gd(ctxt)) {
3682 ulong dr6;
3683
3684 ctxt->ops->get_dr(ctxt, 6, &dr6);
3685 dr6 &= ~15;
3686 dr6 |= DR6_BD | DR6_RTM;
3687 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3688 return emulate_db(ctxt);
6d2a0526 3689 }
3b88e41a
JR		 3690
3691 return X86EMUL_CONTINUE;
3692}
3693
3694static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3695{
9dac77fa
AK		 3696 u64 new_val = ctxt->src.val64;
3697 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3698
3699 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3700 return emulate_gp(ctxt, 0);
3701
3702 return check_dr_read(ctxt);
3703}
3704
01de8b09
JR		 3705static int check_svme(struct x86_emulate_ctxt *ctxt)
3706{
3707 u64 efer;
3708
717746e3 3709 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3710
3711 if (!(efer & EFER_SVME))
3712 return emulate_ud(ctxt);
3713
3714 return X86EMUL_CONTINUE;
3715}
3716
3717static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3718{
dd856efa 3719 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3720
3721 /* Valid physical address? */
d4224449 3722 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3723 return emulate_gp(ctxt, 0);
3724
3725 return check_svme(ctxt);
3726}
3727
d7eb8203
JR		 3728static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3729{
717746e3 3730 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3731
717746e3 3732 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3733 return emulate_ud(ctxt);
3734
3735 return X86EMUL_CONTINUE;
3736}
3737
8061252e
JR		 3738static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3739{
717746e3 3740 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3741 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3742
717746e3 3743 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3744 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3745 return emulate_gp(ctxt, 0);
3746
3747 return X86EMUL_CONTINUE;
3748}
3749
f6511935
JR		 3750static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3751{
9dac77fa
AK		 3752 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3753 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3754 return emulate_gp(ctxt, 0);
3755
3756 return X86EMUL_CONTINUE;
3757}
3758
3759static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3760{
9dac77fa
AK		 3761 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3762 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3763 return emulate_gp(ctxt, 0);
3764
3765 return X86EMUL_CONTINUE;
3766}
3767
73fba5f4 3768#define D(_y) { .flags = (_y) }
d40a6898
PB		 3769#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3770#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3771 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3772#define N D(NotImpl)
01de8b09 3773#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3774#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3775#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3776#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 3777#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 3778#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3779#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3780#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3781#define II(_f, _e, _i) \
d40a6898 3782 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3783#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3784 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3785 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3786#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3787
8d8f4e9f 3788#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3789#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3790#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3791#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3792#define I2bvIP(_f, _e, _i, _p) \
3793 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3794
fb864fbc
AK		 3795#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3796 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3797 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3798
0f54a321
NA		 3799static const struct opcode group7_rm0[] = {
3800 N,
b34a8051 3801 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 3802 N, N, N, N, N, N,
3803};
3804
fd0a0d82 3805static const struct opcode group7_rm1[] = {
1c2545be
TY		 3806 DI(SrcNone | Priv, monitor),
3807 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3808 N, N, N, N, N, N,
3809};
3810
fd0a0d82 3811static const struct opcode group7_rm3[] = {
1c2545be 3812 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 3813 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 3814 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3815 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3816 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3817 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3818 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3819 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3820};
6230f7fc 3821
fd0a0d82 3822static const struct opcode group7_rm7[] = {
d7eb8203 3823 N,
1c2545be 3824 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3825 N, N, N, N, N, N,
3826};
d67fc27a 3827
fd0a0d82 3828static const struct opcode group1[] = {
fb864fbc
AK		 3829 F(Lock, em_add),
3830 F(Lock | PageTable, em_or),
3831 F(Lock, em_adc),
3832 F(Lock, em_sbb),
3833 F(Lock | PageTable, em_and),
3834 F(Lock, em_sub),
3835 F(Lock, em_xor),
3836 F(NoWrite, em_cmp),
73fba5f4
AK		 3837};
3838
fd0a0d82 3839static const struct opcode group1A[] = {
ab708099 3840 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3841};
3842
007a3b54
AK		 3843static const struct opcode group2[] = {
3844 F(DstMem | ModRM, em_rol),
3845 F(DstMem | ModRM, em_ror),
3846 F(DstMem | ModRM, em_rcl),
3847 F(DstMem | ModRM, em_rcr),
3848 F(DstMem | ModRM, em_shl),
3849 F(DstMem | ModRM, em_shr),
3850 F(DstMem | ModRM, em_shl),
3851 F(DstMem | ModRM, em_sar),
3852};
3853
fd0a0d82 3854static const struct opcode group3[] = {
fb864fbc
AK		 3855 F(DstMem | SrcImm | NoWrite, em_test),
3856 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3857 F(DstMem | SrcNone | Lock, em_not),
3858 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3859 F(DstXacc | Src2Mem, em_mul_ex),
3860 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3861 F(DstXacc | Src2Mem, em_div_ex),
3862 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3863};
3864
fd0a0d82 3865static const struct opcode group4[] = {
95413dc4
AK		 3866 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3867 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3868 N, N, N, N, N, N,
3869};
3870
fd0a0d82 3871static const struct opcode group5[] = {
95413dc4
AK		 3872 F(DstMem | SrcNone | Lock, em_inc),
3873 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3874 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 3875 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 3876 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3877 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3878 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3879};
3880
fd0a0d82 3881static const struct opcode group6[] = {
63ea0a49
NA		 3882 DI(Prot | DstMem, sldt),
3883 DI(Prot | DstMem, str),
a14e579f 3884 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3885 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3886 N, N, N, N,
3887};
3888
fd0a0d82 3889static const struct group_dual group7 = { {
606b1c3e
NA		 3890 II(Mov | DstMem, em_sgdt, sgdt),
3891 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3892 II(SrcMem | Priv, em_lgdt, lgdt),
3893 II(SrcMem | Priv, em_lidt, lidt),
3894 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3895 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3896 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3897}, {
0f54a321 3898 EXT(0, group7_rm0),
5ef39c71 3899 EXT(0, group7_rm1),
01de8b09 3900 N, EXT(0, group7_rm3),
1c2545be
TY		 3901 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3902 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3903 EXT(0, group7_rm7),
73fba5f4
AK		 3904} };
3905
fd0a0d82 3906static const struct opcode group8[] = {
73fba5f4 3907 N, N, N, N,
11c363ba
AK		 3908 F(DstMem | SrcImmByte | NoWrite, em_bt),
3909 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3910 F(DstMem | SrcImmByte | Lock, em_btr),
3911 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3912};
3913
fd0a0d82 3914static const struct group_dual group9 = { {
1c2545be 3915 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3916}, {
3917 N, N, N, N, N, N, N, N,
3918} };
3919
fd0a0d82 3920static const struct opcode group11[] = {
1c2545be 3921 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3922 X7(D(Undefined)),
a4d4a7c1
AK		 3923};
3924
13e457e0 3925static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3926 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3927};
3928
3929static const struct group_dual group15 = { {
3930 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3931}, {
3932 N, N, N, N, N, N, N, N,
3933} };
3934
fd0a0d82 3935static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3936 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3937};
3938
39f062ff
NA		 3939static const struct instr_dual instr_dual_0f_2b = {
3940 I(0, em_mov), N
3941};
3942
d5b77069 3943static const struct gprefix pfx_0f_2b = {
39f062ff 3944 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3945};
3946
27ce8258 3947static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3948 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3949};
3950
0a37027e
AW		 3951static const struct gprefix pfx_0f_e7 = {
3952 N, I(Sse, em_mov), N, N,
3953};
3954
045a282c 3955static const struct escape escape_d9 = { {
16bebefe 3956 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3957}, {
3958 /* 0xC0 - 0xC7 */
3959 N, N, N, N, N, N, N, N,
3960 /* 0xC8 - 0xCF */
3961 N, N, N, N, N, N, N, N,
3962 /* 0xD0 - 0xC7 */
3963 N, N, N, N, N, N, N, N,
3964 /* 0xD8 - 0xDF */
3965 N, N, N, N, N, N, N, N,
3966 /* 0xE0 - 0xE7 */
3967 N, N, N, N, N, N, N, N,
3968 /* 0xE8 - 0xEF */
3969 N, N, N, N, N, N, N, N,
3970 /* 0xF0 - 0xF7 */
3971 N, N, N, N, N, N, N, N,
3972 /* 0xF8 - 0xFF */
3973 N, N, N, N, N, N, N, N,
3974} };
3975
3976static const struct escape escape_db = { {
3977 N, N, N, N, N, N, N, N,
3978}, {
3979 /* 0xC0 - 0xC7 */
3980 N, N, N, N, N, N, N, N,
3981 /* 0xC8 - 0xCF */
3982 N, N, N, N, N, N, N, N,
3983 /* 0xD0 - 0xC7 */
3984 N, N, N, N, N, N, N, N,
3985 /* 0xD8 - 0xDF */
3986 N, N, N, N, N, N, N, N,
3987 /* 0xE0 - 0xE7 */
3988 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3989 /* 0xE8 - 0xEF */
3990 N, N, N, N, N, N, N, N,
3991 /* 0xF0 - 0xF7 */
3992 N, N, N, N, N, N, N, N,
3993 /* 0xF8 - 0xFF */
3994 N, N, N, N, N, N, N, N,
3995} };
3996
3997static const struct escape escape_dd = { {
16bebefe 3998 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3999}, {
4000 /* 0xC0 - 0xC7 */
4001 N, N, N, N, N, N, N, N,
4002 /* 0xC8 - 0xCF */
4003 N, N, N, N, N, N, N, N,
4004 /* 0xD0 - 0xC7 */
4005 N, N, N, N, N, N, N, N,
4006 /* 0xD8 - 0xDF */
4007 N, N, N, N, N, N, N, N,
4008 /* 0xE0 - 0xE7 */
4009 N, N, N, N, N, N, N, N,
4010 /* 0xE8 - 0xEF */
4011 N, N, N, N, N, N, N, N,
4012 /* 0xF0 - 0xF7 */
4013 N, N, N, N, N, N, N, N,
4014 /* 0xF8 - 0xFF */
4015 N, N, N, N, N, N, N, N,
4016} };
4017
39f062ff
NA		 4018static const struct instr_dual instr_dual_0f_c3 = {
4019 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4020};
4021
2276b511
NA		 4022static const struct mode_dual mode_dual_63 = {
4023 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4024};
4025
fd0a0d82 4026static const struct opcode opcode_table[256] = {
73fba5f4 4027 /* 0x00 - 0x07 */
fb864fbc 4028 F6ALU(Lock, em_add),
1cd196ea
AK		 4029 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4030 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4031 /* 0x08 - 0x0F */
fb864fbc 4032 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4033 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4034 N,
73fba5f4 4035 /* 0x10 - 0x17 */
fb864fbc 4036 F6ALU(Lock, em_adc),
1cd196ea
AK		 4037 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4038 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4039 /* 0x18 - 0x1F */
fb864fbc 4040 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4041 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4042 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4043 /* 0x20 - 0x27 */
fb864fbc 4044 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4045 /* 0x28 - 0x2F */
fb864fbc 4046 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4047 /* 0x30 - 0x37 */
fb864fbc 4048 F6ALU(Lock, em_xor), N, N,
73fba5f4 4049 /* 0x38 - 0x3F */
fb864fbc 4050 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4051 /* 0x40 - 0x4F */
95413dc4 4052 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4053 /* 0x50 - 0x57 */
63540382 4054 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4055 /* 0x58 - 0x5F */
c54fe504 4056 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4057 /* 0x60 - 0x67 */
b96a7fad
TY		 4058 I(ImplicitOps | Stack | No64, em_pusha),
4059 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4060 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4061 N, N, N, N,
4062 /* 0x68 - 0x6F */
d46164db
AK		 4063 I(SrcImm | Mov | Stack, em_push),
4064 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4065 I(SrcImmByte | Mov | Stack, em_push),
4066 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4067 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4068 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4069 /* 0x70 - 0x7F */
58b7075d 4070 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4071 /* 0x80 - 0x87 */
1c2545be
TY		 4072 G(ByteOp | DstMem | SrcImm, group1),
4073 G(DstMem | SrcImm, group1),
4074 G(ByteOp | DstMem | SrcImm | No64, group1),
4075 G(DstMem | SrcImmByte, group1),
fb864fbc 4076 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4077 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4078 /* 0x88 - 0x8F */
d5ae7ce8 4079 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4080 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4081 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4082 D(ModRM | SrcMem | NoAccess | DstReg),
4083 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4084 G(0, group1A),
73fba5f4 4085 /* 0x90 - 0x97 */
bf608f88 4086 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4087 /* 0x98 - 0x9F */
61429142 4088 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4089 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4090 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4091 II(ImplicitOps | Stack, em_popf, popf),
4092 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4093 /* 0xA0 - 0xA7 */
b9eac5f4 4094 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4095 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4096 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4097 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4098 /* 0xA8 - 0xAF */
fb864fbc 4099 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4100 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4101 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4102 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4103 /* 0xB0 - 0xB7 */
b9eac5f4 4104 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4105 /* 0xB8 - 0xBF */
5e2c6883 4106 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4107 /* 0xC0 - 0xC7 */
007a3b54 4108 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4109 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4110 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4111 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4112 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4113 G(ByteOp, group11), G(0, group11),
73fba5f4 4114 /* 0xC8 - 0xCF */
612e89f0 4115 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4116 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4117 I(ImplicitOps, em_ret_far),
3c6e276f 4118 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4119 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4120 /* 0xD0 - 0xD7 */
007a3b54
AK		 4121 G(Src2One | ByteOp, group2), G(Src2One, group2),
4122 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4123 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4124 I(DstAcc | SrcImmUByte | No64, em_aad),
4125 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4126 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4127 /* 0xD8 - 0xDF */
045a282c 4128 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4129 /* 0xE0 - 0xE7 */
58b7075d
NA		 4130 X3(I(SrcImmByte | NearBranch, em_loop)),
4131 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4132 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4133 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4134 /* 0xE8 - 0xEF */
58b7075d
NA		 4135 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4136 I(SrcImmFAddr | No64, em_jmp_far),
4137 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4138 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4139 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4140 /* 0xF0 - 0xF7 */
bf608f88 4141 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4142 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4143 G(ByteOp, group3), G(0, group3),
73fba5f4 4144 /* 0xF8 - 0xFF */
f411e6cd
TY		 4145 D(ImplicitOps), D(ImplicitOps),
4146 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4147 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4148};
4149
fd0a0d82 4150static const struct opcode twobyte_table[256] = {
73fba5f4 4151 /* 0x00 - 0x0F */
dee6bb70 4152 G(0, group6), GD(0, &group7), N, N,
b51e974f 4153 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4154 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4155 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4156 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4157 /* 0x10 - 0x1F */
103f98ea 4158 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4159 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4160 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4161 /* 0x20 - 0x2F */
9b88ae99
NA		 4162 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4163 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4164 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4165 check_cr_write),
4166 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4167 check_dr_write),
73fba5f4 4168 N, N, N, N,
27ce8258
IM		 4169 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4170 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4171 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4172 N, N, N, N,
73fba5f4 4173 /* 0x30 - 0x3F */
e1e210b0 4174 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4175 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4176 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4177 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4178 I(ImplicitOps | EmulateOnUD, em_sysenter),
4179 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4180 N, N,
73fba5f4
AK		 4181 N, N, N, N, N, N, N, N,
4182 /* 0x40 - 0x4F */
140bad89 4183 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4184 /* 0x50 - 0x5F */
4185 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4186 /* 0x60 - 0x6F */
aa97bb48
AK		 4187 N, N, N, N,
4188 N, N, N, N,
4189 N, N, N, N,
4190 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4191 /* 0x70 - 0x7F */
aa97bb48
AK		 4192 N, N, N, N,
4193 N, N, N, N,
4194 N, N, N, N,
4195 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4196 /* 0x80 - 0x8F */
58b7075d 4197 X16(D(SrcImm | NearBranch)),
73fba5f4 4198 /* 0x90 - 0x9F */
ee45b58e 4199 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4200 /* 0xA0 - 0xA7 */
1cd196ea 4201 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4202 II(ImplicitOps, em_cpuid, cpuid),
4203 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4204 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4205 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4206 /* 0xA8 - 0xAF */
1cd196ea 4207 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
64d60670 4208 II(No64 | EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4209 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4210 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4211 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4212 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4213 /* 0xB0 - 0xB7 */
2fcf5c8a 4214 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4215 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4216 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4217 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4218 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4219 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4220 /* 0xB8 - 0xBF */
4221 N, N,
ce7faab2 4222 G(BitOp, group8),
11c363ba 4223 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4224 I(DstReg | SrcMem | ModRM, em_bsf_c),
4225 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4226 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4227 /* 0xC0 - 0xC7 */
e47a5f5f 4228 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4229 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4230 N, N, N, GD(0, &group9),
9299836e
AK		 4231 /* 0xC8 - 0xCF */
4232 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4233 /* 0xD0 - 0xDF */
4234 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4235 /* 0xE0 - 0xEF */
0a37027e
AW		 4236 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4237 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4238 /* 0xF0 - 0xFF */
4239 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4240};
4241
39f062ff
NA		 4242static const struct instr_dual instr_dual_0f_38_f0 = {
4243 I(DstReg | SrcMem | Mov, em_movbe), N
4244};
4245
4246static const struct instr_dual instr_dual_0f_38_f1 = {
4247 I(DstMem | SrcReg | Mov, em_movbe), N
4248};
4249
0bc5eedb 4250static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4251 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4252};
4253
4254static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4255 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4256};
4257
4258/*
4259 * Insns below are selected by the prefix which indexed by the third opcode
4260 * byte.
4261 */
4262static const struct opcode opcode_map_0f_38[256] = {
4263 /* 0x00 - 0x7f */
4264 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4265 /* 0x80 - 0xef */
4266 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4267 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4268 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4269 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4270 /* 0xf2 - 0xff */
4271 N, N, X4(N), X8(N)
0bc5eedb
BP		 4272};
4273
73fba5f4
AK		 4274#undef D
4275#undef N
4276#undef G
4277#undef GD
4278#undef I
aa97bb48 4279#undef GP
01de8b09 4280#undef EXT
2276b511 4281#undef MD
2b42fce6 4282#undef ID
73fba5f4 4283
8d8f4e9f 4284#undef D2bv
f6511935 4285#undef D2bvIP
8d8f4e9f 4286#undef I2bv
d7841a4b 4287#undef I2bvIP
d67fc27a 4288#undef I6ALU
8d8f4e9f 4289
9dac77fa 4290static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4291{
4292 unsigned size;
4293
9dac77fa 4294 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4295 if (size == 8)
4296 size = 4;
4297 return size;
4298}
4299
4300static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4301 unsigned size, bool sign_extension)
4302{
39f21ee5
AK		 4303 int rc = X86EMUL_CONTINUE;
4304
4305 op->type = OP_IMM;
4306 op->bytes = size;
9dac77fa 4307 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4308 /* NB. Immediates are sign-extended as necessary. */
4309 switch (op->bytes) {
4310 case 1:
e85a1085 4311 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4312 break;
4313 case 2:
e85a1085 4314 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4315 break;
4316 case 4:
e85a1085 4317 op->val = insn_fetch(s32, ctxt);
39f21ee5 4318 break;
5e2c6883
NA		 4319 case 8:
4320 op->val = insn_fetch(s64, ctxt);
4321 break;
39f21ee5
AK		 4322 }
4323 if (!sign_extension) {
4324 switch (op->bytes) {
4325 case 1:
4326 op->val &= 0xff;
4327 break;
4328 case 2:
4329 op->val &= 0xffff;
4330 break;
4331 case 4:
4332 op->val &= 0xffffffff;
4333 break;
4334 }
4335 }
4336done:
4337 return rc;
4338}
4339
a9945549
AK		 4340static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4341 unsigned d)
4342{
4343 int rc = X86EMUL_CONTINUE;
4344
4345 switch (d) {
4346 case OpReg:
2adb5ad9 4347 decode_register_operand(ctxt, op);
a9945549
AK		 4348 break;
4349 case OpImmUByte:
608aabe3 4350 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4351 break;
4352 case OpMem:
41ddf978 4353 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4354 mem_common:
4355 *op = ctxt->memop;
4356 ctxt->memopp = op;
96888977 4357 if (ctxt->d & BitOp)
a9945549
AK		 4358 fetch_bit_operand(ctxt);
4359 op->orig_val = op->val;
4360 break;
41ddf978 4361 case OpMem64:
aaa05f24 4362 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4363 goto mem_common;
a9945549
AK		 4364 case OpAcc:
4365 op->type = OP_REG;
4366 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4367 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4368 fetch_register_operand(op);
4369 op->orig_val = op->val;
4370 break;
820207c8
AK		 4371 case OpAccLo:
4372 op->type = OP_REG;
4373 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4374 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4375 fetch_register_operand(op);
4376 op->orig_val = op->val;
4377 break;
4378 case OpAccHi:
4379 if (ctxt->d & ByteOp) {
4380 op->type = OP_NONE;
4381 break;
4382 }
4383 op->type = OP_REG;
4384 op->bytes = ctxt->op_bytes;
4385 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4386 fetch_register_operand(op);
4387 op->orig_val = op->val;
4388 break;
a9945549
AK		 4389 case OpDI:
4390 op->type = OP_MEM;
4391 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4392 op->addr.mem.ea =
01485a22 4393 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4394 op->addr.mem.seg = VCPU_SREG_ES;
4395 op->val = 0;
b3356bf0 4396 op->count = 1;
a9945549
AK		 4397 break;
4398 case OpDX:
4399 op->type = OP_REG;
4400 op->bytes = 2;
dd856efa 4401 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4402 fetch_register_operand(op);
4403 break;
4dd6a57d 4404 case OpCL:
d29b9d7e 4405 op->type = OP_IMM;
4dd6a57d 4406 op->bytes = 1;
dd856efa 4407 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4408 break;
4409 case OpImmByte:
4410 rc = decode_imm(ctxt, op, 1, true);
4411 break;
4412 case OpOne:
d29b9d7e 4413 op->type = OP_IMM;
4dd6a57d
AK		 4414 op->bytes = 1;
4415 op->val = 1;
4416 break;
4417 case OpImm:
4418 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4419 break;
5e2c6883
NA		 4420 case OpImm64:
4421 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4422 break;
28867cee
AK		 4423 case OpMem8:
4424 ctxt->memop.bytes = 1;
660696d1 4425 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4426 ctxt->memop.addr.reg = decode_register(ctxt,
4427 ctxt->modrm_rm, true);
660696d1
GN		 4428 fetch_register_operand(&ctxt->memop);
4429 }
28867cee 4430 goto mem_common;
0fe59128
AK		 4431 case OpMem16:
4432 ctxt->memop.bytes = 2;
4433 goto mem_common;
4434 case OpMem32:
4435 ctxt->memop.bytes = 4;
4436 goto mem_common;
4437 case OpImmU16:
4438 rc = decode_imm(ctxt, op, 2, false);
4439 break;
4440 case OpImmU:
4441 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4442 break;
4443 case OpSI:
4444 op->type = OP_MEM;
4445 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4446 op->addr.mem.ea =
01485a22 4447 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4448 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4449 op->val = 0;
b3356bf0 4450 op->count = 1;
0fe59128 4451 break;
7fa57952
PB		 4452 case OpXLat:
4453 op->type = OP_MEM;
4454 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4455 op->addr.mem.ea =
01485a22 4456 address_mask(ctxt,
7fa57952
PB		 4457 reg_read(ctxt, VCPU_REGS_RBX) +
4458 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4459 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4460 op->val = 0;
4461 break;
0fe59128
AK		 4462 case OpImmFAddr:
4463 op->type = OP_IMM;
4464 op->addr.mem.ea = ctxt->_eip;
4465 op->bytes = ctxt->op_bytes + 2;
4466 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4467 break;
4468 case OpMemFAddr:
4469 ctxt->memop.bytes = ctxt->op_bytes + 2;
4470 goto mem_common;
c191a7a0 4471 case OpES:
d29b9d7e 4472 op->type = OP_IMM;
c191a7a0
AK		 4473 op->val = VCPU_SREG_ES;
4474 break;
4475 case OpCS:
d29b9d7e 4476 op->type = OP_IMM;
c191a7a0
AK		 4477 op->val = VCPU_SREG_CS;
4478 break;
4479 case OpSS:
d29b9d7e 4480 op->type = OP_IMM;
c191a7a0
AK		 4481 op->val = VCPU_SREG_SS;
4482 break;
4483 case OpDS:
d29b9d7e 4484 op->type = OP_IMM;
c191a7a0
AK		 4485 op->val = VCPU_SREG_DS;
4486 break;
4487 case OpFS:
d29b9d7e 4488 op->type = OP_IMM;
c191a7a0
AK		 4489 op->val = VCPU_SREG_FS;
4490 break;
4491 case OpGS:
d29b9d7e 4492 op->type = OP_IMM;
c191a7a0
AK		 4493 op->val = VCPU_SREG_GS;
4494 break;
a9945549
AK		 4495 case OpImplicit:
4496 /* Special instructions do their own operand decoding. */
4497 default:
4498 op->type = OP_NONE; /* Disable writeback. */
4499 break;
4500 }
4501
4502done:
4503 return rc;
4504}
4505
ef5d75cc 4506int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4507{
dde7e6d1
AK		 4508 int rc = X86EMUL_CONTINUE;
4509 int mode = ctxt->mode;
46561646 4510 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4511 bool op_prefix = false;
573e80fe 4512 bool has_seg_override = false;
46561646 4513 struct opcode opcode;
dde7e6d1 4514
f09ed83e
AK		 4515 ctxt->memop.type = OP_NONE;
4516 ctxt->memopp = NULL;
9dac77fa 4517 ctxt->_eip = ctxt->eip;
17052f16
PB		 4518 ctxt->fetch.ptr = ctxt->fetch.data;
4519 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4520 ctxt->opcode_len = 1;
dc25e89e 4521 if (insn_len > 0)
9dac77fa 4522 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4523 else {
9506d57d 4524 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4525 if (rc != X86EMUL_CONTINUE)
4526 return rc;
4527 }
dde7e6d1
AK		 4528
4529 switch (mode) {
4530 case X86EMUL_MODE_REAL:
4531 case X86EMUL_MODE_VM86:
4532 case X86EMUL_MODE_PROT16:
4533 def_op_bytes = def_ad_bytes = 2;
4534 break;
4535 case X86EMUL_MODE_PROT32:
4536 def_op_bytes = def_ad_bytes = 4;
4537 break;
4538#ifdef CONFIG_X86_64
4539 case X86EMUL_MODE_PROT64:
4540 def_op_bytes = 4;
4541 def_ad_bytes = 8;
4542 break;
4543#endif
4544 default:
1d2887e2 4545 return EMULATION_FAILED;
dde7e6d1
AK		 4546 }
4547
9dac77fa
AK		 4548 ctxt->op_bytes = def_op_bytes;
4549 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4550
4551 /* Legacy prefixes. */
4552 for (;;) {
e85a1085 4553 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4554 case 0x66: /* operand-size override */
0d7cdee8 4555 op_prefix = true;
dde7e6d1 4556 /* switch between 2/4 bytes */
9dac77fa 4557 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4558 break;
4559 case 0x67: /* address-size override */
4560 if (mode == X86EMUL_MODE_PROT64)
4561 /* switch between 4/8 bytes */
9dac77fa 4562 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4563 else
4564 /* switch between 2/4 bytes */
9dac77fa 4565 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4566 break;
4567 case 0x26: /* ES override */
4568 case 0x2e: /* CS override */
4569 case 0x36: /* SS override */
4570 case 0x3e: /* DS override */
573e80fe
BD		 4571 has_seg_override = true;
4572 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4573 break;
4574 case 0x64: /* FS override */
4575 case 0x65: /* GS override */
573e80fe
BD		 4576 has_seg_override = true;
4577 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4578 break;
4579 case 0x40 ... 0x4f: /* REX */
4580 if (mode != X86EMUL_MODE_PROT64)
4581 goto done_prefixes;
9dac77fa 4582 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4583 continue;
4584 case 0xf0: /* LOCK */
9dac77fa 4585 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4586 break;
4587 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4588 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4589 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4590 break;
4591 default:
4592 goto done_prefixes;
4593 }
4594
4595 /* Any legacy prefix after a REX prefix nullifies its effect. */
4596
9dac77fa 4597 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4598 }
4599
4600done_prefixes:
4601
4602 /* REX prefix. */
9dac77fa
AK		 4603 if (ctxt->rex_prefix & 8)
4604 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4605
4606 /* Opcode byte(s). */
9dac77fa 4607 opcode = opcode_table[ctxt->b];
d3ad6243 4608 /* Two-byte opcode? */
9dac77fa 4609 if (ctxt->b == 0x0f) {
1ce19dc1 4610 ctxt->opcode_len = 2;
e85a1085 4611 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4612 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4613
4614 /* 0F_38 opcode map */
4615 if (ctxt->b == 0x38) {
4616 ctxt->opcode_len = 3;
4617 ctxt->b = insn_fetch(u8, ctxt);
4618 opcode = opcode_map_0f_38[ctxt->b];
4619 }
dde7e6d1 4620 }
9dac77fa 4621 ctxt->d = opcode.flags;
dde7e6d1 4622
9f4260e7
TY		 4623 if (ctxt->d & ModRM)
4624 ctxt->modrm = insn_fetch(u8, ctxt);
4625
7fe864dc
NA		 4626 /* vex-prefix instructions are not implemented */
4627 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4628 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4629 ctxt->d = NotImpl;
4630 }
4631
9dac77fa
AK		 4632 while (ctxt->d & GroupMask) {
4633 switch (ctxt->d & GroupMask) {
46561646 4634 case Group:
9dac77fa 4635 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4636 opcode = opcode.u.group[goffset];
4637 break;
4638 case GroupDual:
9dac77fa
AK		 4639 goffset = (ctxt->modrm >> 3) & 7;
4640 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4641 opcode = opcode.u.gdual->mod3[goffset];
4642 else
4643 opcode = opcode.u.gdual->mod012[goffset];
4644 break;
4645 case RMExt:
9dac77fa 4646 goffset = ctxt->modrm & 7;
01de8b09 4647 opcode = opcode.u.group[goffset];
46561646
AK		 4648 break;
4649 case Prefix:
9dac77fa 4650 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4651 return EMULATION_FAILED;
9dac77fa 4652 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4653 switch (simd_prefix) {
4654 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4655 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4656 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4657 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4658 }
4659 break;
045a282c
GN		 4660 case Escape:
4661 if (ctxt->modrm > 0xbf)
4662 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4663 else
4664 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4665 break;
39f062ff
NA		 4666 case InstrDual:
4667 if ((ctxt->modrm >> 6) == 3)
4668 opcode = opcode.u.idual->mod3;
4669 else
4670 opcode = opcode.u.idual->mod012;
4671 break;
2276b511
NA		 4672 case ModeDual:
4673 if (ctxt->mode == X86EMUL_MODE_PROT64)
4674 opcode = opcode.u.mdual->mode64;
4675 else
4676 opcode = opcode.u.mdual->mode32;
4677 break;
46561646 4678 default:
1d2887e2 4679 return EMULATION_FAILED;
0d7cdee8 4680 }
46561646 4681
b1ea50b2 4682 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4683 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4684 }
4685
e24186e0
PB		 4686 /* Unrecognised? */
4687 if (ctxt->d == 0)
4688 return EMULATION_FAILED;
4689
9dac77fa 4690 ctxt->execute = opcode.u.execute;
dde7e6d1 4691
3a6095a0
NA		 4692 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4693 return EMULATION_FAILED;
4694
d40a6898 4695 if (unlikely(ctxt->d &
ed9aad21
NA		 4696 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4697 No16))) {
d40a6898
PB		 4698 /*
4699 * These are copied unconditionally here, and checked unconditionally
4700 * in x86_emulate_insn.
4701 */
4702 ctxt->check_perm = opcode.check_perm;
4703 ctxt->intercept = opcode.intercept;
dde7e6d1 4704
d40a6898
PB		 4705 if (ctxt->d & NotImpl)
4706 return EMULATION_FAILED;
d867162c 4707
58b7075d
NA		 4708 if (mode == X86EMUL_MODE_PROT64) {
4709 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4710 ctxt->op_bytes = 8;
4711 else if (ctxt->d & NearBranch)
4712 ctxt->op_bytes = 8;
4713 }
7f9b4b75 4714
d40a6898
PB		 4715 if (ctxt->d & Op3264) {
4716 if (mode == X86EMUL_MODE_PROT64)
4717 ctxt->op_bytes = 8;
4718 else
4719 ctxt->op_bytes = 4;
4720 }
4721
ed9aad21
NA		 4722 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4723 ctxt->op_bytes = 4;
4724
d40a6898
PB		 4725 if (ctxt->d & Sse)
4726 ctxt->op_bytes = 16;
4727 else if (ctxt->d & Mmx)
4728 ctxt->op_bytes = 8;
4729 }
1253791d 4730
dde7e6d1 4731 /* ModRM and SIB bytes. */
9dac77fa 4732 if (ctxt->d & ModRM) {
f09ed83e 4733 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4734 if (!has_seg_override) {
4735 has_seg_override = true;
4736 ctxt->seg_override = ctxt->modrm_seg;
4737 }
9dac77fa 4738 } else if (ctxt->d & MemAbs)
f09ed83e 4739 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4740 if (rc != X86EMUL_CONTINUE)
4741 goto done;
4742
573e80fe
BD		 4743 if (!has_seg_override)
4744 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4745
573e80fe 4746 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4747
dde7e6d1
AK		 4748 /*
4749 * Decode and fetch the source operand: register, memory
4750 * or immediate.
4751 */
0fe59128 4752 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4753 if (rc != X86EMUL_CONTINUE)
4754 goto done;
4755
dde7e6d1
AK		 4756 /*
4757 * Decode and fetch the second source operand: register, memory
4758 * or immediate.
4759 */
4dd6a57d 4760 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4761 if (rc != X86EMUL_CONTINUE)
4762 goto done;
4763
dde7e6d1 4764 /* Decode and fetch the destination operand: register or memory. */
a9945549 4765 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4766
41061cdb 4767 if (ctxt->rip_relative)
1c1c35ae
NA		 4768 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4769 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4770
a430c916 4771done:
1d2887e2 4772 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4773}
4774
1cb3f3ae
XG		 4775bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4776{
4777 return ctxt->d & PageTable;
4778}
4779
3e2f65d5
GN		 4780static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4781{
3e2f65d5
GN		 4782 /* The second termination condition only applies for REPE
4783 * and REPNE. Test if the repeat string operation prefix is
4784 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4785 * corresponding termination condition according to:
4786 * - if REPE/REPZ and ZF = 0 then done
4787 * - if REPNE/REPNZ and ZF = 1 then done
4788 */
9dac77fa
AK		 4789 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4790 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4791 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 4792 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 4793 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 4794 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 4795 return true;
4796
4797 return false;
4798}
4799
cbe2c9d3
AK		 4800static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4801{
4802 bool fault = false;
4803
4804 ctxt->ops->get_fpu(ctxt);
4805 asm volatile("1: fwait \n\t"
4806 "2: \n\t"
4807 ".pushsection .fixup,\"ax\" \n\t"
4808 "3: \n\t"
4809 "movb $1, %[fault] \n\t"
4810 "jmp 2b \n\t"
4811 ".popsection \n\t"
4812 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4813 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4814 ctxt->ops->put_fpu(ctxt);
4815
4816 if (unlikely(fault))
4817 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4818
4819 return X86EMUL_CONTINUE;
4820}
4821
4822static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4823 struct operand *op)
4824{
4825 if (op->type == OP_MM)
4826 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4827}
4828
e28bbd44
AK		 4829static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4830{
4831 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4832 if (!(ctxt->d & ByteOp))
4833 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4834 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4835 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4836 [fastop]"+S"(fop)
4837 : "c"(ctxt->src2.val));
e28bbd44 4838 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4839 if (!fop) /* exception is returned in fop variable */
4840 return emulate_de(ctxt);
e28bbd44
AK		 4841 return X86EMUL_CONTINUE;
4842}
dd856efa 4843
1498507a
BD		 4844void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4845{
573e80fe
BD		 4846 memset(&ctxt->rip_relative, 0,
4847 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4848
1498507a
BD		 4849 ctxt->io_read.pos = 0;
4850 ctxt->io_read.end = 0;
1498507a
BD		 4851 ctxt->mem_read.end = 0;
4852}
4853
7b105ca2 4854int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4855{
0225fb50 4856 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4857 int rc = X86EMUL_CONTINUE;
9dac77fa 4858 int saved_dst_type = ctxt->dst.type;
8b4caf66 4859
9dac77fa 4860 ctxt->mem_read.pos = 0;
310b5d30 4861
e24186e0
PB		 4862 /* LOCK prefix is allowed only with some instructions */
4863 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4864 rc = emulate_ud(ctxt);
1161624f
GN		 4865 goto done;
4866 }
4867
e24186e0 4868 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4869 rc = emulate_ud(ctxt);
d380a5e4
GN		 4870 goto done;
4871 }
4872
d40a6898
PB		 4873 if (unlikely(ctxt->d &
4874 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4875 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4876 (ctxt->d & Undefined)) {
4877 rc = emulate_ud(ctxt);
4878 goto done;
4879 }
1253791d 4880
d40a6898
PB		 4881 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4882 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4883 rc = emulate_ud(ctxt);
cbe2c9d3 4884 goto done;
d40a6898 4885 }
cbe2c9d3 4886
d40a6898
PB		 4887 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4888 rc = emulate_nm(ctxt);
c4f035c6 4889 goto done;
d40a6898 4890 }
c4f035c6 4891
d40a6898
PB		 4892 if (ctxt->d & Mmx) {
4893 rc = flush_pending_x87_faults(ctxt);
4894 if (rc != X86EMUL_CONTINUE)
4895 goto done;
4896 /*
4897 * Now that we know the fpu is exception safe, we can fetch
4898 * operands from it.
4899 */
4900 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4901 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4902 if (!(ctxt->d & Mov))
4903 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4904 }
e92805ac 4905
a584539b 4906 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 4907 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4908 X86_ICPT_PRE_EXCEPT);
4909 if (rc != X86EMUL_CONTINUE)
4910 goto done;
4911 }
8ea7d6ae 4912
64a38292
NA		 4913 /* Instruction can only be executed in protected mode */
4914 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4915 rc = emulate_ud(ctxt);
4916 goto done;
4917 }
4918
d40a6898
PB		 4919 /* Privileged instruction can be executed only in CPL=0 */
4920 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4921 if (ctxt->d & PrivUD)
4922 rc = emulate_ud(ctxt);
4923 else
4924 rc = emulate_gp(ctxt, 0);
d09beabd 4925 goto done;
d40a6898 4926 }
d09beabd 4927
d40a6898 4928 /* Do instruction specific permission checks */
685bbf4a 4929 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4930 rc = ctxt->check_perm(ctxt);
4931 if (rc != X86EMUL_CONTINUE)
4932 goto done;
4933 }
4934
a584539b 4935 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 4936 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4937 X86_ICPT_POST_EXCEPT);
4938 if (rc != X86EMUL_CONTINUE)
4939 goto done;
4940 }
4941
4942 if (ctxt->rep_prefix && (ctxt->d & String)) {
4943 /* All REP prefixes have the same first termination condition */
4944 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 4945 string_registers_quirk(ctxt);
d40a6898 4946 ctxt->eip = ctxt->_eip;
0efb0440 4947 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 4948 goto done;
4949 }
b9fa9d6b 4950 }
b9fa9d6b
AK		 4951 }
4952
9dac77fa
AK		 4953 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4954 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4955 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4956 if (rc != X86EMUL_CONTINUE)
8b4caf66 4957 goto done;
9dac77fa 4958 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4959 }
4960
9dac77fa
AK		 4961 if (ctxt->src2.type == OP_MEM) {
4962 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4963 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4964 if (rc != X86EMUL_CONTINUE)
4965 goto done;
4966 }
4967
9dac77fa 4968 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4969 goto special_insn;
4970
4971
9dac77fa 4972 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4973 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4974 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4975 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 4976 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 4977 if (!(ctxt->d & NoWrite) &&
4978 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 4979 ctxt->exception.vector == PF_VECTOR)
4980 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 4981 goto done;
c205fb7d 4982 }
038e51de 4983 }
4ff6f8e6
PB		 4984 /* Copy full 64-bit value for CMPXCHG8B. */
4985 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 4986
018a98db
AK		 4987special_insn:
4988
a584539b 4989 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 4990 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4991 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4992 if (rc != X86EMUL_CONTINUE)
4993 goto done;
4994 }
4995
b9a1ecb9 4996 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 4997 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 4998 else
0efb0440 4999 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5000
9dac77fa 5001 if (ctxt->execute) {
e28bbd44
AK		 5002 if (ctxt->d & Fastop) {
5003 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5004 rc = fastop(ctxt, fop);
5005 if (rc != X86EMUL_CONTINUE)
5006 goto done;
5007 goto writeback;
5008 }
9dac77fa 5009 rc = ctxt->execute(ctxt);
ef65c889
AK		 5010 if (rc != X86EMUL_CONTINUE)
5011 goto done;
5012 goto writeback;
5013 }
5014
1ce19dc1 5015 if (ctxt->opcode_len == 2)
6aa8b732 5016 goto twobyte_insn;
0bc5eedb
BP		 5017 else if (ctxt->opcode_len == 3)
5018 goto threebyte_insn;
6aa8b732 5019
9dac77fa 5020 switch (ctxt->b) {
b2833e3c 5021 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5022 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5023 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5024 break;
7e0b54b1 5025 case 0x8d: /* lea r16/r32, m */
9dac77fa 5026 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5027 break;
3d9e77df 5028 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5029 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5030 ctxt->dst.type = OP_NONE;
5031 else
5032 rc = em_xchg(ctxt);
e4f973ae 5033 break;
e8b6fa70 5034 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5035 switch (ctxt->op_bytes) {
5036 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5037 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5038 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5039 }
5040 break;
6e154e56 5041 case 0xcc: /* int3 */
5c5df76b
TY		 5042 rc = emulate_int(ctxt, 3);
5043 break;
6e154e56 5044 case 0xcd: /* int n */
9dac77fa 5045 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5046 break;
5047 case 0xce: /* into */
0efb0440 5048 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5049 rc = emulate_int(ctxt, 4);
6e154e56 5050 break;
1a52e051 5051 case 0xe9: /* jmp rel */
db5b0762 5052 case 0xeb: /* jmp rel short */
234f3ce4 5053 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5054 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5055 break;
111de5d6 5056 case 0xf4: /* hlt */
6c3287f7 5057 ctxt->ops->halt(ctxt);
19fdfa0d 5058 break;
111de5d6
AK		 5059 case 0xf5: /* cmc */
5060 /* complement carry flag from eflags reg */
0efb0440 5061 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5062 break;
5063 case 0xf8: /* clc */
0efb0440 5064 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5065 break;
8744aa9a 5066 case 0xf9: /* stc */
0efb0440 5067 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5068 break;
fb4616f4 5069 case 0xfc: /* cld */
0efb0440 5070 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5071 break;
5072 case 0xfd: /* std */
0efb0440 5073 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5074 break;
91269b8f
AK		 5075 default:
5076 goto cannot_emulate;
6aa8b732 5077 }
018a98db 5078
7d9ddaed
AK		 5079 if (rc != X86EMUL_CONTINUE)
5080 goto done;
5081
018a98db 5082writeback:
fb32b1ed
AK		 5083 if (ctxt->d & SrcWrite) {
5084 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5085 rc = writeback(ctxt, &ctxt->src);
5086 if (rc != X86EMUL_CONTINUE)
5087 goto done;
5088 }
ee212297
NA		 5089 if (!(ctxt->d & NoWrite)) {
5090 rc = writeback(ctxt, &ctxt->dst);
5091 if (rc != X86EMUL_CONTINUE)
5092 goto done;
5093 }
018a98db 5094
5cd21917
GN		 5095 /*
5096 * restore dst type in case the decoding will be reused
5097 * (happens for string instruction )
5098 */
9dac77fa 5099 ctxt->dst.type = saved_dst_type;
5cd21917 5100
9dac77fa 5101 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5102 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5103
9dac77fa 5104 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5105 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5106
9dac77fa 5107 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5108 unsigned int count;
9dac77fa 5109 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5110 if ((ctxt->d & SrcMask) == SrcSI)
5111 count = ctxt->src.count;
5112 else
5113 count = ctxt->dst.count;
01485a22 5114 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5115
d2ddd1c4
GN		 5116 if (!string_insn_completed(ctxt)) {
5117 /*
5118 * Re-enter guest when pio read ahead buffer is empty
5119 * or, if it is not used, after each 1024 iteration.
5120 */
dd856efa 5121 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5122 (r->end == 0 || r->end != r->pos)) {
5123 /*
5124 * Reset read cache. Usually happens before
5125 * decode, but since instruction is restarted
5126 * we have to do it here.
5127 */
9dac77fa 5128 ctxt->mem_read.end = 0;
dd856efa 5129 writeback_registers(ctxt);
d2ddd1c4
GN		 5130 return EMULATION_RESTART;
5131 }
5132 goto done; /* skip rip writeback */
0fa6ccbd 5133 }
0efb0440 5134 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5135 }
d2ddd1c4 5136
9dac77fa 5137 ctxt->eip = ctxt->_eip;
018a98db
AK		 5138
5139done:
e0ad0b47
PB		 5140 if (rc == X86EMUL_PROPAGATE_FAULT) {
5141 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5142 ctxt->have_exception = true;
e0ad0b47 5143 }
775fde86
JR		 5144 if (rc == X86EMUL_INTERCEPTED)
5145 return EMULATION_INTERCEPTED;
5146
dd856efa
AK		 5147 if (rc == X86EMUL_CONTINUE)
5148 writeback_registers(ctxt);
5149
d2ddd1c4 5150 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5151
5152twobyte_insn:
9dac77fa 5153 switch (ctxt->b) {
018a98db 5154 case 0x09: /* wbinvd */
cfb22375 5155 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5156 break;
5157 case 0x08: /* invd */
018a98db
AK		 5158 case 0x0d: /* GrpP (prefetch) */
5159 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5160 case 0x1f: /* nop */
018a98db
AK		 5161 break;
5162 case 0x20: /* mov cr, reg */
9dac77fa 5163 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5164 break;
6aa8b732 5165 case 0x21: /* mov from dr to reg */
9dac77fa 5166 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5167 break;
6aa8b732 5168 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5169 if (test_cc(ctxt->b, ctxt->eflags))
5170 ctxt->dst.val = ctxt->src.val;
b91aa14d 5171 else if (ctxt->op_bytes != 4)
9dac77fa 5172 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5173 break;
b2833e3c 5174 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5175 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5176 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5177 break;
ee45b58e 5178 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5179 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5180 break;
6aa8b732 5181 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5182 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5183 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5184 : (u16) ctxt->src.val;
6aa8b732 5185 break;
6aa8b732 5186 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5187 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5188 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5189 (s16) ctxt->src.val;
6aa8b732 5190 break;
91269b8f
AK		 5191 default:
5192 goto cannot_emulate;
6aa8b732 5193 }
7d9ddaed 5194
0bc5eedb
BP		 5195threebyte_insn:
5196
7d9ddaed
AK		 5197 if (rc != X86EMUL_CONTINUE)
5198 goto done;
5199
6aa8b732
AK		 5200 goto writeback;
5201
5202cannot_emulate:
a0c0ab2f 5203 return EMULATION_FAILED;
6aa8b732 5204}
dd856efa
AK		 5205
5206void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5207{
5208 invalidate_registers(ctxt);
5209}
5210
5211void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5212{
5213 writeback_registers(ctxt);
5214}
Linux kernel - Deliverables
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