Commit | Line | Data |
---|---|---|
6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 27 | #else |
edf88417 | 28 | #include <linux/kvm_host.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
30 | #define DPRINTF(x...) do {} while (0) |
31 | #endif | |
6aa8b732 | 32 | #include <linux/module.h> |
56e82318 | 33 | #include <asm/kvm_emulate.h> |
6aa8b732 | 34 | |
3eeb3288 | 35 | #include "x86.h" |
38ba30ba | 36 | #include "tss.h" |
e99f0507 | 37 | |
6aa8b732 AK |
38 | /* |
39 | * Opcode effective-address decode tables. | |
40 | * Note that we only emulate instructions that have at least one memory | |
41 | * operand (excluding implicit stack references). We assume that stack | |
42 | * references and instruction fetches will never occur in special memory | |
43 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
44 | * not be handled. | |
45 | */ | |
46 | ||
47 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
48 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
49 | /* Destination operand type. */ | |
50 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
51 | #define DstReg (2<<1) /* Register operand. */ | |
52 | #define DstMem (3<<1) /* Memory operand. */ | |
9c9fddd0 | 53 | #define DstAcc (4<<1) /* Destination Accumulator */ |
a682e354 | 54 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ |
9c9fddd0 | 55 | #define DstMask (7<<1) |
6aa8b732 | 56 | /* Source operand type. */ |
9c9fddd0 GT |
57 | #define SrcNone (0<<4) /* No source operand. */ |
58 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
59 | #define SrcReg (1<<4) /* Register operand. */ | |
60 | #define SrcMem (2<<4) /* Memory operand. */ | |
61 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
62 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
63 | #define SrcImm (5<<4) /* Immediate operand. */ | |
64 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 65 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 66 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 67 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 68 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
341de7e3 | 69 | #define SrcMask (0xf<<4) |
6aa8b732 | 70 | /* Generic ModRM decode. */ |
341de7e3 | 71 | #define ModRM (1<<8) |
6aa8b732 | 72 | /* Destination is only written; never read. */ |
341de7e3 GN |
73 | #define Mov (1<<9) |
74 | #define BitOp (1<<10) | |
75 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
76 | #define String (1<<12) /* String instruction (rep capable) */ |
77 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
78 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
79 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
80 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | |
d8769fed | 81 | /* Misc flags */ |
d380a5e4 | 82 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 83 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 84 | #define No64 (1<<28) |
0dc8d10f GT |
85 | /* Source 2 operand type */ |
86 | #define Src2None (0<<29) | |
87 | #define Src2CL (1<<29) | |
88 | #define Src2ImmByte (2<<29) | |
89 | #define Src2One (3<<29) | |
a5f868bd | 90 | #define Src2Imm16 (4<<29) |
e35b7b9c GN |
91 | #define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be |
92 | in memory and second argument is located | |
93 | immediately after the first one in memory. */ | |
0dc8d10f | 94 | #define Src2Mask (7<<29) |
6aa8b732 | 95 | |
43bb19cd | 96 | enum { |
1d6ad207 | 97 | Group1_80, Group1_81, Group1_82, Group1_83, |
d95058a1 | 98 | Group1A, Group3_Byte, Group3, Group4, Group5, Group7, |
60a29d4e | 99 | Group8, Group9, |
43bb19cd AK |
100 | }; |
101 | ||
45ed60b3 | 102 | static u32 opcode_table[256] = { |
6aa8b732 | 103 | /* 0x00 - 0x07 */ |
d380a5e4 | 104 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 105 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 106 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 107 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 108 | /* 0x08 - 0x0F */ |
d380a5e4 | 109 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 110 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
94677e61 MG |
111 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
112 | ImplicitOps | Stack | No64, 0, | |
6aa8b732 | 113 | /* 0x10 - 0x17 */ |
d380a5e4 | 114 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 115 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 116 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 117 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 118 | /* 0x18 - 0x1F */ |
d380a5e4 | 119 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 120 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 121 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 122 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 123 | /* 0x20 - 0x27 */ |
d380a5e4 | 124 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 125 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
aa3a816b | 126 | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 | 127 | /* 0x28 - 0x2F */ |
d380a5e4 | 128 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
129 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
130 | 0, 0, 0, 0, | |
131 | /* 0x30 - 0x37 */ | |
d380a5e4 | 132 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
133 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
134 | 0, 0, 0, 0, | |
135 | /* 0x38 - 0x3F */ | |
136 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
137 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
8a9fee67 GT |
138 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
139 | 0, 0, | |
d77a2507 | 140 | /* 0x40 - 0x47 */ |
33615aa9 | 141 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 142 | /* 0x48 - 0x4F */ |
33615aa9 | 143 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 144 | /* 0x50 - 0x57 */ |
6e3d5dfb AK |
145 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, |
146 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, | |
7f0aaee0 | 147 | /* 0x58 - 0x5F */ |
6e3d5dfb AK |
148 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, |
149 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, | |
7d316911 | 150 | /* 0x60 - 0x67 */ |
abcf14b5 MG |
151 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
152 | 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , | |
7d316911 NK |
153 | 0, 0, 0, 0, |
154 | /* 0x68 - 0x6F */ | |
91ed7a0e | 155 | SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, |
e70669ab LV |
156 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
157 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 | 158 | /* 0x70 - 0x77 */ |
b2833e3c GN |
159 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
160 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
55bebde4 | 161 | /* 0x78 - 0x7F */ |
b2833e3c GN |
162 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
163 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
6aa8b732 | 164 | /* 0x80 - 0x87 */ |
1d6ad207 AK |
165 | Group | Group1_80, Group | Group1_81, |
166 | Group | Group1_82, Group | Group1_83, | |
6aa8b732 | 167 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
d380a5e4 | 168 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
169 | /* 0x88 - 0x8F */ |
170 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
171 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
38d5bc6d | 172 | DstMem | SrcReg | ModRM | Mov, ModRM | DstReg, |
4257198a | 173 | DstReg | SrcMem | ModRM | Mov, Group | Group1A, |
b13354f8 MG |
174 | /* 0x90 - 0x97 */ |
175 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, | |
176 | /* 0x98 - 0x9F */ | |
d8769fed | 177 | 0, 0, SrcImm | Src2Imm16 | No64, 0, |
0654169e | 178 | ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, |
6aa8b732 | 179 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
180 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
181 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
a682e354 GN |
182 | ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String, |
183 | ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String, | |
6aa8b732 | 184 | /* 0xA8 - 0xAF */ |
a682e354 GN |
185 | 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String, |
186 | ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String, | |
187 | ByteOp | DstDI | String, DstDI | String, | |
a5e2e82b MG |
188 | /* 0xB0 - 0xB7 */ |
189 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
190 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
191 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
192 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
193 | /* 0xB8 - 0xBF */ | |
194 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
195 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
196 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
197 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
6aa8b732 | 198 | /* 0xC0 - 0xC7 */ |
d9413cd7 | 199 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 200 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 201 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 | 202 | /* 0xC8 - 0xCF */ |
e637b823 | 203 | 0, 0, 0, ImplicitOps | Stack, |
d8769fed | 204 | ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps, |
6aa8b732 AK |
205 | /* 0xD0 - 0xD7 */ |
206 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
207 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
208 | 0, 0, 0, 0, | |
209 | /* 0xD8 - 0xDF */ | |
210 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b | 211 | /* 0xE0 - 0xE7 */ |
a6a3034c | 212 | 0, 0, 0, 0, |
cf8f70bf GN |
213 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, |
214 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, | |
098c937b | 215 | /* 0xE8 - 0xEF */ |
d53c4777 | 216 | SrcImm | Stack, SrcImm | ImplicitOps, |
d8769fed | 217 | SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps, |
cf8f70bf GN |
218 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, |
219 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, | |
6aa8b732 AK |
220 | /* 0xF0 - 0xF7 */ |
221 | 0, 0, 0, 0, | |
e92805ac | 222 | ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3, |
6aa8b732 | 223 | /* 0xF8 - 0xFF */ |
b284be57 | 224 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fb4616f4 | 225 | ImplicitOps, ImplicitOps, Group | Group4, Group | Group5, |
6aa8b732 AK |
226 | }; |
227 | ||
45ed60b3 | 228 | static u32 twobyte_table[256] = { |
6aa8b732 | 229 | /* 0x00 - 0x0F */ |
e92805ac GN |
230 | 0, Group | GroupDual | Group7, 0, 0, |
231 | 0, ImplicitOps, ImplicitOps | Priv, 0, | |
232 | ImplicitOps | Priv, ImplicitOps | Priv, 0, 0, | |
233 | 0, ImplicitOps | ModRM, 0, 0, | |
6aa8b732 AK |
234 | /* 0x10 - 0x1F */ |
235 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
236 | /* 0x20 - 0x2F */ | |
e92805ac GN |
237 | ModRM | ImplicitOps | Priv, ModRM | Priv, |
238 | ModRM | ImplicitOps | Priv, ModRM | Priv, | |
239 | 0, 0, 0, 0, | |
6aa8b732 AK |
240 | 0, 0, 0, 0, 0, 0, 0, 0, |
241 | /* 0x30 - 0x3F */ | |
e92805ac GN |
242 | ImplicitOps | Priv, 0, ImplicitOps | Priv, 0, |
243 | ImplicitOps, ImplicitOps | Priv, 0, 0, | |
e99f0507 | 244 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
245 | /* 0x40 - 0x47 */ |
246 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
247 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
248 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
249 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
250 | /* 0x48 - 0x4F */ | |
251 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
252 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
253 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
254 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
255 | /* 0x50 - 0x5F */ | |
256 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
257 | /* 0x60 - 0x6F */ | |
258 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
259 | /* 0x70 - 0x7F */ | |
260 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
261 | /* 0x80 - 0x8F */ | |
b2833e3c GN |
262 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, |
263 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, | |
6aa8b732 AK |
264 | /* 0x90 - 0x9F */ |
265 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
266 | /* 0xA0 - 0xA7 */ | |
0934ac9d MG |
267 | ImplicitOps | Stack, ImplicitOps | Stack, |
268 | 0, DstMem | SrcReg | ModRM | BitOp, | |
9bf8ea42 GT |
269 | DstMem | SrcReg | Src2ImmByte | ModRM, |
270 | DstMem | SrcReg | Src2CL | ModRM, 0, 0, | |
6aa8b732 | 271 | /* 0xA8 - 0xAF */ |
0934ac9d | 272 | ImplicitOps | Stack, ImplicitOps | Stack, |
d380a5e4 | 273 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, |
9bf8ea42 GT |
274 | DstMem | SrcReg | Src2ImmByte | ModRM, |
275 | DstMem | SrcReg | Src2CL | ModRM, | |
276 | ModRM, 0, | |
6aa8b732 | 277 | /* 0xB0 - 0xB7 */ |
d380a5e4 GN |
278 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
279 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
280 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
281 | DstReg | SrcMem16 | ModRM | Mov, | |
282 | /* 0xB8 - 0xBF */ | |
d380a5e4 GN |
283 | 0, 0, |
284 | Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
285 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
286 | DstReg | SrcMem16 | ModRM | Mov, | |
287 | /* 0xC0 - 0xCF */ | |
60a29d4e GN |
288 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, |
289 | 0, 0, 0, Group | GroupDual | Group9, | |
a012e65a | 290 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
291 | /* 0xD0 - 0xDF */ |
292 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
293 | /* 0xE0 - 0xEF */ | |
294 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
295 | /* 0xF0 - 0xFF */ | |
296 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
297 | }; | |
298 | ||
45ed60b3 | 299 | static u32 group_table[] = { |
1d6ad207 | 300 | [Group1_80*8] = |
d380a5e4 GN |
301 | ByteOp | DstMem | SrcImm | ModRM | Lock, |
302 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
303 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
304 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
305 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
306 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
307 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
308 | ByteOp | DstMem | SrcImm | ModRM, | |
1d6ad207 | 309 | [Group1_81*8] = |
d380a5e4 GN |
310 | DstMem | SrcImm | ModRM | Lock, |
311 | DstMem | SrcImm | ModRM | Lock, | |
312 | DstMem | SrcImm | ModRM | Lock, | |
313 | DstMem | SrcImm | ModRM | Lock, | |
314 | DstMem | SrcImm | ModRM | Lock, | |
315 | DstMem | SrcImm | ModRM | Lock, | |
316 | DstMem | SrcImm | ModRM | Lock, | |
317 | DstMem | SrcImm | ModRM, | |
1d6ad207 | 318 | [Group1_82*8] = |
e424e191 GN |
319 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, |
320 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
321 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
322 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
323 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
324 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
325 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
326 | ByteOp | DstMem | SrcImm | ModRM | No64, | |
1d6ad207 | 327 | [Group1_83*8] = |
d380a5e4 GN |
328 | DstMem | SrcImmByte | ModRM | Lock, |
329 | DstMem | SrcImmByte | ModRM | Lock, | |
330 | DstMem | SrcImmByte | ModRM | Lock, | |
331 | DstMem | SrcImmByte | ModRM | Lock, | |
332 | DstMem | SrcImmByte | ModRM | Lock, | |
333 | DstMem | SrcImmByte | ModRM | Lock, | |
334 | DstMem | SrcImmByte | ModRM | Lock, | |
335 | DstMem | SrcImmByte | ModRM, | |
43bb19cd AK |
336 | [Group1A*8] = |
337 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 AK |
338 | [Group3_Byte*8] = |
339 | ByteOp | SrcImm | DstMem | ModRM, 0, | |
340 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
341 | 0, 0, 0, 0, | |
342 | [Group3*8] = | |
41afa025 | 343 | DstMem | SrcImm | ModRM, 0, |
6eb06cb2 | 344 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
7d858a19 | 345 | 0, 0, 0, 0, |
fd60754e AK |
346 | [Group4*8] = |
347 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
348 | 0, 0, 0, 0, 0, 0, | |
349 | [Group5*8] = | |
d19292e4 MG |
350 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
351 | SrcMem | ModRM | Stack, 0, | |
ea79849d GN |
352 | SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps, |
353 | SrcMem | ModRM | Stack, 0, | |
d95058a1 | 354 | [Group7*8] = |
e92805ac | 355 | 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv, |
16286d08 | 356 | SrcNone | ModRM | DstMem | Mov, 0, |
e92805ac | 357 | SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv, |
2db2c2eb GN |
358 | [Group8*8] = |
359 | 0, 0, 0, 0, | |
d380a5e4 GN |
360 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock, |
361 | DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, | |
60a29d4e | 362 | [Group9*8] = |
d380a5e4 | 363 | 0, ImplicitOps | ModRM | Lock, 0, 0, 0, 0, 0, 0, |
e09d082c AK |
364 | }; |
365 | ||
45ed60b3 | 366 | static u32 group2_table[] = { |
d95058a1 | 367 | [Group7*8] = |
835e6b80 | 368 | SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv, |
16286d08 | 369 | SrcNone | ModRM | DstMem | Mov, 0, |
835e6b80 | 370 | SrcMem16 | ModRM | Mov | Priv, 0, |
60a29d4e GN |
371 | [Group9*8] = |
372 | 0, 0, 0, 0, 0, 0, 0, 0, | |
e09d082c AK |
373 | }; |
374 | ||
6aa8b732 | 375 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
376 | #define EFLG_ID (1<<21) |
377 | #define EFLG_VIP (1<<20) | |
378 | #define EFLG_VIF (1<<19) | |
379 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
380 | #define EFLG_VM (1<<17) |
381 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
382 | #define EFLG_IOPL (3<<12) |
383 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
384 | #define EFLG_OF (1<<11) |
385 | #define EFLG_DF (1<<10) | |
b1d86143 | 386 | #define EFLG_IF (1<<9) |
d4c6a154 | 387 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
388 | #define EFLG_SF (1<<7) |
389 | #define EFLG_ZF (1<<6) | |
390 | #define EFLG_AF (1<<4) | |
391 | #define EFLG_PF (1<<2) | |
392 | #define EFLG_CF (1<<0) | |
393 | ||
394 | /* | |
395 | * Instruction emulation: | |
396 | * Most instructions are emulated directly via a fragment of inline assembly | |
397 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
398 | * any modified flags. | |
399 | */ | |
400 | ||
05b3e0c2 | 401 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
402 | #define _LO32 "k" /* force 32-bit operand */ |
403 | #define _STK "%%rsp" /* stack pointer */ | |
404 | #elif defined(__i386__) | |
405 | #define _LO32 "" /* force 32-bit operand */ | |
406 | #define _STK "%%esp" /* stack pointer */ | |
407 | #endif | |
408 | ||
409 | /* | |
410 | * These EFLAGS bits are restored from saved value during emulation, and | |
411 | * any changes are written back to the saved value after emulation. | |
412 | */ | |
413 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
414 | ||
415 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
416 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
417 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
418 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
419 | "push %"_tmp"; " \ | |
420 | "push %"_tmp"; " \ | |
421 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
422 | "andl %"_LO32 _tmp",("_STK"); " \ | |
423 | "pushf; " \ | |
424 | "notl %"_LO32 _tmp"; " \ | |
425 | "andl %"_LO32 _tmp",("_STK"); " \ | |
426 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
427 | "pop %"_tmp"; " \ | |
428 | "orl %"_LO32 _tmp",("_STK"); " \ | |
429 | "popf; " \ | |
430 | "pop %"_sav"; " | |
6aa8b732 AK |
431 | |
432 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
433 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
434 | /* _sav |= EFLAGS & _msk; */ \ | |
435 | "pushf; " \ | |
436 | "pop %"_tmp"; " \ | |
437 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
438 | "orl %"_LO32 _tmp",%"_sav"; " | |
439 | ||
dda96d8f AK |
440 | #ifdef CONFIG_X86_64 |
441 | #define ON64(x) x | |
442 | #else | |
443 | #define ON64(x) | |
444 | #endif | |
445 | ||
6b7ad61f AK |
446 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
447 | do { \ | |
448 | __asm__ __volatile__ ( \ | |
449 | _PRE_EFLAGS("0", "4", "2") \ | |
450 | _op _suffix " %"_x"3,%1; " \ | |
451 | _POST_EFLAGS("0", "4", "2") \ | |
452 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
453 | "=&r" (_tmp) \ | |
454 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 455 | } while (0) |
6b7ad61f AK |
456 | |
457 | ||
6aa8b732 AK |
458 | /* Raw emulation: instruction has two explicit operands. */ |
459 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
460 | do { \ |
461 | unsigned long _tmp; \ | |
462 | \ | |
463 | switch ((_dst).bytes) { \ | |
464 | case 2: \ | |
465 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
466 | break; \ | |
467 | case 4: \ | |
468 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
469 | break; \ | |
470 | case 8: \ | |
471 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
472 | break; \ | |
473 | } \ | |
6aa8b732 AK |
474 | } while (0) |
475 | ||
476 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
477 | do { \ | |
6b7ad61f | 478 | unsigned long _tmp; \ |
d77c26fc | 479 | switch ((_dst).bytes) { \ |
6aa8b732 | 480 | case 1: \ |
6b7ad61f | 481 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
482 | break; \ |
483 | default: \ | |
484 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
485 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
486 | break; \ | |
487 | } \ | |
488 | } while (0) | |
489 | ||
490 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
491 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
492 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
493 | "b", "c", "b", "c", "b", "c", "b", "c") | |
494 | ||
495 | /* Source operand is byte, word, long or quad sized. */ | |
496 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
497 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
498 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
499 | ||
500 | /* Source operand is word, long or quad sized. */ | |
501 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
502 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
503 | "w", "r", _LO32, "r", "", "r") | |
504 | ||
d175226a GT |
505 | /* Instruction has three operands and one operand is stored in ECX register */ |
506 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
507 | do { \ | |
508 | unsigned long _tmp; \ | |
509 | _type _clv = (_cl).val; \ | |
510 | _type _srcv = (_src).val; \ | |
511 | _type _dstv = (_dst).val; \ | |
512 | \ | |
513 | __asm__ __volatile__ ( \ | |
514 | _PRE_EFLAGS("0", "5", "2") \ | |
515 | _op _suffix " %4,%1 \n" \ | |
516 | _POST_EFLAGS("0", "5", "2") \ | |
517 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
518 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
519 | ); \ | |
520 | \ | |
521 | (_cl).val = (unsigned long) _clv; \ | |
522 | (_src).val = (unsigned long) _srcv; \ | |
523 | (_dst).val = (unsigned long) _dstv; \ | |
524 | } while (0) | |
525 | ||
526 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
527 | do { \ | |
528 | switch ((_dst).bytes) { \ | |
529 | case 2: \ | |
530 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
531 | "w", unsigned short); \ | |
532 | break; \ | |
533 | case 4: \ | |
534 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
535 | "l", unsigned int); \ | |
536 | break; \ | |
537 | case 8: \ | |
538 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
539 | "q", unsigned long)); \ | |
540 | break; \ | |
541 | } \ | |
542 | } while (0) | |
543 | ||
dda96d8f | 544 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
545 | do { \ |
546 | unsigned long _tmp; \ | |
547 | \ | |
dda96d8f AK |
548 | __asm__ __volatile__ ( \ |
549 | _PRE_EFLAGS("0", "3", "2") \ | |
550 | _op _suffix " %1; " \ | |
551 | _POST_EFLAGS("0", "3", "2") \ | |
552 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
553 | "=&r" (_tmp) \ | |
554 | : "i" (EFLAGS_MASK)); \ | |
555 | } while (0) | |
556 | ||
557 | /* Instruction has only one explicit operand (no source operand). */ | |
558 | #define emulate_1op(_op, _dst, _eflags) \ | |
559 | do { \ | |
d77c26fc | 560 | switch ((_dst).bytes) { \ |
dda96d8f AK |
561 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
562 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
563 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
564 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
565 | } \ |
566 | } while (0) | |
567 | ||
6aa8b732 AK |
568 | /* Fetch next part of the instruction being emulated. */ |
569 | #define insn_fetch(_type, _size, _eip) \ | |
570 | ({ unsigned long _x; \ | |
62266869 | 571 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 572 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
573 | goto done; \ |
574 | (_eip) += (_size); \ | |
575 | (_type)_x; \ | |
576 | }) | |
577 | ||
ddcb2885 HH |
578 | static inline unsigned long ad_mask(struct decode_cache *c) |
579 | { | |
580 | return (1UL << (c->ad_bytes << 3)) - 1; | |
581 | } | |
582 | ||
6aa8b732 | 583 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
584 | static inline unsigned long |
585 | address_mask(struct decode_cache *c, unsigned long reg) | |
586 | { | |
587 | if (c->ad_bytes == sizeof(unsigned long)) | |
588 | return reg; | |
589 | else | |
590 | return reg & ad_mask(c); | |
591 | } | |
592 | ||
593 | static inline unsigned long | |
594 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
595 | { | |
596 | return base + address_mask(c, reg); | |
597 | } | |
598 | ||
7a957275 HH |
599 | static inline void |
600 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
601 | { | |
602 | if (c->ad_bytes == sizeof(unsigned long)) | |
603 | *reg += inc; | |
604 | else | |
605 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
606 | } | |
6aa8b732 | 607 | |
7a957275 HH |
608 | static inline void jmp_rel(struct decode_cache *c, int rel) |
609 | { | |
610 | register_address_increment(c, &c->eip, rel); | |
611 | } | |
098c937b | 612 | |
7a5b56df AK |
613 | static void set_seg_override(struct decode_cache *c, int seg) |
614 | { | |
615 | c->has_seg_override = true; | |
616 | c->seg_override = seg; | |
617 | } | |
618 | ||
619 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) | |
620 | { | |
621 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
622 | return 0; | |
623 | ||
624 | return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg); | |
625 | } | |
626 | ||
627 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
628 | struct decode_cache *c) | |
629 | { | |
630 | if (!c->has_seg_override) | |
631 | return 0; | |
632 | ||
633 | return seg_base(ctxt, c->seg_override); | |
634 | } | |
635 | ||
636 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt) | |
637 | { | |
638 | return seg_base(ctxt, VCPU_SREG_ES); | |
639 | } | |
640 | ||
641 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt) | |
642 | { | |
643 | return seg_base(ctxt, VCPU_SREG_SS); | |
644 | } | |
645 | ||
62266869 AK |
646 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
647 | struct x86_emulate_ops *ops, | |
648 | unsigned long linear, u8 *dest) | |
649 | { | |
650 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
651 | int rc; | |
652 | int size; | |
653 | ||
654 | if (linear < fc->start || linear >= fc->end) { | |
655 | size = min(15UL, PAGE_SIZE - offset_in_page(linear)); | |
1871c602 | 656 | rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL); |
3e2815e9 | 657 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
658 | return rc; |
659 | fc->start = linear; | |
660 | fc->end = linear + size; | |
661 | } | |
662 | *dest = fc->data[linear - fc->start]; | |
3e2815e9 | 663 | return X86EMUL_CONTINUE; |
62266869 AK |
664 | } |
665 | ||
666 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
667 | struct x86_emulate_ops *ops, | |
668 | unsigned long eip, void *dest, unsigned size) | |
669 | { | |
3e2815e9 | 670 | int rc; |
62266869 | 671 | |
eb3c79e6 | 672 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 673 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 674 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
675 | eip += ctxt->cs_base; |
676 | while (size--) { | |
677 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 678 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
679 | return rc; |
680 | } | |
3e2815e9 | 681 | return X86EMUL_CONTINUE; |
62266869 AK |
682 | } |
683 | ||
1e3c5cb0 RR |
684 | /* |
685 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
686 | * pointer into the block that addresses the relevant register. | |
687 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
688 | */ | |
689 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
690 | int highbyte_regs) | |
6aa8b732 AK |
691 | { |
692 | void *p; | |
693 | ||
694 | p = ®s[modrm_reg]; | |
695 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
696 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
697 | return p; | |
698 | } | |
699 | ||
700 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
701 | struct x86_emulate_ops *ops, | |
702 | void *ptr, | |
703 | u16 *size, unsigned long *address, int op_bytes) | |
704 | { | |
705 | int rc; | |
706 | ||
707 | if (op_bytes == 2) | |
708 | op_bytes = 3; | |
709 | *address = 0; | |
cebff02b | 710 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
1871c602 | 711 | ctxt->vcpu, NULL); |
1b30eaa8 | 712 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 713 | return rc; |
cebff02b | 714 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
1871c602 | 715 | ctxt->vcpu, NULL); |
6aa8b732 AK |
716 | return rc; |
717 | } | |
718 | ||
bbe9abbd NK |
719 | static int test_cc(unsigned int condition, unsigned int flags) |
720 | { | |
721 | int rc = 0; | |
722 | ||
723 | switch ((condition & 15) >> 1) { | |
724 | case 0: /* o */ | |
725 | rc |= (flags & EFLG_OF); | |
726 | break; | |
727 | case 1: /* b/c/nae */ | |
728 | rc |= (flags & EFLG_CF); | |
729 | break; | |
730 | case 2: /* z/e */ | |
731 | rc |= (flags & EFLG_ZF); | |
732 | break; | |
733 | case 3: /* be/na */ | |
734 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
735 | break; | |
736 | case 4: /* s */ | |
737 | rc |= (flags & EFLG_SF); | |
738 | break; | |
739 | case 5: /* p/pe */ | |
740 | rc |= (flags & EFLG_PF); | |
741 | break; | |
742 | case 7: /* le/ng */ | |
743 | rc |= (flags & EFLG_ZF); | |
744 | /* fall through */ | |
745 | case 6: /* l/nge */ | |
746 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
747 | break; | |
748 | } | |
749 | ||
750 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
751 | return (!!rc ^ (condition & 1)); | |
752 | } | |
753 | ||
3c118e24 AK |
754 | static void decode_register_operand(struct operand *op, |
755 | struct decode_cache *c, | |
3c118e24 AK |
756 | int inhibit_bytereg) |
757 | { | |
33615aa9 | 758 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 759 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
760 | |
761 | if (!(c->d & ModRM)) | |
762 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
763 | op->type = OP_REG; |
764 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 765 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
766 | op->val = *(u8 *)op->ptr; |
767 | op->bytes = 1; | |
768 | } else { | |
33615aa9 | 769 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
770 | op->bytes = c->op_bytes; |
771 | switch (op->bytes) { | |
772 | case 2: | |
773 | op->val = *(u16 *)op->ptr; | |
774 | break; | |
775 | case 4: | |
776 | op->val = *(u32 *)op->ptr; | |
777 | break; | |
778 | case 8: | |
779 | op->val = *(u64 *) op->ptr; | |
780 | break; | |
781 | } | |
782 | } | |
783 | op->orig_val = op->val; | |
784 | } | |
785 | ||
1c73ef66 AK |
786 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
787 | struct x86_emulate_ops *ops) | |
788 | { | |
789 | struct decode_cache *c = &ctxt->decode; | |
790 | u8 sib; | |
f5b4edcd | 791 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 792 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
793 | |
794 | if (c->rex_prefix) { | |
795 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
796 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
797 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
798 | } | |
799 | ||
800 | c->modrm = insn_fetch(u8, 1, c->eip); | |
801 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
802 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
803 | c->modrm_rm |= (c->modrm & 0x07); | |
804 | c->modrm_ea = 0; | |
805 | c->use_modrm_ea = 1; | |
806 | ||
807 | if (c->modrm_mod == 3) { | |
107d6d2e AK |
808 | c->modrm_ptr = decode_register(c->modrm_rm, |
809 | c->regs, c->d & ByteOp); | |
810 | c->modrm_val = *(unsigned long *)c->modrm_ptr; | |
1c73ef66 AK |
811 | return rc; |
812 | } | |
813 | ||
814 | if (c->ad_bytes == 2) { | |
815 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
816 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
817 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
818 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
819 | ||
820 | /* 16-bit ModR/M decode. */ | |
821 | switch (c->modrm_mod) { | |
822 | case 0: | |
823 | if (c->modrm_rm == 6) | |
824 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
825 | break; | |
826 | case 1: | |
827 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
828 | break; | |
829 | case 2: | |
830 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
831 | break; | |
832 | } | |
833 | switch (c->modrm_rm) { | |
834 | case 0: | |
835 | c->modrm_ea += bx + si; | |
836 | break; | |
837 | case 1: | |
838 | c->modrm_ea += bx + di; | |
839 | break; | |
840 | case 2: | |
841 | c->modrm_ea += bp + si; | |
842 | break; | |
843 | case 3: | |
844 | c->modrm_ea += bp + di; | |
845 | break; | |
846 | case 4: | |
847 | c->modrm_ea += si; | |
848 | break; | |
849 | case 5: | |
850 | c->modrm_ea += di; | |
851 | break; | |
852 | case 6: | |
853 | if (c->modrm_mod != 0) | |
854 | c->modrm_ea += bp; | |
855 | break; | |
856 | case 7: | |
857 | c->modrm_ea += bx; | |
858 | break; | |
859 | } | |
860 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
861 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
7a5b56df AK |
862 | if (!c->has_seg_override) |
863 | set_seg_override(c, VCPU_SREG_SS); | |
1c73ef66 AK |
864 | c->modrm_ea = (u16)c->modrm_ea; |
865 | } else { | |
866 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 867 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
868 | sib = insn_fetch(u8, 1, c->eip); |
869 | index_reg |= (sib >> 3) & 7; | |
870 | base_reg |= sib & 7; | |
871 | scale = sib >> 6; | |
872 | ||
dc71d0f1 AK |
873 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
874 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
875 | else | |
1c73ef66 | 876 | c->modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 877 | if (index_reg != 4) |
1c73ef66 | 878 | c->modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
879 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
880 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 881 | c->rip_relative = 1; |
84411d85 | 882 | } else |
1c73ef66 | 883 | c->modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
884 | switch (c->modrm_mod) { |
885 | case 0: | |
886 | if (c->modrm_rm == 5) | |
887 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
888 | break; | |
889 | case 1: | |
890 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
891 | break; | |
892 | case 2: | |
893 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
894 | break; | |
895 | } | |
896 | } | |
1c73ef66 AK |
897 | done: |
898 | return rc; | |
899 | } | |
900 | ||
901 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
902 | struct x86_emulate_ops *ops) | |
903 | { | |
904 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 905 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
906 | |
907 | switch (c->ad_bytes) { | |
908 | case 2: | |
909 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
910 | break; | |
911 | case 4: | |
912 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
913 | break; | |
914 | case 8: | |
915 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
916 | break; | |
917 | } | |
918 | done: | |
919 | return rc; | |
920 | } | |
921 | ||
6aa8b732 | 922 | int |
8b4caf66 | 923 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 924 | { |
e4e03ded | 925 | struct decode_cache *c = &ctxt->decode; |
3e2815e9 | 926 | int rc = X86EMUL_CONTINUE; |
6aa8b732 | 927 | int mode = ctxt->mode; |
e09d082c | 928 | int def_op_bytes, def_ad_bytes, group; |
6aa8b732 AK |
929 | |
930 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 931 | |
e4e03ded | 932 | memset(c, 0, sizeof(struct decode_cache)); |
063db061 | 933 | c->eip = ctxt->eip; |
7a5b56df | 934 | ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS); |
ad312c7c | 935 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
6aa8b732 AK |
936 | |
937 | switch (mode) { | |
938 | case X86EMUL_MODE_REAL: | |
a0044755 | 939 | case X86EMUL_MODE_VM86: |
6aa8b732 | 940 | case X86EMUL_MODE_PROT16: |
f21b8bf4 | 941 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
942 | break; |
943 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 944 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 945 | break; |
05b3e0c2 | 946 | #ifdef CONFIG_X86_64 |
6aa8b732 | 947 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
948 | def_op_bytes = 4; |
949 | def_ad_bytes = 8; | |
6aa8b732 AK |
950 | break; |
951 | #endif | |
952 | default: | |
953 | return -1; | |
954 | } | |
955 | ||
f21b8bf4 AK |
956 | c->op_bytes = def_op_bytes; |
957 | c->ad_bytes = def_ad_bytes; | |
958 | ||
6aa8b732 | 959 | /* Legacy prefixes. */ |
b4c6abfe | 960 | for (;;) { |
e4e03ded | 961 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 962 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
963 | /* switch between 2/4 bytes */ |
964 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
965 | break; |
966 | case 0x67: /* address-size override */ | |
967 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 968 | /* switch between 4/8 bytes */ |
f21b8bf4 | 969 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 970 | else |
e4e03ded | 971 | /* switch between 2/4 bytes */ |
f21b8bf4 | 972 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 | 973 | break; |
7a5b56df | 974 | case 0x26: /* ES override */ |
6aa8b732 | 975 | case 0x2e: /* CS override */ |
7a5b56df | 976 | case 0x36: /* SS override */ |
6aa8b732 | 977 | case 0x3e: /* DS override */ |
7a5b56df | 978 | set_seg_override(c, (c->b >> 3) & 3); |
6aa8b732 AK |
979 | break; |
980 | case 0x64: /* FS override */ | |
6aa8b732 | 981 | case 0x65: /* GS override */ |
7a5b56df | 982 | set_seg_override(c, c->b & 7); |
6aa8b732 | 983 | break; |
b4c6abfe LV |
984 | case 0x40 ... 0x4f: /* REX */ |
985 | if (mode != X86EMUL_MODE_PROT64) | |
986 | goto done_prefixes; | |
33615aa9 | 987 | c->rex_prefix = c->b; |
b4c6abfe | 988 | continue; |
6aa8b732 | 989 | case 0xf0: /* LOCK */ |
e4e03ded | 990 | c->lock_prefix = 1; |
6aa8b732 | 991 | break; |
ae6200ba | 992 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
993 | c->rep_prefix = REPNE_PREFIX; |
994 | break; | |
6aa8b732 | 995 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 996 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 997 | break; |
6aa8b732 AK |
998 | default: |
999 | goto done_prefixes; | |
1000 | } | |
b4c6abfe LV |
1001 | |
1002 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
1003 | ||
33615aa9 | 1004 | c->rex_prefix = 0; |
6aa8b732 AK |
1005 | } |
1006 | ||
1007 | done_prefixes: | |
1008 | ||
1009 | /* REX prefix. */ | |
1c73ef66 | 1010 | if (c->rex_prefix) |
33615aa9 | 1011 | if (c->rex_prefix & 8) |
e4e03ded | 1012 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
1013 | |
1014 | /* Opcode byte(s). */ | |
e4e03ded LV |
1015 | c->d = opcode_table[c->b]; |
1016 | if (c->d == 0) { | |
6aa8b732 | 1017 | /* Two-byte opcode? */ |
e4e03ded LV |
1018 | if (c->b == 0x0f) { |
1019 | c->twobyte = 1; | |
1020 | c->b = insn_fetch(u8, 1, c->eip); | |
1021 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 1022 | } |
e09d082c | 1023 | } |
6aa8b732 | 1024 | |
e09d082c AK |
1025 | if (c->d & Group) { |
1026 | group = c->d & GroupMask; | |
1027 | c->modrm = insn_fetch(u8, 1, c->eip); | |
1028 | --c->eip; | |
1029 | ||
1030 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
1031 | if ((c->d & GroupDual) && (c->modrm >> 6) == 3) | |
1032 | c->d = group2_table[group]; | |
1033 | else | |
1034 | c->d = group_table[group]; | |
1035 | } | |
1036 | ||
1037 | /* Unrecognised? */ | |
1038 | if (c->d == 0) { | |
1039 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1040 | return -1; | |
6aa8b732 AK |
1041 | } |
1042 | ||
6e3d5dfb AK |
1043 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
1044 | c->op_bytes = 8; | |
1045 | ||
6aa8b732 | 1046 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
1047 | if (c->d & ModRM) |
1048 | rc = decode_modrm(ctxt, ops); | |
1049 | else if (c->d & MemAbs) | |
1050 | rc = decode_abs(ctxt, ops); | |
3e2815e9 | 1051 | if (rc != X86EMUL_CONTINUE) |
1c73ef66 | 1052 | goto done; |
6aa8b732 | 1053 | |
7a5b56df AK |
1054 | if (!c->has_seg_override) |
1055 | set_seg_override(c, VCPU_SREG_DS); | |
c7e75a3d | 1056 | |
7a5b56df AK |
1057 | if (!(!c->twobyte && c->b == 0x8d)) |
1058 | c->modrm_ea += seg_override_base(ctxt, c); | |
c7e75a3d AK |
1059 | |
1060 | if (c->ad_bytes != 8) | |
1061 | c->modrm_ea = (u32)c->modrm_ea; | |
69f55cb1 GN |
1062 | |
1063 | if (c->rip_relative) | |
1064 | c->modrm_ea += c->eip; | |
1065 | ||
6aa8b732 AK |
1066 | /* |
1067 | * Decode and fetch the source operand: register, memory | |
1068 | * or immediate. | |
1069 | */ | |
e4e03ded | 1070 | switch (c->d & SrcMask) { |
6aa8b732 AK |
1071 | case SrcNone: |
1072 | break; | |
1073 | case SrcReg: | |
9f1ef3f8 | 1074 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
1075 | break; |
1076 | case SrcMem16: | |
e4e03ded | 1077 | c->src.bytes = 2; |
6aa8b732 AK |
1078 | goto srcmem_common; |
1079 | case SrcMem32: | |
e4e03ded | 1080 | c->src.bytes = 4; |
6aa8b732 AK |
1081 | goto srcmem_common; |
1082 | case SrcMem: | |
e4e03ded LV |
1083 | c->src.bytes = (c->d & ByteOp) ? 1 : |
1084 | c->op_bytes; | |
b85b9ee9 | 1085 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 1086 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 1087 | break; |
d77c26fc | 1088 | srcmem_common: |
4e62417b AJ |
1089 | /* |
1090 | * For instructions with a ModR/M byte, switch to register | |
1091 | * access if Mod = 3. | |
1092 | */ | |
e4e03ded LV |
1093 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1094 | c->src.type = OP_REG; | |
66b85505 | 1095 | c->src.val = c->modrm_val; |
107d6d2e | 1096 | c->src.ptr = c->modrm_ptr; |
4e62417b AJ |
1097 | break; |
1098 | } | |
e4e03ded | 1099 | c->src.type = OP_MEM; |
69f55cb1 GN |
1100 | c->src.ptr = (unsigned long *)c->modrm_ea; |
1101 | c->src.val = 0; | |
6aa8b732 AK |
1102 | break; |
1103 | case SrcImm: | |
c9eaf20f | 1104 | case SrcImmU: |
e4e03ded LV |
1105 | c->src.type = OP_IMM; |
1106 | c->src.ptr = (unsigned long *)c->eip; | |
1107 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1108 | if (c->src.bytes == 8) | |
1109 | c->src.bytes = 4; | |
6aa8b732 | 1110 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1111 | switch (c->src.bytes) { |
6aa8b732 | 1112 | case 1: |
e4e03ded | 1113 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1114 | break; |
1115 | case 2: | |
e4e03ded | 1116 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1117 | break; |
1118 | case 4: | |
e4e03ded | 1119 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1120 | break; |
1121 | } | |
c9eaf20f AK |
1122 | if ((c->d & SrcMask) == SrcImmU) { |
1123 | switch (c->src.bytes) { | |
1124 | case 1: | |
1125 | c->src.val &= 0xff; | |
1126 | break; | |
1127 | case 2: | |
1128 | c->src.val &= 0xffff; | |
1129 | break; | |
1130 | case 4: | |
1131 | c->src.val &= 0xffffffff; | |
1132 | break; | |
1133 | } | |
1134 | } | |
6aa8b732 AK |
1135 | break; |
1136 | case SrcImmByte: | |
341de7e3 | 1137 | case SrcImmUByte: |
e4e03ded LV |
1138 | c->src.type = OP_IMM; |
1139 | c->src.ptr = (unsigned long *)c->eip; | |
1140 | c->src.bytes = 1; | |
341de7e3 GN |
1141 | if ((c->d & SrcMask) == SrcImmByte) |
1142 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1143 | else | |
1144 | c->src.val = insn_fetch(u8, 1, c->eip); | |
6aa8b732 | 1145 | break; |
bfcadf83 GT |
1146 | case SrcOne: |
1147 | c->src.bytes = 1; | |
1148 | c->src.val = 1; | |
1149 | break; | |
a682e354 GN |
1150 | case SrcSI: |
1151 | c->src.type = OP_MEM; | |
1152 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1153 | c->src.ptr = (unsigned long *) | |
1154 | register_address(c, seg_override_base(ctxt, c), | |
1155 | c->regs[VCPU_REGS_RSI]); | |
1156 | c->src.val = 0; | |
1157 | break; | |
6aa8b732 AK |
1158 | } |
1159 | ||
0dc8d10f GT |
1160 | /* |
1161 | * Decode and fetch the second source operand: register, memory | |
1162 | * or immediate. | |
1163 | */ | |
1164 | switch (c->d & Src2Mask) { | |
1165 | case Src2None: | |
1166 | break; | |
1167 | case Src2CL: | |
1168 | c->src2.bytes = 1; | |
1169 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
1170 | break; | |
1171 | case Src2ImmByte: | |
1172 | c->src2.type = OP_IMM; | |
1173 | c->src2.ptr = (unsigned long *)c->eip; | |
1174 | c->src2.bytes = 1; | |
1175 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
1176 | break; | |
a5f868bd GN |
1177 | case Src2Imm16: |
1178 | c->src2.type = OP_IMM; | |
1179 | c->src2.ptr = (unsigned long *)c->eip; | |
1180 | c->src2.bytes = 2; | |
1181 | c->src2.val = insn_fetch(u16, 2, c->eip); | |
1182 | break; | |
0dc8d10f GT |
1183 | case Src2One: |
1184 | c->src2.bytes = 1; | |
1185 | c->src2.val = 1; | |
1186 | break; | |
e35b7b9c | 1187 | case Src2Mem16: |
e35b7b9c | 1188 | c->src2.type = OP_MEM; |
69f55cb1 GN |
1189 | c->src2.bytes = 2; |
1190 | c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes); | |
1191 | c->src2.val = 0; | |
e35b7b9c | 1192 | break; |
0dc8d10f GT |
1193 | } |
1194 | ||
038e51de | 1195 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1196 | switch (c->d & DstMask) { |
038e51de AK |
1197 | case ImplicitOps: |
1198 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1199 | return 0; |
038e51de | 1200 | case DstReg: |
9f1ef3f8 | 1201 | decode_register_operand(&c->dst, c, |
3c118e24 | 1202 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1203 | break; |
1204 | case DstMem: | |
e4e03ded | 1205 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
89c69638 | 1206 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
e4e03ded | 1207 | c->dst.type = OP_REG; |
66b85505 | 1208 | c->dst.val = c->dst.orig_val = c->modrm_val; |
107d6d2e | 1209 | c->dst.ptr = c->modrm_ptr; |
4e62417b AJ |
1210 | break; |
1211 | } | |
8b4caf66 | 1212 | c->dst.type = OP_MEM; |
69f55cb1 GN |
1213 | c->dst.ptr = (unsigned long *)c->modrm_ea; |
1214 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1215 | c->dst.val = 0; | |
1216 | if (c->d & BitOp) { | |
1217 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
1218 | ||
1219 | c->dst.ptr = (void *)c->dst.ptr + | |
1220 | (c->src.val & mask) / 8; | |
1221 | } | |
8b4caf66 | 1222 | break; |
9c9fddd0 GT |
1223 | case DstAcc: |
1224 | c->dst.type = OP_REG; | |
d6d367d6 | 1225 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
9c9fddd0 | 1226 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; |
d6d367d6 | 1227 | switch (c->dst.bytes) { |
9c9fddd0 GT |
1228 | case 1: |
1229 | c->dst.val = *(u8 *)c->dst.ptr; | |
1230 | break; | |
1231 | case 2: | |
1232 | c->dst.val = *(u16 *)c->dst.ptr; | |
1233 | break; | |
1234 | case 4: | |
1235 | c->dst.val = *(u32 *)c->dst.ptr; | |
1236 | break; | |
d6d367d6 GN |
1237 | case 8: |
1238 | c->dst.val = *(u64 *)c->dst.ptr; | |
1239 | break; | |
9c9fddd0 GT |
1240 | } |
1241 | c->dst.orig_val = c->dst.val; | |
1242 | break; | |
a682e354 GN |
1243 | case DstDI: |
1244 | c->dst.type = OP_MEM; | |
1245 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1246 | c->dst.ptr = (unsigned long *) | |
1247 | register_address(c, es_base(ctxt), | |
1248 | c->regs[VCPU_REGS_RDI]); | |
1249 | c->dst.val = 0; | |
1250 | break; | |
8b4caf66 LV |
1251 | } |
1252 | ||
1253 | done: | |
1254 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1255 | } | |
1256 | ||
38ba30ba GN |
1257 | static u32 desc_limit_scaled(struct desc_struct *desc) |
1258 | { | |
1259 | u32 limit = get_desc_limit(desc); | |
1260 | ||
1261 | return desc->g ? (limit << 12) | 0xfff : limit; | |
1262 | } | |
1263 | ||
1264 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, | |
1265 | struct x86_emulate_ops *ops, | |
1266 | u16 selector, struct desc_ptr *dt) | |
1267 | { | |
1268 | if (selector & 1 << 2) { | |
1269 | struct desc_struct desc; | |
1270 | memset (dt, 0, sizeof *dt); | |
1271 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
1272 | return; | |
1273 | ||
1274 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ | |
1275 | dt->address = get_desc_base(&desc); | |
1276 | } else | |
1277 | ops->get_gdt(dt, ctxt->vcpu); | |
1278 | } | |
1279 | ||
1280 | /* allowed just for 8 bytes segments */ | |
1281 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1282 | struct x86_emulate_ops *ops, | |
1283 | u16 selector, struct desc_struct *desc) | |
1284 | { | |
1285 | struct desc_ptr dt; | |
1286 | u16 index = selector >> 3; | |
1287 | int ret; | |
1288 | u32 err; | |
1289 | ulong addr; | |
1290 | ||
1291 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1292 | ||
1293 | if (dt.size < index * 8 + 7) { | |
1294 | kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); | |
1295 | return X86EMUL_PROPAGATE_FAULT; | |
1296 | } | |
1297 | addr = dt.address + index * 8; | |
1298 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1299 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
1300 | kvm_inject_page_fault(ctxt->vcpu, addr, err); | |
1301 | ||
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | /* allowed just for 8 bytes segments */ | |
1306 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1307 | struct x86_emulate_ops *ops, | |
1308 | u16 selector, struct desc_struct *desc) | |
1309 | { | |
1310 | struct desc_ptr dt; | |
1311 | u16 index = selector >> 3; | |
1312 | u32 err; | |
1313 | ulong addr; | |
1314 | int ret; | |
1315 | ||
1316 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1317 | ||
1318 | if (dt.size < index * 8 + 7) { | |
1319 | kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); | |
1320 | return X86EMUL_PROPAGATE_FAULT; | |
1321 | } | |
1322 | ||
1323 | addr = dt.address + index * 8; | |
1324 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1325 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
1326 | kvm_inject_page_fault(ctxt->vcpu, addr, err); | |
1327 | ||
1328 | return ret; | |
1329 | } | |
1330 | ||
1331 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1332 | struct x86_emulate_ops *ops, | |
1333 | u16 selector, int seg) | |
1334 | { | |
1335 | struct desc_struct seg_desc; | |
1336 | u8 dpl, rpl, cpl; | |
1337 | unsigned err_vec = GP_VECTOR; | |
1338 | u32 err_code = 0; | |
1339 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1340 | int ret; | |
1341 | ||
1342 | memset(&seg_desc, 0, sizeof seg_desc); | |
1343 | ||
1344 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) | |
1345 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1346 | /* set real mode segment descriptor */ | |
1347 | set_desc_base(&seg_desc, selector << 4); | |
1348 | set_desc_limit(&seg_desc, 0xffff); | |
1349 | seg_desc.type = 3; | |
1350 | seg_desc.p = 1; | |
1351 | seg_desc.s = 1; | |
1352 | goto load; | |
1353 | } | |
1354 | ||
1355 | /* NULL selector is not valid for TR, CS and SS */ | |
1356 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1357 | && null_selector) | |
1358 | goto exception; | |
1359 | ||
1360 | /* TR should be in GDT only */ | |
1361 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1362 | goto exception; | |
1363 | ||
1364 | if (null_selector) /* for NULL selector skip all following checks */ | |
1365 | goto load; | |
1366 | ||
1367 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1368 | if (ret != X86EMUL_CONTINUE) | |
1369 | return ret; | |
1370 | ||
1371 | err_code = selector & 0xfffc; | |
1372 | err_vec = GP_VECTOR; | |
1373 | ||
1374 | /* can't load system descriptor into segment selecor */ | |
1375 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1376 | goto exception; | |
1377 | ||
1378 | if (!seg_desc.p) { | |
1379 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1380 | goto exception; | |
1381 | } | |
1382 | ||
1383 | rpl = selector & 3; | |
1384 | dpl = seg_desc.dpl; | |
1385 | cpl = ops->cpl(ctxt->vcpu); | |
1386 | ||
1387 | switch (seg) { | |
1388 | case VCPU_SREG_SS: | |
1389 | /* | |
1390 | * segment is not a writable data segment or segment | |
1391 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1392 | */ | |
1393 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1394 | goto exception; | |
1395 | break; | |
1396 | case VCPU_SREG_CS: | |
1397 | if (!(seg_desc.type & 8)) | |
1398 | goto exception; | |
1399 | ||
1400 | if (seg_desc.type & 4) { | |
1401 | /* conforming */ | |
1402 | if (dpl > cpl) | |
1403 | goto exception; | |
1404 | } else { | |
1405 | /* nonconforming */ | |
1406 | if (rpl > cpl || dpl != cpl) | |
1407 | goto exception; | |
1408 | } | |
1409 | /* CS(RPL) <- CPL */ | |
1410 | selector = (selector & 0xfffc) | cpl; | |
1411 | break; | |
1412 | case VCPU_SREG_TR: | |
1413 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1414 | goto exception; | |
1415 | break; | |
1416 | case VCPU_SREG_LDTR: | |
1417 | if (seg_desc.s || seg_desc.type != 2) | |
1418 | goto exception; | |
1419 | break; | |
1420 | default: /* DS, ES, FS, or GS */ | |
1421 | /* | |
1422 | * segment is not a data or readable code segment or | |
1423 | * ((segment is a data or nonconforming code segment) | |
1424 | * and (both RPL and CPL > DPL)) | |
1425 | */ | |
1426 | if ((seg_desc.type & 0xa) == 0x8 || | |
1427 | (((seg_desc.type & 0xc) != 0xc) && | |
1428 | (rpl > dpl && cpl > dpl))) | |
1429 | goto exception; | |
1430 | break; | |
1431 | } | |
1432 | ||
1433 | if (seg_desc.s) { | |
1434 | /* mark segment as accessed */ | |
1435 | seg_desc.type |= 1; | |
1436 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1437 | if (ret != X86EMUL_CONTINUE) | |
1438 | return ret; | |
1439 | } | |
1440 | load: | |
1441 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1442 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1443 | return X86EMUL_CONTINUE; | |
1444 | exception: | |
1445 | kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code); | |
1446 | return X86EMUL_PROPAGATE_FAULT; | |
1447 | } | |
1448 | ||
8cdbd2c9 LV |
1449 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
1450 | { | |
1451 | struct decode_cache *c = &ctxt->decode; | |
1452 | ||
1453 | c->dst.type = OP_MEM; | |
1454 | c->dst.bytes = c->op_bytes; | |
1455 | c->dst.val = c->src.val; | |
7a957275 | 1456 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
7a5b56df | 1457 | c->dst.ptr = (void *) register_address(c, ss_base(ctxt), |
8cdbd2c9 LV |
1458 | c->regs[VCPU_REGS_RSP]); |
1459 | } | |
1460 | ||
faa5a3ae | 1461 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
350f69dc AK |
1462 | struct x86_emulate_ops *ops, |
1463 | void *dest, int len) | |
8cdbd2c9 LV |
1464 | { |
1465 | struct decode_cache *c = &ctxt->decode; | |
1466 | int rc; | |
1467 | ||
781d0edc AK |
1468 | rc = ops->read_emulated(register_address(c, ss_base(ctxt), |
1469 | c->regs[VCPU_REGS_RSP]), | |
350f69dc | 1470 | dest, len, ctxt->vcpu); |
b60d513c | 1471 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1472 | return rc; |
1473 | ||
350f69dc | 1474 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); |
faa5a3ae AK |
1475 | return rc; |
1476 | } | |
8cdbd2c9 | 1477 | |
d4c6a154 GN |
1478 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1479 | struct x86_emulate_ops *ops, | |
1480 | void *dest, int len) | |
1481 | { | |
1482 | int rc; | |
1483 | unsigned long val, change_mask; | |
1484 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1485 | int cpl = ops->cpl(ctxt->vcpu); |
d4c6a154 GN |
1486 | |
1487 | rc = emulate_pop(ctxt, ops, &val, len); | |
1488 | if (rc != X86EMUL_CONTINUE) | |
1489 | return rc; | |
1490 | ||
1491 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF | |
1492 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
1493 | ||
1494 | switch(ctxt->mode) { | |
1495 | case X86EMUL_MODE_PROT64: | |
1496 | case X86EMUL_MODE_PROT32: | |
1497 | case X86EMUL_MODE_PROT16: | |
1498 | if (cpl == 0) | |
1499 | change_mask |= EFLG_IOPL; | |
1500 | if (cpl <= iopl) | |
1501 | change_mask |= EFLG_IF; | |
1502 | break; | |
1503 | case X86EMUL_MODE_VM86: | |
1504 | if (iopl < 3) { | |
1505 | kvm_inject_gp(ctxt->vcpu, 0); | |
1506 | return X86EMUL_PROPAGATE_FAULT; | |
1507 | } | |
1508 | change_mask |= EFLG_IF; | |
1509 | break; | |
1510 | default: /* real mode */ | |
1511 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1512 | break; | |
1513 | } | |
1514 | ||
1515 | *(unsigned long *)dest = | |
1516 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1517 | ||
1518 | return rc; | |
1519 | } | |
1520 | ||
0934ac9d MG |
1521 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg) |
1522 | { | |
1523 | struct decode_cache *c = &ctxt->decode; | |
1524 | struct kvm_segment segment; | |
1525 | ||
1526 | kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg); | |
1527 | ||
1528 | c->src.val = segment.selector; | |
1529 | emulate_push(ctxt); | |
1530 | } | |
1531 | ||
1532 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, | |
1533 | struct x86_emulate_ops *ops, int seg) | |
1534 | { | |
1535 | struct decode_cache *c = &ctxt->decode; | |
1536 | unsigned long selector; | |
1537 | int rc; | |
1538 | ||
1539 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); | |
1b30eaa8 | 1540 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
1541 | return rc; |
1542 | ||
2e873022 | 1543 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); |
0934ac9d MG |
1544 | return rc; |
1545 | } | |
1546 | ||
abcf14b5 MG |
1547 | static void emulate_pusha(struct x86_emulate_ctxt *ctxt) |
1548 | { | |
1549 | struct decode_cache *c = &ctxt->decode; | |
1550 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1551 | int reg = VCPU_REGS_RAX; | |
1552 | ||
1553 | while (reg <= VCPU_REGS_RDI) { | |
1554 | (reg == VCPU_REGS_RSP) ? | |
1555 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
1556 | ||
1557 | emulate_push(ctxt); | |
1558 | ++reg; | |
1559 | } | |
1560 | } | |
1561 | ||
1562 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, | |
1563 | struct x86_emulate_ops *ops) | |
1564 | { | |
1565 | struct decode_cache *c = &ctxt->decode; | |
1b30eaa8 | 1566 | int rc = X86EMUL_CONTINUE; |
abcf14b5 MG |
1567 | int reg = VCPU_REGS_RDI; |
1568 | ||
1569 | while (reg >= VCPU_REGS_RAX) { | |
1570 | if (reg == VCPU_REGS_RSP) { | |
1571 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1572 | c->op_bytes); | |
1573 | --reg; | |
1574 | } | |
1575 | ||
1576 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); | |
1b30eaa8 | 1577 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
1578 | break; |
1579 | --reg; | |
1580 | } | |
1581 | return rc; | |
1582 | } | |
1583 | ||
faa5a3ae AK |
1584 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
1585 | struct x86_emulate_ops *ops) | |
1586 | { | |
1587 | struct decode_cache *c = &ctxt->decode; | |
faa5a3ae | 1588 | |
1b30eaa8 | 1589 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1590 | } |
1591 | ||
05f086f8 | 1592 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1593 | { |
05f086f8 | 1594 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1595 | switch (c->modrm_reg) { |
1596 | case 0: /* rol */ | |
05f086f8 | 1597 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1598 | break; |
1599 | case 1: /* ror */ | |
05f086f8 | 1600 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1601 | break; |
1602 | case 2: /* rcl */ | |
05f086f8 | 1603 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1604 | break; |
1605 | case 3: /* rcr */ | |
05f086f8 | 1606 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1607 | break; |
1608 | case 4: /* sal/shl */ | |
1609 | case 6: /* sal/shl */ | |
05f086f8 | 1610 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1611 | break; |
1612 | case 5: /* shr */ | |
05f086f8 | 1613 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1614 | break; |
1615 | case 7: /* sar */ | |
05f086f8 | 1616 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1617 | break; |
1618 | } | |
1619 | } | |
1620 | ||
1621 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1622 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1623 | { |
1624 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1625 | |
1626 | switch (c->modrm_reg) { | |
1627 | case 0 ... 1: /* test */ | |
05f086f8 | 1628 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1629 | break; |
1630 | case 2: /* not */ | |
1631 | c->dst.val = ~c->dst.val; | |
1632 | break; | |
1633 | case 3: /* neg */ | |
05f086f8 | 1634 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1635 | break; |
1636 | default: | |
aca06a83 | 1637 | return 0; |
8cdbd2c9 | 1638 | } |
aca06a83 | 1639 | return 1; |
8cdbd2c9 LV |
1640 | } |
1641 | ||
1642 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1643 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1644 | { |
1645 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1646 | |
1647 | switch (c->modrm_reg) { | |
1648 | case 0: /* inc */ | |
05f086f8 | 1649 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1650 | break; |
1651 | case 1: /* dec */ | |
05f086f8 | 1652 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1653 | break; |
d19292e4 MG |
1654 | case 2: /* call near abs */ { |
1655 | long int old_eip; | |
1656 | old_eip = c->eip; | |
1657 | c->eip = c->src.val; | |
1658 | c->src.val = old_eip; | |
1659 | emulate_push(ctxt); | |
1660 | break; | |
1661 | } | |
8cdbd2c9 | 1662 | case 4: /* jmp abs */ |
fd60754e | 1663 | c->eip = c->src.val; |
8cdbd2c9 LV |
1664 | break; |
1665 | case 6: /* push */ | |
fd60754e | 1666 | emulate_push(ctxt); |
8cdbd2c9 | 1667 | break; |
8cdbd2c9 | 1668 | } |
1b30eaa8 | 1669 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1670 | } |
1671 | ||
1672 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1673 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1674 | { |
1675 | struct decode_cache *c = &ctxt->decode; | |
1676 | u64 old, new; | |
1677 | int rc; | |
1678 | ||
69f55cb1 | 1679 | rc = ops->read_emulated(c->modrm_ea, &old, 8, ctxt->vcpu); |
b60d513c | 1680 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1681 | return rc; |
1682 | ||
1683 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1684 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1685 | ||
1686 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1687 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1688 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1689 | |
1690 | } else { | |
1691 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1692 | (u32) c->regs[VCPU_REGS_RBX]; | |
1693 | ||
69f55cb1 | 1694 | rc = ops->cmpxchg_emulated(c->modrm_ea, &old, &new, 8, ctxt->vcpu); |
b60d513c | 1695 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 1696 | return rc; |
05f086f8 | 1697 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1698 | } |
1b30eaa8 | 1699 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1700 | } |
1701 | ||
a77ab5ea AK |
1702 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1703 | struct x86_emulate_ops *ops) | |
1704 | { | |
1705 | struct decode_cache *c = &ctxt->decode; | |
1706 | int rc; | |
1707 | unsigned long cs; | |
1708 | ||
1709 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1710 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1711 | return rc; |
1712 | if (c->op_bytes == 4) | |
1713 | c->eip = (u32)c->eip; | |
1714 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1715 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1716 | return rc; |
2e873022 | 1717 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1718 | return rc; |
1719 | } | |
1720 | ||
8cdbd2c9 LV |
1721 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1722 | struct x86_emulate_ops *ops) | |
1723 | { | |
1724 | int rc; | |
1725 | struct decode_cache *c = &ctxt->decode; | |
1726 | ||
1727 | switch (c->dst.type) { | |
1728 | case OP_REG: | |
1729 | /* The 4-byte case *is* correct: | |
1730 | * in 64-bit mode we zero-extend. | |
1731 | */ | |
1732 | switch (c->dst.bytes) { | |
1733 | case 1: | |
1734 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1735 | break; | |
1736 | case 2: | |
1737 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1738 | break; | |
1739 | case 4: | |
1740 | *c->dst.ptr = (u32)c->dst.val; | |
1741 | break; /* 64b: zero-ext */ | |
1742 | case 8: | |
1743 | *c->dst.ptr = c->dst.val; | |
1744 | break; | |
1745 | } | |
1746 | break; | |
1747 | case OP_MEM: | |
1748 | if (c->lock_prefix) | |
1749 | rc = ops->cmpxchg_emulated( | |
1750 | (unsigned long)c->dst.ptr, | |
1751 | &c->dst.orig_val, | |
1752 | &c->dst.val, | |
1753 | c->dst.bytes, | |
1754 | ctxt->vcpu); | |
1755 | else | |
1756 | rc = ops->write_emulated( | |
1757 | (unsigned long)c->dst.ptr, | |
1758 | &c->dst.val, | |
1759 | c->dst.bytes, | |
1760 | ctxt->vcpu); | |
b60d513c | 1761 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 1762 | return rc; |
a01af5ec LV |
1763 | break; |
1764 | case OP_NONE: | |
1765 | /* no writeback */ | |
1766 | break; | |
8cdbd2c9 LV |
1767 | default: |
1768 | break; | |
1769 | } | |
1b30eaa8 | 1770 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1771 | } |
1772 | ||
a3f9d398 | 1773 | static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) |
310b5d30 GC |
1774 | { |
1775 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); | |
1776 | /* | |
1777 | * an sti; sti; sequence only disable interrupts for the first | |
1778 | * instruction. So, if the last instruction, be it emulated or | |
1779 | * not, left the system with the INT_STI flag enabled, it | |
1780 | * means that the last instruction is an sti. We should not | |
1781 | * leave the flag on in this case. The same goes for mov ss | |
1782 | */ | |
1783 | if (!(int_shadow & mask)) | |
1784 | ctxt->interruptibility = mask; | |
1785 | } | |
1786 | ||
e66bb2cc AP |
1787 | static inline void |
1788 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
1789 | struct kvm_segment *cs, struct kvm_segment *ss) | |
1790 | { | |
1791 | memset(cs, 0, sizeof(struct kvm_segment)); | |
1792 | kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS); | |
1793 | memset(ss, 0, sizeof(struct kvm_segment)); | |
1794 | ||
1795 | cs->l = 0; /* will be adjusted later */ | |
1796 | cs->base = 0; /* flat segment */ | |
1797 | cs->g = 1; /* 4kb granularity */ | |
1798 | cs->limit = 0xffffffff; /* 4GB limit */ | |
1799 | cs->type = 0x0b; /* Read, Execute, Accessed */ | |
1800 | cs->s = 1; | |
1801 | cs->dpl = 0; /* will be adjusted later */ | |
1802 | cs->present = 1; | |
1803 | cs->db = 1; | |
1804 | ||
1805 | ss->unusable = 0; | |
1806 | ss->base = 0; /* flat segment */ | |
1807 | ss->limit = 0xffffffff; /* 4GB limit */ | |
1808 | ss->g = 1; /* 4kb granularity */ | |
1809 | ss->s = 1; | |
1810 | ss->type = 0x03; /* Read/Write, Accessed */ | |
1811 | ss->db = 1; /* 32bit stack segment */ | |
1812 | ss->dpl = 0; | |
1813 | ss->present = 1; | |
1814 | } | |
1815 | ||
1816 | static int | |
1817 | emulate_syscall(struct x86_emulate_ctxt *ctxt) | |
1818 | { | |
1819 | struct decode_cache *c = &ctxt->decode; | |
1820 | struct kvm_segment cs, ss; | |
1821 | u64 msr_data; | |
1822 | ||
1823 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1824 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1825 | ctxt->mode == X86EMUL_MODE_VM86) { | |
1826 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
1827 | return X86EMUL_PROPAGATE_FAULT; | |
1828 | } | |
e66bb2cc AP |
1829 | |
1830 | setup_syscalls_segments(ctxt, &cs, &ss); | |
1831 | ||
1832 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); | |
1833 | msr_data >>= 32; | |
1834 | cs.selector = (u16)(msr_data & 0xfffc); | |
1835 | ss.selector = (u16)(msr_data + 8); | |
1836 | ||
1837 | if (is_long_mode(ctxt->vcpu)) { | |
1838 | cs.db = 0; | |
1839 | cs.l = 1; | |
1840 | } | |
1841 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1842 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1843 | ||
1844 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1845 | if (is_long_mode(ctxt->vcpu)) { | |
1846 | #ifdef CONFIG_X86_64 | |
1847 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1848 | ||
1849 | kvm_x86_ops->get_msr(ctxt->vcpu, | |
1850 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1851 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
1852 | c->eip = msr_data; | |
1853 | ||
1854 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); | |
1855 | ctxt->eflags &= ~(msr_data | EFLG_RF); | |
1856 | #endif | |
1857 | } else { | |
1858 | /* legacy mode */ | |
1859 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); | |
1860 | c->eip = (u32)msr_data; | |
1861 | ||
1862 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1863 | } | |
1864 | ||
e54cfa97 | 1865 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1866 | } |
1867 | ||
8c604352 AP |
1868 | static int |
1869 | emulate_sysenter(struct x86_emulate_ctxt *ctxt) | |
1870 | { | |
1871 | struct decode_cache *c = &ctxt->decode; | |
1872 | struct kvm_segment cs, ss; | |
1873 | u64 msr_data; | |
1874 | ||
a0044755 GN |
1875 | /* inject #GP if in real mode */ |
1876 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
8c604352 | 1877 | kvm_inject_gp(ctxt->vcpu, 0); |
2e901c4c | 1878 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1879 | } |
1880 | ||
1881 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1882 | * Therefore, we inject an #UD. | |
1883 | */ | |
2e901c4c GN |
1884 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
1885 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
1886 | return X86EMUL_PROPAGATE_FAULT; | |
1887 | } | |
8c604352 AP |
1888 | |
1889 | setup_syscalls_segments(ctxt, &cs, &ss); | |
1890 | ||
1891 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); | |
1892 | switch (ctxt->mode) { | |
1893 | case X86EMUL_MODE_PROT32: | |
1894 | if ((msr_data & 0xfffc) == 0x0) { | |
1895 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1896 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1897 | } |
1898 | break; | |
1899 | case X86EMUL_MODE_PROT64: | |
1900 | if (msr_data == 0x0) { | |
1901 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1902 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1903 | } |
1904 | break; | |
1905 | } | |
1906 | ||
1907 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1908 | cs.selector = (u16)msr_data; | |
1909 | cs.selector &= ~SELECTOR_RPL_MASK; | |
1910 | ss.selector = cs.selector + 8; | |
1911 | ss.selector &= ~SELECTOR_RPL_MASK; | |
1912 | if (ctxt->mode == X86EMUL_MODE_PROT64 | |
1913 | || is_long_mode(ctxt->vcpu)) { | |
1914 | cs.db = 0; | |
1915 | cs.l = 1; | |
1916 | } | |
1917 | ||
1918 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1919 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1920 | ||
1921 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); | |
1922 | c->eip = msr_data; | |
1923 | ||
1924 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); | |
1925 | c->regs[VCPU_REGS_RSP] = msr_data; | |
1926 | ||
e54cfa97 | 1927 | return X86EMUL_CONTINUE; |
8c604352 AP |
1928 | } |
1929 | ||
4668f050 AP |
1930 | static int |
1931 | emulate_sysexit(struct x86_emulate_ctxt *ctxt) | |
1932 | { | |
1933 | struct decode_cache *c = &ctxt->decode; | |
1934 | struct kvm_segment cs, ss; | |
1935 | u64 msr_data; | |
1936 | int usermode; | |
1937 | ||
a0044755 GN |
1938 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1939 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1940 | ctxt->mode == X86EMUL_MODE_VM86) { | |
4668f050 | 1941 | kvm_inject_gp(ctxt->vcpu, 0); |
2e901c4c | 1942 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1943 | } |
1944 | ||
4668f050 AP |
1945 | setup_syscalls_segments(ctxt, &cs, &ss); |
1946 | ||
1947 | if ((c->rex_prefix & 0x8) != 0x0) | |
1948 | usermode = X86EMUL_MODE_PROT64; | |
1949 | else | |
1950 | usermode = X86EMUL_MODE_PROT32; | |
1951 | ||
1952 | cs.dpl = 3; | |
1953 | ss.dpl = 3; | |
1954 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); | |
1955 | switch (usermode) { | |
1956 | case X86EMUL_MODE_PROT32: | |
1957 | cs.selector = (u16)(msr_data + 16); | |
1958 | if ((msr_data & 0xfffc) == 0x0) { | |
1959 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1960 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1961 | } |
1962 | ss.selector = (u16)(msr_data + 24); | |
1963 | break; | |
1964 | case X86EMUL_MODE_PROT64: | |
1965 | cs.selector = (u16)(msr_data + 32); | |
1966 | if (msr_data == 0x0) { | |
1967 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1968 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
1969 | } |
1970 | ss.selector = cs.selector + 8; | |
1971 | cs.db = 0; | |
1972 | cs.l = 1; | |
1973 | break; | |
1974 | } | |
1975 | cs.selector |= SELECTOR_RPL_MASK; | |
1976 | ss.selector |= SELECTOR_RPL_MASK; | |
1977 | ||
1978 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1979 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1980 | ||
1981 | c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX]; | |
1982 | c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX]; | |
1983 | ||
e54cfa97 | 1984 | return X86EMUL_CONTINUE; |
4668f050 AP |
1985 | } |
1986 | ||
9c537244 GN |
1987 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1988 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1989 | { |
1990 | int iopl; | |
1991 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1992 | return false; | |
1993 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1994 | return true; | |
1995 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1996 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1997 | } |
1998 | ||
1999 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
2000 | struct x86_emulate_ops *ops, | |
2001 | u16 port, u16 len) | |
2002 | { | |
2003 | struct kvm_segment tr_seg; | |
2004 | int r; | |
2005 | u16 io_bitmap_ptr; | |
2006 | u8 perm, bit_idx = port & 0x7; | |
2007 | unsigned mask = (1 << len) - 1; | |
2008 | ||
2009 | kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR); | |
2010 | if (tr_seg.unusable) | |
2011 | return false; | |
2012 | if (tr_seg.limit < 103) | |
2013 | return false; | |
2014 | r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, | |
2015 | NULL); | |
2016 | if (r != X86EMUL_CONTINUE) | |
2017 | return false; | |
2018 | if (io_bitmap_ptr + port/8 > tr_seg.limit) | |
2019 | return false; | |
2020 | r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1, | |
2021 | ctxt->vcpu, NULL); | |
2022 | if (r != X86EMUL_CONTINUE) | |
2023 | return false; | |
2024 | if ((perm >> bit_idx) & mask) | |
2025 | return false; | |
2026 | return true; | |
2027 | } | |
2028 | ||
2029 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
2030 | struct x86_emulate_ops *ops, | |
2031 | u16 port, u16 len) | |
2032 | { | |
9c537244 | 2033 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2034 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
2035 | return false; | |
2036 | return true; | |
2037 | } | |
2038 | ||
38ba30ba GN |
2039 | static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt, |
2040 | struct x86_emulate_ops *ops, | |
2041 | int seg) | |
2042 | { | |
2043 | struct desc_struct desc; | |
2044 | if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu)) | |
2045 | return get_desc_base(&desc); | |
2046 | else | |
2047 | return ~0; | |
2048 | } | |
2049 | ||
2050 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, | |
2051 | struct x86_emulate_ops *ops, | |
2052 | struct tss_segment_16 *tss) | |
2053 | { | |
2054 | struct decode_cache *c = &ctxt->decode; | |
2055 | ||
2056 | tss->ip = c->eip; | |
2057 | tss->flag = ctxt->eflags; | |
2058 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
2059 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
2060 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
2061 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
2062 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
2063 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
2064 | tss->si = c->regs[VCPU_REGS_RSI]; | |
2065 | tss->di = c->regs[VCPU_REGS_RDI]; | |
2066 | ||
2067 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2068 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2069 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2070 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2071 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2072 | } | |
2073 | ||
2074 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
2075 | struct x86_emulate_ops *ops, | |
2076 | struct tss_segment_16 *tss) | |
2077 | { | |
2078 | struct decode_cache *c = &ctxt->decode; | |
2079 | int ret; | |
2080 | ||
2081 | c->eip = tss->ip; | |
2082 | ctxt->eflags = tss->flag | 2; | |
2083 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
2084 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
2085 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
2086 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
2087 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
2088 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
2089 | c->regs[VCPU_REGS_RSI] = tss->si; | |
2090 | c->regs[VCPU_REGS_RDI] = tss->di; | |
2091 | ||
2092 | /* | |
2093 | * SDM says that segment selectors are loaded before segment | |
2094 | * descriptors | |
2095 | */ | |
2096 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
2097 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2098 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2099 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2100 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2101 | ||
2102 | /* | |
2103 | * Now load segment descriptors. If fault happenes at this stage | |
2104 | * it is handled in a context of new task | |
2105 | */ | |
2106 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
2107 | if (ret != X86EMUL_CONTINUE) | |
2108 | return ret; | |
2109 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2110 | if (ret != X86EMUL_CONTINUE) | |
2111 | return ret; | |
2112 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2113 | if (ret != X86EMUL_CONTINUE) | |
2114 | return ret; | |
2115 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2116 | if (ret != X86EMUL_CONTINUE) | |
2117 | return ret; | |
2118 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2119 | if (ret != X86EMUL_CONTINUE) | |
2120 | return ret; | |
2121 | ||
2122 | return X86EMUL_CONTINUE; | |
2123 | } | |
2124 | ||
2125 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
2126 | struct x86_emulate_ops *ops, | |
2127 | u16 tss_selector, u16 old_tss_sel, | |
2128 | ulong old_tss_base, struct desc_struct *new_desc) | |
2129 | { | |
2130 | struct tss_segment_16 tss_seg; | |
2131 | int ret; | |
2132 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2133 | ||
2134 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2135 | &err); | |
2136 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2137 | /* FIXME: need to provide precise fault address */ | |
2138 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2139 | return ret; | |
2140 | } | |
2141 | ||
2142 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
2143 | ||
2144 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2145 | &err); | |
2146 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2147 | /* FIXME: need to provide precise fault address */ | |
2148 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2149 | return ret; | |
2150 | } | |
2151 | ||
2152 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2153 | &err); | |
2154 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2155 | /* FIXME: need to provide precise fault address */ | |
2156 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2157 | return ret; | |
2158 | } | |
2159 | ||
2160 | if (old_tss_sel != 0xffff) { | |
2161 | tss_seg.prev_task_link = old_tss_sel; | |
2162 | ||
2163 | ret = ops->write_std(new_tss_base, | |
2164 | &tss_seg.prev_task_link, | |
2165 | sizeof tss_seg.prev_task_link, | |
2166 | ctxt->vcpu, &err); | |
2167 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2168 | /* FIXME: need to provide precise fault address */ | |
2169 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2170 | return ret; | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2175 | } | |
2176 | ||
2177 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2178 | struct x86_emulate_ops *ops, | |
2179 | struct tss_segment_32 *tss) | |
2180 | { | |
2181 | struct decode_cache *c = &ctxt->decode; | |
2182 | ||
2183 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2184 | tss->eip = c->eip; | |
2185 | tss->eflags = ctxt->eflags; | |
2186 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2187 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2188 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2189 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2190 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2191 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2192 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2193 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2194 | ||
2195 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2196 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2197 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2198 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2199 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2200 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2201 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2202 | } | |
2203 | ||
2204 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2205 | struct x86_emulate_ops *ops, | |
2206 | struct tss_segment_32 *tss) | |
2207 | { | |
2208 | struct decode_cache *c = &ctxt->decode; | |
2209 | int ret; | |
2210 | ||
2211 | ops->set_cr(3, tss->cr3, ctxt->vcpu); | |
2212 | c->eip = tss->eip; | |
2213 | ctxt->eflags = tss->eflags | 2; | |
2214 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2215 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2216 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2217 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2218 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2219 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2220 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2221 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2222 | ||
2223 | /* | |
2224 | * SDM says that segment selectors are loaded before segment | |
2225 | * descriptors | |
2226 | */ | |
2227 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2228 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2229 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2230 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2231 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2232 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2233 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2234 | ||
2235 | /* | |
2236 | * Now load segment descriptors. If fault happenes at this stage | |
2237 | * it is handled in a context of new task | |
2238 | */ | |
2239 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2240 | if (ret != X86EMUL_CONTINUE) | |
2241 | return ret; | |
2242 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2243 | if (ret != X86EMUL_CONTINUE) | |
2244 | return ret; | |
2245 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2246 | if (ret != X86EMUL_CONTINUE) | |
2247 | return ret; | |
2248 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2249 | if (ret != X86EMUL_CONTINUE) | |
2250 | return ret; | |
2251 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2252 | if (ret != X86EMUL_CONTINUE) | |
2253 | return ret; | |
2254 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2255 | if (ret != X86EMUL_CONTINUE) | |
2256 | return ret; | |
2257 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2258 | if (ret != X86EMUL_CONTINUE) | |
2259 | return ret; | |
2260 | ||
2261 | return X86EMUL_CONTINUE; | |
2262 | } | |
2263 | ||
2264 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2265 | struct x86_emulate_ops *ops, | |
2266 | u16 tss_selector, u16 old_tss_sel, | |
2267 | ulong old_tss_base, struct desc_struct *new_desc) | |
2268 | { | |
2269 | struct tss_segment_32 tss_seg; | |
2270 | int ret; | |
2271 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2272 | ||
2273 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2274 | &err); | |
2275 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2276 | /* FIXME: need to provide precise fault address */ | |
2277 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2278 | return ret; | |
2279 | } | |
2280 | ||
2281 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2282 | ||
2283 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2284 | &err); | |
2285 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2286 | /* FIXME: need to provide precise fault address */ | |
2287 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2288 | return ret; | |
2289 | } | |
2290 | ||
2291 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2292 | &err); | |
2293 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2294 | /* FIXME: need to provide precise fault address */ | |
2295 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2296 | return ret; | |
2297 | } | |
2298 | ||
2299 | if (old_tss_sel != 0xffff) { | |
2300 | tss_seg.prev_task_link = old_tss_sel; | |
2301 | ||
2302 | ret = ops->write_std(new_tss_base, | |
2303 | &tss_seg.prev_task_link, | |
2304 | sizeof tss_seg.prev_task_link, | |
2305 | ctxt->vcpu, &err); | |
2306 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2307 | /* FIXME: need to provide precise fault address */ | |
2308 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2309 | return ret; | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2314 | } | |
2315 | ||
2316 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
2317 | struct x86_emulate_ops *ops, | |
2318 | u16 tss_selector, int reason) | |
2319 | { | |
2320 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2321 | int ret; | |
2322 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2323 | ulong old_tss_base = | |
2324 | get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR); | |
ceffb459 | 2325 | u32 desc_limit; |
38ba30ba GN |
2326 | |
2327 | /* FIXME: old_tss_base == ~0 ? */ | |
2328 | ||
2329 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2330 | if (ret != X86EMUL_CONTINUE) | |
2331 | return ret; | |
2332 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2333 | if (ret != X86EMUL_CONTINUE) | |
2334 | return ret; | |
2335 | ||
2336 | /* FIXME: check that next_tss_desc is tss */ | |
2337 | ||
2338 | if (reason != TASK_SWITCH_IRET) { | |
2339 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2340 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
2341 | kvm_inject_gp(ctxt->vcpu, 0); | |
2342 | return X86EMUL_PROPAGATE_FAULT; | |
2343 | } | |
2344 | } | |
2345 | ||
ceffb459 GN |
2346 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2347 | if (!next_tss_desc.p || | |
2348 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2349 | desc_limit < 0x2b)) { | |
38ba30ba GN |
2350 | kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR, |
2351 | tss_selector & 0xfffc); | |
2352 | return X86EMUL_PROPAGATE_FAULT; | |
2353 | } | |
2354 | ||
2355 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2356 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2357 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2358 | &curr_tss_desc); | |
2359 | } | |
2360 | ||
2361 | if (reason == TASK_SWITCH_IRET) | |
2362 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2363 | ||
2364 | /* set back link to prev task only if NT bit is set in eflags | |
2365 | note that old_tss_sel is not used afetr this point */ | |
2366 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2367 | old_tss_sel = 0xffff; | |
2368 | ||
2369 | if (next_tss_desc.type & 8) | |
2370 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2371 | old_tss_base, &next_tss_desc); | |
2372 | else | |
2373 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2374 | old_tss_base, &next_tss_desc); | |
2375 | ||
2376 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2377 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2378 | ||
2379 | if (reason != TASK_SWITCH_IRET) { | |
2380 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2381 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2382 | &next_tss_desc); | |
2383 | } | |
2384 | ||
2385 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2386 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2387 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2388 | ||
2389 | return ret; | |
2390 | } | |
2391 | ||
2392 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
2393 | struct x86_emulate_ops *ops, | |
2394 | u16 tss_selector, int reason) | |
2395 | { | |
2396 | struct decode_cache *c = &ctxt->decode; | |
2397 | int rc; | |
2398 | ||
2399 | memset(c, 0, sizeof(struct decode_cache)); | |
2400 | c->eip = ctxt->eip; | |
2401 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); | |
2402 | ||
2403 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason); | |
2404 | ||
2405 | if (rc == X86EMUL_CONTINUE) { | |
2406 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); | |
2407 | kvm_rip_write(ctxt->vcpu, c->eip); | |
2408 | } | |
2409 | ||
2410 | return rc; | |
2411 | } | |
2412 | ||
a682e354 | 2413 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2414 | int reg, struct operand *op) |
a682e354 GN |
2415 | { |
2416 | struct decode_cache *c = &ctxt->decode; | |
2417 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2418 | ||
d9271123 GN |
2419 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
2420 | op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]); | |
a682e354 GN |
2421 | } |
2422 | ||
8b4caf66 | 2423 | int |
1be3aa47 | 2424 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 2425 | { |
8b4caf66 | 2426 | u64 msr_data; |
3427318f | 2427 | unsigned long saved_eip = 0; |
8b4caf66 | 2428 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2429 | int rc = X86EMUL_CONTINUE; |
8b4caf66 | 2430 | |
310b5d30 GC |
2431 | ctxt->interruptibility = 0; |
2432 | ||
3427318f LV |
2433 | /* Shadow copy of register state. Committed on successful emulation. |
2434 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
2435 | * modify them. | |
2436 | */ | |
2437 | ||
ad312c7c | 2438 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
3427318f LV |
2439 | saved_eip = c->eip; |
2440 | ||
1161624f GN |
2441 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
2442 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
2443 | goto done; | |
2444 | } | |
2445 | ||
d380a5e4 | 2446 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2447 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
d380a5e4 GN |
2448 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2449 | goto done; | |
2450 | } | |
2451 | ||
e92805ac | 2452 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2453 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
e92805ac GN |
2454 | kvm_inject_gp(ctxt->vcpu, 0); |
2455 | goto done; | |
2456 | } | |
2457 | ||
b9fa9d6b AK |
2458 | if (c->rep_prefix && (c->d & String)) { |
2459 | /* All REP prefixes have the same first termination condition */ | |
c73e197b | 2460 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5fdbf976 | 2461 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
2462 | goto done; |
2463 | } | |
2464 | /* The second termination condition only applies for REPE | |
2465 | * and REPNE. Test if the repeat string operation prefix is | |
2466 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2467 | * corresponding termination condition according to: | |
2468 | * - if REPE/REPZ and ZF = 0 then done | |
2469 | * - if REPNE/REPNZ and ZF = 1 then done | |
2470 | */ | |
2471 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
2472 | (c->b == 0xae) || (c->b == 0xaf)) { | |
2473 | if ((c->rep_prefix == REPE_PREFIX) && | |
2474 | ((ctxt->eflags & EFLG_ZF) == 0)) { | |
5fdbf976 | 2475 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
2476 | goto done; |
2477 | } | |
2478 | if ((c->rep_prefix == REPNE_PREFIX) && | |
2479 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) { | |
5fdbf976 | 2480 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
2481 | goto done; |
2482 | } | |
2483 | } | |
063db061 | 2484 | c->eip = ctxt->eip; |
b9fa9d6b AK |
2485 | } |
2486 | ||
8b4caf66 | 2487 | if (c->src.type == OP_MEM) { |
d77c26fc MD |
2488 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
2489 | &c->src.val, | |
2490 | c->src.bytes, | |
2491 | ctxt->vcpu); | |
b60d513c | 2492 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 LV |
2493 | goto done; |
2494 | c->src.orig_val = c->src.val; | |
2495 | } | |
2496 | ||
e35b7b9c | 2497 | if (c->src2.type == OP_MEM) { |
e35b7b9c GN |
2498 | rc = ops->read_emulated((unsigned long)c->src2.ptr, |
2499 | &c->src2.val, | |
2500 | c->src2.bytes, | |
2501 | ctxt->vcpu); | |
2502 | if (rc != X86EMUL_CONTINUE) | |
2503 | goto done; | |
2504 | } | |
2505 | ||
8b4caf66 LV |
2506 | if ((c->d & DstMask) == ImplicitOps) |
2507 | goto special_insn; | |
2508 | ||
2509 | ||
69f55cb1 GN |
2510 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2511 | /* optimisation - avoid slow emulated read if Mov */ | |
2512 | rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val, | |
2513 | c->dst.bytes, ctxt->vcpu); | |
2514 | if (rc != X86EMUL_CONTINUE) | |
2515 | goto done; | |
038e51de | 2516 | } |
e4e03ded | 2517 | c->dst.orig_val = c->dst.val; |
038e51de | 2518 | |
018a98db AK |
2519 | special_insn: |
2520 | ||
e4e03ded | 2521 | if (c->twobyte) |
6aa8b732 AK |
2522 | goto twobyte_insn; |
2523 | ||
e4e03ded | 2524 | switch (c->b) { |
6aa8b732 AK |
2525 | case 0x00 ... 0x05: |
2526 | add: /* add */ | |
05f086f8 | 2527 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2528 | break; |
0934ac9d | 2529 | case 0x06: /* push es */ |
0934ac9d MG |
2530 | emulate_push_sreg(ctxt, VCPU_SREG_ES); |
2531 | break; | |
2532 | case 0x07: /* pop es */ | |
0934ac9d | 2533 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2534 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2535 | goto done; |
2536 | break; | |
6aa8b732 AK |
2537 | case 0x08 ... 0x0d: |
2538 | or: /* or */ | |
05f086f8 | 2539 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2540 | break; |
0934ac9d | 2541 | case 0x0e: /* push cs */ |
0934ac9d MG |
2542 | emulate_push_sreg(ctxt, VCPU_SREG_CS); |
2543 | break; | |
6aa8b732 AK |
2544 | case 0x10 ... 0x15: |
2545 | adc: /* adc */ | |
05f086f8 | 2546 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2547 | break; |
0934ac9d | 2548 | case 0x16: /* push ss */ |
0934ac9d MG |
2549 | emulate_push_sreg(ctxt, VCPU_SREG_SS); |
2550 | break; | |
2551 | case 0x17: /* pop ss */ | |
0934ac9d | 2552 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2553 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2554 | goto done; |
2555 | break; | |
6aa8b732 AK |
2556 | case 0x18 ... 0x1d: |
2557 | sbb: /* sbb */ | |
05f086f8 | 2558 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2559 | break; |
0934ac9d | 2560 | case 0x1e: /* push ds */ |
0934ac9d MG |
2561 | emulate_push_sreg(ctxt, VCPU_SREG_DS); |
2562 | break; | |
2563 | case 0x1f: /* pop ds */ | |
0934ac9d | 2564 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2565 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2566 | goto done; |
2567 | break; | |
aa3a816b | 2568 | case 0x20 ... 0x25: |
6aa8b732 | 2569 | and: /* and */ |
05f086f8 | 2570 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2571 | break; |
2572 | case 0x28 ... 0x2d: | |
2573 | sub: /* sub */ | |
05f086f8 | 2574 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2575 | break; |
2576 | case 0x30 ... 0x35: | |
2577 | xor: /* xor */ | |
05f086f8 | 2578 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2579 | break; |
2580 | case 0x38 ... 0x3d: | |
2581 | cmp: /* cmp */ | |
05f086f8 | 2582 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2583 | break; |
33615aa9 AK |
2584 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2585 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2586 | break; | |
2587 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2588 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2589 | break; | |
2590 | case 0x50 ... 0x57: /* push reg */ | |
2786b014 | 2591 | emulate_push(ctxt); |
33615aa9 AK |
2592 | break; |
2593 | case 0x58 ... 0x5f: /* pop reg */ | |
2594 | pop_instruction: | |
350f69dc | 2595 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2596 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2597 | goto done; |
33615aa9 | 2598 | break; |
abcf14b5 MG |
2599 | case 0x60: /* pusha */ |
2600 | emulate_pusha(ctxt); | |
2601 | break; | |
2602 | case 0x61: /* popa */ | |
2603 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2604 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2605 | goto done; |
2606 | break; | |
6aa8b732 | 2607 | case 0x63: /* movsxd */ |
8b4caf66 | 2608 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2609 | goto cannot_emulate; |
e4e03ded | 2610 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2611 | break; |
91ed7a0e | 2612 | case 0x68: /* push imm */ |
018a98db | 2613 | case 0x6a: /* push imm8 */ |
018a98db AK |
2614 | emulate_push(ctxt); |
2615 | break; | |
2616 | case 0x6c: /* insb */ | |
2617 | case 0x6d: /* insw/insd */ | |
f850e2e6 GN |
2618 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
2619 | (c->d & ByteOp) ? 1 : c->op_bytes)) { | |
2620 | kvm_inject_gp(ctxt->vcpu, 0); | |
2621 | goto done; | |
2622 | } | |
2623 | if (kvm_emulate_pio_string(ctxt->vcpu, | |
018a98db AK |
2624 | 1, |
2625 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
2626 | c->rep_prefix ? | |
e4706772 | 2627 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 2628 | (ctxt->eflags & EFLG_DF), |
7a5b56df | 2629 | register_address(c, es_base(ctxt), |
018a98db AK |
2630 | c->regs[VCPU_REGS_RDI]), |
2631 | c->rep_prefix, | |
2632 | c->regs[VCPU_REGS_RDX]) == 0) { | |
2633 | c->eip = saved_eip; | |
2634 | return -1; | |
2635 | } | |
2636 | return 0; | |
2637 | case 0x6e: /* outsb */ | |
2638 | case 0x6f: /* outsw/outsd */ | |
f850e2e6 GN |
2639 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
2640 | (c->d & ByteOp) ? 1 : c->op_bytes)) { | |
2641 | kvm_inject_gp(ctxt->vcpu, 0); | |
2642 | goto done; | |
2643 | } | |
851ba692 | 2644 | if (kvm_emulate_pio_string(ctxt->vcpu, |
018a98db AK |
2645 | 0, |
2646 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
2647 | c->rep_prefix ? | |
e4706772 | 2648 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 2649 | (ctxt->eflags & EFLG_DF), |
7a5b56df AK |
2650 | register_address(c, |
2651 | seg_override_base(ctxt, c), | |
018a98db AK |
2652 | c->regs[VCPU_REGS_RSI]), |
2653 | c->rep_prefix, | |
2654 | c->regs[VCPU_REGS_RDX]) == 0) { | |
2655 | c->eip = saved_eip; | |
2656 | return -1; | |
2657 | } | |
2658 | return 0; | |
b2833e3c | 2659 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2660 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2661 | jmp_rel(c, c->src.val); |
018a98db | 2662 | break; |
6aa8b732 | 2663 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2664 | switch (c->modrm_reg) { |
6aa8b732 AK |
2665 | case 0: |
2666 | goto add; | |
2667 | case 1: | |
2668 | goto or; | |
2669 | case 2: | |
2670 | goto adc; | |
2671 | case 3: | |
2672 | goto sbb; | |
2673 | case 4: | |
2674 | goto and; | |
2675 | case 5: | |
2676 | goto sub; | |
2677 | case 6: | |
2678 | goto xor; | |
2679 | case 7: | |
2680 | goto cmp; | |
2681 | } | |
2682 | break; | |
2683 | case 0x84 ... 0x85: | |
05f086f8 | 2684 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2685 | break; |
2686 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2687 | xchg: |
6aa8b732 | 2688 | /* Write back the register source. */ |
e4e03ded | 2689 | switch (c->dst.bytes) { |
6aa8b732 | 2690 | case 1: |
e4e03ded | 2691 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
2692 | break; |
2693 | case 2: | |
e4e03ded | 2694 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
2695 | break; |
2696 | case 4: | |
e4e03ded | 2697 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
2698 | break; /* 64b reg: zero-extend */ |
2699 | case 8: | |
e4e03ded | 2700 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
2701 | break; |
2702 | } | |
2703 | /* | |
2704 | * Write back the memory destination with implicit LOCK | |
2705 | * prefix. | |
2706 | */ | |
e4e03ded LV |
2707 | c->dst.val = c->src.val; |
2708 | c->lock_prefix = 1; | |
6aa8b732 | 2709 | break; |
6aa8b732 | 2710 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2711 | goto mov; |
38d5bc6d GT |
2712 | case 0x8c: { /* mov r/m, sreg */ |
2713 | struct kvm_segment segreg; | |
2714 | ||
5e3ae6c5 | 2715 | if (c->modrm_reg <= VCPU_SREG_GS) |
38d5bc6d GT |
2716 | kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg); |
2717 | else { | |
5e3ae6c5 GN |
2718 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2719 | goto done; | |
38d5bc6d GT |
2720 | } |
2721 | c->dst.val = segreg.selector; | |
2722 | break; | |
2723 | } | |
7e0b54b1 | 2724 | case 0x8d: /* lea r16/r32, m */ |
f9b7aab3 | 2725 | c->dst.val = c->modrm_ea; |
7e0b54b1 | 2726 | break; |
4257198a GT |
2727 | case 0x8e: { /* mov seg, r/m16 */ |
2728 | uint16_t sel; | |
4257198a GT |
2729 | |
2730 | sel = c->src.val; | |
8b9f4414 | 2731 | |
c697518a GN |
2732 | if (c->modrm_reg == VCPU_SREG_CS || |
2733 | c->modrm_reg > VCPU_SREG_GS) { | |
8b9f4414 GN |
2734 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2735 | goto done; | |
2736 | } | |
2737 | ||
310b5d30 | 2738 | if (c->modrm_reg == VCPU_SREG_SS) |
48005f64 | 2739 | toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS); |
310b5d30 | 2740 | |
2e873022 | 2741 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
2742 | |
2743 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2744 | break; | |
2745 | } | |
6aa8b732 | 2746 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 2747 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 2748 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 2749 | goto done; |
6aa8b732 | 2750 | break; |
b13354f8 MG |
2751 | case 0x90: /* nop / xchg r8,rax */ |
2752 | if (!(c->rex_prefix & 1)) { /* nop */ | |
2753 | c->dst.type = OP_NONE; | |
2754 | break; | |
2755 | } | |
2756 | case 0x91 ... 0x97: /* xchg reg,rax */ | |
2757 | c->src.type = c->dst.type = OP_REG; | |
2758 | c->src.bytes = c->dst.bytes = c->op_bytes; | |
2759 | c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX]; | |
2760 | c->src.val = *(c->src.ptr); | |
2761 | goto xchg; | |
fd2a7608 | 2762 | case 0x9c: /* pushf */ |
05f086f8 | 2763 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
2764 | emulate_push(ctxt); |
2765 | break; | |
535eabcf | 2766 | case 0x9d: /* popf */ |
2b48cc75 | 2767 | c->dst.type = OP_REG; |
05f086f8 | 2768 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
2b48cc75 | 2769 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
2770 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
2771 | if (rc != X86EMUL_CONTINUE) | |
2772 | goto done; | |
2773 | break; | |
018a98db AK |
2774 | case 0xa0 ... 0xa1: /* mov */ |
2775 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
2776 | c->dst.val = c->src.val; | |
2777 | break; | |
2778 | case 0xa2 ... 0xa3: /* mov */ | |
2779 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; | |
2780 | break; | |
6aa8b732 | 2781 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 2782 | goto mov; |
6aa8b732 | 2783 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 2784 | c->dst.type = OP_NONE; /* Disable writeback. */ |
d7e5117a | 2785 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); |
a682e354 | 2786 | goto cmp; |
6aa8b732 | 2787 | case 0xaa ... 0xab: /* stos */ |
e4e03ded | 2788 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
2789 | break; |
2790 | case 0xac ... 0xad: /* lods */ | |
a682e354 | 2791 | goto mov; |
6aa8b732 AK |
2792 | case 0xae ... 0xaf: /* scas */ |
2793 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
2794 | goto cannot_emulate; | |
a5e2e82b | 2795 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 2796 | goto mov; |
018a98db AK |
2797 | case 0xc0 ... 0xc1: |
2798 | emulate_grp2(ctxt); | |
2799 | break; | |
111de5d6 | 2800 | case 0xc3: /* ret */ |
cf5de4f8 | 2801 | c->dst.type = OP_REG; |
111de5d6 | 2802 | c->dst.ptr = &c->eip; |
cf5de4f8 | 2803 | c->dst.bytes = c->op_bytes; |
111de5d6 | 2804 | goto pop_instruction; |
018a98db AK |
2805 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
2806 | mov: | |
2807 | c->dst.val = c->src.val; | |
2808 | break; | |
a77ab5ea AK |
2809 | case 0xcb: /* ret far */ |
2810 | rc = emulate_ret_far(ctxt, ops); | |
1b30eaa8 | 2811 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
2812 | goto done; |
2813 | break; | |
018a98db AK |
2814 | case 0xd0 ... 0xd1: /* Grp2 */ |
2815 | c->src.val = 1; | |
2816 | emulate_grp2(ctxt); | |
2817 | break; | |
2818 | case 0xd2 ... 0xd3: /* Grp2 */ | |
2819 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
2820 | emulate_grp2(ctxt); | |
2821 | break; | |
a6a3034c MG |
2822 | case 0xe4: /* inb */ |
2823 | case 0xe5: /* in */ | |
cf8f70bf | 2824 | goto do_io_in; |
a6a3034c MG |
2825 | case 0xe6: /* outb */ |
2826 | case 0xe7: /* out */ | |
cf8f70bf | 2827 | goto do_io_out; |
1a52e051 | 2828 | case 0xe8: /* call (near) */ { |
d53c4777 | 2829 | long int rel = c->src.val; |
e4e03ded | 2830 | c->src.val = (unsigned long) c->eip; |
7a957275 | 2831 | jmp_rel(c, rel); |
8cdbd2c9 LV |
2832 | emulate_push(ctxt); |
2833 | break; | |
1a52e051 NK |
2834 | } |
2835 | case 0xe9: /* jmp rel */ | |
954cd36f | 2836 | goto jmp; |
782b877c | 2837 | case 0xea: /* jmp far */ |
ea79849d | 2838 | jump_far: |
2e873022 GN |
2839 | if (load_segment_descriptor(ctxt, ops, c->src2.val, |
2840 | VCPU_SREG_CS)) | |
c697518a | 2841 | goto done; |
954cd36f | 2842 | |
782b877c | 2843 | c->eip = c->src.val; |
954cd36f | 2844 | break; |
954cd36f GT |
2845 | case 0xeb: |
2846 | jmp: /* jmp rel short */ | |
7a957275 | 2847 | jmp_rel(c, c->src.val); |
a01af5ec | 2848 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 2849 | break; |
a6a3034c MG |
2850 | case 0xec: /* in al,dx */ |
2851 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
2852 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2853 | do_io_in: | |
2854 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2855 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
2856 | kvm_inject_gp(ctxt->vcpu, 0); | |
2857 | goto done; | |
2858 | } | |
2859 | if (!ops->pio_in_emulated(c->dst.bytes, c->src.val, | |
2860 | &c->dst.val, 1, ctxt->vcpu)) | |
2861 | goto done; /* IO is needed */ | |
2862 | break; | |
a6a3034c MG |
2863 | case 0xee: /* out al,dx */ |
2864 | case 0xef: /* out (e/r)ax,dx */ | |
cf8f70bf GN |
2865 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2866 | do_io_out: | |
2867 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2868 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
f850e2e6 GN |
2869 | kvm_inject_gp(ctxt->vcpu, 0); |
2870 | goto done; | |
2871 | } | |
cf8f70bf GN |
2872 | ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, |
2873 | ctxt->vcpu); | |
2874 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 2875 | break; |
111de5d6 | 2876 | case 0xf4: /* hlt */ |
ad312c7c | 2877 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 2878 | break; |
111de5d6 AK |
2879 | case 0xf5: /* cmc */ |
2880 | /* complement carry flag from eflags reg */ | |
2881 | ctxt->eflags ^= EFLG_CF; | |
2882 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2883 | break; | |
018a98db | 2884 | case 0xf6 ... 0xf7: /* Grp3 */ |
aca06a83 GN |
2885 | if (!emulate_grp3(ctxt, ops)) |
2886 | goto cannot_emulate; | |
018a98db | 2887 | break; |
111de5d6 AK |
2888 | case 0xf8: /* clc */ |
2889 | ctxt->eflags &= ~EFLG_CF; | |
2890 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2891 | break; | |
2892 | case 0xfa: /* cli */ | |
9c537244 | 2893 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2894 | kvm_inject_gp(ctxt->vcpu, 0); |
2895 | else { | |
2896 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
2897 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2898 | } | |
111de5d6 AK |
2899 | break; |
2900 | case 0xfb: /* sti */ | |
9c537244 | 2901 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2902 | kvm_inject_gp(ctxt->vcpu, 0); |
2903 | else { | |
48005f64 | 2904 | toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI); |
f850e2e6 GN |
2905 | ctxt->eflags |= X86_EFLAGS_IF; |
2906 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2907 | } | |
111de5d6 | 2908 | break; |
fb4616f4 MG |
2909 | case 0xfc: /* cld */ |
2910 | ctxt->eflags &= ~EFLG_DF; | |
2911 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2912 | break; | |
2913 | case 0xfd: /* std */ | |
2914 | ctxt->eflags |= EFLG_DF; | |
2915 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2916 | break; | |
ea79849d GN |
2917 | case 0xfe: /* Grp4 */ |
2918 | grp45: | |
018a98db | 2919 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 2920 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
2921 | goto done; |
2922 | break; | |
ea79849d GN |
2923 | case 0xff: /* Grp5 */ |
2924 | if (c->modrm_reg == 5) | |
2925 | goto jump_far; | |
2926 | goto grp45; | |
6aa8b732 | 2927 | } |
018a98db AK |
2928 | |
2929 | writeback: | |
2930 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 2931 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
2932 | goto done; |
2933 | ||
a682e354 GN |
2934 | if ((c->d & SrcMask) == SrcSI) |
2935 | string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI, | |
d9271123 | 2936 | &c->src); |
a682e354 GN |
2937 | |
2938 | if ((c->d & DstMask) == DstDI) | |
d9271123 GN |
2939 | string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst); |
2940 | ||
2941 | if (c->rep_prefix && (c->d & String)) | |
2942 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
a682e354 | 2943 | |
018a98db | 2944 | /* Commit shadow register state. */ |
ad312c7c | 2945 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); |
5fdbf976 | 2946 | kvm_rip_write(ctxt->vcpu, c->eip); |
018a98db AK |
2947 | |
2948 | done: | |
2949 | if (rc == X86EMUL_UNHANDLEABLE) { | |
2950 | c->eip = saved_eip; | |
2951 | return -1; | |
2952 | } | |
2953 | return 0; | |
6aa8b732 AK |
2954 | |
2955 | twobyte_insn: | |
e4e03ded | 2956 | switch (c->b) { |
6aa8b732 | 2957 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 2958 | switch (c->modrm_reg) { |
6aa8b732 AK |
2959 | u16 size; |
2960 | unsigned long address; | |
2961 | ||
aca7f966 | 2962 | case 0: /* vmcall */ |
e4e03ded | 2963 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
2964 | goto cannot_emulate; |
2965 | ||
7aa81cc0 | 2966 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 2967 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
2968 | goto done; |
2969 | ||
33e3885d | 2970 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 2971 | c->eip = ctxt->eip; |
16286d08 AK |
2972 | /* Disable writeback. */ |
2973 | c->dst.type = OP_NONE; | |
aca7f966 | 2974 | break; |
6aa8b732 | 2975 | case 2: /* lgdt */ |
e4e03ded LV |
2976 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
2977 | &size, &address, c->op_bytes); | |
1b30eaa8 | 2978 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
2979 | goto done; |
2980 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
2981 | /* Disable writeback. */ |
2982 | c->dst.type = OP_NONE; | |
6aa8b732 | 2983 | break; |
aca7f966 | 2984 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
2985 | if (c->modrm_mod == 3) { |
2986 | switch (c->modrm_rm) { | |
2987 | case 1: | |
2988 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 2989 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
2990 | goto done; |
2991 | break; | |
2992 | default: | |
2993 | goto cannot_emulate; | |
2994 | } | |
aca7f966 | 2995 | } else { |
e4e03ded | 2996 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 2997 | &size, &address, |
e4e03ded | 2998 | c->op_bytes); |
1b30eaa8 | 2999 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3000 | goto done; |
3001 | realmode_lidt(ctxt->vcpu, size, address); | |
3002 | } | |
16286d08 AK |
3003 | /* Disable writeback. */ |
3004 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3005 | break; |
3006 | case 4: /* smsw */ | |
16286d08 | 3007 | c->dst.bytes = 2; |
52a46617 | 3008 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3009 | break; |
3010 | case 6: /* lmsw */ | |
93a152be GN |
3011 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) | |
3012 | (c->src.val & 0x0f), ctxt->vcpu); | |
dc7457ea | 3013 | c->dst.type = OP_NONE; |
6aa8b732 | 3014 | break; |
6e1e5ffe GN |
3015 | case 5: /* not defined */ |
3016 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3017 | goto done; | |
6aa8b732 | 3018 | case 7: /* invlpg*/ |
69f55cb1 | 3019 | emulate_invlpg(ctxt->vcpu, c->modrm_ea); |
16286d08 AK |
3020 | /* Disable writeback. */ |
3021 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3022 | break; |
3023 | default: | |
3024 | goto cannot_emulate; | |
3025 | } | |
3026 | break; | |
e99f0507 | 3027 | case 0x05: /* syscall */ |
e54cfa97 TY |
3028 | rc = emulate_syscall(ctxt); |
3029 | if (rc != X86EMUL_CONTINUE) | |
3030 | goto done; | |
e66bb2cc AP |
3031 | else |
3032 | goto writeback; | |
e99f0507 | 3033 | break; |
018a98db AK |
3034 | case 0x06: |
3035 | emulate_clts(ctxt->vcpu); | |
3036 | c->dst.type = OP_NONE; | |
3037 | break; | |
3038 | case 0x08: /* invd */ | |
3039 | case 0x09: /* wbinvd */ | |
3040 | case 0x0d: /* GrpP (prefetch) */ | |
3041 | case 0x18: /* Grp16 (prefetch/nop) */ | |
3042 | c->dst.type = OP_NONE; | |
3043 | break; | |
3044 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3045 | switch (c->modrm_reg) { |
3046 | case 1: | |
3047 | case 5 ... 7: | |
3048 | case 9 ... 15: | |
3049 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3050 | goto done; | |
3051 | } | |
52a46617 | 3052 | c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db AK |
3053 | c->dst.type = OP_NONE; /* no writeback */ |
3054 | break; | |
6aa8b732 | 3055 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3056 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3057 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
3058 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3059 | goto done; | |
3060 | } | |
3061 | emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); | |
a01af5ec | 3062 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3063 | break; |
018a98db | 3064 | case 0x22: /* mov reg, cr */ |
52a46617 | 3065 | ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu); |
018a98db AK |
3066 | c->dst.type = OP_NONE; |
3067 | break; | |
6aa8b732 | 3068 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3069 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3070 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
3071 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3072 | goto done; | |
3073 | } | |
3074 | emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]); | |
a01af5ec | 3075 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3076 | break; |
018a98db AK |
3077 | case 0x30: |
3078 | /* wrmsr */ | |
3079 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3080 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
0e4176a1 | 3081 | if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
c1a5d4f9 | 3082 | kvm_inject_gp(ctxt->vcpu, 0); |
fd525365 | 3083 | goto done; |
018a98db AK |
3084 | } |
3085 | rc = X86EMUL_CONTINUE; | |
3086 | c->dst.type = OP_NONE; | |
3087 | break; | |
3088 | case 0x32: | |
3089 | /* rdmsr */ | |
0e4176a1 | 3090 | if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
c1a5d4f9 | 3091 | kvm_inject_gp(ctxt->vcpu, 0); |
fd525365 | 3092 | goto done; |
018a98db AK |
3093 | } else { |
3094 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3095 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3096 | } | |
3097 | rc = X86EMUL_CONTINUE; | |
3098 | c->dst.type = OP_NONE; | |
3099 | break; | |
e99f0507 | 3100 | case 0x34: /* sysenter */ |
e54cfa97 TY |
3101 | rc = emulate_sysenter(ctxt); |
3102 | if (rc != X86EMUL_CONTINUE) | |
3103 | goto done; | |
8c604352 AP |
3104 | else |
3105 | goto writeback; | |
e99f0507 AP |
3106 | break; |
3107 | case 0x35: /* sysexit */ | |
e54cfa97 TY |
3108 | rc = emulate_sysexit(ctxt); |
3109 | if (rc != X86EMUL_CONTINUE) | |
3110 | goto done; | |
4668f050 AP |
3111 | else |
3112 | goto writeback; | |
e99f0507 | 3113 | break; |
6aa8b732 | 3114 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3115 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3116 | if (!test_cc(c->b, ctxt->eflags)) |
3117 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3118 | break; |
b2833e3c | 3119 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3120 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3121 | jmp_rel(c, c->src.val); |
018a98db AK |
3122 | c->dst.type = OP_NONE; |
3123 | break; | |
0934ac9d MG |
3124 | case 0xa0: /* push fs */ |
3125 | emulate_push_sreg(ctxt, VCPU_SREG_FS); | |
3126 | break; | |
3127 | case 0xa1: /* pop fs */ | |
3128 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3129 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3130 | goto done; |
3131 | break; | |
7de75248 NK |
3132 | case 0xa3: |
3133 | bt: /* bt */ | |
e4f8e039 | 3134 | c->dst.type = OP_NONE; |
e4e03ded LV |
3135 | /* only subword offset */ |
3136 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3137 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3138 | break; |
9bf8ea42 GT |
3139 | case 0xa4: /* shld imm8, r, r/m */ |
3140 | case 0xa5: /* shld cl, r, r/m */ | |
3141 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3142 | break; | |
0934ac9d MG |
3143 | case 0xa8: /* push gs */ |
3144 | emulate_push_sreg(ctxt, VCPU_SREG_GS); | |
3145 | break; | |
3146 | case 0xa9: /* pop gs */ | |
3147 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3148 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3149 | goto done; |
3150 | break; | |
7de75248 NK |
3151 | case 0xab: |
3152 | bts: /* bts */ | |
e4e03ded LV |
3153 | /* only subword offset */ |
3154 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3155 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3156 | break; |
9bf8ea42 GT |
3157 | case 0xac: /* shrd imm8, r, r/m */ |
3158 | case 0xad: /* shrd cl, r, r/m */ | |
3159 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3160 | break; | |
2a7c5b8b GC |
3161 | case 0xae: /* clflush */ |
3162 | break; | |
6aa8b732 AK |
3163 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3164 | /* | |
3165 | * Save real source value, then compare EAX against | |
3166 | * destination. | |
3167 | */ | |
e4e03ded LV |
3168 | c->src.orig_val = c->src.val; |
3169 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3170 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3171 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3172 | /* Success: write back to memory. */ |
e4e03ded | 3173 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3174 | } else { |
3175 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
3176 | c->dst.type = OP_REG; |
3177 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
3178 | } |
3179 | break; | |
6aa8b732 AK |
3180 | case 0xb3: |
3181 | btr: /* btr */ | |
e4e03ded LV |
3182 | /* only subword offset */ |
3183 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3184 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3185 | break; |
6aa8b732 | 3186 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3187 | c->dst.bytes = c->op_bytes; |
3188 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3189 | : (u16) c->src.val; | |
6aa8b732 | 3190 | break; |
6aa8b732 | 3191 | case 0xba: /* Grp8 */ |
e4e03ded | 3192 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3193 | case 0: |
3194 | goto bt; | |
3195 | case 1: | |
3196 | goto bts; | |
3197 | case 2: | |
3198 | goto btr; | |
3199 | case 3: | |
3200 | goto btc; | |
3201 | } | |
3202 | break; | |
7de75248 NK |
3203 | case 0xbb: |
3204 | btc: /* btc */ | |
e4e03ded LV |
3205 | /* only subword offset */ |
3206 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3207 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3208 | break; |
6aa8b732 | 3209 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3210 | c->dst.bytes = c->op_bytes; |
3211 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3212 | (s16) c->src.val; | |
6aa8b732 | 3213 | break; |
a012e65a | 3214 | case 0xc3: /* movnti */ |
e4e03ded LV |
3215 | c->dst.bytes = c->op_bytes; |
3216 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3217 | (u64) c->src.val; | |
a012e65a | 3218 | break; |
6aa8b732 | 3219 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3220 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3221 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 3222 | goto done; |
018a98db | 3223 | c->dst.type = OP_NONE; |
8cdbd2c9 | 3224 | break; |
6aa8b732 AK |
3225 | } |
3226 | goto writeback; | |
3227 | ||
3228 | cannot_emulate: | |
e4e03ded | 3229 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 3230 | c->eip = saved_eip; |
6aa8b732 AK |
3231 | return -1; |
3232 | } |