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KVM: x86 emulator: switch lds/les/lss/lfs/lgs to direct decode
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
0fe59128
AK		 60
61#define OpBits 5 /* Width of operand field */
b1ea50b2 62#define OpMask ((1ull << OpBits) - 1)
a9945549 63
6aa8b732
AK		 64/*
65 * Opcode effective-address decode tables.
66 * Note that we only emulate instructions that have at least one memory
67 * operand (excluding implicit stack references). We assume that stack
68 * references and instruction fetches will never occur in special memory
69 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
70 * not be handled.
71 */
72
73/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 74#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 75/* Destination operand type. */
a9945549
AK		 76#define DstShift 1
77#define ImplicitOps (OpImplicit << DstShift)
78#define DstReg (OpReg << DstShift)
79#define DstMem (OpMem << DstShift)
80#define DstAcc (OpAcc << DstShift)
81#define DstDI (OpDI << DstShift)
82#define DstMem64 (OpMem64 << DstShift)
83#define DstImmUByte (OpImmUByte << DstShift)
84#define DstDX (OpDX << DstShift)
85#define DstMask (OpMask << DstShift)
6aa8b732 86/* Source operand type. */
0fe59128
AK		 87#define SrcShift 6
88#define SrcNone (OpNone << SrcShift)
89#define SrcReg (OpReg << SrcShift)
90#define SrcMem (OpMem << SrcShift)
91#define SrcMem16 (OpMem16 << SrcShift)
92#define SrcMem32 (OpMem32 << SrcShift)
93#define SrcImm (OpImm << SrcShift)
94#define SrcImmByte (OpImmByte << SrcShift)
95#define SrcOne (OpOne << SrcShift)
96#define SrcImmUByte (OpImmUByte << SrcShift)
97#define SrcImmU (OpImmU << SrcShift)
98#define SrcSI (OpSI << SrcShift)
99#define SrcImmFAddr (OpImmFAddr << SrcShift)
100#define SrcMemFAddr (OpMemFAddr << SrcShift)
101#define SrcAcc (OpAcc << SrcShift)
102#define SrcImmU16 (OpImmU16 << SrcShift)
103#define SrcDX (OpDX << SrcShift)
104#define SrcMask (OpMask << SrcShift)
221192bd
MT		 105#define BitOp (1<<11)
106#define MemAbs (1<<12) /* Memory operand is absolute displacement */
107#define String (1<<13) /* String instruction (rep capable) */
108#define Stack (1<<14) /* Stack instruction (push/pop) */
109#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
110#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
111#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
112#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
113#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
114#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 115/* Generic ModRM decode. */
116#define ModRM (1<<19)
117/* Destination is only written; never read. */
118#define Mov (1<<20)
d8769fed 119/* Misc flags */
8ea7d6ae 120#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 121#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 122#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 123#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 124#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 125#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 126#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 127#define No64 (1<<28)
0dc8d10f 128/* Source 2 operand type */
4dd6a57d
AK		 129#define Src2Shift (29)
130#define Src2None (OpNone << Src2Shift)
131#define Src2CL (OpCL << Src2Shift)
132#define Src2ImmByte (OpImmByte << Src2Shift)
133#define Src2One (OpOne << Src2Shift)
134#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 135#define Src2ES (OpES << Src2Shift)
136#define Src2CS (OpCS << Src2Shift)
137#define Src2SS (OpSS << Src2Shift)
138#define Src2DS (OpDS << Src2Shift)
139#define Src2FS (OpFS << Src2Shift)
140#define Src2GS (OpGS << Src2Shift)
4dd6a57d 141#define Src2Mask (OpMask << Src2Shift)
6aa8b732 142
d0e53325
AK		 143#define X2(x...) x, x
144#define X3(x...) X2(x), x
145#define X4(x...) X2(x), X2(x)
146#define X5(x...) X4(x), x
147#define X6(x...) X4(x), X2(x)
148#define X7(x...) X4(x), X3(x)
149#define X8(x...) X4(x), X4(x)
150#define X16(x...) X8(x), X8(x)
83babbca 151
d65b1dee 152struct opcode {
b1ea50b2
AK		 153 u64 flags : 56;
154 u64 intercept : 8;
120df890 155 union {
ef65c889 156 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 157 struct opcode *group;
158 struct group_dual *gdual;
0d7cdee8 159 struct gprefix *gprefix;
120df890 160 } u;
d09beabd 161 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 162};
163
164struct group_dual {
165 struct opcode mod012[8];
166 struct opcode mod3[8];
d65b1dee
AK		 167};
168
0d7cdee8
AK		 169struct gprefix {
170 struct opcode pfx_no;
171 struct opcode pfx_66;
172 struct opcode pfx_f2;
173 struct opcode pfx_f3;
174};
175
6aa8b732 176/* EFLAGS bit definitions. */
d4c6a154
GN		 177#define EFLG_ID (1<<21)
178#define EFLG_VIP (1<<20)
179#define EFLG_VIF (1<<19)
180#define EFLG_AC (1<<18)
b1d86143
AP		 181#define EFLG_VM (1<<17)
182#define EFLG_RF (1<<16)
d4c6a154
GN		 183#define EFLG_IOPL (3<<12)
184#define EFLG_NT (1<<14)
6aa8b732
AK		 185#define EFLG_OF (1<<11)
186#define EFLG_DF (1<<10)
b1d86143 187#define EFLG_IF (1<<9)
d4c6a154 188#define EFLG_TF (1<<8)
6aa8b732
AK		 189#define EFLG_SF (1<<7)
190#define EFLG_ZF (1<<6)
191#define EFLG_AF (1<<4)
192#define EFLG_PF (1<<2)
193#define EFLG_CF (1<<0)
194
62bd430e
MG		 195#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
196#define EFLG_RESERVED_ONE_MASK 2
197
6aa8b732
AK		 198/*
199 * Instruction emulation:
200 * Most instructions are emulated directly via a fragment of inline assembly
201 * code. This allows us to save/restore EFLAGS and thus very easily pick up
202 * any modified flags.
203 */
204
05b3e0c2 205#if defined(CONFIG_X86_64)
6aa8b732
AK		 206#define _LO32 "k" /* force 32-bit operand */
207#define _STK "%%rsp" /* stack pointer */
208#elif defined(__i386__)
209#define _LO32 "" /* force 32-bit operand */
210#define _STK "%%esp" /* stack pointer */
211#endif
212
213/*
214 * These EFLAGS bits are restored from saved value during emulation, and
215 * any changes are written back to the saved value after emulation.
216 */
217#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
218
219/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 220#define _PRE_EFLAGS(_sav, _msk, _tmp) \
221 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
222 "movl %"_sav",%"_LO32 _tmp"; " \
223 "push %"_tmp"; " \
224 "push %"_tmp"; " \
225 "movl %"_msk",%"_LO32 _tmp"; " \
226 "andl %"_LO32 _tmp",("_STK"); " \
227 "pushf; " \
228 "notl %"_LO32 _tmp"; " \
229 "andl %"_LO32 _tmp",("_STK"); " \
230 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
231 "pop %"_tmp"; " \
232 "orl %"_LO32 _tmp",("_STK"); " \
233 "popf; " \
234 "pop %"_sav"; "
6aa8b732
AK		 235
236/* After executing instruction: write-back necessary bits in EFLAGS. */
237#define _POST_EFLAGS(_sav, _msk, _tmp) \
238 /* _sav |= EFLAGS & _msk; */ \
239 "pushf; " \
240 "pop %"_tmp"; " \
241 "andl %"_msk",%"_LO32 _tmp"; " \
242 "orl %"_LO32 _tmp",%"_sav"; "
243
dda96d8f
AK		 244#ifdef CONFIG_X86_64
245#define ON64(x) x
246#else
247#define ON64(x)
248#endif
249
a31b9cea 250#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 251 do { \
252 __asm__ __volatile__ ( \
253 _PRE_EFLAGS("0", "4", "2") \
254 _op _suffix " %"_x"3,%1; " \
255 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 256 : "=m" ((ctxt)->eflags), \
257 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 258 "=&r" (_tmp) \
a31b9cea 259 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 260 } while (0)
6b7ad61f
AK		 261
262
6aa8b732 263/* Raw emulation: instruction has two explicit operands. */
a31b9cea 264#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 265 do { \
266 unsigned long _tmp; \
267 \
a31b9cea 268 switch ((ctxt)->dst.bytes) { \
6b7ad61f 269 case 2: \
a31b9cea 270 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 271 break; \
272 case 4: \
a31b9cea 273 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 274 break; \
275 case 8: \
a31b9cea 276 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 277 break; \
278 } \
6aa8b732
AK		 279 } while (0)
280
a31b9cea 281#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 282 do { \
6b7ad61f 283 unsigned long _tmp; \
a31b9cea 284 switch ((ctxt)->dst.bytes) { \
6aa8b732 285 case 1: \
a31b9cea 286 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 287 break; \
288 default: \
a31b9cea 289 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 290 _wx, _wy, _lx, _ly, _qx, _qy); \
291 break; \
292 } \
293 } while (0)
294
295/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 296#define emulate_2op_SrcB(ctxt, _op) \
297 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 298
299/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 300#define emulate_2op_SrcV(ctxt, _op) \
301 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 302
303/* Source operand is word, long or quad sized. */
a31b9cea
AK		 304#define emulate_2op_SrcV_nobyte(ctxt, _op) \
305 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 306
d175226a 307/* Instruction has three operands and one operand is stored in ECX register */
29053a60 308#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 309 do { \
310 unsigned long _tmp; \
761441b9
AK		 311 _type _clv = (ctxt)->src2.val; \
312 _type _srcv = (ctxt)->src.val; \
313 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 314 \
315 __asm__ __volatile__ ( \
316 _PRE_EFLAGS("0", "5", "2") \
317 _op _suffix " %4,%1 \n" \
318 _POST_EFLAGS("0", "5", "2") \
761441b9 319 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 320 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
321 ); \
322 \
761441b9
AK		 323 (ctxt)->src2.val = (unsigned long) _clv; \
324 (ctxt)->src2.val = (unsigned long) _srcv; \
325 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 326 } while (0)
327
761441b9 328#define emulate_2op_cl(ctxt, _op) \
7295261c 329 do { \
761441b9 330 switch ((ctxt)->dst.bytes) { \
7295261c 331 case 2: \
29053a60 332 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 333 break; \
334 case 4: \
29053a60 335 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 336 break; \
337 case 8: \
29053a60 338 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 339 break; \
340 } \
d175226a
GT		 341 } while (0)
342
d1eef45d 343#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 344 do { \
345 unsigned long _tmp; \
346 \
dda96d8f
AK		 347 __asm__ __volatile__ ( \
348 _PRE_EFLAGS("0", "3", "2") \
349 _op _suffix " %1; " \
350 _POST_EFLAGS("0", "3", "2") \
d1eef45d 351 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 352 "=&r" (_tmp) \
353 : "i" (EFLAGS_MASK)); \
354 } while (0)
355
356/* Instruction has only one explicit operand (no source operand). */
d1eef45d 357#define emulate_1op(ctxt, _op) \
dda96d8f 358 do { \
d1eef45d
AK		 359 switch ((ctxt)->dst.bytes) { \
360 case 1: __emulate_1op(ctxt, _op, "b"); break; \
361 case 2: __emulate_1op(ctxt, _op, "w"); break; \
362 case 4: __emulate_1op(ctxt, _op, "l"); break; \
363 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 364 } \
365 } while (0)
366
e8f2b1d6 367#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 368 do { \
369 unsigned long _tmp; \
e8f2b1d6
AK		 370 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
371 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 372 \
373 __asm__ __volatile__ ( \
374 _PRE_EFLAGS("0", "5", "1") \
375 "1: \n\t" \
376 _op _suffix " %6; " \
377 "2: \n\t" \
378 _POST_EFLAGS("0", "5", "1") \
379 ".pushsection .fixup,\"ax\" \n\t" \
380 "3: movb $1, %4 \n\t" \
381 "jmp 2b \n\t" \
382 ".popsection \n\t" \
383 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 384 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
385 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
386 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
387 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 388 } while (0)
389
3f9f53b0 390/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 391#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 392 do { \
e8f2b1d6 393 switch((ctxt)->src.bytes) { \
7295261c 394 case 1: \
e8f2b1d6 395 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 396 break; \
397 case 2: \
e8f2b1d6 398 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 399 break; \
400 case 4: \
e8f2b1d6 401 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 402 break; \
403 case 8: ON64( \
e8f2b1d6 404 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 405 break; \
406 } \
407 } while (0)
408
8a76d7f2
JR		 409static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
410 enum x86_intercept intercept,
411 enum x86_intercept_stage stage)
412{
413 struct x86_instruction_info info = {
414 .intercept = intercept,
9dac77fa
AK		 415 .rep_prefix = ctxt->rep_prefix,
416 .modrm_mod = ctxt->modrm_mod,
417 .modrm_reg = ctxt->modrm_reg,
418 .modrm_rm = ctxt->modrm_rm,
419 .src_val = ctxt->src.val64,
420 .src_bytes = ctxt->src.bytes,
421 .dst_bytes = ctxt->dst.bytes,
422 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 423 .next_rip = ctxt->eip,
424 };
425
2953538e 426 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 427}
428
9dac77fa 429static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 430{
9dac77fa 431 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 432}
433
6aa8b732 434/* Access/update address held in a register, based on addressing mode. */
e4706772 435static inline unsigned long
9dac77fa 436address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 437{
9dac77fa 438 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 439 return reg;
440 else
9dac77fa 441 return reg & ad_mask(ctxt);
e4706772
HH		 442}
443
444static inline unsigned long
9dac77fa 445register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 446{
9dac77fa 447 return address_mask(ctxt, reg);
e4706772
HH		 448}
449
7a957275 450static inline void
9dac77fa 451register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 452{
9dac77fa 453 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 454 *reg += inc;
455 else
9dac77fa 456 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 457}
6aa8b732 458
9dac77fa 459static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 460{
9dac77fa 461 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 462}
098c937b 463
56697687
AK		 464static u32 desc_limit_scaled(struct desc_struct *desc)
465{
466 u32 limit = get_desc_limit(desc);
467
468 return desc->g ? (limit << 12) | 0xfff : limit;
469}
470
9dac77fa 471static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 472{
9dac77fa
AK		 473 ctxt->has_seg_override = true;
474 ctxt->seg_override = seg;
7a5b56df
AK		 475}
476
7b105ca2 477static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 478{
479 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
480 return 0;
481
7b105ca2 482 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 483}
484
9dac77fa 485static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 486{
9dac77fa 487 if (!ctxt->has_seg_override)
7a5b56df
AK		 488 return 0;
489
9dac77fa 490 return ctxt->seg_override;
7a5b56df
AK		 491}
492
35d3d4a1
AK		 493static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
494 u32 error, bool valid)
54b8486f 495{
da9cb575
AK		 496 ctxt->exception.vector = vec;
497 ctxt->exception.error_code = error;
498 ctxt->exception.error_code_valid = valid;
35d3d4a1 499 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 500}
501
3b88e41a
JR		 502static int emulate_db(struct x86_emulate_ctxt *ctxt)
503{
504 return emulate_exception(ctxt, DB_VECTOR, 0, false);
505}
506
35d3d4a1 507static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 508{
35d3d4a1 509 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 510}
511
618ff15d
AK		 512static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
513{
514 return emulate_exception(ctxt, SS_VECTOR, err, true);
515}
516
35d3d4a1 517static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 518{
35d3d4a1 519 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 520}
521
35d3d4a1 522static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 523{
35d3d4a1 524 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 525}
526
34d1f490
AK		 527static int emulate_de(struct x86_emulate_ctxt *ctxt)
528{
35d3d4a1 529 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 530}
531
1253791d
AK		 532static int emulate_nm(struct x86_emulate_ctxt *ctxt)
533{
534 return emulate_exception(ctxt, NM_VECTOR, 0, false);
535}
536
1aa36616
AK		 537static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
538{
539 u16 selector;
540 struct desc_struct desc;
541
542 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
543 return selector;
544}
545
546static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
547 unsigned seg)
548{
549 u16 dummy;
550 u32 base3;
551 struct desc_struct desc;
552
553 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
554 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
555}
556
3d9b938e 557static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 558 struct segmented_address addr,
3d9b938e 559 unsigned size, bool write, bool fetch,
52fd8b44
AK		 560 ulong *linear)
561{
618ff15d
AK		 562 struct desc_struct desc;
563 bool usable;
52fd8b44 564 ulong la;
618ff15d 565 u32 lim;
1aa36616 566 u16 sel;
618ff15d 567 unsigned cpl, rpl;
52fd8b44 568
7b105ca2 569 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 570 switch (ctxt->mode) {
571 case X86EMUL_MODE_REAL:
572 break;
573 case X86EMUL_MODE_PROT64:
574 if (((signed long)la << 16) >> 16 != la)
575 return emulate_gp(ctxt, 0);
576 break;
577 default:
1aa36616
AK		 578 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
579 addr.seg);
618ff15d
AK		 580 if (!usable)
581 goto bad;
582 /* code segment or read-only data segment */
583 if (((desc.type & 8) || !(desc.type & 2)) && write)
584 goto bad;
585 /* unreadable code segment */
3d9b938e 586 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 587 goto bad;
588 lim = desc_limit_scaled(&desc);
589 if ((desc.type & 8) || !(desc.type & 4)) {
590 /* expand-up segment */
591 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
592 goto bad;
593 } else {
594 /* exapand-down segment */
595 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
596 goto bad;
597 lim = desc.d ? 0xffffffff : 0xffff;
598 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
599 goto bad;
600 }
717746e3 601 cpl = ctxt->ops->cpl(ctxt);
1aa36616 602 rpl = sel & 3;
618ff15d
AK		 603 cpl = max(cpl, rpl);
604 if (!(desc.type & 8)) {
605 /* data segment */
606 if (cpl > desc.dpl)
607 goto bad;
608 } else if ((desc.type & 8) && !(desc.type & 4)) {
609 /* nonconforming code segment */
610 if (cpl != desc.dpl)
611 goto bad;
612 } else if ((desc.type & 8) && (desc.type & 4)) {
613 /* conforming code segment */
614 if (cpl < desc.dpl)
615 goto bad;
616 }
617 break;
618 }
9dac77fa 619 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 620 la &= (u32)-1;
621 *linear = la;
622 return X86EMUL_CONTINUE;
618ff15d
AK		 623bad:
624 if (addr.seg == VCPU_SREG_SS)
625 return emulate_ss(ctxt, addr.seg);
626 else
627 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 628}
629
3d9b938e
NE		 630static int linearize(struct x86_emulate_ctxt *ctxt,
631 struct segmented_address addr,
632 unsigned size, bool write,
633 ulong *linear)
634{
635 return __linearize(ctxt, addr, size, write, false, linear);
636}
637
638
3ca3ac4d
AK		 639static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
640 struct segmented_address addr,
641 void *data,
642 unsigned size)
643{
9fa088f4
AK		 644 int rc;
645 ulong linear;
646
83b8795a 647 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 648 if (rc != X86EMUL_CONTINUE)
649 return rc;
0f65dd70 650 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 651}
652
807941b1
TY		 653/*
654 * Fetch the next byte of the instruction being emulated which is pointed to
655 * by ctxt->_eip, then increment ctxt->_eip.
656 *
657 * Also prefetch the remaining bytes of the instruction without crossing page
658 * boundary if they are not in fetch_cache yet.
659 */
660static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 661{
9dac77fa 662 struct fetch_cache *fc = &ctxt->fetch;
62266869 663 int rc;
2fb53ad8 664 int size, cur_size;
62266869 665
807941b1 666 if (ctxt->_eip == fc->end) {
3d9b938e 667 unsigned long linear;
807941b1
TY		 668 struct segmented_address addr = { .seg = VCPU_SREG_CS,
669 .ea = ctxt->_eip };
2fb53ad8 670 cur_size = fc->end - fc->start;
807941b1
TY		 671 size = min(15UL - cur_size,
672 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 673 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 674 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 675 return rc;
ef5d75cc
TY		 676 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
677 size, &ctxt->exception);
7d88bb48 678 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 679 return rc;
2fb53ad8 680 fc->end += size;
62266869 681 }
807941b1
TY		 682 *dest = fc->data[ctxt->_eip - fc->start];
683 ctxt->_eip++;
3e2815e9 684 return X86EMUL_CONTINUE;
62266869
AK		 685}
686
687static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 688 void *dest, unsigned size)
62266869 689{
3e2815e9 690 int rc;
62266869 691
eb3c79e6 692 /* x86 instructions are limited to 15 bytes. */
7d88bb48 693 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 694 return X86EMUL_UNHANDLEABLE;
62266869 695 while (size--) {
807941b1 696 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 697 if (rc != X86EMUL_CONTINUE)
62266869
AK		 698 return rc;
699 }
3e2815e9 700 return X86EMUL_CONTINUE;
62266869
AK		 701}
702
67cbc90d 703/* Fetch next part of the instruction being emulated. */
e85a1085 704#define insn_fetch(_type, _ctxt) \
67cbc90d 705({ unsigned long _x; \
e85a1085 706 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 707 if (rc != X86EMUL_CONTINUE) \
708 goto done; \
67cbc90d
TY		 709 (_type)_x; \
710})
711
807941b1
TY		 712#define insn_fetch_arr(_arr, _size, _ctxt) \
713({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 714 if (rc != X86EMUL_CONTINUE) \
715 goto done; \
67cbc90d
TY		 716})
717
1e3c5cb0
RR		 718/*
719 * Given the 'reg' portion of a ModRM byte, and a register block, return a
720 * pointer into the block that addresses the relevant register.
721 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
722 */
723static void *decode_register(u8 modrm_reg, unsigned long *regs,
724 int highbyte_regs)
6aa8b732
AK		 725{
726 void *p;
727
728 p = &regs[modrm_reg];
729 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
730 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
731 return p;
732}
733
734static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 735 struct segmented_address addr,
6aa8b732
AK		 736 u16 *size, unsigned long *address, int op_bytes)
737{
738 int rc;
739
740 if (op_bytes == 2)
741 op_bytes = 3;
742 *address = 0;
3ca3ac4d 743 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 744 if (rc != X86EMUL_CONTINUE)
6aa8b732 745 return rc;
30b31ab6 746 addr.ea += 2;
3ca3ac4d 747 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 748 return rc;
749}
750
bbe9abbd
NK		 751static int test_cc(unsigned int condition, unsigned int flags)
752{
753 int rc = 0;
754
755 switch ((condition & 15) >> 1) {
756 case 0: /* o */
757 rc |= (flags & EFLG_OF);
758 break;
759 case 1: /* b/c/nae */
760 rc |= (flags & EFLG_CF);
761 break;
762 case 2: /* z/e */
763 rc |= (flags & EFLG_ZF);
764 break;
765 case 3: /* be/na */
766 rc |= (flags & (EFLG_CF|EFLG_ZF));
767 break;
768 case 4: /* s */
769 rc |= (flags & EFLG_SF);
770 break;
771 case 5: /* p/pe */
772 rc |= (flags & EFLG_PF);
773 break;
774 case 7: /* le/ng */
775 rc |= (flags & EFLG_ZF);
776 /* fall through */
777 case 6: /* l/nge */
778 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
779 break;
780 }
781
782 /* Odd condition identifiers (lsb == 1) have inverted sense. */
783 return (!!rc ^ (condition & 1));
784}
785
91ff3cb4
AK		 786static void fetch_register_operand(struct operand *op)
787{
788 switch (op->bytes) {
789 case 1:
790 op->val = *(u8 *)op->addr.reg;
791 break;
792 case 2:
793 op->val = *(u16 *)op->addr.reg;
794 break;
795 case 4:
796 op->val = *(u32 *)op->addr.reg;
797 break;
798 case 8:
799 op->val = *(u64 *)op->addr.reg;
800 break;
801 }
802}
803
1253791d
AK		 804static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
805{
806 ctxt->ops->get_fpu(ctxt);
807 switch (reg) {
808 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
809 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
810 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
811 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
812 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
813 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
814 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
815 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
816#ifdef CONFIG_X86_64
817 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
818 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
819 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
820 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
821 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
822 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
823 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
824 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
825#endif
826 default: BUG();
827 }
828 ctxt->ops->put_fpu(ctxt);
829}
830
831static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
832 int reg)
833{
834 ctxt->ops->get_fpu(ctxt);
835 switch (reg) {
836 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
837 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
838 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
839 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
840 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
841 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
842 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
843 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
844#ifdef CONFIG_X86_64
845 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
846 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
847 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
848 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
849 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
850 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
851 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
852 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
853#endif
854 default: BUG();
855 }
856 ctxt->ops->put_fpu(ctxt);
857}
858
859static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
860 struct operand *op,
3c118e24
AK		 861 int inhibit_bytereg)
862{
9dac77fa
AK		 863 unsigned reg = ctxt->modrm_reg;
864 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 865
9dac77fa
AK		 866 if (!(ctxt->d & ModRM))
867 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 868
9dac77fa 869 if (ctxt->d & Sse) {
1253791d
AK		 870 op->type = OP_XMM;
871 op->bytes = 16;
872 op->addr.xmm = reg;
873 read_sse_reg(ctxt, &op->vec_val, reg);
874 return;
875 }
876
3c118e24 877 op->type = OP_REG;
9dac77fa
AK		 878 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
879 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 880 op->bytes = 1;
881 } else {
9dac77fa
AK		 882 op->addr.reg = decode_register(reg, ctxt->regs, 0);
883 op->bytes = ctxt->op_bytes;
3c118e24 884 }
91ff3cb4 885 fetch_register_operand(op);
3c118e24
AK		 886 op->orig_val = op->val;
887}
888
1c73ef66 889static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 890 struct operand *op)
1c73ef66 891{
1c73ef66 892 u8 sib;
f5b4edcd 893 int index_reg = 0, base_reg = 0, scale;
3e2815e9 894 int rc = X86EMUL_CONTINUE;
2dbd0dd7 895 ulong modrm_ea = 0;
1c73ef66 896
9dac77fa
AK		 897 if (ctxt->rex_prefix) {
898 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
899 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
900 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 901 }
902
e85a1085 903 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 904 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
905 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
906 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
907 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 908
9dac77fa 909 if (ctxt->modrm_mod == 3) {
2dbd0dd7 910 op->type = OP_REG;
9dac77fa
AK		 911 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
912 op->addr.reg = decode_register(ctxt->modrm_rm,
913 ctxt->regs, ctxt->d & ByteOp);
914 if (ctxt->d & Sse) {
1253791d
AK		 915 op->type = OP_XMM;
916 op->bytes = 16;
9dac77fa
AK		 917 op->addr.xmm = ctxt->modrm_rm;
918 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 919 return rc;
920 }
2dbd0dd7 921 fetch_register_operand(op);
1c73ef66
AK		 922 return rc;
923 }
924
2dbd0dd7
AK		 925 op->type = OP_MEM;
926
9dac77fa
AK		 927 if (ctxt->ad_bytes == 2) {
928 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
929 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
930 unsigned si = ctxt->regs[VCPU_REGS_RSI];
931 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 932
933 /* 16-bit ModR/M decode. */
9dac77fa 934 switch (ctxt->modrm_mod) {
1c73ef66 935 case 0:
9dac77fa 936 if (ctxt->modrm_rm == 6)
e85a1085 937 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 938 break;
939 case 1:
e85a1085 940 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 941 break;
942 case 2:
e85a1085 943 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 944 break;
945 }
9dac77fa 946 switch (ctxt->modrm_rm) {
1c73ef66 947 case 0:
2dbd0dd7 948 modrm_ea += bx + si;
1c73ef66
AK		 949 break;
950 case 1:
2dbd0dd7 951 modrm_ea += bx + di;
1c73ef66
AK		 952 break;
953 case 2:
2dbd0dd7 954 modrm_ea += bp + si;
1c73ef66
AK		 955 break;
956 case 3:
2dbd0dd7 957 modrm_ea += bp + di;
1c73ef66
AK		 958 break;
959 case 4:
2dbd0dd7 960 modrm_ea += si;
1c73ef66
AK		 961 break;
962 case 5:
2dbd0dd7 963 modrm_ea += di;
1c73ef66
AK		 964 break;
965 case 6:
9dac77fa 966 if (ctxt->modrm_mod != 0)
2dbd0dd7 967 modrm_ea += bp;
1c73ef66
AK		 968 break;
969 case 7:
2dbd0dd7 970 modrm_ea += bx;
1c73ef66
AK		 971 break;
972 }
9dac77fa
AK		 973 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
974 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
975 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 976 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 977 } else {
978 /* 32/64-bit ModR/M decode. */
9dac77fa 979 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 980 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 981 index_reg |= (sib >> 3) & 7;
982 base_reg |= sib & 7;
983 scale = sib >> 6;
984
9dac77fa 985 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 986 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 987 else
9dac77fa 988 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 989 if (index_reg != 4)
9dac77fa
AK		 990 modrm_ea += ctxt->regs[index_reg] << scale;
991 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 992 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 993 ctxt->rip_relative = 1;
84411d85 994 } else
9dac77fa
AK		 995 modrm_ea += ctxt->regs[ctxt->modrm_rm];
996 switch (ctxt->modrm_mod) {
1c73ef66 997 case 0:
9dac77fa 998 if (ctxt->modrm_rm == 5)
e85a1085 999 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1000 break;
1001 case 1:
e85a1085 1002 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1003 break;
1004 case 2:
e85a1085 1005 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1006 break;
1007 }
1008 }
90de84f5 1009 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1010done:
1011 return rc;
1012}
1013
1014static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1015 struct operand *op)
1c73ef66 1016{
3e2815e9 1017 int rc = X86EMUL_CONTINUE;
1c73ef66 1018
2dbd0dd7 1019 op->type = OP_MEM;
9dac77fa 1020 switch (ctxt->ad_bytes) {
1c73ef66 1021 case 2:
e85a1085 1022 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1023 break;
1024 case 4:
e85a1085 1025 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1026 break;
1027 case 8:
e85a1085 1028 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1029 break;
1030 }
1031done:
1032 return rc;
1033}
1034
9dac77fa 1035static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1036{
7129eeca 1037 long sv = 0, mask;
35c843c4 1038
9dac77fa
AK		 1039 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1040 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1041
9dac77fa
AK		 1042 if (ctxt->src.bytes == 2)
1043 sv = (s16)ctxt->src.val & (s16)mask;
1044 else if (ctxt->src.bytes == 4)
1045 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1046
9dac77fa 1047 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1048 }
ba7ff2b7
WY		 1049
1050 /* only subword offset */
9dac77fa 1051 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1052}
1053
dde7e6d1 1054static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1055 unsigned long addr, void *dest, unsigned size)
6aa8b732 1056{
dde7e6d1 1057 int rc;
9dac77fa 1058 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1059
dde7e6d1
AK		 1060 while (size) {
1061 int n = min(size, 8u);
1062 size -= n;
1063 if (mc->pos < mc->end)
1064 goto read_cached;
5cd21917 1065
7b105ca2
TY		 1066 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1067 &ctxt->exception);
dde7e6d1
AK		 1068 if (rc != X86EMUL_CONTINUE)
1069 return rc;
1070 mc->end += n;
6aa8b732 1071
dde7e6d1
AK		 1072 read_cached:
1073 memcpy(dest, mc->data + mc->pos, n);
1074 mc->pos += n;
1075 dest += n;
1076 addr += n;
6aa8b732 1077 }
dde7e6d1
AK		 1078 return X86EMUL_CONTINUE;
1079}
6aa8b732 1080
3ca3ac4d
AK		 1081static int segmented_read(struct x86_emulate_ctxt *ctxt,
1082 struct segmented_address addr,
1083 void *data,
1084 unsigned size)
1085{
9fa088f4
AK		 1086 int rc;
1087 ulong linear;
1088
83b8795a 1089 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1090 if (rc != X86EMUL_CONTINUE)
1091 return rc;
7b105ca2 1092 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1093}
1094
1095static int segmented_write(struct x86_emulate_ctxt *ctxt,
1096 struct segmented_address addr,
1097 const void *data,
1098 unsigned size)
1099{
9fa088f4
AK		 1100 int rc;
1101 ulong linear;
1102
83b8795a 1103 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1104 if (rc != X86EMUL_CONTINUE)
1105 return rc;
0f65dd70
AK		 1106 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1107 &ctxt->exception);
3ca3ac4d
AK		 1108}
1109
1110static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1111 struct segmented_address addr,
1112 const void *orig_data, const void *data,
1113 unsigned size)
1114{
9fa088f4
AK		 1115 int rc;
1116 ulong linear;
1117
83b8795a 1118 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1119 if (rc != X86EMUL_CONTINUE)
1120 return rc;
0f65dd70
AK		 1121 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1122 size, &ctxt->exception);
3ca3ac4d
AK		 1123}
1124
dde7e6d1 1125static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1126 unsigned int size, unsigned short port,
1127 void *dest)
1128{
9dac77fa 1129 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1130
dde7e6d1 1131 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1132 unsigned int in_page, n;
9dac77fa
AK		 1133 unsigned int count = ctxt->rep_prefix ?
1134 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1135 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1136 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1137 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1138 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1139 count);
1140 if (n == 0)
1141 n = 1;
1142 rc->pos = rc->end = 0;
7b105ca2 1143 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1144 return 0;
1145 rc->end = n * size;
6aa8b732
AK		 1146 }
1147
dde7e6d1
AK		 1148 memcpy(dest, rc->data + rc->pos, size);
1149 rc->pos += size;
1150 return 1;
1151}
6aa8b732 1152
dde7e6d1 1153static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1154 u16 selector, struct desc_ptr *dt)
1155{
7b105ca2
TY		 1156 struct x86_emulate_ops *ops = ctxt->ops;
1157
dde7e6d1
AK		 1158 if (selector & 1 << 2) {
1159 struct desc_struct desc;
1aa36616
AK		 1160 u16 sel;
1161
dde7e6d1 1162 memset (dt, 0, sizeof *dt);
1aa36616 1163 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1164 return;
e09d082c 1165
dde7e6d1
AK		 1166 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1167 dt->address = get_desc_base(&desc);
1168 } else
4bff1e86 1169 ops->get_gdt(ctxt, dt);
dde7e6d1 1170}
120df890 1171
dde7e6d1
AK		 1172/* allowed just for 8 bytes segments */
1173static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1174 u16 selector, struct desc_struct *desc)
1175{
1176 struct desc_ptr dt;
1177 u16 index = selector >> 3;
dde7e6d1 1178 ulong addr;
120df890 1179
7b105ca2 1180 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1181
35d3d4a1
AK		 1182 if (dt.size < index * 8 + 7)
1183 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1184
7b105ca2
TY		 1185 addr = dt.address + index * 8;
1186 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1187 &ctxt->exception);
dde7e6d1 1188}
ef65c889 1189
dde7e6d1
AK		 1190/* allowed just for 8 bytes segments */
1191static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1192 u16 selector, struct desc_struct *desc)
1193{
1194 struct desc_ptr dt;
1195 u16 index = selector >> 3;
dde7e6d1 1196 ulong addr;
6aa8b732 1197
7b105ca2 1198 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1199
35d3d4a1
AK		 1200 if (dt.size < index * 8 + 7)
1201 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1202
dde7e6d1 1203 addr = dt.address + index * 8;
7b105ca2
TY		 1204 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1205 &ctxt->exception);
dde7e6d1 1206}
c7e75a3d 1207
5601d05b 1208/* Does not support long mode */
dde7e6d1 1209static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1210 u16 selector, int seg)
1211{
1212 struct desc_struct seg_desc;
1213 u8 dpl, rpl, cpl;
1214 unsigned err_vec = GP_VECTOR;
1215 u32 err_code = 0;
1216 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1217 int ret;
69f55cb1 1218
dde7e6d1 1219 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1220
dde7e6d1
AK		 1221 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1222 || ctxt->mode == X86EMUL_MODE_REAL) {
1223 /* set real mode segment descriptor */
1224 set_desc_base(&seg_desc, selector << 4);
1225 set_desc_limit(&seg_desc, 0xffff);
1226 seg_desc.type = 3;
1227 seg_desc.p = 1;
1228 seg_desc.s = 1;
1229 goto load;
1230 }
1231
1232 /* NULL selector is not valid for TR, CS and SS */
1233 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1234 && null_selector)
1235 goto exception;
1236
1237 /* TR should be in GDT only */
1238 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1239 goto exception;
1240
1241 if (null_selector) /* for NULL selector skip all following checks */
1242 goto load;
1243
7b105ca2 1244 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1245 if (ret != X86EMUL_CONTINUE)
1246 return ret;
1247
1248 err_code = selector & 0xfffc;
1249 err_vec = GP_VECTOR;
1250
1251 /* can't load system descriptor into segment selecor */
1252 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1253 goto exception;
1254
1255 if (!seg_desc.p) {
1256 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1257 goto exception;
1258 }
1259
1260 rpl = selector & 3;
1261 dpl = seg_desc.dpl;
7b105ca2 1262 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1263
1264 switch (seg) {
1265 case VCPU_SREG_SS:
1266 /*
1267 * segment is not a writable data segment or segment
1268 * selector's RPL != CPL or segment selector's RPL != CPL
1269 */
1270 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1271 goto exception;
6aa8b732 1272 break;
dde7e6d1
AK		 1273 case VCPU_SREG_CS:
1274 if (!(seg_desc.type & 8))
1275 goto exception;
1276
1277 if (seg_desc.type & 4) {
1278 /* conforming */
1279 if (dpl > cpl)
1280 goto exception;
1281 } else {
1282 /* nonconforming */
1283 if (rpl > cpl || dpl != cpl)
1284 goto exception;
1285 }
1286 /* CS(RPL) <- CPL */
1287 selector = (selector & 0xfffc) | cpl;
6aa8b732 1288 break;
dde7e6d1
AK		 1289 case VCPU_SREG_TR:
1290 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1291 goto exception;
1292 break;
1293 case VCPU_SREG_LDTR:
1294 if (seg_desc.s || seg_desc.type != 2)
1295 goto exception;
1296 break;
1297 default: /* DS, ES, FS, or GS */
4e62417b 1298 /*
dde7e6d1
AK		 1299 * segment is not a data or readable code segment or
1300 * ((segment is a data or nonconforming code segment)
1301 * and (both RPL and CPL > DPL))
4e62417b 1302 */
dde7e6d1
AK		 1303 if ((seg_desc.type & 0xa) == 0x8 ||
1304 (((seg_desc.type & 0xc) != 0xc) &&
1305 (rpl > dpl && cpl > dpl)))
1306 goto exception;
6aa8b732 1307 break;
dde7e6d1
AK		 1308 }
1309
1310 if (seg_desc.s) {
1311 /* mark segment as accessed */
1312 seg_desc.type |= 1;
7b105ca2 1313 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1314 if (ret != X86EMUL_CONTINUE)
1315 return ret;
1316 }
1317load:
7b105ca2 1318 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1319 return X86EMUL_CONTINUE;
1320exception:
1321 emulate_exception(ctxt, err_vec, err_code, true);
1322 return X86EMUL_PROPAGATE_FAULT;
1323}
1324
31be40b3
WY		 1325static void write_register_operand(struct operand *op)
1326{
1327 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1328 switch (op->bytes) {
1329 case 1:
1330 *(u8 *)op->addr.reg = (u8)op->val;
1331 break;
1332 case 2:
1333 *(u16 *)op->addr.reg = (u16)op->val;
1334 break;
1335 case 4:
1336 *op->addr.reg = (u32)op->val;
1337 break; /* 64b: zero-extend */
1338 case 8:
1339 *op->addr.reg = op->val;
1340 break;
1341 }
1342}
1343
adddcecf 1344static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1345{
1346 int rc;
dde7e6d1 1347
9dac77fa 1348 switch (ctxt->dst.type) {
dde7e6d1 1349 case OP_REG:
9dac77fa 1350 write_register_operand(&ctxt->dst);
6aa8b732 1351 break;
dde7e6d1 1352 case OP_MEM:
9dac77fa 1353 if (ctxt->lock_prefix)
3ca3ac4d 1354 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1355 ctxt->dst.addr.mem,
1356 &ctxt->dst.orig_val,
1357 &ctxt->dst.val,
1358 ctxt->dst.bytes);
341de7e3 1359 else
3ca3ac4d 1360 rc = segmented_write(ctxt,
9dac77fa
AK		 1361 ctxt->dst.addr.mem,
1362 &ctxt->dst.val,
1363 ctxt->dst.bytes);
dde7e6d1
AK		 1364 if (rc != X86EMUL_CONTINUE)
1365 return rc;
a682e354 1366 break;
1253791d 1367 case OP_XMM:
9dac77fa 1368 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1369 break;
dde7e6d1
AK		 1370 case OP_NONE:
1371 /* no writeback */
414e6277 1372 break;
dde7e6d1 1373 default:
414e6277 1374 break;
6aa8b732 1375 }
dde7e6d1
AK		 1376 return X86EMUL_CONTINUE;
1377}
6aa8b732 1378
4487b3b4 1379static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1380{
4179bb02 1381 struct segmented_address addr;
0dc8d10f 1382
9dac77fa
AK		 1383 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1384 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1385 addr.seg = VCPU_SREG_SS;
1386
1387 /* Disable writeback. */
9dac77fa
AK		 1388 ctxt->dst.type = OP_NONE;
1389 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1390}
69f55cb1 1391
dde7e6d1 1392static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1393 void *dest, int len)
1394{
dde7e6d1 1395 int rc;
90de84f5 1396 struct segmented_address addr;
8b4caf66 1397
9dac77fa 1398 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1399 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1400 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1401 if (rc != X86EMUL_CONTINUE)
1402 return rc;
1403
9dac77fa 1404 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1405 return rc;
8b4caf66
LV		 1406}
1407
c54fe504
TY		 1408static int em_pop(struct x86_emulate_ctxt *ctxt)
1409{
9dac77fa 1410 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1411}
1412
dde7e6d1 1413static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1414 void *dest, int len)
9de41573
GN		 1415{
1416 int rc;
dde7e6d1
AK		 1417 unsigned long val, change_mask;
1418 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1419 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1420
3b9be3bf 1421 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1422 if (rc != X86EMUL_CONTINUE)
1423 return rc;
9de41573 1424
dde7e6d1
AK		 1425 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1426 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1427
dde7e6d1
AK		 1428 switch(ctxt->mode) {
1429 case X86EMUL_MODE_PROT64:
1430 case X86EMUL_MODE_PROT32:
1431 case X86EMUL_MODE_PROT16:
1432 if (cpl == 0)
1433 change_mask |= EFLG_IOPL;
1434 if (cpl <= iopl)
1435 change_mask |= EFLG_IF;
1436 break;
1437 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1438 if (iopl < 3)
1439 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1440 change_mask |= EFLG_IF;
1441 break;
1442 default: /* real mode */
1443 change_mask |= (EFLG_IOPL | EFLG_IF);
1444 break;
9de41573 1445 }
dde7e6d1
AK		 1446
1447 *(unsigned long *)dest =
1448 (ctxt->eflags & ~change_mask) | (val & change_mask);
1449
1450 return rc;
9de41573
GN		 1451}
1452
62aaa2f0
TY		 1453static int em_popf(struct x86_emulate_ctxt *ctxt)
1454{
9dac77fa
AK		 1455 ctxt->dst.type = OP_REG;
1456 ctxt->dst.addr.reg = &ctxt->eflags;
1457 ctxt->dst.bytes = ctxt->op_bytes;
1458 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1459}
1460
7b105ca2 1461static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1462{
9dac77fa 1463 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1464
4487b3b4 1465 return em_push(ctxt);
7b262e90
GN		 1466}
1467
7b105ca2 1468static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1469{
dde7e6d1
AK		 1470 unsigned long selector;
1471 int rc;
38ba30ba 1472
9dac77fa 1473 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1474 if (rc != X86EMUL_CONTINUE)
1475 return rc;
1476
7b105ca2 1477 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1478 return rc;
38ba30ba
GN		 1479}
1480
b96a7fad 1481static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1482{
9dac77fa 1483 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1484 int rc = X86EMUL_CONTINUE;
1485 int reg = VCPU_REGS_RAX;
38ba30ba 1486
dde7e6d1
AK		 1487 while (reg <= VCPU_REGS_RDI) {
1488 (reg == VCPU_REGS_RSP) ?
9dac77fa 1489 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1490
4487b3b4 1491 rc = em_push(ctxt);
dde7e6d1
AK		 1492 if (rc != X86EMUL_CONTINUE)
1493 return rc;
38ba30ba 1494
dde7e6d1 1495 ++reg;
38ba30ba 1496 }
38ba30ba 1497
dde7e6d1 1498 return rc;
38ba30ba
GN		 1499}
1500
62aaa2f0
TY		 1501static int em_pushf(struct x86_emulate_ctxt *ctxt)
1502{
9dac77fa 1503 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1504 return em_push(ctxt);
1505}
1506
b96a7fad 1507static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1508{
dde7e6d1
AK		 1509 int rc = X86EMUL_CONTINUE;
1510 int reg = VCPU_REGS_RDI;
38ba30ba 1511
dde7e6d1
AK		 1512 while (reg >= VCPU_REGS_RAX) {
1513 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1514 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1515 ctxt->op_bytes);
dde7e6d1
AK		 1516 --reg;
1517 }
38ba30ba 1518
9dac77fa 1519 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1520 if (rc != X86EMUL_CONTINUE)
1521 break;
1522 --reg;
38ba30ba 1523 }
dde7e6d1 1524 return rc;
38ba30ba
GN		 1525}
1526
7b105ca2 1527int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1528{
7b105ca2 1529 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1530 int rc;
6e154e56
MG		 1531 struct desc_ptr dt;
1532 gva_t cs_addr;
1533 gva_t eip_addr;
1534 u16 cs, eip;
6e154e56
MG		 1535
1536 /* TODO: Add limit checks */
9dac77fa 1537 ctxt->src.val = ctxt->eflags;
4487b3b4 1538 rc = em_push(ctxt);
5c56e1cf
AK		 1539 if (rc != X86EMUL_CONTINUE)
1540 return rc;
6e154e56
MG		 1541
1542 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1543
9dac77fa 1544 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1545 rc = em_push(ctxt);
5c56e1cf
AK		 1546 if (rc != X86EMUL_CONTINUE)
1547 return rc;
6e154e56 1548
9dac77fa 1549 ctxt->src.val = ctxt->_eip;
4487b3b4 1550 rc = em_push(ctxt);
5c56e1cf
AK		 1551 if (rc != X86EMUL_CONTINUE)
1552 return rc;
1553
4bff1e86 1554 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1555
1556 eip_addr = dt.address + (irq << 2);
1557 cs_addr = dt.address + (irq << 2) + 2;
1558
0f65dd70 1559 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1560 if (rc != X86EMUL_CONTINUE)
1561 return rc;
1562
0f65dd70 1563 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
7b105ca2 1567 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1568 if (rc != X86EMUL_CONTINUE)
1569 return rc;
1570
9dac77fa 1571 ctxt->_eip = eip;
6e154e56
MG		 1572
1573 return rc;
1574}
1575
7b105ca2 1576static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1577{
1578 switch(ctxt->mode) {
1579 case X86EMUL_MODE_REAL:
7b105ca2 1580 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1581 case X86EMUL_MODE_VM86:
1582 case X86EMUL_MODE_PROT16:
1583 case X86EMUL_MODE_PROT32:
1584 case X86EMUL_MODE_PROT64:
1585 default:
1586 /* Protected mode interrupts unimplemented yet */
1587 return X86EMUL_UNHANDLEABLE;
1588 }
1589}
1590
7b105ca2 1591static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1592{
dde7e6d1
AK		 1593 int rc = X86EMUL_CONTINUE;
1594 unsigned long temp_eip = 0;
1595 unsigned long temp_eflags = 0;
1596 unsigned long cs = 0;
1597 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1598 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1599 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1600 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1601
dde7e6d1 1602 /* TODO: Add stack limit check */
38ba30ba 1603
9dac77fa 1604 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1605
dde7e6d1
AK		 1606 if (rc != X86EMUL_CONTINUE)
1607 return rc;
38ba30ba 1608
35d3d4a1
AK		 1609 if (temp_eip & ~0xffff)
1610 return emulate_gp(ctxt, 0);
38ba30ba 1611
9dac77fa 1612 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1613
dde7e6d1
AK		 1614 if (rc != X86EMUL_CONTINUE)
1615 return rc;
38ba30ba 1616
9dac77fa 1617 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1618
dde7e6d1
AK		 1619 if (rc != X86EMUL_CONTINUE)
1620 return rc;
38ba30ba 1621
7b105ca2 1622 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1623
dde7e6d1
AK		 1624 if (rc != X86EMUL_CONTINUE)
1625 return rc;
38ba30ba 1626
9dac77fa 1627 ctxt->_eip = temp_eip;
38ba30ba 1628
38ba30ba 1629
9dac77fa 1630 if (ctxt->op_bytes == 4)
dde7e6d1 1631 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1632 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1633 ctxt->eflags &= ~0xffff;
1634 ctxt->eflags |= temp_eflags;
38ba30ba 1635 }
dde7e6d1
AK		 1636
1637 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1638 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1639
1640 return rc;
38ba30ba
GN		 1641}
1642
e01991e7 1643static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1644{
dde7e6d1
AK		 1645 switch(ctxt->mode) {
1646 case X86EMUL_MODE_REAL:
7b105ca2 1647 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1648 case X86EMUL_MODE_VM86:
1649 case X86EMUL_MODE_PROT16:
1650 case X86EMUL_MODE_PROT32:
1651 case X86EMUL_MODE_PROT64:
c37eda13 1652 default:
dde7e6d1
AK		 1653 /* iret from protected mode unimplemented yet */
1654 return X86EMUL_UNHANDLEABLE;
c37eda13 1655 }
c37eda13
WY		 1656}
1657
d2f62766
TY		 1658static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1659{
d2f62766
TY		 1660 int rc;
1661 unsigned short sel;
1662
9dac77fa 1663 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1664
7b105ca2 1665 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1666 if (rc != X86EMUL_CONTINUE)
1667 return rc;
1668
9dac77fa
AK		 1669 ctxt->_eip = 0;
1670 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1671 return X86EMUL_CONTINUE;
1672}
1673
51187683 1674static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1675{
9dac77fa 1676 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1677}
1678
51187683 1679static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1680{
9dac77fa 1681 switch (ctxt->modrm_reg) {
8cdbd2c9 1682 case 0: /* rol */
a31b9cea 1683 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1684 break;
1685 case 1: /* ror */
a31b9cea 1686 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1687 break;
1688 case 2: /* rcl */
a31b9cea 1689 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1690 break;
1691 case 3: /* rcr */
a31b9cea 1692 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1693 break;
1694 case 4: /* sal/shl */
1695 case 6: /* sal/shl */
a31b9cea 1696 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1697 break;
1698 case 5: /* shr */
a31b9cea 1699 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1700 break;
1701 case 7: /* sar */
a31b9cea 1702 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1703 break;
1704 }
51187683 1705 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1706}
1707
3329ece1
AK		 1708static int em_not(struct x86_emulate_ctxt *ctxt)
1709{
1710 ctxt->dst.val = ~ctxt->dst.val;
1711 return X86EMUL_CONTINUE;
1712}
1713
1714static int em_neg(struct x86_emulate_ctxt *ctxt)
1715{
1716 emulate_1op(ctxt, "neg");
1717 return X86EMUL_CONTINUE;
1718}
1719
1720static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1721{
1722 u8 ex = 0;
1723
1724 emulate_1op_rax_rdx(ctxt, "mul", ex);
1725 return X86EMUL_CONTINUE;
1726}
1727
1728static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1729{
1730 u8 ex = 0;
1731
1732 emulate_1op_rax_rdx(ctxt, "imul", ex);
1733 return X86EMUL_CONTINUE;
1734}
1735
1736static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1737{
34d1f490 1738 u8 de = 0;
8cdbd2c9 1739
3329ece1
AK		 1740 emulate_1op_rax_rdx(ctxt, "div", de);
1741 if (de)
1742 return emulate_de(ctxt);
1743 return X86EMUL_CONTINUE;
1744}
1745
1746static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1747{
1748 u8 de = 0;
1749
1750 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1751 if (de)
1752 return emulate_de(ctxt);
8c5eee30 1753 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1754}
1755
51187683 1756static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1757{
4179bb02 1758 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1759
9dac77fa 1760 switch (ctxt->modrm_reg) {
8cdbd2c9 1761 case 0: /* inc */
d1eef45d 1762 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1763 break;
1764 case 1: /* dec */
d1eef45d 1765 emulate_1op(ctxt, "dec");
8cdbd2c9 1766 break;
d19292e4
MG		 1767 case 2: /* call near abs */ {
1768 long int old_eip;
9dac77fa
AK		 1769 old_eip = ctxt->_eip;
1770 ctxt->_eip = ctxt->src.val;
1771 ctxt->src.val = old_eip;
4487b3b4 1772 rc = em_push(ctxt);
d19292e4
MG		 1773 break;
1774 }
8cdbd2c9 1775 case 4: /* jmp abs */
9dac77fa 1776 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1777 break;
d2f62766
TY		 1778 case 5: /* jmp far */
1779 rc = em_jmp_far(ctxt);
1780 break;
8cdbd2c9 1781 case 6: /* push */
4487b3b4 1782 rc = em_push(ctxt);
8cdbd2c9 1783 break;
8cdbd2c9 1784 }
4179bb02 1785 return rc;
8cdbd2c9
LV		 1786}
1787
51187683 1788static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1789{
9dac77fa 1790 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1791
9dac77fa
AK		 1792 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1793 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1794 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1795 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1796 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1797 } else {
9dac77fa
AK		 1798 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1799 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1800
05f086f8 1801 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1802 }
1b30eaa8 1803 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1804}
1805
ebda02c2
TY		 1806static int em_ret(struct x86_emulate_ctxt *ctxt)
1807{
9dac77fa
AK		 1808 ctxt->dst.type = OP_REG;
1809 ctxt->dst.addr.reg = &ctxt->_eip;
1810 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1811 return em_pop(ctxt);
1812}
1813
e01991e7 1814static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1815{
a77ab5ea
AK		 1816 int rc;
1817 unsigned long cs;
1818
9dac77fa 1819 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1820 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1821 return rc;
9dac77fa
AK		 1822 if (ctxt->op_bytes == 4)
1823 ctxt->_eip = (u32)ctxt->_eip;
1824 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1825 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1826 return rc;
7b105ca2 1827 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1828 return rc;
1829}
1830
d4b4325f 1831static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1832{
d4b4325f 1833 int seg = ctxt->src2.val;
09b5f4d3
WY		 1834 unsigned short sel;
1835 int rc;
1836
9dac77fa 1837 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1838
7b105ca2 1839 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1840 if (rc != X86EMUL_CONTINUE)
1841 return rc;
1842
9dac77fa 1843 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1844 return rc;
1845}
1846
7b105ca2 1847static void
e66bb2cc 1848setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1849 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1850{
1aa36616
AK		 1851 u16 selector;
1852
79168fd1 1853 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1854 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1855 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1856
1857 cs->l = 0; /* will be adjusted later */
79168fd1 1858 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1859 cs->g = 1; /* 4kb granularity */
79168fd1 1860 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1861 cs->type = 0x0b; /* Read, Execute, Accessed */
1862 cs->s = 1;
1863 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1864 cs->p = 1;
1865 cs->d = 1;
e66bb2cc 1866
79168fd1
GN		 1867 set_desc_base(ss, 0); /* flat segment */
1868 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1869 ss->g = 1; /* 4kb granularity */
1870 ss->s = 1;
1871 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1872 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1873 ss->dpl = 0;
79168fd1 1874 ss->p = 1;
e66bb2cc
AP		 1875}
1876
e01991e7 1877static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1878{
7b105ca2 1879 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1880 struct desc_struct cs, ss;
e66bb2cc 1881 u64 msr_data;
79168fd1 1882 u16 cs_sel, ss_sel;
c2ad2bb3 1883 u64 efer = 0;
e66bb2cc
AP		 1884
1885 /* syscall is not available in real mode */
2e901c4c 1886 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1887 ctxt->mode == X86EMUL_MODE_VM86)
1888 return emulate_ud(ctxt);
e66bb2cc 1889
c2ad2bb3 1890 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1891 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1892
717746e3 1893 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1894 msr_data >>= 32;
79168fd1
GN		 1895 cs_sel = (u16)(msr_data & 0xfffc);
1896 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1897
c2ad2bb3 1898 if (efer & EFER_LMA) {
79168fd1 1899 cs.d = 0;
e66bb2cc
AP		 1900 cs.l = 1;
1901 }
1aa36616
AK		 1902 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1903 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1904
9dac77fa 1905 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1906 if (efer & EFER_LMA) {
e66bb2cc 1907#ifdef CONFIG_X86_64
9dac77fa 1908 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1909
717746e3 1910 ops->get_msr(ctxt,
3fb1b5db
GN		 1911 ctxt->mode == X86EMUL_MODE_PROT64 ?
1912 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1913 ctxt->_eip = msr_data;
e66bb2cc 1914
717746e3 1915 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1916 ctxt->eflags &= ~(msr_data | EFLG_RF);
1917#endif
1918 } else {
1919 /* legacy mode */
717746e3 1920 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1921 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1922
1923 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1924 }
1925
e54cfa97 1926 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1927}
1928
e01991e7 1929static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1930{
7b105ca2 1931 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1932 struct desc_struct cs, ss;
8c604352 1933 u64 msr_data;
79168fd1 1934 u16 cs_sel, ss_sel;
c2ad2bb3 1935 u64 efer = 0;
8c604352 1936
7b105ca2 1937 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1938 /* inject #GP if in real mode */
35d3d4a1
AK		 1939 if (ctxt->mode == X86EMUL_MODE_REAL)
1940 return emulate_gp(ctxt, 0);
8c604352
AP		 1941
1942 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1943 * Therefore, we inject an #UD.
1944 */
35d3d4a1
AK		 1945 if (ctxt->mode == X86EMUL_MODE_PROT64)
1946 return emulate_ud(ctxt);
8c604352 1947
7b105ca2 1948 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1949
717746e3 1950 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1951 switch (ctxt->mode) {
1952 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1953 if ((msr_data & 0xfffc) == 0x0)
1954 return emulate_gp(ctxt, 0);
8c604352
AP		 1955 break;
1956 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1957 if (msr_data == 0x0)
1958 return emulate_gp(ctxt, 0);
8c604352
AP		 1959 break;
1960 }
1961
1962 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1963 cs_sel = (u16)msr_data;
1964 cs_sel &= ~SELECTOR_RPL_MASK;
1965 ss_sel = cs_sel + 8;
1966 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1967 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1968 cs.d = 0;
8c604352
AP		 1969 cs.l = 1;
1970 }
1971
1aa36616
AK		 1972 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1973 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1974
717746e3 1975 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1976 ctxt->_eip = msr_data;
8c604352 1977
717746e3 1978 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1979 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1980
e54cfa97 1981 return X86EMUL_CONTINUE;
8c604352
AP		 1982}
1983
e01991e7 1984static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1985{
7b105ca2 1986 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1987 struct desc_struct cs, ss;
4668f050
AP		 1988 u64 msr_data;
1989 int usermode;
1249b96e 1990 u16 cs_sel = 0, ss_sel = 0;
4668f050 1991
a0044755
GN		 1992 /* inject #GP if in real mode or Virtual 8086 mode */
1993 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1994 ctxt->mode == X86EMUL_MODE_VM86)
1995 return emulate_gp(ctxt, 0);
4668f050 1996
7b105ca2 1997 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 1998
9dac77fa 1999 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2000 usermode = X86EMUL_MODE_PROT64;
2001 else
2002 usermode = X86EMUL_MODE_PROT32;
2003
2004 cs.dpl = 3;
2005 ss.dpl = 3;
717746e3 2006 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2007 switch (usermode) {
2008 case X86EMUL_MODE_PROT32:
79168fd1 2009 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2010 if ((msr_data & 0xfffc) == 0x0)
2011 return emulate_gp(ctxt, 0);
79168fd1 2012 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2013 break;
2014 case X86EMUL_MODE_PROT64:
79168fd1 2015 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2016 if (msr_data == 0x0)
2017 return emulate_gp(ctxt, 0);
79168fd1
GN		 2018 ss_sel = cs_sel + 8;
2019 cs.d = 0;
4668f050
AP		 2020 cs.l = 1;
2021 break;
2022 }
79168fd1
GN		 2023 cs_sel |= SELECTOR_RPL_MASK;
2024 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2025
1aa36616
AK		 2026 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2027 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2028
9dac77fa
AK		 2029 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2030 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2031
e54cfa97 2032 return X86EMUL_CONTINUE;
4668f050
AP		 2033}
2034
7b105ca2 2035static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2036{
2037 int iopl;
2038 if (ctxt->mode == X86EMUL_MODE_REAL)
2039 return false;
2040 if (ctxt->mode == X86EMUL_MODE_VM86)
2041 return true;
2042 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2043 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2044}
2045
2046static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2047 u16 port, u16 len)
2048{
7b105ca2 2049 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2050 struct desc_struct tr_seg;
5601d05b 2051 u32 base3;
f850e2e6 2052 int r;
1aa36616 2053 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2054 unsigned mask = (1 << len) - 1;
5601d05b 2055 unsigned long base;
f850e2e6 2056
1aa36616 2057 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2058 if (!tr_seg.p)
f850e2e6 2059 return false;
79168fd1 2060 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2061 return false;
5601d05b
GN		 2062 base = get_desc_base(&tr_seg);
2063#ifdef CONFIG_X86_64
2064 base |= ((u64)base3) << 32;
2065#endif
0f65dd70 2066 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2067 if (r != X86EMUL_CONTINUE)
2068 return false;
79168fd1 2069 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2070 return false;
0f65dd70 2071 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2072 if (r != X86EMUL_CONTINUE)
2073 return false;
2074 if ((perm >> bit_idx) & mask)
2075 return false;
2076 return true;
2077}
2078
2079static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2080 u16 port, u16 len)
2081{
4fc40f07
GN		 2082 if (ctxt->perm_ok)
2083 return true;
2084
7b105ca2
TY		 2085 if (emulator_bad_iopl(ctxt))
2086 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2087 return false;
4fc40f07
GN		 2088
2089 ctxt->perm_ok = true;
2090
f850e2e6
GN		 2091 return true;
2092}
2093
38ba30ba 2094static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2095 struct tss_segment_16 *tss)
2096{
9dac77fa 2097 tss->ip = ctxt->_eip;
38ba30ba 2098 tss->flag = ctxt->eflags;
9dac77fa
AK		 2099 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2100 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2101 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2102 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2103 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2104 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2105 tss->si = ctxt->regs[VCPU_REGS_RSI];
2106 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2107
1aa36616
AK		 2108 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2109 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2110 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2111 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2112 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2113}
2114
2115static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2116 struct tss_segment_16 *tss)
2117{
38ba30ba
GN		 2118 int ret;
2119
9dac77fa 2120 ctxt->_eip = tss->ip;
38ba30ba 2121 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2122 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2123 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2124 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2125 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2126 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2127 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2128 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2129 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2130
2131 /*
2132 * SDM says that segment selectors are loaded before segment
2133 * descriptors
2134 */
1aa36616
AK		 2135 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2136 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2137 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2138 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2139 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2140
2141 /*
2142 * Now load segment descriptors. If fault happenes at this stage
2143 * it is handled in a context of new task
2144 */
7b105ca2 2145 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2146 if (ret != X86EMUL_CONTINUE)
2147 return ret;
7b105ca2 2148 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2149 if (ret != X86EMUL_CONTINUE)
2150 return ret;
7b105ca2 2151 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2152 if (ret != X86EMUL_CONTINUE)
2153 return ret;
7b105ca2 2154 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2155 if (ret != X86EMUL_CONTINUE)
2156 return ret;
7b105ca2 2157 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2158 if (ret != X86EMUL_CONTINUE)
2159 return ret;
2160
2161 return X86EMUL_CONTINUE;
2162}
2163
2164static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2165 u16 tss_selector, u16 old_tss_sel,
2166 ulong old_tss_base, struct desc_struct *new_desc)
2167{
7b105ca2 2168 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2169 struct tss_segment_16 tss_seg;
2170 int ret;
bcc55cba 2171 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2172
0f65dd70 2173 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2174 &ctxt->exception);
db297e3d 2175 if (ret != X86EMUL_CONTINUE)
38ba30ba 2176 /* FIXME: need to provide precise fault address */
38ba30ba 2177 return ret;
38ba30ba 2178
7b105ca2 2179 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2180
0f65dd70 2181 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2182 &ctxt->exception);
db297e3d 2183 if (ret != X86EMUL_CONTINUE)
38ba30ba 2184 /* FIXME: need to provide precise fault address */
38ba30ba 2185 return ret;
38ba30ba 2186
0f65dd70 2187 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2188 &ctxt->exception);
db297e3d 2189 if (ret != X86EMUL_CONTINUE)
38ba30ba 2190 /* FIXME: need to provide precise fault address */
38ba30ba 2191 return ret;
38ba30ba
GN		 2192
2193 if (old_tss_sel != 0xffff) {
2194 tss_seg.prev_task_link = old_tss_sel;
2195
0f65dd70 2196 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2197 &tss_seg.prev_task_link,
2198 sizeof tss_seg.prev_task_link,
0f65dd70 2199 &ctxt->exception);
db297e3d 2200 if (ret != X86EMUL_CONTINUE)
38ba30ba 2201 /* FIXME: need to provide precise fault address */
38ba30ba 2202 return ret;
38ba30ba
GN		 2203 }
2204
7b105ca2 2205 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2206}
2207
2208static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2209 struct tss_segment_32 *tss)
2210{
7b105ca2 2211 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2212 tss->eip = ctxt->_eip;
38ba30ba 2213 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2214 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2215 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2216 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2217 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2218 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2219 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2220 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2221 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2222
1aa36616
AK		 2223 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2224 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2225 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2226 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2227 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2228 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2229 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2230}
2231
2232static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2233 struct tss_segment_32 *tss)
2234{
38ba30ba
GN		 2235 int ret;
2236
7b105ca2 2237 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2238 return emulate_gp(ctxt, 0);
9dac77fa 2239 ctxt->_eip = tss->eip;
38ba30ba 2240 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2241 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2242 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2243 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2244 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2245 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2246 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2247 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2248 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2249
2250 /*
2251 * SDM says that segment selectors are loaded before segment
2252 * descriptors
2253 */
1aa36616
AK		 2254 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2255 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2256 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2257 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2258 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2259 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2260 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2261
2262 /*
2263 * Now load segment descriptors. If fault happenes at this stage
2264 * it is handled in a context of new task
2265 */
7b105ca2 2266 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2267 if (ret != X86EMUL_CONTINUE)
2268 return ret;
7b105ca2 2269 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2270 if (ret != X86EMUL_CONTINUE)
2271 return ret;
7b105ca2 2272 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2273 if (ret != X86EMUL_CONTINUE)
2274 return ret;
7b105ca2 2275 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2276 if (ret != X86EMUL_CONTINUE)
2277 return ret;
7b105ca2 2278 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2279 if (ret != X86EMUL_CONTINUE)
2280 return ret;
7b105ca2 2281 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2282 if (ret != X86EMUL_CONTINUE)
2283 return ret;
7b105ca2 2284 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2285 if (ret != X86EMUL_CONTINUE)
2286 return ret;
2287
2288 return X86EMUL_CONTINUE;
2289}
2290
2291static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2292 u16 tss_selector, u16 old_tss_sel,
2293 ulong old_tss_base, struct desc_struct *new_desc)
2294{
7b105ca2 2295 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2296 struct tss_segment_32 tss_seg;
2297 int ret;
bcc55cba 2298 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2299
0f65dd70 2300 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2301 &ctxt->exception);
db297e3d 2302 if (ret != X86EMUL_CONTINUE)
38ba30ba 2303 /* FIXME: need to provide precise fault address */
38ba30ba 2304 return ret;
38ba30ba 2305
7b105ca2 2306 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2307
0f65dd70 2308 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2309 &ctxt->exception);
db297e3d 2310 if (ret != X86EMUL_CONTINUE)
38ba30ba 2311 /* FIXME: need to provide precise fault address */
38ba30ba 2312 return ret;
38ba30ba 2313
0f65dd70 2314 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2315 &ctxt->exception);
db297e3d 2316 if (ret != X86EMUL_CONTINUE)
38ba30ba 2317 /* FIXME: need to provide precise fault address */
38ba30ba 2318 return ret;
38ba30ba
GN		 2319
2320 if (old_tss_sel != 0xffff) {
2321 tss_seg.prev_task_link = old_tss_sel;
2322
0f65dd70 2323 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2324 &tss_seg.prev_task_link,
2325 sizeof tss_seg.prev_task_link,
0f65dd70 2326 &ctxt->exception);
db297e3d 2327 if (ret != X86EMUL_CONTINUE)
38ba30ba 2328 /* FIXME: need to provide precise fault address */
38ba30ba 2329 return ret;
38ba30ba
GN		 2330 }
2331
7b105ca2 2332 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2333}
2334
2335static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2336 u16 tss_selector, int reason,
2337 bool has_error_code, u32 error_code)
38ba30ba 2338{
7b105ca2 2339 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2340 struct desc_struct curr_tss_desc, next_tss_desc;
2341 int ret;
1aa36616 2342 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2343 ulong old_tss_base =
4bff1e86 2344 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2345 u32 desc_limit;
38ba30ba
GN		 2346
2347 /* FIXME: old_tss_base == ~0 ? */
2348
7b105ca2 2349 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2350 if (ret != X86EMUL_CONTINUE)
2351 return ret;
7b105ca2 2352 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2353 if (ret != X86EMUL_CONTINUE)
2354 return ret;
2355
2356 /* FIXME: check that next_tss_desc is tss */
2357
2358 if (reason != TASK_SWITCH_IRET) {
2359 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2360 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2361 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2362 }
2363
ceffb459
GN		 2364 desc_limit = desc_limit_scaled(&next_tss_desc);
2365 if (!next_tss_desc.p ||
2366 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2367 desc_limit < 0x2b)) {
54b8486f 2368 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2369 return X86EMUL_PROPAGATE_FAULT;
2370 }
2371
2372 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2373 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2374 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2375 }
2376
2377 if (reason == TASK_SWITCH_IRET)
2378 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2379
2380 /* set back link to prev task only if NT bit is set in eflags
2381 note that old_tss_sel is not used afetr this point */
2382 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2383 old_tss_sel = 0xffff;
2384
2385 if (next_tss_desc.type & 8)
7b105ca2 2386 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2387 old_tss_base, &next_tss_desc);
2388 else
7b105ca2 2389 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2390 old_tss_base, &next_tss_desc);
0760d448
JK		 2391 if (ret != X86EMUL_CONTINUE)
2392 return ret;
38ba30ba
GN		 2393
2394 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2395 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2396
2397 if (reason != TASK_SWITCH_IRET) {
2398 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2399 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2400 }
2401
717746e3 2402 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2403 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2404
e269fb21 2405 if (has_error_code) {
9dac77fa
AK		 2406 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2407 ctxt->lock_prefix = 0;
2408 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2409 ret = em_push(ctxt);
e269fb21
JK		 2410 }
2411
38ba30ba
GN		 2412 return ret;
2413}
2414
2415int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2416 u16 tss_selector, int reason,
2417 bool has_error_code, u32 error_code)
38ba30ba 2418{
38ba30ba
GN		 2419 int rc;
2420
9dac77fa
AK		 2421 ctxt->_eip = ctxt->eip;
2422 ctxt->dst.type = OP_NONE;
38ba30ba 2423
7b105ca2 2424 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2425 has_error_code, error_code);
38ba30ba 2426
4179bb02 2427 if (rc == X86EMUL_CONTINUE)
9dac77fa 2428 ctxt->eip = ctxt->_eip;
38ba30ba 2429
a0c0ab2f 2430 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2431}
2432
90de84f5 2433static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2434 int reg, struct operand *op)
a682e354 2435{
a682e354
GN		 2436 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2437
9dac77fa
AK		 2438 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2439 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2440 op->addr.mem.seg = seg;
a682e354
GN		 2441}
2442
7af04fc0
AK		 2443static int em_das(struct x86_emulate_ctxt *ctxt)
2444{
7af04fc0
AK		 2445 u8 al, old_al;
2446 bool af, cf, old_cf;
2447
2448 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2449 al = ctxt->dst.val;
7af04fc0
AK		 2450
2451 old_al = al;
2452 old_cf = cf;
2453 cf = false;
2454 af = ctxt->eflags & X86_EFLAGS_AF;
2455 if ((al & 0x0f) > 9 || af) {
2456 al -= 6;
2457 cf = old_cf | (al >= 250);
2458 af = true;
2459 } else {
2460 af = false;
2461 }
2462 if (old_al > 0x99 || old_cf) {
2463 al -= 0x60;
2464 cf = true;
2465 }
2466
9dac77fa 2467 ctxt->dst.val = al;
7af04fc0 2468 /* Set PF, ZF, SF */
9dac77fa
AK		 2469 ctxt->src.type = OP_IMM;
2470 ctxt->src.val = 0;
2471 ctxt->src.bytes = 1;
a31b9cea 2472 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2473 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2474 if (cf)
2475 ctxt->eflags |= X86_EFLAGS_CF;
2476 if (af)
2477 ctxt->eflags |= X86_EFLAGS_AF;
2478 return X86EMUL_CONTINUE;
2479}
2480
0ef753b8
AK		 2481static int em_call_far(struct x86_emulate_ctxt *ctxt)
2482{
0ef753b8
AK		 2483 u16 sel, old_cs;
2484 ulong old_eip;
2485 int rc;
2486
1aa36616 2487 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2488 old_eip = ctxt->_eip;
0ef753b8 2489
9dac77fa 2490 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2491 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2492 return X86EMUL_CONTINUE;
2493
9dac77fa
AK		 2494 ctxt->_eip = 0;
2495 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2496
9dac77fa 2497 ctxt->src.val = old_cs;
4487b3b4 2498 rc = em_push(ctxt);
0ef753b8
AK		 2499 if (rc != X86EMUL_CONTINUE)
2500 return rc;
2501
9dac77fa 2502 ctxt->src.val = old_eip;
4487b3b4 2503 return em_push(ctxt);
0ef753b8
AK		 2504}
2505
40ece7c7
AK		 2506static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2507{
40ece7c7
AK		 2508 int rc;
2509
9dac77fa
AK		 2510 ctxt->dst.type = OP_REG;
2511 ctxt->dst.addr.reg = &ctxt->_eip;
2512 ctxt->dst.bytes = ctxt->op_bytes;
2513 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2514 if (rc != X86EMUL_CONTINUE)
2515 return rc;
9dac77fa 2516 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2517 return X86EMUL_CONTINUE;
2518}
2519
d67fc27a
TY		 2520static int em_add(struct x86_emulate_ctxt *ctxt)
2521{
a31b9cea 2522 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2523 return X86EMUL_CONTINUE;
2524}
2525
2526static int em_or(struct x86_emulate_ctxt *ctxt)
2527{
a31b9cea 2528 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2529 return X86EMUL_CONTINUE;
2530}
2531
2532static int em_adc(struct x86_emulate_ctxt *ctxt)
2533{
a31b9cea 2534 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2535 return X86EMUL_CONTINUE;
2536}
2537
2538static int em_sbb(struct x86_emulate_ctxt *ctxt)
2539{
a31b9cea 2540 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2541 return X86EMUL_CONTINUE;
2542}
2543
2544static int em_and(struct x86_emulate_ctxt *ctxt)
2545{
a31b9cea 2546 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2547 return X86EMUL_CONTINUE;
2548}
2549
2550static int em_sub(struct x86_emulate_ctxt *ctxt)
2551{
a31b9cea 2552 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2553 return X86EMUL_CONTINUE;
2554}
2555
2556static int em_xor(struct x86_emulate_ctxt *ctxt)
2557{
a31b9cea 2558 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2559 return X86EMUL_CONTINUE;
2560}
2561
2562static int em_cmp(struct x86_emulate_ctxt *ctxt)
2563{
a31b9cea 2564 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2565 /* Disable writeback. */
9dac77fa 2566 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2567 return X86EMUL_CONTINUE;
2568}
2569
9f21ca59
TY		 2570static int em_test(struct x86_emulate_ctxt *ctxt)
2571{
a31b9cea 2572 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2573 /* Disable writeback. */
2574 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2575 return X86EMUL_CONTINUE;
2576}
2577
e4f973ae
TY		 2578static int em_xchg(struct x86_emulate_ctxt *ctxt)
2579{
e4f973ae 2580 /* Write back the register source. */
9dac77fa
AK		 2581 ctxt->src.val = ctxt->dst.val;
2582 write_register_operand(&ctxt->src);
e4f973ae
TY		 2583
2584 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2585 ctxt->dst.val = ctxt->src.orig_val;
2586 ctxt->lock_prefix = 1;
e4f973ae
TY		 2587 return X86EMUL_CONTINUE;
2588}
2589
5c82aa29 2590static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2591{
a31b9cea 2592 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2593 return X86EMUL_CONTINUE;
2594}
2595
5c82aa29
AK		 2596static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2597{
9dac77fa 2598 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2599 return em_imul(ctxt);
2600}
2601
61429142
AK		 2602static int em_cwd(struct x86_emulate_ctxt *ctxt)
2603{
9dac77fa
AK		 2604 ctxt->dst.type = OP_REG;
2605 ctxt->dst.bytes = ctxt->src.bytes;
2606 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2607 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2608
2609 return X86EMUL_CONTINUE;
2610}
2611
48bb5d3c
AK		 2612static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2613{
48bb5d3c
AK		 2614 u64 tsc = 0;
2615
717746e3 2616 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2617 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2618 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2619 return X86EMUL_CONTINUE;
2620}
2621
b9eac5f4
AK		 2622static int em_mov(struct x86_emulate_ctxt *ctxt)
2623{
9dac77fa 2624 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2625 return X86EMUL_CONTINUE;
2626}
2627
1bd5f469
TY		 2628static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2629{
9dac77fa 2630 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2631 return emulate_ud(ctxt);
2632
9dac77fa 2633 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2634 return X86EMUL_CONTINUE;
2635}
2636
2637static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2638{
9dac77fa 2639 u16 sel = ctxt->src.val;
1bd5f469 2640
9dac77fa 2641 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2642 return emulate_ud(ctxt);
2643
9dac77fa 2644 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2645 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2646
2647 /* Disable writeback. */
9dac77fa
AK		 2648 ctxt->dst.type = OP_NONE;
2649 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2650}
2651
aa97bb48
AK		 2652static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2653{
9dac77fa 2654 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2655 return X86EMUL_CONTINUE;
2656}
2657
38503911
AK		 2658static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2659{
9fa088f4
AK		 2660 int rc;
2661 ulong linear;
2662
9dac77fa 2663 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2664 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2665 ctxt->ops->invlpg(ctxt, linear);
38503911 2666 /* Disable writeback. */
9dac77fa 2667 ctxt->dst.type = OP_NONE;
38503911
AK		 2668 return X86EMUL_CONTINUE;
2669}
2670
2d04a05b
AK		 2671static int em_clts(struct x86_emulate_ctxt *ctxt)
2672{
2673 ulong cr0;
2674
2675 cr0 = ctxt->ops->get_cr(ctxt, 0);
2676 cr0 &= ~X86_CR0_TS;
2677 ctxt->ops->set_cr(ctxt, 0, cr0);
2678 return X86EMUL_CONTINUE;
2679}
2680
26d05cc7
AK		 2681static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2682{
26d05cc7
AK		 2683 int rc;
2684
9dac77fa 2685 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2686 return X86EMUL_UNHANDLEABLE;
2687
2688 rc = ctxt->ops->fix_hypercall(ctxt);
2689 if (rc != X86EMUL_CONTINUE)
2690 return rc;
2691
2692 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2693 ctxt->_eip = ctxt->eip;
26d05cc7 2694 /* Disable writeback. */
9dac77fa 2695 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2696 return X86EMUL_CONTINUE;
2697}
2698
2699static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2700{
26d05cc7
AK		 2701 struct desc_ptr desc_ptr;
2702 int rc;
2703
9dac77fa 2704 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2705 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2706 ctxt->op_bytes);
26d05cc7
AK		 2707 if (rc != X86EMUL_CONTINUE)
2708 return rc;
2709 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2710 /* Disable writeback. */
9dac77fa 2711 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2712 return X86EMUL_CONTINUE;
2713}
2714
5ef39c71 2715static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2716{
26d05cc7
AK		 2717 int rc;
2718
5ef39c71
AK		 2719 rc = ctxt->ops->fix_hypercall(ctxt);
2720
26d05cc7 2721 /* Disable writeback. */
9dac77fa 2722 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2723 return rc;
2724}
2725
2726static int em_lidt(struct x86_emulate_ctxt *ctxt)
2727{
26d05cc7
AK		 2728 struct desc_ptr desc_ptr;
2729 int rc;
2730
9dac77fa 2731 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2732 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2733 ctxt->op_bytes);
26d05cc7
AK		 2734 if (rc != X86EMUL_CONTINUE)
2735 return rc;
2736 ctxt->ops->set_idt(ctxt, &desc_ptr);
2737 /* Disable writeback. */
9dac77fa 2738 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2739 return X86EMUL_CONTINUE;
2740}
2741
2742static int em_smsw(struct x86_emulate_ctxt *ctxt)
2743{
9dac77fa
AK		 2744 ctxt->dst.bytes = 2;
2745 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2746 return X86EMUL_CONTINUE;
2747}
2748
2749static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2750{
26d05cc7 2751 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2752 | (ctxt->src.val & 0x0f));
2753 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2754 return X86EMUL_CONTINUE;
2755}
2756
d06e03ad
TY		 2757static int em_loop(struct x86_emulate_ctxt *ctxt)
2758{
9dac77fa
AK		 2759 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2760 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2761 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2762 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2763
2764 return X86EMUL_CONTINUE;
2765}
2766
2767static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2768{
9dac77fa
AK		 2769 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2770 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2771
2772 return X86EMUL_CONTINUE;
2773}
2774
f411e6cd
TY		 2775static int em_cli(struct x86_emulate_ctxt *ctxt)
2776{
2777 if (emulator_bad_iopl(ctxt))
2778 return emulate_gp(ctxt, 0);
2779
2780 ctxt->eflags &= ~X86_EFLAGS_IF;
2781 return X86EMUL_CONTINUE;
2782}
2783
2784static int em_sti(struct x86_emulate_ctxt *ctxt)
2785{
2786 if (emulator_bad_iopl(ctxt))
2787 return emulate_gp(ctxt, 0);
2788
2789 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2790 ctxt->eflags |= X86_EFLAGS_IF;
2791 return X86EMUL_CONTINUE;
2792}
2793
cfec82cb
JR		 2794static bool valid_cr(int nr)
2795{
2796 switch (nr) {
2797 case 0:
2798 case 2 ... 4:
2799 case 8:
2800 return true;
2801 default:
2802 return false;
2803 }
2804}
2805
2806static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2807{
9dac77fa 2808 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2809 return emulate_ud(ctxt);
2810
2811 return X86EMUL_CONTINUE;
2812}
2813
2814static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2815{
9dac77fa
AK		 2816 u64 new_val = ctxt->src.val64;
2817 int cr = ctxt->modrm_reg;
c2ad2bb3 2818 u64 efer = 0;
cfec82cb
JR		 2819
2820 static u64 cr_reserved_bits[] = {
2821 0xffffffff00000000ULL,
2822 0, 0, 0, /* CR3 checked later */
2823 CR4_RESERVED_BITS,
2824 0, 0, 0,
2825 CR8_RESERVED_BITS,
2826 };
2827
2828 if (!valid_cr(cr))
2829 return emulate_ud(ctxt);
2830
2831 if (new_val & cr_reserved_bits[cr])
2832 return emulate_gp(ctxt, 0);
2833
2834 switch (cr) {
2835 case 0: {
c2ad2bb3 2836 u64 cr4;
cfec82cb
JR		 2837 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2838 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2839 return emulate_gp(ctxt, 0);
2840
717746e3
AK		 2841 cr4 = ctxt->ops->get_cr(ctxt, 4);
2842 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2843
2844 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2845 !(cr4 & X86_CR4_PAE))
2846 return emulate_gp(ctxt, 0);
2847
2848 break;
2849 }
2850 case 3: {
2851 u64 rsvd = 0;
2852
c2ad2bb3
AK		 2853 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2854 if (efer & EFER_LMA)
cfec82cb 2855 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2856 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2857 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2858 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2859 rsvd = CR3_NONPAE_RESERVED_BITS;
2860
2861 if (new_val & rsvd)
2862 return emulate_gp(ctxt, 0);
2863
2864 break;
2865 }
2866 case 4: {
c2ad2bb3 2867 u64 cr4;
cfec82cb 2868
717746e3
AK		 2869 cr4 = ctxt->ops->get_cr(ctxt, 4);
2870 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2871
2872 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2873 return emulate_gp(ctxt, 0);
2874
2875 break;
2876 }
2877 }
2878
2879 return X86EMUL_CONTINUE;
2880}
2881
3b88e41a
JR		 2882static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2883{
2884 unsigned long dr7;
2885
717746e3 2886 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2887
2888 /* Check if DR7.Global_Enable is set */
2889 return dr7 & (1 << 13);
2890}
2891
2892static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2893{
9dac77fa 2894 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2895 u64 cr4;
2896
2897 if (dr > 7)
2898 return emulate_ud(ctxt);
2899
717746e3 2900 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2901 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2902 return emulate_ud(ctxt);
2903
2904 if (check_dr7_gd(ctxt))
2905 return emulate_db(ctxt);
2906
2907 return X86EMUL_CONTINUE;
2908}
2909
2910static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2911{
9dac77fa
AK		 2912 u64 new_val = ctxt->src.val64;
2913 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2914
2915 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2916 return emulate_gp(ctxt, 0);
2917
2918 return check_dr_read(ctxt);
2919}
2920
01de8b09
JR		 2921static int check_svme(struct x86_emulate_ctxt *ctxt)
2922{
2923 u64 efer;
2924
717746e3 2925 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2926
2927 if (!(efer & EFER_SVME))
2928 return emulate_ud(ctxt);
2929
2930 return X86EMUL_CONTINUE;
2931}
2932
2933static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2934{
9dac77fa 2935 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2936
2937 /* Valid physical address? */
d4224449 2938 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2939 return emulate_gp(ctxt, 0);
2940
2941 return check_svme(ctxt);
2942}
2943
d7eb8203
JR		 2944static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2945{
717746e3 2946 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2947
717746e3 2948 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2949 return emulate_ud(ctxt);
2950
2951 return X86EMUL_CONTINUE;
2952}
2953
8061252e
JR		 2954static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2955{
717746e3 2956 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2957 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2958
717746e3 2959 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2960 (rcx > 3))
2961 return emulate_gp(ctxt, 0);
2962
2963 return X86EMUL_CONTINUE;
2964}
2965
f6511935
JR		 2966static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2967{
9dac77fa
AK		 2968 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2969 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2970 return emulate_gp(ctxt, 0);
2971
2972 return X86EMUL_CONTINUE;
2973}
2974
2975static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2976{
9dac77fa
AK		 2977 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2978 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2979 return emulate_gp(ctxt, 0);
2980
2981 return X86EMUL_CONTINUE;
2982}
2983
73fba5f4 2984#define D(_y) { .flags = (_y) }
c4f035c6 2985#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2986#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2987 .check_perm = (_p) }
73fba5f4 2988#define N D(0)
01de8b09 2989#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2990#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2991#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2992#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2993#define II(_f, _e, _i) \
2994 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2995#define IIP(_f, _e, _i, _p) \
2996 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2997 .check_perm = (_p) }
aa97bb48 2998#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2999
8d8f4e9f 3000#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3001#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 3002#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3003
d67fc27a
TY		 3004#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3005 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3006 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3007
d7eb8203
JR		 3008static struct opcode group7_rm1[] = {
3009 DI(SrcNone | ModRM | Priv, monitor),
3010 DI(SrcNone | ModRM | Priv, mwait),
3011 N, N, N, N, N, N,
3012};
3013
01de8b09
JR		 3014static struct opcode group7_rm3[] = {
3015 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3016 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3017 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3018 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3019 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3020 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3021 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3022 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3023};
6230f7fc 3024
d7eb8203
JR		 3025static struct opcode group7_rm7[] = {
3026 N,
3027 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3028 N, N, N, N, N, N,
3029};
d67fc27a 3030
73fba5f4 3031static struct opcode group1[] = {
d67fc27a
TY		 3032 I(Lock, em_add),
3033 I(Lock, em_or),
3034 I(Lock, em_adc),
3035 I(Lock, em_sbb),
3036 I(Lock, em_and),
3037 I(Lock, em_sub),
3038 I(Lock, em_xor),
3039 I(0, em_cmp),
73fba5f4
AK		 3040};
3041
3042static struct opcode group1A[] = {
3043 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3044};
3045
3046static struct opcode group3[] = {
3329ece1
AK		 3047 I(DstMem | SrcImm | ModRM, em_test),
3048 I(DstMem | SrcImm | ModRM, em_test),
3049 I(DstMem | SrcNone | ModRM | Lock, em_not),
3050 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3051 I(SrcMem | ModRM, em_mul_ex),
3052 I(SrcMem | ModRM, em_imul_ex),
3053 I(SrcMem | ModRM, em_div_ex),
3054 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3055};
3056
3057static struct opcode group4[] = {
3058 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3059 N, N, N, N, N, N,
3060};
3061
3062static struct opcode group5[] = {
3063 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3064 D(SrcMem | ModRM | Stack),
3065 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3066 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3067 D(SrcMem | ModRM | Stack), N,
3068};
3069
dee6bb70
JR		 3070static struct opcode group6[] = {
3071 DI(ModRM | Prot, sldt),
3072 DI(ModRM | Prot, str),
3073 DI(ModRM | Prot | Priv, lldt),
3074 DI(ModRM | Prot | Priv, ltr),
3075 N, N, N, N,
3076};
3077
73fba5f4 3078static struct group_dual group7 = { {
dee6bb70
JR		 3079 DI(ModRM | Mov | DstMem | Priv, sgdt),
3080 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3081 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3082 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3083 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3084 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3085 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3086}, {
5ef39c71
AK		 3087 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3088 EXT(0, group7_rm1),
01de8b09 3089 N, EXT(0, group7_rm3),
5ef39c71
AK		 3090 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3091 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3092} };
3093
3094static struct opcode group8[] = {
3095 N, N, N, N,
3096 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3097 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3098};
3099
3100static struct group_dual group9 = { {
3101 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3102}, {
3103 N, N, N, N, N, N, N, N,
3104} };
3105
a4d4a7c1
AK		 3106static struct opcode group11[] = {
3107 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3108};
3109
aa97bb48
AK		 3110static struct gprefix pfx_0f_6f_0f_7f = {
3111 N, N, N, I(Sse, em_movdqu),
3112};
3113
73fba5f4
AK		 3114static struct opcode opcode_table[256] = {
3115 /* 0x00 - 0x07 */
d67fc27a 3116 I6ALU(Lock, em_add),
c191a7a0
AK		 3117 D(ImplicitOps | Stack | No64 | Src2ES),
3118 D(ImplicitOps | Stack | No64 | Src2ES),
73fba5f4 3119 /* 0x08 - 0x0F */
d67fc27a 3120 I6ALU(Lock, em_or),
c191a7a0 3121 D(ImplicitOps | Stack | No64 | Src2CS), N,
73fba5f4 3122 /* 0x10 - 0x17 */
d67fc27a 3123 I6ALU(Lock, em_adc),
c191a7a0
AK		 3124 D(ImplicitOps | Stack | No64 | Src2SS),
3125 D(ImplicitOps | Stack | No64 | Src2SS),
73fba5f4 3126 /* 0x18 - 0x1F */
d67fc27a 3127 I6ALU(Lock, em_sbb),
c191a7a0
AK		 3128 D(ImplicitOps | Stack | No64 | Src2DS),
3129 D(ImplicitOps | Stack | No64 | Src2DS),
73fba5f4 3130 /* 0x20 - 0x27 */
d67fc27a 3131 I6ALU(Lock, em_and), N, N,
73fba5f4 3132 /* 0x28 - 0x2F */
d67fc27a 3133 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3134 /* 0x30 - 0x37 */
d67fc27a 3135 I6ALU(Lock, em_xor), N, N,
73fba5f4 3136 /* 0x38 - 0x3F */
d67fc27a 3137 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3138 /* 0x40 - 0x4F */
3139 X16(D(DstReg)),
3140 /* 0x50 - 0x57 */
63540382 3141 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3142 /* 0x58 - 0x5F */
c54fe504 3143 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3144 /* 0x60 - 0x67 */
b96a7fad
TY		 3145 I(ImplicitOps | Stack | No64, em_pusha),
3146 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3147 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3148 N, N, N, N,
3149 /* 0x68 - 0x6F */
d46164db
AK		 3150 I(SrcImm | Mov | Stack, em_push),
3151 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3152 I(SrcImmByte | Mov | Stack, em_push),
3153 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3154 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3155 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3156 /* 0x70 - 0x7F */
3157 X16(D(SrcImmByte)),
3158 /* 0x80 - 0x87 */
3159 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3160 G(DstMem | SrcImm | ModRM | Group, group1),
3161 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3162 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3163 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3164 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3165 /* 0x88 - 0x8F */
b9eac5f4
AK		 3166 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3167 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3168 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3169 D(ModRM | SrcMem | NoAccess | DstReg),
3170 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3171 G(0, group1A),
73fba5f4 3172 /* 0x90 - 0x97 */
bf608f88 3173 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3174 /* 0x98 - 0x9F */
61429142 3175 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3176 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3177 II(ImplicitOps | Stack, em_pushf, pushf),
3178 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3179 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3180 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3181 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3182 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3183 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3184 /* 0xA8 - 0xAF */
9f21ca59 3185 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3186 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3187 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3188 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3189 /* 0xB0 - 0xB7 */
b9eac5f4 3190 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3191 /* 0xB8 - 0xBF */
b9eac5f4 3192 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3193 /* 0xC0 - 0xC7 */
d2c6c7ad 3194 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3195 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3196 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3197 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3198 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3199 G(ByteOp, group11), G(0, group11),
73fba5f4 3200 /* 0xC8 - 0xCF */
db5b0762 3201 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3202 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3203 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3204 /* 0xD0 - 0xD7 */
d2c6c7ad 3205 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3206 N, N, N, N,
3207 /* 0xD8 - 0xDF */
3208 N, N, N, N, N, N, N, N,
3209 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3210 X3(I(SrcImmByte, em_loop)),
3211 I(SrcImmByte, em_jcxz),
f6511935
JR		 3212 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3213 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3214 /* 0xE8 - 0xEF */
3215 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3216 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3217 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3218 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3219 /* 0xF0 - 0xF7 */
bf608f88 3220 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3221 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3222 G(ByteOp, group3), G(0, group3),
73fba5f4 3223 /* 0xF8 - 0xFF */
f411e6cd
TY		 3224 D(ImplicitOps), D(ImplicitOps),
3225 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3226 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3227};
3228
3229static struct opcode twobyte_table[256] = {
3230 /* 0x00 - 0x0F */
dee6bb70 3231 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3232 N, I(ImplicitOps | VendorSpecific, em_syscall),
3233 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3234 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3235 N, D(ImplicitOps | ModRM), N, N,
3236 /* 0x10 - 0x1F */
3237 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3238 /* 0x20 - 0x2F */
cfec82cb 3239 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3240 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3241 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3242 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3243 N, N, N, N,
3244 N, N, N, N, N, N, N, N,
3245 /* 0x30 - 0x3F */
8061252e
JR		 3246 DI(ImplicitOps | Priv, wrmsr),
3247 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3248 DI(ImplicitOps | Priv, rdmsr),
3249 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3250 I(ImplicitOps | VendorSpecific, em_sysenter),
3251 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3252 N, N,
73fba5f4
AK		 3253 N, N, N, N, N, N, N, N,
3254 /* 0x40 - 0x4F */
3255 X16(D(DstReg | SrcMem | ModRM | Mov)),
3256 /* 0x50 - 0x5F */
3257 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3258 /* 0x60 - 0x6F */
aa97bb48
AK		 3259 N, N, N, N,
3260 N, N, N, N,
3261 N, N, N, N,
3262 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3263 /* 0x70 - 0x7F */
aa97bb48
AK		 3264 N, N, N, N,
3265 N, N, N, N,
3266 N, N, N, N,
3267 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3268 /* 0x80 - 0x8F */
3269 X16(D(SrcImm)),
3270 /* 0x90 - 0x9F */
ee45b58e 3271 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3272 /* 0xA0 - 0xA7 */
c191a7a0 3273 D(Stack | Src2FS), D(Stack | Src2FS),
8061252e 3274 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3275 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3276 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3277 /* 0xA8 - 0xAF */
c191a7a0 3278 D(Stack | Src2GS), D(Stack | Src2GS),
8061252e 3279 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3280 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3281 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3282 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3283 /* 0xB0 - 0xB7 */
739ae406 3284 D2bv(DstMem | SrcReg | ModRM | Lock),
d4b4325f 3285 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
c191a7a0 3286 D(DstMem | SrcReg | ModRM | BitOp | Lock),
d4b4325f
AK		 3287 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3288 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
09b5f4d3 3289 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3290 /* 0xB8 - 0xBF */
3291 N, N,
ba7ff2b7 3292 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3293 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3294 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3295 /* 0xC0 - 0xCF */
739ae406 3296 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3297 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3298 N, N, N, GD(0, &group9),
3299 N, N, N, N, N, N, N, N,
3300 /* 0xD0 - 0xDF */
3301 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3302 /* 0xE0 - 0xEF */
3303 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3304 /* 0xF0 - 0xFF */
3305 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3306};
3307
3308#undef D
3309#undef N
3310#undef G
3311#undef GD
3312#undef I
aa97bb48 3313#undef GP
01de8b09 3314#undef EXT
73fba5f4 3315
8d8f4e9f 3316#undef D2bv
f6511935 3317#undef D2bvIP
8d8f4e9f 3318#undef I2bv
d67fc27a 3319#undef I6ALU
8d8f4e9f 3320
9dac77fa 3321static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3322{
3323 unsigned size;
3324
9dac77fa 3325 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3326 if (size == 8)
3327 size = 4;
3328 return size;
3329}
3330
3331static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3332 unsigned size, bool sign_extension)
3333{
39f21ee5
AK		 3334 int rc = X86EMUL_CONTINUE;
3335
3336 op->type = OP_IMM;
3337 op->bytes = size;
9dac77fa 3338 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3339 /* NB. Immediates are sign-extended as necessary. */
3340 switch (op->bytes) {
3341 case 1:
e85a1085 3342 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3343 break;
3344 case 2:
e85a1085 3345 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3346 break;
3347 case 4:
e85a1085 3348 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3349 break;
3350 }
3351 if (!sign_extension) {
3352 switch (op->bytes) {
3353 case 1:
3354 op->val &= 0xff;
3355 break;
3356 case 2:
3357 op->val &= 0xffff;
3358 break;
3359 case 4:
3360 op->val &= 0xffffffff;
3361 break;
3362 }
3363 }
3364done:
3365 return rc;
3366}
3367
a9945549
AK		 3368static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3369 unsigned d)
3370{
3371 int rc = X86EMUL_CONTINUE;
3372
3373 switch (d) {
3374 case OpReg:
3375 decode_register_operand(ctxt, op,
5217973e 3376 op == &ctxt->dst &&
a9945549
AK		 3377 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3378 break;
3379 case OpImmUByte:
608aabe3 3380 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3381 break;
3382 case OpMem:
41ddf978 3383 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3384 mem_common:
3385 *op = ctxt->memop;
3386 ctxt->memopp = op;
3387 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3388 fetch_bit_operand(ctxt);
3389 op->orig_val = op->val;
3390 break;
41ddf978
AK		 3391 case OpMem64:
3392 ctxt->memop.bytes = 8;
3393 goto mem_common;
a9945549
AK		 3394 case OpAcc:
3395 op->type = OP_REG;
3396 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3397 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3398 fetch_register_operand(op);
3399 op->orig_val = op->val;
3400 break;
3401 case OpDI:
3402 op->type = OP_MEM;
3403 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3404 op->addr.mem.ea =
3405 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3406 op->addr.mem.seg = VCPU_SREG_ES;
3407 op->val = 0;
3408 break;
3409 case OpDX:
3410 op->type = OP_REG;
3411 op->bytes = 2;
3412 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3413 fetch_register_operand(op);
3414 break;
4dd6a57d
AK		 3415 case OpCL:
3416 op->bytes = 1;
3417 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3418 break;
3419 case OpImmByte:
3420 rc = decode_imm(ctxt, op, 1, true);
3421 break;
3422 case OpOne:
3423 op->bytes = 1;
3424 op->val = 1;
3425 break;
3426 case OpImm:
3427 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3428 break;
0fe59128
AK		 3429 case OpMem16:
3430 ctxt->memop.bytes = 2;
3431 goto mem_common;
3432 case OpMem32:
3433 ctxt->memop.bytes = 4;
3434 goto mem_common;
3435 case OpImmU16:
3436 rc = decode_imm(ctxt, op, 2, false);
3437 break;
3438 case OpImmU:
3439 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3440 break;
3441 case OpSI:
3442 op->type = OP_MEM;
3443 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3444 op->addr.mem.ea =
3445 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3446 op->addr.mem.seg = seg_override(ctxt);
3447 op->val = 0;
3448 break;
3449 case OpImmFAddr:
3450 op->type = OP_IMM;
3451 op->addr.mem.ea = ctxt->_eip;
3452 op->bytes = ctxt->op_bytes + 2;
3453 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3454 break;
3455 case OpMemFAddr:
3456 ctxt->memop.bytes = ctxt->op_bytes + 2;
3457 goto mem_common;
c191a7a0
AK		 3458 case OpES:
3459 op->val = VCPU_SREG_ES;
3460 break;
3461 case OpCS:
3462 op->val = VCPU_SREG_CS;
3463 break;
3464 case OpSS:
3465 op->val = VCPU_SREG_SS;
3466 break;
3467 case OpDS:
3468 op->val = VCPU_SREG_DS;
3469 break;
3470 case OpFS:
3471 op->val = VCPU_SREG_FS;
3472 break;
3473 case OpGS:
3474 op->val = VCPU_SREG_GS;
3475 break;
a9945549
AK		 3476 case OpImplicit:
3477 /* Special instructions do their own operand decoding. */
3478 default:
3479 op->type = OP_NONE; /* Disable writeback. */
3480 break;
3481 }
3482
3483done:
3484 return rc;
3485}
3486
ef5d75cc 3487int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3488{
dde7e6d1
AK		 3489 int rc = X86EMUL_CONTINUE;
3490 int mode = ctxt->mode;
46561646 3491 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3492 bool op_prefix = false;
46561646 3493 struct opcode opcode;
dde7e6d1 3494
f09ed83e
AK		 3495 ctxt->memop.type = OP_NONE;
3496 ctxt->memopp = NULL;
9dac77fa
AK		 3497 ctxt->_eip = ctxt->eip;
3498 ctxt->fetch.start = ctxt->_eip;
3499 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3500 if (insn_len > 0)
9dac77fa 3501 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3502
3503 switch (mode) {
3504 case X86EMUL_MODE_REAL:
3505 case X86EMUL_MODE_VM86:
3506 case X86EMUL_MODE_PROT16:
3507 def_op_bytes = def_ad_bytes = 2;
3508 break;
3509 case X86EMUL_MODE_PROT32:
3510 def_op_bytes = def_ad_bytes = 4;
3511 break;
3512#ifdef CONFIG_X86_64
3513 case X86EMUL_MODE_PROT64:
3514 def_op_bytes = 4;
3515 def_ad_bytes = 8;
3516 break;
3517#endif
3518 default:
1d2887e2 3519 return EMULATION_FAILED;
dde7e6d1
AK		 3520 }
3521
9dac77fa
AK		 3522 ctxt->op_bytes = def_op_bytes;
3523 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3524
3525 /* Legacy prefixes. */
3526 for (;;) {
e85a1085 3527 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3528 case 0x66: /* operand-size override */
0d7cdee8 3529 op_prefix = true;
dde7e6d1 3530 /* switch between 2/4 bytes */
9dac77fa 3531 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3532 break;
3533 case 0x67: /* address-size override */
3534 if (mode == X86EMUL_MODE_PROT64)
3535 /* switch between 4/8 bytes */
9dac77fa 3536 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3537 else
3538 /* switch between 2/4 bytes */
9dac77fa 3539 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3540 break;
3541 case 0x26: /* ES override */
3542 case 0x2e: /* CS override */
3543 case 0x36: /* SS override */
3544 case 0x3e: /* DS override */
9dac77fa 3545 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3546 break;
3547 case 0x64: /* FS override */
3548 case 0x65: /* GS override */
9dac77fa 3549 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3550 break;
3551 case 0x40 ... 0x4f: /* REX */
3552 if (mode != X86EMUL_MODE_PROT64)
3553 goto done_prefixes;
9dac77fa 3554 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3555 continue;
3556 case 0xf0: /* LOCK */
9dac77fa 3557 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3558 break;
3559 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3560 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3561 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3562 break;
3563 default:
3564 goto done_prefixes;
3565 }
3566
3567 /* Any legacy prefix after a REX prefix nullifies its effect. */
3568
9dac77fa 3569 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3570 }
3571
3572done_prefixes:
3573
3574 /* REX prefix. */
9dac77fa
AK		 3575 if (ctxt->rex_prefix & 8)
3576 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3577
3578 /* Opcode byte(s). */
9dac77fa 3579 opcode = opcode_table[ctxt->b];
d3ad6243 3580 /* Two-byte opcode? */
9dac77fa
AK		 3581 if (ctxt->b == 0x0f) {
3582 ctxt->twobyte = 1;
e85a1085 3583 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3584 opcode = twobyte_table[ctxt->b];
dde7e6d1 3585 }
9dac77fa 3586 ctxt->d = opcode.flags;
dde7e6d1 3587
9dac77fa
AK		 3588 while (ctxt->d & GroupMask) {
3589 switch (ctxt->d & GroupMask) {
46561646 3590 case Group:
e85a1085 3591 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3592 --ctxt->_eip;
3593 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3594 opcode = opcode.u.group[goffset];
3595 break;
3596 case GroupDual:
e85a1085 3597 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3598 --ctxt->_eip;
3599 goffset = (ctxt->modrm >> 3) & 7;
3600 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3601 opcode = opcode.u.gdual->mod3[goffset];
3602 else
3603 opcode = opcode.u.gdual->mod012[goffset];
3604 break;
3605 case RMExt:
9dac77fa 3606 goffset = ctxt->modrm & 7;
01de8b09 3607 opcode = opcode.u.group[goffset];
46561646
AK		 3608 break;
3609 case Prefix:
9dac77fa 3610 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3611 return EMULATION_FAILED;
9dac77fa 3612 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3613 switch (simd_prefix) {
3614 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3615 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3616 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3617 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3618 }
3619 break;
3620 default:
1d2887e2 3621 return EMULATION_FAILED;
0d7cdee8 3622 }
46561646 3623
b1ea50b2 3624 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3625 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3626 }
3627
9dac77fa
AK		 3628 ctxt->execute = opcode.u.execute;
3629 ctxt->check_perm = opcode.check_perm;
3630 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3631
3632 /* Unrecognised? */
9dac77fa 3633 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3634 return EMULATION_FAILED;
dde7e6d1 3635
9dac77fa 3636 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3637 return EMULATION_FAILED;
d867162c 3638
9dac77fa
AK		 3639 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3640 ctxt->op_bytes = 8;
dde7e6d1 3641
9dac77fa 3642 if (ctxt->d & Op3264) {
7f9b4b75 3643 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3644 ctxt->op_bytes = 8;
7f9b4b75 3645 else
9dac77fa 3646 ctxt->op_bytes = 4;
7f9b4b75
AK		 3647 }
3648
9dac77fa
AK		 3649 if (ctxt->d & Sse)
3650 ctxt->op_bytes = 16;
1253791d 3651
dde7e6d1 3652 /* ModRM and SIB bytes. */
9dac77fa 3653 if (ctxt->d & ModRM) {
f09ed83e 3654 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3655 if (!ctxt->has_seg_override)
3656 set_seg_override(ctxt, ctxt->modrm_seg);
3657 } else if (ctxt->d & MemAbs)
f09ed83e 3658 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3659 if (rc != X86EMUL_CONTINUE)
3660 goto done;
3661
9dac77fa
AK		 3662 if (!ctxt->has_seg_override)
3663 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3664
f09ed83e 3665 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3666
f09ed83e
AK		 3667 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3668 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3669
dde7e6d1
AK		 3670 /*
3671 * Decode and fetch the source operand: register, memory
3672 * or immediate.
3673 */
0fe59128 3674 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 3675 if (rc != X86EMUL_CONTINUE)
3676 goto done;
3677
dde7e6d1
AK		 3678 /*
3679 * Decode and fetch the second source operand: register, memory
3680 * or immediate.
3681 */
4dd6a57d 3682 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3683 if (rc != X86EMUL_CONTINUE)
3684 goto done;
3685
dde7e6d1 3686 /* Decode and fetch the destination operand: register or memory. */
a9945549 3687 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3688
3689done:
f09ed83e
AK		 3690 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3691 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3692
1d2887e2 3693 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3694}
3695
3e2f65d5
GN		 3696static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3697{
3e2f65d5
GN		 3698 /* The second termination condition only applies for REPE
3699 * and REPNE. Test if the repeat string operation prefix is
3700 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3701 * corresponding termination condition according to:
3702 * - if REPE/REPZ and ZF = 0 then done
3703 * - if REPNE/REPNZ and ZF = 1 then done
3704 */
9dac77fa
AK		 3705 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3706 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3707 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3708 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3709 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3710 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3711 return true;
3712
3713 return false;
3714}
3715
7b105ca2 3716int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3717{
9aabc88f 3718 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3719 u64 msr_data;
1b30eaa8 3720 int rc = X86EMUL_CONTINUE;
9dac77fa 3721 int saved_dst_type = ctxt->dst.type;
8b4caf66 3722
9dac77fa 3723 ctxt->mem_read.pos = 0;
310b5d30 3724
9dac77fa 3725 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3726 rc = emulate_ud(ctxt);
1161624f
GN		 3727 goto done;
3728 }
3729
d380a5e4 3730 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3731 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3732 rc = emulate_ud(ctxt);
d380a5e4
GN		 3733 goto done;
3734 }
3735
9dac77fa 3736 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3737 rc = emulate_ud(ctxt);
081bca0e
AK		 3738 goto done;
3739 }
3740
9dac77fa 3741 if ((ctxt->d & Sse)
717746e3
AK		 3742 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3743 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3744 rc = emulate_ud(ctxt);
3745 goto done;
3746 }
3747
9dac77fa 3748 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3749 rc = emulate_nm(ctxt);
3750 goto done;
3751 }
3752
9dac77fa
AK		 3753 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3754 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3755 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3756 if (rc != X86EMUL_CONTINUE)
3757 goto done;
3758 }
3759
e92805ac 3760 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3761 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3762 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3763 goto done;
3764 }
3765
8ea7d6ae 3766 /* Instruction can only be executed in protected mode */
9dac77fa 3767 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3768 rc = emulate_ud(ctxt);
3769 goto done;
3770 }
3771
d09beabd 3772 /* Do instruction specific permission checks */
9dac77fa
AK		 3773 if (ctxt->check_perm) {
3774 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3775 if (rc != X86EMUL_CONTINUE)
3776 goto done;
3777 }
3778
9dac77fa
AK		 3779 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3780 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3781 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3782 if (rc != X86EMUL_CONTINUE)
3783 goto done;
3784 }
3785
9dac77fa 3786 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3787 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3788 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3789 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3790 goto done;
3791 }
b9fa9d6b
AK		 3792 }
3793
9dac77fa
AK		 3794 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3795 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3796 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3797 if (rc != X86EMUL_CONTINUE)
8b4caf66 3798 goto done;
9dac77fa 3799 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3800 }
3801
9dac77fa
AK		 3802 if (ctxt->src2.type == OP_MEM) {
3803 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3804 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3805 if (rc != X86EMUL_CONTINUE)
3806 goto done;
3807 }
3808
9dac77fa 3809 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3810 goto special_insn;
3811
3812
9dac77fa 3813 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3814 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3815 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3816 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3817 if (rc != X86EMUL_CONTINUE)
3818 goto done;
038e51de 3819 }
9dac77fa 3820 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3821
018a98db
AK		 3822special_insn:
3823
9dac77fa
AK		 3824 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3825 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3826 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3827 if (rc != X86EMUL_CONTINUE)
3828 goto done;
3829 }
3830
9dac77fa
AK		 3831 if (ctxt->execute) {
3832 rc = ctxt->execute(ctxt);
ef65c889
AK		 3833 if (rc != X86EMUL_CONTINUE)
3834 goto done;
3835 goto writeback;
3836 }
3837
9dac77fa 3838 if (ctxt->twobyte)
6aa8b732
AK		 3839 goto twobyte_insn;
3840
9dac77fa 3841 switch (ctxt->b) {
0934ac9d 3842 case 0x06: /* push es */
0934ac9d 3843 case 0x0e: /* push cs */
0934ac9d 3844 case 0x16: /* push ss */
0934ac9d 3845 case 0x1e: /* push ds */
c191a7a0 3846 rc = emulate_push_sreg(ctxt, ctxt->src2.val);
0934ac9d 3847 break;
c191a7a0
AK		 3848 case 0x07: /* pop es */
3849 case 0x17: /* pop ss */
0934ac9d 3850 case 0x1f: /* pop ds */
c191a7a0 3851 rc = emulate_pop_sreg(ctxt, ctxt->src2.val);
33615aa9 3852 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3853 emulate_1op(ctxt, "inc");
33615aa9
AK		 3854 break;
3855 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3856 emulate_1op(ctxt, "dec");
33615aa9 3857 break;
6aa8b732 3858 case 0x63: /* movsxd */
8b4caf66 3859 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3860 goto cannot_emulate;
9dac77fa 3861 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3862 break;
018a98db
AK		 3863 case 0x6c: /* insb */
3864 case 0x6d: /* insw/insd */
9dac77fa 3865 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3866 goto do_io_in;
018a98db
AK		 3867 case 0x6e: /* outsb */
3868 case 0x6f: /* outsw/outsd */
9dac77fa 3869 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3870 goto do_io_out;
7972995b 3871 break;
b2833e3c 3872 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3873 if (test_cc(ctxt->b, ctxt->eflags))
3874 jmp_rel(ctxt, ctxt->src.val);
018a98db 3875 break;
7e0b54b1 3876 case 0x8d: /* lea r16/r32, m */
9dac77fa 3877 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3878 break;
6aa8b732 3879 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3880 rc = em_grp1a(ctxt);
6aa8b732 3881 break;
3d9e77df 3882 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3883 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3884 break;
e4f973ae
TY		 3885 rc = em_xchg(ctxt);
3886 break;
e8b6fa70 3887 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3888 switch (ctxt->op_bytes) {
3889 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3890 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3891 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3892 }
3893 break;
018a98db 3894 case 0xc0 ... 0xc1:
51187683 3895 rc = em_grp2(ctxt);
018a98db 3896 break;
6e154e56 3897 case 0xcc: /* int3 */
5c5df76b
TY		 3898 rc = emulate_int(ctxt, 3);
3899 break;
6e154e56 3900 case 0xcd: /* int n */
9dac77fa 3901 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3902 break;
3903 case 0xce: /* into */
5c5df76b
TY		 3904 if (ctxt->eflags & EFLG_OF)
3905 rc = emulate_int(ctxt, 4);
6e154e56 3906 break;
018a98db 3907 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3908 rc = em_grp2(ctxt);
018a98db
AK		 3909 break;
3910 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3911 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3912 rc = em_grp2(ctxt);
018a98db 3913 break;
a6a3034c
MG		 3914 case 0xe4: /* inb */
3915 case 0xe5: /* in */
cf8f70bf 3916 goto do_io_in;
a6a3034c
MG		 3917 case 0xe6: /* outb */
3918 case 0xe7: /* out */
cf8f70bf 3919 goto do_io_out;
1a52e051 3920 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3921 long int rel = ctxt->src.val;
3922 ctxt->src.val = (unsigned long) ctxt->_eip;
3923 jmp_rel(ctxt, rel);
4487b3b4 3924 rc = em_push(ctxt);
8cdbd2c9 3925 break;
1a52e051
NK		 3926 }
3927 case 0xe9: /* jmp rel */
db5b0762 3928 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3929 jmp_rel(ctxt, ctxt->src.val);
3930 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3931 break;
a6a3034c
MG		 3932 case 0xec: /* in al,dx */
3933 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3934 do_io_in:
9dac77fa
AK		 3935 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3936 &ctxt->dst.val))
cf8f70bf
GN		 3937 goto done; /* IO is needed */
3938 break;
ce7a0ad3
WY		 3939 case 0xee: /* out dx,al */
3940 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3941 do_io_out:
9dac77fa
AK		 3942 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3943 &ctxt->src.val, 1);
3944 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3945 break;
111de5d6 3946 case 0xf4: /* hlt */
6c3287f7 3947 ctxt->ops->halt(ctxt);
19fdfa0d 3948 break;
111de5d6
AK		 3949 case 0xf5: /* cmc */
3950 /* complement carry flag from eflags reg */
3951 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 3952 break;
3953 case 0xf8: /* clc */
3954 ctxt->eflags &= ~EFLG_CF;
111de5d6 3955 break;
8744aa9a
MG		 3956 case 0xf9: /* stc */
3957 ctxt->eflags |= EFLG_CF;
3958 break;
fb4616f4
MG		 3959 case 0xfc: /* cld */
3960 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3961 break;
3962 case 0xfd: /* std */
3963 ctxt->eflags |= EFLG_DF;
fb4616f4 3964 break;
ea79849d 3965 case 0xfe: /* Grp4 */
51187683 3966 rc = em_grp45(ctxt);
018a98db 3967 break;
ea79849d 3968 case 0xff: /* Grp5 */
51187683
TY		 3969 rc = em_grp45(ctxt);
3970 break;
91269b8f
AK		 3971 default:
3972 goto cannot_emulate;
6aa8b732 3973 }
018a98db 3974
7d9ddaed
AK		 3975 if (rc != X86EMUL_CONTINUE)
3976 goto done;
3977
018a98db 3978writeback:
adddcecf 3979 rc = writeback(ctxt);
1b30eaa8 3980 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3981 goto done;
3982
5cd21917
GN		 3983 /*
3984 * restore dst type in case the decoding will be reused
3985 * (happens for string instruction )
3986 */
9dac77fa 3987 ctxt->dst.type = saved_dst_type;
5cd21917 3988
9dac77fa
AK		 3989 if ((ctxt->d & SrcMask) == SrcSI)
3990 string_addr_inc(ctxt, seg_override(ctxt),
3991 VCPU_REGS_RSI, &ctxt->src);
a682e354 3992
9dac77fa 3993 if ((ctxt->d & DstMask) == DstDI)
90de84f5 3994 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 3995 &ctxt->dst);
d9271123 3996
9dac77fa
AK		 3997 if (ctxt->rep_prefix && (ctxt->d & String)) {
3998 struct read_cache *r = &ctxt->io_read;
3999 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4000
d2ddd1c4
GN		 4001 if (!string_insn_completed(ctxt)) {
4002 /*
4003 * Re-enter guest when pio read ahead buffer is empty
4004 * or, if it is not used, after each 1024 iteration.
4005 */
9dac77fa 4006 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4007 (r->end == 0 || r->end != r->pos)) {
4008 /*
4009 * Reset read cache. Usually happens before
4010 * decode, but since instruction is restarted
4011 * we have to do it here.
4012 */
9dac77fa 4013 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4014 return EMULATION_RESTART;
4015 }
4016 goto done; /* skip rip writeback */
0fa6ccbd 4017 }
5cd21917 4018 }
d2ddd1c4 4019
9dac77fa 4020 ctxt->eip = ctxt->_eip;
018a98db
AK		 4021
4022done:
da9cb575
AK		 4023 if (rc == X86EMUL_PROPAGATE_FAULT)
4024 ctxt->have_exception = true;
775fde86
JR		 4025 if (rc == X86EMUL_INTERCEPTED)
4026 return EMULATION_INTERCEPTED;
4027
d2ddd1c4 4028 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4029
4030twobyte_insn:
9dac77fa 4031 switch (ctxt->b) {
018a98db 4032 case 0x09: /* wbinvd */
cfb22375 4033 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4034 break;
4035 case 0x08: /* invd */
018a98db
AK		 4036 case 0x0d: /* GrpP (prefetch) */
4037 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4038 break;
4039 case 0x20: /* mov cr, reg */
9dac77fa 4040 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4041 break;
6aa8b732 4042 case 0x21: /* mov from dr to reg */
9dac77fa 4043 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4044 break;
018a98db 4045 case 0x22: /* mov reg, cr */
9dac77fa 4046 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4047 emulate_gp(ctxt, 0);
da9cb575 4048 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4049 goto done;
4050 }
9dac77fa 4051 ctxt->dst.type = OP_NONE;
018a98db 4052 break;
6aa8b732 4053 case 0x23: /* mov from reg to dr */
9dac77fa 4054 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4055 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4056 ~0ULL : ~0U)) < 0) {
338dbc97 4057 /* #UD condition is already handled by the code above */
54b8486f 4058 emulate_gp(ctxt, 0);
da9cb575 4059 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4060 goto done;
4061 }
4062
9dac77fa 4063 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4064 break;
018a98db
AK		 4065 case 0x30:
4066 /* wrmsr */
9dac77fa
AK		 4067 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4068 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4069 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4070 emulate_gp(ctxt, 0);
da9cb575 4071 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4072 goto done;
018a98db
AK		 4073 }
4074 rc = X86EMUL_CONTINUE;
018a98db
AK		 4075 break;
4076 case 0x32:
4077 /* rdmsr */
9dac77fa 4078 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4079 emulate_gp(ctxt, 0);
da9cb575 4080 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4081 goto done;
018a98db 4082 } else {
9dac77fa
AK		 4083 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4084 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4085 }
4086 rc = X86EMUL_CONTINUE;
018a98db 4087 break;
6aa8b732 4088 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4089 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4090 if (!test_cc(ctxt->b, ctxt->eflags))
4091 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4092 break;
b2833e3c 4093 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4094 if (test_cc(ctxt->b, ctxt->eflags))
4095 jmp_rel(ctxt, ctxt->src.val);
018a98db 4096 break;
ee45b58e 4097 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4098 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4099 break;
0934ac9d 4100 case 0xa0: /* push fs */
c191a7a0
AK		 4101 case 0xa8: /* push gs */
4102 rc = emulate_push_sreg(ctxt, ctxt->src2.val);
0934ac9d
MG		 4103 break;
4104 case 0xa1: /* pop fs */
c191a7a0
AK		 4105 case 0xa9: /* pop gs */
4106 rc = emulate_pop_sreg(ctxt, ctxt->src2.val);
0934ac9d 4107 break;
7de75248
NK		 4108 case 0xa3:
4109 bt: /* bt */
9dac77fa 4110 ctxt->dst.type = OP_NONE;
e4e03ded 4111 /* only subword offset */
9dac77fa 4112 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4113 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4114 break;
9bf8ea42
GT		 4115 case 0xa4: /* shld imm8, r, r/m */
4116 case 0xa5: /* shld cl, r, r/m */
761441b9 4117 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4118 break;
7de75248
NK		 4119 case 0xab:
4120 bts: /* bts */
a31b9cea 4121 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4122 break;
9bf8ea42
GT		 4123 case 0xac: /* shrd imm8, r, r/m */
4124 case 0xad: /* shrd cl, r, r/m */
761441b9 4125 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4126 break;
2a7c5b8b
GC		 4127 case 0xae: /* clflush */
4128 break;
6aa8b732
AK		 4129 case 0xb0 ... 0xb1: /* cmpxchg */
4130 /*
4131 * Save real source value, then compare EAX against
4132 * destination.
4133 */
9dac77fa
AK		 4134 ctxt->src.orig_val = ctxt->src.val;
4135 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4136 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4137 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4138 /* Success: write back to memory. */
9dac77fa 4139 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4140 } else {
4141 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4142 ctxt->dst.type = OP_REG;
4143 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4144 }
4145 break;
6aa8b732
AK		 4146 case 0xb3:
4147 btr: /* btr */
a31b9cea 4148 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4149 break;
6aa8b732 4150 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4151 ctxt->dst.bytes = ctxt->op_bytes;
4152 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4153 : (u16) ctxt->src.val;
6aa8b732 4154 break;
6aa8b732 4155 case 0xba: /* Grp8 */
9dac77fa 4156 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4157 case 0:
4158 goto bt;
4159 case 1:
4160 goto bts;
4161 case 2:
4162 goto btr;
4163 case 3:
4164 goto btc;
4165 }
4166 break;
7de75248
NK		 4167 case 0xbb:
4168 btc: /* btc */
a31b9cea 4169 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4170 break;
d9574a25
WY		 4171 case 0xbc: { /* bsf */
4172 u8 zf;
4173 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4174 : "=r"(ctxt->dst.val), "=q"(zf)
4175 : "r"(ctxt->src.val));
d9574a25
WY		 4176 ctxt->eflags &= ~X86_EFLAGS_ZF;
4177 if (zf) {
4178 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4179 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4180 }
4181 break;
4182 }
4183 case 0xbd: { /* bsr */
4184 u8 zf;
4185 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4186 : "=r"(ctxt->dst.val), "=q"(zf)
4187 : "r"(ctxt->src.val));
d9574a25
WY		 4188 ctxt->eflags &= ~X86_EFLAGS_ZF;
4189 if (zf) {
4190 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4191 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4192 }
4193 break;
4194 }
6aa8b732 4195 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4196 ctxt->dst.bytes = ctxt->op_bytes;
4197 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4198 (s16) ctxt->src.val;
6aa8b732 4199 break;
92f738a5 4200 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4201 emulate_2op_SrcV(ctxt, "add");
92f738a5 4202 /* Write back the register source. */
9dac77fa
AK		 4203 ctxt->src.val = ctxt->dst.orig_val;
4204 write_register_operand(&ctxt->src);
92f738a5 4205 break;
a012e65a 4206 case 0xc3: /* movnti */
9dac77fa
AK		 4207 ctxt->dst.bytes = ctxt->op_bytes;
4208 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4209 (u64) ctxt->src.val;
a012e65a 4210 break;
6aa8b732 4211 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4212 rc = em_grp9(ctxt);
8cdbd2c9 4213 break;
91269b8f
AK		 4214 default:
4215 goto cannot_emulate;
6aa8b732 4216 }
7d9ddaed
AK		 4217
4218 if (rc != X86EMUL_CONTINUE)
4219 goto done;
4220
6aa8b732
AK		 4221 goto writeback;
4222
4223cannot_emulate:
a0c0ab2f 4224 return EMULATION_FAILED;
6aa8b732 4225}
Linux kernel - Deliverables
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