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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 27 | #else |
edf88417 | 28 | #include <linux/kvm_host.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
30 | #define DPRINTF(x...) do {} while (0) |
31 | #endif | |
6aa8b732 | 32 | #include <linux/module.h> |
56e82318 | 33 | #include <asm/kvm_emulate.h> |
6aa8b732 | 34 | |
3eeb3288 | 35 | #include "x86.h" |
e99f0507 | 36 | |
6aa8b732 AK |
37 | /* |
38 | * Opcode effective-address decode tables. | |
39 | * Note that we only emulate instructions that have at least one memory | |
40 | * operand (excluding implicit stack references). We assume that stack | |
41 | * references and instruction fetches will never occur in special memory | |
42 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
43 | * not be handled. | |
44 | */ | |
45 | ||
46 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
47 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
48 | /* Destination operand type. */ | |
49 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
50 | #define DstReg (2<<1) /* Register operand. */ | |
51 | #define DstMem (3<<1) /* Memory operand. */ | |
9c9fddd0 GT |
52 | #define DstAcc (4<<1) /* Destination Accumulator */ |
53 | #define DstMask (7<<1) | |
6aa8b732 | 54 | /* Source operand type. */ |
9c9fddd0 GT |
55 | #define SrcNone (0<<4) /* No source operand. */ |
56 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
57 | #define SrcReg (1<<4) /* Register operand. */ | |
58 | #define SrcMem (2<<4) /* Memory operand. */ | |
59 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
60 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
61 | #define SrcImm (5<<4) /* Immediate operand. */ | |
62 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 63 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 64 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 65 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
341de7e3 | 66 | #define SrcMask (0xf<<4) |
6aa8b732 | 67 | /* Generic ModRM decode. */ |
341de7e3 | 68 | #define ModRM (1<<8) |
6aa8b732 | 69 | /* Destination is only written; never read. */ |
341de7e3 GN |
70 | #define Mov (1<<9) |
71 | #define BitOp (1<<10) | |
72 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
73 | #define String (1<<12) /* String instruction (rep capable) */ |
74 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
75 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
76 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
77 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | |
d8769fed MG |
78 | /* Misc flags */ |
79 | #define No64 (1<<28) | |
0dc8d10f GT |
80 | /* Source 2 operand type */ |
81 | #define Src2None (0<<29) | |
82 | #define Src2CL (1<<29) | |
83 | #define Src2ImmByte (2<<29) | |
84 | #define Src2One (3<<29) | |
a5f868bd | 85 | #define Src2Imm16 (4<<29) |
0dc8d10f | 86 | #define Src2Mask (7<<29) |
6aa8b732 | 87 | |
43bb19cd | 88 | enum { |
1d6ad207 | 89 | Group1_80, Group1_81, Group1_82, Group1_83, |
d95058a1 | 90 | Group1A, Group3_Byte, Group3, Group4, Group5, Group7, |
60a29d4e | 91 | Group8, Group9, |
43bb19cd AK |
92 | }; |
93 | ||
45ed60b3 | 94 | static u32 opcode_table[256] = { |
6aa8b732 AK |
95 | /* 0x00 - 0x07 */ |
96 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
97 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
0934ac9d | 98 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 99 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 AK |
100 | /* 0x08 - 0x0F */ |
101 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
102 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
94677e61 MG |
103 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
104 | ImplicitOps | Stack | No64, 0, | |
6aa8b732 AK |
105 | /* 0x10 - 0x17 */ |
106 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
107 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
0934ac9d | 108 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 109 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 AK |
110 | /* 0x18 - 0x1F */ |
111 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
112 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
0934ac9d | 113 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 114 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 AK |
115 | /* 0x20 - 0x27 */ |
116 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
117 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
aa3a816b | 118 | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 AK |
119 | /* 0x28 - 0x2F */ |
120 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
121 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
122 | 0, 0, 0, 0, | |
123 | /* 0x30 - 0x37 */ | |
124 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
125 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
126 | 0, 0, 0, 0, | |
127 | /* 0x38 - 0x3F */ | |
128 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
129 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
8a9fee67 GT |
130 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
131 | 0, 0, | |
d77a2507 | 132 | /* 0x40 - 0x47 */ |
33615aa9 | 133 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 134 | /* 0x48 - 0x4F */ |
33615aa9 | 135 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 136 | /* 0x50 - 0x57 */ |
6e3d5dfb AK |
137 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, |
138 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, | |
7f0aaee0 | 139 | /* 0x58 - 0x5F */ |
6e3d5dfb AK |
140 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, |
141 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, | |
7d316911 | 142 | /* 0x60 - 0x67 */ |
abcf14b5 MG |
143 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
144 | 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , | |
7d316911 NK |
145 | 0, 0, 0, 0, |
146 | /* 0x68 - 0x6F */ | |
91ed7a0e | 147 | SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, |
e70669ab LV |
148 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
149 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 | 150 | /* 0x70 - 0x77 */ |
b2833e3c GN |
151 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
152 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
55bebde4 | 153 | /* 0x78 - 0x7F */ |
b2833e3c GN |
154 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
155 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
6aa8b732 | 156 | /* 0x80 - 0x87 */ |
1d6ad207 AK |
157 | Group | Group1_80, Group | Group1_81, |
158 | Group | Group1_82, Group | Group1_83, | |
6aa8b732 AK |
159 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
160 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
161 | /* 0x88 - 0x8F */ | |
162 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
163 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
38d5bc6d | 164 | DstMem | SrcReg | ModRM | Mov, ModRM | DstReg, |
4257198a | 165 | DstReg | SrcMem | ModRM | Mov, Group | Group1A, |
b13354f8 MG |
166 | /* 0x90 - 0x97 */ |
167 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, | |
168 | /* 0x98 - 0x9F */ | |
d8769fed | 169 | 0, 0, SrcImm | Src2Imm16 | No64, 0, |
0654169e | 170 | ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, |
6aa8b732 | 171 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
172 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
173 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
b9fa9d6b AK |
174 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
175 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
6aa8b732 | 176 | /* 0xA8 - 0xAF */ |
b9fa9d6b AK |
177 | 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
178 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, | |
179 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
a5e2e82b MG |
180 | /* 0xB0 - 0xB7 */ |
181 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
182 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
183 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
184 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
185 | /* 0xB8 - 0xBF */ | |
186 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
187 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
188 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
189 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
6aa8b732 | 190 | /* 0xC0 - 0xC7 */ |
d9413cd7 | 191 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 192 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 193 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 | 194 | /* 0xC8 - 0xCF */ |
e637b823 | 195 | 0, 0, 0, ImplicitOps | Stack, |
d8769fed | 196 | ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps, |
6aa8b732 AK |
197 | /* 0xD0 - 0xD7 */ |
198 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
199 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
200 | 0, 0, 0, 0, | |
201 | /* 0xD8 - 0xDF */ | |
202 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b | 203 | /* 0xE0 - 0xE7 */ |
a6a3034c | 204 | 0, 0, 0, 0, |
84ce66a6 GN |
205 | ByteOp | SrcImmUByte, SrcImmUByte, |
206 | ByteOp | SrcImmUByte, SrcImmUByte, | |
098c937b | 207 | /* 0xE8 - 0xEF */ |
d53c4777 | 208 | SrcImm | Stack, SrcImm | ImplicitOps, |
d8769fed | 209 | SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps, |
a6a3034c MG |
210 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, |
211 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, | |
6aa8b732 AK |
212 | /* 0xF0 - 0xF7 */ |
213 | 0, 0, 0, 0, | |
7d858a19 | 214 | ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3, |
6aa8b732 | 215 | /* 0xF8 - 0xFF */ |
b284be57 | 216 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fb4616f4 | 217 | ImplicitOps, ImplicitOps, Group | Group4, Group | Group5, |
6aa8b732 AK |
218 | }; |
219 | ||
45ed60b3 | 220 | static u32 twobyte_table[256] = { |
6aa8b732 | 221 | /* 0x00 - 0x0F */ |
e99f0507 | 222 | 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0, |
651a3e29 | 223 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
6aa8b732 AK |
224 | /* 0x10 - 0x1F */ |
225 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
226 | /* 0x20 - 0x2F */ | |
227 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, | |
228 | 0, 0, 0, 0, 0, 0, 0, 0, | |
229 | /* 0x30 - 0x3F */ | |
e99f0507 AP |
230 | ImplicitOps, 0, ImplicitOps, 0, |
231 | ImplicitOps, ImplicitOps, 0, 0, | |
232 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6aa8b732 AK |
233 | /* 0x40 - 0x47 */ |
234 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
235 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
236 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
237 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
238 | /* 0x48 - 0x4F */ | |
239 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
240 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
241 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
242 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
243 | /* 0x50 - 0x5F */ | |
244 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
245 | /* 0x60 - 0x6F */ | |
246 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
247 | /* 0x70 - 0x7F */ | |
248 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
249 | /* 0x80 - 0x8F */ | |
b2833e3c GN |
250 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, |
251 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, | |
6aa8b732 AK |
252 | /* 0x90 - 0x9F */ |
253 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
254 | /* 0xA0 - 0xA7 */ | |
0934ac9d MG |
255 | ImplicitOps | Stack, ImplicitOps | Stack, |
256 | 0, DstMem | SrcReg | ModRM | BitOp, | |
9bf8ea42 GT |
257 | DstMem | SrcReg | Src2ImmByte | ModRM, |
258 | DstMem | SrcReg | Src2CL | ModRM, 0, 0, | |
6aa8b732 | 259 | /* 0xA8 - 0xAF */ |
0934ac9d MG |
260 | ImplicitOps | Stack, ImplicitOps | Stack, |
261 | 0, DstMem | SrcReg | ModRM | BitOp, | |
9bf8ea42 GT |
262 | DstMem | SrcReg | Src2ImmByte | ModRM, |
263 | DstMem | SrcReg | Src2CL | ModRM, | |
264 | ModRM, 0, | |
6aa8b732 AK |
265 | /* 0xB0 - 0xB7 */ |
266 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, | |
038e51de | 267 | DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
268 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
269 | DstReg | SrcMem16 | ModRM | Mov, | |
270 | /* 0xB8 - 0xBF */ | |
2db2c2eb | 271 | 0, 0, Group | Group8, DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
272 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
273 | DstReg | SrcMem16 | ModRM | Mov, | |
274 | /* 0xC0 - 0xCF */ | |
60a29d4e GN |
275 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, |
276 | 0, 0, 0, Group | GroupDual | Group9, | |
a012e65a | 277 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
278 | /* 0xD0 - 0xDF */ |
279 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
280 | /* 0xE0 - 0xEF */ | |
281 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
282 | /* 0xF0 - 0xFF */ | |
283 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
284 | }; | |
285 | ||
45ed60b3 | 286 | static u32 group_table[] = { |
1d6ad207 AK |
287 | [Group1_80*8] = |
288 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
289 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
290 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
291 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
292 | [Group1_81*8] = | |
293 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
294 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
295 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
296 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
297 | [Group1_82*8] = | |
298 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
299 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
300 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
301 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
302 | [Group1_83*8] = | |
303 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
304 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
305 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
306 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
43bb19cd AK |
307 | [Group1A*8] = |
308 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 AK |
309 | [Group3_Byte*8] = |
310 | ByteOp | SrcImm | DstMem | ModRM, 0, | |
311 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
312 | 0, 0, 0, 0, | |
313 | [Group3*8] = | |
41afa025 | 314 | DstMem | SrcImm | ModRM, 0, |
6eb06cb2 | 315 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
7d858a19 | 316 | 0, 0, 0, 0, |
fd60754e AK |
317 | [Group4*8] = |
318 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
319 | 0, 0, 0, 0, 0, 0, | |
320 | [Group5*8] = | |
d19292e4 MG |
321 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
322 | SrcMem | ModRM | Stack, 0, | |
ef46f18e | 323 | SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0, |
d95058a1 AK |
324 | [Group7*8] = |
325 | 0, 0, ModRM | SrcMem, ModRM | SrcMem, | |
16286d08 AK |
326 | SrcNone | ModRM | DstMem | Mov, 0, |
327 | SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp, | |
2db2c2eb GN |
328 | [Group8*8] = |
329 | 0, 0, 0, 0, | |
330 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
331 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
60a29d4e GN |
332 | [Group9*8] = |
333 | 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, | |
e09d082c AK |
334 | }; |
335 | ||
45ed60b3 | 336 | static u32 group2_table[] = { |
d95058a1 | 337 | [Group7*8] = |
fbce554e | 338 | SrcNone | ModRM, 0, 0, SrcNone | ModRM, |
16286d08 AK |
339 | SrcNone | ModRM | DstMem | Mov, 0, |
340 | SrcMem16 | ModRM | Mov, 0, | |
60a29d4e GN |
341 | [Group9*8] = |
342 | 0, 0, 0, 0, 0, 0, 0, 0, | |
e09d082c AK |
343 | }; |
344 | ||
6aa8b732 | 345 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
346 | #define EFLG_ID (1<<21) |
347 | #define EFLG_VIP (1<<20) | |
348 | #define EFLG_VIF (1<<19) | |
349 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
350 | #define EFLG_VM (1<<17) |
351 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
352 | #define EFLG_IOPL (3<<12) |
353 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
354 | #define EFLG_OF (1<<11) |
355 | #define EFLG_DF (1<<10) | |
b1d86143 | 356 | #define EFLG_IF (1<<9) |
d4c6a154 | 357 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
358 | #define EFLG_SF (1<<7) |
359 | #define EFLG_ZF (1<<6) | |
360 | #define EFLG_AF (1<<4) | |
361 | #define EFLG_PF (1<<2) | |
362 | #define EFLG_CF (1<<0) | |
363 | ||
364 | /* | |
365 | * Instruction emulation: | |
366 | * Most instructions are emulated directly via a fragment of inline assembly | |
367 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
368 | * any modified flags. | |
369 | */ | |
370 | ||
05b3e0c2 | 371 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
372 | #define _LO32 "k" /* force 32-bit operand */ |
373 | #define _STK "%%rsp" /* stack pointer */ | |
374 | #elif defined(__i386__) | |
375 | #define _LO32 "" /* force 32-bit operand */ | |
376 | #define _STK "%%esp" /* stack pointer */ | |
377 | #endif | |
378 | ||
379 | /* | |
380 | * These EFLAGS bits are restored from saved value during emulation, and | |
381 | * any changes are written back to the saved value after emulation. | |
382 | */ | |
383 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
384 | ||
385 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
386 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
387 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
388 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
389 | "push %"_tmp"; " \ | |
390 | "push %"_tmp"; " \ | |
391 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
392 | "andl %"_LO32 _tmp",("_STK"); " \ | |
393 | "pushf; " \ | |
394 | "notl %"_LO32 _tmp"; " \ | |
395 | "andl %"_LO32 _tmp",("_STK"); " \ | |
396 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
397 | "pop %"_tmp"; " \ | |
398 | "orl %"_LO32 _tmp",("_STK"); " \ | |
399 | "popf; " \ | |
400 | "pop %"_sav"; " | |
6aa8b732 AK |
401 | |
402 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
403 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
404 | /* _sav |= EFLAGS & _msk; */ \ | |
405 | "pushf; " \ | |
406 | "pop %"_tmp"; " \ | |
407 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
408 | "orl %"_LO32 _tmp",%"_sav"; " | |
409 | ||
dda96d8f AK |
410 | #ifdef CONFIG_X86_64 |
411 | #define ON64(x) x | |
412 | #else | |
413 | #define ON64(x) | |
414 | #endif | |
415 | ||
6b7ad61f AK |
416 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
417 | do { \ | |
418 | __asm__ __volatile__ ( \ | |
419 | _PRE_EFLAGS("0", "4", "2") \ | |
420 | _op _suffix " %"_x"3,%1; " \ | |
421 | _POST_EFLAGS("0", "4", "2") \ | |
422 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
423 | "=&r" (_tmp) \ | |
424 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 425 | } while (0) |
6b7ad61f AK |
426 | |
427 | ||
6aa8b732 AK |
428 | /* Raw emulation: instruction has two explicit operands. */ |
429 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
430 | do { \ |
431 | unsigned long _tmp; \ | |
432 | \ | |
433 | switch ((_dst).bytes) { \ | |
434 | case 2: \ | |
435 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
436 | break; \ | |
437 | case 4: \ | |
438 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
439 | break; \ | |
440 | case 8: \ | |
441 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
442 | break; \ | |
443 | } \ | |
6aa8b732 AK |
444 | } while (0) |
445 | ||
446 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
447 | do { \ | |
6b7ad61f | 448 | unsigned long _tmp; \ |
d77c26fc | 449 | switch ((_dst).bytes) { \ |
6aa8b732 | 450 | case 1: \ |
6b7ad61f | 451 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
452 | break; \ |
453 | default: \ | |
454 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
455 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
456 | break; \ | |
457 | } \ | |
458 | } while (0) | |
459 | ||
460 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
461 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
462 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
463 | "b", "c", "b", "c", "b", "c", "b", "c") | |
464 | ||
465 | /* Source operand is byte, word, long or quad sized. */ | |
466 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
467 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
468 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
469 | ||
470 | /* Source operand is word, long or quad sized. */ | |
471 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
472 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
473 | "w", "r", _LO32, "r", "", "r") | |
474 | ||
d175226a GT |
475 | /* Instruction has three operands and one operand is stored in ECX register */ |
476 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
477 | do { \ | |
478 | unsigned long _tmp; \ | |
479 | _type _clv = (_cl).val; \ | |
480 | _type _srcv = (_src).val; \ | |
481 | _type _dstv = (_dst).val; \ | |
482 | \ | |
483 | __asm__ __volatile__ ( \ | |
484 | _PRE_EFLAGS("0", "5", "2") \ | |
485 | _op _suffix " %4,%1 \n" \ | |
486 | _POST_EFLAGS("0", "5", "2") \ | |
487 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
488 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
489 | ); \ | |
490 | \ | |
491 | (_cl).val = (unsigned long) _clv; \ | |
492 | (_src).val = (unsigned long) _srcv; \ | |
493 | (_dst).val = (unsigned long) _dstv; \ | |
494 | } while (0) | |
495 | ||
496 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
497 | do { \ | |
498 | switch ((_dst).bytes) { \ | |
499 | case 2: \ | |
500 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
501 | "w", unsigned short); \ | |
502 | break; \ | |
503 | case 4: \ | |
504 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
505 | "l", unsigned int); \ | |
506 | break; \ | |
507 | case 8: \ | |
508 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
509 | "q", unsigned long)); \ | |
510 | break; \ | |
511 | } \ | |
512 | } while (0) | |
513 | ||
dda96d8f | 514 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
515 | do { \ |
516 | unsigned long _tmp; \ | |
517 | \ | |
dda96d8f AK |
518 | __asm__ __volatile__ ( \ |
519 | _PRE_EFLAGS("0", "3", "2") \ | |
520 | _op _suffix " %1; " \ | |
521 | _POST_EFLAGS("0", "3", "2") \ | |
522 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
523 | "=&r" (_tmp) \ | |
524 | : "i" (EFLAGS_MASK)); \ | |
525 | } while (0) | |
526 | ||
527 | /* Instruction has only one explicit operand (no source operand). */ | |
528 | #define emulate_1op(_op, _dst, _eflags) \ | |
529 | do { \ | |
d77c26fc | 530 | switch ((_dst).bytes) { \ |
dda96d8f AK |
531 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
532 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
533 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
534 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
535 | } \ |
536 | } while (0) | |
537 | ||
6aa8b732 AK |
538 | /* Fetch next part of the instruction being emulated. */ |
539 | #define insn_fetch(_type, _size, _eip) \ | |
540 | ({ unsigned long _x; \ | |
62266869 | 541 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
d77c26fc | 542 | if (rc != 0) \ |
6aa8b732 AK |
543 | goto done; \ |
544 | (_eip) += (_size); \ | |
545 | (_type)_x; \ | |
546 | }) | |
547 | ||
ddcb2885 HH |
548 | static inline unsigned long ad_mask(struct decode_cache *c) |
549 | { | |
550 | return (1UL << (c->ad_bytes << 3)) - 1; | |
551 | } | |
552 | ||
6aa8b732 | 553 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
554 | static inline unsigned long |
555 | address_mask(struct decode_cache *c, unsigned long reg) | |
556 | { | |
557 | if (c->ad_bytes == sizeof(unsigned long)) | |
558 | return reg; | |
559 | else | |
560 | return reg & ad_mask(c); | |
561 | } | |
562 | ||
563 | static inline unsigned long | |
564 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
565 | { | |
566 | return base + address_mask(c, reg); | |
567 | } | |
568 | ||
7a957275 HH |
569 | static inline void |
570 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
571 | { | |
572 | if (c->ad_bytes == sizeof(unsigned long)) | |
573 | *reg += inc; | |
574 | else | |
575 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
576 | } | |
6aa8b732 | 577 | |
7a957275 HH |
578 | static inline void jmp_rel(struct decode_cache *c, int rel) |
579 | { | |
580 | register_address_increment(c, &c->eip, rel); | |
581 | } | |
098c937b | 582 | |
7a5b56df AK |
583 | static void set_seg_override(struct decode_cache *c, int seg) |
584 | { | |
585 | c->has_seg_override = true; | |
586 | c->seg_override = seg; | |
587 | } | |
588 | ||
589 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) | |
590 | { | |
591 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
592 | return 0; | |
593 | ||
594 | return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg); | |
595 | } | |
596 | ||
597 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
598 | struct decode_cache *c) | |
599 | { | |
600 | if (!c->has_seg_override) | |
601 | return 0; | |
602 | ||
603 | return seg_base(ctxt, c->seg_override); | |
604 | } | |
605 | ||
606 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt) | |
607 | { | |
608 | return seg_base(ctxt, VCPU_SREG_ES); | |
609 | } | |
610 | ||
611 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt) | |
612 | { | |
613 | return seg_base(ctxt, VCPU_SREG_SS); | |
614 | } | |
615 | ||
62266869 AK |
616 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
617 | struct x86_emulate_ops *ops, | |
618 | unsigned long linear, u8 *dest) | |
619 | { | |
620 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
621 | int rc; | |
622 | int size; | |
623 | ||
624 | if (linear < fc->start || linear >= fc->end) { | |
625 | size = min(15UL, PAGE_SIZE - offset_in_page(linear)); | |
1871c602 | 626 | rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL); |
62266869 AK |
627 | if (rc) |
628 | return rc; | |
629 | fc->start = linear; | |
630 | fc->end = linear + size; | |
631 | } | |
632 | *dest = fc->data[linear - fc->start]; | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
637 | struct x86_emulate_ops *ops, | |
638 | unsigned long eip, void *dest, unsigned size) | |
639 | { | |
640 | int rc = 0; | |
641 | ||
eb3c79e6 AK |
642 | /* x86 instructions are limited to 15 bytes. */ |
643 | if (eip + size - ctxt->decode.eip_orig > 15) | |
644 | return X86EMUL_UNHANDLEABLE; | |
62266869 AK |
645 | eip += ctxt->cs_base; |
646 | while (size--) { | |
647 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
648 | if (rc) | |
649 | return rc; | |
650 | } | |
651 | return 0; | |
652 | } | |
653 | ||
1e3c5cb0 RR |
654 | /* |
655 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
656 | * pointer into the block that addresses the relevant register. | |
657 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
658 | */ | |
659 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
660 | int highbyte_regs) | |
6aa8b732 AK |
661 | { |
662 | void *p; | |
663 | ||
664 | p = ®s[modrm_reg]; | |
665 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
666 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
667 | return p; | |
668 | } | |
669 | ||
670 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
671 | struct x86_emulate_ops *ops, | |
672 | void *ptr, | |
673 | u16 *size, unsigned long *address, int op_bytes) | |
674 | { | |
675 | int rc; | |
676 | ||
677 | if (op_bytes == 2) | |
678 | op_bytes = 3; | |
679 | *address = 0; | |
cebff02b | 680 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
1871c602 | 681 | ctxt->vcpu, NULL); |
6aa8b732 AK |
682 | if (rc) |
683 | return rc; | |
cebff02b | 684 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
1871c602 | 685 | ctxt->vcpu, NULL); |
6aa8b732 AK |
686 | return rc; |
687 | } | |
688 | ||
bbe9abbd NK |
689 | static int test_cc(unsigned int condition, unsigned int flags) |
690 | { | |
691 | int rc = 0; | |
692 | ||
693 | switch ((condition & 15) >> 1) { | |
694 | case 0: /* o */ | |
695 | rc |= (flags & EFLG_OF); | |
696 | break; | |
697 | case 1: /* b/c/nae */ | |
698 | rc |= (flags & EFLG_CF); | |
699 | break; | |
700 | case 2: /* z/e */ | |
701 | rc |= (flags & EFLG_ZF); | |
702 | break; | |
703 | case 3: /* be/na */ | |
704 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
705 | break; | |
706 | case 4: /* s */ | |
707 | rc |= (flags & EFLG_SF); | |
708 | break; | |
709 | case 5: /* p/pe */ | |
710 | rc |= (flags & EFLG_PF); | |
711 | break; | |
712 | case 7: /* le/ng */ | |
713 | rc |= (flags & EFLG_ZF); | |
714 | /* fall through */ | |
715 | case 6: /* l/nge */ | |
716 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
717 | break; | |
718 | } | |
719 | ||
720 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
721 | return (!!rc ^ (condition & 1)); | |
722 | } | |
723 | ||
3c118e24 AK |
724 | static void decode_register_operand(struct operand *op, |
725 | struct decode_cache *c, | |
3c118e24 AK |
726 | int inhibit_bytereg) |
727 | { | |
33615aa9 | 728 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 729 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
730 | |
731 | if (!(c->d & ModRM)) | |
732 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
733 | op->type = OP_REG; |
734 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 735 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
736 | op->val = *(u8 *)op->ptr; |
737 | op->bytes = 1; | |
738 | } else { | |
33615aa9 | 739 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
740 | op->bytes = c->op_bytes; |
741 | switch (op->bytes) { | |
742 | case 2: | |
743 | op->val = *(u16 *)op->ptr; | |
744 | break; | |
745 | case 4: | |
746 | op->val = *(u32 *)op->ptr; | |
747 | break; | |
748 | case 8: | |
749 | op->val = *(u64 *) op->ptr; | |
750 | break; | |
751 | } | |
752 | } | |
753 | op->orig_val = op->val; | |
754 | } | |
755 | ||
1c73ef66 AK |
756 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
757 | struct x86_emulate_ops *ops) | |
758 | { | |
759 | struct decode_cache *c = &ctxt->decode; | |
760 | u8 sib; | |
f5b4edcd | 761 | int index_reg = 0, base_reg = 0, scale; |
1c73ef66 AK |
762 | int rc = 0; |
763 | ||
764 | if (c->rex_prefix) { | |
765 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
766 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
767 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
768 | } | |
769 | ||
770 | c->modrm = insn_fetch(u8, 1, c->eip); | |
771 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
772 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
773 | c->modrm_rm |= (c->modrm & 0x07); | |
774 | c->modrm_ea = 0; | |
775 | c->use_modrm_ea = 1; | |
776 | ||
777 | if (c->modrm_mod == 3) { | |
107d6d2e AK |
778 | c->modrm_ptr = decode_register(c->modrm_rm, |
779 | c->regs, c->d & ByteOp); | |
780 | c->modrm_val = *(unsigned long *)c->modrm_ptr; | |
1c73ef66 AK |
781 | return rc; |
782 | } | |
783 | ||
784 | if (c->ad_bytes == 2) { | |
785 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
786 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
787 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
788 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
789 | ||
790 | /* 16-bit ModR/M decode. */ | |
791 | switch (c->modrm_mod) { | |
792 | case 0: | |
793 | if (c->modrm_rm == 6) | |
794 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
795 | break; | |
796 | case 1: | |
797 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
798 | break; | |
799 | case 2: | |
800 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
801 | break; | |
802 | } | |
803 | switch (c->modrm_rm) { | |
804 | case 0: | |
805 | c->modrm_ea += bx + si; | |
806 | break; | |
807 | case 1: | |
808 | c->modrm_ea += bx + di; | |
809 | break; | |
810 | case 2: | |
811 | c->modrm_ea += bp + si; | |
812 | break; | |
813 | case 3: | |
814 | c->modrm_ea += bp + di; | |
815 | break; | |
816 | case 4: | |
817 | c->modrm_ea += si; | |
818 | break; | |
819 | case 5: | |
820 | c->modrm_ea += di; | |
821 | break; | |
822 | case 6: | |
823 | if (c->modrm_mod != 0) | |
824 | c->modrm_ea += bp; | |
825 | break; | |
826 | case 7: | |
827 | c->modrm_ea += bx; | |
828 | break; | |
829 | } | |
830 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
831 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
7a5b56df AK |
832 | if (!c->has_seg_override) |
833 | set_seg_override(c, VCPU_SREG_SS); | |
1c73ef66 AK |
834 | c->modrm_ea = (u16)c->modrm_ea; |
835 | } else { | |
836 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 837 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
838 | sib = insn_fetch(u8, 1, c->eip); |
839 | index_reg |= (sib >> 3) & 7; | |
840 | base_reg |= sib & 7; | |
841 | scale = sib >> 6; | |
842 | ||
dc71d0f1 AK |
843 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
844 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
845 | else | |
1c73ef66 | 846 | c->modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 847 | if (index_reg != 4) |
1c73ef66 | 848 | c->modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
849 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
850 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 851 | c->rip_relative = 1; |
84411d85 | 852 | } else |
1c73ef66 | 853 | c->modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
854 | switch (c->modrm_mod) { |
855 | case 0: | |
856 | if (c->modrm_rm == 5) | |
857 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
858 | break; | |
859 | case 1: | |
860 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
861 | break; | |
862 | case 2: | |
863 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
864 | break; | |
865 | } | |
866 | } | |
1c73ef66 AK |
867 | done: |
868 | return rc; | |
869 | } | |
870 | ||
871 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
872 | struct x86_emulate_ops *ops) | |
873 | { | |
874 | struct decode_cache *c = &ctxt->decode; | |
875 | int rc = 0; | |
876 | ||
877 | switch (c->ad_bytes) { | |
878 | case 2: | |
879 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
880 | break; | |
881 | case 4: | |
882 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
883 | break; | |
884 | case 8: | |
885 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
886 | break; | |
887 | } | |
888 | done: | |
889 | return rc; | |
890 | } | |
891 | ||
6aa8b732 | 892 | int |
8b4caf66 | 893 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 894 | { |
e4e03ded | 895 | struct decode_cache *c = &ctxt->decode; |
6aa8b732 | 896 | int rc = 0; |
6aa8b732 | 897 | int mode = ctxt->mode; |
e09d082c | 898 | int def_op_bytes, def_ad_bytes, group; |
6aa8b732 AK |
899 | |
900 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 901 | |
e4e03ded | 902 | memset(c, 0, sizeof(struct decode_cache)); |
eb3c79e6 | 903 | c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu); |
7a5b56df | 904 | ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS); |
ad312c7c | 905 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
6aa8b732 AK |
906 | |
907 | switch (mode) { | |
908 | case X86EMUL_MODE_REAL: | |
a0044755 | 909 | case X86EMUL_MODE_VM86: |
6aa8b732 | 910 | case X86EMUL_MODE_PROT16: |
f21b8bf4 | 911 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
912 | break; |
913 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 914 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 915 | break; |
05b3e0c2 | 916 | #ifdef CONFIG_X86_64 |
6aa8b732 | 917 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
918 | def_op_bytes = 4; |
919 | def_ad_bytes = 8; | |
6aa8b732 AK |
920 | break; |
921 | #endif | |
922 | default: | |
923 | return -1; | |
924 | } | |
925 | ||
f21b8bf4 AK |
926 | c->op_bytes = def_op_bytes; |
927 | c->ad_bytes = def_ad_bytes; | |
928 | ||
6aa8b732 | 929 | /* Legacy prefixes. */ |
b4c6abfe | 930 | for (;;) { |
e4e03ded | 931 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 932 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
933 | /* switch between 2/4 bytes */ |
934 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
935 | break; |
936 | case 0x67: /* address-size override */ | |
937 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 938 | /* switch between 4/8 bytes */ |
f21b8bf4 | 939 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 940 | else |
e4e03ded | 941 | /* switch between 2/4 bytes */ |
f21b8bf4 | 942 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 | 943 | break; |
7a5b56df | 944 | case 0x26: /* ES override */ |
6aa8b732 | 945 | case 0x2e: /* CS override */ |
7a5b56df | 946 | case 0x36: /* SS override */ |
6aa8b732 | 947 | case 0x3e: /* DS override */ |
7a5b56df | 948 | set_seg_override(c, (c->b >> 3) & 3); |
6aa8b732 AK |
949 | break; |
950 | case 0x64: /* FS override */ | |
6aa8b732 | 951 | case 0x65: /* GS override */ |
7a5b56df | 952 | set_seg_override(c, c->b & 7); |
6aa8b732 | 953 | break; |
b4c6abfe LV |
954 | case 0x40 ... 0x4f: /* REX */ |
955 | if (mode != X86EMUL_MODE_PROT64) | |
956 | goto done_prefixes; | |
33615aa9 | 957 | c->rex_prefix = c->b; |
b4c6abfe | 958 | continue; |
6aa8b732 | 959 | case 0xf0: /* LOCK */ |
e4e03ded | 960 | c->lock_prefix = 1; |
6aa8b732 | 961 | break; |
ae6200ba | 962 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
963 | c->rep_prefix = REPNE_PREFIX; |
964 | break; | |
6aa8b732 | 965 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 966 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 967 | break; |
6aa8b732 AK |
968 | default: |
969 | goto done_prefixes; | |
970 | } | |
b4c6abfe LV |
971 | |
972 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
973 | ||
33615aa9 | 974 | c->rex_prefix = 0; |
6aa8b732 AK |
975 | } |
976 | ||
977 | done_prefixes: | |
978 | ||
979 | /* REX prefix. */ | |
1c73ef66 | 980 | if (c->rex_prefix) |
33615aa9 | 981 | if (c->rex_prefix & 8) |
e4e03ded | 982 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
983 | |
984 | /* Opcode byte(s). */ | |
e4e03ded LV |
985 | c->d = opcode_table[c->b]; |
986 | if (c->d == 0) { | |
6aa8b732 | 987 | /* Two-byte opcode? */ |
e4e03ded LV |
988 | if (c->b == 0x0f) { |
989 | c->twobyte = 1; | |
990 | c->b = insn_fetch(u8, 1, c->eip); | |
991 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 992 | } |
e09d082c | 993 | } |
6aa8b732 | 994 | |
d8769fed MG |
995 | if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
996 | kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");; | |
997 | return -1; | |
998 | } | |
999 | ||
e09d082c AK |
1000 | if (c->d & Group) { |
1001 | group = c->d & GroupMask; | |
1002 | c->modrm = insn_fetch(u8, 1, c->eip); | |
1003 | --c->eip; | |
1004 | ||
1005 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
1006 | if ((c->d & GroupDual) && (c->modrm >> 6) == 3) | |
1007 | c->d = group2_table[group]; | |
1008 | else | |
1009 | c->d = group_table[group]; | |
1010 | } | |
1011 | ||
1012 | /* Unrecognised? */ | |
1013 | if (c->d == 0) { | |
1014 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1015 | return -1; | |
6aa8b732 AK |
1016 | } |
1017 | ||
6e3d5dfb AK |
1018 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
1019 | c->op_bytes = 8; | |
1020 | ||
6aa8b732 | 1021 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
1022 | if (c->d & ModRM) |
1023 | rc = decode_modrm(ctxt, ops); | |
1024 | else if (c->d & MemAbs) | |
1025 | rc = decode_abs(ctxt, ops); | |
1026 | if (rc) | |
1027 | goto done; | |
6aa8b732 | 1028 | |
7a5b56df AK |
1029 | if (!c->has_seg_override) |
1030 | set_seg_override(c, VCPU_SREG_DS); | |
c7e75a3d | 1031 | |
7a5b56df AK |
1032 | if (!(!c->twobyte && c->b == 0x8d)) |
1033 | c->modrm_ea += seg_override_base(ctxt, c); | |
c7e75a3d AK |
1034 | |
1035 | if (c->ad_bytes != 8) | |
1036 | c->modrm_ea = (u32)c->modrm_ea; | |
6aa8b732 AK |
1037 | /* |
1038 | * Decode and fetch the source operand: register, memory | |
1039 | * or immediate. | |
1040 | */ | |
e4e03ded | 1041 | switch (c->d & SrcMask) { |
6aa8b732 AK |
1042 | case SrcNone: |
1043 | break; | |
1044 | case SrcReg: | |
9f1ef3f8 | 1045 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
1046 | break; |
1047 | case SrcMem16: | |
e4e03ded | 1048 | c->src.bytes = 2; |
6aa8b732 AK |
1049 | goto srcmem_common; |
1050 | case SrcMem32: | |
e4e03ded | 1051 | c->src.bytes = 4; |
6aa8b732 AK |
1052 | goto srcmem_common; |
1053 | case SrcMem: | |
e4e03ded LV |
1054 | c->src.bytes = (c->d & ByteOp) ? 1 : |
1055 | c->op_bytes; | |
b85b9ee9 | 1056 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 1057 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 1058 | break; |
d77c26fc | 1059 | srcmem_common: |
4e62417b AJ |
1060 | /* |
1061 | * For instructions with a ModR/M byte, switch to register | |
1062 | * access if Mod = 3. | |
1063 | */ | |
e4e03ded LV |
1064 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1065 | c->src.type = OP_REG; | |
66b85505 | 1066 | c->src.val = c->modrm_val; |
107d6d2e | 1067 | c->src.ptr = c->modrm_ptr; |
4e62417b AJ |
1068 | break; |
1069 | } | |
e4e03ded | 1070 | c->src.type = OP_MEM; |
6aa8b732 AK |
1071 | break; |
1072 | case SrcImm: | |
c9eaf20f | 1073 | case SrcImmU: |
e4e03ded LV |
1074 | c->src.type = OP_IMM; |
1075 | c->src.ptr = (unsigned long *)c->eip; | |
1076 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1077 | if (c->src.bytes == 8) | |
1078 | c->src.bytes = 4; | |
6aa8b732 | 1079 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1080 | switch (c->src.bytes) { |
6aa8b732 | 1081 | case 1: |
e4e03ded | 1082 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1083 | break; |
1084 | case 2: | |
e4e03ded | 1085 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1086 | break; |
1087 | case 4: | |
e4e03ded | 1088 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1089 | break; |
1090 | } | |
c9eaf20f AK |
1091 | if ((c->d & SrcMask) == SrcImmU) { |
1092 | switch (c->src.bytes) { | |
1093 | case 1: | |
1094 | c->src.val &= 0xff; | |
1095 | break; | |
1096 | case 2: | |
1097 | c->src.val &= 0xffff; | |
1098 | break; | |
1099 | case 4: | |
1100 | c->src.val &= 0xffffffff; | |
1101 | break; | |
1102 | } | |
1103 | } | |
6aa8b732 AK |
1104 | break; |
1105 | case SrcImmByte: | |
341de7e3 | 1106 | case SrcImmUByte: |
e4e03ded LV |
1107 | c->src.type = OP_IMM; |
1108 | c->src.ptr = (unsigned long *)c->eip; | |
1109 | c->src.bytes = 1; | |
341de7e3 GN |
1110 | if ((c->d & SrcMask) == SrcImmByte) |
1111 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1112 | else | |
1113 | c->src.val = insn_fetch(u8, 1, c->eip); | |
6aa8b732 | 1114 | break; |
bfcadf83 GT |
1115 | case SrcOne: |
1116 | c->src.bytes = 1; | |
1117 | c->src.val = 1; | |
1118 | break; | |
6aa8b732 AK |
1119 | } |
1120 | ||
0dc8d10f GT |
1121 | /* |
1122 | * Decode and fetch the second source operand: register, memory | |
1123 | * or immediate. | |
1124 | */ | |
1125 | switch (c->d & Src2Mask) { | |
1126 | case Src2None: | |
1127 | break; | |
1128 | case Src2CL: | |
1129 | c->src2.bytes = 1; | |
1130 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
1131 | break; | |
1132 | case Src2ImmByte: | |
1133 | c->src2.type = OP_IMM; | |
1134 | c->src2.ptr = (unsigned long *)c->eip; | |
1135 | c->src2.bytes = 1; | |
1136 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
1137 | break; | |
a5f868bd GN |
1138 | case Src2Imm16: |
1139 | c->src2.type = OP_IMM; | |
1140 | c->src2.ptr = (unsigned long *)c->eip; | |
1141 | c->src2.bytes = 2; | |
1142 | c->src2.val = insn_fetch(u16, 2, c->eip); | |
1143 | break; | |
0dc8d10f GT |
1144 | case Src2One: |
1145 | c->src2.bytes = 1; | |
1146 | c->src2.val = 1; | |
1147 | break; | |
1148 | } | |
1149 | ||
038e51de | 1150 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1151 | switch (c->d & DstMask) { |
038e51de AK |
1152 | case ImplicitOps: |
1153 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1154 | return 0; |
038e51de | 1155 | case DstReg: |
9f1ef3f8 | 1156 | decode_register_operand(&c->dst, c, |
3c118e24 | 1157 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1158 | break; |
1159 | case DstMem: | |
e4e03ded | 1160 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
89c69638 | 1161 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
e4e03ded | 1162 | c->dst.type = OP_REG; |
66b85505 | 1163 | c->dst.val = c->dst.orig_val = c->modrm_val; |
107d6d2e | 1164 | c->dst.ptr = c->modrm_ptr; |
4e62417b AJ |
1165 | break; |
1166 | } | |
8b4caf66 LV |
1167 | c->dst.type = OP_MEM; |
1168 | break; | |
9c9fddd0 GT |
1169 | case DstAcc: |
1170 | c->dst.type = OP_REG; | |
1171 | c->dst.bytes = c->op_bytes; | |
1172 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1173 | switch (c->op_bytes) { | |
1174 | case 1: | |
1175 | c->dst.val = *(u8 *)c->dst.ptr; | |
1176 | break; | |
1177 | case 2: | |
1178 | c->dst.val = *(u16 *)c->dst.ptr; | |
1179 | break; | |
1180 | case 4: | |
1181 | c->dst.val = *(u32 *)c->dst.ptr; | |
1182 | break; | |
1183 | } | |
1184 | c->dst.orig_val = c->dst.val; | |
1185 | break; | |
8b4caf66 LV |
1186 | } |
1187 | ||
f5b4edcd AK |
1188 | if (c->rip_relative) |
1189 | c->modrm_ea += c->eip; | |
1190 | ||
8b4caf66 LV |
1191 | done: |
1192 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1193 | } | |
1194 | ||
8cdbd2c9 LV |
1195 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
1196 | { | |
1197 | struct decode_cache *c = &ctxt->decode; | |
1198 | ||
1199 | c->dst.type = OP_MEM; | |
1200 | c->dst.bytes = c->op_bytes; | |
1201 | c->dst.val = c->src.val; | |
7a957275 | 1202 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
7a5b56df | 1203 | c->dst.ptr = (void *) register_address(c, ss_base(ctxt), |
8cdbd2c9 LV |
1204 | c->regs[VCPU_REGS_RSP]); |
1205 | } | |
1206 | ||
faa5a3ae | 1207 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
350f69dc AK |
1208 | struct x86_emulate_ops *ops, |
1209 | void *dest, int len) | |
8cdbd2c9 LV |
1210 | { |
1211 | struct decode_cache *c = &ctxt->decode; | |
1212 | int rc; | |
1213 | ||
781d0edc AK |
1214 | rc = ops->read_emulated(register_address(c, ss_base(ctxt), |
1215 | c->regs[VCPU_REGS_RSP]), | |
350f69dc | 1216 | dest, len, ctxt->vcpu); |
b60d513c | 1217 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1218 | return rc; |
1219 | ||
350f69dc | 1220 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); |
faa5a3ae AK |
1221 | return rc; |
1222 | } | |
8cdbd2c9 | 1223 | |
d4c6a154 GN |
1224 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1225 | struct x86_emulate_ops *ops, | |
1226 | void *dest, int len) | |
1227 | { | |
1228 | int rc; | |
1229 | unsigned long val, change_mask; | |
1230 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1231 | int cpl = kvm_x86_ops->get_cpl(ctxt->vcpu); | |
1232 | ||
1233 | rc = emulate_pop(ctxt, ops, &val, len); | |
1234 | if (rc != X86EMUL_CONTINUE) | |
1235 | return rc; | |
1236 | ||
1237 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF | |
1238 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
1239 | ||
1240 | switch(ctxt->mode) { | |
1241 | case X86EMUL_MODE_PROT64: | |
1242 | case X86EMUL_MODE_PROT32: | |
1243 | case X86EMUL_MODE_PROT16: | |
1244 | if (cpl == 0) | |
1245 | change_mask |= EFLG_IOPL; | |
1246 | if (cpl <= iopl) | |
1247 | change_mask |= EFLG_IF; | |
1248 | break; | |
1249 | case X86EMUL_MODE_VM86: | |
1250 | if (iopl < 3) { | |
1251 | kvm_inject_gp(ctxt->vcpu, 0); | |
1252 | return X86EMUL_PROPAGATE_FAULT; | |
1253 | } | |
1254 | change_mask |= EFLG_IF; | |
1255 | break; | |
1256 | default: /* real mode */ | |
1257 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1258 | break; | |
1259 | } | |
1260 | ||
1261 | *(unsigned long *)dest = | |
1262 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1263 | ||
1264 | return rc; | |
1265 | } | |
1266 | ||
0934ac9d MG |
1267 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg) |
1268 | { | |
1269 | struct decode_cache *c = &ctxt->decode; | |
1270 | struct kvm_segment segment; | |
1271 | ||
1272 | kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg); | |
1273 | ||
1274 | c->src.val = segment.selector; | |
1275 | emulate_push(ctxt); | |
1276 | } | |
1277 | ||
1278 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, | |
1279 | struct x86_emulate_ops *ops, int seg) | |
1280 | { | |
1281 | struct decode_cache *c = &ctxt->decode; | |
1282 | unsigned long selector; | |
1283 | int rc; | |
1284 | ||
1285 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); | |
1286 | if (rc != 0) | |
1287 | return rc; | |
1288 | ||
1289 | rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg); | |
1290 | return rc; | |
1291 | } | |
1292 | ||
abcf14b5 MG |
1293 | static void emulate_pusha(struct x86_emulate_ctxt *ctxt) |
1294 | { | |
1295 | struct decode_cache *c = &ctxt->decode; | |
1296 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1297 | int reg = VCPU_REGS_RAX; | |
1298 | ||
1299 | while (reg <= VCPU_REGS_RDI) { | |
1300 | (reg == VCPU_REGS_RSP) ? | |
1301 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
1302 | ||
1303 | emulate_push(ctxt); | |
1304 | ++reg; | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, | |
1309 | struct x86_emulate_ops *ops) | |
1310 | { | |
1311 | struct decode_cache *c = &ctxt->decode; | |
1312 | int rc = 0; | |
1313 | int reg = VCPU_REGS_RDI; | |
1314 | ||
1315 | while (reg >= VCPU_REGS_RAX) { | |
1316 | if (reg == VCPU_REGS_RSP) { | |
1317 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1318 | c->op_bytes); | |
1319 | --reg; | |
1320 | } | |
1321 | ||
1322 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); | |
1323 | if (rc != 0) | |
1324 | break; | |
1325 | --reg; | |
1326 | } | |
1327 | return rc; | |
1328 | } | |
1329 | ||
faa5a3ae AK |
1330 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
1331 | struct x86_emulate_ops *ops) | |
1332 | { | |
1333 | struct decode_cache *c = &ctxt->decode; | |
1334 | int rc; | |
1335 | ||
350f69dc | 1336 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
faa5a3ae AK |
1337 | if (rc != 0) |
1338 | return rc; | |
8cdbd2c9 LV |
1339 | return 0; |
1340 | } | |
1341 | ||
05f086f8 | 1342 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1343 | { |
05f086f8 | 1344 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1345 | switch (c->modrm_reg) { |
1346 | case 0: /* rol */ | |
05f086f8 | 1347 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1348 | break; |
1349 | case 1: /* ror */ | |
05f086f8 | 1350 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1351 | break; |
1352 | case 2: /* rcl */ | |
05f086f8 | 1353 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1354 | break; |
1355 | case 3: /* rcr */ | |
05f086f8 | 1356 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1357 | break; |
1358 | case 4: /* sal/shl */ | |
1359 | case 6: /* sal/shl */ | |
05f086f8 | 1360 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1361 | break; |
1362 | case 5: /* shr */ | |
05f086f8 | 1363 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1364 | break; |
1365 | case 7: /* sar */ | |
05f086f8 | 1366 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1367 | break; |
1368 | } | |
1369 | } | |
1370 | ||
1371 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1372 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1373 | { |
1374 | struct decode_cache *c = &ctxt->decode; | |
1375 | int rc = 0; | |
1376 | ||
1377 | switch (c->modrm_reg) { | |
1378 | case 0 ... 1: /* test */ | |
05f086f8 | 1379 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1380 | break; |
1381 | case 2: /* not */ | |
1382 | c->dst.val = ~c->dst.val; | |
1383 | break; | |
1384 | case 3: /* neg */ | |
05f086f8 | 1385 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1386 | break; |
1387 | default: | |
1388 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1389 | rc = X86EMUL_UNHANDLEABLE; | |
1390 | break; | |
1391 | } | |
8cdbd2c9 LV |
1392 | return rc; |
1393 | } | |
1394 | ||
1395 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1396 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1397 | { |
1398 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1399 | |
1400 | switch (c->modrm_reg) { | |
1401 | case 0: /* inc */ | |
05f086f8 | 1402 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1403 | break; |
1404 | case 1: /* dec */ | |
05f086f8 | 1405 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1406 | break; |
d19292e4 MG |
1407 | case 2: /* call near abs */ { |
1408 | long int old_eip; | |
1409 | old_eip = c->eip; | |
1410 | c->eip = c->src.val; | |
1411 | c->src.val = old_eip; | |
1412 | emulate_push(ctxt); | |
1413 | break; | |
1414 | } | |
8cdbd2c9 | 1415 | case 4: /* jmp abs */ |
fd60754e | 1416 | c->eip = c->src.val; |
8cdbd2c9 LV |
1417 | break; |
1418 | case 6: /* push */ | |
fd60754e | 1419 | emulate_push(ctxt); |
8cdbd2c9 | 1420 | break; |
8cdbd2c9 LV |
1421 | } |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
1426 | struct x86_emulate_ops *ops, | |
e8d8d7fe | 1427 | unsigned long memop) |
8cdbd2c9 LV |
1428 | { |
1429 | struct decode_cache *c = &ctxt->decode; | |
1430 | u64 old, new; | |
1431 | int rc; | |
1432 | ||
e8d8d7fe | 1433 | rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu); |
b60d513c | 1434 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1435 | return rc; |
1436 | ||
1437 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1438 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1439 | ||
1440 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1441 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1442 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1443 | |
1444 | } else { | |
1445 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1446 | (u32) c->regs[VCPU_REGS_RBX]; | |
1447 | ||
e8d8d7fe | 1448 | rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu); |
b60d513c | 1449 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 1450 | return rc; |
05f086f8 | 1451 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 LV |
1452 | } |
1453 | return 0; | |
1454 | } | |
1455 | ||
a77ab5ea AK |
1456 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1457 | struct x86_emulate_ops *ops) | |
1458 | { | |
1459 | struct decode_cache *c = &ctxt->decode; | |
1460 | int rc; | |
1461 | unsigned long cs; | |
1462 | ||
1463 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1464 | if (rc) | |
1465 | return rc; | |
1466 | if (c->op_bytes == 4) | |
1467 | c->eip = (u32)c->eip; | |
1468 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1469 | if (rc) | |
1470 | return rc; | |
1471 | rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS); | |
1472 | return rc; | |
1473 | } | |
1474 | ||
8cdbd2c9 LV |
1475 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1476 | struct x86_emulate_ops *ops) | |
1477 | { | |
1478 | int rc; | |
1479 | struct decode_cache *c = &ctxt->decode; | |
1480 | ||
1481 | switch (c->dst.type) { | |
1482 | case OP_REG: | |
1483 | /* The 4-byte case *is* correct: | |
1484 | * in 64-bit mode we zero-extend. | |
1485 | */ | |
1486 | switch (c->dst.bytes) { | |
1487 | case 1: | |
1488 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1489 | break; | |
1490 | case 2: | |
1491 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1492 | break; | |
1493 | case 4: | |
1494 | *c->dst.ptr = (u32)c->dst.val; | |
1495 | break; /* 64b: zero-ext */ | |
1496 | case 8: | |
1497 | *c->dst.ptr = c->dst.val; | |
1498 | break; | |
1499 | } | |
1500 | break; | |
1501 | case OP_MEM: | |
1502 | if (c->lock_prefix) | |
1503 | rc = ops->cmpxchg_emulated( | |
1504 | (unsigned long)c->dst.ptr, | |
1505 | &c->dst.orig_val, | |
1506 | &c->dst.val, | |
1507 | c->dst.bytes, | |
1508 | ctxt->vcpu); | |
1509 | else | |
1510 | rc = ops->write_emulated( | |
1511 | (unsigned long)c->dst.ptr, | |
1512 | &c->dst.val, | |
1513 | c->dst.bytes, | |
1514 | ctxt->vcpu); | |
b60d513c | 1515 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 1516 | return rc; |
a01af5ec LV |
1517 | break; |
1518 | case OP_NONE: | |
1519 | /* no writeback */ | |
1520 | break; | |
8cdbd2c9 LV |
1521 | default: |
1522 | break; | |
1523 | } | |
1524 | return 0; | |
1525 | } | |
1526 | ||
a3f9d398 | 1527 | static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) |
310b5d30 GC |
1528 | { |
1529 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); | |
1530 | /* | |
1531 | * an sti; sti; sequence only disable interrupts for the first | |
1532 | * instruction. So, if the last instruction, be it emulated or | |
1533 | * not, left the system with the INT_STI flag enabled, it | |
1534 | * means that the last instruction is an sti. We should not | |
1535 | * leave the flag on in this case. The same goes for mov ss | |
1536 | */ | |
1537 | if (!(int_shadow & mask)) | |
1538 | ctxt->interruptibility = mask; | |
1539 | } | |
1540 | ||
e66bb2cc AP |
1541 | static inline void |
1542 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
1543 | struct kvm_segment *cs, struct kvm_segment *ss) | |
1544 | { | |
1545 | memset(cs, 0, sizeof(struct kvm_segment)); | |
1546 | kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS); | |
1547 | memset(ss, 0, sizeof(struct kvm_segment)); | |
1548 | ||
1549 | cs->l = 0; /* will be adjusted later */ | |
1550 | cs->base = 0; /* flat segment */ | |
1551 | cs->g = 1; /* 4kb granularity */ | |
1552 | cs->limit = 0xffffffff; /* 4GB limit */ | |
1553 | cs->type = 0x0b; /* Read, Execute, Accessed */ | |
1554 | cs->s = 1; | |
1555 | cs->dpl = 0; /* will be adjusted later */ | |
1556 | cs->present = 1; | |
1557 | cs->db = 1; | |
1558 | ||
1559 | ss->unusable = 0; | |
1560 | ss->base = 0; /* flat segment */ | |
1561 | ss->limit = 0xffffffff; /* 4GB limit */ | |
1562 | ss->g = 1; /* 4kb granularity */ | |
1563 | ss->s = 1; | |
1564 | ss->type = 0x03; /* Read/Write, Accessed */ | |
1565 | ss->db = 1; /* 32bit stack segment */ | |
1566 | ss->dpl = 0; | |
1567 | ss->present = 1; | |
1568 | } | |
1569 | ||
1570 | static int | |
1571 | emulate_syscall(struct x86_emulate_ctxt *ctxt) | |
1572 | { | |
1573 | struct decode_cache *c = &ctxt->decode; | |
1574 | struct kvm_segment cs, ss; | |
1575 | u64 msr_data; | |
1576 | ||
1577 | /* syscall is not available in real mode */ | |
1578 | if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL | |
a0044755 | 1579 | || ctxt->mode == X86EMUL_MODE_VM86) |
e66bb2cc AP |
1580 | return -1; |
1581 | ||
1582 | setup_syscalls_segments(ctxt, &cs, &ss); | |
1583 | ||
1584 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); | |
1585 | msr_data >>= 32; | |
1586 | cs.selector = (u16)(msr_data & 0xfffc); | |
1587 | ss.selector = (u16)(msr_data + 8); | |
1588 | ||
1589 | if (is_long_mode(ctxt->vcpu)) { | |
1590 | cs.db = 0; | |
1591 | cs.l = 1; | |
1592 | } | |
1593 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1594 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1595 | ||
1596 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1597 | if (is_long_mode(ctxt->vcpu)) { | |
1598 | #ifdef CONFIG_X86_64 | |
1599 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1600 | ||
1601 | kvm_x86_ops->get_msr(ctxt->vcpu, | |
1602 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1603 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
1604 | c->eip = msr_data; | |
1605 | ||
1606 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); | |
1607 | ctxt->eflags &= ~(msr_data | EFLG_RF); | |
1608 | #endif | |
1609 | } else { | |
1610 | /* legacy mode */ | |
1611 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); | |
1612 | c->eip = (u32)msr_data; | |
1613 | ||
1614 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1615 | } | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
8c604352 AP |
1620 | static int |
1621 | emulate_sysenter(struct x86_emulate_ctxt *ctxt) | |
1622 | { | |
1623 | struct decode_cache *c = &ctxt->decode; | |
1624 | struct kvm_segment cs, ss; | |
1625 | u64 msr_data; | |
1626 | ||
1627 | /* inject #UD if LOCK prefix is used */ | |
1628 | if (c->lock_prefix) | |
1629 | return -1; | |
1630 | ||
a0044755 GN |
1631 | /* inject #GP if in real mode */ |
1632 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
8c604352 AP |
1633 | kvm_inject_gp(ctxt->vcpu, 0); |
1634 | return -1; | |
1635 | } | |
1636 | ||
1637 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1638 | * Therefore, we inject an #UD. | |
1639 | */ | |
1640 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
1641 | return -1; | |
1642 | ||
1643 | setup_syscalls_segments(ctxt, &cs, &ss); | |
1644 | ||
1645 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); | |
1646 | switch (ctxt->mode) { | |
1647 | case X86EMUL_MODE_PROT32: | |
1648 | if ((msr_data & 0xfffc) == 0x0) { | |
1649 | kvm_inject_gp(ctxt->vcpu, 0); | |
1650 | return -1; | |
1651 | } | |
1652 | break; | |
1653 | case X86EMUL_MODE_PROT64: | |
1654 | if (msr_data == 0x0) { | |
1655 | kvm_inject_gp(ctxt->vcpu, 0); | |
1656 | return -1; | |
1657 | } | |
1658 | break; | |
1659 | } | |
1660 | ||
1661 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1662 | cs.selector = (u16)msr_data; | |
1663 | cs.selector &= ~SELECTOR_RPL_MASK; | |
1664 | ss.selector = cs.selector + 8; | |
1665 | ss.selector &= ~SELECTOR_RPL_MASK; | |
1666 | if (ctxt->mode == X86EMUL_MODE_PROT64 | |
1667 | || is_long_mode(ctxt->vcpu)) { | |
1668 | cs.db = 0; | |
1669 | cs.l = 1; | |
1670 | } | |
1671 | ||
1672 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1673 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1674 | ||
1675 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); | |
1676 | c->eip = msr_data; | |
1677 | ||
1678 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); | |
1679 | c->regs[VCPU_REGS_RSP] = msr_data; | |
1680 | ||
1681 | return 0; | |
1682 | } | |
1683 | ||
4668f050 AP |
1684 | static int |
1685 | emulate_sysexit(struct x86_emulate_ctxt *ctxt) | |
1686 | { | |
1687 | struct decode_cache *c = &ctxt->decode; | |
1688 | struct kvm_segment cs, ss; | |
1689 | u64 msr_data; | |
1690 | int usermode; | |
1691 | ||
1692 | /* inject #UD if LOCK prefix is used */ | |
1693 | if (c->lock_prefix) | |
1694 | return -1; | |
1695 | ||
a0044755 GN |
1696 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1697 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
1698 | ctxt->mode == X86EMUL_MODE_VM86) { | |
4668f050 AP |
1699 | kvm_inject_gp(ctxt->vcpu, 0); |
1700 | return -1; | |
1701 | } | |
1702 | ||
1703 | /* sysexit must be called from CPL 0 */ | |
1704 | if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) { | |
1705 | kvm_inject_gp(ctxt->vcpu, 0); | |
1706 | return -1; | |
1707 | } | |
1708 | ||
1709 | setup_syscalls_segments(ctxt, &cs, &ss); | |
1710 | ||
1711 | if ((c->rex_prefix & 0x8) != 0x0) | |
1712 | usermode = X86EMUL_MODE_PROT64; | |
1713 | else | |
1714 | usermode = X86EMUL_MODE_PROT32; | |
1715 | ||
1716 | cs.dpl = 3; | |
1717 | ss.dpl = 3; | |
1718 | kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); | |
1719 | switch (usermode) { | |
1720 | case X86EMUL_MODE_PROT32: | |
1721 | cs.selector = (u16)(msr_data + 16); | |
1722 | if ((msr_data & 0xfffc) == 0x0) { | |
1723 | kvm_inject_gp(ctxt->vcpu, 0); | |
1724 | return -1; | |
1725 | } | |
1726 | ss.selector = (u16)(msr_data + 24); | |
1727 | break; | |
1728 | case X86EMUL_MODE_PROT64: | |
1729 | cs.selector = (u16)(msr_data + 32); | |
1730 | if (msr_data == 0x0) { | |
1731 | kvm_inject_gp(ctxt->vcpu, 0); | |
1732 | return -1; | |
1733 | } | |
1734 | ss.selector = cs.selector + 8; | |
1735 | cs.db = 0; | |
1736 | cs.l = 1; | |
1737 | break; | |
1738 | } | |
1739 | cs.selector |= SELECTOR_RPL_MASK; | |
1740 | ss.selector |= SELECTOR_RPL_MASK; | |
1741 | ||
1742 | kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); | |
1743 | kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); | |
1744 | ||
1745 | c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX]; | |
1746 | c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX]; | |
1747 | ||
1748 | return 0; | |
1749 | } | |
1750 | ||
f850e2e6 GN |
1751 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
1752 | { | |
1753 | int iopl; | |
1754 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1755 | return false; | |
1756 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1757 | return true; | |
1758 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1759 | return kvm_x86_ops->get_cpl(ctxt->vcpu) > iopl; | |
1760 | } | |
1761 | ||
1762 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1763 | struct x86_emulate_ops *ops, | |
1764 | u16 port, u16 len) | |
1765 | { | |
1766 | struct kvm_segment tr_seg; | |
1767 | int r; | |
1768 | u16 io_bitmap_ptr; | |
1769 | u8 perm, bit_idx = port & 0x7; | |
1770 | unsigned mask = (1 << len) - 1; | |
1771 | ||
1772 | kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR); | |
1773 | if (tr_seg.unusable) | |
1774 | return false; | |
1775 | if (tr_seg.limit < 103) | |
1776 | return false; | |
1777 | r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, | |
1778 | NULL); | |
1779 | if (r != X86EMUL_CONTINUE) | |
1780 | return false; | |
1781 | if (io_bitmap_ptr + port/8 > tr_seg.limit) | |
1782 | return false; | |
1783 | r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1, | |
1784 | ctxt->vcpu, NULL); | |
1785 | if (r != X86EMUL_CONTINUE) | |
1786 | return false; | |
1787 | if ((perm >> bit_idx) & mask) | |
1788 | return false; | |
1789 | return true; | |
1790 | } | |
1791 | ||
1792 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1793 | struct x86_emulate_ops *ops, | |
1794 | u16 port, u16 len) | |
1795 | { | |
1796 | if (emulator_bad_iopl(ctxt)) | |
1797 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) | |
1798 | return false; | |
1799 | return true; | |
1800 | } | |
1801 | ||
8b4caf66 | 1802 | int |
1be3aa47 | 1803 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 1804 | { |
e8d8d7fe | 1805 | unsigned long memop = 0; |
8b4caf66 | 1806 | u64 msr_data; |
3427318f | 1807 | unsigned long saved_eip = 0; |
8b4caf66 | 1808 | struct decode_cache *c = &ctxt->decode; |
a6a3034c MG |
1809 | unsigned int port; |
1810 | int io_dir_in; | |
1be3aa47 | 1811 | int rc = 0; |
8b4caf66 | 1812 | |
310b5d30 GC |
1813 | ctxt->interruptibility = 0; |
1814 | ||
3427318f LV |
1815 | /* Shadow copy of register state. Committed on successful emulation. |
1816 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
1817 | * modify them. | |
1818 | */ | |
1819 | ||
ad312c7c | 1820 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
3427318f LV |
1821 | saved_eip = c->eip; |
1822 | ||
c7e75a3d | 1823 | if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) |
e8d8d7fe | 1824 | memop = c->modrm_ea; |
8b4caf66 | 1825 | |
b9fa9d6b AK |
1826 | if (c->rep_prefix && (c->d & String)) { |
1827 | /* All REP prefixes have the same first termination condition */ | |
1828 | if (c->regs[VCPU_REGS_RCX] == 0) { | |
5fdbf976 | 1829 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
1830 | goto done; |
1831 | } | |
1832 | /* The second termination condition only applies for REPE | |
1833 | * and REPNE. Test if the repeat string operation prefix is | |
1834 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
1835 | * corresponding termination condition according to: | |
1836 | * - if REPE/REPZ and ZF = 0 then done | |
1837 | * - if REPNE/REPNZ and ZF = 1 then done | |
1838 | */ | |
1839 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
1840 | (c->b == 0xae) || (c->b == 0xaf)) { | |
1841 | if ((c->rep_prefix == REPE_PREFIX) && | |
1842 | ((ctxt->eflags & EFLG_ZF) == 0)) { | |
5fdbf976 | 1843 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
1844 | goto done; |
1845 | } | |
1846 | if ((c->rep_prefix == REPNE_PREFIX) && | |
1847 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) { | |
5fdbf976 | 1848 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
1849 | goto done; |
1850 | } | |
1851 | } | |
1852 | c->regs[VCPU_REGS_RCX]--; | |
5fdbf976 | 1853 | c->eip = kvm_rip_read(ctxt->vcpu); |
b9fa9d6b AK |
1854 | } |
1855 | ||
8b4caf66 | 1856 | if (c->src.type == OP_MEM) { |
e8d8d7fe | 1857 | c->src.ptr = (unsigned long *)memop; |
8b4caf66 | 1858 | c->src.val = 0; |
d77c26fc MD |
1859 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
1860 | &c->src.val, | |
1861 | c->src.bytes, | |
1862 | ctxt->vcpu); | |
b60d513c | 1863 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 LV |
1864 | goto done; |
1865 | c->src.orig_val = c->src.val; | |
1866 | } | |
1867 | ||
1868 | if ((c->d & DstMask) == ImplicitOps) | |
1869 | goto special_insn; | |
1870 | ||
1871 | ||
1872 | if (c->dst.type == OP_MEM) { | |
e8d8d7fe | 1873 | c->dst.ptr = (unsigned long *)memop; |
8b4caf66 LV |
1874 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
1875 | c->dst.val = 0; | |
e4e03ded LV |
1876 | if (c->d & BitOp) { |
1877 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
df513e2c | 1878 | |
e4e03ded LV |
1879 | c->dst.ptr = (void *)c->dst.ptr + |
1880 | (c->src.val & mask) / 8; | |
038e51de | 1881 | } |
b60d513c TY |
1882 | if (!(c->d & Mov)) { |
1883 | /* optimisation - avoid slow emulated read */ | |
1884 | rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1885 | &c->dst.val, | |
1886 | c->dst.bytes, | |
1887 | ctxt->vcpu); | |
1888 | if (rc != X86EMUL_CONTINUE) | |
1889 | goto done; | |
1890 | } | |
038e51de | 1891 | } |
e4e03ded | 1892 | c->dst.orig_val = c->dst.val; |
038e51de | 1893 | |
018a98db AK |
1894 | special_insn: |
1895 | ||
e4e03ded | 1896 | if (c->twobyte) |
6aa8b732 AK |
1897 | goto twobyte_insn; |
1898 | ||
e4e03ded | 1899 | switch (c->b) { |
6aa8b732 AK |
1900 | case 0x00 ... 0x05: |
1901 | add: /* add */ | |
05f086f8 | 1902 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1903 | break; |
0934ac9d | 1904 | case 0x06: /* push es */ |
0934ac9d MG |
1905 | emulate_push_sreg(ctxt, VCPU_SREG_ES); |
1906 | break; | |
1907 | case 0x07: /* pop es */ | |
0934ac9d MG |
1908 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1909 | if (rc != 0) | |
1910 | goto done; | |
1911 | break; | |
6aa8b732 AK |
1912 | case 0x08 ... 0x0d: |
1913 | or: /* or */ | |
05f086f8 | 1914 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1915 | break; |
0934ac9d | 1916 | case 0x0e: /* push cs */ |
0934ac9d MG |
1917 | emulate_push_sreg(ctxt, VCPU_SREG_CS); |
1918 | break; | |
6aa8b732 AK |
1919 | case 0x10 ... 0x15: |
1920 | adc: /* adc */ | |
05f086f8 | 1921 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1922 | break; |
0934ac9d | 1923 | case 0x16: /* push ss */ |
0934ac9d MG |
1924 | emulate_push_sreg(ctxt, VCPU_SREG_SS); |
1925 | break; | |
1926 | case 0x17: /* pop ss */ | |
0934ac9d MG |
1927 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1928 | if (rc != 0) | |
1929 | goto done; | |
1930 | break; | |
6aa8b732 AK |
1931 | case 0x18 ... 0x1d: |
1932 | sbb: /* sbb */ | |
05f086f8 | 1933 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1934 | break; |
0934ac9d | 1935 | case 0x1e: /* push ds */ |
0934ac9d MG |
1936 | emulate_push_sreg(ctxt, VCPU_SREG_DS); |
1937 | break; | |
1938 | case 0x1f: /* pop ds */ | |
0934ac9d MG |
1939 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1940 | if (rc != 0) | |
1941 | goto done; | |
1942 | break; | |
aa3a816b | 1943 | case 0x20 ... 0x25: |
6aa8b732 | 1944 | and: /* and */ |
05f086f8 | 1945 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1946 | break; |
1947 | case 0x28 ... 0x2d: | |
1948 | sub: /* sub */ | |
05f086f8 | 1949 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1950 | break; |
1951 | case 0x30 ... 0x35: | |
1952 | xor: /* xor */ | |
05f086f8 | 1953 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1954 | break; |
1955 | case 0x38 ... 0x3d: | |
1956 | cmp: /* cmp */ | |
05f086f8 | 1957 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1958 | break; |
33615aa9 AK |
1959 | case 0x40 ... 0x47: /* inc r16/r32 */ |
1960 | emulate_1op("inc", c->dst, ctxt->eflags); | |
1961 | break; | |
1962 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
1963 | emulate_1op("dec", c->dst, ctxt->eflags); | |
1964 | break; | |
1965 | case 0x50 ... 0x57: /* push reg */ | |
2786b014 | 1966 | emulate_push(ctxt); |
33615aa9 AK |
1967 | break; |
1968 | case 0x58 ... 0x5f: /* pop reg */ | |
1969 | pop_instruction: | |
350f69dc | 1970 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
8a09b687 | 1971 | if (rc != 0) |
33615aa9 | 1972 | goto done; |
33615aa9 | 1973 | break; |
abcf14b5 MG |
1974 | case 0x60: /* pusha */ |
1975 | emulate_pusha(ctxt); | |
1976 | break; | |
1977 | case 0x61: /* popa */ | |
1978 | rc = emulate_popa(ctxt, ops); | |
1979 | if (rc != 0) | |
1980 | goto done; | |
1981 | break; | |
6aa8b732 | 1982 | case 0x63: /* movsxd */ |
8b4caf66 | 1983 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 1984 | goto cannot_emulate; |
e4e03ded | 1985 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 1986 | break; |
91ed7a0e | 1987 | case 0x68: /* push imm */ |
018a98db | 1988 | case 0x6a: /* push imm8 */ |
018a98db AK |
1989 | emulate_push(ctxt); |
1990 | break; | |
1991 | case 0x6c: /* insb */ | |
1992 | case 0x6d: /* insw/insd */ | |
f850e2e6 GN |
1993 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
1994 | (c->d & ByteOp) ? 1 : c->op_bytes)) { | |
1995 | kvm_inject_gp(ctxt->vcpu, 0); | |
1996 | goto done; | |
1997 | } | |
1998 | if (kvm_emulate_pio_string(ctxt->vcpu, | |
018a98db AK |
1999 | 1, |
2000 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
2001 | c->rep_prefix ? | |
e4706772 | 2002 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 2003 | (ctxt->eflags & EFLG_DF), |
7a5b56df | 2004 | register_address(c, es_base(ctxt), |
018a98db AK |
2005 | c->regs[VCPU_REGS_RDI]), |
2006 | c->rep_prefix, | |
2007 | c->regs[VCPU_REGS_RDX]) == 0) { | |
2008 | c->eip = saved_eip; | |
2009 | return -1; | |
2010 | } | |
2011 | return 0; | |
2012 | case 0x6e: /* outsb */ | |
2013 | case 0x6f: /* outsw/outsd */ | |
f850e2e6 GN |
2014 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
2015 | (c->d & ByteOp) ? 1 : c->op_bytes)) { | |
2016 | kvm_inject_gp(ctxt->vcpu, 0); | |
2017 | goto done; | |
2018 | } | |
851ba692 | 2019 | if (kvm_emulate_pio_string(ctxt->vcpu, |
018a98db AK |
2020 | 0, |
2021 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
2022 | c->rep_prefix ? | |
e4706772 | 2023 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 2024 | (ctxt->eflags & EFLG_DF), |
7a5b56df AK |
2025 | register_address(c, |
2026 | seg_override_base(ctxt, c), | |
018a98db AK |
2027 | c->regs[VCPU_REGS_RSI]), |
2028 | c->rep_prefix, | |
2029 | c->regs[VCPU_REGS_RDX]) == 0) { | |
2030 | c->eip = saved_eip; | |
2031 | return -1; | |
2032 | } | |
2033 | return 0; | |
b2833e3c | 2034 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2035 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2036 | jmp_rel(c, c->src.val); |
018a98db | 2037 | break; |
6aa8b732 | 2038 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2039 | switch (c->modrm_reg) { |
6aa8b732 AK |
2040 | case 0: |
2041 | goto add; | |
2042 | case 1: | |
2043 | goto or; | |
2044 | case 2: | |
2045 | goto adc; | |
2046 | case 3: | |
2047 | goto sbb; | |
2048 | case 4: | |
2049 | goto and; | |
2050 | case 5: | |
2051 | goto sub; | |
2052 | case 6: | |
2053 | goto xor; | |
2054 | case 7: | |
2055 | goto cmp; | |
2056 | } | |
2057 | break; | |
2058 | case 0x84 ... 0x85: | |
05f086f8 | 2059 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2060 | break; |
2061 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2062 | xchg: |
6aa8b732 | 2063 | /* Write back the register source. */ |
e4e03ded | 2064 | switch (c->dst.bytes) { |
6aa8b732 | 2065 | case 1: |
e4e03ded | 2066 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
2067 | break; |
2068 | case 2: | |
e4e03ded | 2069 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
2070 | break; |
2071 | case 4: | |
e4e03ded | 2072 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
2073 | break; /* 64b reg: zero-extend */ |
2074 | case 8: | |
e4e03ded | 2075 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
2076 | break; |
2077 | } | |
2078 | /* | |
2079 | * Write back the memory destination with implicit LOCK | |
2080 | * prefix. | |
2081 | */ | |
e4e03ded LV |
2082 | c->dst.val = c->src.val; |
2083 | c->lock_prefix = 1; | |
6aa8b732 | 2084 | break; |
6aa8b732 | 2085 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2086 | goto mov; |
38d5bc6d GT |
2087 | case 0x8c: { /* mov r/m, sreg */ |
2088 | struct kvm_segment segreg; | |
2089 | ||
2090 | if (c->modrm_reg <= 5) | |
2091 | kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg); | |
2092 | else { | |
2093 | printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n", | |
2094 | c->modrm); | |
2095 | goto cannot_emulate; | |
2096 | } | |
2097 | c->dst.val = segreg.selector; | |
2098 | break; | |
2099 | } | |
7e0b54b1 | 2100 | case 0x8d: /* lea r16/r32, m */ |
f9b7aab3 | 2101 | c->dst.val = c->modrm_ea; |
7e0b54b1 | 2102 | break; |
4257198a GT |
2103 | case 0x8e: { /* mov seg, r/m16 */ |
2104 | uint16_t sel; | |
2105 | int type_bits; | |
2106 | int err; | |
2107 | ||
2108 | sel = c->src.val; | |
310b5d30 GC |
2109 | if (c->modrm_reg == VCPU_SREG_SS) |
2110 | toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS); | |
2111 | ||
4257198a GT |
2112 | if (c->modrm_reg <= 5) { |
2113 | type_bits = (c->modrm_reg == 1) ? 9 : 1; | |
2114 | err = kvm_load_segment_descriptor(ctxt->vcpu, sel, | |
2115 | type_bits, c->modrm_reg); | |
2116 | } else { | |
2117 | printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n", | |
2118 | c->modrm); | |
2119 | goto cannot_emulate; | |
2120 | } | |
2121 | ||
2122 | if (err < 0) | |
2123 | goto cannot_emulate; | |
2124 | ||
2125 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2126 | break; | |
2127 | } | |
6aa8b732 | 2128 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 LV |
2129 | rc = emulate_grp1a(ctxt, ops); |
2130 | if (rc != 0) | |
6aa8b732 | 2131 | goto done; |
6aa8b732 | 2132 | break; |
b13354f8 MG |
2133 | case 0x90: /* nop / xchg r8,rax */ |
2134 | if (!(c->rex_prefix & 1)) { /* nop */ | |
2135 | c->dst.type = OP_NONE; | |
2136 | break; | |
2137 | } | |
2138 | case 0x91 ... 0x97: /* xchg reg,rax */ | |
2139 | c->src.type = c->dst.type = OP_REG; | |
2140 | c->src.bytes = c->dst.bytes = c->op_bytes; | |
2141 | c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX]; | |
2142 | c->src.val = *(c->src.ptr); | |
2143 | goto xchg; | |
fd2a7608 | 2144 | case 0x9c: /* pushf */ |
05f086f8 | 2145 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
2146 | emulate_push(ctxt); |
2147 | break; | |
535eabcf | 2148 | case 0x9d: /* popf */ |
2b48cc75 | 2149 | c->dst.type = OP_REG; |
05f086f8 | 2150 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
2b48cc75 | 2151 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
2152 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
2153 | if (rc != X86EMUL_CONTINUE) | |
2154 | goto done; | |
2155 | break; | |
018a98db AK |
2156 | case 0xa0 ... 0xa1: /* mov */ |
2157 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
2158 | c->dst.val = c->src.val; | |
2159 | break; | |
2160 | case 0xa2 ... 0xa3: /* mov */ | |
2161 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; | |
2162 | break; | |
6aa8b732 | 2163 | case 0xa4 ... 0xa5: /* movs */ |
e4e03ded LV |
2164 | c->dst.type = OP_MEM; |
2165 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 2166 | c->dst.ptr = (unsigned long *)register_address(c, |
7a5b56df | 2167 | es_base(ctxt), |
e4e03ded | 2168 | c->regs[VCPU_REGS_RDI]); |
b60d513c TY |
2169 | rc = ops->read_emulated(register_address(c, |
2170 | seg_override_base(ctxt, c), | |
2171 | c->regs[VCPU_REGS_RSI]), | |
e4e03ded | 2172 | &c->dst.val, |
b60d513c TY |
2173 | c->dst.bytes, ctxt->vcpu); |
2174 | if (rc != X86EMUL_CONTINUE) | |
6aa8b732 | 2175 | goto done; |
7a957275 | 2176 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 2177 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 2178 | : c->dst.bytes); |
7a957275 | 2179 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 2180 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 2181 | : c->dst.bytes); |
6aa8b732 AK |
2182 | break; |
2183 | case 0xa6 ... 0xa7: /* cmps */ | |
d7e5117a GT |
2184 | c->src.type = OP_NONE; /* Disable writeback. */ |
2185 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 2186 | c->src.ptr = (unsigned long *)register_address(c, |
7a5b56df | 2187 | seg_override_base(ctxt, c), |
d7e5117a | 2188 | c->regs[VCPU_REGS_RSI]); |
b60d513c TY |
2189 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
2190 | &c->src.val, | |
2191 | c->src.bytes, | |
2192 | ctxt->vcpu); | |
2193 | if (rc != X86EMUL_CONTINUE) | |
d7e5117a GT |
2194 | goto done; |
2195 | ||
2196 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2197 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 2198 | c->dst.ptr = (unsigned long *)register_address(c, |
7a5b56df | 2199 | es_base(ctxt), |
d7e5117a | 2200 | c->regs[VCPU_REGS_RDI]); |
b60d513c TY |
2201 | rc = ops->read_emulated((unsigned long)c->dst.ptr, |
2202 | &c->dst.val, | |
2203 | c->dst.bytes, | |
2204 | ctxt->vcpu); | |
2205 | if (rc != X86EMUL_CONTINUE) | |
d7e5117a GT |
2206 | goto done; |
2207 | ||
2208 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); | |
2209 | ||
2210 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); | |
2211 | ||
7a957275 | 2212 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
d7e5117a GT |
2213 | (ctxt->eflags & EFLG_DF) ? -c->src.bytes |
2214 | : c->src.bytes); | |
7a957275 | 2215 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
d7e5117a GT |
2216 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
2217 | : c->dst.bytes); | |
2218 | ||
2219 | break; | |
6aa8b732 | 2220 | case 0xaa ... 0xab: /* stos */ |
e4e03ded LV |
2221 | c->dst.type = OP_MEM; |
2222 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 2223 | c->dst.ptr = (unsigned long *)register_address(c, |
7a5b56df | 2224 | es_base(ctxt), |
a7e6c88a | 2225 | c->regs[VCPU_REGS_RDI]); |
e4e03ded | 2226 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
7a957275 | 2227 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 2228 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 2229 | : c->dst.bytes); |
6aa8b732 AK |
2230 | break; |
2231 | case 0xac ... 0xad: /* lods */ | |
e4e03ded LV |
2232 | c->dst.type = OP_REG; |
2233 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2234 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
b60d513c TY |
2235 | rc = ops->read_emulated(register_address(c, |
2236 | seg_override_base(ctxt, c), | |
2237 | c->regs[VCPU_REGS_RSI]), | |
2238 | &c->dst.val, | |
2239 | c->dst.bytes, | |
2240 | ctxt->vcpu); | |
2241 | if (rc != X86EMUL_CONTINUE) | |
6aa8b732 | 2242 | goto done; |
7a957275 | 2243 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 2244 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 2245 | : c->dst.bytes); |
6aa8b732 AK |
2246 | break; |
2247 | case 0xae ... 0xaf: /* scas */ | |
2248 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
2249 | goto cannot_emulate; | |
a5e2e82b | 2250 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 2251 | goto mov; |
018a98db AK |
2252 | case 0xc0 ... 0xc1: |
2253 | emulate_grp2(ctxt); | |
2254 | break; | |
111de5d6 | 2255 | case 0xc3: /* ret */ |
cf5de4f8 | 2256 | c->dst.type = OP_REG; |
111de5d6 | 2257 | c->dst.ptr = &c->eip; |
cf5de4f8 | 2258 | c->dst.bytes = c->op_bytes; |
111de5d6 | 2259 | goto pop_instruction; |
018a98db AK |
2260 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
2261 | mov: | |
2262 | c->dst.val = c->src.val; | |
2263 | break; | |
a77ab5ea AK |
2264 | case 0xcb: /* ret far */ |
2265 | rc = emulate_ret_far(ctxt, ops); | |
2266 | if (rc) | |
2267 | goto done; | |
2268 | break; | |
018a98db AK |
2269 | case 0xd0 ... 0xd1: /* Grp2 */ |
2270 | c->src.val = 1; | |
2271 | emulate_grp2(ctxt); | |
2272 | break; | |
2273 | case 0xd2 ... 0xd3: /* Grp2 */ | |
2274 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
2275 | emulate_grp2(ctxt); | |
2276 | break; | |
a6a3034c MG |
2277 | case 0xe4: /* inb */ |
2278 | case 0xe5: /* in */ | |
84ce66a6 | 2279 | port = c->src.val; |
a6a3034c MG |
2280 | io_dir_in = 1; |
2281 | goto do_io; | |
2282 | case 0xe6: /* outb */ | |
2283 | case 0xe7: /* out */ | |
84ce66a6 | 2284 | port = c->src.val; |
a6a3034c MG |
2285 | io_dir_in = 0; |
2286 | goto do_io; | |
1a52e051 | 2287 | case 0xe8: /* call (near) */ { |
d53c4777 | 2288 | long int rel = c->src.val; |
e4e03ded | 2289 | c->src.val = (unsigned long) c->eip; |
7a957275 | 2290 | jmp_rel(c, rel); |
8cdbd2c9 LV |
2291 | emulate_push(ctxt); |
2292 | break; | |
1a52e051 NK |
2293 | } |
2294 | case 0xe9: /* jmp rel */ | |
954cd36f | 2295 | goto jmp; |
782b877c GN |
2296 | case 0xea: /* jmp far */ |
2297 | if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9, | |
2298 | VCPU_SREG_CS) < 0) { | |
954cd36f GT |
2299 | DPRINTF("jmp far: Failed to load CS descriptor\n"); |
2300 | goto cannot_emulate; | |
2301 | } | |
2302 | ||
782b877c | 2303 | c->eip = c->src.val; |
954cd36f | 2304 | break; |
954cd36f GT |
2305 | case 0xeb: |
2306 | jmp: /* jmp rel short */ | |
7a957275 | 2307 | jmp_rel(c, c->src.val); |
a01af5ec | 2308 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 2309 | break; |
a6a3034c MG |
2310 | case 0xec: /* in al,dx */ |
2311 | case 0xed: /* in (e/r)ax,dx */ | |
2312 | port = c->regs[VCPU_REGS_RDX]; | |
2313 | io_dir_in = 1; | |
2314 | goto do_io; | |
2315 | case 0xee: /* out al,dx */ | |
2316 | case 0xef: /* out (e/r)ax,dx */ | |
2317 | port = c->regs[VCPU_REGS_RDX]; | |
2318 | io_dir_in = 0; | |
f850e2e6 GN |
2319 | do_io: |
2320 | if (!emulator_io_permited(ctxt, ops, port, | |
2321 | (c->d & ByteOp) ? 1 : c->op_bytes)) { | |
2322 | kvm_inject_gp(ctxt->vcpu, 0); | |
2323 | goto done; | |
2324 | } | |
2325 | if (kvm_emulate_pio(ctxt->vcpu, io_dir_in, | |
a6a3034c MG |
2326 | (c->d & ByteOp) ? 1 : c->op_bytes, |
2327 | port) != 0) { | |
2328 | c->eip = saved_eip; | |
2329 | goto cannot_emulate; | |
2330 | } | |
e93f36bc | 2331 | break; |
111de5d6 | 2332 | case 0xf4: /* hlt */ |
ad312c7c | 2333 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 2334 | break; |
111de5d6 AK |
2335 | case 0xf5: /* cmc */ |
2336 | /* complement carry flag from eflags reg */ | |
2337 | ctxt->eflags ^= EFLG_CF; | |
2338 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2339 | break; | |
018a98db AK |
2340 | case 0xf6 ... 0xf7: /* Grp3 */ |
2341 | rc = emulate_grp3(ctxt, ops); | |
2342 | if (rc != 0) | |
2343 | goto done; | |
2344 | break; | |
111de5d6 AK |
2345 | case 0xf8: /* clc */ |
2346 | ctxt->eflags &= ~EFLG_CF; | |
2347 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2348 | break; | |
2349 | case 0xfa: /* cli */ | |
f850e2e6 GN |
2350 | if (emulator_bad_iopl(ctxt)) |
2351 | kvm_inject_gp(ctxt->vcpu, 0); | |
2352 | else { | |
2353 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
2354 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2355 | } | |
111de5d6 AK |
2356 | break; |
2357 | case 0xfb: /* sti */ | |
f850e2e6 GN |
2358 | if (emulator_bad_iopl(ctxt)) |
2359 | kvm_inject_gp(ctxt->vcpu, 0); | |
2360 | else { | |
2361 | toggle_interruptibility(ctxt, X86_SHADOW_INT_STI); | |
2362 | ctxt->eflags |= X86_EFLAGS_IF; | |
2363 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2364 | } | |
111de5d6 | 2365 | break; |
fb4616f4 MG |
2366 | case 0xfc: /* cld */ |
2367 | ctxt->eflags &= ~EFLG_DF; | |
2368 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2369 | break; | |
2370 | case 0xfd: /* std */ | |
2371 | ctxt->eflags |= EFLG_DF; | |
2372 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2373 | break; | |
018a98db AK |
2374 | case 0xfe ... 0xff: /* Grp4/Grp5 */ |
2375 | rc = emulate_grp45(ctxt, ops); | |
2376 | if (rc != 0) | |
2377 | goto done; | |
2378 | break; | |
6aa8b732 | 2379 | } |
018a98db AK |
2380 | |
2381 | writeback: | |
2382 | rc = writeback(ctxt, ops); | |
2383 | if (rc != 0) | |
2384 | goto done; | |
2385 | ||
2386 | /* Commit shadow register state. */ | |
ad312c7c | 2387 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); |
5fdbf976 | 2388 | kvm_rip_write(ctxt->vcpu, c->eip); |
018a98db AK |
2389 | |
2390 | done: | |
2391 | if (rc == X86EMUL_UNHANDLEABLE) { | |
2392 | c->eip = saved_eip; | |
2393 | return -1; | |
2394 | } | |
2395 | return 0; | |
6aa8b732 AK |
2396 | |
2397 | twobyte_insn: | |
e4e03ded | 2398 | switch (c->b) { |
6aa8b732 | 2399 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 2400 | switch (c->modrm_reg) { |
6aa8b732 AK |
2401 | u16 size; |
2402 | unsigned long address; | |
2403 | ||
aca7f966 | 2404 | case 0: /* vmcall */ |
e4e03ded | 2405 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
2406 | goto cannot_emulate; |
2407 | ||
7aa81cc0 AL |
2408 | rc = kvm_fix_hypercall(ctxt->vcpu); |
2409 | if (rc) | |
2410 | goto done; | |
2411 | ||
33e3885d | 2412 | /* Let the processor re-execute the fixed hypercall */ |
5fdbf976 | 2413 | c->eip = kvm_rip_read(ctxt->vcpu); |
16286d08 AK |
2414 | /* Disable writeback. */ |
2415 | c->dst.type = OP_NONE; | |
aca7f966 | 2416 | break; |
6aa8b732 | 2417 | case 2: /* lgdt */ |
e4e03ded LV |
2418 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
2419 | &size, &address, c->op_bytes); | |
6aa8b732 AK |
2420 | if (rc) |
2421 | goto done; | |
2422 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
2423 | /* Disable writeback. */ |
2424 | c->dst.type = OP_NONE; | |
6aa8b732 | 2425 | break; |
aca7f966 | 2426 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
2427 | if (c->modrm_mod == 3) { |
2428 | switch (c->modrm_rm) { | |
2429 | case 1: | |
2430 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
2431 | if (rc) | |
2432 | goto done; | |
2433 | break; | |
2434 | default: | |
2435 | goto cannot_emulate; | |
2436 | } | |
aca7f966 | 2437 | } else { |
e4e03ded | 2438 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 2439 | &size, &address, |
e4e03ded | 2440 | c->op_bytes); |
aca7f966 AL |
2441 | if (rc) |
2442 | goto done; | |
2443 | realmode_lidt(ctxt->vcpu, size, address); | |
2444 | } | |
16286d08 AK |
2445 | /* Disable writeback. */ |
2446 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
2447 | break; |
2448 | case 4: /* smsw */ | |
16286d08 AK |
2449 | c->dst.bytes = 2; |
2450 | c->dst.val = realmode_get_cr(ctxt->vcpu, 0); | |
6aa8b732 AK |
2451 | break; |
2452 | case 6: /* lmsw */ | |
16286d08 AK |
2453 | realmode_lmsw(ctxt->vcpu, (u16)c->src.val, |
2454 | &ctxt->eflags); | |
dc7457ea | 2455 | c->dst.type = OP_NONE; |
6aa8b732 AK |
2456 | break; |
2457 | case 7: /* invlpg*/ | |
e8d8d7fe | 2458 | emulate_invlpg(ctxt->vcpu, memop); |
16286d08 AK |
2459 | /* Disable writeback. */ |
2460 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
2461 | break; |
2462 | default: | |
2463 | goto cannot_emulate; | |
2464 | } | |
2465 | break; | |
e99f0507 | 2466 | case 0x05: /* syscall */ |
e66bb2cc AP |
2467 | if (emulate_syscall(ctxt) == -1) |
2468 | goto cannot_emulate; | |
2469 | else | |
2470 | goto writeback; | |
e99f0507 | 2471 | break; |
018a98db AK |
2472 | case 0x06: |
2473 | emulate_clts(ctxt->vcpu); | |
2474 | c->dst.type = OP_NONE; | |
2475 | break; | |
2476 | case 0x08: /* invd */ | |
2477 | case 0x09: /* wbinvd */ | |
2478 | case 0x0d: /* GrpP (prefetch) */ | |
2479 | case 0x18: /* Grp16 (prefetch/nop) */ | |
2480 | c->dst.type = OP_NONE; | |
2481 | break; | |
2482 | case 0x20: /* mov cr, reg */ | |
2483 | if (c->modrm_mod != 3) | |
2484 | goto cannot_emulate; | |
2485 | c->regs[c->modrm_rm] = | |
2486 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); | |
2487 | c->dst.type = OP_NONE; /* no writeback */ | |
2488 | break; | |
6aa8b732 | 2489 | case 0x21: /* mov from dr to reg */ |
e4e03ded | 2490 | if (c->modrm_mod != 3) |
6aa8b732 | 2491 | goto cannot_emulate; |
8cdbd2c9 | 2492 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
a01af5ec LV |
2493 | if (rc) |
2494 | goto cannot_emulate; | |
2495 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 2496 | break; |
018a98db AK |
2497 | case 0x22: /* mov reg, cr */ |
2498 | if (c->modrm_mod != 3) | |
2499 | goto cannot_emulate; | |
2500 | realmode_set_cr(ctxt->vcpu, | |
2501 | c->modrm_reg, c->modrm_val, &ctxt->eflags); | |
2502 | c->dst.type = OP_NONE; | |
2503 | break; | |
6aa8b732 | 2504 | case 0x23: /* mov from reg to dr */ |
e4e03ded | 2505 | if (c->modrm_mod != 3) |
6aa8b732 | 2506 | goto cannot_emulate; |
e4e03ded LV |
2507 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
2508 | c->regs[c->modrm_rm]); | |
a01af5ec LV |
2509 | if (rc) |
2510 | goto cannot_emulate; | |
2511 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 2512 | break; |
018a98db AK |
2513 | case 0x30: |
2514 | /* wrmsr */ | |
2515 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
2516 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
2517 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); | |
2518 | if (rc) { | |
c1a5d4f9 | 2519 | kvm_inject_gp(ctxt->vcpu, 0); |
5fdbf976 | 2520 | c->eip = kvm_rip_read(ctxt->vcpu); |
018a98db AK |
2521 | } |
2522 | rc = X86EMUL_CONTINUE; | |
2523 | c->dst.type = OP_NONE; | |
2524 | break; | |
2525 | case 0x32: | |
2526 | /* rdmsr */ | |
2527 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); | |
2528 | if (rc) { | |
c1a5d4f9 | 2529 | kvm_inject_gp(ctxt->vcpu, 0); |
5fdbf976 | 2530 | c->eip = kvm_rip_read(ctxt->vcpu); |
018a98db AK |
2531 | } else { |
2532 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
2533 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
2534 | } | |
2535 | rc = X86EMUL_CONTINUE; | |
2536 | c->dst.type = OP_NONE; | |
2537 | break; | |
e99f0507 | 2538 | case 0x34: /* sysenter */ |
8c604352 AP |
2539 | if (emulate_sysenter(ctxt) == -1) |
2540 | goto cannot_emulate; | |
2541 | else | |
2542 | goto writeback; | |
e99f0507 AP |
2543 | break; |
2544 | case 0x35: /* sysexit */ | |
4668f050 AP |
2545 | if (emulate_sysexit(ctxt) == -1) |
2546 | goto cannot_emulate; | |
2547 | else | |
2548 | goto writeback; | |
e99f0507 | 2549 | break; |
6aa8b732 | 2550 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 2551 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
2552 | if (!test_cc(c->b, ctxt->eflags)) |
2553 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 2554 | break; |
b2833e3c | 2555 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 2556 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2557 | jmp_rel(c, c->src.val); |
018a98db AK |
2558 | c->dst.type = OP_NONE; |
2559 | break; | |
0934ac9d MG |
2560 | case 0xa0: /* push fs */ |
2561 | emulate_push_sreg(ctxt, VCPU_SREG_FS); | |
2562 | break; | |
2563 | case 0xa1: /* pop fs */ | |
2564 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
2565 | if (rc != 0) | |
2566 | goto done; | |
2567 | break; | |
7de75248 NK |
2568 | case 0xa3: |
2569 | bt: /* bt */ | |
e4f8e039 | 2570 | c->dst.type = OP_NONE; |
e4e03ded LV |
2571 | /* only subword offset */ |
2572 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 2573 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 2574 | break; |
9bf8ea42 GT |
2575 | case 0xa4: /* shld imm8, r, r/m */ |
2576 | case 0xa5: /* shld cl, r, r/m */ | |
2577 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
2578 | break; | |
0934ac9d MG |
2579 | case 0xa8: /* push gs */ |
2580 | emulate_push_sreg(ctxt, VCPU_SREG_GS); | |
2581 | break; | |
2582 | case 0xa9: /* pop gs */ | |
2583 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
2584 | if (rc != 0) | |
2585 | goto done; | |
2586 | break; | |
7de75248 NK |
2587 | case 0xab: |
2588 | bts: /* bts */ | |
e4e03ded LV |
2589 | /* only subword offset */ |
2590 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 2591 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 2592 | break; |
9bf8ea42 GT |
2593 | case 0xac: /* shrd imm8, r, r/m */ |
2594 | case 0xad: /* shrd cl, r, r/m */ | |
2595 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
2596 | break; | |
2a7c5b8b GC |
2597 | case 0xae: /* clflush */ |
2598 | break; | |
6aa8b732 AK |
2599 | case 0xb0 ... 0xb1: /* cmpxchg */ |
2600 | /* | |
2601 | * Save real source value, then compare EAX against | |
2602 | * destination. | |
2603 | */ | |
e4e03ded LV |
2604 | c->src.orig_val = c->src.val; |
2605 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
2606 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
2607 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 2608 | /* Success: write back to memory. */ |
e4e03ded | 2609 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
2610 | } else { |
2611 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
2612 | c->dst.type = OP_REG; |
2613 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
2614 | } |
2615 | break; | |
6aa8b732 AK |
2616 | case 0xb3: |
2617 | btr: /* btr */ | |
e4e03ded LV |
2618 | /* only subword offset */ |
2619 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 2620 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2621 | break; |
6aa8b732 | 2622 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
2623 | c->dst.bytes = c->op_bytes; |
2624 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
2625 | : (u16) c->src.val; | |
6aa8b732 | 2626 | break; |
6aa8b732 | 2627 | case 0xba: /* Grp8 */ |
e4e03ded | 2628 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
2629 | case 0: |
2630 | goto bt; | |
2631 | case 1: | |
2632 | goto bts; | |
2633 | case 2: | |
2634 | goto btr; | |
2635 | case 3: | |
2636 | goto btc; | |
2637 | } | |
2638 | break; | |
7de75248 NK |
2639 | case 0xbb: |
2640 | btc: /* btc */ | |
e4e03ded LV |
2641 | /* only subword offset */ |
2642 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 2643 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 2644 | break; |
6aa8b732 | 2645 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
2646 | c->dst.bytes = c->op_bytes; |
2647 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
2648 | (s16) c->src.val; | |
6aa8b732 | 2649 | break; |
a012e65a | 2650 | case 0xc3: /* movnti */ |
e4e03ded LV |
2651 | c->dst.bytes = c->op_bytes; |
2652 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
2653 | (u64) c->src.val; | |
a012e65a | 2654 | break; |
6aa8b732 | 2655 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
e8d8d7fe | 2656 | rc = emulate_grp9(ctxt, ops, memop); |
8cdbd2c9 LV |
2657 | if (rc != 0) |
2658 | goto done; | |
018a98db | 2659 | c->dst.type = OP_NONE; |
8cdbd2c9 | 2660 | break; |
6aa8b732 AK |
2661 | } |
2662 | goto writeback; | |
2663 | ||
2664 | cannot_emulate: | |
e4e03ded | 2665 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 2666 | c->eip = saved_eip; |
6aa8b732 AK |
2667 | return -1; |
2668 | } |