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KVM: x86: Perform limit checks when assigning EIP
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 169#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 170#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 171
820207c8 172#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 173
d0e53325
AK		 174#define X2(x...) x, x
175#define X3(x...) X2(x), x
176#define X4(x...) X2(x), X2(x)
177#define X5(x...) X4(x), x
178#define X6(x...) X4(x), X2(x)
179#define X7(x...) X4(x), X3(x)
180#define X8(x...) X4(x), X4(x)
181#define X16(x...) X8(x), X8(x)
83babbca 182
e28bbd44
AK		 183#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
184#define FASTOP_SIZE 8
185
186/*
187 * fastop functions have a special calling convention:
188 *
017da7b6
AK		 189 * dst: rax (in/out)
190 * src: rdx (in/out)
e28bbd44
AK		 191 * src2: rcx (in)
192 * flags: rflags (in/out)
b8c0b6ae 193 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 194 *
195 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
196 * different operand sizes can be reached by calculation, rather than a jump
197 * table (which would be bigger than the code).
198 *
199 * fastop functions are declared as taking a never-defined fastop parameter,
200 * so they can't be called from C directly.
201 */
202
203struct fastop;
204
d65b1dee 205struct opcode {
b1ea50b2
AK		 206 u64 flags : 56;
207 u64 intercept : 8;
120df890 208 union {
ef65c889 209 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 210 const struct opcode *group;
211 const struct group_dual *gdual;
212 const struct gprefix *gprefix;
045a282c 213 const struct escape *esc;
e28bbd44 214 void (*fastop)(struct fastop *fake);
120df890 215 } u;
d09beabd 216 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 217};
218
219struct group_dual {
220 struct opcode mod012[8];
221 struct opcode mod3[8];
d65b1dee
AK		 222};
223
0d7cdee8
AK		 224struct gprefix {
225 struct opcode pfx_no;
226 struct opcode pfx_66;
227 struct opcode pfx_f2;
228 struct opcode pfx_f3;
229};
230
045a282c
GN		 231struct escape {
232 struct opcode op[8];
233 struct opcode high[64];
234};
235
6aa8b732 236/* EFLAGS bit definitions. */
d4c6a154
GN		 237#define EFLG_ID (1<<21)
238#define EFLG_VIP (1<<20)
239#define EFLG_VIF (1<<19)
240#define EFLG_AC (1<<18)
b1d86143
AP		 241#define EFLG_VM (1<<17)
242#define EFLG_RF (1<<16)
d4c6a154
GN		 243#define EFLG_IOPL (3<<12)
244#define EFLG_NT (1<<14)
6aa8b732
AK		 245#define EFLG_OF (1<<11)
246#define EFLG_DF (1<<10)
b1d86143 247#define EFLG_IF (1<<9)
d4c6a154 248#define EFLG_TF (1<<8)
6aa8b732
AK		 249#define EFLG_SF (1<<7)
250#define EFLG_ZF (1<<6)
251#define EFLG_AF (1<<4)
252#define EFLG_PF (1<<2)
253#define EFLG_CF (1<<0)
254
62bd430e
MG		 255#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
256#define EFLG_RESERVED_ONE_MASK 2
257
dd856efa
AK		 258static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
259{
260 if (!(ctxt->regs_valid & (1 << nr))) {
261 ctxt->regs_valid |= 1 << nr;
262 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
263 }
264 return ctxt->_regs[nr];
265}
266
267static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
268{
269 ctxt->regs_valid |= 1 << nr;
270 ctxt->regs_dirty |= 1 << nr;
271 return &ctxt->_regs[nr];
272}
273
274static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 reg_read(ctxt, nr);
277 return reg_write(ctxt, nr);
278}
279
280static void writeback_registers(struct x86_emulate_ctxt *ctxt)
281{
282 unsigned reg;
283
284 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
285 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
286}
287
288static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
289{
290 ctxt->regs_dirty = 0;
291 ctxt->regs_valid = 0;
292}
293
6aa8b732
AK		 294/*
295 * These EFLAGS bits are restored from saved value during emulation, and
296 * any changes are written back to the saved value after emulation.
297 */
298#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
299
dda96d8f
AK		 300#ifdef CONFIG_X86_64
301#define ON64(x) x
302#else
303#define ON64(x)
304#endif
305
4d758349
AK		 306static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
307
b7d491e7
AK		 308#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
309#define FOP_RET "ret \n\t"
310
311#define FOP_START(op) \
312 extern void em_##op(struct fastop *fake); \
313 asm(".pushsection .text, \"ax\" \n\t" \
314 ".global em_" #op " \n\t" \
315 FOP_ALIGN \
316 "em_" #op ": \n\t"
317
318#define FOP_END \
319 ".popsection")
320
0bdea068
AK		 321#define FOPNOP() FOP_ALIGN FOP_RET
322
b7d491e7 323#define FOP1E(op, dst) \
b8c0b6ae
AK		 324 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
325
326#define FOP1EEX(op, dst) \
327 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 328
329#define FASTOP1(op) \
330 FOP_START(op) \
331 FOP1E(op##b, al) \
332 FOP1E(op##w, ax) \
333 FOP1E(op##l, eax) \
334 ON64(FOP1E(op##q, rax)) \
335 FOP_END
336
b9fa409b
AK		 337/* 1-operand, using src2 (for MUL/DIV r/m) */
338#define FASTOP1SRC2(op, name) \
339 FOP_START(name) \
340 FOP1E(op, cl) \
341 FOP1E(op, cx) \
342 FOP1E(op, ecx) \
343 ON64(FOP1E(op, rcx)) \
344 FOP_END
345
b8c0b6ae
AK		 346/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
347#define FASTOP1SRC2EX(op, name) \
348 FOP_START(name) \
349 FOP1EEX(op, cl) \
350 FOP1EEX(op, cx) \
351 FOP1EEX(op, ecx) \
352 ON64(FOP1EEX(op, rcx)) \
353 FOP_END
354
f7857f35
AK		 355#define FOP2E(op, dst, src) \
356 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
357
358#define FASTOP2(op) \
359 FOP_START(op) \
017da7b6
AK		 360 FOP2E(op##b, al, dl) \
361 FOP2E(op##w, ax, dx) \
362 FOP2E(op##l, eax, edx) \
363 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 364 FOP_END
365
11c363ba
AK		 366/* 2 operand, word only */
367#define FASTOP2W(op) \
368 FOP_START(op) \
369 FOPNOP() \
017da7b6
AK		 370 FOP2E(op##w, ax, dx) \
371 FOP2E(op##l, eax, edx) \
372 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 373 FOP_END
374
007a3b54
AK		 375/* 2 operand, src is CL */
376#define FASTOP2CL(op) \
377 FOP_START(op) \
378 FOP2E(op##b, al, cl) \
379 FOP2E(op##w, ax, cl) \
380 FOP2E(op##l, eax, cl) \
381 ON64(FOP2E(op##q, rax, cl)) \
382 FOP_END
383
5aca3722
NA		 384/* 2 operand, src and dest are reversed */
385#define FASTOP2R(op, name) \
386 FOP_START(name) \
387 FOP2E(op##b, dl, al) \
388 FOP2E(op##w, dx, ax) \
389 FOP2E(op##l, edx, eax) \
390 ON64(FOP2E(op##q, rdx, rax)) \
391 FOP_END
392
0bdea068
AK		 393#define FOP3E(op, dst, src, src2) \
394 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
395
396/* 3-operand, word-only, src2=cl */
397#define FASTOP3WCL(op) \
398 FOP_START(op) \
399 FOPNOP() \
017da7b6
AK		 400 FOP3E(op##w, ax, dx, cl) \
401 FOP3E(op##l, eax, edx, cl) \
402 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 403 FOP_END
404
9ae9feba
AK		 405/* Special case for SETcc - 1 instruction per cc */
406#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
407
b8c0b6ae
AK		 408asm(".global kvm_fastop_exception \n"
409 "kvm_fastop_exception: xor %esi, %esi; ret");
410
9ae9feba
AK		 411FOP_START(setcc)
412FOP_SETCC(seto)
413FOP_SETCC(setno)
414FOP_SETCC(setc)
415FOP_SETCC(setnc)
416FOP_SETCC(setz)
417FOP_SETCC(setnz)
418FOP_SETCC(setbe)
419FOP_SETCC(setnbe)
420FOP_SETCC(sets)
421FOP_SETCC(setns)
422FOP_SETCC(setp)
423FOP_SETCC(setnp)
424FOP_SETCC(setl)
425FOP_SETCC(setnl)
426FOP_SETCC(setle)
427FOP_SETCC(setnle)
428FOP_END;
429
326f578f
PB		 430FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
431FOP_END;
432
8a76d7f2
JR		 433static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
434 enum x86_intercept intercept,
435 enum x86_intercept_stage stage)
436{
437 struct x86_instruction_info info = {
438 .intercept = intercept,
9dac77fa
AK		 439 .rep_prefix = ctxt->rep_prefix,
440 .modrm_mod = ctxt->modrm_mod,
441 .modrm_reg = ctxt->modrm_reg,
442 .modrm_rm = ctxt->modrm_rm,
443 .src_val = ctxt->src.val64,
6cbc5f5a 444 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 445 .src_bytes = ctxt->src.bytes,
446 .dst_bytes = ctxt->dst.bytes,
447 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 448 .next_rip = ctxt->eip,
449 };
450
2953538e 451 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 452}
453
f47cfa31
AK		 454static void assign_masked(ulong *dest, ulong src, ulong mask)
455{
456 *dest = (*dest & ~mask) | (src & mask);
457}
458
9dac77fa 459static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 460{
9dac77fa 461 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 462}
463
f47cfa31
AK		 464static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
465{
466 u16 sel;
467 struct desc_struct ss;
468
469 if (ctxt->mode == X86EMUL_MODE_PROT64)
470 return ~0UL;
471 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
472 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
473}
474
612e89f0
AK		 475static int stack_size(struct x86_emulate_ctxt *ctxt)
476{
477 return (__fls(stack_mask(ctxt)) + 1) >> 3;
478}
479
6aa8b732 480/* Access/update address held in a register, based on addressing mode. */
e4706772 481static inline unsigned long
9dac77fa 482address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 483{
9dac77fa 484 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 485 return reg;
486 else
9dac77fa 487 return reg & ad_mask(ctxt);
e4706772
HH		 488}
489
490static inline unsigned long
9dac77fa 491register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 492{
9dac77fa 493 return address_mask(ctxt, reg);
e4706772
HH		 494}
495
5ad105e5
AK		 496static void masked_increment(ulong *reg, ulong mask, int inc)
497{
498 assign_masked(reg, *reg + inc, mask);
499}
500
7a957275 501static inline void
9dac77fa 502register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 503{
5ad105e5
AK		 504 ulong mask;
505
9dac77fa 506 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 507 mask = ~0UL;
7a957275 508 else
5ad105e5
AK		 509 mask = ad_mask(ctxt);
510 masked_increment(reg, mask, inc);
511}
512
513static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
514{
dd856efa 515 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 516}
6aa8b732 517
56697687
AK		 518static u32 desc_limit_scaled(struct desc_struct *desc)
519{
520 u32 limit = get_desc_limit(desc);
521
522 return desc->g ? (limit << 12) | 0xfff : limit;
523}
524
7b105ca2 525static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 526{
527 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
528 return 0;
529
7b105ca2 530 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 531}
532
35d3d4a1
AK		 533static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
534 u32 error, bool valid)
54b8486f 535{
e0ad0b47 536 WARN_ON(vec > 0x1f);
da9cb575
AK		 537 ctxt->exception.vector = vec;
538 ctxt->exception.error_code = error;
539 ctxt->exception.error_code_valid = valid;
35d3d4a1 540 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 541}
542
3b88e41a
JR		 543static int emulate_db(struct x86_emulate_ctxt *ctxt)
544{
545 return emulate_exception(ctxt, DB_VECTOR, 0, false);
546}
547
35d3d4a1 548static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 549{
35d3d4a1 550 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 551}
552
618ff15d
AK		 553static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
554{
555 return emulate_exception(ctxt, SS_VECTOR, err, true);
556}
557
35d3d4a1 558static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 559{
35d3d4a1 560 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 561}
562
35d3d4a1 563static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 566}
567
34d1f490
AK		 568static int emulate_de(struct x86_emulate_ctxt *ctxt)
569{
35d3d4a1 570 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 571}
572
1253791d
AK		 573static int emulate_nm(struct x86_emulate_ctxt *ctxt)
574{
575 return emulate_exception(ctxt, NM_VECTOR, 0, false);
576}
577
1aa36616
AK		 578static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
579{
580 u16 selector;
581 struct desc_struct desc;
582
583 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
584 return selector;
585}
586
587static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
588 unsigned seg)
589{
590 u16 dummy;
591 u32 base3;
592 struct desc_struct desc;
593
594 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
595 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
596}
597
1c11b376
AK		 598/*
599 * x86 defines three classes of vector instructions: explicitly
600 * aligned, explicitly unaligned, and the rest, which change behaviour
601 * depending on whether they're AVX encoded or not.
602 *
603 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
604 * subject to the same check.
605 */
606static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
607{
608 if (likely(size < 16))
609 return false;
610
611 if (ctxt->d & Aligned)
612 return true;
613 else if (ctxt->d & Unaligned)
614 return false;
615 else if (ctxt->d & Avx)
616 return false;
617 else
618 return true;
619}
620
d09155d2
PB		 621static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
622 struct segmented_address addr,
623 unsigned *max_size, unsigned size,
624 bool write, bool fetch,
d50eaa18 625 enum x86emul_mode mode, ulong *linear)
52fd8b44 626{
618ff15d
AK		 627 struct desc_struct desc;
628 bool usable;
52fd8b44 629 ulong la;
618ff15d 630 u32 lim;
1aa36616 631 u16 sel;
52fd8b44 632
1c1c35ae 633 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 634 *max_size = 0;
d50eaa18 635 switch (mode) {
618ff15d 636 case X86EMUL_MODE_PROT64:
4be4de7e 637 if (is_noncanonical_address(la))
618ff15d 638 return emulate_gp(ctxt, 0);
fd56e154
PB		 639
640 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
641 if (size > *max_size)
642 goto bad;
618ff15d
AK		 643 break;
644 default:
1aa36616
AK		 645 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
646 addr.seg);
618ff15d
AK		 647 if (!usable)
648 goto bad;
58b7825b
GN		 649 /* code segment in protected mode or read-only data segment */
650 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
651 || !(desc.type & 2)) && write)
618ff15d
AK		 652 goto bad;
653 /* unreadable code segment */
3d9b938e 654 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 655 goto bad;
656 lim = desc_limit_scaled(&desc);
7d882ffa 657 if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d 658 /* expand-up segment */
fd56e154 659 if (addr.ea > lim)
618ff15d 660 goto bad;
fd56e154 661 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 662 } else {
fc058680 663 /* expand-down segment */
fd56e154 664 if (addr.ea <= lim)
618ff15d
AK		 665 goto bad;
666 lim = desc.d ? 0xffffffff : 0xffff;
fd56e154 667 if (addr.ea > lim)
618ff15d 668 goto bad;
fd56e154 669 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 670 }
fd56e154
PB		 671 if (size > *max_size)
672 goto bad;
618ff15d
AK		 673 break;
674 }
518547b3 675 if (ctxt->mode != X86EMUL_MODE_PROT64)
52fd8b44 676 la &= (u32)-1;
1c11b376
AK		 677 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
678 return emulate_gp(ctxt, 0);
52fd8b44
AK		 679 *linear = la;
680 return X86EMUL_CONTINUE;
618ff15d
AK		 681bad:
682 if (addr.seg == VCPU_SREG_SS)
3606189f 683 return emulate_ss(ctxt, 0);
618ff15d 684 else
3606189f 685 return emulate_gp(ctxt, 0);
52fd8b44
AK		 686}
687
3d9b938e
NE		 688static int linearize(struct x86_emulate_ctxt *ctxt,
689 struct segmented_address addr,
690 unsigned size, bool write,
691 ulong *linear)
692{
fd56e154 693 unsigned max_size;
d50eaa18
NA		 694 return __linearize(ctxt, addr, &max_size, size, write, false,
695 ctxt->mode, linear);
3d9b938e
NE		 696}
697
d50eaa18
NA		 698static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
699 enum x86emul_mode mode)
700{
701 ulong linear;
702 int rc;
703 unsigned max_size;
704 struct segmented_address addr = { .seg = VCPU_SREG_CS,
705 .ea = dst };
706
707 if (ctxt->op_bytes != sizeof(unsigned long))
708 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
709 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
710 if (rc == X86EMUL_CONTINUE)
711 ctxt->_eip = addr.ea;
712 return rc;
713}
714
715static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
716{
717 return assign_eip(ctxt, dst, ctxt->mode);
718}
719
720static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
721 const struct desc_struct *cs_desc)
722{
723 enum x86emul_mode mode = ctxt->mode;
724
725#ifdef CONFIG_X86_64
726 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
727 u64 efer = 0;
728
729 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
730 if (efer & EFER_LMA)
731 mode = X86EMUL_MODE_PROT64;
732 }
733#endif
734 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
735 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
736 return assign_eip(ctxt, dst, mode);
737}
738
739static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
740{
741 return assign_eip_near(ctxt, ctxt->_eip + rel);
742}
3d9b938e 743
3ca3ac4d
AK		 744static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
745 struct segmented_address addr,
746 void *data,
747 unsigned size)
748{
9fa088f4
AK		 749 int rc;
750 ulong linear;
751
83b8795a 752 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 753 if (rc != X86EMUL_CONTINUE)
754 return rc;
0f65dd70 755 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 756}
757
807941b1 758/*
285ca9e9 759 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 760 * boundary if they are not in fetch_cache yet.
761 */
9506d57d 762static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 763{
62266869 764 int rc;
fd56e154 765 unsigned size, max_size;
285ca9e9 766 unsigned long linear;
17052f16 767 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 768 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 769 .ea = ctxt->eip + cur_size };
770
fd56e154
PB		 771 /*
772 * We do not know exactly how many bytes will be needed, and
773 * __linearize is expensive, so fetch as much as possible. We
774 * just have to avoid going beyond the 15 byte limit, the end
775 * of the segment, or the end of the page.
776 *
777 * __linearize is called with size 0 so that it does not do any
778 * boundary check itself. Instead, we use max_size to check
779 * against op_size.
780 */
d50eaa18
NA		 781 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
782 &linear);
719d5a9b
PB		 783 if (unlikely(rc != X86EMUL_CONTINUE))
784 return rc;
785
fd56e154 786 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 787 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 788
789 /*
790 * One instruction can only straddle two pages,
791 * and one has been loaded at the beginning of
792 * x86_decode_insn. So, if not enough bytes
793 * still, we must have hit the 15-byte boundary.
794 */
795 if (unlikely(size < op_size))
fd56e154
PB		 796 return emulate_gp(ctxt, 0);
797
17052f16 798 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 799 size, &ctxt->exception);
800 if (unlikely(rc != X86EMUL_CONTINUE))
801 return rc;
17052f16 802 ctxt->fetch.end += size;
3e2815e9 803 return X86EMUL_CONTINUE;
62266869
AK		 804}
805
9506d57d
PB		 806static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
807 unsigned size)
62266869 808{
08da44ae
NA		 809 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
810
811 if (unlikely(done_size < size))
812 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 813 else
814 return X86EMUL_CONTINUE;
62266869
AK		 815}
816
67cbc90d 817/* Fetch next part of the instruction being emulated. */
e85a1085 818#define insn_fetch(_type, _ctxt) \
9506d57d 819({ _type _x; \
9506d57d
PB		 820 \
821 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 822 if (rc != X86EMUL_CONTINUE) \
823 goto done; \
9506d57d 824 ctxt->_eip += sizeof(_type); \
17052f16
PB		 825 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
826 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 827 _x; \
67cbc90d
TY		 828})
829
807941b1 830#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 831({ \
9506d57d 832 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 833 if (rc != X86EMUL_CONTINUE) \
834 goto done; \
9506d57d 835 ctxt->_eip += (_size); \
17052f16
PB		 836 memcpy(_arr, ctxt->fetch.ptr, _size); \
837 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 838})
839
1e3c5cb0
RR		 840/*
841 * Given the 'reg' portion of a ModRM byte, and a register block, return a
842 * pointer into the block that addresses the relevant register.
843 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
844 */
dd856efa 845static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 846 int byteop)
6aa8b732
AK		 847{
848 void *p;
aa9ac1a6 849 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 850
6aa8b732 851 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 852 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
853 else
854 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 855 return p;
856}
857
858static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 859 struct segmented_address addr,
6aa8b732
AK		 860 u16 *size, unsigned long *address, int op_bytes)
861{
862 int rc;
863
864 if (op_bytes == 2)
865 op_bytes = 3;
866 *address = 0;
3ca3ac4d 867 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 868 if (rc != X86EMUL_CONTINUE)
6aa8b732 869 return rc;
30b31ab6 870 addr.ea += 2;
3ca3ac4d 871 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 872 return rc;
873}
874
34b77652
AK		 875FASTOP2(add);
876FASTOP2(or);
877FASTOP2(adc);
878FASTOP2(sbb);
879FASTOP2(and);
880FASTOP2(sub);
881FASTOP2(xor);
882FASTOP2(cmp);
883FASTOP2(test);
884
b9fa409b
AK		 885FASTOP1SRC2(mul, mul_ex);
886FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 887FASTOP1SRC2EX(div, div_ex);
888FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 889
34b77652
AK		 890FASTOP3WCL(shld);
891FASTOP3WCL(shrd);
892
893FASTOP2W(imul);
894
895FASTOP1(not);
896FASTOP1(neg);
897FASTOP1(inc);
898FASTOP1(dec);
899
900FASTOP2CL(rol);
901FASTOP2CL(ror);
902FASTOP2CL(rcl);
903FASTOP2CL(rcr);
904FASTOP2CL(shl);
905FASTOP2CL(shr);
906FASTOP2CL(sar);
907
908FASTOP2W(bsf);
909FASTOP2W(bsr);
910FASTOP2W(bt);
911FASTOP2W(bts);
912FASTOP2W(btr);
913FASTOP2W(btc);
914
e47a5f5f
AK		 915FASTOP2(xadd);
916
5aca3722
NA		 917FASTOP2R(cmp, cmp_r);
918
9ae9feba 919static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 920{
9ae9feba
AK		 921 u8 rc;
922 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 923
9ae9feba 924 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 925 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 926 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
927 return rc;
bbe9abbd
NK		 928}
929
91ff3cb4
AK		 930static void fetch_register_operand(struct operand *op)
931{
932 switch (op->bytes) {
933 case 1:
934 op->val = *(u8 *)op->addr.reg;
935 break;
936 case 2:
937 op->val = *(u16 *)op->addr.reg;
938 break;
939 case 4:
940 op->val = *(u32 *)op->addr.reg;
941 break;
942 case 8:
943 op->val = *(u64 *)op->addr.reg;
944 break;
945 }
946}
947
1253791d
AK		 948static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
949{
950 ctxt->ops->get_fpu(ctxt);
951 switch (reg) {
89a87c67
MK		 952 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
953 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
954 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
955 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
956 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
957 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
958 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
959 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 960#ifdef CONFIG_X86_64
89a87c67
MK		 961 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
962 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
963 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
964 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
965 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
966 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
967 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
968 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 969#endif
970 default: BUG();
971 }
972 ctxt->ops->put_fpu(ctxt);
973}
974
975static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
976 int reg)
977{
978 ctxt->ops->get_fpu(ctxt);
979 switch (reg) {
89a87c67
MK		 980 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
981 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
982 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
983 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
984 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
985 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
986 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
987 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 988#ifdef CONFIG_X86_64
89a87c67
MK		 989 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
990 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
991 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
992 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
993 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
994 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
995 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
996 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 997#endif
998 default: BUG();
999 }
1000 ctxt->ops->put_fpu(ctxt);
1001}
1002
cbe2c9d3
AK		 1003static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1004{
1005 ctxt->ops->get_fpu(ctxt);
1006 switch (reg) {
1007 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1008 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1009 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1010 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1011 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1012 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1013 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1014 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1015 default: BUG();
1016 }
1017 ctxt->ops->put_fpu(ctxt);
1018}
1019
1020static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1021{
1022 ctxt->ops->get_fpu(ctxt);
1023 switch (reg) {
1024 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1025 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1026 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1027 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1028 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1029 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1030 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1031 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1032 default: BUG();
1033 }
1034 ctxt->ops->put_fpu(ctxt);
1035}
1036
045a282c
GN		 1037static int em_fninit(struct x86_emulate_ctxt *ctxt)
1038{
1039 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1040 return emulate_nm(ctxt);
1041
1042 ctxt->ops->get_fpu(ctxt);
1043 asm volatile("fninit");
1044 ctxt->ops->put_fpu(ctxt);
1045 return X86EMUL_CONTINUE;
1046}
1047
1048static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1049{
1050 u16 fcw;
1051
1052 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1053 return emulate_nm(ctxt);
1054
1055 ctxt->ops->get_fpu(ctxt);
1056 asm volatile("fnstcw %0": "+m"(fcw));
1057 ctxt->ops->put_fpu(ctxt);
1058
1059 /* force 2 byte destination */
1060 ctxt->dst.bytes = 2;
1061 ctxt->dst.val = fcw;
1062
1063 return X86EMUL_CONTINUE;
1064}
1065
1066static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1067{
1068 u16 fsw;
1069
1070 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1071 return emulate_nm(ctxt);
1072
1073 ctxt->ops->get_fpu(ctxt);
1074 asm volatile("fnstsw %0": "+m"(fsw));
1075 ctxt->ops->put_fpu(ctxt);
1076
1077 /* force 2 byte destination */
1078 ctxt->dst.bytes = 2;
1079 ctxt->dst.val = fsw;
1080
1081 return X86EMUL_CONTINUE;
1082}
1083
1253791d 1084static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1085 struct operand *op)
3c118e24 1086{
9dac77fa 1087 unsigned reg = ctxt->modrm_reg;
33615aa9 1088
9dac77fa
AK		 1089 if (!(ctxt->d & ModRM))
1090 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1091
9dac77fa 1092 if (ctxt->d & Sse) {
1253791d
AK		 1093 op->type = OP_XMM;
1094 op->bytes = 16;
1095 op->addr.xmm = reg;
1096 read_sse_reg(ctxt, &op->vec_val, reg);
1097 return;
1098 }
cbe2c9d3
AK		 1099 if (ctxt->d & Mmx) {
1100 reg &= 7;
1101 op->type = OP_MM;
1102 op->bytes = 8;
1103 op->addr.mm = reg;
1104 return;
1105 }
1253791d 1106
3c118e24 1107 op->type = OP_REG;
6d4d85ec
GN		 1108 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1109 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1110
91ff3cb4 1111 fetch_register_operand(op);
3c118e24
AK		 1112 op->orig_val = op->val;
1113}
1114
a6e3407b
AK		 1115static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1116{
1117 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1118 ctxt->modrm_seg = VCPU_SREG_SS;
1119}
1120
1c73ef66 1121static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1122 struct operand *op)
1c73ef66 1123{
1c73ef66 1124 u8 sib;
02357bdc 1125 int index_reg, base_reg, scale;
3e2815e9 1126 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1127 ulong modrm_ea = 0;
1c73ef66 1128
02357bdc
BD		 1129 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1130 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1131 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1132
02357bdc 1133 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1134 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1135 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1136 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1137
9b88ae99 1138 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1139 op->type = OP_REG;
9dac77fa 1140 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1141 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1142 ctxt->d & ByteOp);
9dac77fa 1143 if (ctxt->d & Sse) {
1253791d
AK		 1144 op->type = OP_XMM;
1145 op->bytes = 16;
9dac77fa
AK		 1146 op->addr.xmm = ctxt->modrm_rm;
1147 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1148 return rc;
1149 }
cbe2c9d3
AK		 1150 if (ctxt->d & Mmx) {
1151 op->type = OP_MM;
1152 op->bytes = 8;
bdc90722 1153 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1154 return rc;
1155 }
2dbd0dd7 1156 fetch_register_operand(op);
1c73ef66
AK		 1157 return rc;
1158 }
1159
2dbd0dd7
AK		 1160 op->type = OP_MEM;
1161
9dac77fa 1162 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1163 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1164 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1165 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1166 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1167
1168 /* 16-bit ModR/M decode. */
9dac77fa 1169 switch (ctxt->modrm_mod) {
1c73ef66 1170 case 0:
9dac77fa 1171 if (ctxt->modrm_rm == 6)
e85a1085 1172 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1173 break;
1174 case 1:
e85a1085 1175 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1176 break;
1177 case 2:
e85a1085 1178 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1179 break;
1180 }
9dac77fa 1181 switch (ctxt->modrm_rm) {
1c73ef66 1182 case 0:
2dbd0dd7 1183 modrm_ea += bx + si;
1c73ef66
AK		 1184 break;
1185 case 1:
2dbd0dd7 1186 modrm_ea += bx + di;
1c73ef66
AK		 1187 break;
1188 case 2:
2dbd0dd7 1189 modrm_ea += bp + si;
1c73ef66
AK		 1190 break;
1191 case 3:
2dbd0dd7 1192 modrm_ea += bp + di;
1c73ef66
AK		 1193 break;
1194 case 4:
2dbd0dd7 1195 modrm_ea += si;
1c73ef66
AK		 1196 break;
1197 case 5:
2dbd0dd7 1198 modrm_ea += di;
1c73ef66
AK		 1199 break;
1200 case 6:
9dac77fa 1201 if (ctxt->modrm_mod != 0)
2dbd0dd7 1202 modrm_ea += bp;
1c73ef66
AK		 1203 break;
1204 case 7:
2dbd0dd7 1205 modrm_ea += bx;
1c73ef66
AK		 1206 break;
1207 }
9dac77fa
AK		 1208 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1209 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1210 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1211 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1212 } else {
1213 /* 32/64-bit ModR/M decode. */
9dac77fa 1214 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1215 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1216 index_reg |= (sib >> 3) & 7;
1217 base_reg |= sib & 7;
1218 scale = sib >> 6;
1219
9dac77fa 1220 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1221 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1222 else {
dd856efa 1223 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1224 adjust_modrm_seg(ctxt, base_reg);
1225 }
dc71d0f1 1226 if (index_reg != 4)
dd856efa 1227 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1228 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1229 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1230 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1231 ctxt->rip_relative = 1;
a6e3407b
AK		 1232 } else {
1233 base_reg = ctxt->modrm_rm;
dd856efa 1234 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1235 adjust_modrm_seg(ctxt, base_reg);
1236 }
9dac77fa 1237 switch (ctxt->modrm_mod) {
1c73ef66 1238 case 1:
e85a1085 1239 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1240 break;
1241 case 2:
e85a1085 1242 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1243 break;
1244 }
1245 }
90de84f5 1246 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1247 if (ctxt->ad_bytes != 8)
1248 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1249
1c73ef66
AK		 1250done:
1251 return rc;
1252}
1253
1254static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1255 struct operand *op)
1c73ef66 1256{
3e2815e9 1257 int rc = X86EMUL_CONTINUE;
1c73ef66 1258
2dbd0dd7 1259 op->type = OP_MEM;
9dac77fa 1260 switch (ctxt->ad_bytes) {
1c73ef66 1261 case 2:
e85a1085 1262 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1263 break;
1264 case 4:
e85a1085 1265 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1266 break;
1267 case 8:
e85a1085 1268 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1269 break;
1270 }
1271done:
1272 return rc;
1273}
1274
9dac77fa 1275static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1276{
7129eeca 1277 long sv = 0, mask;
35c843c4 1278
9dac77fa 1279 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1280 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1281
9dac77fa
AK		 1282 if (ctxt->src.bytes == 2)
1283 sv = (s16)ctxt->src.val & (s16)mask;
1284 else if (ctxt->src.bytes == 4)
1285 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1286 else
1287 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1288
1c1c35ae
NA		 1289 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1290 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1291 }
ba7ff2b7
WY		 1292
1293 /* only subword offset */
9dac77fa 1294 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1295}
1296
dde7e6d1 1297static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1298 unsigned long addr, void *dest, unsigned size)
6aa8b732 1299{
dde7e6d1 1300 int rc;
9dac77fa 1301 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1302
f23b070e
XG		 1303 if (mc->pos < mc->end)
1304 goto read_cached;
6aa8b732 1305
f23b070e
XG		 1306 WARN_ON((mc->end + size) >= sizeof(mc->data));
1307
1308 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1309 &ctxt->exception);
1310 if (rc != X86EMUL_CONTINUE)
1311 return rc;
1312
1313 mc->end += size;
1314
1315read_cached:
1316 memcpy(dest, mc->data + mc->pos, size);
1317 mc->pos += size;
dde7e6d1
AK		 1318 return X86EMUL_CONTINUE;
1319}
6aa8b732 1320
3ca3ac4d
AK		 1321static int segmented_read(struct x86_emulate_ctxt *ctxt,
1322 struct segmented_address addr,
1323 void *data,
1324 unsigned size)
1325{
9fa088f4
AK		 1326 int rc;
1327 ulong linear;
1328
83b8795a 1329 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1330 if (rc != X86EMUL_CONTINUE)
1331 return rc;
7b105ca2 1332 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1333}
1334
1335static int segmented_write(struct x86_emulate_ctxt *ctxt,
1336 struct segmented_address addr,
1337 const void *data,
1338 unsigned size)
1339{
9fa088f4
AK		 1340 int rc;
1341 ulong linear;
1342
83b8795a 1343 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1344 if (rc != X86EMUL_CONTINUE)
1345 return rc;
0f65dd70
AK		 1346 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1347 &ctxt->exception);
3ca3ac4d
AK		 1348}
1349
1350static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1351 struct segmented_address addr,
1352 const void *orig_data, const void *data,
1353 unsigned size)
1354{
9fa088f4
AK		 1355 int rc;
1356 ulong linear;
1357
83b8795a 1358 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1359 if (rc != X86EMUL_CONTINUE)
1360 return rc;
0f65dd70
AK		 1361 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1362 size, &ctxt->exception);
3ca3ac4d
AK		 1363}
1364
dde7e6d1 1365static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1366 unsigned int size, unsigned short port,
1367 void *dest)
1368{
9dac77fa 1369 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1370
dde7e6d1 1371 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1372 unsigned int in_page, n;
9dac77fa 1373 unsigned int count = ctxt->rep_prefix ?
dd856efa 1374 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1375 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1376 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1377 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1378 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1379 if (n == 0)
1380 n = 1;
1381 rc->pos = rc->end = 0;
7b105ca2 1382 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1383 return 0;
1384 rc->end = n * size;
6aa8b732
AK		 1385 }
1386
e6e39f04
NA		 1387 if (ctxt->rep_prefix && (ctxt->d & String) &&
1388 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1389 ctxt->dst.data = rc->data + rc->pos;
1390 ctxt->dst.type = OP_MEM_STR;
1391 ctxt->dst.count = (rc->end - rc->pos) / size;
1392 rc->pos = rc->end;
1393 } else {
1394 memcpy(dest, rc->data + rc->pos, size);
1395 rc->pos += size;
1396 }
dde7e6d1
AK		 1397 return 1;
1398}
6aa8b732 1399
7f3d35fd
KW		 1400static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1401 u16 index, struct desc_struct *desc)
1402{
1403 struct desc_ptr dt;
1404 ulong addr;
1405
1406 ctxt->ops->get_idt(ctxt, &dt);
1407
1408 if (dt.size < index * 8 + 7)
1409 return emulate_gp(ctxt, index << 3 | 0x2);
1410
1411 addr = dt.address + index * 8;
1412 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1413 &ctxt->exception);
1414}
1415
dde7e6d1 1416static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1417 u16 selector, struct desc_ptr *dt)
1418{
0225fb50 1419 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1420 u32 base3 = 0;
7b105ca2 1421
dde7e6d1
AK		 1422 if (selector & 1 << 2) {
1423 struct desc_struct desc;
1aa36616
AK		 1424 u16 sel;
1425
dde7e6d1 1426 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1427 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1428 VCPU_SREG_LDTR))
dde7e6d1 1429 return;
e09d082c 1430
dde7e6d1 1431 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1432 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1433 } else
4bff1e86 1434 ops->get_gdt(ctxt, dt);
dde7e6d1 1435}
120df890 1436
dde7e6d1
AK		 1437/* allowed just for 8 bytes segments */
1438static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1439 u16 selector, struct desc_struct *desc,
1440 ulong *desc_addr_p)
dde7e6d1
AK		 1441{
1442 struct desc_ptr dt;
1443 u16 index = selector >> 3;
dde7e6d1 1444 ulong addr;
120df890 1445
7b105ca2 1446 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1447
35d3d4a1
AK		 1448 if (dt.size < index * 8 + 7)
1449 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1450
e919464b 1451 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1452 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1453 &ctxt->exception);
dde7e6d1 1454}
ef65c889 1455
dde7e6d1
AK		 1456/* allowed just for 8 bytes segments */
1457static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1458 u16 selector, struct desc_struct *desc)
1459{
1460 struct desc_ptr dt;
1461 u16 index = selector >> 3;
dde7e6d1 1462 ulong addr;
6aa8b732 1463
7b105ca2 1464 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1465
35d3d4a1
AK		 1466 if (dt.size < index * 8 + 7)
1467 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1468
dde7e6d1 1469 addr = dt.address + index * 8;
7b105ca2
TY		 1470 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1471 &ctxt->exception);
dde7e6d1 1472}
c7e75a3d 1473
5601d05b 1474/* Does not support long mode */
2356aaeb 1475static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1476 u16 selector, int seg, u8 cpl,
1477 bool in_task_switch,
1478 struct desc_struct *desc)
dde7e6d1 1479{
869be99c 1480 struct desc_struct seg_desc, old_desc;
2356aaeb 1481 u8 dpl, rpl;
dde7e6d1
AK		 1482 unsigned err_vec = GP_VECTOR;
1483 u32 err_code = 0;
1484 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1485 ulong desc_addr;
dde7e6d1 1486 int ret;
03ebebeb 1487 u16 dummy;
e37a75a1 1488 u32 base3 = 0;
69f55cb1 1489
dde7e6d1 1490 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1491
f8da94e9
KW		 1492 if (ctxt->mode == X86EMUL_MODE_REAL) {
1493 /* set real mode segment descriptor (keep limit etc. for
1494 * unreal mode) */
03ebebeb 1495 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1496 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1497 goto load;
f8da94e9
KW		 1498 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1499 /* VM86 needs a clean new segment descriptor */
1500 set_desc_base(&seg_desc, selector << 4);
1501 set_desc_limit(&seg_desc, 0xffff);
1502 seg_desc.type = 3;
1503 seg_desc.p = 1;
1504 seg_desc.s = 1;
1505 seg_desc.dpl = 3;
1506 goto load;
dde7e6d1
AK		 1507 }
1508
79d5b4c3 1509 rpl = selector & 3;
79d5b4c3
AK		 1510
1511 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1512 if ((seg == VCPU_SREG_CS
1513 || (seg == VCPU_SREG_SS
1514 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1515 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1516 && null_selector)
1517 goto exception;
1518
1519 /* TR should be in GDT only */
1520 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1521 goto exception;
1522
1523 if (null_selector) /* for NULL selector skip all following checks */
1524 goto load;
1525
e919464b 1526 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1527 if (ret != X86EMUL_CONTINUE)
1528 return ret;
1529
1530 err_code = selector & 0xfffc;
15fc0752 1531 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1532
fc058680 1533 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1534 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1535 goto exception;
1536
1537 if (!seg_desc.p) {
1538 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1539 goto exception;
1540 }
1541
dde7e6d1 1542 dpl = seg_desc.dpl;
dde7e6d1
AK		 1543
1544 switch (seg) {
1545 case VCPU_SREG_SS:
1546 /*
1547 * segment is not a writable data segment or segment
1548 * selector's RPL != CPL or segment selector's RPL != CPL
1549 */
1550 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1551 goto exception;
6aa8b732 1552 break;
dde7e6d1
AK		 1553 case VCPU_SREG_CS:
1554 if (!(seg_desc.type & 8))
1555 goto exception;
1556
1557 if (seg_desc.type & 4) {
1558 /* conforming */
1559 if (dpl > cpl)
1560 goto exception;
1561 } else {
1562 /* nonconforming */
1563 if (rpl > cpl || dpl != cpl)
1564 goto exception;
1565 }
040c8dc8
NA		 1566 /* in long-mode d/b must be clear if l is set */
1567 if (seg_desc.d && seg_desc.l) {
1568 u64 efer = 0;
1569
1570 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1571 if (efer & EFER_LMA)
1572 goto exception;
1573 }
1574
dde7e6d1
AK		 1575 /* CS(RPL) <- CPL */
1576 selector = (selector & 0xfffc) | cpl;
6aa8b732 1577 break;
dde7e6d1
AK		 1578 case VCPU_SREG_TR:
1579 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1580 goto exception;
869be99c
AK		 1581 old_desc = seg_desc;
1582 seg_desc.type |= 2; /* busy */
1583 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1584 sizeof(seg_desc), &ctxt->exception);
1585 if (ret != X86EMUL_CONTINUE)
1586 return ret;
dde7e6d1
AK		 1587 break;
1588 case VCPU_SREG_LDTR:
1589 if (seg_desc.s || seg_desc.type != 2)
1590 goto exception;
1591 break;
1592 default: /* DS, ES, FS, or GS */
4e62417b 1593 /*
dde7e6d1
AK		 1594 * segment is not a data or readable code segment or
1595 * ((segment is a data or nonconforming code segment)
1596 * and (both RPL and CPL > DPL))
4e62417b 1597 */
dde7e6d1
AK		 1598 if ((seg_desc.type & 0xa) == 0x8 ||
1599 (((seg_desc.type & 0xc) != 0xc) &&
1600 (rpl > dpl && cpl > dpl)))
1601 goto exception;
6aa8b732 1602 break;
dde7e6d1
AK		 1603 }
1604
1605 if (seg_desc.s) {
1606 /* mark segment as accessed */
1607 seg_desc.type |= 1;
7b105ca2 1608 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1609 if (ret != X86EMUL_CONTINUE)
1610 return ret;
e37a75a1
NA		 1611 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1612 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1613 sizeof(base3), &ctxt->exception);
1614 if (ret != X86EMUL_CONTINUE)
1615 return ret;
9a9abf6b
NA		 1616 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1617 ((u64)base3 << 32)))
1618 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1619 }
1620load:
e37a75a1 1621 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1622 if (desc)
1623 *desc = seg_desc;
dde7e6d1
AK		 1624 return X86EMUL_CONTINUE;
1625exception:
592f0858 1626 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1627}
1628
2356aaeb
PB		 1629static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1630 u16 selector, int seg)
1631{
1632 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1633 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1634}
1635
31be40b3
WY		 1636static void write_register_operand(struct operand *op)
1637{
1638 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1639 switch (op->bytes) {
1640 case 1:
1641 *(u8 *)op->addr.reg = (u8)op->val;
1642 break;
1643 case 2:
1644 *(u16 *)op->addr.reg = (u16)op->val;
1645 break;
1646 case 4:
1647 *op->addr.reg = (u32)op->val;
1648 break; /* 64b: zero-extend */
1649 case 8:
1650 *op->addr.reg = op->val;
1651 break;
1652 }
1653}
1654
fb32b1ed 1655static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1656{
fb32b1ed 1657 switch (op->type) {
dde7e6d1 1658 case OP_REG:
fb32b1ed 1659 write_register_operand(op);
6aa8b732 1660 break;
dde7e6d1 1661 case OP_MEM:
9dac77fa 1662 if (ctxt->lock_prefix)
f5f87dfb
PB		 1663 return segmented_cmpxchg(ctxt,
1664 op->addr.mem,
1665 &op->orig_val,
1666 &op->val,
1667 op->bytes);
1668 else
1669 return segmented_write(ctxt,
fb32b1ed 1670 op->addr.mem,
fb32b1ed
AK		 1671 &op->val,
1672 op->bytes);
a682e354 1673 break;
b3356bf0 1674 case OP_MEM_STR:
f5f87dfb
PB		 1675 return segmented_write(ctxt,
1676 op->addr.mem,
1677 op->data,
1678 op->bytes * op->count);
b3356bf0 1679 break;
1253791d 1680 case OP_XMM:
fb32b1ed 1681 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1682 break;
cbe2c9d3 1683 case OP_MM:
fb32b1ed 1684 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1685 break;
dde7e6d1
AK		 1686 case OP_NONE:
1687 /* no writeback */
414e6277 1688 break;
dde7e6d1 1689 default:
414e6277 1690 break;
6aa8b732 1691 }
dde7e6d1
AK		 1692 return X86EMUL_CONTINUE;
1693}
6aa8b732 1694
51ddff50 1695static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1696{
4179bb02 1697 struct segmented_address addr;
0dc8d10f 1698
5ad105e5 1699 rsp_increment(ctxt, -bytes);
dd856efa 1700 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1701 addr.seg = VCPU_SREG_SS;
1702
51ddff50
AK		 1703 return segmented_write(ctxt, addr, data, bytes);
1704}
1705
1706static int em_push(struct x86_emulate_ctxt *ctxt)
1707{
4179bb02 1708 /* Disable writeback. */
9dac77fa 1709 ctxt->dst.type = OP_NONE;
51ddff50 1710 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1711}
69f55cb1 1712
dde7e6d1 1713static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1714 void *dest, int len)
1715{
dde7e6d1 1716 int rc;
90de84f5 1717 struct segmented_address addr;
8b4caf66 1718
dd856efa 1719 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1720 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1721 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1722 if (rc != X86EMUL_CONTINUE)
1723 return rc;
1724
5ad105e5 1725 rsp_increment(ctxt, len);
dde7e6d1 1726 return rc;
8b4caf66
LV		 1727}
1728
c54fe504
TY		 1729static int em_pop(struct x86_emulate_ctxt *ctxt)
1730{
9dac77fa 1731 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1732}
1733
dde7e6d1 1734static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1735 void *dest, int len)
9de41573
GN		 1736{
1737 int rc;
dde7e6d1
AK		 1738 unsigned long val, change_mask;
1739 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1740 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1741
3b9be3bf 1742 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1743 if (rc != X86EMUL_CONTINUE)
1744 return rc;
9de41573 1745
dde7e6d1 1746 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1747 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1748
dde7e6d1
AK		 1749 switch(ctxt->mode) {
1750 case X86EMUL_MODE_PROT64:
1751 case X86EMUL_MODE_PROT32:
1752 case X86EMUL_MODE_PROT16:
1753 if (cpl == 0)
1754 change_mask |= EFLG_IOPL;
1755 if (cpl <= iopl)
1756 change_mask |= EFLG_IF;
1757 break;
1758 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1759 if (iopl < 3)
1760 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1761 change_mask |= EFLG_IF;
1762 break;
1763 default: /* real mode */
1764 change_mask |= (EFLG_IOPL | EFLG_IF);
1765 break;
9de41573 1766 }
dde7e6d1
AK		 1767
1768 *(unsigned long *)dest =
1769 (ctxt->eflags & ~change_mask) | (val & change_mask);
1770
1771 return rc;
9de41573
GN		 1772}
1773
62aaa2f0
TY		 1774static int em_popf(struct x86_emulate_ctxt *ctxt)
1775{
9dac77fa
AK		 1776 ctxt->dst.type = OP_REG;
1777 ctxt->dst.addr.reg = &ctxt->eflags;
1778 ctxt->dst.bytes = ctxt->op_bytes;
1779 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1780}
1781
612e89f0
AK		 1782static int em_enter(struct x86_emulate_ctxt *ctxt)
1783{
1784 int rc;
1785 unsigned frame_size = ctxt->src.val;
1786 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1787 ulong rbp;
612e89f0
AK		 1788
1789 if (nesting_level)
1790 return X86EMUL_UNHANDLEABLE;
1791
dd856efa
AK		 1792 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1793 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1794 if (rc != X86EMUL_CONTINUE)
1795 return rc;
dd856efa 1796 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1797 stack_mask(ctxt));
dd856efa
AK		 1798 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1799 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1800 stack_mask(ctxt));
1801 return X86EMUL_CONTINUE;
1802}
1803
f47cfa31
AK		 1804static int em_leave(struct x86_emulate_ctxt *ctxt)
1805{
dd856efa 1806 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1807 stack_mask(ctxt));
dd856efa 1808 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1809}
1810
1cd196ea 1811static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1812{
1cd196ea
AK		 1813 int seg = ctxt->src2.val;
1814
9dac77fa 1815 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1816 if (ctxt->op_bytes == 4) {
1817 rsp_increment(ctxt, -2);
1818 ctxt->op_bytes = 2;
1819 }
7b262e90 1820
4487b3b4 1821 return em_push(ctxt);
7b262e90
GN		 1822}
1823
1cd196ea 1824static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1825{
1cd196ea 1826 int seg = ctxt->src2.val;
dde7e6d1
AK		 1827 unsigned long selector;
1828 int rc;
38ba30ba 1829
9dac77fa 1830 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1831 if (rc != X86EMUL_CONTINUE)
1832 return rc;
1833
a5457e7b
PB		 1834 if (ctxt->modrm_reg == VCPU_SREG_SS)
1835 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1836
7b105ca2 1837 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1838 return rc;
38ba30ba
GN		 1839}
1840
b96a7fad 1841static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1842{
dd856efa 1843 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1844 int rc = X86EMUL_CONTINUE;
1845 int reg = VCPU_REGS_RAX;
38ba30ba 1846
dde7e6d1
AK		 1847 while (reg <= VCPU_REGS_RDI) {
1848 (reg == VCPU_REGS_RSP) ?
dd856efa 1849 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1850
4487b3b4 1851 rc = em_push(ctxt);
dde7e6d1
AK		 1852 if (rc != X86EMUL_CONTINUE)
1853 return rc;
38ba30ba 1854
dde7e6d1 1855 ++reg;
38ba30ba 1856 }
38ba30ba 1857
dde7e6d1 1858 return rc;
38ba30ba
GN		 1859}
1860
62aaa2f0
TY		 1861static int em_pushf(struct x86_emulate_ctxt *ctxt)
1862{
9dac77fa 1863 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1864 return em_push(ctxt);
1865}
1866
b96a7fad 1867static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1868{
dde7e6d1
AK		 1869 int rc = X86EMUL_CONTINUE;
1870 int reg = VCPU_REGS_RDI;
38ba30ba 1871
dde7e6d1
AK		 1872 while (reg >= VCPU_REGS_RAX) {
1873 if (reg == VCPU_REGS_RSP) {
5ad105e5 1874 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1875 --reg;
1876 }
38ba30ba 1877
dd856efa 1878 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1879 if (rc != X86EMUL_CONTINUE)
1880 break;
1881 --reg;
38ba30ba 1882 }
dde7e6d1 1883 return rc;
38ba30ba
GN		 1884}
1885
dd856efa 1886static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1887{
0225fb50 1888 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1889 int rc;
6e154e56
MG		 1890 struct desc_ptr dt;
1891 gva_t cs_addr;
1892 gva_t eip_addr;
1893 u16 cs, eip;
6e154e56
MG		 1894
1895 /* TODO: Add limit checks */
9dac77fa 1896 ctxt->src.val = ctxt->eflags;
4487b3b4 1897 rc = em_push(ctxt);
5c56e1cf
AK		 1898 if (rc != X86EMUL_CONTINUE)
1899 return rc;
6e154e56
MG		 1900
1901 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1902
9dac77fa 1903 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1904 rc = em_push(ctxt);
5c56e1cf
AK		 1905 if (rc != X86EMUL_CONTINUE)
1906 return rc;
6e154e56 1907
9dac77fa 1908 ctxt->src.val = ctxt->_eip;
4487b3b4 1909 rc = em_push(ctxt);
5c56e1cf
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
4bff1e86 1913 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1914
1915 eip_addr = dt.address + (irq << 2);
1916 cs_addr = dt.address + (irq << 2) + 2;
1917
0f65dd70 1918 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1919 if (rc != X86EMUL_CONTINUE)
1920 return rc;
1921
0f65dd70 1922 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1923 if (rc != X86EMUL_CONTINUE)
1924 return rc;
1925
7b105ca2 1926 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1927 if (rc != X86EMUL_CONTINUE)
1928 return rc;
1929
9dac77fa 1930 ctxt->_eip = eip;
6e154e56
MG		 1931
1932 return rc;
1933}
1934
dd856efa
AK		 1935int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1936{
1937 int rc;
1938
1939 invalidate_registers(ctxt);
1940 rc = __emulate_int_real(ctxt, irq);
1941 if (rc == X86EMUL_CONTINUE)
1942 writeback_registers(ctxt);
1943 return rc;
1944}
1945
7b105ca2 1946static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1947{
1948 switch(ctxt->mode) {
1949 case X86EMUL_MODE_REAL:
dd856efa 1950 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1951 case X86EMUL_MODE_VM86:
1952 case X86EMUL_MODE_PROT16:
1953 case X86EMUL_MODE_PROT32:
1954 case X86EMUL_MODE_PROT64:
1955 default:
1956 /* Protected mode interrupts unimplemented yet */
1957 return X86EMUL_UNHANDLEABLE;
1958 }
1959}
1960
7b105ca2 1961static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1962{
dde7e6d1
AK		 1963 int rc = X86EMUL_CONTINUE;
1964 unsigned long temp_eip = 0;
1965 unsigned long temp_eflags = 0;
1966 unsigned long cs = 0;
1967 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1968 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1969 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1970 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1971
dde7e6d1 1972 /* TODO: Add stack limit check */
38ba30ba 1973
9dac77fa 1974 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1975
dde7e6d1
AK		 1976 if (rc != X86EMUL_CONTINUE)
1977 return rc;
38ba30ba 1978
35d3d4a1
AK		 1979 if (temp_eip & ~0xffff)
1980 return emulate_gp(ctxt, 0);
38ba30ba 1981
9dac77fa 1982 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1983
dde7e6d1
AK		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
38ba30ba 1986
9dac77fa 1987 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1988
dde7e6d1
AK		 1989 if (rc != X86EMUL_CONTINUE)
1990 return rc;
38ba30ba 1991
7b105ca2 1992 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1993
dde7e6d1
AK		 1994 if (rc != X86EMUL_CONTINUE)
1995 return rc;
38ba30ba 1996
9dac77fa 1997 ctxt->_eip = temp_eip;
38ba30ba 1998
38ba30ba 1999
9dac77fa 2000 if (ctxt->op_bytes == 4)
dde7e6d1 2001 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2002 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2003 ctxt->eflags &= ~0xffff;
2004 ctxt->eflags |= temp_eflags;
38ba30ba 2005 }
dde7e6d1
AK		 2006
2007 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2008 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2009
2010 return rc;
38ba30ba
GN		 2011}
2012
e01991e7 2013static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2014{
dde7e6d1
AK		 2015 switch(ctxt->mode) {
2016 case X86EMUL_MODE_REAL:
7b105ca2 2017 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2018 case X86EMUL_MODE_VM86:
2019 case X86EMUL_MODE_PROT16:
2020 case X86EMUL_MODE_PROT32:
2021 case X86EMUL_MODE_PROT64:
c37eda13 2022 default:
dde7e6d1
AK		 2023 /* iret from protected mode unimplemented yet */
2024 return X86EMUL_UNHANDLEABLE;
c37eda13 2025 }
c37eda13
WY		 2026}
2027
d2f62766
TY		 2028static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2029{
d2f62766 2030 int rc;
d1442d85
NA		 2031 unsigned short sel, old_sel;
2032 struct desc_struct old_desc, new_desc;
2033 const struct x86_emulate_ops *ops = ctxt->ops;
2034 u8 cpl = ctxt->ops->cpl(ctxt);
2035
2036 /* Assignment of RIP may only fail in 64-bit mode */
2037 if (ctxt->mode == X86EMUL_MODE_PROT64)
2038 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2039 VCPU_SREG_CS);
d2f62766 2040
9dac77fa 2041 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2042
d1442d85
NA		 2043 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2044 &new_desc);
d2f62766
TY		 2045 if (rc != X86EMUL_CONTINUE)
2046 return rc;
2047
d50eaa18 2048 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2049 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2050 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2051 /* assigning eip failed; restore the old cs */
2052 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2053 return rc;
2054 }
2055 return rc;
d2f62766
TY		 2056}
2057
f7784046 2058static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2059{
f7784046
NA		 2060 return assign_eip_near(ctxt, ctxt->src.val);
2061}
8cdbd2c9 2062
f7784046
NA		 2063static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2064{
2065 int rc;
2066 long int old_eip;
2067
2068 old_eip = ctxt->_eip;
2069 rc = assign_eip_near(ctxt, ctxt->src.val);
2070 if (rc != X86EMUL_CONTINUE)
2071 return rc;
2072 ctxt->src.val = old_eip;
2073 rc = em_push(ctxt);
4179bb02 2074 return rc;
8cdbd2c9
LV		 2075}
2076
e0dac408 2077static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2078{
9dac77fa 2079 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2080
aaa05f24
NA		 2081 if (ctxt->dst.bytes == 16)
2082 return X86EMUL_UNHANDLEABLE;
2083
dd856efa
AK		 2084 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2085 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2086 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2087 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2088 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2089 } else {
dd856efa
AK		 2090 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2091 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2092
05f086f8 2093 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2094 }
1b30eaa8 2095 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2096}
2097
ebda02c2
TY		 2098static int em_ret(struct x86_emulate_ctxt *ctxt)
2099{
234f3ce4
NA		 2100 int rc;
2101 unsigned long eip;
2102
2103 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2104 if (rc != X86EMUL_CONTINUE)
2105 return rc;
2106
2107 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2108}
2109
e01991e7 2110static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2111{
a77ab5ea 2112 int rc;
d1442d85
NA		 2113 unsigned long eip, cs;
2114 u16 old_cs;
9e8919ae 2115 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2116 struct desc_struct old_desc, new_desc;
2117 const struct x86_emulate_ops *ops = ctxt->ops;
2118
2119 if (ctxt->mode == X86EMUL_MODE_PROT64)
2120 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2121 VCPU_SREG_CS);
a77ab5ea 2122
d1442d85 2123 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2124 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2125 return rc;
9dac77fa 2126 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2127 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2128 return rc;
9e8919ae
NA		 2129 /* Outer-privilege level return is not implemented */
2130 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2131 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2132 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2133 &new_desc);
2134 if (rc != X86EMUL_CONTINUE)
2135 return rc;
d50eaa18 2136 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2137 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2138 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2139 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2140 }
a77ab5ea
AK		 2141 return rc;
2142}
2143
3261107e
BR		 2144static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2145{
2146 int rc;
2147
2148 rc = em_ret_far(ctxt);
2149 if (rc != X86EMUL_CONTINUE)
2150 return rc;
2151 rsp_increment(ctxt, ctxt->src.val);
2152 return X86EMUL_CONTINUE;
2153}
2154
e940b5c2
TY		 2155static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2156{
2157 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2158 ctxt->dst.orig_val = ctxt->dst.val;
2159 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2160 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2161 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2162 fastop(ctxt, em_cmp);
e940b5c2
TY		 2163
2164 if (ctxt->eflags & EFLG_ZF) {
2165 /* Success: write back to memory. */
2166 ctxt->dst.val = ctxt->src.orig_val;
2167 } else {
2168 /* Failure: write the value we saw to EAX. */
2169 ctxt->dst.type = OP_REG;
dd856efa 2170 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2171 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2172 }
2173 return X86EMUL_CONTINUE;
2174}
2175
d4b4325f 2176static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2177{
d4b4325f 2178 int seg = ctxt->src2.val;
09b5f4d3
WY		 2179 unsigned short sel;
2180 int rc;
2181
9dac77fa 2182 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2183
7b105ca2 2184 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2185 if (rc != X86EMUL_CONTINUE)
2186 return rc;
2187
9dac77fa 2188 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2189 return rc;
2190}
2191
7b105ca2 2192static void
e66bb2cc 2193setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2194 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2195{
e66bb2cc 2196 cs->l = 0; /* will be adjusted later */
79168fd1 2197 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2198 cs->g = 1; /* 4kb granularity */
79168fd1 2199 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2200 cs->type = 0x0b; /* Read, Execute, Accessed */
2201 cs->s = 1;
2202 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2203 cs->p = 1;
2204 cs->d = 1;
99245b50 2205 cs->avl = 0;
e66bb2cc 2206
79168fd1
GN		 2207 set_desc_base(ss, 0); /* flat segment */
2208 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2209 ss->g = 1; /* 4kb granularity */
2210 ss->s = 1;
2211 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2212 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2213 ss->dpl = 0;
79168fd1 2214 ss->p = 1;
99245b50
GN		 2215 ss->l = 0;
2216 ss->avl = 0;
e66bb2cc
AP		 2217}
2218
1a18a69b
AK		 2219static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2220{
2221 u32 eax, ebx, ecx, edx;
2222
2223 eax = ecx = 0;
0017f93a
AK		 2224 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2225 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2226 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2227 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2228}
2229
c2226fc9
SB		 2230static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2231{
0225fb50 2232 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2233 u32 eax, ebx, ecx, edx;
2234
2235 /*
2236 * syscall should always be enabled in longmode - so only become
2237 * vendor specific (cpuid) if other modes are active...
2238 */
2239 if (ctxt->mode == X86EMUL_MODE_PROT64)
2240 return true;
2241
2242 eax = 0x00000000;
2243 ecx = 0x00000000;
0017f93a
AK		 2244 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2245 /*
2246 * Intel ("GenuineIntel")
2247 * remark: Intel CPUs only support "syscall" in 64bit
2248 * longmode. Also an 64bit guest with a
2249 * 32bit compat-app running will #UD !! While this
2250 * behaviour can be fixed (by emulating) into AMD
2251 * response - CPUs of AMD can't behave like Intel.
2252 */
2253 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2254 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2255 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2256 return false;
2257
2258 /* AMD ("AuthenticAMD") */
2259 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2260 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2261 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2262 return true;
2263
2264 /* AMD ("AMDisbetter!") */
2265 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2266 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2267 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2268 return true;
c2226fc9
SB		 2269
2270 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2271 return false;
2272}
2273
e01991e7 2274static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2275{
0225fb50 2276 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2277 struct desc_struct cs, ss;
e66bb2cc 2278 u64 msr_data;
79168fd1 2279 u16 cs_sel, ss_sel;
c2ad2bb3 2280 u64 efer = 0;
e66bb2cc
AP		 2281
2282 /* syscall is not available in real mode */
2e901c4c 2283 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2284 ctxt->mode == X86EMUL_MODE_VM86)
2285 return emulate_ud(ctxt);
e66bb2cc 2286
c2226fc9
SB		 2287 if (!(em_syscall_is_enabled(ctxt)))
2288 return emulate_ud(ctxt);
2289
c2ad2bb3 2290 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2291 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2292
c2226fc9
SB		 2293 if (!(efer & EFER_SCE))
2294 return emulate_ud(ctxt);
2295
717746e3 2296 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2297 msr_data >>= 32;
79168fd1
GN		 2298 cs_sel = (u16)(msr_data & 0xfffc);
2299 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2300
c2ad2bb3 2301 if (efer & EFER_LMA) {
79168fd1 2302 cs.d = 0;
e66bb2cc
AP		 2303 cs.l = 1;
2304 }
1aa36616
AK		 2305 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2306 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2307
dd856efa 2308 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2309 if (efer & EFER_LMA) {
e66bb2cc 2310#ifdef CONFIG_X86_64
6c6cb69b 2311 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2312
717746e3 2313 ops->get_msr(ctxt,
3fb1b5db
GN		 2314 ctxt->mode == X86EMUL_MODE_PROT64 ?
2315 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2316 ctxt->_eip = msr_data;
e66bb2cc 2317
717746e3 2318 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2319 ctxt->eflags &= ~msr_data;
807c1425 2320 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2321#endif
2322 } else {
2323 /* legacy mode */
717746e3 2324 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2325 ctxt->_eip = (u32)msr_data;
e66bb2cc 2326
6c6cb69b 2327 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2328 }
2329
e54cfa97 2330 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2331}
2332
e01991e7 2333static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2334{
0225fb50 2335 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2336 struct desc_struct cs, ss;
8c604352 2337 u64 msr_data;
79168fd1 2338 u16 cs_sel, ss_sel;
c2ad2bb3 2339 u64 efer = 0;
8c604352 2340
7b105ca2 2341 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2342 /* inject #GP if in real mode */
35d3d4a1
AK		 2343 if (ctxt->mode == X86EMUL_MODE_REAL)
2344 return emulate_gp(ctxt, 0);
8c604352 2345
1a18a69b
AK		 2346 /*
2347 * Not recognized on AMD in compat mode (but is recognized in legacy
2348 * mode).
2349 */
2350 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2351 && !vendor_intel(ctxt))
2352 return emulate_ud(ctxt);
2353
b2c9d43e 2354 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2355 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2356 return X86EMUL_UNHANDLEABLE;
8c604352 2357
7b105ca2 2358 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2359
717746e3 2360 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2361 switch (ctxt->mode) {
2362 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2363 if ((msr_data & 0xfffc) == 0x0)
2364 return emulate_gp(ctxt, 0);
8c604352
AP		 2365 break;
2366 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2367 if (msr_data == 0x0)
2368 return emulate_gp(ctxt, 0);
8c604352 2369 break;
9d1b39a9
GN		 2370 default:
2371 break;
8c604352
AP		 2372 }
2373
6c6cb69b 2374 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2375 cs_sel = (u16)msr_data;
2376 cs_sel &= ~SELECTOR_RPL_MASK;
2377 ss_sel = cs_sel + 8;
2378 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2379 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2380 cs.d = 0;
8c604352
AP		 2381 cs.l = 1;
2382 }
2383
1aa36616
AK		 2384 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2385 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2386
717746e3 2387 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2388 ctxt->_eip = msr_data;
8c604352 2389
717746e3 2390 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2391 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2392
e54cfa97 2393 return X86EMUL_CONTINUE;
8c604352
AP		 2394}
2395
e01991e7 2396static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2397{
0225fb50 2398 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2399 struct desc_struct cs, ss;
234f3ce4 2400 u64 msr_data, rcx, rdx;
4668f050 2401 int usermode;
1249b96e 2402 u16 cs_sel = 0, ss_sel = 0;
4668f050 2403
a0044755
GN		 2404 /* inject #GP if in real mode or Virtual 8086 mode */
2405 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2406 ctxt->mode == X86EMUL_MODE_VM86)
2407 return emulate_gp(ctxt, 0);
4668f050 2408
7b105ca2 2409 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2410
9dac77fa 2411 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2412 usermode = X86EMUL_MODE_PROT64;
2413 else
2414 usermode = X86EMUL_MODE_PROT32;
2415
234f3ce4
NA		 2416 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2417 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2418
4668f050
AP		 2419 cs.dpl = 3;
2420 ss.dpl = 3;
717746e3 2421 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2422 switch (usermode) {
2423 case X86EMUL_MODE_PROT32:
79168fd1 2424 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2425 if ((msr_data & 0xfffc) == 0x0)
2426 return emulate_gp(ctxt, 0);
79168fd1 2427 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2428 rcx = (u32)rcx;
2429 rdx = (u32)rdx;
4668f050
AP		 2430 break;
2431 case X86EMUL_MODE_PROT64:
79168fd1 2432 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2433 if (msr_data == 0x0)
2434 return emulate_gp(ctxt, 0);
79168fd1
GN		 2435 ss_sel = cs_sel + 8;
2436 cs.d = 0;
4668f050 2437 cs.l = 1;
234f3ce4
NA		 2438 if (is_noncanonical_address(rcx) ||
2439 is_noncanonical_address(rdx))
2440 return emulate_gp(ctxt, 0);
4668f050
AP		 2441 break;
2442 }
79168fd1
GN		 2443 cs_sel |= SELECTOR_RPL_MASK;
2444 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2445
1aa36616
AK		 2446 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2447 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2448
234f3ce4
NA		 2449 ctxt->_eip = rdx;
2450 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2451
e54cfa97 2452 return X86EMUL_CONTINUE;
4668f050
AP		 2453}
2454
7b105ca2 2455static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2456{
2457 int iopl;
2458 if (ctxt->mode == X86EMUL_MODE_REAL)
2459 return false;
2460 if (ctxt->mode == X86EMUL_MODE_VM86)
2461 return true;
2462 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2463 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2464}
2465
2466static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2467 u16 port, u16 len)
2468{
0225fb50 2469 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2470 struct desc_struct tr_seg;
5601d05b 2471 u32 base3;
f850e2e6 2472 int r;
1aa36616 2473 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2474 unsigned mask = (1 << len) - 1;
5601d05b 2475 unsigned long base;
f850e2e6 2476
1aa36616 2477 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2478 if (!tr_seg.p)
f850e2e6 2479 return false;
79168fd1 2480 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2481 return false;
5601d05b
GN		 2482 base = get_desc_base(&tr_seg);
2483#ifdef CONFIG_X86_64
2484 base |= ((u64)base3) << 32;
2485#endif
0f65dd70 2486 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2487 if (r != X86EMUL_CONTINUE)
2488 return false;
79168fd1 2489 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2490 return false;
0f65dd70 2491 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2492 if (r != X86EMUL_CONTINUE)
2493 return false;
2494 if ((perm >> bit_idx) & mask)
2495 return false;
2496 return true;
2497}
2498
2499static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2500 u16 port, u16 len)
2501{
4fc40f07
GN		 2502 if (ctxt->perm_ok)
2503 return true;
2504
7b105ca2
TY		 2505 if (emulator_bad_iopl(ctxt))
2506 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2507 return false;
4fc40f07
GN		 2508
2509 ctxt->perm_ok = true;
2510
f850e2e6
GN		 2511 return true;
2512}
2513
38ba30ba 2514static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2515 struct tss_segment_16 *tss)
2516{
9dac77fa 2517 tss->ip = ctxt->_eip;
38ba30ba 2518 tss->flag = ctxt->eflags;
dd856efa
AK		 2519 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2520 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2521 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2522 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2523 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2524 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2525 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2526 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2527
1aa36616
AK		 2528 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2529 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2530 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2531 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2532 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2533}
2534
2535static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2536 struct tss_segment_16 *tss)
2537{
38ba30ba 2538 int ret;
2356aaeb 2539 u8 cpl;
38ba30ba 2540
9dac77fa 2541 ctxt->_eip = tss->ip;
38ba30ba 2542 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2543 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2544 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2545 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2546 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2547 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2548 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2549 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2550 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2551
2552 /*
2553 * SDM says that segment selectors are loaded before segment
2554 * descriptors
2555 */
1aa36616
AK		 2556 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2557 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2558 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2559 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2560 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2561
2356aaeb
PB		 2562 cpl = tss->cs & 3;
2563
38ba30ba 2564 /*
fc058680 2565 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2566 * it is handled in a context of new task
2567 */
d1442d85
NA		 2568 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2569 true, NULL);
38ba30ba
GN		 2570 if (ret != X86EMUL_CONTINUE)
2571 return ret;
d1442d85
NA		 2572 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2573 true, NULL);
38ba30ba
GN		 2574 if (ret != X86EMUL_CONTINUE)
2575 return ret;
d1442d85
NA		 2576 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2577 true, NULL);
38ba30ba
GN		 2578 if (ret != X86EMUL_CONTINUE)
2579 return ret;
d1442d85
NA		 2580 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2581 true, NULL);
38ba30ba
GN		 2582 if (ret != X86EMUL_CONTINUE)
2583 return ret;
d1442d85
NA		 2584 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2585 true, NULL);
38ba30ba
GN		 2586 if (ret != X86EMUL_CONTINUE)
2587 return ret;
2588
2589 return X86EMUL_CONTINUE;
2590}
2591
2592static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2593 u16 tss_selector, u16 old_tss_sel,
2594 ulong old_tss_base, struct desc_struct *new_desc)
2595{
0225fb50 2596 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2597 struct tss_segment_16 tss_seg;
2598 int ret;
bcc55cba 2599 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2600
0f65dd70 2601 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2602 &ctxt->exception);
db297e3d 2603 if (ret != X86EMUL_CONTINUE)
38ba30ba 2604 /* FIXME: need to provide precise fault address */
38ba30ba 2605 return ret;
38ba30ba 2606
7b105ca2 2607 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2608
0f65dd70 2609 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2610 &ctxt->exception);
db297e3d 2611 if (ret != X86EMUL_CONTINUE)
38ba30ba 2612 /* FIXME: need to provide precise fault address */
38ba30ba 2613 return ret;
38ba30ba 2614
0f65dd70 2615 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2616 &ctxt->exception);
db297e3d 2617 if (ret != X86EMUL_CONTINUE)
38ba30ba 2618 /* FIXME: need to provide precise fault address */
38ba30ba 2619 return ret;
38ba30ba
GN		 2620
2621 if (old_tss_sel != 0xffff) {
2622 tss_seg.prev_task_link = old_tss_sel;
2623
0f65dd70 2624 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2625 &tss_seg.prev_task_link,
2626 sizeof tss_seg.prev_task_link,
0f65dd70 2627 &ctxt->exception);
db297e3d 2628 if (ret != X86EMUL_CONTINUE)
38ba30ba 2629 /* FIXME: need to provide precise fault address */
38ba30ba 2630 return ret;
38ba30ba
GN		 2631 }
2632
7b105ca2 2633 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2634}
2635
2636static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2637 struct tss_segment_32 *tss)
2638{
5c7411e2 2639 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2640 tss->eip = ctxt->_eip;
38ba30ba 2641 tss->eflags = ctxt->eflags;
dd856efa
AK		 2642 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2643 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2644 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2645 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2646 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2647 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2648 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2649 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2650
1aa36616
AK		 2651 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2652 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2653 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2654 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2655 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2656 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2657}
2658
2659static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2660 struct tss_segment_32 *tss)
2661{
38ba30ba 2662 int ret;
2356aaeb 2663 u8 cpl;
38ba30ba 2664
7b105ca2 2665 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2666 return emulate_gp(ctxt, 0);
9dac77fa 2667 ctxt->_eip = tss->eip;
38ba30ba 2668 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2669
2670 /* General purpose registers */
dd856efa
AK		 2671 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2672 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2673 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2674 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2675 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2676 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2677 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2678 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2679
2680 /*
2681 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2682 * descriptors. This is important because CPL checks will
2683 * use CS.RPL.
38ba30ba 2684 */
1aa36616
AK		 2685 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2686 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2687 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2688 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2689 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2690 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2691 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2692
4cee4798
KW		 2693 /*
2694 * If we're switching between Protected Mode and VM86, we need to make
2695 * sure to update the mode before loading the segment descriptors so
2696 * that the selectors are interpreted correctly.
4cee4798 2697 */
2356aaeb 2698 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2699 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2700 cpl = 3;
2701 } else {
4cee4798 2702 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2703 cpl = tss->cs & 3;
2704 }
4cee4798 2705
38ba30ba
GN		 2706 /*
2707 * Now load segment descriptors. If fault happenes at this stage
2708 * it is handled in a context of new task
2709 */
d1442d85
NA		 2710 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2711 cpl, true, NULL);
38ba30ba
GN		 2712 if (ret != X86EMUL_CONTINUE)
2713 return ret;
d1442d85
NA		 2714 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2715 true, NULL);
38ba30ba
GN		 2716 if (ret != X86EMUL_CONTINUE)
2717 return ret;
d1442d85
NA		 2718 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2719 true, NULL);
38ba30ba
GN		 2720 if (ret != X86EMUL_CONTINUE)
2721 return ret;
d1442d85
NA		 2722 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2723 true, NULL);
38ba30ba
GN		 2724 if (ret != X86EMUL_CONTINUE)
2725 return ret;
d1442d85
NA		 2726 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2727 true, NULL);
38ba30ba
GN		 2728 if (ret != X86EMUL_CONTINUE)
2729 return ret;
d1442d85
NA		 2730 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2731 true, NULL);
38ba30ba
GN		 2732 if (ret != X86EMUL_CONTINUE)
2733 return ret;
d1442d85
NA		 2734 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2735 true, NULL);
38ba30ba
GN		 2736 if (ret != X86EMUL_CONTINUE)
2737 return ret;
2738
2739 return X86EMUL_CONTINUE;
2740}
2741
2742static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2743 u16 tss_selector, u16 old_tss_sel,
2744 ulong old_tss_base, struct desc_struct *new_desc)
2745{
0225fb50 2746 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2747 struct tss_segment_32 tss_seg;
2748 int ret;
bcc55cba 2749 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2750 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2751 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2752
0f65dd70 2753 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2754 &ctxt->exception);
db297e3d 2755 if (ret != X86EMUL_CONTINUE)
38ba30ba 2756 /* FIXME: need to provide precise fault address */
38ba30ba 2757 return ret;
38ba30ba 2758
7b105ca2 2759 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2760
5c7411e2
NA		 2761 /* Only GP registers and segment selectors are saved */
2762 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2763 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2764 if (ret != X86EMUL_CONTINUE)
38ba30ba 2765 /* FIXME: need to provide precise fault address */
38ba30ba 2766 return ret;
38ba30ba 2767
0f65dd70 2768 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2769 &ctxt->exception);
db297e3d 2770 if (ret != X86EMUL_CONTINUE)
38ba30ba 2771 /* FIXME: need to provide precise fault address */
38ba30ba 2772 return ret;
38ba30ba
GN		 2773
2774 if (old_tss_sel != 0xffff) {
2775 tss_seg.prev_task_link = old_tss_sel;
2776
0f65dd70 2777 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2778 &tss_seg.prev_task_link,
2779 sizeof tss_seg.prev_task_link,
0f65dd70 2780 &ctxt->exception);
db297e3d 2781 if (ret != X86EMUL_CONTINUE)
38ba30ba 2782 /* FIXME: need to provide precise fault address */
38ba30ba 2783 return ret;
38ba30ba
GN		 2784 }
2785
7b105ca2 2786 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2787}
2788
2789static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2790 u16 tss_selector, int idt_index, int reason,
e269fb21 2791 bool has_error_code, u32 error_code)
38ba30ba 2792{
0225fb50 2793 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2794 struct desc_struct curr_tss_desc, next_tss_desc;
2795 int ret;
1aa36616 2796 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2797 ulong old_tss_base =
4bff1e86 2798 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2799 u32 desc_limit;
e919464b 2800 ulong desc_addr;
38ba30ba
GN		 2801
2802 /* FIXME: old_tss_base == ~0 ? */
2803
e919464b 2804 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2805 if (ret != X86EMUL_CONTINUE)
2806 return ret;
e919464b 2807 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2808 if (ret != X86EMUL_CONTINUE)
2809 return ret;
2810
2811 /* FIXME: check that next_tss_desc is tss */
2812
7f3d35fd
KW		 2813 /*
2814 * Check privileges. The three cases are task switch caused by...
2815 *
2816 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2817 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2818 * 3. jmp/call to TSS/task-gate: No check is performed since the
2819 * hardware checks it before exiting.
7f3d35fd
KW		 2820 */
2821 if (reason == TASK_SWITCH_GATE) {
2822 if (idt_index != -1) {
2823 /* Software interrupts */
2824 struct desc_struct task_gate_desc;
2825 int dpl;
2826
2827 ret = read_interrupt_descriptor(ctxt, idt_index,
2828 &task_gate_desc);
2829 if (ret != X86EMUL_CONTINUE)
2830 return ret;
2831
2832 dpl = task_gate_desc.dpl;
2833 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2834 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2835 }
38ba30ba
GN		 2836 }
2837
ceffb459
GN		 2838 desc_limit = desc_limit_scaled(&next_tss_desc);
2839 if (!next_tss_desc.p ||
2840 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2841 desc_limit < 0x2b)) {
592f0858 2842 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2843 }
2844
2845 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2846 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2847 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2848 }
2849
2850 if (reason == TASK_SWITCH_IRET)
2851 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2852
2853 /* set back link to prev task only if NT bit is set in eflags
fc058680 2854 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2855 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2856 old_tss_sel = 0xffff;
2857
2858 if (next_tss_desc.type & 8)
7b105ca2 2859 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2860 old_tss_base, &next_tss_desc);
2861 else
7b105ca2 2862 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2863 old_tss_base, &next_tss_desc);
0760d448
JK		 2864 if (ret != X86EMUL_CONTINUE)
2865 return ret;
38ba30ba
GN		 2866
2867 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2868 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2869
2870 if (reason != TASK_SWITCH_IRET) {
2871 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2872 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2873 }
2874
717746e3 2875 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2876 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2877
e269fb21 2878 if (has_error_code) {
9dac77fa
AK		 2879 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2880 ctxt->lock_prefix = 0;
2881 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2882 ret = em_push(ctxt);
e269fb21
JK		 2883 }
2884
38ba30ba
GN		 2885 return ret;
2886}
2887
2888int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2889 u16 tss_selector, int idt_index, int reason,
e269fb21 2890 bool has_error_code, u32 error_code)
38ba30ba 2891{
38ba30ba
GN		 2892 int rc;
2893
dd856efa 2894 invalidate_registers(ctxt);
9dac77fa
AK		 2895 ctxt->_eip = ctxt->eip;
2896 ctxt->dst.type = OP_NONE;
38ba30ba 2897
7f3d35fd 2898 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2899 has_error_code, error_code);
38ba30ba 2900
dd856efa 2901 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2902 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2903 writeback_registers(ctxt);
2904 }
38ba30ba 2905
a0c0ab2f 2906 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2907}
2908
f3bd64c6
GN		 2909static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2910 struct operand *op)
a682e354 2911{
b3356bf0 2912 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2913
dd856efa
AK		 2914 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2915 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2916}
2917
7af04fc0
AK		 2918static int em_das(struct x86_emulate_ctxt *ctxt)
2919{
7af04fc0
AK		 2920 u8 al, old_al;
2921 bool af, cf, old_cf;
2922
2923 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2924 al = ctxt->dst.val;
7af04fc0
AK		 2925
2926 old_al = al;
2927 old_cf = cf;
2928 cf = false;
2929 af = ctxt->eflags & X86_EFLAGS_AF;
2930 if ((al & 0x0f) > 9 || af) {
2931 al -= 6;
2932 cf = old_cf | (al >= 250);
2933 af = true;
2934 } else {
2935 af = false;
2936 }
2937 if (old_al > 0x99 || old_cf) {
2938 al -= 0x60;
2939 cf = true;
2940 }
2941
9dac77fa 2942 ctxt->dst.val = al;
7af04fc0 2943 /* Set PF, ZF, SF */
9dac77fa
AK		 2944 ctxt->src.type = OP_IMM;
2945 ctxt->src.val = 0;
2946 ctxt->src.bytes = 1;
158de57f 2947 fastop(ctxt, em_or);
7af04fc0
AK		 2948 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2949 if (cf)
2950 ctxt->eflags |= X86_EFLAGS_CF;
2951 if (af)
2952 ctxt->eflags |= X86_EFLAGS_AF;
2953 return X86EMUL_CONTINUE;
2954}
2955
a035d5c6
PB		 2956static int em_aam(struct x86_emulate_ctxt *ctxt)
2957{
2958 u8 al, ah;
2959
2960 if (ctxt->src.val == 0)
2961 return emulate_de(ctxt);
2962
2963 al = ctxt->dst.val & 0xff;
2964 ah = al / ctxt->src.val;
2965 al %= ctxt->src.val;
2966
2967 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2968
2969 /* Set PF, ZF, SF */
2970 ctxt->src.type = OP_IMM;
2971 ctxt->src.val = 0;
2972 ctxt->src.bytes = 1;
2973 fastop(ctxt, em_or);
2974
2975 return X86EMUL_CONTINUE;
2976}
2977
7f662273
GN		 2978static int em_aad(struct x86_emulate_ctxt *ctxt)
2979{
2980 u8 al = ctxt->dst.val & 0xff;
2981 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2982
2983 al = (al + (ah * ctxt->src.val)) & 0xff;
2984
2985 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2986
f583c29b
GN		 2987 /* Set PF, ZF, SF */
2988 ctxt->src.type = OP_IMM;
2989 ctxt->src.val = 0;
2990 ctxt->src.bytes = 1;
2991 fastop(ctxt, em_or);
7f662273
GN		 2992
2993 return X86EMUL_CONTINUE;
2994}
2995
d4ddafcd
TY		 2996static int em_call(struct x86_emulate_ctxt *ctxt)
2997{
234f3ce4 2998 int rc;
d4ddafcd
TY		 2999 long rel = ctxt->src.val;
3000
3001 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3002 rc = jmp_rel(ctxt, rel);
3003 if (rc != X86EMUL_CONTINUE)
3004 return rc;
d4ddafcd
TY		 3005 return em_push(ctxt);
3006}
3007
0ef753b8
AK		 3008static int em_call_far(struct x86_emulate_ctxt *ctxt)
3009{
0ef753b8
AK		 3010 u16 sel, old_cs;
3011 ulong old_eip;
3012 int rc;
d1442d85
NA		 3013 struct desc_struct old_desc, new_desc;
3014 const struct x86_emulate_ops *ops = ctxt->ops;
3015 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3016
9dac77fa 3017 old_eip = ctxt->_eip;
d1442d85 3018 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3019
9dac77fa 3020 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3021 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3022 &new_desc);
3023 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3024 return X86EMUL_CONTINUE;
3025
d50eaa18 3026 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3027 if (rc != X86EMUL_CONTINUE)
3028 goto fail;
0ef753b8 3029
9dac77fa 3030 ctxt->src.val = old_cs;
4487b3b4 3031 rc = em_push(ctxt);
0ef753b8 3032 if (rc != X86EMUL_CONTINUE)
d1442d85 3033 goto fail;
0ef753b8 3034
9dac77fa 3035 ctxt->src.val = old_eip;
d1442d85
NA		 3036 rc = em_push(ctxt);
3037 /* If we failed, we tainted the memory, but the very least we should
3038 restore cs */
3039 if (rc != X86EMUL_CONTINUE)
3040 goto fail;
3041 return rc;
3042fail:
3043 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3044 return rc;
3045
0ef753b8
AK		 3046}
3047
40ece7c7
AK		 3048static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3049{
40ece7c7 3050 int rc;
234f3ce4 3051 unsigned long eip;
40ece7c7 3052
234f3ce4
NA		 3053 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3054 if (rc != X86EMUL_CONTINUE)
3055 return rc;
3056 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3057 if (rc != X86EMUL_CONTINUE)
3058 return rc;
5ad105e5 3059 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3060 return X86EMUL_CONTINUE;
3061}
3062
e4f973ae
TY		 3063static int em_xchg(struct x86_emulate_ctxt *ctxt)
3064{
e4f973ae 3065 /* Write back the register source. */
9dac77fa
AK		 3066 ctxt->src.val = ctxt->dst.val;
3067 write_register_operand(&ctxt->src);
e4f973ae
TY		 3068
3069 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3070 ctxt->dst.val = ctxt->src.orig_val;
3071 ctxt->lock_prefix = 1;
e4f973ae
TY		 3072 return X86EMUL_CONTINUE;
3073}
3074
5c82aa29
AK		 3075static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3076{
9dac77fa 3077 ctxt->dst.val = ctxt->src2.val;
4d758349 3078 return fastop(ctxt, em_imul);
5c82aa29
AK		 3079}
3080
61429142
AK		 3081static int em_cwd(struct x86_emulate_ctxt *ctxt)
3082{
9dac77fa
AK		 3083 ctxt->dst.type = OP_REG;
3084 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3085 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3086 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3087
3088 return X86EMUL_CONTINUE;
3089}
3090
48bb5d3c
AK		 3091static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3092{
48bb5d3c
AK		 3093 u64 tsc = 0;
3094
717746e3 3095 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3096 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3097 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3098 return X86EMUL_CONTINUE;
3099}
3100
222d21aa
AK		 3101static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3102{
3103 u64 pmc;
3104
dd856efa 3105 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3106 return emulate_gp(ctxt, 0);
dd856efa
AK		 3107 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3108 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3109 return X86EMUL_CONTINUE;
3110}
3111
b9eac5f4
AK		 3112static int em_mov(struct x86_emulate_ctxt *ctxt)
3113{
54cfdb3e 3114 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3115 return X86EMUL_CONTINUE;
3116}
3117
84cffe49
BP		 3118#define FFL(x) bit(X86_FEATURE_##x)
3119
3120static int em_movbe(struct x86_emulate_ctxt *ctxt)
3121{
3122 u32 ebx, ecx, edx, eax = 1;
3123 u16 tmp;
3124
3125 /*
3126 * Check MOVBE is set in the guest-visible CPUID leaf.
3127 */
3128 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3129 if (!(ecx & FFL(MOVBE)))
3130 return emulate_ud(ctxt);
3131
3132 switch (ctxt->op_bytes) {
3133 case 2:
3134 /*
3135 * From MOVBE definition: "...When the operand size is 16 bits,
3136 * the upper word of the destination register remains unchanged
3137 * ..."
3138 *
3139 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3140 * rules so we have to do the operation almost per hand.
3141 */
3142 tmp = (u16)ctxt->src.val;
3143 ctxt->dst.val &= ~0xffffUL;
3144 ctxt->dst.val |= (unsigned long)swab16(tmp);
3145 break;
3146 case 4:
3147 ctxt->dst.val = swab32((u32)ctxt->src.val);
3148 break;
3149 case 8:
3150 ctxt->dst.val = swab64(ctxt->src.val);
3151 break;
3152 default:
592f0858 3153 BUG();
84cffe49
BP		 3154 }
3155 return X86EMUL_CONTINUE;
3156}
3157
bc00f8d2
TY		 3158static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3159{
3160 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3161 return emulate_gp(ctxt, 0);
3162
3163 /* Disable writeback. */
3164 ctxt->dst.type = OP_NONE;
3165 return X86EMUL_CONTINUE;
3166}
3167
3168static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3169{
3170 unsigned long val;
3171
3172 if (ctxt->mode == X86EMUL_MODE_PROT64)
3173 val = ctxt->src.val & ~0ULL;
3174 else
3175 val = ctxt->src.val & ~0U;
3176
3177 /* #UD condition is already handled. */
3178 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3179 return emulate_gp(ctxt, 0);
3180
3181 /* Disable writeback. */
3182 ctxt->dst.type = OP_NONE;
3183 return X86EMUL_CONTINUE;
3184}
3185
e1e210b0
TY		 3186static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3187{
3188 u64 msr_data;
3189
dd856efa
AK		 3190 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3191 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3192 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3193 return emulate_gp(ctxt, 0);
3194
3195 return X86EMUL_CONTINUE;
3196}
3197
3198static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3199{
3200 u64 msr_data;
3201
dd856efa 3202 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3203 return emulate_gp(ctxt, 0);
3204
dd856efa
AK		 3205 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3206 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3207 return X86EMUL_CONTINUE;
3208}
3209
1bd5f469
TY		 3210static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3211{
9dac77fa 3212 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3213 return emulate_ud(ctxt);
3214
9dac77fa 3215 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3216 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3217 ctxt->dst.bytes = 2;
1bd5f469
TY		 3218 return X86EMUL_CONTINUE;
3219}
3220
3221static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3222{
9dac77fa 3223 u16 sel = ctxt->src.val;
1bd5f469 3224
9dac77fa 3225 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3226 return emulate_ud(ctxt);
3227
9dac77fa 3228 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3229 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3230
3231 /* Disable writeback. */
9dac77fa
AK		 3232 ctxt->dst.type = OP_NONE;
3233 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3234}
3235
a14e579f
AK		 3236static int em_lldt(struct x86_emulate_ctxt *ctxt)
3237{
3238 u16 sel = ctxt->src.val;
3239
3240 /* Disable writeback. */
3241 ctxt->dst.type = OP_NONE;
3242 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3243}
3244
80890006
AK		 3245static int em_ltr(struct x86_emulate_ctxt *ctxt)
3246{
3247 u16 sel = ctxt->src.val;
3248
3249 /* Disable writeback. */
3250 ctxt->dst.type = OP_NONE;
3251 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3252}
3253
38503911
AK		 3254static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3255{
9fa088f4
AK		 3256 int rc;
3257 ulong linear;
3258
9dac77fa 3259 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3260 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3261 ctxt->ops->invlpg(ctxt, linear);
38503911 3262 /* Disable writeback. */
9dac77fa 3263 ctxt->dst.type = OP_NONE;
38503911
AK		 3264 return X86EMUL_CONTINUE;
3265}
3266
2d04a05b
AK		 3267static int em_clts(struct x86_emulate_ctxt *ctxt)
3268{
3269 ulong cr0;
3270
3271 cr0 = ctxt->ops->get_cr(ctxt, 0);
3272 cr0 &= ~X86_CR0_TS;
3273 ctxt->ops->set_cr(ctxt, 0, cr0);
3274 return X86EMUL_CONTINUE;
3275}
3276
26d05cc7
AK		 3277static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3278{
0f54a321 3279 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3280
26d05cc7
AK		 3281 if (rc != X86EMUL_CONTINUE)
3282 return rc;
3283
3284 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3285 ctxt->_eip = ctxt->eip;
26d05cc7 3286 /* Disable writeback. */
9dac77fa 3287 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3288 return X86EMUL_CONTINUE;
3289}
3290
96051572
AK		 3291static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3292 void (*get)(struct x86_emulate_ctxt *ctxt,
3293 struct desc_ptr *ptr))
3294{
3295 struct desc_ptr desc_ptr;
3296
3297 if (ctxt->mode == X86EMUL_MODE_PROT64)
3298 ctxt->op_bytes = 8;
3299 get(ctxt, &desc_ptr);
3300 if (ctxt->op_bytes == 2) {
3301 ctxt->op_bytes = 4;
3302 desc_ptr.address &= 0x00ffffff;
3303 }
3304 /* Disable writeback. */
3305 ctxt->dst.type = OP_NONE;
3306 return segmented_write(ctxt, ctxt->dst.addr.mem,
3307 &desc_ptr, 2 + ctxt->op_bytes);
3308}
3309
3310static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3311{
3312 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3313}
3314
3315static int em_sidt(struct x86_emulate_ctxt *ctxt)
3316{
3317 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3318}
3319
5b7f6a1e 3320static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3321{
26d05cc7
AK		 3322 struct desc_ptr desc_ptr;
3323 int rc;
3324
510425ff
AK		 3325 if (ctxt->mode == X86EMUL_MODE_PROT64)
3326 ctxt->op_bytes = 8;
9dac77fa 3327 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3328 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3329 ctxt->op_bytes);
26d05cc7
AK		 3330 if (rc != X86EMUL_CONTINUE)
3331 return rc;
9a9abf6b
NA		 3332 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3333 is_noncanonical_address(desc_ptr.address))
3334 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3335 if (lgdt)
3336 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3337 else
3338 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3339 /* Disable writeback. */
9dac77fa 3340 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3341 return X86EMUL_CONTINUE;
3342}
3343
5b7f6a1e
NA		 3344static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3345{
3346 return em_lgdt_lidt(ctxt, true);
3347}
3348
5ef39c71 3349static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3350{
26d05cc7
AK		 3351 int rc;
3352
5ef39c71
AK		 3353 rc = ctxt->ops->fix_hypercall(ctxt);
3354
26d05cc7 3355 /* Disable writeback. */
9dac77fa 3356 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3357 return rc;
3358}
3359
3360static int em_lidt(struct x86_emulate_ctxt *ctxt)
3361{
5b7f6a1e 3362 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3363}
3364
3365static int em_smsw(struct x86_emulate_ctxt *ctxt)
3366{
32e94d06
NA		 3367 if (ctxt->dst.type == OP_MEM)
3368 ctxt->dst.bytes = 2;
9dac77fa 3369 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3370 return X86EMUL_CONTINUE;
3371}
3372
3373static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3374{
26d05cc7 3375 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3376 | (ctxt->src.val & 0x0f));
3377 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3378 return X86EMUL_CONTINUE;
3379}
3380
d06e03ad
TY		 3381static int em_loop(struct x86_emulate_ctxt *ctxt)
3382{
234f3ce4
NA		 3383 int rc = X86EMUL_CONTINUE;
3384
dd856efa
AK		 3385 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3386 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3387 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3388 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3389
234f3ce4 3390 return rc;
d06e03ad
TY		 3391}
3392
3393static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3394{
234f3ce4
NA		 3395 int rc = X86EMUL_CONTINUE;
3396
dd856efa 3397 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3398 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3399
234f3ce4 3400 return rc;
d06e03ad
TY		 3401}
3402
d7841a4b
TY		 3403static int em_in(struct x86_emulate_ctxt *ctxt)
3404{
3405 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3406 &ctxt->dst.val))
3407 return X86EMUL_IO_NEEDED;
3408
3409 return X86EMUL_CONTINUE;
3410}
3411
3412static int em_out(struct x86_emulate_ctxt *ctxt)
3413{
3414 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3415 &ctxt->src.val, 1);
3416 /* Disable writeback. */
3417 ctxt->dst.type = OP_NONE;
3418 return X86EMUL_CONTINUE;
3419}
3420
f411e6cd
TY		 3421static int em_cli(struct x86_emulate_ctxt *ctxt)
3422{
3423 if (emulator_bad_iopl(ctxt))
3424 return emulate_gp(ctxt, 0);
3425
3426 ctxt->eflags &= ~X86_EFLAGS_IF;
3427 return X86EMUL_CONTINUE;
3428}
3429
3430static int em_sti(struct x86_emulate_ctxt *ctxt)
3431{
3432 if (emulator_bad_iopl(ctxt))
3433 return emulate_gp(ctxt, 0);
3434
3435 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3436 ctxt->eflags |= X86_EFLAGS_IF;
3437 return X86EMUL_CONTINUE;
3438}
3439
6d6eede4
AK		 3440static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3441{
3442 u32 eax, ebx, ecx, edx;
3443
dd856efa
AK		 3444 eax = reg_read(ctxt, VCPU_REGS_RAX);
3445 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3446 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3447 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3448 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3449 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3450 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3451 return X86EMUL_CONTINUE;
3452}
3453
98f73630
PB		 3454static int em_sahf(struct x86_emulate_ctxt *ctxt)
3455{
3456 u32 flags;
3457
3458 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3459 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3460
3461 ctxt->eflags &= ~0xffUL;
3462 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3463 return X86EMUL_CONTINUE;
3464}
3465
2dd7caa0
AK		 3466static int em_lahf(struct x86_emulate_ctxt *ctxt)
3467{
dd856efa
AK		 3468 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3469 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3470 return X86EMUL_CONTINUE;
3471}
3472
9299836e
AK		 3473static int em_bswap(struct x86_emulate_ctxt *ctxt)
3474{
3475 switch (ctxt->op_bytes) {
3476#ifdef CONFIG_X86_64
3477 case 8:
3478 asm("bswap %0" : "+r"(ctxt->dst.val));
3479 break;
3480#endif
3481 default:
3482 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3483 break;
3484 }
3485 return X86EMUL_CONTINUE;
3486}
3487
13e457e0
NA		 3488static int em_clflush(struct x86_emulate_ctxt *ctxt)
3489{
3490 /* emulating clflush regardless of cpuid */
3491 return X86EMUL_CONTINUE;
3492}
3493
cfec82cb
JR		 3494static bool valid_cr(int nr)
3495{
3496 switch (nr) {
3497 case 0:
3498 case 2 ... 4:
3499 case 8:
3500 return true;
3501 default:
3502 return false;
3503 }
3504}
3505
3506static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3507{
9dac77fa 3508 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3509 return emulate_ud(ctxt);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
3514static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3515{
9dac77fa
AK		 3516 u64 new_val = ctxt->src.val64;
3517 int cr = ctxt->modrm_reg;
c2ad2bb3 3518 u64 efer = 0;
cfec82cb
JR		 3519
3520 static u64 cr_reserved_bits[] = {
3521 0xffffffff00000000ULL,
3522 0, 0, 0, /* CR3 checked later */
3523 CR4_RESERVED_BITS,
3524 0, 0, 0,
3525 CR8_RESERVED_BITS,
3526 };
3527
3528 if (!valid_cr(cr))
3529 return emulate_ud(ctxt);
3530
3531 if (new_val & cr_reserved_bits[cr])
3532 return emulate_gp(ctxt, 0);
3533
3534 switch (cr) {
3535 case 0: {
c2ad2bb3 3536 u64 cr4;
cfec82cb
JR		 3537 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3538 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3539 return emulate_gp(ctxt, 0);
3540
717746e3
AK		 3541 cr4 = ctxt->ops->get_cr(ctxt, 4);
3542 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3543
3544 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3545 !(cr4 & X86_CR4_PAE))
3546 return emulate_gp(ctxt, 0);
3547
3548 break;
3549 }
3550 case 3: {
3551 u64 rsvd = 0;
3552
c2ad2bb3
AK		 3553 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3554 if (efer & EFER_LMA)
9d88fca7 3555 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3556
3557 if (new_val & rsvd)
3558 return emulate_gp(ctxt, 0);
3559
3560 break;
3561 }
3562 case 4: {
717746e3 3563 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3564
3565 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3566 return emulate_gp(ctxt, 0);
3567
3568 break;
3569 }
3570 }
3571
3572 return X86EMUL_CONTINUE;
3573}
3574
3b88e41a
JR		 3575static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3576{
3577 unsigned long dr7;
3578
717746e3 3579 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3580
3581 /* Check if DR7.Global_Enable is set */
3582 return dr7 & (1 << 13);
3583}
3584
3585static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3586{
9dac77fa 3587 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3588 u64 cr4;
3589
3590 if (dr > 7)
3591 return emulate_ud(ctxt);
3592
717746e3 3593 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3594 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3595 return emulate_ud(ctxt);
3596
6d2a0526
NA		 3597 if (check_dr7_gd(ctxt)) {
3598 ulong dr6;
3599
3600 ctxt->ops->get_dr(ctxt, 6, &dr6);
3601 dr6 &= ~15;
3602 dr6 |= DR6_BD | DR6_RTM;
3603 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3604 return emulate_db(ctxt);
6d2a0526 3605 }
3b88e41a
JR		 3606
3607 return X86EMUL_CONTINUE;
3608}
3609
3610static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3611{
9dac77fa
AK		 3612 u64 new_val = ctxt->src.val64;
3613 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3614
3615 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3616 return emulate_gp(ctxt, 0);
3617
3618 return check_dr_read(ctxt);
3619}
3620
01de8b09
JR		 3621static int check_svme(struct x86_emulate_ctxt *ctxt)
3622{
3623 u64 efer;
3624
717746e3 3625 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3626
3627 if (!(efer & EFER_SVME))
3628 return emulate_ud(ctxt);
3629
3630 return X86EMUL_CONTINUE;
3631}
3632
3633static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3634{
dd856efa 3635 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3636
3637 /* Valid physical address? */
d4224449 3638 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3639 return emulate_gp(ctxt, 0);
3640
3641 return check_svme(ctxt);
3642}
3643
d7eb8203
JR		 3644static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3645{
717746e3 3646 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3647
717746e3 3648 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3649 return emulate_ud(ctxt);
3650
3651 return X86EMUL_CONTINUE;
3652}
3653
8061252e
JR		 3654static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3655{
717746e3 3656 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3657 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3658
717746e3 3659 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3660 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3661 return emulate_gp(ctxt, 0);
3662
3663 return X86EMUL_CONTINUE;
3664}
3665
f6511935
JR		 3666static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3667{
9dac77fa
AK		 3668 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3669 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3670 return emulate_gp(ctxt, 0);
3671
3672 return X86EMUL_CONTINUE;
3673}
3674
3675static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3676{
9dac77fa
AK		 3677 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3678 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3679 return emulate_gp(ctxt, 0);
3680
3681 return X86EMUL_CONTINUE;
3682}
3683
73fba5f4 3684#define D(_y) { .flags = (_y) }
d40a6898
PB		 3685#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3686#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3687 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3688#define N D(NotImpl)
01de8b09 3689#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3690#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3691#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3692#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3693#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3694#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3695#define II(_f, _e, _i) \
d40a6898 3696 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3697#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3698 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3699 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3700#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3701
8d8f4e9f 3702#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3703#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3704#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3705#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3706#define I2bvIP(_f, _e, _i, _p) \
3707 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3708
fb864fbc
AK		 3709#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3710 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3711 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3712
0f54a321
NA		 3713static const struct opcode group7_rm0[] = {
3714 N,
3715 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3716 N, N, N, N, N, N,
3717};
3718
fd0a0d82 3719static const struct opcode group7_rm1[] = {
1c2545be
TY		 3720 DI(SrcNone | Priv, monitor),
3721 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3722 N, N, N, N, N, N,
3723};
3724
fd0a0d82 3725static const struct opcode group7_rm3[] = {
1c2545be 3726 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3727 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3728 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3729 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3730 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3731 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3732 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3733 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3734};
6230f7fc 3735
fd0a0d82 3736static const struct opcode group7_rm7[] = {
d7eb8203 3737 N,
1c2545be 3738 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3739 N, N, N, N, N, N,
3740};
d67fc27a 3741
fd0a0d82 3742static const struct opcode group1[] = {
fb864fbc
AK		 3743 F(Lock, em_add),
3744 F(Lock | PageTable, em_or),
3745 F(Lock, em_adc),
3746 F(Lock, em_sbb),
3747 F(Lock | PageTable, em_and),
3748 F(Lock, em_sub),
3749 F(Lock, em_xor),
3750 F(NoWrite, em_cmp),
73fba5f4
AK		 3751};
3752
fd0a0d82 3753static const struct opcode group1A[] = {
1c2545be 3754 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3755};
3756
007a3b54
AK		 3757static const struct opcode group2[] = {
3758 F(DstMem | ModRM, em_rol),
3759 F(DstMem | ModRM, em_ror),
3760 F(DstMem | ModRM, em_rcl),
3761 F(DstMem | ModRM, em_rcr),
3762 F(DstMem | ModRM, em_shl),
3763 F(DstMem | ModRM, em_shr),
3764 F(DstMem | ModRM, em_shl),
3765 F(DstMem | ModRM, em_sar),
3766};
3767
fd0a0d82 3768static const struct opcode group3[] = {
fb864fbc
AK		 3769 F(DstMem | SrcImm | NoWrite, em_test),
3770 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3771 F(DstMem | SrcNone | Lock, em_not),
3772 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3773 F(DstXacc | Src2Mem, em_mul_ex),
3774 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3775 F(DstXacc | Src2Mem, em_div_ex),
3776 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3777};
3778
fd0a0d82 3779static const struct opcode group4[] = {
95413dc4
AK		 3780 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3781 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3782 N, N, N, N, N, N,
3783};
3784
fd0a0d82 3785static const struct opcode group5[] = {
95413dc4
AK		 3786 F(DstMem | SrcNone | Lock, em_inc),
3787 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3788 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3789 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3790 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3791 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3792 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3793};
3794
fd0a0d82 3795static const struct opcode group6[] = {
1c2545be
TY		 3796 DI(Prot, sldt),
3797 DI(Prot, str),
a14e579f 3798 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3799 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3800 N, N, N, N,
3801};
3802
fd0a0d82 3803static const struct group_dual group7 = { {
606b1c3e
NA		 3804 II(Mov | DstMem, em_sgdt, sgdt),
3805 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3806 II(SrcMem | Priv, em_lgdt, lgdt),
3807 II(SrcMem | Priv, em_lidt, lidt),
3808 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3809 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3810 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3811}, {
0f54a321 3812 EXT(0, group7_rm0),
5ef39c71 3813 EXT(0, group7_rm1),
01de8b09 3814 N, EXT(0, group7_rm3),
1c2545be
TY		 3815 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3816 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3817 EXT(0, group7_rm7),
73fba5f4
AK		 3818} };
3819
fd0a0d82 3820static const struct opcode group8[] = {
73fba5f4 3821 N, N, N, N,
11c363ba
AK		 3822 F(DstMem | SrcImmByte | NoWrite, em_bt),
3823 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3824 F(DstMem | SrcImmByte | Lock, em_btr),
3825 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3826};
3827
fd0a0d82 3828static const struct group_dual group9 = { {
1c2545be 3829 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3830}, {
3831 N, N, N, N, N, N, N, N,
3832} };
3833
fd0a0d82 3834static const struct opcode group11[] = {
1c2545be 3835 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3836 X7(D(Undefined)),
a4d4a7c1
AK		 3837};
3838
13e457e0 3839static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3840 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3841};
3842
3843static const struct group_dual group15 = { {
3844 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3845}, {
3846 N, N, N, N, N, N, N, N,
3847} };
3848
fd0a0d82 3849static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3850 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3851};
3852
d5b77069
PB		 3853static const struct gprefix pfx_0f_2b = {
3854 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3855};
3856
27ce8258 3857static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3858 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3859};
3860
0a37027e
AW		 3861static const struct gprefix pfx_0f_e7 = {
3862 N, I(Sse, em_mov), N, N,
3863};
3864
045a282c
GN		 3865static const struct escape escape_d9 = { {
3866 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3867}, {
3868 /* 0xC0 - 0xC7 */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xC8 - 0xCF */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xD0 - 0xC7 */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xD8 - 0xDF */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xE0 - 0xE7 */
3877 N, N, N, N, N, N, N, N,
3878 /* 0xE8 - 0xEF */
3879 N, N, N, N, N, N, N, N,
3880 /* 0xF0 - 0xF7 */
3881 N, N, N, N, N, N, N, N,
3882 /* 0xF8 - 0xFF */
3883 N, N, N, N, N, N, N, N,
3884} };
3885
3886static const struct escape escape_db = { {
3887 N, N, N, N, N, N, N, N,
3888}, {
3889 /* 0xC0 - 0xC7 */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xC8 - 0xCF */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xD0 - 0xC7 */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xD8 - 0xDF */
3896 N, N, N, N, N, N, N, N,
3897 /* 0xE0 - 0xE7 */
3898 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3899 /* 0xE8 - 0xEF */
3900 N, N, N, N, N, N, N, N,
3901 /* 0xF0 - 0xF7 */
3902 N, N, N, N, N, N, N, N,
3903 /* 0xF8 - 0xFF */
3904 N, N, N, N, N, N, N, N,
3905} };
3906
3907static const struct escape escape_dd = { {
3908 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3909}, {
3910 /* 0xC0 - 0xC7 */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xC8 - 0xCF */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xD0 - 0xC7 */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xD8 - 0xDF */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xE0 - 0xE7 */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xE8 - 0xEF */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xF0 - 0xF7 */
3923 N, N, N, N, N, N, N, N,
3924 /* 0xF8 - 0xFF */
3925 N, N, N, N, N, N, N, N,
3926} };
3927
fd0a0d82 3928static const struct opcode opcode_table[256] = {
73fba5f4 3929 /* 0x00 - 0x07 */
fb864fbc 3930 F6ALU(Lock, em_add),
1cd196ea
AK		 3931 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3932 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3933 /* 0x08 - 0x0F */
fb864fbc 3934 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3935 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3936 N,
73fba5f4 3937 /* 0x10 - 0x17 */
fb864fbc 3938 F6ALU(Lock, em_adc),
1cd196ea
AK		 3939 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3940 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3941 /* 0x18 - 0x1F */
fb864fbc 3942 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3943 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3944 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3945 /* 0x20 - 0x27 */
fb864fbc 3946 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3947 /* 0x28 - 0x2F */
fb864fbc 3948 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3949 /* 0x30 - 0x37 */
fb864fbc 3950 F6ALU(Lock, em_xor), N, N,
73fba5f4 3951 /* 0x38 - 0x3F */
fb864fbc 3952 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3953 /* 0x40 - 0x4F */
95413dc4 3954 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3955 /* 0x50 - 0x57 */
63540382 3956 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3957 /* 0x58 - 0x5F */
c54fe504 3958 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3959 /* 0x60 - 0x67 */
b96a7fad
TY		 3960 I(ImplicitOps | Stack | No64, em_pusha),
3961 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3962 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3963 N, N, N, N,
3964 /* 0x68 - 0x6F */
d46164db
AK		 3965 I(SrcImm | Mov | Stack, em_push),
3966 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3967 I(SrcImmByte | Mov | Stack, em_push),
3968 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3969 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3970 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3971 /* 0x70 - 0x7F */
58b7075d 3972 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3973 /* 0x80 - 0x87 */
1c2545be
TY		 3974 G(ByteOp | DstMem | SrcImm, group1),
3975 G(DstMem | SrcImm, group1),
3976 G(ByteOp | DstMem | SrcImm | No64, group1),
3977 G(DstMem | SrcImmByte, group1),
fb864fbc 3978 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3979 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3980 /* 0x88 - 0x8F */
d5ae7ce8 3981 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3982 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3983 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3984 D(ModRM | SrcMem | NoAccess | DstReg),
3985 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3986 G(0, group1A),
73fba5f4 3987 /* 0x90 - 0x97 */
bf608f88 3988 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3989 /* 0x98 - 0x9F */
61429142 3990 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3991 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3992 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3993 II(ImplicitOps | Stack, em_popf, popf),
3994 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3995 /* 0xA0 - 0xA7 */
b9eac5f4 3996 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3997 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3998 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 3999 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4000 /* 0xA8 - 0xAF */
fb864fbc 4001 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4002 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4003 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4004 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4005 /* 0xB0 - 0xB7 */
b9eac5f4 4006 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4007 /* 0xB8 - 0xBF */
5e2c6883 4008 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4009 /* 0xC0 - 0xC7 */
007a3b54 4010 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4011 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4012 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4013 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4014 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4015 G(ByteOp, group11), G(0, group11),
73fba5f4 4016 /* 0xC8 - 0xCF */
612e89f0 4017 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4018 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4019 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4020 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4021 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4022 /* 0xD0 - 0xD7 */
007a3b54
AK		 4023 G(Src2One | ByteOp, group2), G(Src2One, group2),
4024 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4025 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4026 I(DstAcc | SrcImmUByte | No64, em_aad),
4027 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4028 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4029 /* 0xD8 - 0xDF */
045a282c 4030 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4031 /* 0xE0 - 0xE7 */
58b7075d
NA		 4032 X3(I(SrcImmByte | NearBranch, em_loop)),
4033 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4034 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4035 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4036 /* 0xE8 - 0xEF */
58b7075d
NA		 4037 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4038 I(SrcImmFAddr | No64, em_jmp_far),
4039 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4040 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4041 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4042 /* 0xF0 - 0xF7 */
bf608f88 4043 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4044 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4045 G(ByteOp, group3), G(0, group3),
73fba5f4 4046 /* 0xF8 - 0xFF */
f411e6cd
TY		 4047 D(ImplicitOps), D(ImplicitOps),
4048 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4049 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4050};
4051
fd0a0d82 4052static const struct opcode twobyte_table[256] = {
73fba5f4 4053 /* 0x00 - 0x0F */
dee6bb70 4054 G(0, group6), GD(0, &group7), N, N,
b51e974f 4055 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4056 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4057 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4058 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4059 /* 0x10 - 0x1F */
103f98ea 4060 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4061 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4062 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4063 /* 0x20 - 0x2F */
9b88ae99
NA		 4064 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4065 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4066 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4067 check_cr_write),
4068 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4069 check_dr_write),
73fba5f4 4070 N, N, N, N,
27ce8258
IM		 4071 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4072 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4073 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4074 N, N, N, N,
73fba5f4 4075 /* 0x30 - 0x3F */
e1e210b0 4076 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4077 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4078 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4079 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4080 I(ImplicitOps | EmulateOnUD, em_sysenter),
4081 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4082 N, N,
73fba5f4
AK		 4083 N, N, N, N, N, N, N, N,
4084 /* 0x40 - 0x4F */
140bad89 4085 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4086 /* 0x50 - 0x5F */
4087 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4088 /* 0x60 - 0x6F */
aa97bb48
AK		 4089 N, N, N, N,
4090 N, N, N, N,
4091 N, N, N, N,
4092 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4093 /* 0x70 - 0x7F */
aa97bb48
AK		 4094 N, N, N, N,
4095 N, N, N, N,
4096 N, N, N, N,
4097 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4098 /* 0x80 - 0x8F */
58b7075d 4099 X16(D(SrcImm | NearBranch)),
73fba5f4 4100 /* 0x90 - 0x9F */
ee45b58e 4101 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4102 /* 0xA0 - 0xA7 */
1cd196ea 4103 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4104 II(ImplicitOps, em_cpuid, cpuid),
4105 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4106 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4107 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4108 /* 0xA8 - 0xAF */
1cd196ea 4109 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4110 DI(ImplicitOps, rsm),
11c363ba 4111 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4112 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4113 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4114 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4115 /* 0xB0 - 0xB7 */
e940b5c2 4116 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4117 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4118 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4119 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4120 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4121 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4122 /* 0xB8 - 0xBF */
4123 N, N,
ce7faab2 4124 G(BitOp, group8),
11c363ba
AK		 4125 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4126 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4127 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4128 /* 0xC0 - 0xC7 */
e47a5f5f 4129 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
ed9aad21 4130 N, I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov),
73fba5f4 4131 N, N, N, GD(0, &group9),
9299836e
AK		 4132 /* 0xC8 - 0xCF */
4133 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4134 /* 0xD0 - 0xDF */
4135 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4136 /* 0xE0 - 0xEF */
0a37027e
AW		 4137 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4138 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4139 /* 0xF0 - 0xFF */
4140 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4141};
4142
0bc5eedb 4143static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4144 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4145};
4146
4147static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4148 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4149};
4150
4151/*
4152 * Insns below are selected by the prefix which indexed by the third opcode
4153 * byte.
4154 */
4155static const struct opcode opcode_map_0f_38[256] = {
4156 /* 0x00 - 0x7f */
4157 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4158 /* 0x80 - 0xef */
4159 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4160 /* 0xf0 - 0xf1 */
4161 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4162 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4163 /* 0xf2 - 0xff */
4164 N, N, X4(N), X8(N)
0bc5eedb
BP		 4165};
4166
73fba5f4
AK		 4167#undef D
4168#undef N
4169#undef G
4170#undef GD
4171#undef I
aa97bb48 4172#undef GP
01de8b09 4173#undef EXT
73fba5f4 4174
8d8f4e9f 4175#undef D2bv
f6511935 4176#undef D2bvIP
8d8f4e9f 4177#undef I2bv
d7841a4b 4178#undef I2bvIP
d67fc27a 4179#undef I6ALU
8d8f4e9f 4180
9dac77fa 4181static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4182{
4183 unsigned size;
4184
9dac77fa 4185 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4186 if (size == 8)
4187 size = 4;
4188 return size;
4189}
4190
4191static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4192 unsigned size, bool sign_extension)
4193{
39f21ee5
AK		 4194 int rc = X86EMUL_CONTINUE;
4195
4196 op->type = OP_IMM;
4197 op->bytes = size;
9dac77fa 4198 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4199 /* NB. Immediates are sign-extended as necessary. */
4200 switch (op->bytes) {
4201 case 1:
e85a1085 4202 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4203 break;
4204 case 2:
e85a1085 4205 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4206 break;
4207 case 4:
e85a1085 4208 op->val = insn_fetch(s32, ctxt);
39f21ee5 4209 break;
5e2c6883
NA		 4210 case 8:
4211 op->val = insn_fetch(s64, ctxt);
4212 break;
39f21ee5
AK		 4213 }
4214 if (!sign_extension) {
4215 switch (op->bytes) {
4216 case 1:
4217 op->val &= 0xff;
4218 break;
4219 case 2:
4220 op->val &= 0xffff;
4221 break;
4222 case 4:
4223 op->val &= 0xffffffff;
4224 break;
4225 }
4226 }
4227done:
4228 return rc;
4229}
4230
a9945549
AK		 4231static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4232 unsigned d)
4233{
4234 int rc = X86EMUL_CONTINUE;
4235
4236 switch (d) {
4237 case OpReg:
2adb5ad9 4238 decode_register_operand(ctxt, op);
a9945549
AK		 4239 break;
4240 case OpImmUByte:
608aabe3 4241 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4242 break;
4243 case OpMem:
41ddf978 4244 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4245 mem_common:
4246 *op = ctxt->memop;
4247 ctxt->memopp = op;
96888977 4248 if (ctxt->d & BitOp)
a9945549
AK		 4249 fetch_bit_operand(ctxt);
4250 op->orig_val = op->val;
4251 break;
41ddf978 4252 case OpMem64:
aaa05f24 4253 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4254 goto mem_common;
a9945549
AK		 4255 case OpAcc:
4256 op->type = OP_REG;
4257 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4258 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4259 fetch_register_operand(op);
4260 op->orig_val = op->val;
4261 break;
820207c8
AK		 4262 case OpAccLo:
4263 op->type = OP_REG;
4264 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4265 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4266 fetch_register_operand(op);
4267 op->orig_val = op->val;
4268 break;
4269 case OpAccHi:
4270 if (ctxt->d & ByteOp) {
4271 op->type = OP_NONE;
4272 break;
4273 }
4274 op->type = OP_REG;
4275 op->bytes = ctxt->op_bytes;
4276 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4277 fetch_register_operand(op);
4278 op->orig_val = op->val;
4279 break;
a9945549
AK		 4280 case OpDI:
4281 op->type = OP_MEM;
4282 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4283 op->addr.mem.ea =
dd856efa 4284 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4285 op->addr.mem.seg = VCPU_SREG_ES;
4286 op->val = 0;
b3356bf0 4287 op->count = 1;
a9945549
AK		 4288 break;
4289 case OpDX:
4290 op->type = OP_REG;
4291 op->bytes = 2;
dd856efa 4292 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4293 fetch_register_operand(op);
4294 break;
4dd6a57d
AK		 4295 case OpCL:
4296 op->bytes = 1;
dd856efa 4297 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4298 break;
4299 case OpImmByte:
4300 rc = decode_imm(ctxt, op, 1, true);
4301 break;
4302 case OpOne:
4303 op->bytes = 1;
4304 op->val = 1;
4305 break;
4306 case OpImm:
4307 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4308 break;
5e2c6883
NA		 4309 case OpImm64:
4310 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4311 break;
28867cee
AK		 4312 case OpMem8:
4313 ctxt->memop.bytes = 1;
660696d1 4314 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4315 ctxt->memop.addr.reg = decode_register(ctxt,
4316 ctxt->modrm_rm, true);
660696d1
GN		 4317 fetch_register_operand(&ctxt->memop);
4318 }
28867cee 4319 goto mem_common;
0fe59128
AK		 4320 case OpMem16:
4321 ctxt->memop.bytes = 2;
4322 goto mem_common;
4323 case OpMem32:
4324 ctxt->memop.bytes = 4;
4325 goto mem_common;
4326 case OpImmU16:
4327 rc = decode_imm(ctxt, op, 2, false);
4328 break;
4329 case OpImmU:
4330 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4331 break;
4332 case OpSI:
4333 op->type = OP_MEM;
4334 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4335 op->addr.mem.ea =
dd856efa 4336 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4337 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4338 op->val = 0;
b3356bf0 4339 op->count = 1;
0fe59128 4340 break;
7fa57952
PB		 4341 case OpXLat:
4342 op->type = OP_MEM;
4343 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4344 op->addr.mem.ea =
4345 register_address(ctxt,
4346 reg_read(ctxt, VCPU_REGS_RBX) +
4347 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4348 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4349 op->val = 0;
4350 break;
0fe59128
AK		 4351 case OpImmFAddr:
4352 op->type = OP_IMM;
4353 op->addr.mem.ea = ctxt->_eip;
4354 op->bytes = ctxt->op_bytes + 2;
4355 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4356 break;
4357 case OpMemFAddr:
4358 ctxt->memop.bytes = ctxt->op_bytes + 2;
4359 goto mem_common;
c191a7a0
AK		 4360 case OpES:
4361 op->val = VCPU_SREG_ES;
4362 break;
4363 case OpCS:
4364 op->val = VCPU_SREG_CS;
4365 break;
4366 case OpSS:
4367 op->val = VCPU_SREG_SS;
4368 break;
4369 case OpDS:
4370 op->val = VCPU_SREG_DS;
4371 break;
4372 case OpFS:
4373 op->val = VCPU_SREG_FS;
4374 break;
4375 case OpGS:
4376 op->val = VCPU_SREG_GS;
4377 break;
a9945549
AK		 4378 case OpImplicit:
4379 /* Special instructions do their own operand decoding. */
4380 default:
4381 op->type = OP_NONE; /* Disable writeback. */
4382 break;
4383 }
4384
4385done:
4386 return rc;
4387}
4388
ef5d75cc 4389int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4390{
dde7e6d1
AK		 4391 int rc = X86EMUL_CONTINUE;
4392 int mode = ctxt->mode;
46561646 4393 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4394 bool op_prefix = false;
573e80fe 4395 bool has_seg_override = false;
46561646 4396 struct opcode opcode;
dde7e6d1 4397
f09ed83e
AK		 4398 ctxt->memop.type = OP_NONE;
4399 ctxt->memopp = NULL;
9dac77fa 4400 ctxt->_eip = ctxt->eip;
17052f16
PB		 4401 ctxt->fetch.ptr = ctxt->fetch.data;
4402 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4403 ctxt->opcode_len = 1;
dc25e89e 4404 if (insn_len > 0)
9dac77fa 4405 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4406 else {
9506d57d 4407 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4408 if (rc != X86EMUL_CONTINUE)
4409 return rc;
4410 }
dde7e6d1
AK		 4411
4412 switch (mode) {
4413 case X86EMUL_MODE_REAL:
4414 case X86EMUL_MODE_VM86:
4415 case X86EMUL_MODE_PROT16:
4416 def_op_bytes = def_ad_bytes = 2;
4417 break;
4418 case X86EMUL_MODE_PROT32:
4419 def_op_bytes = def_ad_bytes = 4;
4420 break;
4421#ifdef CONFIG_X86_64
4422 case X86EMUL_MODE_PROT64:
4423 def_op_bytes = 4;
4424 def_ad_bytes = 8;
4425 break;
4426#endif
4427 default:
1d2887e2 4428 return EMULATION_FAILED;
dde7e6d1
AK		 4429 }
4430
9dac77fa
AK		 4431 ctxt->op_bytes = def_op_bytes;
4432 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4433
4434 /* Legacy prefixes. */
4435 for (;;) {
e85a1085 4436 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4437 case 0x66: /* operand-size override */
0d7cdee8 4438 op_prefix = true;
dde7e6d1 4439 /* switch between 2/4 bytes */
9dac77fa 4440 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4441 break;
4442 case 0x67: /* address-size override */
4443 if (mode == X86EMUL_MODE_PROT64)
4444 /* switch between 4/8 bytes */
9dac77fa 4445 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4446 else
4447 /* switch between 2/4 bytes */
9dac77fa 4448 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4449 break;
4450 case 0x26: /* ES override */
4451 case 0x2e: /* CS override */
4452 case 0x36: /* SS override */
4453 case 0x3e: /* DS override */
573e80fe
BD		 4454 has_seg_override = true;
4455 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4456 break;
4457 case 0x64: /* FS override */
4458 case 0x65: /* GS override */
573e80fe
BD		 4459 has_seg_override = true;
4460 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4461 break;
4462 case 0x40 ... 0x4f: /* REX */
4463 if (mode != X86EMUL_MODE_PROT64)
4464 goto done_prefixes;
9dac77fa 4465 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4466 continue;
4467 case 0xf0: /* LOCK */
9dac77fa 4468 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4469 break;
4470 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4471 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4472 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4473 break;
4474 default:
4475 goto done_prefixes;
4476 }
4477
4478 /* Any legacy prefix after a REX prefix nullifies its effect. */
4479
9dac77fa 4480 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4481 }
4482
4483done_prefixes:
4484
4485 /* REX prefix. */
9dac77fa
AK		 4486 if (ctxt->rex_prefix & 8)
4487 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4488
4489 /* Opcode byte(s). */
9dac77fa 4490 opcode = opcode_table[ctxt->b];
d3ad6243 4491 /* Two-byte opcode? */
9dac77fa 4492 if (ctxt->b == 0x0f) {
1ce19dc1 4493 ctxt->opcode_len = 2;
e85a1085 4494 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4495 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4496
4497 /* 0F_38 opcode map */
4498 if (ctxt->b == 0x38) {
4499 ctxt->opcode_len = 3;
4500 ctxt->b = insn_fetch(u8, ctxt);
4501 opcode = opcode_map_0f_38[ctxt->b];
4502 }
dde7e6d1 4503 }
9dac77fa 4504 ctxt->d = opcode.flags;
dde7e6d1 4505
9f4260e7
TY		 4506 if (ctxt->d & ModRM)
4507 ctxt->modrm = insn_fetch(u8, ctxt);
4508
7fe864dc
NA		 4509 /* vex-prefix instructions are not implemented */
4510 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4511 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4512 ctxt->d = NotImpl;
4513 }
4514
9dac77fa
AK		 4515 while (ctxt->d & GroupMask) {
4516 switch (ctxt->d & GroupMask) {
46561646 4517 case Group:
9dac77fa 4518 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4519 opcode = opcode.u.group[goffset];
4520 break;
4521 case GroupDual:
9dac77fa
AK		 4522 goffset = (ctxt->modrm >> 3) & 7;
4523 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4524 opcode = opcode.u.gdual->mod3[goffset];
4525 else
4526 opcode = opcode.u.gdual->mod012[goffset];
4527 break;
4528 case RMExt:
9dac77fa 4529 goffset = ctxt->modrm & 7;
01de8b09 4530 opcode = opcode.u.group[goffset];
46561646
AK		 4531 break;
4532 case Prefix:
9dac77fa 4533 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4534 return EMULATION_FAILED;
9dac77fa 4535 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4536 switch (simd_prefix) {
4537 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4538 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4539 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4540 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4541 }
4542 break;
045a282c
GN		 4543 case Escape:
4544 if (ctxt->modrm > 0xbf)
4545 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4546 else
4547 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4548 break;
46561646 4549 default:
1d2887e2 4550 return EMULATION_FAILED;
0d7cdee8 4551 }
46561646 4552
b1ea50b2 4553 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4554 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4555 }
4556
e24186e0
PB		 4557 /* Unrecognised? */
4558 if (ctxt->d == 0)
4559 return EMULATION_FAILED;
4560
9dac77fa 4561 ctxt->execute = opcode.u.execute;
dde7e6d1 4562
3a6095a0
NA		 4563 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4564 return EMULATION_FAILED;
4565
d40a6898 4566 if (unlikely(ctxt->d &
ed9aad21
NA		 4567 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4568 No16))) {
d40a6898
PB		 4569 /*
4570 * These are copied unconditionally here, and checked unconditionally
4571 * in x86_emulate_insn.
4572 */
4573 ctxt->check_perm = opcode.check_perm;
4574 ctxt->intercept = opcode.intercept;
dde7e6d1 4575
d40a6898
PB		 4576 if (ctxt->d & NotImpl)
4577 return EMULATION_FAILED;
d867162c 4578
58b7075d
NA		 4579 if (mode == X86EMUL_MODE_PROT64) {
4580 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4581 ctxt->op_bytes = 8;
4582 else if (ctxt->d & NearBranch)
4583 ctxt->op_bytes = 8;
4584 }
7f9b4b75 4585
d40a6898
PB		 4586 if (ctxt->d & Op3264) {
4587 if (mode == X86EMUL_MODE_PROT64)
4588 ctxt->op_bytes = 8;
4589 else
4590 ctxt->op_bytes = 4;
4591 }
4592
ed9aad21
NA		 4593 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4594 ctxt->op_bytes = 4;
4595
d40a6898
PB		 4596 if (ctxt->d & Sse)
4597 ctxt->op_bytes = 16;
4598 else if (ctxt->d & Mmx)
4599 ctxt->op_bytes = 8;
4600 }
1253791d 4601
dde7e6d1 4602 /* ModRM and SIB bytes. */
9dac77fa 4603 if (ctxt->d & ModRM) {
f09ed83e 4604 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4605 if (!has_seg_override) {
4606 has_seg_override = true;
4607 ctxt->seg_override = ctxt->modrm_seg;
4608 }
9dac77fa 4609 } else if (ctxt->d & MemAbs)
f09ed83e 4610 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4611 if (rc != X86EMUL_CONTINUE)
4612 goto done;
4613
573e80fe
BD		 4614 if (!has_seg_override)
4615 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4616
573e80fe 4617 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4618
dde7e6d1
AK		 4619 /*
4620 * Decode and fetch the source operand: register, memory
4621 * or immediate.
4622 */
0fe59128 4623 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4624 if (rc != X86EMUL_CONTINUE)
4625 goto done;
4626
dde7e6d1
AK		 4627 /*
4628 * Decode and fetch the second source operand: register, memory
4629 * or immediate.
4630 */
4dd6a57d 4631 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4632 if (rc != X86EMUL_CONTINUE)
4633 goto done;
4634
dde7e6d1 4635 /* Decode and fetch the destination operand: register or memory. */
a9945549 4636 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4637
41061cdb 4638 if (ctxt->rip_relative)
1c1c35ae
NA		 4639 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4640 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4641
a430c916 4642done:
1d2887e2 4643 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4644}
4645
1cb3f3ae
XG		 4646bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4647{
4648 return ctxt->d & PageTable;
4649}
4650
3e2f65d5
GN		 4651static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4652{
3e2f65d5
GN		 4653 /* The second termination condition only applies for REPE
4654 * and REPNE. Test if the repeat string operation prefix is
4655 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4656 * corresponding termination condition according to:
4657 * - if REPE/REPZ and ZF = 0 then done
4658 * - if REPNE/REPNZ and ZF = 1 then done
4659 */
9dac77fa
AK		 4660 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4661 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4662 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4663 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4664 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4665 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4666 return true;
4667
4668 return false;
4669}
4670
cbe2c9d3
AK		 4671static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4672{
4673 bool fault = false;
4674
4675 ctxt->ops->get_fpu(ctxt);
4676 asm volatile("1: fwait \n\t"
4677 "2: \n\t"
4678 ".pushsection .fixup,\"ax\" \n\t"
4679 "3: \n\t"
4680 "movb $1, %[fault] \n\t"
4681 "jmp 2b \n\t"
4682 ".popsection \n\t"
4683 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4684 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4685 ctxt->ops->put_fpu(ctxt);
4686
4687 if (unlikely(fault))
4688 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4689
4690 return X86EMUL_CONTINUE;
4691}
4692
4693static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4694 struct operand *op)
4695{
4696 if (op->type == OP_MM)
4697 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4698}
4699
e28bbd44
AK		 4700static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4701{
4702 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4703 if (!(ctxt->d & ByteOp))
4704 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4705 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4706 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4707 [fastop]"+S"(fop)
4708 : "c"(ctxt->src2.val));
e28bbd44 4709 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4710 if (!fop) /* exception is returned in fop variable */
4711 return emulate_de(ctxt);
e28bbd44
AK		 4712 return X86EMUL_CONTINUE;
4713}
dd856efa 4714
1498507a
BD		 4715void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4716{
573e80fe
BD		 4717 memset(&ctxt->rip_relative, 0,
4718 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4719
1498507a
BD		 4720 ctxt->io_read.pos = 0;
4721 ctxt->io_read.end = 0;
1498507a
BD		 4722 ctxt->mem_read.end = 0;
4723}
4724
7b105ca2 4725int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4726{
0225fb50 4727 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4728 int rc = X86EMUL_CONTINUE;
9dac77fa 4729 int saved_dst_type = ctxt->dst.type;
8b4caf66 4730
9dac77fa 4731 ctxt->mem_read.pos = 0;
310b5d30 4732
e24186e0
PB		 4733 /* LOCK prefix is allowed only with some instructions */
4734 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4735 rc = emulate_ud(ctxt);
1161624f
GN		 4736 goto done;
4737 }
4738
e24186e0 4739 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4740 rc = emulate_ud(ctxt);
d380a5e4
GN		 4741 goto done;
4742 }
4743
d40a6898
PB		 4744 if (unlikely(ctxt->d &
4745 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4746 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4747 (ctxt->d & Undefined)) {
4748 rc = emulate_ud(ctxt);
4749 goto done;
4750 }
1253791d 4751
d40a6898
PB		 4752 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4753 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4754 rc = emulate_ud(ctxt);
cbe2c9d3 4755 goto done;
d40a6898 4756 }
cbe2c9d3 4757
d40a6898
PB		 4758 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4759 rc = emulate_nm(ctxt);
c4f035c6 4760 goto done;
d40a6898 4761 }
c4f035c6 4762
d40a6898
PB		 4763 if (ctxt->d & Mmx) {
4764 rc = flush_pending_x87_faults(ctxt);
4765 if (rc != X86EMUL_CONTINUE)
4766 goto done;
4767 /*
4768 * Now that we know the fpu is exception safe, we can fetch
4769 * operands from it.
4770 */
4771 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4772 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4773 if (!(ctxt->d & Mov))
4774 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4775 }
e92805ac 4776
685bbf4a 4777 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4778 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4779 X86_ICPT_PRE_EXCEPT);
4780 if (rc != X86EMUL_CONTINUE)
4781 goto done;
4782 }
8ea7d6ae 4783
d40a6898
PB		 4784 /* Privileged instruction can be executed only in CPL=0 */
4785 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4786 if (ctxt->d & PrivUD)
4787 rc = emulate_ud(ctxt);
4788 else
4789 rc = emulate_gp(ctxt, 0);
d09beabd 4790 goto done;
d40a6898 4791 }
d09beabd 4792
d40a6898
PB		 4793 /* Instruction can only be executed in protected mode */
4794 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4795 rc = emulate_ud(ctxt);
c4f035c6 4796 goto done;
d40a6898 4797 }
c4f035c6 4798
d40a6898 4799 /* Do instruction specific permission checks */
685bbf4a 4800 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4801 rc = ctxt->check_perm(ctxt);
4802 if (rc != X86EMUL_CONTINUE)
4803 goto done;
4804 }
4805
685bbf4a 4806 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4807 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4808 X86_ICPT_POST_EXCEPT);
4809 if (rc != X86EMUL_CONTINUE)
4810 goto done;
4811 }
4812
4813 if (ctxt->rep_prefix && (ctxt->d & String)) {
4814 /* All REP prefixes have the same first termination condition */
4815 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4816 ctxt->eip = ctxt->_eip;
4467c3f1 4817 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4818 goto done;
4819 }
b9fa9d6b 4820 }
b9fa9d6b
AK		 4821 }
4822
9dac77fa
AK		 4823 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4824 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4825 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4826 if (rc != X86EMUL_CONTINUE)
8b4caf66 4827 goto done;
9dac77fa 4828 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4829 }
4830
9dac77fa
AK		 4831 if (ctxt->src2.type == OP_MEM) {
4832 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4833 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4834 if (rc != X86EMUL_CONTINUE)
4835 goto done;
4836 }
4837
9dac77fa 4838 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4839 goto special_insn;
4840
4841
9dac77fa 4842 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4843 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4844 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4845 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4846 if (rc != X86EMUL_CONTINUE)
4847 goto done;
038e51de 4848 }
9dac77fa 4849 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4850
018a98db
AK		 4851special_insn:
4852
685bbf4a 4853 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4854 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4855 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4856 if (rc != X86EMUL_CONTINUE)
4857 goto done;
4858 }
4859
b9a1ecb9
NA		 4860 if (ctxt->rep_prefix && (ctxt->d & String))
4861 ctxt->eflags |= EFLG_RF;
4862 else
4863 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4864
9dac77fa 4865 if (ctxt->execute) {
e28bbd44
AK		 4866 if (ctxt->d & Fastop) {
4867 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4868 rc = fastop(ctxt, fop);
4869 if (rc != X86EMUL_CONTINUE)
4870 goto done;
4871 goto writeback;
4872 }
9dac77fa 4873 rc = ctxt->execute(ctxt);
ef65c889
AK		 4874 if (rc != X86EMUL_CONTINUE)
4875 goto done;
4876 goto writeback;
4877 }
4878
1ce19dc1 4879 if (ctxt->opcode_len == 2)
6aa8b732 4880 goto twobyte_insn;
0bc5eedb
BP		 4881 else if (ctxt->opcode_len == 3)
4882 goto threebyte_insn;
6aa8b732 4883
9dac77fa 4884 switch (ctxt->b) {
6aa8b732 4885 case 0x63: /* movsxd */
8b4caf66 4886 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4887 goto cannot_emulate;
9dac77fa 4888 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4889 break;
b2833e3c 4890 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4891 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4892 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4893 break;
7e0b54b1 4894 case 0x8d: /* lea r16/r32, m */
9dac77fa 4895 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4896 break;
3d9e77df 4897 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4898 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4899 ctxt->dst.type = OP_NONE;
4900 else
4901 rc = em_xchg(ctxt);
e4f973ae 4902 break;
e8b6fa70 4903 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4904 switch (ctxt->op_bytes) {
4905 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4906 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4907 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4908 }
4909 break;
6e154e56 4910 case 0xcc: /* int3 */
5c5df76b
TY		 4911 rc = emulate_int(ctxt, 3);
4912 break;
6e154e56 4913 case 0xcd: /* int n */
9dac77fa 4914 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4915 break;
4916 case 0xce: /* into */
5c5df76b
TY		 4917 if (ctxt->eflags & EFLG_OF)
4918 rc = emulate_int(ctxt, 4);
6e154e56 4919 break;
1a52e051 4920 case 0xe9: /* jmp rel */
db5b0762 4921 case 0xeb: /* jmp rel short */
234f3ce4 4922 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4923 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4924 break;
111de5d6 4925 case 0xf4: /* hlt */
6c3287f7 4926 ctxt->ops->halt(ctxt);
19fdfa0d 4927 break;
111de5d6
AK		 4928 case 0xf5: /* cmc */
4929 /* complement carry flag from eflags reg */
4930 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4931 break;
4932 case 0xf8: /* clc */
4933 ctxt->eflags &= ~EFLG_CF;
111de5d6 4934 break;
8744aa9a
MG		 4935 case 0xf9: /* stc */
4936 ctxt->eflags |= EFLG_CF;
4937 break;
fb4616f4
MG		 4938 case 0xfc: /* cld */
4939 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4940 break;
4941 case 0xfd: /* std */
4942 ctxt->eflags |= EFLG_DF;
fb4616f4 4943 break;
91269b8f
AK		 4944 default:
4945 goto cannot_emulate;
6aa8b732 4946 }
018a98db 4947
7d9ddaed
AK		 4948 if (rc != X86EMUL_CONTINUE)
4949 goto done;
4950
018a98db 4951writeback:
fb32b1ed
AK		 4952 if (ctxt->d & SrcWrite) {
4953 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4954 rc = writeback(ctxt, &ctxt->src);
4955 if (rc != X86EMUL_CONTINUE)
4956 goto done;
4957 }
ee212297
NA		 4958 if (!(ctxt->d & NoWrite)) {
4959 rc = writeback(ctxt, &ctxt->dst);
4960 if (rc != X86EMUL_CONTINUE)
4961 goto done;
4962 }
018a98db 4963
5cd21917
GN		 4964 /*
4965 * restore dst type in case the decoding will be reused
4966 * (happens for string instruction )
4967 */
9dac77fa 4968 ctxt->dst.type = saved_dst_type;
5cd21917 4969
9dac77fa 4970 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4971 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4972
9dac77fa 4973 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4974 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4975
9dac77fa 4976 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4977 unsigned int count;
9dac77fa 4978 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4979 if ((ctxt->d & SrcMask) == SrcSI)
4980 count = ctxt->src.count;
4981 else
4982 count = ctxt->dst.count;
4983 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4984 -count);
3e2f65d5 4985
d2ddd1c4
GN		 4986 if (!string_insn_completed(ctxt)) {
4987 /*
4988 * Re-enter guest when pio read ahead buffer is empty
4989 * or, if it is not used, after each 1024 iteration.
4990 */
dd856efa 4991 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4992 (r->end == 0 || r->end != r->pos)) {
4993 /*
4994 * Reset read cache. Usually happens before
4995 * decode, but since instruction is restarted
4996 * we have to do it here.
4997 */
9dac77fa 4998 ctxt->mem_read.end = 0;
dd856efa 4999 writeback_registers(ctxt);
d2ddd1c4
GN		 5000 return EMULATION_RESTART;
5001 }
5002 goto done; /* skip rip writeback */
0fa6ccbd 5003 }
b9a1ecb9 5004 ctxt->eflags &= ~EFLG_RF;
5cd21917 5005 }
d2ddd1c4 5006
9dac77fa 5007 ctxt->eip = ctxt->_eip;
018a98db
AK		 5008
5009done:
e0ad0b47
PB		 5010 if (rc == X86EMUL_PROPAGATE_FAULT) {
5011 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5012 ctxt->have_exception = true;
e0ad0b47 5013 }
775fde86
JR		 5014 if (rc == X86EMUL_INTERCEPTED)
5015 return EMULATION_INTERCEPTED;
5016
dd856efa
AK		 5017 if (rc == X86EMUL_CONTINUE)
5018 writeback_registers(ctxt);
5019
d2ddd1c4 5020 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5021
5022twobyte_insn:
9dac77fa 5023 switch (ctxt->b) {
018a98db 5024 case 0x09: /* wbinvd */
cfb22375 5025 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5026 break;
5027 case 0x08: /* invd */
018a98db
AK		 5028 case 0x0d: /* GrpP (prefetch) */
5029 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5030 case 0x1f: /* nop */
018a98db
AK		 5031 break;
5032 case 0x20: /* mov cr, reg */
9dac77fa 5033 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5034 break;
6aa8b732 5035 case 0x21: /* mov from dr to reg */
9dac77fa 5036 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5037 break;
6aa8b732 5038 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5039 if (test_cc(ctxt->b, ctxt->eflags))
5040 ctxt->dst.val = ctxt->src.val;
5041 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5042 ctxt->op_bytes != 4)
9dac77fa 5043 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5044 break;
b2833e3c 5045 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5046 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5047 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5048 break;
ee45b58e 5049 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5050 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5051 break;
6aa8b732 5052 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5053 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5054 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5055 : (u16) ctxt->src.val;
6aa8b732 5056 break;
6aa8b732 5057 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5058 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5059 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5060 (s16) ctxt->src.val;
6aa8b732 5061 break;
91269b8f
AK		 5062 default:
5063 goto cannot_emulate;
6aa8b732 5064 }
7d9ddaed 5065
0bc5eedb
BP		 5066threebyte_insn:
5067
7d9ddaed
AK		 5068 if (rc != X86EMUL_CONTINUE)
5069 goto done;
5070
6aa8b732
AK		 5071 goto writeback;
5072
5073cannot_emulate:
a0c0ab2f 5074 return EMULATION_FAILED;
6aa8b732 5075}
dd856efa
AK		 5076
5077void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5078{
5079 invalidate_registers(ctxt);
5080}
5081
5082void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5083{
5084 writeback_registers(ctxt);
5085}
Linux kernel - Deliverables
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