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KVM: x86 emulator: drop DPRINTF()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 78/* Misc flags */
5a506b12 79#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 80#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 81#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 82#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 83#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 84#define No64 (1<<28)
0dc8d10f
GT		 85/* Source 2 operand type */
86#define Src2None (0<<29)
87#define Src2CL (1<<29)
88#define Src2ImmByte (2<<29)
89#define Src2One (3<<29)
7db41eb7 90#define Src2Imm (4<<29)
0dc8d10f 91#define Src2Mask (7<<29)
6aa8b732 92
d0e53325
AK		 93#define X2(x...) x, x
94#define X3(x...) X2(x), x
95#define X4(x...) X2(x), X2(x)
96#define X5(x...) X4(x), x
97#define X6(x...) X4(x), X2(x)
98#define X7(x...) X4(x), X3(x)
99#define X8(x...) X4(x), X4(x)
100#define X16(x...) X8(x), X8(x)
83babbca 101
d65b1dee
AK		 102struct opcode {
103 u32 flags;
120df890 104 union {
ef65c889 105 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 106 struct opcode *group;
107 struct group_dual *gdual;
108 } u;
109};
110
111struct group_dual {
112 struct opcode mod012[8];
113 struct opcode mod3[8];
d65b1dee
AK		 114};
115
6aa8b732 116/* EFLAGS bit definitions. */
d4c6a154
GN		 117#define EFLG_ID (1<<21)
118#define EFLG_VIP (1<<20)
119#define EFLG_VIF (1<<19)
120#define EFLG_AC (1<<18)
b1d86143
AP		 121#define EFLG_VM (1<<17)
122#define EFLG_RF (1<<16)
d4c6a154
GN		 123#define EFLG_IOPL (3<<12)
124#define EFLG_NT (1<<14)
6aa8b732
AK		 125#define EFLG_OF (1<<11)
126#define EFLG_DF (1<<10)
b1d86143 127#define EFLG_IF (1<<9)
d4c6a154 128#define EFLG_TF (1<<8)
6aa8b732
AK		 129#define EFLG_SF (1<<7)
130#define EFLG_ZF (1<<6)
131#define EFLG_AF (1<<4)
132#define EFLG_PF (1<<2)
133#define EFLG_CF (1<<0)
134
62bd430e
MG		 135#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
136#define EFLG_RESERVED_ONE_MASK 2
137
6aa8b732
AK		 138/*
139 * Instruction emulation:
140 * Most instructions are emulated directly via a fragment of inline assembly
141 * code. This allows us to save/restore EFLAGS and thus very easily pick up
142 * any modified flags.
143 */
144
05b3e0c2 145#if defined(CONFIG_X86_64)
6aa8b732
AK		 146#define _LO32 "k" /* force 32-bit operand */
147#define _STK "%%rsp" /* stack pointer */
148#elif defined(__i386__)
149#define _LO32 "" /* force 32-bit operand */
150#define _STK "%%esp" /* stack pointer */
151#endif
152
153/*
154 * These EFLAGS bits are restored from saved value during emulation, and
155 * any changes are written back to the saved value after emulation.
156 */
157#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
158
159/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 160#define _PRE_EFLAGS(_sav, _msk, _tmp) \
161 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
162 "movl %"_sav",%"_LO32 _tmp"; " \
163 "push %"_tmp"; " \
164 "push %"_tmp"; " \
165 "movl %"_msk",%"_LO32 _tmp"; " \
166 "andl %"_LO32 _tmp",("_STK"); " \
167 "pushf; " \
168 "notl %"_LO32 _tmp"; " \
169 "andl %"_LO32 _tmp",("_STK"); " \
170 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
171 "pop %"_tmp"; " \
172 "orl %"_LO32 _tmp",("_STK"); " \
173 "popf; " \
174 "pop %"_sav"; "
6aa8b732
AK		 175
176/* After executing instruction: write-back necessary bits in EFLAGS. */
177#define _POST_EFLAGS(_sav, _msk, _tmp) \
178 /* _sav |= EFLAGS & _msk; */ \
179 "pushf; " \
180 "pop %"_tmp"; " \
181 "andl %"_msk",%"_LO32 _tmp"; " \
182 "orl %"_LO32 _tmp",%"_sav"; "
183
dda96d8f
AK		 184#ifdef CONFIG_X86_64
185#define ON64(x) x
186#else
187#define ON64(x)
188#endif
189
b3b3d25a 190#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 191 do { \
192 __asm__ __volatile__ ( \
193 _PRE_EFLAGS("0", "4", "2") \
194 _op _suffix " %"_x"3,%1; " \
195 _POST_EFLAGS("0", "4", "2") \
fb2c2641 196 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 197 "=&r" (_tmp) \
198 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 199 } while (0)
6b7ad61f
AK		 200
201
6aa8b732
AK		 202/* Raw emulation: instruction has two explicit operands. */
203#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 204 do { \
205 unsigned long _tmp; \
206 \
207 switch ((_dst).bytes) { \
208 case 2: \
b3b3d25a 209 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 210 break; \
211 case 4: \
b3b3d25a 212 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 213 break; \
214 case 8: \
b3b3d25a 215 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 216 break; \
217 } \
6aa8b732
AK		 218 } while (0)
219
220#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
221 do { \
6b7ad61f 222 unsigned long _tmp; \
d77c26fc 223 switch ((_dst).bytes) { \
6aa8b732 224 case 1: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 226 break; \
227 default: \
228 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
229 _wx, _wy, _lx, _ly, _qx, _qy); \
230 break; \
231 } \
232 } while (0)
233
234/* Source operand is byte-sized and may be restricted to just %cl. */
235#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
236 __emulate_2op(_op, _src, _dst, _eflags, \
237 "b", "c", "b", "c", "b", "c", "b", "c")
238
239/* Source operand is byte, word, long or quad sized. */
240#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
241 __emulate_2op(_op, _src, _dst, _eflags, \
242 "b", "q", "w", "r", _LO32, "r", "", "r")
243
244/* Source operand is word, long or quad sized. */
245#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
246 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
247 "w", "r", _LO32, "r", "", "r")
248
d175226a
GT		 249/* Instruction has three operands and one operand is stored in ECX register */
250#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
251 do { \
252 unsigned long _tmp; \
253 _type _clv = (_cl).val; \
254 _type _srcv = (_src).val; \
255 _type _dstv = (_dst).val; \
256 \
257 __asm__ __volatile__ ( \
258 _PRE_EFLAGS("0", "5", "2") \
259 _op _suffix " %4,%1 \n" \
260 _POST_EFLAGS("0", "5", "2") \
261 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
262 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
263 ); \
264 \
265 (_cl).val = (unsigned long) _clv; \
266 (_src).val = (unsigned long) _srcv; \
267 (_dst).val = (unsigned long) _dstv; \
268 } while (0)
269
270#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
271 do { \
272 switch ((_dst).bytes) { \
273 case 2: \
274 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
275 "w", unsigned short); \
276 break; \
277 case 4: \
278 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
279 "l", unsigned int); \
280 break; \
281 case 8: \
282 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "q", unsigned long)); \
284 break; \
285 } \
286 } while (0)
287
dda96d8f 288#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 289 do { \
290 unsigned long _tmp; \
291 \
dda96d8f
AK		 292 __asm__ __volatile__ ( \
293 _PRE_EFLAGS("0", "3", "2") \
294 _op _suffix " %1; " \
295 _POST_EFLAGS("0", "3", "2") \
296 : "=m" (_eflags), "+m" ((_dst).val), \
297 "=&r" (_tmp) \
298 : "i" (EFLAGS_MASK)); \
299 } while (0)
300
301/* Instruction has only one explicit operand (no source operand). */
302#define emulate_1op(_op, _dst, _eflags) \
303 do { \
d77c26fc 304 switch ((_dst).bytes) { \
dda96d8f
AK		 305 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
306 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
307 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
308 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 309 } \
310 } while (0)
311
3f9f53b0
MG		 312#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
313 do { \
314 unsigned long _tmp; \
315 \
316 __asm__ __volatile__ ( \
317 _PRE_EFLAGS("0", "4", "1") \
318 _op _suffix " %5; " \
319 _POST_EFLAGS("0", "4", "1") \
320 : "=m" (_eflags), "=&r" (_tmp), \
321 "+a" (_rax), "+d" (_rdx) \
322 : "i" (EFLAGS_MASK), "m" ((_src).val), \
323 "a" (_rax), "d" (_rdx)); \
324 } while (0)
325
f6b3597b
AK		 326#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
327 do { \
328 unsigned long _tmp; \
329 \
330 __asm__ __volatile__ ( \
331 _PRE_EFLAGS("0", "5", "1") \
332 "1: \n\t" \
333 _op _suffix " %6; " \
334 "2: \n\t" \
335 _POST_EFLAGS("0", "5", "1") \
336 ".pushsection .fixup,\"ax\" \n\t" \
337 "3: movb $1, %4 \n\t" \
338 "jmp 2b \n\t" \
339 ".popsection \n\t" \
340 _ASM_EXTABLE(1b, 3b) \
341 : "=m" (_eflags), "=&r" (_tmp), \
342 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
343 : "i" (EFLAGS_MASK), "m" ((_src).val), \
344 "a" (_rax), "d" (_rdx)); \
345 } while (0)
346
3f9f53b0
MG		 347/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
348#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
349 do { \
350 switch((_src).bytes) { \
351 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
352 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
353 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
354 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
355 } \
356 } while (0)
357
f6b3597b
AK		 358#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
359 do { \
360 switch((_src).bytes) { \
361 case 1: \
362 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
363 _eflags, "b", _ex); \
364 break; \
365 case 2: \
366 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
367 _eflags, "w", _ex); \
368 break; \
369 case 4: \
370 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
371 _eflags, "l", _ex); \
372 break; \
373 case 8: ON64( \
374 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
375 _eflags, "q", _ex)); \
376 break; \
377 } \
378 } while (0)
379
6aa8b732
AK		 380/* Fetch next part of the instruction being emulated. */
381#define insn_fetch(_type, _size, _eip) \
382({ unsigned long _x; \
62266869 383 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 384 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 385 goto done; \
386 (_eip) += (_size); \
387 (_type)_x; \
388})
389
414e6277
GN		 390#define insn_fetch_arr(_arr, _size, _eip) \
391({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
392 if (rc != X86EMUL_CONTINUE) \
393 goto done; \
394 (_eip) += (_size); \
395})
396
ddcb2885
HH		 397static inline unsigned long ad_mask(struct decode_cache *c)
398{
399 return (1UL << (c->ad_bytes << 3)) - 1;
400}
401
6aa8b732 402/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 403static inline unsigned long
404address_mask(struct decode_cache *c, unsigned long reg)
405{
406 if (c->ad_bytes == sizeof(unsigned long))
407 return reg;
408 else
409 return reg & ad_mask(c);
410}
411
412static inline unsigned long
413register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
414{
415 return base + address_mask(c, reg);
416}
417
7a957275
HH		 418static inline void
419register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
420{
421 if (c->ad_bytes == sizeof(unsigned long))
422 *reg += inc;
423 else
424 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
425}
6aa8b732 426
7a957275
HH		 427static inline void jmp_rel(struct decode_cache *c, int rel)
428{
429 register_address_increment(c, &c->eip, rel);
430}
098c937b 431
7a5b56df
AK		 432static void set_seg_override(struct decode_cache *c, int seg)
433{
434 c->has_seg_override = true;
435 c->seg_override = seg;
436}
437
79168fd1
GN		 438static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
439 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 440{
441 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
442 return 0;
443
79168fd1 444 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 445}
446
447static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 448 struct x86_emulate_ops *ops,
7a5b56df
AK		 449 struct decode_cache *c)
450{
451 if (!c->has_seg_override)
452 return 0;
453
79168fd1 454 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 455}
456
79168fd1
GN		 457static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
458 struct x86_emulate_ops *ops)
7a5b56df 459{
79168fd1 460 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 461}
462
79168fd1
GN		 463static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
464 struct x86_emulate_ops *ops)
7a5b56df 465{
79168fd1 466 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 467}
468
54b8486f
GN		 469static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
470 u32 error, bool valid)
471{
472 ctxt->exception = vec;
473 ctxt->error_code = error;
474 ctxt->error_code_valid = valid;
54b8486f
GN		 475}
476
477static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
478{
479 emulate_exception(ctxt, GP_VECTOR, err, true);
480}
481
8df25a32 482static void emulate_pf(struct x86_emulate_ctxt *ctxt)
54b8486f 483{
8df25a32 484 emulate_exception(ctxt, PF_VECTOR, 0, true);
54b8486f
GN		 485}
486
487static void emulate_ud(struct x86_emulate_ctxt *ctxt)
488{
489 emulate_exception(ctxt, UD_VECTOR, 0, false);
490}
491
492static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
493{
494 emulate_exception(ctxt, TS_VECTOR, err, true);
495}
496
34d1f490
AK		 497static int emulate_de(struct x86_emulate_ctxt *ctxt)
498{
499 emulate_exception(ctxt, DE_VECTOR, 0, false);
500 return X86EMUL_PROPAGATE_FAULT;
501}
502
62266869
AK		 503static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
504 struct x86_emulate_ops *ops,
2fb53ad8 505 unsigned long eip, u8 *dest)
62266869
AK		 506{
507 struct fetch_cache *fc = &ctxt->decode.fetch;
508 int rc;
2fb53ad8 509 int size, cur_size;
62266869 510
2fb53ad8
AK		 511 if (eip == fc->end) {
512 cur_size = fc->end - fc->start;
513 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
514 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
515 size, ctxt->vcpu, NULL);
3e2815e9 516 if (rc != X86EMUL_CONTINUE)
62266869 517 return rc;
2fb53ad8 518 fc->end += size;
62266869 519 }
2fb53ad8 520 *dest = fc->data[eip - fc->start];
3e2815e9 521 return X86EMUL_CONTINUE;
62266869
AK		 522}
523
524static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
525 struct x86_emulate_ops *ops,
526 unsigned long eip, void *dest, unsigned size)
527{
3e2815e9 528 int rc;
62266869 529
eb3c79e6 530 /* x86 instructions are limited to 15 bytes. */
063db061 531 if (eip + size - ctxt->eip > 15)
eb3c79e6 532 return X86EMUL_UNHANDLEABLE;
62266869
AK		 533 while (size--) {
534 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 535 if (rc != X86EMUL_CONTINUE)
62266869
AK		 536 return rc;
537 }
3e2815e9 538 return X86EMUL_CONTINUE;
62266869
AK		 539}
540
1e3c5cb0
RR		 541/*
542 * Given the 'reg' portion of a ModRM byte, and a register block, return a
543 * pointer into the block that addresses the relevant register.
544 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
545 */
546static void *decode_register(u8 modrm_reg, unsigned long *regs,
547 int highbyte_regs)
6aa8b732
AK		 548{
549 void *p;
550
551 p = &regs[modrm_reg];
552 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
553 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
554 return p;
555}
556
557static int read_descriptor(struct x86_emulate_ctxt *ctxt,
558 struct x86_emulate_ops *ops,
1a6440ae 559 ulong addr,
6aa8b732
AK		 560 u16 *size, unsigned long *address, int op_bytes)
561{
562 int rc;
563
564 if (op_bytes == 2)
565 op_bytes = 3;
566 *address = 0;
1a6440ae 567 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 568 if (rc != X86EMUL_CONTINUE)
6aa8b732 569 return rc;
1a6440ae 570 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 571 return rc;
572}
573
bbe9abbd
NK		 574static int test_cc(unsigned int condition, unsigned int flags)
575{
576 int rc = 0;
577
578 switch ((condition & 15) >> 1) {
579 case 0: /* o */
580 rc |= (flags & EFLG_OF);
581 break;
582 case 1: /* b/c/nae */
583 rc |= (flags & EFLG_CF);
584 break;
585 case 2: /* z/e */
586 rc |= (flags & EFLG_ZF);
587 break;
588 case 3: /* be/na */
589 rc |= (flags & (EFLG_CF|EFLG_ZF));
590 break;
591 case 4: /* s */
592 rc |= (flags & EFLG_SF);
593 break;
594 case 5: /* p/pe */
595 rc |= (flags & EFLG_PF);
596 break;
597 case 7: /* le/ng */
598 rc |= (flags & EFLG_ZF);
599 /* fall through */
600 case 6: /* l/nge */
601 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
602 break;
603 }
604
605 /* Odd condition identifiers (lsb == 1) have inverted sense. */
606 return (!!rc ^ (condition & 1));
607}
608
91ff3cb4
AK		 609static void fetch_register_operand(struct operand *op)
610{
611 switch (op->bytes) {
612 case 1:
613 op->val = *(u8 *)op->addr.reg;
614 break;
615 case 2:
616 op->val = *(u16 *)op->addr.reg;
617 break;
618 case 4:
619 op->val = *(u32 *)op->addr.reg;
620 break;
621 case 8:
622 op->val = *(u64 *)op->addr.reg;
623 break;
624 }
625}
626
3c118e24
AK		 627static void decode_register_operand(struct operand *op,
628 struct decode_cache *c,
3c118e24
AK		 629 int inhibit_bytereg)
630{
33615aa9 631 unsigned reg = c->modrm_reg;
9f1ef3f8 632 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 633
634 if (!(c->d & ModRM))
635 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 636 op->type = OP_REG;
637 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 638 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 639 op->bytes = 1;
640 } else {
1a6440ae 641 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 642 op->bytes = c->op_bytes;
3c118e24 643 }
91ff3cb4 644 fetch_register_operand(op);
3c118e24
AK		 645 op->orig_val = op->val;
646}
647
1c73ef66 648static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 649 struct x86_emulate_ops *ops,
650 struct operand *op)
1c73ef66
AK		 651{
652 struct decode_cache *c = &ctxt->decode;
653 u8 sib;
f5b4edcd 654 int index_reg = 0, base_reg = 0, scale;
3e2815e9 655 int rc = X86EMUL_CONTINUE;
2dbd0dd7 656 ulong modrm_ea = 0;
1c73ef66
AK		 657
658 if (c->rex_prefix) {
659 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
660 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
661 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
662 }
663
664 c->modrm = insn_fetch(u8, 1, c->eip);
665 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
666 c->modrm_reg |= (c->modrm & 0x38) >> 3;
667 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 668 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 669
670 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 671 op->type = OP_REG;
672 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
673 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 674 c->regs, c->d & ByteOp);
2dbd0dd7 675 fetch_register_operand(op);
1c73ef66
AK		 676 return rc;
677 }
678
2dbd0dd7
AK		 679 op->type = OP_MEM;
680
1c73ef66
AK		 681 if (c->ad_bytes == 2) {
682 unsigned bx = c->regs[VCPU_REGS_RBX];
683 unsigned bp = c->regs[VCPU_REGS_RBP];
684 unsigned si = c->regs[VCPU_REGS_RSI];
685 unsigned di = c->regs[VCPU_REGS_RDI];
686
687 /* 16-bit ModR/M decode. */
688 switch (c->modrm_mod) {
689 case 0:
690 if (c->modrm_rm == 6)
2dbd0dd7 691 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 692 break;
693 case 1:
2dbd0dd7 694 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 695 break;
696 case 2:
2dbd0dd7 697 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 698 break;
699 }
700 switch (c->modrm_rm) {
701 case 0:
2dbd0dd7 702 modrm_ea += bx + si;
1c73ef66
AK		 703 break;
704 case 1:
2dbd0dd7 705 modrm_ea += bx + di;
1c73ef66
AK		 706 break;
707 case 2:
2dbd0dd7 708 modrm_ea += bp + si;
1c73ef66
AK		 709 break;
710 case 3:
2dbd0dd7 711 modrm_ea += bp + di;
1c73ef66
AK		 712 break;
713 case 4:
2dbd0dd7 714 modrm_ea += si;
1c73ef66
AK		 715 break;
716 case 5:
2dbd0dd7 717 modrm_ea += di;
1c73ef66
AK		 718 break;
719 case 6:
720 if (c->modrm_mod != 0)
2dbd0dd7 721 modrm_ea += bp;
1c73ef66
AK		 722 break;
723 case 7:
2dbd0dd7 724 modrm_ea += bx;
1c73ef66
AK		 725 break;
726 }
727 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
728 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 729 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 730 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 731 } else {
732 /* 32/64-bit ModR/M decode. */
84411d85 733 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 734 sib = insn_fetch(u8, 1, c->eip);
735 index_reg |= (sib >> 3) & 7;
736 base_reg |= sib & 7;
737 scale = sib >> 6;
738
dc71d0f1 739 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 740 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 741 else
2dbd0dd7 742 modrm_ea += c->regs[base_reg];
dc71d0f1 743 if (index_reg != 4)
2dbd0dd7 744 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 745 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
746 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 747 c->rip_relative = 1;
84411d85 748 } else
2dbd0dd7 749 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 750 switch (c->modrm_mod) {
751 case 0:
752 if (c->modrm_rm == 5)
2dbd0dd7 753 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 754 break;
755 case 1:
2dbd0dd7 756 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 757 break;
758 case 2:
2dbd0dd7 759 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 760 break;
761 }
762 }
2dbd0dd7 763 op->addr.mem = modrm_ea;
1c73ef66
AK		 764done:
765 return rc;
766}
767
768static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 769 struct x86_emulate_ops *ops,
770 struct operand *op)
1c73ef66
AK		 771{
772 struct decode_cache *c = &ctxt->decode;
3e2815e9 773 int rc = X86EMUL_CONTINUE;
1c73ef66 774
2dbd0dd7 775 op->type = OP_MEM;
1c73ef66
AK		 776 switch (c->ad_bytes) {
777 case 2:
2dbd0dd7 778 op->addr.mem = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 779 break;
780 case 4:
2dbd0dd7 781 op->addr.mem = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 782 break;
783 case 8:
2dbd0dd7 784 op->addr.mem = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 785 break;
786 }
787done:
788 return rc;
789}
790
35c843c4
WY		 791static void fetch_bit_operand(struct decode_cache *c)
792{
7129eeca 793 long sv = 0, mask;
35c843c4 794
3885f18f 795 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 796 mask = ~(c->dst.bytes * 8 - 1);
797
798 if (c->src.bytes == 2)
799 sv = (s16)c->src.val & (s16)mask;
800 else if (c->src.bytes == 4)
801 sv = (s32)c->src.val & (s32)mask;
802
803 c->dst.addr.mem += (sv >> 3);
804 }
ba7ff2b7
WY		 805
806 /* only subword offset */
807 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 808}
809
dde7e6d1
AK		 810static int read_emulated(struct x86_emulate_ctxt *ctxt,
811 struct x86_emulate_ops *ops,
812 unsigned long addr, void *dest, unsigned size)
6aa8b732 813{
dde7e6d1
AK		 814 int rc;
815 struct read_cache *mc = &ctxt->decode.mem_read;
816 u32 err;
6aa8b732 817
dde7e6d1
AK		 818 while (size) {
819 int n = min(size, 8u);
820 size -= n;
821 if (mc->pos < mc->end)
822 goto read_cached;
5cd21917 823
dde7e6d1
AK		 824 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
825 ctxt->vcpu);
826 if (rc == X86EMUL_PROPAGATE_FAULT)
8df25a32 827 emulate_pf(ctxt);
dde7e6d1
AK		 828 if (rc != X86EMUL_CONTINUE)
829 return rc;
830 mc->end += n;
6aa8b732 831
dde7e6d1
AK		 832 read_cached:
833 memcpy(dest, mc->data + mc->pos, n);
834 mc->pos += n;
835 dest += n;
836 addr += n;
6aa8b732 837 }
dde7e6d1
AK		 838 return X86EMUL_CONTINUE;
839}
6aa8b732 840
dde7e6d1
AK		 841static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
842 struct x86_emulate_ops *ops,
843 unsigned int size, unsigned short port,
844 void *dest)
845{
846 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 847
dde7e6d1
AK		 848 if (rc->pos == rc->end) { /* refill pio read ahead */
849 struct decode_cache *c = &ctxt->decode;
850 unsigned int in_page, n;
851 unsigned int count = c->rep_prefix ?
852 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
853 in_page = (ctxt->eflags & EFLG_DF) ?
854 offset_in_page(c->regs[VCPU_REGS_RDI]) :
855 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
856 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
857 count);
858 if (n == 0)
859 n = 1;
860 rc->pos = rc->end = 0;
861 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
862 return 0;
863 rc->end = n * size;
6aa8b732
AK		 864 }
865
dde7e6d1
AK		 866 memcpy(dest, rc->data + rc->pos, size);
867 rc->pos += size;
868 return 1;
869}
6aa8b732 870
dde7e6d1
AK		 871static u32 desc_limit_scaled(struct desc_struct *desc)
872{
873 u32 limit = get_desc_limit(desc);
6aa8b732 874
dde7e6d1
AK		 875 return desc->g ? (limit << 12) | 0xfff : limit;
876}
6aa8b732 877
dde7e6d1
AK		 878static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
879 struct x86_emulate_ops *ops,
880 u16 selector, struct desc_ptr *dt)
881{
882 if (selector & 1 << 2) {
883 struct desc_struct desc;
884 memset (dt, 0, sizeof *dt);
885 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
886 return;
e09d082c 887
dde7e6d1
AK		 888 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
889 dt->address = get_desc_base(&desc);
890 } else
891 ops->get_gdt(dt, ctxt->vcpu);
892}
120df890 893
dde7e6d1
AK		 894/* allowed just for 8 bytes segments */
895static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
896 struct x86_emulate_ops *ops,
897 u16 selector, struct desc_struct *desc)
898{
899 struct desc_ptr dt;
900 u16 index = selector >> 3;
901 int ret;
902 u32 err;
903 ulong addr;
120df890 904
dde7e6d1 905 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 906
dde7e6d1
AK		 907 if (dt.size < index * 8 + 7) {
908 emulate_gp(ctxt, selector & 0xfffc);
909 return X86EMUL_PROPAGATE_FAULT;
e09d082c 910 }
dde7e6d1
AK		 911 addr = dt.address + index * 8;
912 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
913 if (ret == X86EMUL_PROPAGATE_FAULT)
8df25a32 914 emulate_pf(ctxt);
e09d082c 915
dde7e6d1
AK		 916 return ret;
917}
ef65c889 918
dde7e6d1
AK		 919/* allowed just for 8 bytes segments */
920static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
921 struct x86_emulate_ops *ops,
922 u16 selector, struct desc_struct *desc)
923{
924 struct desc_ptr dt;
925 u16 index = selector >> 3;
926 u32 err;
927 ulong addr;
928 int ret;
6aa8b732 929
dde7e6d1 930 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 931
dde7e6d1
AK		 932 if (dt.size < index * 8 + 7) {
933 emulate_gp(ctxt, selector & 0xfffc);
934 return X86EMUL_PROPAGATE_FAULT;
935 }
6aa8b732 936
dde7e6d1
AK		 937 addr = dt.address + index * 8;
938 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
939 if (ret == X86EMUL_PROPAGATE_FAULT)
8df25a32 940 emulate_pf(ctxt);
c7e75a3d 941
dde7e6d1
AK		 942 return ret;
943}
c7e75a3d 944
dde7e6d1
AK		 945static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
946 struct x86_emulate_ops *ops,
947 u16 selector, int seg)
948{
949 struct desc_struct seg_desc;
950 u8 dpl, rpl, cpl;
951 unsigned err_vec = GP_VECTOR;
952 u32 err_code = 0;
953 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
954 int ret;
69f55cb1 955
dde7e6d1 956 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 957
dde7e6d1
AK		 958 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
959 || ctxt->mode == X86EMUL_MODE_REAL) {
960 /* set real mode segment descriptor */
961 set_desc_base(&seg_desc, selector << 4);
962 set_desc_limit(&seg_desc, 0xffff);
963 seg_desc.type = 3;
964 seg_desc.p = 1;
965 seg_desc.s = 1;
966 goto load;
967 }
968
969 /* NULL selector is not valid for TR, CS and SS */
970 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
971 && null_selector)
972 goto exception;
973
974 /* TR should be in GDT only */
975 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
976 goto exception;
977
978 if (null_selector) /* for NULL selector skip all following checks */
979 goto load;
980
981 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
982 if (ret != X86EMUL_CONTINUE)
983 return ret;
984
985 err_code = selector & 0xfffc;
986 err_vec = GP_VECTOR;
987
988 /* can't load system descriptor into segment selecor */
989 if (seg <= VCPU_SREG_GS && !seg_desc.s)
990 goto exception;
991
992 if (!seg_desc.p) {
993 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
994 goto exception;
995 }
996
997 rpl = selector & 3;
998 dpl = seg_desc.dpl;
999 cpl = ops->cpl(ctxt->vcpu);
1000
1001 switch (seg) {
1002 case VCPU_SREG_SS:
1003 /*
1004 * segment is not a writable data segment or segment
1005 * selector's RPL != CPL or segment selector's RPL != CPL
1006 */
1007 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1008 goto exception;
6aa8b732 1009 break;
dde7e6d1
AK		 1010 case VCPU_SREG_CS:
1011 if (!(seg_desc.type & 8))
1012 goto exception;
1013
1014 if (seg_desc.type & 4) {
1015 /* conforming */
1016 if (dpl > cpl)
1017 goto exception;
1018 } else {
1019 /* nonconforming */
1020 if (rpl > cpl || dpl != cpl)
1021 goto exception;
1022 }
1023 /* CS(RPL) <- CPL */
1024 selector = (selector & 0xfffc) | cpl;
6aa8b732 1025 break;
dde7e6d1
AK		 1026 case VCPU_SREG_TR:
1027 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1028 goto exception;
1029 break;
1030 case VCPU_SREG_LDTR:
1031 if (seg_desc.s || seg_desc.type != 2)
1032 goto exception;
1033 break;
1034 default: /* DS, ES, FS, or GS */
4e62417b 1035 /*
dde7e6d1
AK		 1036 * segment is not a data or readable code segment or
1037 * ((segment is a data or nonconforming code segment)
1038 * and (both RPL and CPL > DPL))
4e62417b 1039 */
dde7e6d1
AK		 1040 if ((seg_desc.type & 0xa) == 0x8 ||
1041 (((seg_desc.type & 0xc) != 0xc) &&
1042 (rpl > dpl && cpl > dpl)))
1043 goto exception;
6aa8b732 1044 break;
dde7e6d1
AK		 1045 }
1046
1047 if (seg_desc.s) {
1048 /* mark segment as accessed */
1049 seg_desc.type |= 1;
1050 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1051 if (ret != X86EMUL_CONTINUE)
1052 return ret;
1053 }
1054load:
1055 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1056 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1057 return X86EMUL_CONTINUE;
1058exception:
1059 emulate_exception(ctxt, err_vec, err_code, true);
1060 return X86EMUL_PROPAGATE_FAULT;
1061}
1062
31be40b3
WY		 1063static void write_register_operand(struct operand *op)
1064{
1065 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1066 switch (op->bytes) {
1067 case 1:
1068 *(u8 *)op->addr.reg = (u8)op->val;
1069 break;
1070 case 2:
1071 *(u16 *)op->addr.reg = (u16)op->val;
1072 break;
1073 case 4:
1074 *op->addr.reg = (u32)op->val;
1075 break; /* 64b: zero-extend */
1076 case 8:
1077 *op->addr.reg = op->val;
1078 break;
1079 }
1080}
1081
dde7e6d1
AK		 1082static inline int writeback(struct x86_emulate_ctxt *ctxt,
1083 struct x86_emulate_ops *ops)
1084{
1085 int rc;
1086 struct decode_cache *c = &ctxt->decode;
1087 u32 err;
1088
1089 switch (c->dst.type) {
1090 case OP_REG:
31be40b3 1091 write_register_operand(&c->dst);
6aa8b732 1092 break;
dde7e6d1
AK		 1093 case OP_MEM:
1094 if (c->lock_prefix)
1095 rc = ops->cmpxchg_emulated(
1a6440ae 1096 c->dst.addr.mem,
dde7e6d1
AK		 1097 &c->dst.orig_val,
1098 &c->dst.val,
1099 c->dst.bytes,
1100 &err,
1101 ctxt->vcpu);
341de7e3 1102 else
dde7e6d1 1103 rc = ops->write_emulated(
1a6440ae 1104 c->dst.addr.mem,
dde7e6d1
AK		 1105 &c->dst.val,
1106 c->dst.bytes,
1107 &err,
1108 ctxt->vcpu);
1109 if (rc == X86EMUL_PROPAGATE_FAULT)
8df25a32 1110 emulate_pf(ctxt);
dde7e6d1
AK		 1111 if (rc != X86EMUL_CONTINUE)
1112 return rc;
a682e354 1113 break;
dde7e6d1
AK		 1114 case OP_NONE:
1115 /* no writeback */
414e6277 1116 break;
dde7e6d1 1117 default:
414e6277 1118 break;
6aa8b732 1119 }
dde7e6d1
AK		 1120 return X86EMUL_CONTINUE;
1121}
6aa8b732 1122
dde7e6d1
AK		 1123static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1124 struct x86_emulate_ops *ops)
1125{
1126 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1127
dde7e6d1
AK		 1128 c->dst.type = OP_MEM;
1129 c->dst.bytes = c->op_bytes;
1130 c->dst.val = c->src.val;
1131 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1132 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1133 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1134}
69f55cb1 1135
dde7e6d1
AK		 1136static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1137 struct x86_emulate_ops *ops,
1138 void *dest, int len)
1139{
1140 struct decode_cache *c = &ctxt->decode;
1141 int rc;
8b4caf66 1142
dde7e6d1
AK		 1143 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1144 c->regs[VCPU_REGS_RSP]),
1145 dest, len);
1146 if (rc != X86EMUL_CONTINUE)
1147 return rc;
1148
1149 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1150 return rc;
8b4caf66
LV		 1151}
1152
dde7e6d1
AK		 1153static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1154 struct x86_emulate_ops *ops,
1155 void *dest, int len)
9de41573
GN		 1156{
1157 int rc;
dde7e6d1
AK		 1158 unsigned long val, change_mask;
1159 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1160 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1161
dde7e6d1
AK		 1162 rc = emulate_pop(ctxt, ops, &val, len);
1163 if (rc != X86EMUL_CONTINUE)
1164 return rc;
9de41573 1165
dde7e6d1
AK		 1166 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1167 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1168
dde7e6d1
AK		 1169 switch(ctxt->mode) {
1170 case X86EMUL_MODE_PROT64:
1171 case X86EMUL_MODE_PROT32:
1172 case X86EMUL_MODE_PROT16:
1173 if (cpl == 0)
1174 change_mask |= EFLG_IOPL;
1175 if (cpl <= iopl)
1176 change_mask |= EFLG_IF;
1177 break;
1178 case X86EMUL_MODE_VM86:
1179 if (iopl < 3) {
1180 emulate_gp(ctxt, 0);
1181 return X86EMUL_PROPAGATE_FAULT;
1182 }
1183 change_mask |= EFLG_IF;
1184 break;
1185 default: /* real mode */
1186 change_mask |= (EFLG_IOPL | EFLG_IF);
1187 break;
9de41573 1188 }
dde7e6d1
AK		 1189
1190 *(unsigned long *)dest =
1191 (ctxt->eflags & ~change_mask) | (val & change_mask);
1192
d47f00a6
JR		 1193 if (rc == X86EMUL_PROPAGATE_FAULT)
1194 emulate_pf(ctxt);
1195
dde7e6d1 1196 return rc;
9de41573
GN		 1197}
1198
dde7e6d1
AK		 1199static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1200 struct x86_emulate_ops *ops, int seg)
7b262e90 1201{
dde7e6d1 1202 struct decode_cache *c = &ctxt->decode;
7b262e90 1203
dde7e6d1 1204 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1205
dde7e6d1 1206 emulate_push(ctxt, ops);
7b262e90
GN		 1207}
1208
dde7e6d1
AK		 1209static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1210 struct x86_emulate_ops *ops, int seg)
38ba30ba 1211{
dde7e6d1
AK		 1212 struct decode_cache *c = &ctxt->decode;
1213 unsigned long selector;
1214 int rc;
38ba30ba 1215
dde7e6d1
AK		 1216 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1217 if (rc != X86EMUL_CONTINUE)
1218 return rc;
1219
1220 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1221 return rc;
38ba30ba
GN		 1222}
1223
dde7e6d1
AK		 1224static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1225 struct x86_emulate_ops *ops)
38ba30ba 1226{
dde7e6d1
AK		 1227 struct decode_cache *c = &ctxt->decode;
1228 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1229 int rc = X86EMUL_CONTINUE;
1230 int reg = VCPU_REGS_RAX;
38ba30ba 1231
dde7e6d1
AK		 1232 while (reg <= VCPU_REGS_RDI) {
1233 (reg == VCPU_REGS_RSP) ?
1234 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1235
dde7e6d1 1236 emulate_push(ctxt, ops);
38ba30ba 1237
dde7e6d1
AK		 1238 rc = writeback(ctxt, ops);
1239 if (rc != X86EMUL_CONTINUE)
1240 return rc;
38ba30ba 1241
dde7e6d1 1242 ++reg;
38ba30ba 1243 }
38ba30ba 1244
dde7e6d1
AK		 1245 /* Disable writeback. */
1246 c->dst.type = OP_NONE;
1247
1248 return rc;
38ba30ba
GN		 1249}
1250
dde7e6d1
AK		 1251static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1252 struct x86_emulate_ops *ops)
38ba30ba 1253{
dde7e6d1
AK		 1254 struct decode_cache *c = &ctxt->decode;
1255 int rc = X86EMUL_CONTINUE;
1256 int reg = VCPU_REGS_RDI;
38ba30ba 1257
dde7e6d1
AK		 1258 while (reg >= VCPU_REGS_RAX) {
1259 if (reg == VCPU_REGS_RSP) {
1260 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1261 c->op_bytes);
1262 --reg;
1263 }
38ba30ba 1264
dde7e6d1
AK		 1265 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1266 if (rc != X86EMUL_CONTINUE)
1267 break;
1268 --reg;
38ba30ba 1269 }
dde7e6d1 1270 return rc;
38ba30ba
GN		 1271}
1272
6e154e56
MG		 1273int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1274 struct x86_emulate_ops *ops, int irq)
1275{
1276 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1277 int rc;
6e154e56
MG		 1278 struct desc_ptr dt;
1279 gva_t cs_addr;
1280 gva_t eip_addr;
1281 u16 cs, eip;
1282 u32 err;
1283
1284 /* TODO: Add limit checks */
1285 c->src.val = ctxt->eflags;
1286 emulate_push(ctxt, ops);
5c56e1cf
AK		 1287 rc = writeback(ctxt, ops);
1288 if (rc != X86EMUL_CONTINUE)
1289 return rc;
6e154e56
MG		 1290
1291 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1292
1293 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1294 emulate_push(ctxt, ops);
5c56e1cf
AK		 1295 rc = writeback(ctxt, ops);
1296 if (rc != X86EMUL_CONTINUE)
1297 return rc;
6e154e56
MG		 1298
1299 c->src.val = c->eip;
1300 emulate_push(ctxt, ops);
5c56e1cf
AK		 1301 rc = writeback(ctxt, ops);
1302 if (rc != X86EMUL_CONTINUE)
1303 return rc;
1304
1305 c->dst.type = OP_NONE;
6e154e56
MG		 1306
1307 ops->get_idt(&dt, ctxt->vcpu);
1308
1309 eip_addr = dt.address + (irq << 2);
1310 cs_addr = dt.address + (irq << 2) + 2;
1311
1312 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1313 if (rc != X86EMUL_CONTINUE)
1314 return rc;
1315
1316 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1317 if (rc != X86EMUL_CONTINUE)
1318 return rc;
1319
1320 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1321 if (rc != X86EMUL_CONTINUE)
1322 return rc;
1323
1324 c->eip = eip;
1325
1326 return rc;
1327}
1328
1329static int emulate_int(struct x86_emulate_ctxt *ctxt,
1330 struct x86_emulate_ops *ops, int irq)
1331{
1332 switch(ctxt->mode) {
1333 case X86EMUL_MODE_REAL:
1334 return emulate_int_real(ctxt, ops, irq);
1335 case X86EMUL_MODE_VM86:
1336 case X86EMUL_MODE_PROT16:
1337 case X86EMUL_MODE_PROT32:
1338 case X86EMUL_MODE_PROT64:
1339 default:
1340 /* Protected mode interrupts unimplemented yet */
1341 return X86EMUL_UNHANDLEABLE;
1342 }
1343}
1344
dde7e6d1
AK		 1345static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1346 struct x86_emulate_ops *ops)
38ba30ba 1347{
dde7e6d1
AK		 1348 struct decode_cache *c = &ctxt->decode;
1349 int rc = X86EMUL_CONTINUE;
1350 unsigned long temp_eip = 0;
1351 unsigned long temp_eflags = 0;
1352 unsigned long cs = 0;
1353 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1354 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1355 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1356 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1357
dde7e6d1 1358 /* TODO: Add stack limit check */
38ba30ba 1359
dde7e6d1 1360 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1361
dde7e6d1
AK		 1362 if (rc != X86EMUL_CONTINUE)
1363 return rc;
38ba30ba 1364
dde7e6d1
AK		 1365 if (temp_eip & ~0xffff) {
1366 emulate_gp(ctxt, 0);
1367 return X86EMUL_PROPAGATE_FAULT;
1368 }
38ba30ba 1369
dde7e6d1 1370 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1371
dde7e6d1
AK		 1372 if (rc != X86EMUL_CONTINUE)
1373 return rc;
38ba30ba 1374
dde7e6d1 1375 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1376
dde7e6d1
AK		 1377 if (rc != X86EMUL_CONTINUE)
1378 return rc;
38ba30ba 1379
dde7e6d1 1380 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1381
dde7e6d1
AK		 1382 if (rc != X86EMUL_CONTINUE)
1383 return rc;
38ba30ba 1384
dde7e6d1 1385 c->eip = temp_eip;
38ba30ba 1386
38ba30ba 1387
dde7e6d1
AK		 1388 if (c->op_bytes == 4)
1389 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1390 else if (c->op_bytes == 2) {
1391 ctxt->eflags &= ~0xffff;
1392 ctxt->eflags |= temp_eflags;
38ba30ba 1393 }
dde7e6d1
AK		 1394
1395 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1396 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1397
1398 return rc;
38ba30ba
GN		 1399}
1400
dde7e6d1
AK		 1401static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1402 struct x86_emulate_ops* ops)
c37eda13 1403{
dde7e6d1
AK		 1404 switch(ctxt->mode) {
1405 case X86EMUL_MODE_REAL:
1406 return emulate_iret_real(ctxt, ops);
1407 case X86EMUL_MODE_VM86:
1408 case X86EMUL_MODE_PROT16:
1409 case X86EMUL_MODE_PROT32:
1410 case X86EMUL_MODE_PROT64:
c37eda13 1411 default:
dde7e6d1
AK		 1412 /* iret from protected mode unimplemented yet */
1413 return X86EMUL_UNHANDLEABLE;
c37eda13 1414 }
c37eda13
WY		 1415}
1416
dde7e6d1 1417static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1418 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1419{
1420 struct decode_cache *c = &ctxt->decode;
1421
dde7e6d1 1422 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1423}
1424
dde7e6d1 1425static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1426{
05f086f8 1427 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1428 switch (c->modrm_reg) {
1429 case 0: /* rol */
05f086f8 1430 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1431 break;
1432 case 1: /* ror */
05f086f8 1433 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1434 break;
1435 case 2: /* rcl */
05f086f8 1436 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1437 break;
1438 case 3: /* rcr */
05f086f8 1439 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1440 break;
1441 case 4: /* sal/shl */
1442 case 6: /* sal/shl */
05f086f8 1443 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1444 break;
1445 case 5: /* shr */
05f086f8 1446 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1447 break;
1448 case 7: /* sar */
05f086f8 1449 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1450 break;
1451 }
1452}
1453
1454static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1455 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1456{
1457 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1458 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1459 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1460 u8 de = 0;
8cdbd2c9
LV		 1461
1462 switch (c->modrm_reg) {
1463 case 0 ... 1: /* test */
05f086f8 1464 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1465 break;
1466 case 2: /* not */
1467 c->dst.val = ~c->dst.val;
1468 break;
1469 case 3: /* neg */
05f086f8 1470 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1471 break;
3f9f53b0
MG		 1472 case 4: /* mul */
1473 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1474 break;
1475 case 5: /* imul */
1476 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1477 break;
1478 case 6: /* div */
34d1f490
AK		 1479 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1480 ctxt->eflags, de);
3f9f53b0
MG		 1481 break;
1482 case 7: /* idiv */
34d1f490
AK		 1483 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1484 ctxt->eflags, de);
3f9f53b0 1485 break;
8cdbd2c9 1486 default:
8c5eee30 1487 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1488 }
34d1f490
AK		 1489 if (de)
1490 return emulate_de(ctxt);
8c5eee30 1491 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1492}
1493
1494static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1495 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1496{
1497 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1498
1499 switch (c->modrm_reg) {
1500 case 0: /* inc */
05f086f8 1501 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1502 break;
1503 case 1: /* dec */
05f086f8 1504 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1505 break;
d19292e4
MG		 1506 case 2: /* call near abs */ {
1507 long int old_eip;
1508 old_eip = c->eip;
1509 c->eip = c->src.val;
1510 c->src.val = old_eip;
79168fd1 1511 emulate_push(ctxt, ops);
d19292e4
MG		 1512 break;
1513 }
8cdbd2c9 1514 case 4: /* jmp abs */
fd60754e 1515 c->eip = c->src.val;
8cdbd2c9
LV		 1516 break;
1517 case 6: /* push */
79168fd1 1518 emulate_push(ctxt, ops);
8cdbd2c9 1519 break;
8cdbd2c9 1520 }
1b30eaa8 1521 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1522}
1523
1524static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1525 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1526{
1527 struct decode_cache *c = &ctxt->decode;
16518d5a 1528 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1529
1530 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1531 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1532 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1533 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1534 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1535 } else {
16518d5a
AK		 1536 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1537 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1538
05f086f8 1539 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1540 }
1b30eaa8 1541 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1542}
1543
a77ab5ea
AK		 1544static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1545 struct x86_emulate_ops *ops)
1546{
1547 struct decode_cache *c = &ctxt->decode;
1548 int rc;
1549 unsigned long cs;
1550
1551 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1552 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1553 return rc;
1554 if (c->op_bytes == 4)
1555 c->eip = (u32)c->eip;
1556 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1557 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1558 return rc;
2e873022 1559 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1560 return rc;
1561}
1562
09b5f4d3
WY		 1563static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1564 struct x86_emulate_ops *ops, int seg)
1565{
1566 struct decode_cache *c = &ctxt->decode;
1567 unsigned short sel;
1568 int rc;
1569
1570 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1571
1572 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1573 if (rc != X86EMUL_CONTINUE)
1574 return rc;
1575
1576 c->dst.val = c->src.val;
1577 return rc;
1578}
1579
e66bb2cc
AP		 1580static inline void
1581setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1582 struct x86_emulate_ops *ops, struct desc_struct *cs,
1583 struct desc_struct *ss)
e66bb2cc 1584{
79168fd1
GN		 1585 memset(cs, 0, sizeof(struct desc_struct));
1586 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1587 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1588
1589 cs->l = 0; /* will be adjusted later */
79168fd1 1590 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1591 cs->g = 1; /* 4kb granularity */
79168fd1 1592 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1593 cs->type = 0x0b; /* Read, Execute, Accessed */
1594 cs->s = 1;
1595 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1596 cs->p = 1;
1597 cs->d = 1;
e66bb2cc 1598
79168fd1
GN		 1599 set_desc_base(ss, 0); /* flat segment */
1600 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1601 ss->g = 1; /* 4kb granularity */
1602 ss->s = 1;
1603 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1604 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1605 ss->dpl = 0;
79168fd1 1606 ss->p = 1;
e66bb2cc
AP		 1607}
1608
1609static int
3fb1b5db 1610emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1611{
1612 struct decode_cache *c = &ctxt->decode;
79168fd1 1613 struct desc_struct cs, ss;
e66bb2cc 1614 u64 msr_data;
79168fd1 1615 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1616
1617 /* syscall is not available in real mode */
2e901c4c
GN		 1618 if (ctxt->mode == X86EMUL_MODE_REAL ||
1619 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1620 emulate_ud(ctxt);
2e901c4c
GN		 1621 return X86EMUL_PROPAGATE_FAULT;
1622 }
e66bb2cc 1623
79168fd1 1624 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1625
3fb1b5db 1626 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1627 msr_data >>= 32;
79168fd1
GN		 1628 cs_sel = (u16)(msr_data & 0xfffc);
1629 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1630
1631 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1632 cs.d = 0;
e66bb2cc
AP		 1633 cs.l = 1;
1634 }
79168fd1
GN		 1635 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1636 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1637 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1638 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1639
1640 c->regs[VCPU_REGS_RCX] = c->eip;
1641 if (is_long_mode(ctxt->vcpu)) {
1642#ifdef CONFIG_X86_64
1643 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1644
3fb1b5db
GN		 1645 ops->get_msr(ctxt->vcpu,
1646 ctxt->mode == X86EMUL_MODE_PROT64 ?
1647 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1648 c->eip = msr_data;
1649
3fb1b5db 1650 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1651 ctxt->eflags &= ~(msr_data | EFLG_RF);
1652#endif
1653 } else {
1654 /* legacy mode */
3fb1b5db 1655 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1656 c->eip = (u32)msr_data;
1657
1658 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1659 }
1660
e54cfa97 1661 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1662}
1663
8c604352 1664static int
3fb1b5db 1665emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1666{
1667 struct decode_cache *c = &ctxt->decode;
79168fd1 1668 struct desc_struct cs, ss;
8c604352 1669 u64 msr_data;
79168fd1 1670 u16 cs_sel, ss_sel;
8c604352 1671
a0044755
GN		 1672 /* inject #GP if in real mode */
1673 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1674 emulate_gp(ctxt, 0);
2e901c4c 1675 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1676 }
1677
1678 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1679 * Therefore, we inject an #UD.
1680 */
2e901c4c 1681 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1682 emulate_ud(ctxt);
2e901c4c
GN		 1683 return X86EMUL_PROPAGATE_FAULT;
1684 }
8c604352 1685
79168fd1 1686 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1687
3fb1b5db 1688 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1689 switch (ctxt->mode) {
1690 case X86EMUL_MODE_PROT32:
1691 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1692 emulate_gp(ctxt, 0);
e54cfa97 1693 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1694 }
1695 break;
1696 case X86EMUL_MODE_PROT64:
1697 if (msr_data == 0x0) {
54b8486f 1698 emulate_gp(ctxt, 0);
e54cfa97 1699 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1700 }
1701 break;
1702 }
1703
1704 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1705 cs_sel = (u16)msr_data;
1706 cs_sel &= ~SELECTOR_RPL_MASK;
1707 ss_sel = cs_sel + 8;
1708 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1709 if (ctxt->mode == X86EMUL_MODE_PROT64
1710 || is_long_mode(ctxt->vcpu)) {
79168fd1 1711 cs.d = 0;
8c604352
AP		 1712 cs.l = 1;
1713 }
1714
79168fd1
GN		 1715 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1716 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1717 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1718 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1719
3fb1b5db 1720 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1721 c->eip = msr_data;
1722
3fb1b5db 1723 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1724 c->regs[VCPU_REGS_RSP] = msr_data;
1725
e54cfa97 1726 return X86EMUL_CONTINUE;
8c604352
AP		 1727}
1728
4668f050 1729static int
3fb1b5db 1730emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1731{
1732 struct decode_cache *c = &ctxt->decode;
79168fd1 1733 struct desc_struct cs, ss;
4668f050
AP		 1734 u64 msr_data;
1735 int usermode;
79168fd1 1736 u16 cs_sel, ss_sel;
4668f050 1737
a0044755
GN		 1738 /* inject #GP if in real mode or Virtual 8086 mode */
1739 if (ctxt->mode == X86EMUL_MODE_REAL ||
1740 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1741 emulate_gp(ctxt, 0);
2e901c4c 1742 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1743 }
1744
79168fd1 1745 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1746
1747 if ((c->rex_prefix & 0x8) != 0x0)
1748 usermode = X86EMUL_MODE_PROT64;
1749 else
1750 usermode = X86EMUL_MODE_PROT32;
1751
1752 cs.dpl = 3;
1753 ss.dpl = 3;
3fb1b5db 1754 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1755 switch (usermode) {
1756 case X86EMUL_MODE_PROT32:
79168fd1 1757 cs_sel = (u16)(msr_data + 16);
4668f050 1758 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1759 emulate_gp(ctxt, 0);
e54cfa97 1760 return X86EMUL_PROPAGATE_FAULT;
4668f050 1761 }
79168fd1 1762 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1763 break;
1764 case X86EMUL_MODE_PROT64:
79168fd1 1765 cs_sel = (u16)(msr_data + 32);
4668f050 1766 if (msr_data == 0x0) {
54b8486f 1767 emulate_gp(ctxt, 0);
e54cfa97 1768 return X86EMUL_PROPAGATE_FAULT;
4668f050 1769 }
79168fd1
GN		 1770 ss_sel = cs_sel + 8;
1771 cs.d = 0;
4668f050
AP		 1772 cs.l = 1;
1773 break;
1774 }
79168fd1
GN		 1775 cs_sel |= SELECTOR_RPL_MASK;
1776 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1777
79168fd1
GN		 1778 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1779 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1780 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1781 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1782
bdb475a3
GN		 1783 c->eip = c->regs[VCPU_REGS_RDX];
1784 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1785
e54cfa97 1786 return X86EMUL_CONTINUE;
4668f050
AP		 1787}
1788
9c537244
GN		 1789static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1790 struct x86_emulate_ops *ops)
f850e2e6
GN		 1791{
1792 int iopl;
1793 if (ctxt->mode == X86EMUL_MODE_REAL)
1794 return false;
1795 if (ctxt->mode == X86EMUL_MODE_VM86)
1796 return true;
1797 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1798 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1799}
1800
1801static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1802 struct x86_emulate_ops *ops,
1803 u16 port, u16 len)
1804{
79168fd1 1805 struct desc_struct tr_seg;
f850e2e6
GN		 1806 int r;
1807 u16 io_bitmap_ptr;
1808 u8 perm, bit_idx = port & 0x7;
1809 unsigned mask = (1 << len) - 1;
1810
79168fd1
GN		 1811 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1812 if (!tr_seg.p)
f850e2e6 1813 return false;
79168fd1 1814 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1815 return false;
79168fd1
GN		 1816 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1817 ctxt->vcpu, NULL);
f850e2e6
GN		 1818 if (r != X86EMUL_CONTINUE)
1819 return false;
79168fd1 1820 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1821 return false;
79168fd1
GN		 1822 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1823 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1824 if (r != X86EMUL_CONTINUE)
1825 return false;
1826 if ((perm >> bit_idx) & mask)
1827 return false;
1828 return true;
1829}
1830
1831static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1832 struct x86_emulate_ops *ops,
1833 u16 port, u16 len)
1834{
4fc40f07
GN		 1835 if (ctxt->perm_ok)
1836 return true;
1837
9c537244 1838 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1839 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1840 return false;
4fc40f07
GN		 1841
1842 ctxt->perm_ok = true;
1843
f850e2e6
GN		 1844 return true;
1845}
1846
38ba30ba
GN		 1847static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1848 struct x86_emulate_ops *ops,
1849 struct tss_segment_16 *tss)
1850{
1851 struct decode_cache *c = &ctxt->decode;
1852
1853 tss->ip = c->eip;
1854 tss->flag = ctxt->eflags;
1855 tss->ax = c->regs[VCPU_REGS_RAX];
1856 tss->cx = c->regs[VCPU_REGS_RCX];
1857 tss->dx = c->regs[VCPU_REGS_RDX];
1858 tss->bx = c->regs[VCPU_REGS_RBX];
1859 tss->sp = c->regs[VCPU_REGS_RSP];
1860 tss->bp = c->regs[VCPU_REGS_RBP];
1861 tss->si = c->regs[VCPU_REGS_RSI];
1862 tss->di = c->regs[VCPU_REGS_RDI];
1863
1864 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1865 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1866 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1867 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1868 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1869}
1870
1871static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1872 struct x86_emulate_ops *ops,
1873 struct tss_segment_16 *tss)
1874{
1875 struct decode_cache *c = &ctxt->decode;
1876 int ret;
1877
1878 c->eip = tss->ip;
1879 ctxt->eflags = tss->flag | 2;
1880 c->regs[VCPU_REGS_RAX] = tss->ax;
1881 c->regs[VCPU_REGS_RCX] = tss->cx;
1882 c->regs[VCPU_REGS_RDX] = tss->dx;
1883 c->regs[VCPU_REGS_RBX] = tss->bx;
1884 c->regs[VCPU_REGS_RSP] = tss->sp;
1885 c->regs[VCPU_REGS_RBP] = tss->bp;
1886 c->regs[VCPU_REGS_RSI] = tss->si;
1887 c->regs[VCPU_REGS_RDI] = tss->di;
1888
1889 /*
1890 * SDM says that segment selectors are loaded before segment
1891 * descriptors
1892 */
1893 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1894 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1895 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1896 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1897 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1898
1899 /*
1900 * Now load segment descriptors. If fault happenes at this stage
1901 * it is handled in a context of new task
1902 */
1903 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1904 if (ret != X86EMUL_CONTINUE)
1905 return ret;
1906 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1907 if (ret != X86EMUL_CONTINUE)
1908 return ret;
1909 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1910 if (ret != X86EMUL_CONTINUE)
1911 return ret;
1912 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1913 if (ret != X86EMUL_CONTINUE)
1914 return ret;
1915 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1916 if (ret != X86EMUL_CONTINUE)
1917 return ret;
1918
1919 return X86EMUL_CONTINUE;
1920}
1921
1922static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1923 struct x86_emulate_ops *ops,
1924 u16 tss_selector, u16 old_tss_sel,
1925 ulong old_tss_base, struct desc_struct *new_desc)
1926{
1927 struct tss_segment_16 tss_seg;
1928 int ret;
1929 u32 err, new_tss_base = get_desc_base(new_desc);
1930
1931 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1932 &err);
1933 if (ret == X86EMUL_PROPAGATE_FAULT) {
1934 /* FIXME: need to provide precise fault address */
8df25a32 1935 emulate_pf(ctxt);
38ba30ba
GN		 1936 return ret;
1937 }
1938
1939 save_state_to_tss16(ctxt, ops, &tss_seg);
1940
1941 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1942 &err);
1943 if (ret == X86EMUL_PROPAGATE_FAULT) {
1944 /* FIXME: need to provide precise fault address */
8df25a32 1945 emulate_pf(ctxt);
38ba30ba
GN		 1946 return ret;
1947 }
1948
1949 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1950 &err);
1951 if (ret == X86EMUL_PROPAGATE_FAULT) {
1952 /* FIXME: need to provide precise fault address */
8df25a32 1953 emulate_pf(ctxt);
38ba30ba
GN		 1954 return ret;
1955 }
1956
1957 if (old_tss_sel != 0xffff) {
1958 tss_seg.prev_task_link = old_tss_sel;
1959
1960 ret = ops->write_std(new_tss_base,
1961 &tss_seg.prev_task_link,
1962 sizeof tss_seg.prev_task_link,
1963 ctxt->vcpu, &err);
1964 if (ret == X86EMUL_PROPAGATE_FAULT) {
1965 /* FIXME: need to provide precise fault address */
8df25a32 1966 emulate_pf(ctxt);
38ba30ba
GN		 1967 return ret;
1968 }
1969 }
1970
1971 return load_state_from_tss16(ctxt, ops, &tss_seg);
1972}
1973
1974static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1975 struct x86_emulate_ops *ops,
1976 struct tss_segment_32 *tss)
1977{
1978 struct decode_cache *c = &ctxt->decode;
1979
1980 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1981 tss->eip = c->eip;
1982 tss->eflags = ctxt->eflags;
1983 tss->eax = c->regs[VCPU_REGS_RAX];
1984 tss->ecx = c->regs[VCPU_REGS_RCX];
1985 tss->edx = c->regs[VCPU_REGS_RDX];
1986 tss->ebx = c->regs[VCPU_REGS_RBX];
1987 tss->esp = c->regs[VCPU_REGS_RSP];
1988 tss->ebp = c->regs[VCPU_REGS_RBP];
1989 tss->esi = c->regs[VCPU_REGS_RSI];
1990 tss->edi = c->regs[VCPU_REGS_RDI];
1991
1992 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1993 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1994 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1995 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1996 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1997 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1998 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1999}
2000
2001static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2002 struct x86_emulate_ops *ops,
2003 struct tss_segment_32 *tss)
2004{
2005 struct decode_cache *c = &ctxt->decode;
2006 int ret;
2007
0f12244f 2008 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2009 emulate_gp(ctxt, 0);
0f12244f
GN		 2010 return X86EMUL_PROPAGATE_FAULT;
2011 }
38ba30ba
GN		 2012 c->eip = tss->eip;
2013 ctxt->eflags = tss->eflags | 2;
2014 c->regs[VCPU_REGS_RAX] = tss->eax;
2015 c->regs[VCPU_REGS_RCX] = tss->ecx;
2016 c->regs[VCPU_REGS_RDX] = tss->edx;
2017 c->regs[VCPU_REGS_RBX] = tss->ebx;
2018 c->regs[VCPU_REGS_RSP] = tss->esp;
2019 c->regs[VCPU_REGS_RBP] = tss->ebp;
2020 c->regs[VCPU_REGS_RSI] = tss->esi;
2021 c->regs[VCPU_REGS_RDI] = tss->edi;
2022
2023 /*
2024 * SDM says that segment selectors are loaded before segment
2025 * descriptors
2026 */
2027 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2028 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2029 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2030 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2031 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2032 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2033 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2034
2035 /*
2036 * Now load segment descriptors. If fault happenes at this stage
2037 * it is handled in a context of new task
2038 */
2039 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2040 if (ret != X86EMUL_CONTINUE)
2041 return ret;
2042 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2043 if (ret != X86EMUL_CONTINUE)
2044 return ret;
2045 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2046 if (ret != X86EMUL_CONTINUE)
2047 return ret;
2048 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2049 if (ret != X86EMUL_CONTINUE)
2050 return ret;
2051 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2052 if (ret != X86EMUL_CONTINUE)
2053 return ret;
2054 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2055 if (ret != X86EMUL_CONTINUE)
2056 return ret;
2057 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2058 if (ret != X86EMUL_CONTINUE)
2059 return ret;
2060
2061 return X86EMUL_CONTINUE;
2062}
2063
2064static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2065 struct x86_emulate_ops *ops,
2066 u16 tss_selector, u16 old_tss_sel,
2067 ulong old_tss_base, struct desc_struct *new_desc)
2068{
2069 struct tss_segment_32 tss_seg;
2070 int ret;
2071 u32 err, new_tss_base = get_desc_base(new_desc);
2072
2073 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2074 &err);
2075 if (ret == X86EMUL_PROPAGATE_FAULT) {
2076 /* FIXME: need to provide precise fault address */
8df25a32 2077 emulate_pf(ctxt);
38ba30ba
GN		 2078 return ret;
2079 }
2080
2081 save_state_to_tss32(ctxt, ops, &tss_seg);
2082
2083 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2084 &err);
2085 if (ret == X86EMUL_PROPAGATE_FAULT) {
2086 /* FIXME: need to provide precise fault address */
8df25a32 2087 emulate_pf(ctxt);
38ba30ba
GN		 2088 return ret;
2089 }
2090
2091 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2092 &err);
2093 if (ret == X86EMUL_PROPAGATE_FAULT) {
2094 /* FIXME: need to provide precise fault address */
8df25a32 2095 emulate_pf(ctxt);
38ba30ba
GN		 2096 return ret;
2097 }
2098
2099 if (old_tss_sel != 0xffff) {
2100 tss_seg.prev_task_link = old_tss_sel;
2101
2102 ret = ops->write_std(new_tss_base,
2103 &tss_seg.prev_task_link,
2104 sizeof tss_seg.prev_task_link,
2105 ctxt->vcpu, &err);
2106 if (ret == X86EMUL_PROPAGATE_FAULT) {
2107 /* FIXME: need to provide precise fault address */
8df25a32 2108 emulate_pf(ctxt);
38ba30ba
GN		 2109 return ret;
2110 }
2111 }
2112
2113 return load_state_from_tss32(ctxt, ops, &tss_seg);
2114}
2115
2116static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2117 struct x86_emulate_ops *ops,
2118 u16 tss_selector, int reason,
2119 bool has_error_code, u32 error_code)
38ba30ba
GN		 2120{
2121 struct desc_struct curr_tss_desc, next_tss_desc;
2122 int ret;
2123 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2124 ulong old_tss_base =
5951c442 2125 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2126 u32 desc_limit;
38ba30ba
GN		 2127
2128 /* FIXME: old_tss_base == ~0 ? */
2129
2130 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
2133 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
2136
2137 /* FIXME: check that next_tss_desc is tss */
2138
2139 if (reason != TASK_SWITCH_IRET) {
2140 if ((tss_selector & 3) > next_tss_desc.dpl ||
2141 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2142 emulate_gp(ctxt, 0);
38ba30ba
GN		 2143 return X86EMUL_PROPAGATE_FAULT;
2144 }
2145 }
2146
ceffb459
GN		 2147 desc_limit = desc_limit_scaled(&next_tss_desc);
2148 if (!next_tss_desc.p ||
2149 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2150 desc_limit < 0x2b)) {
54b8486f 2151 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2152 return X86EMUL_PROPAGATE_FAULT;
2153 }
2154
2155 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2156 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2157 write_segment_descriptor(ctxt, ops, old_tss_sel,
2158 &curr_tss_desc);
2159 }
2160
2161 if (reason == TASK_SWITCH_IRET)
2162 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2163
2164 /* set back link to prev task only if NT bit is set in eflags
2165 note that old_tss_sel is not used afetr this point */
2166 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2167 old_tss_sel = 0xffff;
2168
2169 if (next_tss_desc.type & 8)
2170 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2171 old_tss_base, &next_tss_desc);
2172 else
2173 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2174 old_tss_base, &next_tss_desc);
0760d448
JK		 2175 if (ret != X86EMUL_CONTINUE)
2176 return ret;
38ba30ba
GN		 2177
2178 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2179 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2180
2181 if (reason != TASK_SWITCH_IRET) {
2182 next_tss_desc.type |= (1 << 1); /* set busy flag */
2183 write_segment_descriptor(ctxt, ops, tss_selector,
2184 &next_tss_desc);
2185 }
2186
2187 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2188 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2189 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2190
e269fb21
JK		 2191 if (has_error_code) {
2192 struct decode_cache *c = &ctxt->decode;
2193
2194 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2195 c->lock_prefix = 0;
2196 c->src.val = (unsigned long) error_code;
79168fd1 2197 emulate_push(ctxt, ops);
e269fb21
JK		 2198 }
2199
38ba30ba
GN		 2200 return ret;
2201}
2202
2203int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2204 u16 tss_selector, int reason,
2205 bool has_error_code, u32 error_code)
38ba30ba 2206{
9aabc88f 2207 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2208 struct decode_cache *c = &ctxt->decode;
2209 int rc;
2210
38ba30ba 2211 c->eip = ctxt->eip;
e269fb21 2212 c->dst.type = OP_NONE;
38ba30ba 2213
e269fb21
JK		 2214 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2215 has_error_code, error_code);
38ba30ba
GN		 2216
2217 if (rc == X86EMUL_CONTINUE) {
e269fb21 2218 rc = writeback(ctxt, ops);
95c55886
GN		 2219 if (rc == X86EMUL_CONTINUE)
2220 ctxt->eip = c->eip;
38ba30ba
GN		 2221 }
2222
19d04437 2223 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2224}
2225
a682e354 2226static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2227 int reg, struct operand *op)
a682e354
GN		 2228{
2229 struct decode_cache *c = &ctxt->decode;
2230 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2231
d9271123 2232 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2233 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2234}
2235
63540382
AK		 2236static int em_push(struct x86_emulate_ctxt *ctxt)
2237{
2238 emulate_push(ctxt, ctxt->ops);
2239 return X86EMUL_CONTINUE;
2240}
2241
7af04fc0
AK		 2242static int em_das(struct x86_emulate_ctxt *ctxt)
2243{
2244 struct decode_cache *c = &ctxt->decode;
2245 u8 al, old_al;
2246 bool af, cf, old_cf;
2247
2248 cf = ctxt->eflags & X86_EFLAGS_CF;
2249 al = c->dst.val;
2250
2251 old_al = al;
2252 old_cf = cf;
2253 cf = false;
2254 af = ctxt->eflags & X86_EFLAGS_AF;
2255 if ((al & 0x0f) > 9 || af) {
2256 al -= 6;
2257 cf = old_cf | (al >= 250);
2258 af = true;
2259 } else {
2260 af = false;
2261 }
2262 if (old_al > 0x99 || old_cf) {
2263 al -= 0x60;
2264 cf = true;
2265 }
2266
2267 c->dst.val = al;
2268 /* Set PF, ZF, SF */
2269 c->src.type = OP_IMM;
2270 c->src.val = 0;
2271 c->src.bytes = 1;
2272 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2273 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2274 if (cf)
2275 ctxt->eflags |= X86_EFLAGS_CF;
2276 if (af)
2277 ctxt->eflags |= X86_EFLAGS_AF;
2278 return X86EMUL_CONTINUE;
2279}
2280
0ef753b8
AK		 2281static int em_call_far(struct x86_emulate_ctxt *ctxt)
2282{
2283 struct decode_cache *c = &ctxt->decode;
2284 u16 sel, old_cs;
2285 ulong old_eip;
2286 int rc;
2287
2288 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2289 old_eip = c->eip;
2290
2291 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2292 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2293 return X86EMUL_CONTINUE;
2294
2295 c->eip = 0;
2296 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2297
2298 c->src.val = old_cs;
2299 emulate_push(ctxt, ctxt->ops);
2300 rc = writeback(ctxt, ctxt->ops);
2301 if (rc != X86EMUL_CONTINUE)
2302 return rc;
2303
2304 c->src.val = old_eip;
2305 emulate_push(ctxt, ctxt->ops);
2306 rc = writeback(ctxt, ctxt->ops);
2307 if (rc != X86EMUL_CONTINUE)
2308 return rc;
2309
2310 c->dst.type = OP_NONE;
2311
2312 return X86EMUL_CONTINUE;
2313}
2314
40ece7c7
AK		 2315static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2316{
2317 struct decode_cache *c = &ctxt->decode;
2318 int rc;
2319
2320 c->dst.type = OP_REG;
2321 c->dst.addr.reg = &c->eip;
2322 c->dst.bytes = c->op_bytes;
2323 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2324 if (rc != X86EMUL_CONTINUE)
2325 return rc;
2326 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2327 return X86EMUL_CONTINUE;
2328}
2329
5c82aa29 2330static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2331{
2332 struct decode_cache *c = &ctxt->decode;
2333
f3a1b9f4
AK		 2334 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2335 return X86EMUL_CONTINUE;
2336}
2337
5c82aa29
AK		 2338static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2339{
2340 struct decode_cache *c = &ctxt->decode;
2341
2342 c->dst.val = c->src2.val;
2343 return em_imul(ctxt);
2344}
2345
61429142
AK		 2346static int em_cwd(struct x86_emulate_ctxt *ctxt)
2347{
2348 struct decode_cache *c = &ctxt->decode;
2349
2350 c->dst.type = OP_REG;
2351 c->dst.bytes = c->src.bytes;
2352 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2353 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2354
2355 return X86EMUL_CONTINUE;
2356}
2357
48bb5d3c
AK		 2358static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2359{
2360 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2361 struct decode_cache *c = &ctxt->decode;
2362 u64 tsc = 0;
2363
2364 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2365 emulate_gp(ctxt, 0);
2366 return X86EMUL_PROPAGATE_FAULT;
2367 }
2368 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2369 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2370 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2371 return X86EMUL_CONTINUE;
2372}
2373
b9eac5f4
AK		 2374static int em_mov(struct x86_emulate_ctxt *ctxt)
2375{
2376 struct decode_cache *c = &ctxt->decode;
2377 c->dst.val = c->src.val;
2378 return X86EMUL_CONTINUE;
2379}
2380
73fba5f4
AK		 2381#define D(_y) { .flags = (_y) }
2382#define N D(0)
2383#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2384#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2385#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2386
8d8f4e9f
AK		 2387#define D2bv(_f) D((_f) | ByteOp), D(_f)
2388#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2389
6230f7fc
AK		 2390#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2391 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2392 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2393
2394
73fba5f4
AK		 2395static struct opcode group1[] = {
2396 X7(D(Lock)), N
2397};
2398
2399static struct opcode group1A[] = {
2400 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2401};
2402
2403static struct opcode group3[] = {
2404 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2405 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2406 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2407};
2408
2409static struct opcode group4[] = {
2410 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2411 N, N, N, N, N, N,
2412};
2413
2414static struct opcode group5[] = {
2415 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2416 D(SrcMem | ModRM | Stack),
2417 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2418 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2419 D(SrcMem | ModRM | Stack), N,
2420};
2421
2422static struct group_dual group7 = { {
2423 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2424 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2425 D(SrcMem16 | ModRM | Mov | Priv),
2426 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4
AK		 2427}, {
2428 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2429 D(SrcNone | ModRM | DstMem | Mov), N,
2430 D(SrcMem16 | ModRM | Mov | Priv), N,
2431} };
2432
2433static struct opcode group8[] = {
2434 N, N, N, N,
2435 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2436 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2437};
2438
2439static struct group_dual group9 = { {
2440 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2441}, {
2442 N, N, N, N, N, N, N, N,
2443} };
2444
a4d4a7c1
AK		 2445static struct opcode group11[] = {
2446 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2447};
2448
73fba5f4
AK		 2449static struct opcode opcode_table[256] = {
2450 /* 0x00 - 0x07 */
6230f7fc 2451 D6ALU(Lock),
73fba5f4
AK		 2452 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2453 /* 0x08 - 0x0F */
6230f7fc 2454 D6ALU(Lock),
73fba5f4
AK		 2455 D(ImplicitOps | Stack | No64), N,
2456 /* 0x10 - 0x17 */
6230f7fc 2457 D6ALU(Lock),
73fba5f4
AK		 2458 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2459 /* 0x18 - 0x1F */
6230f7fc 2460 D6ALU(Lock),
73fba5f4
AK		 2461 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2462 /* 0x20 - 0x27 */
6230f7fc 2463 D6ALU(Lock), N, N,
73fba5f4 2464 /* 0x28 - 0x2F */
6230f7fc 2465 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2466 /* 0x30 - 0x37 */
6230f7fc 2467 D6ALU(Lock), N, N,
73fba5f4 2468 /* 0x38 - 0x3F */
6230f7fc 2469 D6ALU(0), N, N,
73fba5f4
AK		 2470 /* 0x40 - 0x4F */
2471 X16(D(DstReg)),
2472 /* 0x50 - 0x57 */
63540382 2473 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2474 /* 0x58 - 0x5F */
2475 X8(D(DstReg | Stack)),
2476 /* 0x60 - 0x67 */
2477 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2478 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2479 N, N, N, N,
2480 /* 0x68 - 0x6F */
d46164db
AK		 2481 I(SrcImm | Mov | Stack, em_push),
2482 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2483 I(SrcImmByte | Mov | Stack, em_push),
2484 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2485 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2486 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2487 /* 0x70 - 0x7F */
2488 X16(D(SrcImmByte)),
2489 /* 0x80 - 0x87 */
2490 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2491 G(DstMem | SrcImm | ModRM | Group, group1),
2492 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2493 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2494 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2495 /* 0x88 - 0x8F */
b9eac5f4
AK		 2496 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2497 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2498 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2499 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2500 /* 0x90 - 0x97 */
3d9e77df 2501 X8(D(SrcAcc | DstReg)),
73fba5f4 2502 /* 0x98 - 0x9F */
61429142 2503 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2504 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2505 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2506 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2507 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2508 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2509 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2510 D2bv(SrcSI | DstDI | String),
73fba5f4 2511 /* 0xA8 - 0xAF */
50748613 2512 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2513 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2514 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2515 D2bv(SrcAcc | DstDI | String),
73fba5f4 2516 /* 0xB0 - 0xB7 */
b9eac5f4 2517 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2518 /* 0xB8 - 0xBF */
b9eac5f4 2519 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2520 /* 0xC0 - 0xC7 */
d2c6c7ad 2521 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2522 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2523 D(ImplicitOps | Stack),
09b5f4d3 2524 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2525 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2526 /* 0xC8 - 0xCF */
2527 N, N, N, D(ImplicitOps | Stack),
2528 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2529 /* 0xD0 - 0xD7 */
d2c6c7ad 2530 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2531 N, N, N, N,
2532 /* 0xD8 - 0xDF */
2533 N, N, N, N, N, N, N, N,
2534 /* 0xE0 - 0xE7 */
e4abac67 2535 X4(D(SrcImmByte)),
d269e396 2536 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2537 /* 0xE8 - 0xEF */
2538 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2539 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2540 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2541 /* 0xF0 - 0xF7 */
2542 N, N, N, N,
2543 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2544 /* 0xF8 - 0xFF */
8744aa9a 2545 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2546 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2547};
2548
2549static struct opcode twobyte_table[256] = {
2550 /* 0x00 - 0x0F */
2551 N, GD(0, &group7), N, N,
2552 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2553 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2554 N, D(ImplicitOps | ModRM), N, N,
2555 /* 0x10 - 0x1F */
2556 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2557 /* 0x20 - 0x2F */
b27f3856
AK		 2558 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2559 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2560 N, N, N, N,
2561 N, N, N, N, N, N, N, N,
2562 /* 0x30 - 0x3F */
48bb5d3c
AK		 2563 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2564 D(ImplicitOps | Priv), N,
73fba5f4
AK		 2565 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2566 N, N, N, N, N, N, N, N,
2567 /* 0x40 - 0x4F */
2568 X16(D(DstReg | SrcMem | ModRM | Mov)),
2569 /* 0x50 - 0x5F */
2570 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2571 /* 0x60 - 0x6F */
2572 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2573 /* 0x70 - 0x7F */
2574 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2575 /* 0x80 - 0x8F */
2576 X16(D(SrcImm)),
2577 /* 0x90 - 0x9F */
ee45b58e 2578 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2579 /* 0xA0 - 0xA7 */
2580 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2581 N, D(DstMem | SrcReg | ModRM | BitOp),
2582 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2583 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2584 /* 0xA8 - 0xAF */
2585 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2586 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2587 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2588 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2589 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2590 /* 0xB0 - 0xB7 */
739ae406 2591 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2592 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2593 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2594 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2595 /* 0xB8 - 0xBF */
2596 N, N,
ba7ff2b7 2597 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2598 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2599 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2600 /* 0xC0 - 0xCF */
739ae406 2601 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2602 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2603 N, N, N, GD(0, &group9),
2604 N, N, N, N, N, N, N, N,
2605 /* 0xD0 - 0xDF */
2606 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2607 /* 0xE0 - 0xEF */
2608 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2609 /* 0xF0 - 0xFF */
2610 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2611};
2612
2613#undef D
2614#undef N
2615#undef G
2616#undef GD
2617#undef I
2618
8d8f4e9f
AK		 2619#undef D2bv
2620#undef I2bv
6230f7fc 2621#undef D6ALU
8d8f4e9f 2622
39f21ee5
AK		 2623static unsigned imm_size(struct decode_cache *c)
2624{
2625 unsigned size;
2626
2627 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2628 if (size == 8)
2629 size = 4;
2630 return size;
2631}
2632
2633static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2634 unsigned size, bool sign_extension)
2635{
2636 struct decode_cache *c = &ctxt->decode;
2637 struct x86_emulate_ops *ops = ctxt->ops;
2638 int rc = X86EMUL_CONTINUE;
2639
2640 op->type = OP_IMM;
2641 op->bytes = size;
2642 op->addr.mem = c->eip;
2643 /* NB. Immediates are sign-extended as necessary. */
2644 switch (op->bytes) {
2645 case 1:
2646 op->val = insn_fetch(s8, 1, c->eip);
2647 break;
2648 case 2:
2649 op->val = insn_fetch(s16, 2, c->eip);
2650 break;
2651 case 4:
2652 op->val = insn_fetch(s32, 4, c->eip);
2653 break;
2654 }
2655 if (!sign_extension) {
2656 switch (op->bytes) {
2657 case 1:
2658 op->val &= 0xff;
2659 break;
2660 case 2:
2661 op->val &= 0xffff;
2662 break;
2663 case 4:
2664 op->val &= 0xffffffff;
2665 break;
2666 }
2667 }
2668done:
2669 return rc;
2670}
2671
dde7e6d1
AK		 2672int
2673x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2674{
2675 struct x86_emulate_ops *ops = ctxt->ops;
2676 struct decode_cache *c = &ctxt->decode;
2677 int rc = X86EMUL_CONTINUE;
2678 int mode = ctxt->mode;
2679 int def_op_bytes, def_ad_bytes, dual, goffset;
2680 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2681 struct operand memop = { .type = OP_NONE };
dde7e6d1 2682
dde7e6d1
AK		 2683 c->eip = ctxt->eip;
2684 c->fetch.start = c->fetch.end = c->eip;
2685 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2686
2687 switch (mode) {
2688 case X86EMUL_MODE_REAL:
2689 case X86EMUL_MODE_VM86:
2690 case X86EMUL_MODE_PROT16:
2691 def_op_bytes = def_ad_bytes = 2;
2692 break;
2693 case X86EMUL_MODE_PROT32:
2694 def_op_bytes = def_ad_bytes = 4;
2695 break;
2696#ifdef CONFIG_X86_64
2697 case X86EMUL_MODE_PROT64:
2698 def_op_bytes = 4;
2699 def_ad_bytes = 8;
2700 break;
2701#endif
2702 default:
2703 return -1;
2704 }
2705
2706 c->op_bytes = def_op_bytes;
2707 c->ad_bytes = def_ad_bytes;
2708
2709 /* Legacy prefixes. */
2710 for (;;) {
2711 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2712 case 0x66: /* operand-size override */
2713 /* switch between 2/4 bytes */
2714 c->op_bytes = def_op_bytes ^ 6;
2715 break;
2716 case 0x67: /* address-size override */
2717 if (mode == X86EMUL_MODE_PROT64)
2718 /* switch between 4/8 bytes */
2719 c->ad_bytes = def_ad_bytes ^ 12;
2720 else
2721 /* switch between 2/4 bytes */
2722 c->ad_bytes = def_ad_bytes ^ 6;
2723 break;
2724 case 0x26: /* ES override */
2725 case 0x2e: /* CS override */
2726 case 0x36: /* SS override */
2727 case 0x3e: /* DS override */
2728 set_seg_override(c, (c->b >> 3) & 3);
2729 break;
2730 case 0x64: /* FS override */
2731 case 0x65: /* GS override */
2732 set_seg_override(c, c->b & 7);
2733 break;
2734 case 0x40 ... 0x4f: /* REX */
2735 if (mode != X86EMUL_MODE_PROT64)
2736 goto done_prefixes;
2737 c->rex_prefix = c->b;
2738 continue;
2739 case 0xf0: /* LOCK */
2740 c->lock_prefix = 1;
2741 break;
2742 case 0xf2: /* REPNE/REPNZ */
2743 c->rep_prefix = REPNE_PREFIX;
2744 break;
2745 case 0xf3: /* REP/REPE/REPZ */
2746 c->rep_prefix = REPE_PREFIX;
2747 break;
2748 default:
2749 goto done_prefixes;
2750 }
2751
2752 /* Any legacy prefix after a REX prefix nullifies its effect. */
2753
2754 c->rex_prefix = 0;
2755 }
2756
2757done_prefixes:
2758
2759 /* REX prefix. */
1e87e3ef
AK		 2760 if (c->rex_prefix & 8)
2761 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2762
2763 /* Opcode byte(s). */
2764 opcode = opcode_table[c->b];
d3ad6243
WY		 2765 /* Two-byte opcode? */
2766 if (c->b == 0x0f) {
2767 c->twobyte = 1;
2768 c->b = insn_fetch(u8, 1, c->eip);
2769 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2770 }
2771 c->d = opcode.flags;
2772
2773 if (c->d & Group) {
2774 dual = c->d & GroupDual;
2775 c->modrm = insn_fetch(u8, 1, c->eip);
2776 --c->eip;
2777
2778 if (c->d & GroupDual) {
2779 g_mod012 = opcode.u.gdual->mod012;
2780 g_mod3 = opcode.u.gdual->mod3;
2781 } else
2782 g_mod012 = g_mod3 = opcode.u.group;
2783
2784 c->d &= ~(Group | GroupDual);
2785
2786 goffset = (c->modrm >> 3) & 7;
2787
2788 if ((c->modrm >> 6) == 3)
2789 opcode = g_mod3[goffset];
2790 else
2791 opcode = g_mod012[goffset];
2792 c->d |= opcode.flags;
2793 }
2794
2795 c->execute = opcode.u.execute;
2796
2797 /* Unrecognised? */
d53db5ef 2798 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 2799 return -1;
dde7e6d1
AK		 2800
2801 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2802 c->op_bytes = 8;
2803
7f9b4b75
AK		 2804 if (c->d & Op3264) {
2805 if (mode == X86EMUL_MODE_PROT64)
2806 c->op_bytes = 8;
2807 else
2808 c->op_bytes = 4;
2809 }
2810
dde7e6d1 2811 /* ModRM and SIB bytes. */
09ee57cd 2812 if (c->d & ModRM) {
2dbd0dd7 2813 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2814 if (!c->has_seg_override)
2815 set_seg_override(c, c->modrm_seg);
2816 } else if (c->d & MemAbs)
2dbd0dd7 2817 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2818 if (rc != X86EMUL_CONTINUE)
2819 goto done;
2820
2821 if (!c->has_seg_override)
2822 set_seg_override(c, VCPU_SREG_DS);
2823
2dbd0dd7
AK		 2824 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2825 memop.addr.mem += seg_override_base(ctxt, ops, c);
dde7e6d1 2826
2dbd0dd7
AK		 2827 if (memop.type == OP_MEM && c->ad_bytes != 8)
2828 memop.addr.mem = (u32)memop.addr.mem;
dde7e6d1 2829
2dbd0dd7
AK		 2830 if (memop.type == OP_MEM && c->rip_relative)
2831 memop.addr.mem += c->eip;
dde7e6d1
AK		 2832
2833 /*
2834 * Decode and fetch the source operand: register, memory
2835 * or immediate.
2836 */
2837 switch (c->d & SrcMask) {
2838 case SrcNone:
2839 break;
2840 case SrcReg:
2841 decode_register_operand(&c->src, c, 0);
2842 break;
2843 case SrcMem16:
2dbd0dd7 2844 memop.bytes = 2;
dde7e6d1
AK		 2845 goto srcmem_common;
2846 case SrcMem32:
2dbd0dd7 2847 memop.bytes = 4;
dde7e6d1
AK		 2848 goto srcmem_common;
2849 case SrcMem:
2dbd0dd7 2850 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2851 c->op_bytes;
dde7e6d1 2852 srcmem_common:
2dbd0dd7 2853 c->src = memop;
dde7e6d1 2854 break;
b250e605 2855 case SrcImmU16:
39f21ee5
AK		 2856 rc = decode_imm(ctxt, &c->src, 2, false);
2857 break;
dde7e6d1 2858 case SrcImm:
39f21ee5
AK		 2859 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2860 break;
dde7e6d1 2861 case SrcImmU:
39f21ee5 2862 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2863 break;
2864 case SrcImmByte:
39f21ee5
AK		 2865 rc = decode_imm(ctxt, &c->src, 1, true);
2866 break;
dde7e6d1 2867 case SrcImmUByte:
39f21ee5 2868 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2869 break;
2870 case SrcAcc:
2871 c->src.type = OP_REG;
2872 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2873 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2874 fetch_register_operand(&c->src);
dde7e6d1
AK		 2875 break;
2876 case SrcOne:
2877 c->src.bytes = 1;
2878 c->src.val = 1;
2879 break;
2880 case SrcSI:
2881 c->src.type = OP_MEM;
2882 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2883 c->src.addr.mem =
dde7e6d1
AK		 2884 register_address(c, seg_override_base(ctxt, ops, c),
2885 c->regs[VCPU_REGS_RSI]);
2886 c->src.val = 0;
2887 break;
2888 case SrcImmFAddr:
2889 c->src.type = OP_IMM;
1a6440ae 2890 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2891 c->src.bytes = c->op_bytes + 2;
2892 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2893 break;
2894 case SrcMemFAddr:
2dbd0dd7
AK		 2895 memop.bytes = c->op_bytes + 2;
2896 goto srcmem_common;
dde7e6d1
AK		 2897 break;
2898 }
2899
39f21ee5
AK		 2900 if (rc != X86EMUL_CONTINUE)
2901 goto done;
2902
dde7e6d1
AK		 2903 /*
2904 * Decode and fetch the second source operand: register, memory
2905 * or immediate.
2906 */
2907 switch (c->d & Src2Mask) {
2908 case Src2None:
2909 break;
2910 case Src2CL:
2911 c->src2.bytes = 1;
2912 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2913 break;
2914 case Src2ImmByte:
39f21ee5 2915 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2916 break;
2917 case Src2One:
2918 c->src2.bytes = 1;
2919 c->src2.val = 1;
2920 break;
7db41eb7
AK		 2921 case Src2Imm:
2922 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2923 break;
dde7e6d1
AK		 2924 }
2925
39f21ee5
AK		 2926 if (rc != X86EMUL_CONTINUE)
2927 goto done;
2928
dde7e6d1
AK		 2929 /* Decode and fetch the destination operand: register or memory. */
2930 switch (c->d & DstMask) {
dde7e6d1
AK		 2931 case DstReg:
2932 decode_register_operand(&c->dst, c,
2933 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2934 break;
943858e2
WY		 2935 case DstImmUByte:
2936 c->dst.type = OP_IMM;
2937 c->dst.addr.mem = c->eip;
2938 c->dst.bytes = 1;
2939 c->dst.val = insn_fetch(u8, 1, c->eip);
2940 break;
dde7e6d1
AK		 2941 case DstMem:
2942 case DstMem64:
2dbd0dd7 2943 c->dst = memop;
dde7e6d1
AK		 2944 if ((c->d & DstMask) == DstMem64)
2945 c->dst.bytes = 8;
2946 else
2947 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2948 if (c->d & BitOp)
2949 fetch_bit_operand(c);
2dbd0dd7 2950 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2951 break;
2952 case DstAcc:
2953 c->dst.type = OP_REG;
2954 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2955 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2956 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2957 c->dst.orig_val = c->dst.val;
2958 break;
2959 case DstDI:
2960 c->dst.type = OP_MEM;
2961 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2962 c->dst.addr.mem =
dde7e6d1
AK		 2963 register_address(c, es_base(ctxt, ops),
2964 c->regs[VCPU_REGS_RDI]);
2965 c->dst.val = 0;
2966 break;
36089fed
WY		 2967 case ImplicitOps:
2968 /* Special instructions do their own operand decoding. */
2969 default:
2970 c->dst.type = OP_NONE; /* Disable writeback. */
2971 return 0;
dde7e6d1
AK		 2972 }
2973
2974done:
2975 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2976}
2977
3e2f65d5
GN		 2978static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2979{
2980 struct decode_cache *c = &ctxt->decode;
2981
2982 /* The second termination condition only applies for REPE
2983 * and REPNE. Test if the repeat string operation prefix is
2984 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2985 * corresponding termination condition according to:
2986 * - if REPE/REPZ and ZF = 0 then done
2987 * - if REPNE/REPNZ and ZF = 1 then done
2988 */
2989 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2990 (c->b == 0xae) || (c->b == 0xaf))
2991 && (((c->rep_prefix == REPE_PREFIX) &&
2992 ((ctxt->eflags & EFLG_ZF) == 0))
2993 || ((c->rep_prefix == REPNE_PREFIX) &&
2994 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2995 return true;
2996
2997 return false;
2998}
2999
8b4caf66 3000int
9aabc88f 3001x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3002{
9aabc88f 3003 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3004 u64 msr_data;
8b4caf66 3005 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3006 int rc = X86EMUL_CONTINUE;
5cd21917 3007 int saved_dst_type = c->dst.type;
6e154e56 3008 int irq; /* Used for int 3, int, and into */
8b4caf66 3009
9de41573 3010 ctxt->decode.mem_read.pos = 0;
310b5d30 3011
1161624f 3012 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 3013 emulate_ud(ctxt);
1161624f
GN		 3014 goto done;
3015 }
3016
d380a5e4 3017 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3018 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 3019 emulate_ud(ctxt);
d380a5e4
GN		 3020 goto done;
3021 }
3022
081bca0e
AK		 3023 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3024 emulate_ud(ctxt);
3025 goto done;
3026 }
3027
e92805ac 3028 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3029 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 3030 emulate_gp(ctxt, 0);
e92805ac
GN		 3031 goto done;
3032 }
3033
b9fa9d6b
AK		 3034 if (c->rep_prefix && (c->d & String)) {
3035 /* All REP prefixes have the same first termination condition */
c73e197b 3036 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3037 ctxt->eip = c->eip;
b9fa9d6b
AK		 3038 goto done;
3039 }
b9fa9d6b
AK		 3040 }
3041
c483c02a 3042 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
1a6440ae 3043 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 3044 c->src.valptr, c->src.bytes);
b60d513c 3045 if (rc != X86EMUL_CONTINUE)
8b4caf66 3046 goto done;
16518d5a 3047 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3048 }
3049
e35b7b9c 3050 if (c->src2.type == OP_MEM) {
1a6440ae 3051 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 3052 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3053 if (rc != X86EMUL_CONTINUE)
3054 goto done;
3055 }
3056
8b4caf66
LV		 3057 if ((c->d & DstMask) == ImplicitOps)
3058 goto special_insn;
3059
3060
69f55cb1
GN		 3061 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3062 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 3063 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 3064 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3065 if (rc != X86EMUL_CONTINUE)
3066 goto done;
038e51de 3067 }
e4e03ded 3068 c->dst.orig_val = c->dst.val;
038e51de 3069
018a98db
AK		 3070special_insn:
3071
ef65c889
AK		 3072 if (c->execute) {
3073 rc = c->execute(ctxt);
3074 if (rc != X86EMUL_CONTINUE)
3075 goto done;
3076 goto writeback;
3077 }
3078
e4e03ded 3079 if (c->twobyte)
6aa8b732
AK		 3080 goto twobyte_insn;
3081
e4e03ded 3082 switch (c->b) {
6aa8b732
AK		 3083 case 0x00 ... 0x05:
3084 add: /* add */
05f086f8 3085 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3086 break;
0934ac9d 3087 case 0x06: /* push es */
79168fd1 3088 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3089 break;
3090 case 0x07: /* pop es */
0934ac9d 3091 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3092 break;
6aa8b732
AK		 3093 case 0x08 ... 0x0d:
3094 or: /* or */
05f086f8 3095 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3096 break;
0934ac9d 3097 case 0x0e: /* push cs */
79168fd1 3098 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3099 break;
6aa8b732
AK		 3100 case 0x10 ... 0x15:
3101 adc: /* adc */
05f086f8 3102 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3103 break;
0934ac9d 3104 case 0x16: /* push ss */
79168fd1 3105 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3106 break;
3107 case 0x17: /* pop ss */
0934ac9d 3108 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3109 break;
6aa8b732
AK		 3110 case 0x18 ... 0x1d:
3111 sbb: /* sbb */
05f086f8 3112 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3113 break;
0934ac9d 3114 case 0x1e: /* push ds */
79168fd1 3115 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3116 break;
3117 case 0x1f: /* pop ds */
0934ac9d 3118 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3119 break;
aa3a816b 3120 case 0x20 ... 0x25:
6aa8b732 3121 and: /* and */
05f086f8 3122 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3123 break;
3124 case 0x28 ... 0x2d:
3125 sub: /* sub */
05f086f8 3126 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3127 break;
3128 case 0x30 ... 0x35:
3129 xor: /* xor */
05f086f8 3130 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3131 break;
3132 case 0x38 ... 0x3d:
3133 cmp: /* cmp */
05f086f8 3134 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3135 break;
33615aa9
AK		 3136 case 0x40 ... 0x47: /* inc r16/r32 */
3137 emulate_1op("inc", c->dst, ctxt->eflags);
3138 break;
3139 case 0x48 ... 0x4f: /* dec r16/r32 */
3140 emulate_1op("dec", c->dst, ctxt->eflags);
3141 break;
33615aa9
AK		 3142 case 0x58 ... 0x5f: /* pop reg */
3143 pop_instruction:
350f69dc 3144 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3145 break;
abcf14b5 3146 case 0x60: /* pusha */
c37eda13 3147 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3148 break;
3149 case 0x61: /* popa */
3150 rc = emulate_popa(ctxt, ops);
abcf14b5 3151 break;
6aa8b732 3152 case 0x63: /* movsxd */
8b4caf66 3153 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3154 goto cannot_emulate;
e4e03ded 3155 c->dst.val = (s32) c->src.val;
6aa8b732 3156 break;
018a98db
AK		 3157 case 0x6c: /* insb */
3158 case 0x6d: /* insw/insd */
a13a63fa
WY		 3159 c->src.val = c->regs[VCPU_REGS_RDX];
3160 goto do_io_in;
018a98db
AK		 3161 case 0x6e: /* outsb */
3162 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3163 c->dst.val = c->regs[VCPU_REGS_RDX];
3164 goto do_io_out;
7972995b 3165 break;
b2833e3c 3166 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3167 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3168 jmp_rel(c, c->src.val);
018a98db 3169 break;
6aa8b732 3170 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3171 switch (c->modrm_reg) {
6aa8b732
AK		 3172 case 0:
3173 goto add;
3174 case 1:
3175 goto or;
3176 case 2:
3177 goto adc;
3178 case 3:
3179 goto sbb;
3180 case 4:
3181 goto and;
3182 case 5:
3183 goto sub;
3184 case 6:
3185 goto xor;
3186 case 7:
3187 goto cmp;
3188 }
3189 break;
3190 case 0x84 ... 0x85:
dfb507c4 3191 test:
05f086f8 3192 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3193 break;
3194 case 0x86 ... 0x87: /* xchg */
b13354f8 3195 xchg:
6aa8b732 3196 /* Write back the register source. */
31be40b3
WY		 3197 c->src.val = c->dst.val;
3198 write_register_operand(&c->src);
6aa8b732
AK		 3199 /*
3200 * Write back the memory destination with implicit LOCK
3201 * prefix.
3202 */
31be40b3 3203 c->dst.val = c->src.orig_val;
e4e03ded 3204 c->lock_prefix = 1;
6aa8b732 3205 break;
79168fd1
GN		 3206 case 0x8c: /* mov r/m, sreg */
3207 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3208 emulate_ud(ctxt);
5e3ae6c5 3209 goto done;
38d5bc6d 3210 }
79168fd1 3211 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3212 break;
7e0b54b1 3213 case 0x8d: /* lea r16/r32, m */
342fc630 3214 c->dst.val = c->src.addr.mem;
7e0b54b1 3215 break;
4257198a
GT		 3216 case 0x8e: { /* mov seg, r/m16 */
3217 uint16_t sel;
4257198a
GT		 3218
3219 sel = c->src.val;
8b9f4414 3220
c697518a
GN		 3221 if (c->modrm_reg == VCPU_SREG_CS ||
3222 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3223 emulate_ud(ctxt);
8b9f4414
GN		 3224 goto done;
3225 }
3226
310b5d30 3227 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3228 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3229
2e873022 3230 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3231
3232 c->dst.type = OP_NONE; /* Disable writeback. */
3233 break;
3234 }
6aa8b732 3235 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3236 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3237 break;
3d9e77df
AK		 3238 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3239 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3240 break;
b13354f8 3241 goto xchg;
e8b6fa70
WY		 3242 case 0x98: /* cbw/cwde/cdqe */
3243 switch (c->op_bytes) {
3244 case 2: c->dst.val = (s8)c->dst.val; break;
3245 case 4: c->dst.val = (s16)c->dst.val; break;
3246 case 8: c->dst.val = (s32)c->dst.val; break;
3247 }
3248 break;
fd2a7608 3249 case 0x9c: /* pushf */
05f086f8 3250 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3251 emulate_push(ctxt, ops);
8cdbd2c9 3252 break;
535eabcf 3253 case 0x9d: /* popf */
2b48cc75 3254 c->dst.type = OP_REG;
1a6440ae 3255 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3256 c->dst.bytes = c->op_bytes;
d4c6a154 3257 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3258 break;
6aa8b732 3259 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3260 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3261 goto cmp;
dfb507c4
MG		 3262 case 0xa8 ... 0xa9: /* test ax, imm */
3263 goto test;
6aa8b732 3264 case 0xae ... 0xaf: /* scas */
f6b33fc5 3265 goto cmp;
018a98db
AK		 3266 case 0xc0 ... 0xc1:
3267 emulate_grp2(ctxt);
3268 break;
111de5d6 3269 case 0xc3: /* ret */
cf5de4f8 3270 c->dst.type = OP_REG;
1a6440ae 3271 c->dst.addr.reg = &c->eip;
cf5de4f8 3272 c->dst.bytes = c->op_bytes;
111de5d6 3273 goto pop_instruction;
09b5f4d3
WY		 3274 case 0xc4: /* les */
3275 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3276 break;
3277 case 0xc5: /* lds */
3278 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3279 break;
a77ab5ea
AK		 3280 case 0xcb: /* ret far */
3281 rc = emulate_ret_far(ctxt, ops);
62bd430e 3282 break;
6e154e56
MG		 3283 case 0xcc: /* int3 */
3284 irq = 3;
3285 goto do_interrupt;
3286 case 0xcd: /* int n */
3287 irq = c->src.val;
3288 do_interrupt:
3289 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3290 break;
3291 case 0xce: /* into */
3292 if (ctxt->eflags & EFLG_OF) {
3293 irq = 4;
3294 goto do_interrupt;
3295 }
3296 break;
62bd430e
MG		 3297 case 0xcf: /* iret */
3298 rc = emulate_iret(ctxt, ops);
a77ab5ea 3299 break;
018a98db 3300 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3301 emulate_grp2(ctxt);
3302 break;
3303 case 0xd2 ... 0xd3: /* Grp2 */
3304 c->src.val = c->regs[VCPU_REGS_RCX];
3305 emulate_grp2(ctxt);
3306 break;
f2f31845
WY		 3307 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3308 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3309 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3310 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3311 jmp_rel(c, c->src.val);
3312 break;
e4abac67
WY		 3313 case 0xe3: /* jcxz/jecxz/jrcxz */
3314 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3315 jmp_rel(c, c->src.val);
3316 break;
a6a3034c
MG		 3317 case 0xe4: /* inb */
3318 case 0xe5: /* in */
cf8f70bf 3319 goto do_io_in;
a6a3034c
MG		 3320 case 0xe6: /* outb */
3321 case 0xe7: /* out */
cf8f70bf 3322 goto do_io_out;
1a52e051 3323 case 0xe8: /* call (near) */ {
d53c4777 3324 long int rel = c->src.val;
e4e03ded 3325 c->src.val = (unsigned long) c->eip;
7a957275 3326 jmp_rel(c, rel);
79168fd1 3327 emulate_push(ctxt, ops);
8cdbd2c9 3328 break;
1a52e051
NK		 3329 }
3330 case 0xe9: /* jmp rel */
954cd36f 3331 goto jmp;
414e6277
GN		 3332 case 0xea: { /* jmp far */
3333 unsigned short sel;
ea79849d 3334 jump_far:
414e6277
GN		 3335 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3336
3337 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3338 goto done;
954cd36f 3339
414e6277
GN		 3340 c->eip = 0;
3341 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3342 break;
414e6277 3343 }
954cd36f
GT		 3344 case 0xeb:
3345 jmp: /* jmp rel short */
7a957275 3346 jmp_rel(c, c->src.val);
a01af5ec 3347 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3348 break;
a6a3034c
MG		 3349 case 0xec: /* in al,dx */
3350 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3351 c->src.val = c->regs[VCPU_REGS_RDX];
3352 do_io_in:
3353 c->dst.bytes = min(c->dst.bytes, 4u);
3354 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3355 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3356 goto done;
3357 }
7b262e90
GN		 3358 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3359 &c->dst.val))
cf8f70bf
GN		 3360 goto done; /* IO is needed */
3361 break;
ce7a0ad3
WY		 3362 case 0xee: /* out dx,al */
3363 case 0xef: /* out dx,(e/r)ax */
41167be5 3364 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3365 do_io_out:
41167be5
WY		 3366 c->src.bytes = min(c->src.bytes, 4u);
3367 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3368 c->src.bytes)) {
54b8486f 3369 emulate_gp(ctxt, 0);
f850e2e6
GN		 3370 goto done;
3371 }
41167be5
WY		 3372 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3373 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3374 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3375 break;
111de5d6 3376 case 0xf4: /* hlt */
ad312c7c 3377 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3378 break;
111de5d6
AK		 3379 case 0xf5: /* cmc */
3380 /* complement carry flag from eflags reg */
3381 ctxt->eflags ^= EFLG_CF;
111de5d6 3382 break;
018a98db 3383 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3384 rc = emulate_grp3(ctxt, ops);
018a98db 3385 break;
111de5d6
AK		 3386 case 0xf8: /* clc */
3387 ctxt->eflags &= ~EFLG_CF;
111de5d6 3388 break;
8744aa9a
MG		 3389 case 0xf9: /* stc */
3390 ctxt->eflags |= EFLG_CF;
3391 break;
111de5d6 3392 case 0xfa: /* cli */
07cbc6c1 3393 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3394 emulate_gp(ctxt, 0);
07cbc6c1 3395 goto done;
36089fed 3396 } else
f850e2e6 3397 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3398 break;
3399 case 0xfb: /* sti */
07cbc6c1 3400 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3401 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3402 goto done;
3403 } else {
95cb2295 3404 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3405 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3406 }
111de5d6 3407 break;
fb4616f4
MG		 3408 case 0xfc: /* cld */
3409 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3410 break;
3411 case 0xfd: /* std */
3412 ctxt->eflags |= EFLG_DF;
fb4616f4 3413 break;
ea79849d
GN		 3414 case 0xfe: /* Grp4 */
3415 grp45:
018a98db 3416 rc = emulate_grp45(ctxt, ops);
018a98db 3417 break;
ea79849d
GN		 3418 case 0xff: /* Grp5 */
3419 if (c->modrm_reg == 5)
3420 goto jump_far;
3421 goto grp45;
91269b8f
AK		 3422 default:
3423 goto cannot_emulate;
6aa8b732 3424 }
018a98db 3425
7d9ddaed
AK		 3426 if (rc != X86EMUL_CONTINUE)
3427 goto done;
3428
018a98db
AK		 3429writeback:
3430 rc = writeback(ctxt, ops);
1b30eaa8 3431 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3432 goto done;
3433
5cd21917
GN		 3434 /*
3435 * restore dst type in case the decoding will be reused
3436 * (happens for string instruction )
3437 */
3438 c->dst.type = saved_dst_type;
3439
a682e354 3440 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3441 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3442 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3443
3444 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3445 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3446 &c->dst);
d9271123 3447
5cd21917 3448 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3449 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3450 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3451
d2ddd1c4
GN		 3452 if (!string_insn_completed(ctxt)) {
3453 /*
3454 * Re-enter guest when pio read ahead buffer is empty
3455 * or, if it is not used, after each 1024 iteration.
3456 */
3457 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3458 (r->end == 0 || r->end != r->pos)) {
3459 /*
3460 * Reset read cache. Usually happens before
3461 * decode, but since instruction is restarted
3462 * we have to do it here.
3463 */
3464 ctxt->decode.mem_read.end = 0;
3465 return EMULATION_RESTART;
3466 }
3467 goto done; /* skip rip writeback */
0fa6ccbd 3468 }
5cd21917 3469 }
d2ddd1c4
GN		 3470
3471 ctxt->eip = c->eip;
018a98db
AK		 3472
3473done:
d2ddd1c4 3474 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3475
3476twobyte_insn:
e4e03ded 3477 switch (c->b) {
6aa8b732 3478 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3479 switch (c->modrm_reg) {
6aa8b732
AK		 3480 u16 size;
3481 unsigned long address;
3482
aca7f966 3483 case 0: /* vmcall */
e4e03ded 3484 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3485 goto cannot_emulate;
3486
7aa81cc0 3487 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3488 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3489 goto done;
3490
33e3885d 3491 /* Let the processor re-execute the fixed hypercall */
063db061 3492 c->eip = ctxt->eip;
16286d08
AK		 3493 /* Disable writeback. */
3494 c->dst.type = OP_NONE;
aca7f966 3495 break;
6aa8b732 3496 case 2: /* lgdt */
1a6440ae 3497 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3498 &size, &address, c->op_bytes);
1b30eaa8 3499 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3500 goto done;
3501 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3502 /* Disable writeback. */
3503 c->dst.type = OP_NONE;
6aa8b732 3504 break;
aca7f966 3505 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3506 if (c->modrm_mod == 3) {
3507 switch (c->modrm_rm) {
3508 case 1:
3509 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3510 break;
3511 default:
3512 goto cannot_emulate;
3513 }
aca7f966 3514 } else {
1a6440ae 3515 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3516 &size, &address,
e4e03ded 3517 c->op_bytes);
1b30eaa8 3518 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3519 goto done;
3520 realmode_lidt(ctxt->vcpu, size, address);
3521 }
16286d08
AK		 3522 /* Disable writeback. */
3523 c->dst.type = OP_NONE;
6aa8b732
AK		 3524 break;
3525 case 4: /* smsw */
16286d08 3526 c->dst.bytes = 2;
52a46617 3527 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3528 break;
3529 case 6: /* lmsw */
9928ff60 3530 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3531 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3532 c->dst.type = OP_NONE;
6aa8b732 3533 break;
6e1e5ffe 3534 case 5: /* not defined */
54b8486f 3535 emulate_ud(ctxt);
6e1e5ffe 3536 goto done;
6aa8b732 3537 case 7: /* invlpg*/
1f6f0580 3538 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
16286d08
AK		 3539 /* Disable writeback. */
3540 c->dst.type = OP_NONE;
6aa8b732
AK		 3541 break;
3542 default:
3543 goto cannot_emulate;
3544 }
3545 break;
e99f0507 3546 case 0x05: /* syscall */
3fb1b5db 3547 rc = emulate_syscall(ctxt, ops);
e99f0507 3548 break;
018a98db
AK		 3549 case 0x06:
3550 emulate_clts(ctxt->vcpu);
018a98db 3551 break;
018a98db 3552 case 0x09: /* wbinvd */
f5f48ee1 3553 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3554 break;
3555 case 0x08: /* invd */
018a98db
AK		 3556 case 0x0d: /* GrpP (prefetch) */
3557 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3558 break;
3559 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3560 switch (c->modrm_reg) {
3561 case 1:
3562 case 5 ... 7:
3563 case 9 ... 15:
54b8486f 3564 emulate_ud(ctxt);
6aebfa6e
GN		 3565 goto done;
3566 }
1a0c7d44 3567 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3568 break;
6aa8b732 3569 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3570 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3571 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3572 emulate_ud(ctxt);
1e470be5
GN		 3573 goto done;
3574 }
b27f3856 3575 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3576 break;
018a98db 3577 case 0x22: /* mov reg, cr */
1a0c7d44 3578 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3579 emulate_gp(ctxt, 0);
0f12244f
GN		 3580 goto done;
3581 }
018a98db
AK		 3582 c->dst.type = OP_NONE;
3583 break;
6aa8b732 3584 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3585 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3586 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3587 emulate_ud(ctxt);
1e470be5
GN		 3588 goto done;
3589 }
35aa5375 3590
b27f3856 3591 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3592 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3593 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3594 /* #UD condition is already handled by the code above */
54b8486f 3595 emulate_gp(ctxt, 0);
338dbc97
GN		 3596 goto done;
3597 }
3598
a01af5ec 3599 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3600 break;
018a98db
AK		 3601 case 0x30:
3602 /* wrmsr */
3603 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3604 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3605 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3606 emulate_gp(ctxt, 0);
fd525365 3607 goto done;
018a98db
AK		 3608 }
3609 rc = X86EMUL_CONTINUE;
018a98db
AK		 3610 break;
3611 case 0x32:
3612 /* rdmsr */
3fb1b5db 3613 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3614 emulate_gp(ctxt, 0);
fd525365 3615 goto done;
018a98db
AK		 3616 } else {
3617 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3618 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3619 }
3620 rc = X86EMUL_CONTINUE;
018a98db 3621 break;
e99f0507 3622 case 0x34: /* sysenter */
3fb1b5db 3623 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3624 break;
3625 case 0x35: /* sysexit */
3fb1b5db 3626 rc = emulate_sysexit(ctxt, ops);
e99f0507 3627 break;
6aa8b732 3628 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3629 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3630 if (!test_cc(c->b, ctxt->eflags))
3631 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3632 break;
b2833e3c 3633 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3634 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3635 jmp_rel(c, c->src.val);
018a98db 3636 break;
ee45b58e
WY		 3637 case 0x90 ... 0x9f: /* setcc r/m8 */
3638 c->dst.val = test_cc(c->b, ctxt->eflags);
3639 break;
0934ac9d 3640 case 0xa0: /* push fs */
79168fd1 3641 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3642 break;
3643 case 0xa1: /* pop fs */
3644 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3645 break;
7de75248
NK		 3646 case 0xa3:
3647 bt: /* bt */
e4f8e039 3648 c->dst.type = OP_NONE;
e4e03ded
LV		 3649 /* only subword offset */
3650 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3651 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3652 break;
9bf8ea42
GT		 3653 case 0xa4: /* shld imm8, r, r/m */
3654 case 0xa5: /* shld cl, r, r/m */
3655 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3656 break;
0934ac9d 3657 case 0xa8: /* push gs */
79168fd1 3658 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3659 break;
3660 case 0xa9: /* pop gs */
3661 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3662 break;
7de75248
NK		 3663 case 0xab:
3664 bts: /* bts */
05f086f8 3665 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3666 break;
9bf8ea42
GT		 3667 case 0xac: /* shrd imm8, r, r/m */
3668 case 0xad: /* shrd cl, r, r/m */
3669 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3670 break;
2a7c5b8b
GC		 3671 case 0xae: /* clflush */
3672 break;
6aa8b732
AK		 3673 case 0xb0 ... 0xb1: /* cmpxchg */
3674 /*
3675 * Save real source value, then compare EAX against
3676 * destination.
3677 */
e4e03ded
LV		 3678 c->src.orig_val = c->src.val;
3679 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3680 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3681 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3682 /* Success: write back to memory. */
e4e03ded 3683 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3684 } else {
3685 /* Failure: write the value we saw to EAX. */
e4e03ded 3686 c->dst.type = OP_REG;
1a6440ae 3687 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3688 }
3689 break;
09b5f4d3
WY		 3690 case 0xb2: /* lss */
3691 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3692 break;
6aa8b732
AK		 3693 case 0xb3:
3694 btr: /* btr */
05f086f8 3695 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3696 break;
09b5f4d3
WY		 3697 case 0xb4: /* lfs */
3698 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3699 break;
3700 case 0xb5: /* lgs */
3701 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3702 break;
6aa8b732 3703 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3704 c->dst.bytes = c->op_bytes;
3705 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3706 : (u16) c->src.val;
6aa8b732 3707 break;
6aa8b732 3708 case 0xba: /* Grp8 */
e4e03ded 3709 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3710 case 0:
3711 goto bt;
3712 case 1:
3713 goto bts;
3714 case 2:
3715 goto btr;
3716 case 3:
3717 goto btc;
3718 }
3719 break;
7de75248
NK		 3720 case 0xbb:
3721 btc: /* btc */
05f086f8 3722 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3723 break;
d9574a25
WY		 3724 case 0xbc: { /* bsf */
3725 u8 zf;
3726 __asm__ ("bsf %2, %0; setz %1"
3727 : "=r"(c->dst.val), "=q"(zf)
3728 : "r"(c->src.val));
3729 ctxt->eflags &= ~X86_EFLAGS_ZF;
3730 if (zf) {
3731 ctxt->eflags |= X86_EFLAGS_ZF;
3732 c->dst.type = OP_NONE; /* Disable writeback. */
3733 }
3734 break;
3735 }
3736 case 0xbd: { /* bsr */
3737 u8 zf;
3738 __asm__ ("bsr %2, %0; setz %1"
3739 : "=r"(c->dst.val), "=q"(zf)
3740 : "r"(c->src.val));
3741 ctxt->eflags &= ~X86_EFLAGS_ZF;
3742 if (zf) {
3743 ctxt->eflags |= X86_EFLAGS_ZF;
3744 c->dst.type = OP_NONE; /* Disable writeback. */
3745 }
3746 break;
3747 }
6aa8b732 3748 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3749 c->dst.bytes = c->op_bytes;
3750 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3751 (s16) c->src.val;
6aa8b732 3752 break;
92f738a5
WY		 3753 case 0xc0 ... 0xc1: /* xadd */
3754 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3755 /* Write back the register source. */
3756 c->src.val = c->dst.orig_val;
3757 write_register_operand(&c->src);
3758 break;
a012e65a 3759 case 0xc3: /* movnti */
e4e03ded
LV		 3760 c->dst.bytes = c->op_bytes;
3761 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3762 (u64) c->src.val;
a012e65a 3763 break;
6aa8b732 3764 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3765 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3766 break;
91269b8f
AK		 3767 default:
3768 goto cannot_emulate;
6aa8b732 3769 }
7d9ddaed
AK		 3770
3771 if (rc != X86EMUL_CONTINUE)
3772 goto done;
3773
6aa8b732
AK		 3774 goto writeback;
3775
3776cannot_emulate:
6aa8b732
AK		 3777 return -1;
3778}
Linux kernel - Deliverables
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