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KVM: x86 emulator: vendor specific instructions
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 78/* Misc flags */
d867162c 79#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 80#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 81#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 82#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 83#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 84#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 85#define No64 (1<<28)
0dc8d10f
GT		 86/* Source 2 operand type */
87#define Src2None (0<<29)
88#define Src2CL (1<<29)
89#define Src2ImmByte (2<<29)
90#define Src2One (3<<29)
7db41eb7 91#define Src2Imm (4<<29)
0dc8d10f 92#define Src2Mask (7<<29)
6aa8b732 93
d0e53325
AK		 94#define X2(x...) x, x
95#define X3(x...) X2(x), x
96#define X4(x...) X2(x), X2(x)
97#define X5(x...) X4(x), x
98#define X6(x...) X4(x), X2(x)
99#define X7(x...) X4(x), X3(x)
100#define X8(x...) X4(x), X4(x)
101#define X16(x...) X8(x), X8(x)
83babbca 102
d65b1dee
AK		 103struct opcode {
104 u32 flags;
120df890 105 union {
ef65c889 106 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 107 struct opcode *group;
108 struct group_dual *gdual;
109 } u;
110};
111
112struct group_dual {
113 struct opcode mod012[8];
114 struct opcode mod3[8];
d65b1dee
AK		 115};
116
6aa8b732 117/* EFLAGS bit definitions. */
d4c6a154
GN		 118#define EFLG_ID (1<<21)
119#define EFLG_VIP (1<<20)
120#define EFLG_VIF (1<<19)
121#define EFLG_AC (1<<18)
b1d86143
AP		 122#define EFLG_VM (1<<17)
123#define EFLG_RF (1<<16)
d4c6a154
GN		 124#define EFLG_IOPL (3<<12)
125#define EFLG_NT (1<<14)
6aa8b732
AK		 126#define EFLG_OF (1<<11)
127#define EFLG_DF (1<<10)
b1d86143 128#define EFLG_IF (1<<9)
d4c6a154 129#define EFLG_TF (1<<8)
6aa8b732
AK		 130#define EFLG_SF (1<<7)
131#define EFLG_ZF (1<<6)
132#define EFLG_AF (1<<4)
133#define EFLG_PF (1<<2)
134#define EFLG_CF (1<<0)
135
62bd430e
MG		 136#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
137#define EFLG_RESERVED_ONE_MASK 2
138
6aa8b732
AK		 139/*
140 * Instruction emulation:
141 * Most instructions are emulated directly via a fragment of inline assembly
142 * code. This allows us to save/restore EFLAGS and thus very easily pick up
143 * any modified flags.
144 */
145
05b3e0c2 146#if defined(CONFIG_X86_64)
6aa8b732
AK		 147#define _LO32 "k" /* force 32-bit operand */
148#define _STK "%%rsp" /* stack pointer */
149#elif defined(__i386__)
150#define _LO32 "" /* force 32-bit operand */
151#define _STK "%%esp" /* stack pointer */
152#endif
153
154/*
155 * These EFLAGS bits are restored from saved value during emulation, and
156 * any changes are written back to the saved value after emulation.
157 */
158#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
159
160/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 161#define _PRE_EFLAGS(_sav, _msk, _tmp) \
162 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
163 "movl %"_sav",%"_LO32 _tmp"; " \
164 "push %"_tmp"; " \
165 "push %"_tmp"; " \
166 "movl %"_msk",%"_LO32 _tmp"; " \
167 "andl %"_LO32 _tmp",("_STK"); " \
168 "pushf; " \
169 "notl %"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
172 "pop %"_tmp"; " \
173 "orl %"_LO32 _tmp",("_STK"); " \
174 "popf; " \
175 "pop %"_sav"; "
6aa8b732
AK		 176
177/* After executing instruction: write-back necessary bits in EFLAGS. */
178#define _POST_EFLAGS(_sav, _msk, _tmp) \
179 /* _sav |= EFLAGS & _msk; */ \
180 "pushf; " \
181 "pop %"_tmp"; " \
182 "andl %"_msk",%"_LO32 _tmp"; " \
183 "orl %"_LO32 _tmp",%"_sav"; "
184
dda96d8f
AK		 185#ifdef CONFIG_X86_64
186#define ON64(x) x
187#else
188#define ON64(x)
189#endif
190
b3b3d25a 191#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 192 do { \
193 __asm__ __volatile__ ( \
194 _PRE_EFLAGS("0", "4", "2") \
195 _op _suffix " %"_x"3,%1; " \
196 _POST_EFLAGS("0", "4", "2") \
fb2c2641 197 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 198 "=&r" (_tmp) \
199 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 200 } while (0)
6b7ad61f
AK		 201
202
6aa8b732
AK		 203/* Raw emulation: instruction has two explicit operands. */
204#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 205 do { \
206 unsigned long _tmp; \
207 \
208 switch ((_dst).bytes) { \
209 case 2: \
b3b3d25a 210 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 211 break; \
212 case 4: \
b3b3d25a 213 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 214 break; \
215 case 8: \
b3b3d25a 216 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 217 break; \
218 } \
6aa8b732
AK		 219 } while (0)
220
221#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
222 do { \
6b7ad61f 223 unsigned long _tmp; \
d77c26fc 224 switch ((_dst).bytes) { \
6aa8b732 225 case 1: \
b3b3d25a 226 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 227 break; \
228 default: \
229 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
230 _wx, _wy, _lx, _ly, _qx, _qy); \
231 break; \
232 } \
233 } while (0)
234
235/* Source operand is byte-sized and may be restricted to just %cl. */
236#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
237 __emulate_2op(_op, _src, _dst, _eflags, \
238 "b", "c", "b", "c", "b", "c", "b", "c")
239
240/* Source operand is byte, word, long or quad sized. */
241#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
242 __emulate_2op(_op, _src, _dst, _eflags, \
243 "b", "q", "w", "r", _LO32, "r", "", "r")
244
245/* Source operand is word, long or quad sized. */
246#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
247 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
248 "w", "r", _LO32, "r", "", "r")
249
d175226a
GT		 250/* Instruction has three operands and one operand is stored in ECX register */
251#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
252 do { \
253 unsigned long _tmp; \
254 _type _clv = (_cl).val; \
255 _type _srcv = (_src).val; \
256 _type _dstv = (_dst).val; \
257 \
258 __asm__ __volatile__ ( \
259 _PRE_EFLAGS("0", "5", "2") \
260 _op _suffix " %4,%1 \n" \
261 _POST_EFLAGS("0", "5", "2") \
262 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
263 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
264 ); \
265 \
266 (_cl).val = (unsigned long) _clv; \
267 (_src).val = (unsigned long) _srcv; \
268 (_dst).val = (unsigned long) _dstv; \
269 } while (0)
270
271#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
272 do { \
273 switch ((_dst).bytes) { \
274 case 2: \
275 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
276 "w", unsigned short); \
277 break; \
278 case 4: \
279 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
280 "l", unsigned int); \
281 break; \
282 case 8: \
283 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
284 "q", unsigned long)); \
285 break; \
286 } \
287 } while (0)
288
dda96d8f 289#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 290 do { \
291 unsigned long _tmp; \
292 \
dda96d8f
AK		 293 __asm__ __volatile__ ( \
294 _PRE_EFLAGS("0", "3", "2") \
295 _op _suffix " %1; " \
296 _POST_EFLAGS("0", "3", "2") \
297 : "=m" (_eflags), "+m" ((_dst).val), \
298 "=&r" (_tmp) \
299 : "i" (EFLAGS_MASK)); \
300 } while (0)
301
302/* Instruction has only one explicit operand (no source operand). */
303#define emulate_1op(_op, _dst, _eflags) \
304 do { \
d77c26fc 305 switch ((_dst).bytes) { \
dda96d8f
AK		 306 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
307 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
308 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
309 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 310 } \
311 } while (0)
312
3f9f53b0
MG		 313#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
314 do { \
315 unsigned long _tmp; \
316 \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0", "4", "1") \
319 _op _suffix " %5; " \
320 _POST_EFLAGS("0", "4", "1") \
321 : "=m" (_eflags), "=&r" (_tmp), \
322 "+a" (_rax), "+d" (_rdx) \
323 : "i" (EFLAGS_MASK), "m" ((_src).val), \
324 "a" (_rax), "d" (_rdx)); \
325 } while (0)
326
f6b3597b
AK		 327#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "5", "1") \
333 "1: \n\t" \
334 _op _suffix " %6; " \
335 "2: \n\t" \
336 _POST_EFLAGS("0", "5", "1") \
337 ".pushsection .fixup,\"ax\" \n\t" \
338 "3: movb $1, %4 \n\t" \
339 "jmp 2b \n\t" \
340 ".popsection \n\t" \
341 _ASM_EXTABLE(1b, 3b) \
342 : "=m" (_eflags), "=&r" (_tmp), \
343 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
344 : "i" (EFLAGS_MASK), "m" ((_src).val), \
345 "a" (_rax), "d" (_rdx)); \
346 } while (0)
347
3f9f53b0
MG		 348/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
349#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
350 do { \
351 switch((_src).bytes) { \
352 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
353 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
354 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
355 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
356 } \
357 } while (0)
358
f6b3597b
AK		 359#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
360 do { \
361 switch((_src).bytes) { \
362 case 1: \
363 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
364 _eflags, "b", _ex); \
365 break; \
366 case 2: \
367 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
368 _eflags, "w", _ex); \
369 break; \
370 case 4: \
371 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
372 _eflags, "l", _ex); \
373 break; \
374 case 8: ON64( \
375 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
376 _eflags, "q", _ex)); \
377 break; \
378 } \
379 } while (0)
380
6aa8b732
AK		 381/* Fetch next part of the instruction being emulated. */
382#define insn_fetch(_type, _size, _eip) \
383({ unsigned long _x; \
62266869 384 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 385 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 386 goto done; \
387 (_eip) += (_size); \
388 (_type)_x; \
389})
390
414e6277
GN		 391#define insn_fetch_arr(_arr, _size, _eip) \
392({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
393 if (rc != X86EMUL_CONTINUE) \
394 goto done; \
395 (_eip) += (_size); \
396})
397
ddcb2885
HH		 398static inline unsigned long ad_mask(struct decode_cache *c)
399{
400 return (1UL << (c->ad_bytes << 3)) - 1;
401}
402
6aa8b732 403/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 404static inline unsigned long
405address_mask(struct decode_cache *c, unsigned long reg)
406{
407 if (c->ad_bytes == sizeof(unsigned long))
408 return reg;
409 else
410 return reg & ad_mask(c);
411}
412
413static inline unsigned long
90de84f5 414register_address(struct decode_cache *c, unsigned long reg)
e4706772 415{
90de84f5 416 return address_mask(c, reg);
e4706772
HH		 417}
418
7a957275
HH		 419static inline void
420register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
421{
422 if (c->ad_bytes == sizeof(unsigned long))
423 *reg += inc;
424 else
425 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
426}
6aa8b732 427
7a957275
HH		 428static inline void jmp_rel(struct decode_cache *c, int rel)
429{
430 register_address_increment(c, &c->eip, rel);
431}
098c937b 432
7a5b56df
AK		 433static void set_seg_override(struct decode_cache *c, int seg)
434{
435 c->has_seg_override = true;
436 c->seg_override = seg;
437}
438
79168fd1
GN		 439static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
440 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 441{
442 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
443 return 0;
444
79168fd1 445 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 446}
447
90de84f5
AK		 448static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
449 struct x86_emulate_ops *ops,
450 struct decode_cache *c)
7a5b56df
AK		 451{
452 if (!c->has_seg_override)
453 return 0;
454
90de84f5 455 return c->seg_override;
7a5b56df
AK		 456}
457
90de84f5
AK		 458static ulong linear(struct x86_emulate_ctxt *ctxt,
459 struct segmented_address addr)
7a5b56df 460{
90de84f5
AK		 461 struct decode_cache *c = &ctxt->decode;
462 ulong la;
7a5b56df 463
90de84f5
AK		 464 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
465 if (c->ad_bytes != 8)
466 la &= (u32)-1;
467 return la;
7a5b56df
AK		 468}
469
35d3d4a1
AK		 470static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
471 u32 error, bool valid)
54b8486f 472{
da9cb575
AK		 473 ctxt->exception.vector = vec;
474 ctxt->exception.error_code = error;
475 ctxt->exception.error_code_valid = valid;
35d3d4a1 476 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 477}
478
35d3d4a1 479static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 480{
35d3d4a1 481 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 482}
483
35d3d4a1 484static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 485{
35d3d4a1 486 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 487}
488
35d3d4a1 489static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 490{
35d3d4a1 491 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 492}
493
34d1f490
AK		 494static int emulate_de(struct x86_emulate_ctxt *ctxt)
495{
35d3d4a1 496 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 497}
498
62266869
AK		 499static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
500 struct x86_emulate_ops *ops,
2fb53ad8 501 unsigned long eip, u8 *dest)
62266869
AK		 502{
503 struct fetch_cache *fc = &ctxt->decode.fetch;
504 int rc;
2fb53ad8 505 int size, cur_size;
62266869 506
2fb53ad8
AK		 507 if (eip == fc->end) {
508 cur_size = fc->end - fc->start;
509 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
510 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 511 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 512 if (rc != X86EMUL_CONTINUE)
62266869 513 return rc;
2fb53ad8 514 fc->end += size;
62266869 515 }
2fb53ad8 516 *dest = fc->data[eip - fc->start];
3e2815e9 517 return X86EMUL_CONTINUE;
62266869
AK		 518}
519
520static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
521 struct x86_emulate_ops *ops,
522 unsigned long eip, void *dest, unsigned size)
523{
3e2815e9 524 int rc;
62266869 525
eb3c79e6 526 /* x86 instructions are limited to 15 bytes. */
063db061 527 if (eip + size - ctxt->eip > 15)
eb3c79e6 528 return X86EMUL_UNHANDLEABLE;
62266869
AK		 529 while (size--) {
530 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 531 if (rc != X86EMUL_CONTINUE)
62266869
AK		 532 return rc;
533 }
3e2815e9 534 return X86EMUL_CONTINUE;
62266869
AK		 535}
536
1e3c5cb0
RR		 537/*
538 * Given the 'reg' portion of a ModRM byte, and a register block, return a
539 * pointer into the block that addresses the relevant register.
540 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
541 */
542static void *decode_register(u8 modrm_reg, unsigned long *regs,
543 int highbyte_regs)
6aa8b732
AK		 544{
545 void *p;
546
547 p = &regs[modrm_reg];
548 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
549 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
550 return p;
551}
552
553static int read_descriptor(struct x86_emulate_ctxt *ctxt,
554 struct x86_emulate_ops *ops,
90de84f5 555 struct segmented_address addr,
6aa8b732
AK		 556 u16 *size, unsigned long *address, int op_bytes)
557{
558 int rc;
559
560 if (op_bytes == 2)
561 op_bytes = 3;
562 *address = 0;
90de84f5 563 rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2,
bcc55cba 564 ctxt->vcpu, &ctxt->exception);
1b30eaa8 565 if (rc != X86EMUL_CONTINUE)
6aa8b732 566 return rc;
30b31ab6
AK		 567 addr.ea += 2;
568 rc = ops->read_std(linear(ctxt, addr), address, op_bytes,
bcc55cba 569 ctxt->vcpu, &ctxt->exception);
6aa8b732
AK		 570 return rc;
571}
572
bbe9abbd
NK		 573static int test_cc(unsigned int condition, unsigned int flags)
574{
575 int rc = 0;
576
577 switch ((condition & 15) >> 1) {
578 case 0: /* o */
579 rc |= (flags & EFLG_OF);
580 break;
581 case 1: /* b/c/nae */
582 rc |= (flags & EFLG_CF);
583 break;
584 case 2: /* z/e */
585 rc |= (flags & EFLG_ZF);
586 break;
587 case 3: /* be/na */
588 rc |= (flags & (EFLG_CF|EFLG_ZF));
589 break;
590 case 4: /* s */
591 rc |= (flags & EFLG_SF);
592 break;
593 case 5: /* p/pe */
594 rc |= (flags & EFLG_PF);
595 break;
596 case 7: /* le/ng */
597 rc |= (flags & EFLG_ZF);
598 /* fall through */
599 case 6: /* l/nge */
600 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
601 break;
602 }
603
604 /* Odd condition identifiers (lsb == 1) have inverted sense. */
605 return (!!rc ^ (condition & 1));
606}
607
91ff3cb4
AK		 608static void fetch_register_operand(struct operand *op)
609{
610 switch (op->bytes) {
611 case 1:
612 op->val = *(u8 *)op->addr.reg;
613 break;
614 case 2:
615 op->val = *(u16 *)op->addr.reg;
616 break;
617 case 4:
618 op->val = *(u32 *)op->addr.reg;
619 break;
620 case 8:
621 op->val = *(u64 *)op->addr.reg;
622 break;
623 }
624}
625
3c118e24
AK		 626static void decode_register_operand(struct operand *op,
627 struct decode_cache *c,
3c118e24
AK		 628 int inhibit_bytereg)
629{
33615aa9 630 unsigned reg = c->modrm_reg;
9f1ef3f8 631 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 632
633 if (!(c->d & ModRM))
634 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 635 op->type = OP_REG;
636 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 637 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 638 op->bytes = 1;
639 } else {
1a6440ae 640 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 641 op->bytes = c->op_bytes;
3c118e24 642 }
91ff3cb4 643 fetch_register_operand(op);
3c118e24
AK		 644 op->orig_val = op->val;
645}
646
1c73ef66 647static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 648 struct x86_emulate_ops *ops,
649 struct operand *op)
1c73ef66
AK		 650{
651 struct decode_cache *c = &ctxt->decode;
652 u8 sib;
f5b4edcd 653 int index_reg = 0, base_reg = 0, scale;
3e2815e9 654 int rc = X86EMUL_CONTINUE;
2dbd0dd7 655 ulong modrm_ea = 0;
1c73ef66
AK		 656
657 if (c->rex_prefix) {
658 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
659 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
660 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
661 }
662
663 c->modrm = insn_fetch(u8, 1, c->eip);
664 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
665 c->modrm_reg |= (c->modrm & 0x38) >> 3;
666 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 667 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 668
669 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 670 op->type = OP_REG;
671 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
672 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 673 c->regs, c->d & ByteOp);
2dbd0dd7 674 fetch_register_operand(op);
1c73ef66
AK		 675 return rc;
676 }
677
2dbd0dd7
AK		 678 op->type = OP_MEM;
679
1c73ef66
AK		 680 if (c->ad_bytes == 2) {
681 unsigned bx = c->regs[VCPU_REGS_RBX];
682 unsigned bp = c->regs[VCPU_REGS_RBP];
683 unsigned si = c->regs[VCPU_REGS_RSI];
684 unsigned di = c->regs[VCPU_REGS_RDI];
685
686 /* 16-bit ModR/M decode. */
687 switch (c->modrm_mod) {
688 case 0:
689 if (c->modrm_rm == 6)
2dbd0dd7 690 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 691 break;
692 case 1:
2dbd0dd7 693 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 694 break;
695 case 2:
2dbd0dd7 696 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 697 break;
698 }
699 switch (c->modrm_rm) {
700 case 0:
2dbd0dd7 701 modrm_ea += bx + si;
1c73ef66
AK		 702 break;
703 case 1:
2dbd0dd7 704 modrm_ea += bx + di;
1c73ef66
AK		 705 break;
706 case 2:
2dbd0dd7 707 modrm_ea += bp + si;
1c73ef66
AK		 708 break;
709 case 3:
2dbd0dd7 710 modrm_ea += bp + di;
1c73ef66
AK		 711 break;
712 case 4:
2dbd0dd7 713 modrm_ea += si;
1c73ef66
AK		 714 break;
715 case 5:
2dbd0dd7 716 modrm_ea += di;
1c73ef66
AK		 717 break;
718 case 6:
719 if (c->modrm_mod != 0)
2dbd0dd7 720 modrm_ea += bp;
1c73ef66
AK		 721 break;
722 case 7:
2dbd0dd7 723 modrm_ea += bx;
1c73ef66
AK		 724 break;
725 }
726 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
727 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 728 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 729 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 730 } else {
731 /* 32/64-bit ModR/M decode. */
84411d85 732 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 733 sib = insn_fetch(u8, 1, c->eip);
734 index_reg |= (sib >> 3) & 7;
735 base_reg |= sib & 7;
736 scale = sib >> 6;
737
dc71d0f1 738 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 739 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 740 else
2dbd0dd7 741 modrm_ea += c->regs[base_reg];
dc71d0f1 742 if (index_reg != 4)
2dbd0dd7 743 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 744 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
745 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 746 c->rip_relative = 1;
84411d85 747 } else
2dbd0dd7 748 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 749 switch (c->modrm_mod) {
750 case 0:
751 if (c->modrm_rm == 5)
2dbd0dd7 752 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 753 break;
754 case 1:
2dbd0dd7 755 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 756 break;
757 case 2:
2dbd0dd7 758 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 759 break;
760 }
761 }
90de84f5 762 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 763done:
764 return rc;
765}
766
767static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 768 struct x86_emulate_ops *ops,
769 struct operand *op)
1c73ef66
AK		 770{
771 struct decode_cache *c = &ctxt->decode;
3e2815e9 772 int rc = X86EMUL_CONTINUE;
1c73ef66 773
2dbd0dd7 774 op->type = OP_MEM;
1c73ef66
AK		 775 switch (c->ad_bytes) {
776 case 2:
90de84f5 777 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 778 break;
779 case 4:
90de84f5 780 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 781 break;
782 case 8:
90de84f5 783 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 784 break;
785 }
786done:
787 return rc;
788}
789
35c843c4
WY		 790static void fetch_bit_operand(struct decode_cache *c)
791{
7129eeca 792 long sv = 0, mask;
35c843c4 793
3885f18f 794 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 795 mask = ~(c->dst.bytes * 8 - 1);
796
797 if (c->src.bytes == 2)
798 sv = (s16)c->src.val & (s16)mask;
799 else if (c->src.bytes == 4)
800 sv = (s32)c->src.val & (s32)mask;
801
90de84f5 802 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 803 }
ba7ff2b7
WY		 804
805 /* only subword offset */
806 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 807}
808
dde7e6d1
AK		 809static int read_emulated(struct x86_emulate_ctxt *ctxt,
810 struct x86_emulate_ops *ops,
811 unsigned long addr, void *dest, unsigned size)
6aa8b732 812{
dde7e6d1
AK		 813 int rc;
814 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 815
dde7e6d1
AK		 816 while (size) {
817 int n = min(size, 8u);
818 size -= n;
819 if (mc->pos < mc->end)
820 goto read_cached;
5cd21917 821
bcc55cba
AK		 822 rc = ops->read_emulated(addr, mc->data + mc->end, n,
823 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 824 if (rc != X86EMUL_CONTINUE)
825 return rc;
826 mc->end += n;
6aa8b732 827
dde7e6d1
AK		 828 read_cached:
829 memcpy(dest, mc->data + mc->pos, n);
830 mc->pos += n;
831 dest += n;
832 addr += n;
6aa8b732 833 }
dde7e6d1
AK		 834 return X86EMUL_CONTINUE;
835}
6aa8b732 836
dde7e6d1
AK		 837static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
838 struct x86_emulate_ops *ops,
839 unsigned int size, unsigned short port,
840 void *dest)
841{
842 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 843
dde7e6d1
AK		 844 if (rc->pos == rc->end) { /* refill pio read ahead */
845 struct decode_cache *c = &ctxt->decode;
846 unsigned int in_page, n;
847 unsigned int count = c->rep_prefix ?
848 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
849 in_page = (ctxt->eflags & EFLG_DF) ?
850 offset_in_page(c->regs[VCPU_REGS_RDI]) :
851 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
852 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
853 count);
854 if (n == 0)
855 n = 1;
856 rc->pos = rc->end = 0;
857 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
858 return 0;
859 rc->end = n * size;
6aa8b732
AK		 860 }
861
dde7e6d1
AK		 862 memcpy(dest, rc->data + rc->pos, size);
863 rc->pos += size;
864 return 1;
865}
6aa8b732 866
dde7e6d1
AK		 867static u32 desc_limit_scaled(struct desc_struct *desc)
868{
869 u32 limit = get_desc_limit(desc);
6aa8b732 870
dde7e6d1
AK		 871 return desc->g ? (limit << 12) | 0xfff : limit;
872}
6aa8b732 873
dde7e6d1
AK		 874static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
875 struct x86_emulate_ops *ops,
876 u16 selector, struct desc_ptr *dt)
877{
878 if (selector & 1 << 2) {
879 struct desc_struct desc;
880 memset (dt, 0, sizeof *dt);
881 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
882 return;
e09d082c 883
dde7e6d1
AK		 884 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
885 dt->address = get_desc_base(&desc);
886 } else
887 ops->get_gdt(dt, ctxt->vcpu);
888}
120df890 889
dde7e6d1
AK		 890/* allowed just for 8 bytes segments */
891static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
892 struct x86_emulate_ops *ops,
893 u16 selector, struct desc_struct *desc)
894{
895 struct desc_ptr dt;
896 u16 index = selector >> 3;
897 int ret;
dde7e6d1 898 ulong addr;
120df890 899
dde7e6d1 900 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 901
35d3d4a1
AK		 902 if (dt.size < index * 8 + 7)
903 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 904 addr = dt.address + index * 8;
bcc55cba
AK		 905 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
906 &ctxt->exception);
e09d082c 907
dde7e6d1
AK		 908 return ret;
909}
ef65c889 910
dde7e6d1
AK		 911/* allowed just for 8 bytes segments */
912static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
913 struct x86_emulate_ops *ops,
914 u16 selector, struct desc_struct *desc)
915{
916 struct desc_ptr dt;
917 u16 index = selector >> 3;
dde7e6d1
AK		 918 ulong addr;
919 int ret;
6aa8b732 920
dde7e6d1 921 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 922
35d3d4a1
AK		 923 if (dt.size < index * 8 + 7)
924 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 925
dde7e6d1 926 addr = dt.address + index * 8;
bcc55cba
AK		 927 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
928 &ctxt->exception);
c7e75a3d 929
dde7e6d1
AK		 930 return ret;
931}
c7e75a3d 932
dde7e6d1
AK		 933static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
934 struct x86_emulate_ops *ops,
935 u16 selector, int seg)
936{
937 struct desc_struct seg_desc;
938 u8 dpl, rpl, cpl;
939 unsigned err_vec = GP_VECTOR;
940 u32 err_code = 0;
941 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
942 int ret;
69f55cb1 943
dde7e6d1 944 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 945
dde7e6d1
AK		 946 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
947 || ctxt->mode == X86EMUL_MODE_REAL) {
948 /* set real mode segment descriptor */
949 set_desc_base(&seg_desc, selector << 4);
950 set_desc_limit(&seg_desc, 0xffff);
951 seg_desc.type = 3;
952 seg_desc.p = 1;
953 seg_desc.s = 1;
954 goto load;
955 }
956
957 /* NULL selector is not valid for TR, CS and SS */
958 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
959 && null_selector)
960 goto exception;
961
962 /* TR should be in GDT only */
963 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
964 goto exception;
965
966 if (null_selector) /* for NULL selector skip all following checks */
967 goto load;
968
969 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
970 if (ret != X86EMUL_CONTINUE)
971 return ret;
972
973 err_code = selector & 0xfffc;
974 err_vec = GP_VECTOR;
975
976 /* can't load system descriptor into segment selecor */
977 if (seg <= VCPU_SREG_GS && !seg_desc.s)
978 goto exception;
979
980 if (!seg_desc.p) {
981 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
982 goto exception;
983 }
984
985 rpl = selector & 3;
986 dpl = seg_desc.dpl;
987 cpl = ops->cpl(ctxt->vcpu);
988
989 switch (seg) {
990 case VCPU_SREG_SS:
991 /*
992 * segment is not a writable data segment or segment
993 * selector's RPL != CPL or segment selector's RPL != CPL
994 */
995 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
996 goto exception;
6aa8b732 997 break;
dde7e6d1
AK		 998 case VCPU_SREG_CS:
999 if (!(seg_desc.type & 8))
1000 goto exception;
1001
1002 if (seg_desc.type & 4) {
1003 /* conforming */
1004 if (dpl > cpl)
1005 goto exception;
1006 } else {
1007 /* nonconforming */
1008 if (rpl > cpl || dpl != cpl)
1009 goto exception;
1010 }
1011 /* CS(RPL) <- CPL */
1012 selector = (selector & 0xfffc) | cpl;
6aa8b732 1013 break;
dde7e6d1
AK		 1014 case VCPU_SREG_TR:
1015 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1016 goto exception;
1017 break;
1018 case VCPU_SREG_LDTR:
1019 if (seg_desc.s || seg_desc.type != 2)
1020 goto exception;
1021 break;
1022 default: /* DS, ES, FS, or GS */
4e62417b 1023 /*
dde7e6d1
AK		 1024 * segment is not a data or readable code segment or
1025 * ((segment is a data or nonconforming code segment)
1026 * and (both RPL and CPL > DPL))
4e62417b 1027 */
dde7e6d1
AK		 1028 if ((seg_desc.type & 0xa) == 0x8 ||
1029 (((seg_desc.type & 0xc) != 0xc) &&
1030 (rpl > dpl && cpl > dpl)))
1031 goto exception;
6aa8b732 1032 break;
dde7e6d1
AK		 1033 }
1034
1035 if (seg_desc.s) {
1036 /* mark segment as accessed */
1037 seg_desc.type |= 1;
1038 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1039 if (ret != X86EMUL_CONTINUE)
1040 return ret;
1041 }
1042load:
1043 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1044 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1045 return X86EMUL_CONTINUE;
1046exception:
1047 emulate_exception(ctxt, err_vec, err_code, true);
1048 return X86EMUL_PROPAGATE_FAULT;
1049}
1050
31be40b3
WY		 1051static void write_register_operand(struct operand *op)
1052{
1053 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1054 switch (op->bytes) {
1055 case 1:
1056 *(u8 *)op->addr.reg = (u8)op->val;
1057 break;
1058 case 2:
1059 *(u16 *)op->addr.reg = (u16)op->val;
1060 break;
1061 case 4:
1062 *op->addr.reg = (u32)op->val;
1063 break; /* 64b: zero-extend */
1064 case 8:
1065 *op->addr.reg = op->val;
1066 break;
1067 }
1068}
1069
dde7e6d1
AK		 1070static inline int writeback(struct x86_emulate_ctxt *ctxt,
1071 struct x86_emulate_ops *ops)
1072{
1073 int rc;
1074 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1075
1076 switch (c->dst.type) {
1077 case OP_REG:
31be40b3 1078 write_register_operand(&c->dst);
6aa8b732 1079 break;
dde7e6d1
AK		 1080 case OP_MEM:
1081 if (c->lock_prefix)
1082 rc = ops->cmpxchg_emulated(
90de84f5 1083 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1084 &c->dst.orig_val,
1085 &c->dst.val,
1086 c->dst.bytes,
bcc55cba 1087 &ctxt->exception,
dde7e6d1 1088 ctxt->vcpu);
341de7e3 1089 else
dde7e6d1 1090 rc = ops->write_emulated(
90de84f5 1091 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1092 &c->dst.val,
1093 c->dst.bytes,
bcc55cba 1094 &ctxt->exception,
dde7e6d1 1095 ctxt->vcpu);
dde7e6d1
AK		 1096 if (rc != X86EMUL_CONTINUE)
1097 return rc;
a682e354 1098 break;
dde7e6d1
AK		 1099 case OP_NONE:
1100 /* no writeback */
414e6277 1101 break;
dde7e6d1 1102 default:
414e6277 1103 break;
6aa8b732 1104 }
dde7e6d1
AK		 1105 return X86EMUL_CONTINUE;
1106}
6aa8b732 1107
dde7e6d1
AK		 1108static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops)
1110{
1111 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1112
dde7e6d1
AK		 1113 c->dst.type = OP_MEM;
1114 c->dst.bytes = c->op_bytes;
1115 c->dst.val = c->src.val;
1116 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1117 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1118 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1119}
69f55cb1 1120
dde7e6d1
AK		 1121static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1122 struct x86_emulate_ops *ops,
1123 void *dest, int len)
1124{
1125 struct decode_cache *c = &ctxt->decode;
1126 int rc;
90de84f5 1127 struct segmented_address addr;
8b4caf66 1128
90de84f5
AK		 1129 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1130 addr.seg = VCPU_SREG_SS;
1131 rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len);
dde7e6d1
AK		 1132 if (rc != X86EMUL_CONTINUE)
1133 return rc;
1134
1135 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1136 return rc;
8b4caf66
LV		 1137}
1138
dde7e6d1
AK		 1139static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1140 struct x86_emulate_ops *ops,
1141 void *dest, int len)
9de41573
GN		 1142{
1143 int rc;
dde7e6d1
AK		 1144 unsigned long val, change_mask;
1145 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1146 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1147
dde7e6d1
AK		 1148 rc = emulate_pop(ctxt, ops, &val, len);
1149 if (rc != X86EMUL_CONTINUE)
1150 return rc;
9de41573 1151
dde7e6d1
AK		 1152 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1153 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1154
dde7e6d1
AK		 1155 switch(ctxt->mode) {
1156 case X86EMUL_MODE_PROT64:
1157 case X86EMUL_MODE_PROT32:
1158 case X86EMUL_MODE_PROT16:
1159 if (cpl == 0)
1160 change_mask |= EFLG_IOPL;
1161 if (cpl <= iopl)
1162 change_mask |= EFLG_IF;
1163 break;
1164 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1165 if (iopl < 3)
1166 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1167 change_mask |= EFLG_IF;
1168 break;
1169 default: /* real mode */
1170 change_mask |= (EFLG_IOPL | EFLG_IF);
1171 break;
9de41573 1172 }
dde7e6d1
AK		 1173
1174 *(unsigned long *)dest =
1175 (ctxt->eflags & ~change_mask) | (val & change_mask);
1176
1177 return rc;
9de41573
GN		 1178}
1179
dde7e6d1
AK		 1180static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1181 struct x86_emulate_ops *ops, int seg)
7b262e90 1182{
dde7e6d1 1183 struct decode_cache *c = &ctxt->decode;
7b262e90 1184
dde7e6d1 1185 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1186
dde7e6d1 1187 emulate_push(ctxt, ops);
7b262e90
GN		 1188}
1189
dde7e6d1
AK		 1190static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1191 struct x86_emulate_ops *ops, int seg)
38ba30ba 1192{
dde7e6d1
AK		 1193 struct decode_cache *c = &ctxt->decode;
1194 unsigned long selector;
1195 int rc;
38ba30ba 1196
dde7e6d1
AK		 1197 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1198 if (rc != X86EMUL_CONTINUE)
1199 return rc;
1200
1201 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1202 return rc;
38ba30ba
GN		 1203}
1204
dde7e6d1
AK		 1205static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1206 struct x86_emulate_ops *ops)
38ba30ba 1207{
dde7e6d1
AK		 1208 struct decode_cache *c = &ctxt->decode;
1209 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1210 int rc = X86EMUL_CONTINUE;
1211 int reg = VCPU_REGS_RAX;
38ba30ba 1212
dde7e6d1
AK		 1213 while (reg <= VCPU_REGS_RDI) {
1214 (reg == VCPU_REGS_RSP) ?
1215 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1216
dde7e6d1 1217 emulate_push(ctxt, ops);
38ba30ba 1218
dde7e6d1
AK		 1219 rc = writeback(ctxt, ops);
1220 if (rc != X86EMUL_CONTINUE)
1221 return rc;
38ba30ba 1222
dde7e6d1 1223 ++reg;
38ba30ba 1224 }
38ba30ba 1225
dde7e6d1
AK		 1226 /* Disable writeback. */
1227 c->dst.type = OP_NONE;
1228
1229 return rc;
38ba30ba
GN		 1230}
1231
dde7e6d1
AK		 1232static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1233 struct x86_emulate_ops *ops)
38ba30ba 1234{
dde7e6d1
AK		 1235 struct decode_cache *c = &ctxt->decode;
1236 int rc = X86EMUL_CONTINUE;
1237 int reg = VCPU_REGS_RDI;
38ba30ba 1238
dde7e6d1
AK		 1239 while (reg >= VCPU_REGS_RAX) {
1240 if (reg == VCPU_REGS_RSP) {
1241 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1242 c->op_bytes);
1243 --reg;
1244 }
38ba30ba 1245
dde7e6d1
AK		 1246 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1247 if (rc != X86EMUL_CONTINUE)
1248 break;
1249 --reg;
38ba30ba 1250 }
dde7e6d1 1251 return rc;
38ba30ba
GN		 1252}
1253
6e154e56
MG		 1254int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1255 struct x86_emulate_ops *ops, int irq)
1256{
1257 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1258 int rc;
6e154e56
MG		 1259 struct desc_ptr dt;
1260 gva_t cs_addr;
1261 gva_t eip_addr;
1262 u16 cs, eip;
6e154e56
MG		 1263
1264 /* TODO: Add limit checks */
1265 c->src.val = ctxt->eflags;
1266 emulate_push(ctxt, ops);
5c56e1cf
AK		 1267 rc = writeback(ctxt, ops);
1268 if (rc != X86EMUL_CONTINUE)
1269 return rc;
6e154e56
MG		 1270
1271 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1272
1273 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1274 emulate_push(ctxt, ops);
5c56e1cf
AK		 1275 rc = writeback(ctxt, ops);
1276 if (rc != X86EMUL_CONTINUE)
1277 return rc;
6e154e56
MG		 1278
1279 c->src.val = c->eip;
1280 emulate_push(ctxt, ops);
5c56e1cf
AK		 1281 rc = writeback(ctxt, ops);
1282 if (rc != X86EMUL_CONTINUE)
1283 return rc;
1284
1285 c->dst.type = OP_NONE;
6e154e56
MG		 1286
1287 ops->get_idt(&dt, ctxt->vcpu);
1288
1289 eip_addr = dt.address + (irq << 2);
1290 cs_addr = dt.address + (irq << 2) + 2;
1291
bcc55cba 1292 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1293 if (rc != X86EMUL_CONTINUE)
1294 return rc;
1295
bcc55cba 1296 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1297 if (rc != X86EMUL_CONTINUE)
1298 return rc;
1299
1300 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1301 if (rc != X86EMUL_CONTINUE)
1302 return rc;
1303
1304 c->eip = eip;
1305
1306 return rc;
1307}
1308
1309static int emulate_int(struct x86_emulate_ctxt *ctxt,
1310 struct x86_emulate_ops *ops, int irq)
1311{
1312 switch(ctxt->mode) {
1313 case X86EMUL_MODE_REAL:
1314 return emulate_int_real(ctxt, ops, irq);
1315 case X86EMUL_MODE_VM86:
1316 case X86EMUL_MODE_PROT16:
1317 case X86EMUL_MODE_PROT32:
1318 case X86EMUL_MODE_PROT64:
1319 default:
1320 /* Protected mode interrupts unimplemented yet */
1321 return X86EMUL_UNHANDLEABLE;
1322 }
1323}
1324
dde7e6d1
AK		 1325static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1326 struct x86_emulate_ops *ops)
38ba30ba 1327{
dde7e6d1
AK		 1328 struct decode_cache *c = &ctxt->decode;
1329 int rc = X86EMUL_CONTINUE;
1330 unsigned long temp_eip = 0;
1331 unsigned long temp_eflags = 0;
1332 unsigned long cs = 0;
1333 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1334 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1335 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1336 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1337
dde7e6d1 1338 /* TODO: Add stack limit check */
38ba30ba 1339
dde7e6d1 1340 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1341
dde7e6d1
AK		 1342 if (rc != X86EMUL_CONTINUE)
1343 return rc;
38ba30ba 1344
35d3d4a1
AK		 1345 if (temp_eip & ~0xffff)
1346 return emulate_gp(ctxt, 0);
38ba30ba 1347
dde7e6d1 1348 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1349
dde7e6d1
AK		 1350 if (rc != X86EMUL_CONTINUE)
1351 return rc;
38ba30ba 1352
dde7e6d1 1353 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1354
dde7e6d1
AK		 1355 if (rc != X86EMUL_CONTINUE)
1356 return rc;
38ba30ba 1357
dde7e6d1 1358 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1359
dde7e6d1
AK		 1360 if (rc != X86EMUL_CONTINUE)
1361 return rc;
38ba30ba 1362
dde7e6d1 1363 c->eip = temp_eip;
38ba30ba 1364
38ba30ba 1365
dde7e6d1
AK		 1366 if (c->op_bytes == 4)
1367 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1368 else if (c->op_bytes == 2) {
1369 ctxt->eflags &= ~0xffff;
1370 ctxt->eflags |= temp_eflags;
38ba30ba 1371 }
dde7e6d1
AK		 1372
1373 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1374 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1375
1376 return rc;
38ba30ba
GN		 1377}
1378
dde7e6d1
AK		 1379static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1380 struct x86_emulate_ops* ops)
c37eda13 1381{
dde7e6d1
AK		 1382 switch(ctxt->mode) {
1383 case X86EMUL_MODE_REAL:
1384 return emulate_iret_real(ctxt, ops);
1385 case X86EMUL_MODE_VM86:
1386 case X86EMUL_MODE_PROT16:
1387 case X86EMUL_MODE_PROT32:
1388 case X86EMUL_MODE_PROT64:
c37eda13 1389 default:
dde7e6d1
AK		 1390 /* iret from protected mode unimplemented yet */
1391 return X86EMUL_UNHANDLEABLE;
c37eda13 1392 }
c37eda13
WY		 1393}
1394
dde7e6d1 1395static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1396 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1397{
1398 struct decode_cache *c = &ctxt->decode;
1399
dde7e6d1 1400 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1401}
1402
dde7e6d1 1403static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1404{
05f086f8 1405 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1406 switch (c->modrm_reg) {
1407 case 0: /* rol */
05f086f8 1408 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1409 break;
1410 case 1: /* ror */
05f086f8 1411 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1412 break;
1413 case 2: /* rcl */
05f086f8 1414 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1415 break;
1416 case 3: /* rcr */
05f086f8 1417 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1418 break;
1419 case 4: /* sal/shl */
1420 case 6: /* sal/shl */
05f086f8 1421 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1422 break;
1423 case 5: /* shr */
05f086f8 1424 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1425 break;
1426 case 7: /* sar */
05f086f8 1427 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1428 break;
1429 }
1430}
1431
1432static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1433 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1434{
1435 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1436 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1437 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1438 u8 de = 0;
8cdbd2c9
LV		 1439
1440 switch (c->modrm_reg) {
1441 case 0 ... 1: /* test */
05f086f8 1442 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1443 break;
1444 case 2: /* not */
1445 c->dst.val = ~c->dst.val;
1446 break;
1447 case 3: /* neg */
05f086f8 1448 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1449 break;
3f9f53b0
MG		 1450 case 4: /* mul */
1451 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1452 break;
1453 case 5: /* imul */
1454 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1455 break;
1456 case 6: /* div */
34d1f490
AK		 1457 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1458 ctxt->eflags, de);
3f9f53b0
MG		 1459 break;
1460 case 7: /* idiv */
34d1f490
AK		 1461 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1462 ctxt->eflags, de);
3f9f53b0 1463 break;
8cdbd2c9 1464 default:
8c5eee30 1465 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1466 }
34d1f490
AK		 1467 if (de)
1468 return emulate_de(ctxt);
8c5eee30 1469 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1470}
1471
1472static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1473 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1474{
1475 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1476
1477 switch (c->modrm_reg) {
1478 case 0: /* inc */
05f086f8 1479 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1480 break;
1481 case 1: /* dec */
05f086f8 1482 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1483 break;
d19292e4
MG		 1484 case 2: /* call near abs */ {
1485 long int old_eip;
1486 old_eip = c->eip;
1487 c->eip = c->src.val;
1488 c->src.val = old_eip;
79168fd1 1489 emulate_push(ctxt, ops);
d19292e4
MG		 1490 break;
1491 }
8cdbd2c9 1492 case 4: /* jmp abs */
fd60754e 1493 c->eip = c->src.val;
8cdbd2c9
LV		 1494 break;
1495 case 6: /* push */
79168fd1 1496 emulate_push(ctxt, ops);
8cdbd2c9 1497 break;
8cdbd2c9 1498 }
1b30eaa8 1499 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1500}
1501
1502static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1503 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1504{
1505 struct decode_cache *c = &ctxt->decode;
16518d5a 1506 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1507
1508 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1509 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1510 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1511 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1512 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1513 } else {
16518d5a
AK		 1514 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1515 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1516
05f086f8 1517 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1518 }
1b30eaa8 1519 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1520}
1521
a77ab5ea
AK		 1522static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1523 struct x86_emulate_ops *ops)
1524{
1525 struct decode_cache *c = &ctxt->decode;
1526 int rc;
1527 unsigned long cs;
1528
1529 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1530 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1531 return rc;
1532 if (c->op_bytes == 4)
1533 c->eip = (u32)c->eip;
1534 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1535 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1536 return rc;
2e873022 1537 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1538 return rc;
1539}
1540
09b5f4d3
WY		 1541static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1542 struct x86_emulate_ops *ops, int seg)
1543{
1544 struct decode_cache *c = &ctxt->decode;
1545 unsigned short sel;
1546 int rc;
1547
1548 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1549
1550 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1551 if (rc != X86EMUL_CONTINUE)
1552 return rc;
1553
1554 c->dst.val = c->src.val;
1555 return rc;
1556}
1557
e66bb2cc
AP		 1558static inline void
1559setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1560 struct x86_emulate_ops *ops, struct desc_struct *cs,
1561 struct desc_struct *ss)
e66bb2cc 1562{
79168fd1
GN		 1563 memset(cs, 0, sizeof(struct desc_struct));
1564 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1565 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1566
1567 cs->l = 0; /* will be adjusted later */
79168fd1 1568 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1569 cs->g = 1; /* 4kb granularity */
79168fd1 1570 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1571 cs->type = 0x0b; /* Read, Execute, Accessed */
1572 cs->s = 1;
1573 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1574 cs->p = 1;
1575 cs->d = 1;
e66bb2cc 1576
79168fd1
GN		 1577 set_desc_base(ss, 0); /* flat segment */
1578 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1579 ss->g = 1; /* 4kb granularity */
1580 ss->s = 1;
1581 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1582 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1583 ss->dpl = 0;
79168fd1 1584 ss->p = 1;
e66bb2cc
AP		 1585}
1586
1587static int
3fb1b5db 1588emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1589{
1590 struct decode_cache *c = &ctxt->decode;
79168fd1 1591 struct desc_struct cs, ss;
e66bb2cc 1592 u64 msr_data;
79168fd1 1593 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1594
1595 /* syscall is not available in real mode */
2e901c4c 1596 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1597 ctxt->mode == X86EMUL_MODE_VM86)
1598 return emulate_ud(ctxt);
e66bb2cc 1599
79168fd1 1600 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1601
3fb1b5db 1602 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1603 msr_data >>= 32;
79168fd1
GN		 1604 cs_sel = (u16)(msr_data & 0xfffc);
1605 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1606
1607 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1608 cs.d = 0;
e66bb2cc
AP		 1609 cs.l = 1;
1610 }
79168fd1
GN		 1611 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1612 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1613 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1614 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1615
1616 c->regs[VCPU_REGS_RCX] = c->eip;
1617 if (is_long_mode(ctxt->vcpu)) {
1618#ifdef CONFIG_X86_64
1619 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1620
3fb1b5db
GN		 1621 ops->get_msr(ctxt->vcpu,
1622 ctxt->mode == X86EMUL_MODE_PROT64 ?
1623 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1624 c->eip = msr_data;
1625
3fb1b5db 1626 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1627 ctxt->eflags &= ~(msr_data | EFLG_RF);
1628#endif
1629 } else {
1630 /* legacy mode */
3fb1b5db 1631 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1632 c->eip = (u32)msr_data;
1633
1634 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1635 }
1636
e54cfa97 1637 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1638}
1639
8c604352 1640static int
3fb1b5db 1641emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1642{
1643 struct decode_cache *c = &ctxt->decode;
79168fd1 1644 struct desc_struct cs, ss;
8c604352 1645 u64 msr_data;
79168fd1 1646 u16 cs_sel, ss_sel;
8c604352 1647
a0044755 1648 /* inject #GP if in real mode */
35d3d4a1
AK		 1649 if (ctxt->mode == X86EMUL_MODE_REAL)
1650 return emulate_gp(ctxt, 0);
8c604352
AP		 1651
1652 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1653 * Therefore, we inject an #UD.
1654 */
35d3d4a1
AK		 1655 if (ctxt->mode == X86EMUL_MODE_PROT64)
1656 return emulate_ud(ctxt);
8c604352 1657
79168fd1 1658 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1659
3fb1b5db 1660 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1661 switch (ctxt->mode) {
1662 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1663 if ((msr_data & 0xfffc) == 0x0)
1664 return emulate_gp(ctxt, 0);
8c604352
AP		 1665 break;
1666 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1667 if (msr_data == 0x0)
1668 return emulate_gp(ctxt, 0);
8c604352
AP		 1669 break;
1670 }
1671
1672 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1673 cs_sel = (u16)msr_data;
1674 cs_sel &= ~SELECTOR_RPL_MASK;
1675 ss_sel = cs_sel + 8;
1676 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1677 if (ctxt->mode == X86EMUL_MODE_PROT64
1678 || is_long_mode(ctxt->vcpu)) {
79168fd1 1679 cs.d = 0;
8c604352
AP		 1680 cs.l = 1;
1681 }
1682
79168fd1
GN		 1683 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1684 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1685 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1686 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1687
3fb1b5db 1688 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1689 c->eip = msr_data;
1690
3fb1b5db 1691 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1692 c->regs[VCPU_REGS_RSP] = msr_data;
1693
e54cfa97 1694 return X86EMUL_CONTINUE;
8c604352
AP		 1695}
1696
4668f050 1697static int
3fb1b5db 1698emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1699{
1700 struct decode_cache *c = &ctxt->decode;
79168fd1 1701 struct desc_struct cs, ss;
4668f050
AP		 1702 u64 msr_data;
1703 int usermode;
79168fd1 1704 u16 cs_sel, ss_sel;
4668f050 1705
a0044755
GN		 1706 /* inject #GP if in real mode or Virtual 8086 mode */
1707 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1708 ctxt->mode == X86EMUL_MODE_VM86)
1709 return emulate_gp(ctxt, 0);
4668f050 1710
79168fd1 1711 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1712
1713 if ((c->rex_prefix & 0x8) != 0x0)
1714 usermode = X86EMUL_MODE_PROT64;
1715 else
1716 usermode = X86EMUL_MODE_PROT32;
1717
1718 cs.dpl = 3;
1719 ss.dpl = 3;
3fb1b5db 1720 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1721 switch (usermode) {
1722 case X86EMUL_MODE_PROT32:
79168fd1 1723 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1724 if ((msr_data & 0xfffc) == 0x0)
1725 return emulate_gp(ctxt, 0);
79168fd1 1726 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1727 break;
1728 case X86EMUL_MODE_PROT64:
79168fd1 1729 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1730 if (msr_data == 0x0)
1731 return emulate_gp(ctxt, 0);
79168fd1
GN		 1732 ss_sel = cs_sel + 8;
1733 cs.d = 0;
4668f050
AP		 1734 cs.l = 1;
1735 break;
1736 }
79168fd1
GN		 1737 cs_sel |= SELECTOR_RPL_MASK;
1738 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1739
79168fd1
GN		 1740 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1741 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1742 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1743 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1744
bdb475a3
GN		 1745 c->eip = c->regs[VCPU_REGS_RDX];
1746 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1747
e54cfa97 1748 return X86EMUL_CONTINUE;
4668f050
AP		 1749}
1750
9c537244
GN		 1751static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1752 struct x86_emulate_ops *ops)
f850e2e6
GN		 1753{
1754 int iopl;
1755 if (ctxt->mode == X86EMUL_MODE_REAL)
1756 return false;
1757 if (ctxt->mode == X86EMUL_MODE_VM86)
1758 return true;
1759 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1760 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1761}
1762
1763static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1764 struct x86_emulate_ops *ops,
1765 u16 port, u16 len)
1766{
79168fd1 1767 struct desc_struct tr_seg;
f850e2e6
GN		 1768 int r;
1769 u16 io_bitmap_ptr;
1770 u8 perm, bit_idx = port & 0x7;
1771 unsigned mask = (1 << len) - 1;
1772
79168fd1
GN		 1773 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1774 if (!tr_seg.p)
f850e2e6 1775 return false;
79168fd1 1776 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1777 return false;
79168fd1
GN		 1778 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1779 ctxt->vcpu, NULL);
f850e2e6
GN		 1780 if (r != X86EMUL_CONTINUE)
1781 return false;
79168fd1 1782 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1783 return false;
79168fd1
GN		 1784 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1785 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1786 if (r != X86EMUL_CONTINUE)
1787 return false;
1788 if ((perm >> bit_idx) & mask)
1789 return false;
1790 return true;
1791}
1792
1793static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1794 struct x86_emulate_ops *ops,
1795 u16 port, u16 len)
1796{
4fc40f07
GN		 1797 if (ctxt->perm_ok)
1798 return true;
1799
9c537244 1800 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1801 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1802 return false;
4fc40f07
GN		 1803
1804 ctxt->perm_ok = true;
1805
f850e2e6
GN		 1806 return true;
1807}
1808
38ba30ba
GN		 1809static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1810 struct x86_emulate_ops *ops,
1811 struct tss_segment_16 *tss)
1812{
1813 struct decode_cache *c = &ctxt->decode;
1814
1815 tss->ip = c->eip;
1816 tss->flag = ctxt->eflags;
1817 tss->ax = c->regs[VCPU_REGS_RAX];
1818 tss->cx = c->regs[VCPU_REGS_RCX];
1819 tss->dx = c->regs[VCPU_REGS_RDX];
1820 tss->bx = c->regs[VCPU_REGS_RBX];
1821 tss->sp = c->regs[VCPU_REGS_RSP];
1822 tss->bp = c->regs[VCPU_REGS_RBP];
1823 tss->si = c->regs[VCPU_REGS_RSI];
1824 tss->di = c->regs[VCPU_REGS_RDI];
1825
1826 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1827 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1828 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1829 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1830 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1831}
1832
1833static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1834 struct x86_emulate_ops *ops,
1835 struct tss_segment_16 *tss)
1836{
1837 struct decode_cache *c = &ctxt->decode;
1838 int ret;
1839
1840 c->eip = tss->ip;
1841 ctxt->eflags = tss->flag | 2;
1842 c->regs[VCPU_REGS_RAX] = tss->ax;
1843 c->regs[VCPU_REGS_RCX] = tss->cx;
1844 c->regs[VCPU_REGS_RDX] = tss->dx;
1845 c->regs[VCPU_REGS_RBX] = tss->bx;
1846 c->regs[VCPU_REGS_RSP] = tss->sp;
1847 c->regs[VCPU_REGS_RBP] = tss->bp;
1848 c->regs[VCPU_REGS_RSI] = tss->si;
1849 c->regs[VCPU_REGS_RDI] = tss->di;
1850
1851 /*
1852 * SDM says that segment selectors are loaded before segment
1853 * descriptors
1854 */
1855 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1856 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1857 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1858 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1859 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1860
1861 /*
1862 * Now load segment descriptors. If fault happenes at this stage
1863 * it is handled in a context of new task
1864 */
1865 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1866 if (ret != X86EMUL_CONTINUE)
1867 return ret;
1868 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1869 if (ret != X86EMUL_CONTINUE)
1870 return ret;
1871 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1872 if (ret != X86EMUL_CONTINUE)
1873 return ret;
1874 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1875 if (ret != X86EMUL_CONTINUE)
1876 return ret;
1877 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1878 if (ret != X86EMUL_CONTINUE)
1879 return ret;
1880
1881 return X86EMUL_CONTINUE;
1882}
1883
1884static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1885 struct x86_emulate_ops *ops,
1886 u16 tss_selector, u16 old_tss_sel,
1887 ulong old_tss_base, struct desc_struct *new_desc)
1888{
1889 struct tss_segment_16 tss_seg;
1890 int ret;
bcc55cba 1891 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 1892
1893 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1894 &ctxt->exception);
db297e3d 1895 if (ret != X86EMUL_CONTINUE)
38ba30ba 1896 /* FIXME: need to provide precise fault address */
38ba30ba 1897 return ret;
38ba30ba
GN		 1898
1899 save_state_to_tss16(ctxt, ops, &tss_seg);
1900
1901 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1902 &ctxt->exception);
db297e3d 1903 if (ret != X86EMUL_CONTINUE)
38ba30ba 1904 /* FIXME: need to provide precise fault address */
38ba30ba 1905 return ret;
38ba30ba
GN		 1906
1907 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1908 &ctxt->exception);
db297e3d 1909 if (ret != X86EMUL_CONTINUE)
38ba30ba 1910 /* FIXME: need to provide precise fault address */
38ba30ba 1911 return ret;
38ba30ba
GN		 1912
1913 if (old_tss_sel != 0xffff) {
1914 tss_seg.prev_task_link = old_tss_sel;
1915
1916 ret = ops->write_std(new_tss_base,
1917 &tss_seg.prev_task_link,
1918 sizeof tss_seg.prev_task_link,
bcc55cba 1919 ctxt->vcpu, &ctxt->exception);
db297e3d 1920 if (ret != X86EMUL_CONTINUE)
38ba30ba 1921 /* FIXME: need to provide precise fault address */
38ba30ba 1922 return ret;
38ba30ba
GN		 1923 }
1924
1925 return load_state_from_tss16(ctxt, ops, &tss_seg);
1926}
1927
1928static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1929 struct x86_emulate_ops *ops,
1930 struct tss_segment_32 *tss)
1931{
1932 struct decode_cache *c = &ctxt->decode;
1933
1934 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1935 tss->eip = c->eip;
1936 tss->eflags = ctxt->eflags;
1937 tss->eax = c->regs[VCPU_REGS_RAX];
1938 tss->ecx = c->regs[VCPU_REGS_RCX];
1939 tss->edx = c->regs[VCPU_REGS_RDX];
1940 tss->ebx = c->regs[VCPU_REGS_RBX];
1941 tss->esp = c->regs[VCPU_REGS_RSP];
1942 tss->ebp = c->regs[VCPU_REGS_RBP];
1943 tss->esi = c->regs[VCPU_REGS_RSI];
1944 tss->edi = c->regs[VCPU_REGS_RDI];
1945
1946 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1947 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1948 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1949 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1950 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1951 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1952 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1953}
1954
1955static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1956 struct x86_emulate_ops *ops,
1957 struct tss_segment_32 *tss)
1958{
1959 struct decode_cache *c = &ctxt->decode;
1960 int ret;
1961
35d3d4a1
AK		 1962 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
1963 return emulate_gp(ctxt, 0);
38ba30ba
GN		 1964 c->eip = tss->eip;
1965 ctxt->eflags = tss->eflags | 2;
1966 c->regs[VCPU_REGS_RAX] = tss->eax;
1967 c->regs[VCPU_REGS_RCX] = tss->ecx;
1968 c->regs[VCPU_REGS_RDX] = tss->edx;
1969 c->regs[VCPU_REGS_RBX] = tss->ebx;
1970 c->regs[VCPU_REGS_RSP] = tss->esp;
1971 c->regs[VCPU_REGS_RBP] = tss->ebp;
1972 c->regs[VCPU_REGS_RSI] = tss->esi;
1973 c->regs[VCPU_REGS_RDI] = tss->edi;
1974
1975 /*
1976 * SDM says that segment selectors are loaded before segment
1977 * descriptors
1978 */
1979 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1980 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1981 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1982 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1983 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1984 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1985 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1986
1987 /*
1988 * Now load segment descriptors. If fault happenes at this stage
1989 * it is handled in a context of new task
1990 */
1991 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1992 if (ret != X86EMUL_CONTINUE)
1993 return ret;
1994 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1995 if (ret != X86EMUL_CONTINUE)
1996 return ret;
1997 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1998 if (ret != X86EMUL_CONTINUE)
1999 return ret;
2000 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2001 if (ret != X86EMUL_CONTINUE)
2002 return ret;
2003 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2004 if (ret != X86EMUL_CONTINUE)
2005 return ret;
2006 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2007 if (ret != X86EMUL_CONTINUE)
2008 return ret;
2009 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2010 if (ret != X86EMUL_CONTINUE)
2011 return ret;
2012
2013 return X86EMUL_CONTINUE;
2014}
2015
2016static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2017 struct x86_emulate_ops *ops,
2018 u16 tss_selector, u16 old_tss_sel,
2019 ulong old_tss_base, struct desc_struct *new_desc)
2020{
2021 struct tss_segment_32 tss_seg;
2022 int ret;
bcc55cba 2023 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2024
2025 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2026 &ctxt->exception);
db297e3d 2027 if (ret != X86EMUL_CONTINUE)
38ba30ba 2028 /* FIXME: need to provide precise fault address */
38ba30ba 2029 return ret;
38ba30ba
GN		 2030
2031 save_state_to_tss32(ctxt, ops, &tss_seg);
2032
2033 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2034 &ctxt->exception);
db297e3d 2035 if (ret != X86EMUL_CONTINUE)
38ba30ba 2036 /* FIXME: need to provide precise fault address */
38ba30ba 2037 return ret;
38ba30ba
GN		 2038
2039 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2040 &ctxt->exception);
db297e3d 2041 if (ret != X86EMUL_CONTINUE)
38ba30ba 2042 /* FIXME: need to provide precise fault address */
38ba30ba 2043 return ret;
38ba30ba
GN		 2044
2045 if (old_tss_sel != 0xffff) {
2046 tss_seg.prev_task_link = old_tss_sel;
2047
2048 ret = ops->write_std(new_tss_base,
2049 &tss_seg.prev_task_link,
2050 sizeof tss_seg.prev_task_link,
bcc55cba 2051 ctxt->vcpu, &ctxt->exception);
db297e3d 2052 if (ret != X86EMUL_CONTINUE)
38ba30ba 2053 /* FIXME: need to provide precise fault address */
38ba30ba 2054 return ret;
38ba30ba
GN		 2055 }
2056
2057 return load_state_from_tss32(ctxt, ops, &tss_seg);
2058}
2059
2060static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2061 struct x86_emulate_ops *ops,
2062 u16 tss_selector, int reason,
2063 bool has_error_code, u32 error_code)
38ba30ba
GN		 2064{
2065 struct desc_struct curr_tss_desc, next_tss_desc;
2066 int ret;
2067 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2068 ulong old_tss_base =
5951c442 2069 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2070 u32 desc_limit;
38ba30ba
GN		 2071
2072 /* FIXME: old_tss_base == ~0 ? */
2073
2074 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2075 if (ret != X86EMUL_CONTINUE)
2076 return ret;
2077 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2078 if (ret != X86EMUL_CONTINUE)
2079 return ret;
2080
2081 /* FIXME: check that next_tss_desc is tss */
2082
2083 if (reason != TASK_SWITCH_IRET) {
2084 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2085 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2086 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2087 }
2088
ceffb459
GN		 2089 desc_limit = desc_limit_scaled(&next_tss_desc);
2090 if (!next_tss_desc.p ||
2091 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2092 desc_limit < 0x2b)) {
54b8486f 2093 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2094 return X86EMUL_PROPAGATE_FAULT;
2095 }
2096
2097 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2098 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2099 write_segment_descriptor(ctxt, ops, old_tss_sel,
2100 &curr_tss_desc);
2101 }
2102
2103 if (reason == TASK_SWITCH_IRET)
2104 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2105
2106 /* set back link to prev task only if NT bit is set in eflags
2107 note that old_tss_sel is not used afetr this point */
2108 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2109 old_tss_sel = 0xffff;
2110
2111 if (next_tss_desc.type & 8)
2112 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2113 old_tss_base, &next_tss_desc);
2114 else
2115 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2116 old_tss_base, &next_tss_desc);
0760d448
JK		 2117 if (ret != X86EMUL_CONTINUE)
2118 return ret;
38ba30ba
GN		 2119
2120 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2121 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2122
2123 if (reason != TASK_SWITCH_IRET) {
2124 next_tss_desc.type |= (1 << 1); /* set busy flag */
2125 write_segment_descriptor(ctxt, ops, tss_selector,
2126 &next_tss_desc);
2127 }
2128
2129 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2130 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2131 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2132
e269fb21
JK		 2133 if (has_error_code) {
2134 struct decode_cache *c = &ctxt->decode;
2135
2136 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2137 c->lock_prefix = 0;
2138 c->src.val = (unsigned long) error_code;
79168fd1 2139 emulate_push(ctxt, ops);
e269fb21
JK		 2140 }
2141
38ba30ba
GN		 2142 return ret;
2143}
2144
2145int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2146 u16 tss_selector, int reason,
2147 bool has_error_code, u32 error_code)
38ba30ba 2148{
9aabc88f 2149 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2150 struct decode_cache *c = &ctxt->decode;
2151 int rc;
2152
38ba30ba 2153 c->eip = ctxt->eip;
e269fb21 2154 c->dst.type = OP_NONE;
38ba30ba 2155
e269fb21
JK		 2156 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2157 has_error_code, error_code);
38ba30ba
GN		 2158
2159 if (rc == X86EMUL_CONTINUE) {
e269fb21 2160 rc = writeback(ctxt, ops);
95c55886
GN		 2161 if (rc == X86EMUL_CONTINUE)
2162 ctxt->eip = c->eip;
38ba30ba
GN		 2163 }
2164
19d04437 2165 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2166}
2167
90de84f5 2168static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2169 int reg, struct operand *op)
a682e354
GN		 2170{
2171 struct decode_cache *c = &ctxt->decode;
2172 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2173
d9271123 2174 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2175 op->addr.mem.ea = register_address(c, c->regs[reg]);
2176 op->addr.mem.seg = seg;
a682e354
GN		 2177}
2178
63540382
AK		 2179static int em_push(struct x86_emulate_ctxt *ctxt)
2180{
2181 emulate_push(ctxt, ctxt->ops);
2182 return X86EMUL_CONTINUE;
2183}
2184
7af04fc0
AK		 2185static int em_das(struct x86_emulate_ctxt *ctxt)
2186{
2187 struct decode_cache *c = &ctxt->decode;
2188 u8 al, old_al;
2189 bool af, cf, old_cf;
2190
2191 cf = ctxt->eflags & X86_EFLAGS_CF;
2192 al = c->dst.val;
2193
2194 old_al = al;
2195 old_cf = cf;
2196 cf = false;
2197 af = ctxt->eflags & X86_EFLAGS_AF;
2198 if ((al & 0x0f) > 9 || af) {
2199 al -= 6;
2200 cf = old_cf | (al >= 250);
2201 af = true;
2202 } else {
2203 af = false;
2204 }
2205 if (old_al > 0x99 || old_cf) {
2206 al -= 0x60;
2207 cf = true;
2208 }
2209
2210 c->dst.val = al;
2211 /* Set PF, ZF, SF */
2212 c->src.type = OP_IMM;
2213 c->src.val = 0;
2214 c->src.bytes = 1;
2215 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2216 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2217 if (cf)
2218 ctxt->eflags |= X86_EFLAGS_CF;
2219 if (af)
2220 ctxt->eflags |= X86_EFLAGS_AF;
2221 return X86EMUL_CONTINUE;
2222}
2223
0ef753b8
AK		 2224static int em_call_far(struct x86_emulate_ctxt *ctxt)
2225{
2226 struct decode_cache *c = &ctxt->decode;
2227 u16 sel, old_cs;
2228 ulong old_eip;
2229 int rc;
2230
2231 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2232 old_eip = c->eip;
2233
2234 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2235 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2236 return X86EMUL_CONTINUE;
2237
2238 c->eip = 0;
2239 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2240
2241 c->src.val = old_cs;
2242 emulate_push(ctxt, ctxt->ops);
2243 rc = writeback(ctxt, ctxt->ops);
2244 if (rc != X86EMUL_CONTINUE)
2245 return rc;
2246
2247 c->src.val = old_eip;
2248 emulate_push(ctxt, ctxt->ops);
2249 rc = writeback(ctxt, ctxt->ops);
2250 if (rc != X86EMUL_CONTINUE)
2251 return rc;
2252
2253 c->dst.type = OP_NONE;
2254
2255 return X86EMUL_CONTINUE;
2256}
2257
40ece7c7
AK		 2258static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2259{
2260 struct decode_cache *c = &ctxt->decode;
2261 int rc;
2262
2263 c->dst.type = OP_REG;
2264 c->dst.addr.reg = &c->eip;
2265 c->dst.bytes = c->op_bytes;
2266 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2267 if (rc != X86EMUL_CONTINUE)
2268 return rc;
2269 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2270 return X86EMUL_CONTINUE;
2271}
2272
5c82aa29 2273static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2274{
2275 struct decode_cache *c = &ctxt->decode;
2276
f3a1b9f4
AK		 2277 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2278 return X86EMUL_CONTINUE;
2279}
2280
5c82aa29
AK		 2281static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2282{
2283 struct decode_cache *c = &ctxt->decode;
2284
2285 c->dst.val = c->src2.val;
2286 return em_imul(ctxt);
2287}
2288
61429142
AK		 2289static int em_cwd(struct x86_emulate_ctxt *ctxt)
2290{
2291 struct decode_cache *c = &ctxt->decode;
2292
2293 c->dst.type = OP_REG;
2294 c->dst.bytes = c->src.bytes;
2295 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2296 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2297
2298 return X86EMUL_CONTINUE;
2299}
2300
48bb5d3c
AK		 2301static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2302{
2303 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2304 struct decode_cache *c = &ctxt->decode;
2305 u64 tsc = 0;
2306
35d3d4a1
AK		 2307 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD))
2308 return emulate_gp(ctxt, 0);
48bb5d3c
AK		 2309 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2310 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2311 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2312 return X86EMUL_CONTINUE;
2313}
2314
b9eac5f4
AK		 2315static int em_mov(struct x86_emulate_ctxt *ctxt)
2316{
2317 struct decode_cache *c = &ctxt->decode;
2318 c->dst.val = c->src.val;
2319 return X86EMUL_CONTINUE;
2320}
2321
73fba5f4
AK		 2322#define D(_y) { .flags = (_y) }
2323#define N D(0)
2324#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2325#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2326#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2327
8d8f4e9f
AK		 2328#define D2bv(_f) D((_f) | ByteOp), D(_f)
2329#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2330
6230f7fc
AK		 2331#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2332 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2333 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2334
2335
73fba5f4
AK		 2336static struct opcode group1[] = {
2337 X7(D(Lock)), N
2338};
2339
2340static struct opcode group1A[] = {
2341 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2342};
2343
2344static struct opcode group3[] = {
2345 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2346 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2347 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2348};
2349
2350static struct opcode group4[] = {
2351 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2352 N, N, N, N, N, N,
2353};
2354
2355static struct opcode group5[] = {
2356 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2357 D(SrcMem | ModRM | Stack),
2358 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2359 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2360 D(SrcMem | ModRM | Stack), N,
2361};
2362
2363static struct group_dual group7 = { {
2364 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2365 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2366 D(SrcMem16 | ModRM | Mov | Priv),
2367 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4 2368}, {
d867162c
AK		 2369 D(SrcNone | ModRM | Priv | VendorSpecific), N,
2370 N, D(SrcNone | ModRM | Priv | VendorSpecific),
73fba5f4
AK		 2371 D(SrcNone | ModRM | DstMem | Mov), N,
2372 D(SrcMem16 | ModRM | Mov | Priv), N,
2373} };
2374
2375static struct opcode group8[] = {
2376 N, N, N, N,
2377 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2378 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2379};
2380
2381static struct group_dual group9 = { {
2382 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2383}, {
2384 N, N, N, N, N, N, N, N,
2385} };
2386
a4d4a7c1
AK		 2387static struct opcode group11[] = {
2388 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2389};
2390
73fba5f4
AK		 2391static struct opcode opcode_table[256] = {
2392 /* 0x00 - 0x07 */
6230f7fc 2393 D6ALU(Lock),
73fba5f4
AK		 2394 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2395 /* 0x08 - 0x0F */
6230f7fc 2396 D6ALU(Lock),
73fba5f4
AK		 2397 D(ImplicitOps | Stack | No64), N,
2398 /* 0x10 - 0x17 */
6230f7fc 2399 D6ALU(Lock),
73fba5f4
AK		 2400 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2401 /* 0x18 - 0x1F */
6230f7fc 2402 D6ALU(Lock),
73fba5f4
AK		 2403 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2404 /* 0x20 - 0x27 */
6230f7fc 2405 D6ALU(Lock), N, N,
73fba5f4 2406 /* 0x28 - 0x2F */
6230f7fc 2407 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2408 /* 0x30 - 0x37 */
6230f7fc 2409 D6ALU(Lock), N, N,
73fba5f4 2410 /* 0x38 - 0x3F */
6230f7fc 2411 D6ALU(0), N, N,
73fba5f4
AK		 2412 /* 0x40 - 0x4F */
2413 X16(D(DstReg)),
2414 /* 0x50 - 0x57 */
63540382 2415 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2416 /* 0x58 - 0x5F */
2417 X8(D(DstReg | Stack)),
2418 /* 0x60 - 0x67 */
2419 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2420 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2421 N, N, N, N,
2422 /* 0x68 - 0x6F */
d46164db
AK		 2423 I(SrcImm | Mov | Stack, em_push),
2424 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2425 I(SrcImmByte | Mov | Stack, em_push),
2426 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2427 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2428 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2429 /* 0x70 - 0x7F */
2430 X16(D(SrcImmByte)),
2431 /* 0x80 - 0x87 */
2432 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2433 G(DstMem | SrcImm | ModRM | Group, group1),
2434 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2435 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2436 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2437 /* 0x88 - 0x8F */
b9eac5f4
AK		 2438 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2439 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2440 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2441 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2442 /* 0x90 - 0x97 */
3d9e77df 2443 X8(D(SrcAcc | DstReg)),
73fba5f4 2444 /* 0x98 - 0x9F */
61429142 2445 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2446 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2447 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2448 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2449 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2450 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2451 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2452 D2bv(SrcSI | DstDI | String),
73fba5f4 2453 /* 0xA8 - 0xAF */
50748613 2454 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2455 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2456 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2457 D2bv(SrcAcc | DstDI | String),
73fba5f4 2458 /* 0xB0 - 0xB7 */
b9eac5f4 2459 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2460 /* 0xB8 - 0xBF */
b9eac5f4 2461 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2462 /* 0xC0 - 0xC7 */
d2c6c7ad 2463 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2464 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2465 D(ImplicitOps | Stack),
09b5f4d3 2466 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2467 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2468 /* 0xC8 - 0xCF */
2469 N, N, N, D(ImplicitOps | Stack),
2470 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2471 /* 0xD0 - 0xD7 */
d2c6c7ad 2472 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2473 N, N, N, N,
2474 /* 0xD8 - 0xDF */
2475 N, N, N, N, N, N, N, N,
2476 /* 0xE0 - 0xE7 */
e4abac67 2477 X4(D(SrcImmByte)),
d269e396 2478 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2479 /* 0xE8 - 0xEF */
2480 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2481 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2482 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2483 /* 0xF0 - 0xF7 */
2484 N, N, N, N,
2485 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2486 /* 0xF8 - 0xFF */
8744aa9a 2487 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2488 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2489};
2490
2491static struct opcode twobyte_table[256] = {
2492 /* 0x00 - 0x0F */
2493 N, GD(0, &group7), N, N,
d867162c 2494 N, D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv), N,
73fba5f4
AK		 2495 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2496 N, D(ImplicitOps | ModRM), N, N,
2497 /* 0x10 - 0x1F */
2498 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2499 /* 0x20 - 0x2F */
b27f3856
AK		 2500 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2501 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2502 N, N, N, N,
2503 N, N, N, N, N, N, N, N,
2504 /* 0x30 - 0x3F */
48bb5d3c
AK		 2505 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2506 D(ImplicitOps | Priv), N,
d867162c
AK		 2507 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2508 N, N,
73fba5f4
AK		 2509 N, N, N, N, N, N, N, N,
2510 /* 0x40 - 0x4F */
2511 X16(D(DstReg | SrcMem | ModRM | Mov)),
2512 /* 0x50 - 0x5F */
2513 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2514 /* 0x60 - 0x6F */
2515 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2516 /* 0x70 - 0x7F */
2517 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2518 /* 0x80 - 0x8F */
2519 X16(D(SrcImm)),
2520 /* 0x90 - 0x9F */
ee45b58e 2521 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2522 /* 0xA0 - 0xA7 */
2523 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2524 N, D(DstMem | SrcReg | ModRM | BitOp),
2525 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2526 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2527 /* 0xA8 - 0xAF */
2528 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2529 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2530 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2531 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2532 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2533 /* 0xB0 - 0xB7 */
739ae406 2534 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2535 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2536 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2537 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2538 /* 0xB8 - 0xBF */
2539 N, N,
ba7ff2b7 2540 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2541 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2542 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2543 /* 0xC0 - 0xCF */
739ae406 2544 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2545 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2546 N, N, N, GD(0, &group9),
2547 N, N, N, N, N, N, N, N,
2548 /* 0xD0 - 0xDF */
2549 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2550 /* 0xE0 - 0xEF */
2551 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2552 /* 0xF0 - 0xFF */
2553 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2554};
2555
2556#undef D
2557#undef N
2558#undef G
2559#undef GD
2560#undef I
2561
8d8f4e9f
AK		 2562#undef D2bv
2563#undef I2bv
6230f7fc 2564#undef D6ALU
8d8f4e9f 2565
39f21ee5
AK		 2566static unsigned imm_size(struct decode_cache *c)
2567{
2568 unsigned size;
2569
2570 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2571 if (size == 8)
2572 size = 4;
2573 return size;
2574}
2575
2576static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2577 unsigned size, bool sign_extension)
2578{
2579 struct decode_cache *c = &ctxt->decode;
2580 struct x86_emulate_ops *ops = ctxt->ops;
2581 int rc = X86EMUL_CONTINUE;
2582
2583 op->type = OP_IMM;
2584 op->bytes = size;
90de84f5 2585 op->addr.mem.ea = c->eip;
39f21ee5
AK		 2586 /* NB. Immediates are sign-extended as necessary. */
2587 switch (op->bytes) {
2588 case 1:
2589 op->val = insn_fetch(s8, 1, c->eip);
2590 break;
2591 case 2:
2592 op->val = insn_fetch(s16, 2, c->eip);
2593 break;
2594 case 4:
2595 op->val = insn_fetch(s32, 4, c->eip);
2596 break;
2597 }
2598 if (!sign_extension) {
2599 switch (op->bytes) {
2600 case 1:
2601 op->val &= 0xff;
2602 break;
2603 case 2:
2604 op->val &= 0xffff;
2605 break;
2606 case 4:
2607 op->val &= 0xffffffff;
2608 break;
2609 }
2610 }
2611done:
2612 return rc;
2613}
2614
dde7e6d1 2615int
dc25e89e 2616x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 2617{
2618 struct x86_emulate_ops *ops = ctxt->ops;
2619 struct decode_cache *c = &ctxt->decode;
2620 int rc = X86EMUL_CONTINUE;
2621 int mode = ctxt->mode;
2622 int def_op_bytes, def_ad_bytes, dual, goffset;
2623 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2624 struct operand memop = { .type = OP_NONE };
dde7e6d1 2625
dde7e6d1 2626 c->eip = ctxt->eip;
dc25e89e
AP		 2627 c->fetch.start = c->eip;
2628 c->fetch.end = c->fetch.start + insn_len;
2629 if (insn_len > 0)
2630 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 2631 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2632
2633 switch (mode) {
2634 case X86EMUL_MODE_REAL:
2635 case X86EMUL_MODE_VM86:
2636 case X86EMUL_MODE_PROT16:
2637 def_op_bytes = def_ad_bytes = 2;
2638 break;
2639 case X86EMUL_MODE_PROT32:
2640 def_op_bytes = def_ad_bytes = 4;
2641 break;
2642#ifdef CONFIG_X86_64
2643 case X86EMUL_MODE_PROT64:
2644 def_op_bytes = 4;
2645 def_ad_bytes = 8;
2646 break;
2647#endif
2648 default:
2649 return -1;
2650 }
2651
2652 c->op_bytes = def_op_bytes;
2653 c->ad_bytes = def_ad_bytes;
2654
2655 /* Legacy prefixes. */
2656 for (;;) {
2657 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2658 case 0x66: /* operand-size override */
2659 /* switch between 2/4 bytes */
2660 c->op_bytes = def_op_bytes ^ 6;
2661 break;
2662 case 0x67: /* address-size override */
2663 if (mode == X86EMUL_MODE_PROT64)
2664 /* switch between 4/8 bytes */
2665 c->ad_bytes = def_ad_bytes ^ 12;
2666 else
2667 /* switch between 2/4 bytes */
2668 c->ad_bytes = def_ad_bytes ^ 6;
2669 break;
2670 case 0x26: /* ES override */
2671 case 0x2e: /* CS override */
2672 case 0x36: /* SS override */
2673 case 0x3e: /* DS override */
2674 set_seg_override(c, (c->b >> 3) & 3);
2675 break;
2676 case 0x64: /* FS override */
2677 case 0x65: /* GS override */
2678 set_seg_override(c, c->b & 7);
2679 break;
2680 case 0x40 ... 0x4f: /* REX */
2681 if (mode != X86EMUL_MODE_PROT64)
2682 goto done_prefixes;
2683 c->rex_prefix = c->b;
2684 continue;
2685 case 0xf0: /* LOCK */
2686 c->lock_prefix = 1;
2687 break;
2688 case 0xf2: /* REPNE/REPNZ */
2689 c->rep_prefix = REPNE_PREFIX;
2690 break;
2691 case 0xf3: /* REP/REPE/REPZ */
2692 c->rep_prefix = REPE_PREFIX;
2693 break;
2694 default:
2695 goto done_prefixes;
2696 }
2697
2698 /* Any legacy prefix after a REX prefix nullifies its effect. */
2699
2700 c->rex_prefix = 0;
2701 }
2702
2703done_prefixes:
2704
2705 /* REX prefix. */
1e87e3ef
AK		 2706 if (c->rex_prefix & 8)
2707 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2708
2709 /* Opcode byte(s). */
2710 opcode = opcode_table[c->b];
d3ad6243
WY		 2711 /* Two-byte opcode? */
2712 if (c->b == 0x0f) {
2713 c->twobyte = 1;
2714 c->b = insn_fetch(u8, 1, c->eip);
2715 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2716 }
2717 c->d = opcode.flags;
2718
2719 if (c->d & Group) {
2720 dual = c->d & GroupDual;
2721 c->modrm = insn_fetch(u8, 1, c->eip);
2722 --c->eip;
2723
2724 if (c->d & GroupDual) {
2725 g_mod012 = opcode.u.gdual->mod012;
2726 g_mod3 = opcode.u.gdual->mod3;
2727 } else
2728 g_mod012 = g_mod3 = opcode.u.group;
2729
2730 c->d &= ~(Group | GroupDual);
2731
2732 goffset = (c->modrm >> 3) & 7;
2733
2734 if ((c->modrm >> 6) == 3)
2735 opcode = g_mod3[goffset];
2736 else
2737 opcode = g_mod012[goffset];
2738 c->d |= opcode.flags;
2739 }
2740
2741 c->execute = opcode.u.execute;
2742
2743 /* Unrecognised? */
d53db5ef 2744 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 2745 return -1;
dde7e6d1 2746
d867162c
AK		 2747 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
2748 return -1;
2749
dde7e6d1
AK		 2750 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2751 c->op_bytes = 8;
2752
7f9b4b75
AK		 2753 if (c->d & Op3264) {
2754 if (mode == X86EMUL_MODE_PROT64)
2755 c->op_bytes = 8;
2756 else
2757 c->op_bytes = 4;
2758 }
2759
dde7e6d1 2760 /* ModRM and SIB bytes. */
09ee57cd 2761 if (c->d & ModRM) {
2dbd0dd7 2762 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2763 if (!c->has_seg_override)
2764 set_seg_override(c, c->modrm_seg);
2765 } else if (c->d & MemAbs)
2dbd0dd7 2766 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2767 if (rc != X86EMUL_CONTINUE)
2768 goto done;
2769
2770 if (!c->has_seg_override)
2771 set_seg_override(c, VCPU_SREG_DS);
2772
90de84f5 2773 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 2774
2dbd0dd7 2775 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 2776 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 2777
2dbd0dd7 2778 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 2779 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 2780
2781 /*
2782 * Decode and fetch the source operand: register, memory
2783 * or immediate.
2784 */
2785 switch (c->d & SrcMask) {
2786 case SrcNone:
2787 break;
2788 case SrcReg:
2789 decode_register_operand(&c->src, c, 0);
2790 break;
2791 case SrcMem16:
2dbd0dd7 2792 memop.bytes = 2;
dde7e6d1
AK		 2793 goto srcmem_common;
2794 case SrcMem32:
2dbd0dd7 2795 memop.bytes = 4;
dde7e6d1
AK		 2796 goto srcmem_common;
2797 case SrcMem:
2dbd0dd7 2798 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2799 c->op_bytes;
dde7e6d1 2800 srcmem_common:
2dbd0dd7 2801 c->src = memop;
dde7e6d1 2802 break;
b250e605 2803 case SrcImmU16:
39f21ee5
AK		 2804 rc = decode_imm(ctxt, &c->src, 2, false);
2805 break;
dde7e6d1 2806 case SrcImm:
39f21ee5
AK		 2807 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2808 break;
dde7e6d1 2809 case SrcImmU:
39f21ee5 2810 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2811 break;
2812 case SrcImmByte:
39f21ee5
AK		 2813 rc = decode_imm(ctxt, &c->src, 1, true);
2814 break;
dde7e6d1 2815 case SrcImmUByte:
39f21ee5 2816 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2817 break;
2818 case SrcAcc:
2819 c->src.type = OP_REG;
2820 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2821 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2822 fetch_register_operand(&c->src);
dde7e6d1
AK		 2823 break;
2824 case SrcOne:
2825 c->src.bytes = 1;
2826 c->src.val = 1;
2827 break;
2828 case SrcSI:
2829 c->src.type = OP_MEM;
2830 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2831 c->src.addr.mem.ea =
2832 register_address(c, c->regs[VCPU_REGS_RSI]);
2833 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 2834 c->src.val = 0;
2835 break;
2836 case SrcImmFAddr:
2837 c->src.type = OP_IMM;
90de84f5 2838 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 2839 c->src.bytes = c->op_bytes + 2;
2840 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2841 break;
2842 case SrcMemFAddr:
2dbd0dd7
AK		 2843 memop.bytes = c->op_bytes + 2;
2844 goto srcmem_common;
dde7e6d1
AK		 2845 break;
2846 }
2847
39f21ee5
AK		 2848 if (rc != X86EMUL_CONTINUE)
2849 goto done;
2850
dde7e6d1
AK		 2851 /*
2852 * Decode and fetch the second source operand: register, memory
2853 * or immediate.
2854 */
2855 switch (c->d & Src2Mask) {
2856 case Src2None:
2857 break;
2858 case Src2CL:
2859 c->src2.bytes = 1;
2860 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2861 break;
2862 case Src2ImmByte:
39f21ee5 2863 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2864 break;
2865 case Src2One:
2866 c->src2.bytes = 1;
2867 c->src2.val = 1;
2868 break;
7db41eb7
AK		 2869 case Src2Imm:
2870 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2871 break;
dde7e6d1
AK		 2872 }
2873
39f21ee5
AK		 2874 if (rc != X86EMUL_CONTINUE)
2875 goto done;
2876
dde7e6d1
AK		 2877 /* Decode and fetch the destination operand: register or memory. */
2878 switch (c->d & DstMask) {
dde7e6d1
AK		 2879 case DstReg:
2880 decode_register_operand(&c->dst, c,
2881 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2882 break;
943858e2
WY		 2883 case DstImmUByte:
2884 c->dst.type = OP_IMM;
90de84f5 2885 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 2886 c->dst.bytes = 1;
2887 c->dst.val = insn_fetch(u8, 1, c->eip);
2888 break;
dde7e6d1
AK		 2889 case DstMem:
2890 case DstMem64:
2dbd0dd7 2891 c->dst = memop;
dde7e6d1
AK		 2892 if ((c->d & DstMask) == DstMem64)
2893 c->dst.bytes = 8;
2894 else
2895 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2896 if (c->d & BitOp)
2897 fetch_bit_operand(c);
2dbd0dd7 2898 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2899 break;
2900 case DstAcc:
2901 c->dst.type = OP_REG;
2902 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2903 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2904 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2905 c->dst.orig_val = c->dst.val;
2906 break;
2907 case DstDI:
2908 c->dst.type = OP_MEM;
2909 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2910 c->dst.addr.mem.ea =
2911 register_address(c, c->regs[VCPU_REGS_RDI]);
2912 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 2913 c->dst.val = 0;
2914 break;
36089fed
WY		 2915 case ImplicitOps:
2916 /* Special instructions do their own operand decoding. */
2917 default:
2918 c->dst.type = OP_NONE; /* Disable writeback. */
2919 return 0;
dde7e6d1
AK		 2920 }
2921
2922done:
2923 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2924}
2925
3e2f65d5
GN		 2926static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2927{
2928 struct decode_cache *c = &ctxt->decode;
2929
2930 /* The second termination condition only applies for REPE
2931 * and REPNE. Test if the repeat string operation prefix is
2932 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2933 * corresponding termination condition according to:
2934 * - if REPE/REPZ and ZF = 0 then done
2935 * - if REPNE/REPNZ and ZF = 1 then done
2936 */
2937 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2938 (c->b == 0xae) || (c->b == 0xaf))
2939 && (((c->rep_prefix == REPE_PREFIX) &&
2940 ((ctxt->eflags & EFLG_ZF) == 0))
2941 || ((c->rep_prefix == REPNE_PREFIX) &&
2942 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2943 return true;
2944
2945 return false;
2946}
2947
8b4caf66 2948int
9aabc88f 2949x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2950{
9aabc88f 2951 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2952 u64 msr_data;
8b4caf66 2953 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2954 int rc = X86EMUL_CONTINUE;
5cd21917 2955 int saved_dst_type = c->dst.type;
6e154e56 2956 int irq; /* Used for int 3, int, and into */
8b4caf66 2957
9de41573 2958 ctxt->decode.mem_read.pos = 0;
310b5d30 2959
1161624f 2960 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 2961 rc = emulate_ud(ctxt);
1161624f
GN		 2962 goto done;
2963 }
2964
d380a5e4 2965 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2966 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 2967 rc = emulate_ud(ctxt);
d380a5e4
GN		 2968 goto done;
2969 }
2970
081bca0e 2971 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 2972 rc = emulate_ud(ctxt);
081bca0e
AK		 2973 goto done;
2974 }
2975
e92805ac 2976 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2977 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 2978 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 2979 goto done;
2980 }
2981
b9fa9d6b
AK		 2982 if (c->rep_prefix && (c->d & String)) {
2983 /* All REP prefixes have the same first termination condition */
c73e197b 2984 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 2985 ctxt->eip = c->eip;
b9fa9d6b
AK		 2986 goto done;
2987 }
b9fa9d6b
AK		 2988 }
2989
c483c02a 2990 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
90de84f5 2991 rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem),
414e6277 2992 c->src.valptr, c->src.bytes);
b60d513c 2993 if (rc != X86EMUL_CONTINUE)
8b4caf66 2994 goto done;
16518d5a 2995 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2996 }
2997
e35b7b9c 2998 if (c->src2.type == OP_MEM) {
90de84f5 2999 rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem),
9de41573 3000 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3001 if (rc != X86EMUL_CONTINUE)
3002 goto done;
3003 }
3004
8b4caf66
LV		 3005 if ((c->d & DstMask) == ImplicitOps)
3006 goto special_insn;
3007
3008
69f55cb1
GN		 3009 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3010 /* optimisation - avoid slow emulated read if Mov */
90de84f5 3011 rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem),
9de41573 3012 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3013 if (rc != X86EMUL_CONTINUE)
3014 goto done;
038e51de 3015 }
e4e03ded 3016 c->dst.orig_val = c->dst.val;
038e51de 3017
018a98db
AK		 3018special_insn:
3019
ef65c889
AK		 3020 if (c->execute) {
3021 rc = c->execute(ctxt);
3022 if (rc != X86EMUL_CONTINUE)
3023 goto done;
3024 goto writeback;
3025 }
3026
e4e03ded 3027 if (c->twobyte)
6aa8b732
AK		 3028 goto twobyte_insn;
3029
e4e03ded 3030 switch (c->b) {
6aa8b732
AK		 3031 case 0x00 ... 0x05:
3032 add: /* add */
05f086f8 3033 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3034 break;
0934ac9d 3035 case 0x06: /* push es */
79168fd1 3036 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3037 break;
3038 case 0x07: /* pop es */
0934ac9d 3039 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3040 break;
6aa8b732
AK		 3041 case 0x08 ... 0x0d:
3042 or: /* or */
05f086f8 3043 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3044 break;
0934ac9d 3045 case 0x0e: /* push cs */
79168fd1 3046 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3047 break;
6aa8b732
AK		 3048 case 0x10 ... 0x15:
3049 adc: /* adc */
05f086f8 3050 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3051 break;
0934ac9d 3052 case 0x16: /* push ss */
79168fd1 3053 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3054 break;
3055 case 0x17: /* pop ss */
0934ac9d 3056 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3057 break;
6aa8b732
AK		 3058 case 0x18 ... 0x1d:
3059 sbb: /* sbb */
05f086f8 3060 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3061 break;
0934ac9d 3062 case 0x1e: /* push ds */
79168fd1 3063 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3064 break;
3065 case 0x1f: /* pop ds */
0934ac9d 3066 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3067 break;
aa3a816b 3068 case 0x20 ... 0x25:
6aa8b732 3069 and: /* and */
05f086f8 3070 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3071 break;
3072 case 0x28 ... 0x2d:
3073 sub: /* sub */
05f086f8 3074 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3075 break;
3076 case 0x30 ... 0x35:
3077 xor: /* xor */
05f086f8 3078 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3079 break;
3080 case 0x38 ... 0x3d:
3081 cmp: /* cmp */
05f086f8 3082 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3083 break;
33615aa9
AK		 3084 case 0x40 ... 0x47: /* inc r16/r32 */
3085 emulate_1op("inc", c->dst, ctxt->eflags);
3086 break;
3087 case 0x48 ... 0x4f: /* dec r16/r32 */
3088 emulate_1op("dec", c->dst, ctxt->eflags);
3089 break;
33615aa9
AK		 3090 case 0x58 ... 0x5f: /* pop reg */
3091 pop_instruction:
350f69dc 3092 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3093 break;
abcf14b5 3094 case 0x60: /* pusha */
c37eda13 3095 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3096 break;
3097 case 0x61: /* popa */
3098 rc = emulate_popa(ctxt, ops);
abcf14b5 3099 break;
6aa8b732 3100 case 0x63: /* movsxd */
8b4caf66 3101 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3102 goto cannot_emulate;
e4e03ded 3103 c->dst.val = (s32) c->src.val;
6aa8b732 3104 break;
018a98db
AK		 3105 case 0x6c: /* insb */
3106 case 0x6d: /* insw/insd */
a13a63fa
WY		 3107 c->src.val = c->regs[VCPU_REGS_RDX];
3108 goto do_io_in;
018a98db
AK		 3109 case 0x6e: /* outsb */
3110 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3111 c->dst.val = c->regs[VCPU_REGS_RDX];
3112 goto do_io_out;
7972995b 3113 break;
b2833e3c 3114 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3115 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3116 jmp_rel(c, c->src.val);
018a98db 3117 break;
6aa8b732 3118 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3119 switch (c->modrm_reg) {
6aa8b732
AK		 3120 case 0:
3121 goto add;
3122 case 1:
3123 goto or;
3124 case 2:
3125 goto adc;
3126 case 3:
3127 goto sbb;
3128 case 4:
3129 goto and;
3130 case 5:
3131 goto sub;
3132 case 6:
3133 goto xor;
3134 case 7:
3135 goto cmp;
3136 }
3137 break;
3138 case 0x84 ... 0x85:
dfb507c4 3139 test:
05f086f8 3140 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3141 break;
3142 case 0x86 ... 0x87: /* xchg */
b13354f8 3143 xchg:
6aa8b732 3144 /* Write back the register source. */
31be40b3
WY		 3145 c->src.val = c->dst.val;
3146 write_register_operand(&c->src);
6aa8b732
AK		 3147 /*
3148 * Write back the memory destination with implicit LOCK
3149 * prefix.
3150 */
31be40b3 3151 c->dst.val = c->src.orig_val;
e4e03ded 3152 c->lock_prefix = 1;
6aa8b732 3153 break;
79168fd1
GN		 3154 case 0x8c: /* mov r/m, sreg */
3155 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3156 rc = emulate_ud(ctxt);
5e3ae6c5 3157 goto done;
38d5bc6d 3158 }
79168fd1 3159 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3160 break;
7e0b54b1 3161 case 0x8d: /* lea r16/r32, m */
90de84f5 3162 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3163 break;
4257198a
GT		 3164 case 0x8e: { /* mov seg, r/m16 */
3165 uint16_t sel;
4257198a
GT		 3166
3167 sel = c->src.val;
8b9f4414 3168
c697518a
GN		 3169 if (c->modrm_reg == VCPU_SREG_CS ||
3170 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3171 rc = emulate_ud(ctxt);
8b9f4414
GN		 3172 goto done;
3173 }
3174
310b5d30 3175 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3176 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3177
2e873022 3178 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3179
3180 c->dst.type = OP_NONE; /* Disable writeback. */
3181 break;
3182 }
6aa8b732 3183 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3184 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3185 break;
3d9e77df
AK		 3186 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3187 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3188 break;
b13354f8 3189 goto xchg;
e8b6fa70
WY		 3190 case 0x98: /* cbw/cwde/cdqe */
3191 switch (c->op_bytes) {
3192 case 2: c->dst.val = (s8)c->dst.val; break;
3193 case 4: c->dst.val = (s16)c->dst.val; break;
3194 case 8: c->dst.val = (s32)c->dst.val; break;
3195 }
3196 break;
fd2a7608 3197 case 0x9c: /* pushf */
05f086f8 3198 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3199 emulate_push(ctxt, ops);
8cdbd2c9 3200 break;
535eabcf 3201 case 0x9d: /* popf */
2b48cc75 3202 c->dst.type = OP_REG;
1a6440ae 3203 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3204 c->dst.bytes = c->op_bytes;
d4c6a154 3205 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3206 break;
6aa8b732 3207 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3208 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3209 goto cmp;
dfb507c4
MG		 3210 case 0xa8 ... 0xa9: /* test ax, imm */
3211 goto test;
6aa8b732 3212 case 0xae ... 0xaf: /* scas */
f6b33fc5 3213 goto cmp;
018a98db
AK		 3214 case 0xc0 ... 0xc1:
3215 emulate_grp2(ctxt);
3216 break;
111de5d6 3217 case 0xc3: /* ret */
cf5de4f8 3218 c->dst.type = OP_REG;
1a6440ae 3219 c->dst.addr.reg = &c->eip;
cf5de4f8 3220 c->dst.bytes = c->op_bytes;
111de5d6 3221 goto pop_instruction;
09b5f4d3
WY		 3222 case 0xc4: /* les */
3223 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3224 break;
3225 case 0xc5: /* lds */
3226 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3227 break;
a77ab5ea
AK		 3228 case 0xcb: /* ret far */
3229 rc = emulate_ret_far(ctxt, ops);
62bd430e 3230 break;
6e154e56
MG		 3231 case 0xcc: /* int3 */
3232 irq = 3;
3233 goto do_interrupt;
3234 case 0xcd: /* int n */
3235 irq = c->src.val;
3236 do_interrupt:
3237 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3238 break;
3239 case 0xce: /* into */
3240 if (ctxt->eflags & EFLG_OF) {
3241 irq = 4;
3242 goto do_interrupt;
3243 }
3244 break;
62bd430e
MG		 3245 case 0xcf: /* iret */
3246 rc = emulate_iret(ctxt, ops);
a77ab5ea 3247 break;
018a98db 3248 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3249 emulate_grp2(ctxt);
3250 break;
3251 case 0xd2 ... 0xd3: /* Grp2 */
3252 c->src.val = c->regs[VCPU_REGS_RCX];
3253 emulate_grp2(ctxt);
3254 break;
f2f31845
WY		 3255 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3256 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3257 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3258 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3259 jmp_rel(c, c->src.val);
3260 break;
e4abac67
WY		 3261 case 0xe3: /* jcxz/jecxz/jrcxz */
3262 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3263 jmp_rel(c, c->src.val);
3264 break;
a6a3034c
MG		 3265 case 0xe4: /* inb */
3266 case 0xe5: /* in */
cf8f70bf 3267 goto do_io_in;
a6a3034c
MG		 3268 case 0xe6: /* outb */
3269 case 0xe7: /* out */
cf8f70bf 3270 goto do_io_out;
1a52e051 3271 case 0xe8: /* call (near) */ {
d53c4777 3272 long int rel = c->src.val;
e4e03ded 3273 c->src.val = (unsigned long) c->eip;
7a957275 3274 jmp_rel(c, rel);
79168fd1 3275 emulate_push(ctxt, ops);
8cdbd2c9 3276 break;
1a52e051
NK		 3277 }
3278 case 0xe9: /* jmp rel */
954cd36f 3279 goto jmp;
414e6277
GN		 3280 case 0xea: { /* jmp far */
3281 unsigned short sel;
ea79849d 3282 jump_far:
414e6277
GN		 3283 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3284
3285 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3286 goto done;
954cd36f 3287
414e6277
GN		 3288 c->eip = 0;
3289 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3290 break;
414e6277 3291 }
954cd36f
GT		 3292 case 0xeb:
3293 jmp: /* jmp rel short */
7a957275 3294 jmp_rel(c, c->src.val);
a01af5ec 3295 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3296 break;
a6a3034c
MG		 3297 case 0xec: /* in al,dx */
3298 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3299 c->src.val = c->regs[VCPU_REGS_RDX];
3300 do_io_in:
3301 c->dst.bytes = min(c->dst.bytes, 4u);
3302 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
35d3d4a1 3303 rc = emulate_gp(ctxt, 0);
cf8f70bf
GN		 3304 goto done;
3305 }
7b262e90
GN		 3306 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3307 &c->dst.val))
cf8f70bf
GN		 3308 goto done; /* IO is needed */
3309 break;
ce7a0ad3
WY		 3310 case 0xee: /* out dx,al */
3311 case 0xef: /* out dx,(e/r)ax */
41167be5 3312 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3313 do_io_out:
41167be5
WY		 3314 c->src.bytes = min(c->src.bytes, 4u);
3315 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3316 c->src.bytes)) {
35d3d4a1 3317 rc = emulate_gp(ctxt, 0);
f850e2e6
GN		 3318 goto done;
3319 }
41167be5
WY		 3320 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3321 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3322 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3323 break;
111de5d6 3324 case 0xf4: /* hlt */
ad312c7c 3325 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3326 break;
111de5d6
AK		 3327 case 0xf5: /* cmc */
3328 /* complement carry flag from eflags reg */
3329 ctxt->eflags ^= EFLG_CF;
111de5d6 3330 break;
018a98db 3331 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3332 rc = emulate_grp3(ctxt, ops);
018a98db 3333 break;
111de5d6
AK		 3334 case 0xf8: /* clc */
3335 ctxt->eflags &= ~EFLG_CF;
111de5d6 3336 break;
8744aa9a
MG		 3337 case 0xf9: /* stc */
3338 ctxt->eflags |= EFLG_CF;
3339 break;
111de5d6 3340 case 0xfa: /* cli */
07cbc6c1 3341 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3342 rc = emulate_gp(ctxt, 0);
07cbc6c1 3343 goto done;
36089fed 3344 } else
f850e2e6 3345 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3346 break;
3347 case 0xfb: /* sti */
07cbc6c1 3348 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3349 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3350 goto done;
3351 } else {
95cb2295 3352 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3353 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3354 }
111de5d6 3355 break;
fb4616f4
MG		 3356 case 0xfc: /* cld */
3357 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3358 break;
3359 case 0xfd: /* std */
3360 ctxt->eflags |= EFLG_DF;
fb4616f4 3361 break;
ea79849d
GN		 3362 case 0xfe: /* Grp4 */
3363 grp45:
018a98db 3364 rc = emulate_grp45(ctxt, ops);
018a98db 3365 break;
ea79849d
GN		 3366 case 0xff: /* Grp5 */
3367 if (c->modrm_reg == 5)
3368 goto jump_far;
3369 goto grp45;
91269b8f
AK		 3370 default:
3371 goto cannot_emulate;
6aa8b732 3372 }
018a98db 3373
7d9ddaed
AK		 3374 if (rc != X86EMUL_CONTINUE)
3375 goto done;
3376
018a98db
AK		 3377writeback:
3378 rc = writeback(ctxt, ops);
1b30eaa8 3379 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3380 goto done;
3381
5cd21917
GN		 3382 /*
3383 * restore dst type in case the decoding will be reused
3384 * (happens for string instruction )
3385 */
3386 c->dst.type = saved_dst_type;
3387
a682e354 3388 if ((c->d & SrcMask) == SrcSI)
90de84f5 3389 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3390 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3391
3392 if ((c->d & DstMask) == DstDI)
90de84f5 3393 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3394 &c->dst);
d9271123 3395
5cd21917 3396 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3397 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3398 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3399
d2ddd1c4
GN		 3400 if (!string_insn_completed(ctxt)) {
3401 /*
3402 * Re-enter guest when pio read ahead buffer is empty
3403 * or, if it is not used, after each 1024 iteration.
3404 */
3405 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3406 (r->end == 0 || r->end != r->pos)) {
3407 /*
3408 * Reset read cache. Usually happens before
3409 * decode, but since instruction is restarted
3410 * we have to do it here.
3411 */
3412 ctxt->decode.mem_read.end = 0;
3413 return EMULATION_RESTART;
3414 }
3415 goto done; /* skip rip writeback */
0fa6ccbd 3416 }
5cd21917 3417 }
d2ddd1c4
GN		 3418
3419 ctxt->eip = c->eip;
018a98db
AK		 3420
3421done:
da9cb575
AK		 3422 if (rc == X86EMUL_PROPAGATE_FAULT)
3423 ctxt->have_exception = true;
d2ddd1c4 3424 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3425
3426twobyte_insn:
e4e03ded 3427 switch (c->b) {
6aa8b732 3428 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3429 switch (c->modrm_reg) {
6aa8b732
AK		 3430 u16 size;
3431 unsigned long address;
3432
aca7f966 3433 case 0: /* vmcall */
e4e03ded 3434 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3435 goto cannot_emulate;
3436
7aa81cc0 3437 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3438 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3439 goto done;
3440
33e3885d 3441 /* Let the processor re-execute the fixed hypercall */
063db061 3442 c->eip = ctxt->eip;
16286d08
AK		 3443 /* Disable writeback. */
3444 c->dst.type = OP_NONE;
aca7f966 3445 break;
6aa8b732 3446 case 2: /* lgdt */
1a6440ae 3447 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3448 &size, &address, c->op_bytes);
1b30eaa8 3449 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3450 goto done;
3451 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3452 /* Disable writeback. */
3453 c->dst.type = OP_NONE;
6aa8b732 3454 break;
aca7f966 3455 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3456 if (c->modrm_mod == 3) {
3457 switch (c->modrm_rm) {
3458 case 1:
3459 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3460 break;
3461 default:
3462 goto cannot_emulate;
3463 }
aca7f966 3464 } else {
1a6440ae 3465 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3466 &size, &address,
e4e03ded 3467 c->op_bytes);
1b30eaa8 3468 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3469 goto done;
3470 realmode_lidt(ctxt->vcpu, size, address);
3471 }
16286d08
AK		 3472 /* Disable writeback. */
3473 c->dst.type = OP_NONE;
6aa8b732
AK		 3474 break;
3475 case 4: /* smsw */
16286d08 3476 c->dst.bytes = 2;
52a46617 3477 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3478 break;
3479 case 6: /* lmsw */
9928ff60 3480 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3481 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3482 c->dst.type = OP_NONE;
6aa8b732 3483 break;
6e1e5ffe 3484 case 5: /* not defined */
54b8486f 3485 emulate_ud(ctxt);
da9cb575 3486 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 3487 goto done;
6aa8b732 3488 case 7: /* invlpg*/
90de84f5
AK		 3489 emulate_invlpg(ctxt->vcpu,
3490 linear(ctxt, c->src.addr.mem));
16286d08
AK		 3491 /* Disable writeback. */
3492 c->dst.type = OP_NONE;
6aa8b732
AK		 3493 break;
3494 default:
3495 goto cannot_emulate;
3496 }
3497 break;
e99f0507 3498 case 0x05: /* syscall */
3fb1b5db 3499 rc = emulate_syscall(ctxt, ops);
e99f0507 3500 break;
018a98db
AK		 3501 case 0x06:
3502 emulate_clts(ctxt->vcpu);
018a98db 3503 break;
018a98db 3504 case 0x09: /* wbinvd */
f5f48ee1 3505 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3506 break;
3507 case 0x08: /* invd */
018a98db
AK		 3508 case 0x0d: /* GrpP (prefetch) */
3509 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3510 break;
3511 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3512 switch (c->modrm_reg) {
3513 case 1:
3514 case 5 ... 7:
3515 case 9 ... 15:
54b8486f 3516 emulate_ud(ctxt);
da9cb575 3517 rc = X86EMUL_PROPAGATE_FAULT;
6aebfa6e
GN		 3518 goto done;
3519 }
1a0c7d44 3520 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3521 break;
6aa8b732 3522 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3523 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3524 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3525 emulate_ud(ctxt);
da9cb575 3526 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3527 goto done;
3528 }
b27f3856 3529 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3530 break;
018a98db 3531 case 0x22: /* mov reg, cr */
1a0c7d44 3532 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3533 emulate_gp(ctxt, 0);
da9cb575 3534 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 3535 goto done;
3536 }
018a98db
AK		 3537 c->dst.type = OP_NONE;
3538 break;
6aa8b732 3539 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3540 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3541 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3542 emulate_ud(ctxt);
da9cb575 3543 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3544 goto done;
3545 }
35aa5375 3546
b27f3856 3547 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3548 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3549 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3550 /* #UD condition is already handled by the code above */
54b8486f 3551 emulate_gp(ctxt, 0);
da9cb575 3552 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 3553 goto done;
3554 }
3555
a01af5ec 3556 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3557 break;
018a98db
AK		 3558 case 0x30:
3559 /* wrmsr */
3560 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3561 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3562 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3563 emulate_gp(ctxt, 0);
da9cb575 3564 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3565 goto done;
018a98db
AK		 3566 }
3567 rc = X86EMUL_CONTINUE;
018a98db
AK		 3568 break;
3569 case 0x32:
3570 /* rdmsr */
3fb1b5db 3571 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3572 emulate_gp(ctxt, 0);
da9cb575 3573 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3574 goto done;
018a98db
AK		 3575 } else {
3576 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3577 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3578 }
3579 rc = X86EMUL_CONTINUE;
018a98db 3580 break;
e99f0507 3581 case 0x34: /* sysenter */
3fb1b5db 3582 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3583 break;
3584 case 0x35: /* sysexit */
3fb1b5db 3585 rc = emulate_sysexit(ctxt, ops);
e99f0507 3586 break;
6aa8b732 3587 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3588 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3589 if (!test_cc(c->b, ctxt->eflags))
3590 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3591 break;
b2833e3c 3592 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3593 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3594 jmp_rel(c, c->src.val);
018a98db 3595 break;
ee45b58e
WY		 3596 case 0x90 ... 0x9f: /* setcc r/m8 */
3597 c->dst.val = test_cc(c->b, ctxt->eflags);
3598 break;
0934ac9d 3599 case 0xa0: /* push fs */
79168fd1 3600 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3601 break;
3602 case 0xa1: /* pop fs */
3603 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3604 break;
7de75248
NK		 3605 case 0xa3:
3606 bt: /* bt */
e4f8e039 3607 c->dst.type = OP_NONE;
e4e03ded
LV		 3608 /* only subword offset */
3609 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3610 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3611 break;
9bf8ea42
GT		 3612 case 0xa4: /* shld imm8, r, r/m */
3613 case 0xa5: /* shld cl, r, r/m */
3614 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3615 break;
0934ac9d 3616 case 0xa8: /* push gs */
79168fd1 3617 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3618 break;
3619 case 0xa9: /* pop gs */
3620 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3621 break;
7de75248
NK		 3622 case 0xab:
3623 bts: /* bts */
05f086f8 3624 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3625 break;
9bf8ea42
GT		 3626 case 0xac: /* shrd imm8, r, r/m */
3627 case 0xad: /* shrd cl, r, r/m */
3628 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3629 break;
2a7c5b8b
GC		 3630 case 0xae: /* clflush */
3631 break;
6aa8b732
AK		 3632 case 0xb0 ... 0xb1: /* cmpxchg */
3633 /*
3634 * Save real source value, then compare EAX against
3635 * destination.
3636 */
e4e03ded
LV		 3637 c->src.orig_val = c->src.val;
3638 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3639 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3640 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3641 /* Success: write back to memory. */
e4e03ded 3642 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3643 } else {
3644 /* Failure: write the value we saw to EAX. */
e4e03ded 3645 c->dst.type = OP_REG;
1a6440ae 3646 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3647 }
3648 break;
09b5f4d3
WY		 3649 case 0xb2: /* lss */
3650 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3651 break;
6aa8b732
AK		 3652 case 0xb3:
3653 btr: /* btr */
05f086f8 3654 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3655 break;
09b5f4d3
WY		 3656 case 0xb4: /* lfs */
3657 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3658 break;
3659 case 0xb5: /* lgs */
3660 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3661 break;
6aa8b732 3662 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3663 c->dst.bytes = c->op_bytes;
3664 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3665 : (u16) c->src.val;
6aa8b732 3666 break;
6aa8b732 3667 case 0xba: /* Grp8 */
e4e03ded 3668 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3669 case 0:
3670 goto bt;
3671 case 1:
3672 goto bts;
3673 case 2:
3674 goto btr;
3675 case 3:
3676 goto btc;
3677 }
3678 break;
7de75248
NK		 3679 case 0xbb:
3680 btc: /* btc */
05f086f8 3681 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3682 break;
d9574a25
WY		 3683 case 0xbc: { /* bsf */
3684 u8 zf;
3685 __asm__ ("bsf %2, %0; setz %1"
3686 : "=r"(c->dst.val), "=q"(zf)
3687 : "r"(c->src.val));
3688 ctxt->eflags &= ~X86_EFLAGS_ZF;
3689 if (zf) {
3690 ctxt->eflags |= X86_EFLAGS_ZF;
3691 c->dst.type = OP_NONE; /* Disable writeback. */
3692 }
3693 break;
3694 }
3695 case 0xbd: { /* bsr */
3696 u8 zf;
3697 __asm__ ("bsr %2, %0; setz %1"
3698 : "=r"(c->dst.val), "=q"(zf)
3699 : "r"(c->src.val));
3700 ctxt->eflags &= ~X86_EFLAGS_ZF;
3701 if (zf) {
3702 ctxt->eflags |= X86_EFLAGS_ZF;
3703 c->dst.type = OP_NONE; /* Disable writeback. */
3704 }
3705 break;
3706 }
6aa8b732 3707 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3708 c->dst.bytes = c->op_bytes;
3709 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3710 (s16) c->src.val;
6aa8b732 3711 break;
92f738a5
WY		 3712 case 0xc0 ... 0xc1: /* xadd */
3713 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3714 /* Write back the register source. */
3715 c->src.val = c->dst.orig_val;
3716 write_register_operand(&c->src);
3717 break;
a012e65a 3718 case 0xc3: /* movnti */
e4e03ded
LV		 3719 c->dst.bytes = c->op_bytes;
3720 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3721 (u64) c->src.val;
a012e65a 3722 break;
6aa8b732 3723 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3724 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3725 break;
91269b8f
AK		 3726 default:
3727 goto cannot_emulate;
6aa8b732 3728 }
7d9ddaed
AK		 3729
3730 if (rc != X86EMUL_CONTINUE)
3731 goto done;
3732
6aa8b732
AK		 3733 goto writeback;
3734
3735cannot_emulate:
6aa8b732
AK		 3736 return -1;
3737}
Linux kernel - Deliverables
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