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KVM: x86: Emulator ignores LDTR/TR extended base on LLDT/LTR
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
6aa8b732 165
820207c8 166#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 167
d0e53325
AK		 168#define X2(x...) x, x
169#define X3(x...) X2(x), x
170#define X4(x...) X2(x), X2(x)
171#define X5(x...) X4(x), x
172#define X6(x...) X4(x), X2(x)
173#define X7(x...) X4(x), X3(x)
174#define X8(x...) X4(x), X4(x)
175#define X16(x...) X8(x), X8(x)
83babbca 176
e28bbd44
AK		 177#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
178#define FASTOP_SIZE 8
179
180/*
181 * fastop functions have a special calling convention:
182 *
017da7b6
AK		 183 * dst: rax (in/out)
184 * src: rdx (in/out)
e28bbd44
AK		 185 * src2: rcx (in)
186 * flags: rflags (in/out)
b8c0b6ae 187 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 188 *
189 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
190 * different operand sizes can be reached by calculation, rather than a jump
191 * table (which would be bigger than the code).
192 *
193 * fastop functions are declared as taking a never-defined fastop parameter,
194 * so they can't be called from C directly.
195 */
196
197struct fastop;
198
d65b1dee 199struct opcode {
b1ea50b2
AK		 200 u64 flags : 56;
201 u64 intercept : 8;
120df890 202 union {
ef65c889 203 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 204 const struct opcode *group;
205 const struct group_dual *gdual;
206 const struct gprefix *gprefix;
045a282c 207 const struct escape *esc;
e28bbd44 208 void (*fastop)(struct fastop *fake);
120df890 209 } u;
d09beabd 210 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 211};
212
213struct group_dual {
214 struct opcode mod012[8];
215 struct opcode mod3[8];
d65b1dee
AK		 216};
217
0d7cdee8
AK		 218struct gprefix {
219 struct opcode pfx_no;
220 struct opcode pfx_66;
221 struct opcode pfx_f2;
222 struct opcode pfx_f3;
223};
224
045a282c
GN		 225struct escape {
226 struct opcode op[8];
227 struct opcode high[64];
228};
229
6aa8b732 230/* EFLAGS bit definitions. */
d4c6a154
GN		 231#define EFLG_ID (1<<21)
232#define EFLG_VIP (1<<20)
233#define EFLG_VIF (1<<19)
234#define EFLG_AC (1<<18)
b1d86143
AP		 235#define EFLG_VM (1<<17)
236#define EFLG_RF (1<<16)
d4c6a154
GN		 237#define EFLG_IOPL (3<<12)
238#define EFLG_NT (1<<14)
6aa8b732
AK		 239#define EFLG_OF (1<<11)
240#define EFLG_DF (1<<10)
b1d86143 241#define EFLG_IF (1<<9)
d4c6a154 242#define EFLG_TF (1<<8)
6aa8b732
AK		 243#define EFLG_SF (1<<7)
244#define EFLG_ZF (1<<6)
245#define EFLG_AF (1<<4)
246#define EFLG_PF (1<<2)
247#define EFLG_CF (1<<0)
248
62bd430e
MG		 249#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
250#define EFLG_RESERVED_ONE_MASK 2
251
dd856efa
AK		 252static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
253{
254 if (!(ctxt->regs_valid & (1 << nr))) {
255 ctxt->regs_valid |= 1 << nr;
256 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
257 }
258 return ctxt->_regs[nr];
259}
260
261static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 ctxt->regs_valid |= 1 << nr;
264 ctxt->regs_dirty |= 1 << nr;
265 return &ctxt->_regs[nr];
266}
267
268static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
269{
270 reg_read(ctxt, nr);
271 return reg_write(ctxt, nr);
272}
273
274static void writeback_registers(struct x86_emulate_ctxt *ctxt)
275{
276 unsigned reg;
277
278 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
279 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
280}
281
282static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
283{
284 ctxt->regs_dirty = 0;
285 ctxt->regs_valid = 0;
286}
287
6aa8b732
AK		 288/*
289 * These EFLAGS bits are restored from saved value during emulation, and
290 * any changes are written back to the saved value after emulation.
291 */
292#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
293
dda96d8f
AK		 294#ifdef CONFIG_X86_64
295#define ON64(x) x
296#else
297#define ON64(x)
298#endif
299
4d758349
AK		 300static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
301
b7d491e7
AK		 302#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
303#define FOP_RET "ret \n\t"
304
305#define FOP_START(op) \
306 extern void em_##op(struct fastop *fake); \
307 asm(".pushsection .text, \"ax\" \n\t" \
308 ".global em_" #op " \n\t" \
309 FOP_ALIGN \
310 "em_" #op ": \n\t"
311
312#define FOP_END \
313 ".popsection")
314
0bdea068
AK		 315#define FOPNOP() FOP_ALIGN FOP_RET
316
b7d491e7 317#define FOP1E(op, dst) \
b8c0b6ae
AK		 318 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
319
320#define FOP1EEX(op, dst) \
321 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 322
323#define FASTOP1(op) \
324 FOP_START(op) \
325 FOP1E(op##b, al) \
326 FOP1E(op##w, ax) \
327 FOP1E(op##l, eax) \
328 ON64(FOP1E(op##q, rax)) \
329 FOP_END
330
b9fa409b
AK		 331/* 1-operand, using src2 (for MUL/DIV r/m) */
332#define FASTOP1SRC2(op, name) \
333 FOP_START(name) \
334 FOP1E(op, cl) \
335 FOP1E(op, cx) \
336 FOP1E(op, ecx) \
337 ON64(FOP1E(op, rcx)) \
338 FOP_END
339
b8c0b6ae
AK		 340/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
341#define FASTOP1SRC2EX(op, name) \
342 FOP_START(name) \
343 FOP1EEX(op, cl) \
344 FOP1EEX(op, cx) \
345 FOP1EEX(op, ecx) \
346 ON64(FOP1EEX(op, rcx)) \
347 FOP_END
348
f7857f35
AK		 349#define FOP2E(op, dst, src) \
350 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
351
352#define FASTOP2(op) \
353 FOP_START(op) \
017da7b6
AK		 354 FOP2E(op##b, al, dl) \
355 FOP2E(op##w, ax, dx) \
356 FOP2E(op##l, eax, edx) \
357 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 358 FOP_END
359
11c363ba
AK		 360/* 2 operand, word only */
361#define FASTOP2W(op) \
362 FOP_START(op) \
363 FOPNOP() \
017da7b6
AK		 364 FOP2E(op##w, ax, dx) \
365 FOP2E(op##l, eax, edx) \
366 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 367 FOP_END
368
007a3b54
AK		 369/* 2 operand, src is CL */
370#define FASTOP2CL(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, cl) \
373 FOP2E(op##w, ax, cl) \
374 FOP2E(op##l, eax, cl) \
375 ON64(FOP2E(op##q, rax, cl)) \
376 FOP_END
377
0bdea068
AK		 378#define FOP3E(op, dst, src, src2) \
379 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
380
381/* 3-operand, word-only, src2=cl */
382#define FASTOP3WCL(op) \
383 FOP_START(op) \
384 FOPNOP() \
017da7b6
AK		 385 FOP3E(op##w, ax, dx, cl) \
386 FOP3E(op##l, eax, edx, cl) \
387 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 388 FOP_END
389
9ae9feba
AK		 390/* Special case for SETcc - 1 instruction per cc */
391#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
392
b8c0b6ae
AK		 393asm(".global kvm_fastop_exception \n"
394 "kvm_fastop_exception: xor %esi, %esi; ret");
395
9ae9feba
AK		 396FOP_START(setcc)
397FOP_SETCC(seto)
398FOP_SETCC(setno)
399FOP_SETCC(setc)
400FOP_SETCC(setnc)
401FOP_SETCC(setz)
402FOP_SETCC(setnz)
403FOP_SETCC(setbe)
404FOP_SETCC(setnbe)
405FOP_SETCC(sets)
406FOP_SETCC(setns)
407FOP_SETCC(setp)
408FOP_SETCC(setnp)
409FOP_SETCC(setl)
410FOP_SETCC(setnl)
411FOP_SETCC(setle)
412FOP_SETCC(setnle)
413FOP_END;
414
326f578f
PB		 415FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
416FOP_END;
417
8a76d7f2
JR		 418static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
419 enum x86_intercept intercept,
420 enum x86_intercept_stage stage)
421{
422 struct x86_instruction_info info = {
423 .intercept = intercept,
9dac77fa
AK		 424 .rep_prefix = ctxt->rep_prefix,
425 .modrm_mod = ctxt->modrm_mod,
426 .modrm_reg = ctxt->modrm_reg,
427 .modrm_rm = ctxt->modrm_rm,
428 .src_val = ctxt->src.val64,
429 .src_bytes = ctxt->src.bytes,
430 .dst_bytes = ctxt->dst.bytes,
431 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 432 .next_rip = ctxt->eip,
433 };
434
2953538e 435 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 436}
437
f47cfa31
AK		 438static void assign_masked(ulong *dest, ulong src, ulong mask)
439{
440 *dest = (*dest & ~mask) | (src & mask);
441}
442
9dac77fa 443static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 444{
9dac77fa 445 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 446}
447
f47cfa31
AK		 448static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
449{
450 u16 sel;
451 struct desc_struct ss;
452
453 if (ctxt->mode == X86EMUL_MODE_PROT64)
454 return ~0UL;
455 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
456 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
457}
458
612e89f0
AK		 459static int stack_size(struct x86_emulate_ctxt *ctxt)
460{
461 return (__fls(stack_mask(ctxt)) + 1) >> 3;
462}
463
6aa8b732 464/* Access/update address held in a register, based on addressing mode. */
e4706772 465static inline unsigned long
9dac77fa 466address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 467{
9dac77fa 468 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 469 return reg;
470 else
9dac77fa 471 return reg & ad_mask(ctxt);
e4706772
HH		 472}
473
474static inline unsigned long
9dac77fa 475register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 476{
9dac77fa 477 return address_mask(ctxt, reg);
e4706772
HH		 478}
479
5ad105e5
AK		 480static void masked_increment(ulong *reg, ulong mask, int inc)
481{
482 assign_masked(reg, *reg + inc, mask);
483}
484
7a957275 485static inline void
9dac77fa 486register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 487{
5ad105e5
AK		 488 ulong mask;
489
9dac77fa 490 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 491 mask = ~0UL;
7a957275 492 else
5ad105e5
AK		 493 mask = ad_mask(ctxt);
494 masked_increment(reg, mask, inc);
495}
496
497static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
498{
dd856efa 499 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 500}
6aa8b732 501
9dac77fa 502static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 503{
9dac77fa 504 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 505}
098c937b 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
9dac77fa 514static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 515{
9dac77fa
AK		 516 ctxt->has_seg_override = true;
517 ctxt->seg_override = seg;
7a5b56df
AK		 518}
519
7b105ca2 520static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 521{
522 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
523 return 0;
524
7b105ca2 525 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 526}
527
9dac77fa 528static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 529{
9dac77fa 530 if (!ctxt->has_seg_override)
7a5b56df
AK		 531 return 0;
532
9dac77fa 533 return ctxt->seg_override;
7a5b56df
AK		 534}
535
35d3d4a1
AK		 536static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
537 u32 error, bool valid)
54b8486f 538{
da9cb575
AK		 539 ctxt->exception.vector = vec;
540 ctxt->exception.error_code = error;
541 ctxt->exception.error_code_valid = valid;
35d3d4a1 542 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 543}
544
3b88e41a
JR		 545static int emulate_db(struct x86_emulate_ctxt *ctxt)
546{
547 return emulate_exception(ctxt, DB_VECTOR, 0, false);
548}
549
35d3d4a1 550static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 551{
35d3d4a1 552 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 553}
554
618ff15d
AK		 555static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
556{
557 return emulate_exception(ctxt, SS_VECTOR, err, true);
558}
559
35d3d4a1 560static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 561{
35d3d4a1 562 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 563}
564
35d3d4a1 565static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 566{
35d3d4a1 567 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 568}
569
34d1f490
AK		 570static int emulate_de(struct x86_emulate_ctxt *ctxt)
571{
35d3d4a1 572 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 573}
574
1253791d
AK		 575static int emulate_nm(struct x86_emulate_ctxt *ctxt)
576{
577 return emulate_exception(ctxt, NM_VECTOR, 0, false);
578}
579
1aa36616
AK		 580static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
581{
582 u16 selector;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
586 return selector;
587}
588
589static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
590 unsigned seg)
591{
592 u16 dummy;
593 u32 base3;
594 struct desc_struct desc;
595
596 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
597 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
598}
599
1c11b376
AK		 600/*
601 * x86 defines three classes of vector instructions: explicitly
602 * aligned, explicitly unaligned, and the rest, which change behaviour
603 * depending on whether they're AVX encoded or not.
604 *
605 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
606 * subject to the same check.
607 */
608static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
609{
610 if (likely(size < 16))
611 return false;
612
613 if (ctxt->d & Aligned)
614 return true;
615 else if (ctxt->d & Unaligned)
616 return false;
617 else if (ctxt->d & Avx)
618 return false;
619 else
620 return true;
621}
622
3d9b938e 623static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 624 struct segmented_address addr,
3d9b938e 625 unsigned size, bool write, bool fetch,
52fd8b44
AK		 626 ulong *linear)
627{
618ff15d
AK		 628 struct desc_struct desc;
629 bool usable;
52fd8b44 630 ulong la;
618ff15d 631 u32 lim;
1aa36616 632 u16 sel;
3a78a4f4 633 unsigned cpl;
52fd8b44 634
7b105ca2 635 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 636 switch (ctxt->mode) {
618ff15d
AK		 637 case X86EMUL_MODE_PROT64:
638 if (((signed long)la << 16) >> 16 != la)
639 return emulate_gp(ctxt, 0);
640 break;
641 default:
1aa36616
AK		 642 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
643 addr.seg);
618ff15d
AK		 644 if (!usable)
645 goto bad;
58b7825b
GN		 646 /* code segment in protected mode or read-only data segment */
647 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
648 || !(desc.type & 2)) && write)
618ff15d
AK		 649 goto bad;
650 /* unreadable code segment */
3d9b938e 651 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 652 goto bad;
653 lim = desc_limit_scaled(&desc);
654 if ((desc.type & 8) || !(desc.type & 4)) {
655 /* expand-up segment */
656 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
657 goto bad;
658 } else {
fc058680 659 /* expand-down segment */
618ff15d
AK		 660 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
661 goto bad;
662 lim = desc.d ? 0xffffffff : 0xffff;
663 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
664 goto bad;
665 }
717746e3 666 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 667 if (!(desc.type & 8)) {
668 /* data segment */
669 if (cpl > desc.dpl)
670 goto bad;
671 } else if ((desc.type & 8) && !(desc.type & 4)) {
672 /* nonconforming code segment */
673 if (cpl != desc.dpl)
674 goto bad;
675 } else if ((desc.type & 8) && (desc.type & 4)) {
676 /* conforming code segment */
677 if (cpl < desc.dpl)
678 goto bad;
679 }
680 break;
681 }
9dac77fa 682 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 683 la &= (u32)-1;
1c11b376
AK		 684 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
685 return emulate_gp(ctxt, 0);
52fd8b44
AK		 686 *linear = la;
687 return X86EMUL_CONTINUE;
618ff15d
AK		 688bad:
689 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 690 return emulate_ss(ctxt, sel);
618ff15d 691 else
0afbe2f8 692 return emulate_gp(ctxt, sel);
52fd8b44
AK		 693}
694
3d9b938e
NE		 695static int linearize(struct x86_emulate_ctxt *ctxt,
696 struct segmented_address addr,
697 unsigned size, bool write,
698 ulong *linear)
699{
700 return __linearize(ctxt, addr, size, write, false, linear);
701}
702
703
3ca3ac4d
AK		 704static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
705 struct segmented_address addr,
706 void *data,
707 unsigned size)
708{
9fa088f4
AK		 709 int rc;
710 ulong linear;
711
83b8795a 712 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 713 if (rc != X86EMUL_CONTINUE)
714 return rc;
0f65dd70 715 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 716}
717
807941b1
TY		 718/*
719 * Fetch the next byte of the instruction being emulated which is pointed to
720 * by ctxt->_eip, then increment ctxt->_eip.
721 *
722 * Also prefetch the remaining bytes of the instruction without crossing page
723 * boundary if they are not in fetch_cache yet.
724 */
725static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 726{
9dac77fa 727 struct fetch_cache *fc = &ctxt->fetch;
62266869 728 int rc;
2fb53ad8 729 int size, cur_size;
62266869 730
807941b1 731 if (ctxt->_eip == fc->end) {
3d9b938e 732 unsigned long linear;
807941b1
TY		 733 struct segmented_address addr = { .seg = VCPU_SREG_CS,
734 .ea = ctxt->_eip };
2fb53ad8 735 cur_size = fc->end - fc->start;
807941b1
TY		 736 size = min(15UL - cur_size,
737 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 738 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 739 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 740 return rc;
ef5d75cc
TY		 741 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
742 size, &ctxt->exception);
7d88bb48 743 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 744 return rc;
2fb53ad8 745 fc->end += size;
62266869 746 }
807941b1
TY		 747 *dest = fc->data[ctxt->_eip - fc->start];
748 ctxt->_eip++;
3e2815e9 749 return X86EMUL_CONTINUE;
62266869
AK		 750}
751
752static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 753 void *dest, unsigned size)
62266869 754{
3e2815e9 755 int rc;
62266869 756
eb3c79e6 757 /* x86 instructions are limited to 15 bytes. */
7d88bb48 758 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 759 return X86EMUL_UNHANDLEABLE;
62266869 760 while (size--) {
807941b1 761 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 762 if (rc != X86EMUL_CONTINUE)
62266869
AK		 763 return rc;
764 }
3e2815e9 765 return X86EMUL_CONTINUE;
62266869
AK		 766}
767
67cbc90d 768/* Fetch next part of the instruction being emulated. */
e85a1085 769#define insn_fetch(_type, _ctxt) \
67cbc90d 770({ unsigned long _x; \
e85a1085 771 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 772 if (rc != X86EMUL_CONTINUE) \
773 goto done; \
67cbc90d
TY		 774 (_type)_x; \
775})
776
807941b1
TY		 777#define insn_fetch_arr(_arr, _size, _ctxt) \
778({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 779 if (rc != X86EMUL_CONTINUE) \
780 goto done; \
67cbc90d
TY		 781})
782
1e3c5cb0
RR		 783/*
784 * Given the 'reg' portion of a ModRM byte, and a register block, return a
785 * pointer into the block that addresses the relevant register.
786 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
787 */
dd856efa 788static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 789 int byteop)
6aa8b732
AK		 790{
791 void *p;
aa9ac1a6 792 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 793
6aa8b732 794 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 795 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
796 else
797 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 798 return p;
799}
800
801static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 802 struct segmented_address addr,
6aa8b732
AK		 803 u16 *size, unsigned long *address, int op_bytes)
804{
805 int rc;
806
807 if (op_bytes == 2)
808 op_bytes = 3;
809 *address = 0;
3ca3ac4d 810 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 811 if (rc != X86EMUL_CONTINUE)
6aa8b732 812 return rc;
30b31ab6 813 addr.ea += 2;
3ca3ac4d 814 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 815 return rc;
816}
817
34b77652
AK		 818FASTOP2(add);
819FASTOP2(or);
820FASTOP2(adc);
821FASTOP2(sbb);
822FASTOP2(and);
823FASTOP2(sub);
824FASTOP2(xor);
825FASTOP2(cmp);
826FASTOP2(test);
827
b9fa409b
AK		 828FASTOP1SRC2(mul, mul_ex);
829FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 830FASTOP1SRC2EX(div, div_ex);
831FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 832
34b77652
AK		 833FASTOP3WCL(shld);
834FASTOP3WCL(shrd);
835
836FASTOP2W(imul);
837
838FASTOP1(not);
839FASTOP1(neg);
840FASTOP1(inc);
841FASTOP1(dec);
842
843FASTOP2CL(rol);
844FASTOP2CL(ror);
845FASTOP2CL(rcl);
846FASTOP2CL(rcr);
847FASTOP2CL(shl);
848FASTOP2CL(shr);
849FASTOP2CL(sar);
850
851FASTOP2W(bsf);
852FASTOP2W(bsr);
853FASTOP2W(bt);
854FASTOP2W(bts);
855FASTOP2W(btr);
856FASTOP2W(btc);
857
e47a5f5f
AK		 858FASTOP2(xadd);
859
9ae9feba 860static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 861{
9ae9feba
AK		 862 u8 rc;
863 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 864
9ae9feba 865 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 866 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 867 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
868 return rc;
bbe9abbd
NK		 869}
870
91ff3cb4
AK		 871static void fetch_register_operand(struct operand *op)
872{
873 switch (op->bytes) {
874 case 1:
875 op->val = *(u8 *)op->addr.reg;
876 break;
877 case 2:
878 op->val = *(u16 *)op->addr.reg;
879 break;
880 case 4:
881 op->val = *(u32 *)op->addr.reg;
882 break;
883 case 8:
884 op->val = *(u64 *)op->addr.reg;
885 break;
886 }
887}
888
1253791d
AK		 889static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
890{
891 ctxt->ops->get_fpu(ctxt);
892 switch (reg) {
89a87c67
MK		 893 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
894 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
895 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
896 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
897 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
898 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
899 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
900 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 901#ifdef CONFIG_X86_64
89a87c67
MK		 902 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
903 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
904 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
905 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
906 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
907 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
908 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
909 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 910#endif
911 default: BUG();
912 }
913 ctxt->ops->put_fpu(ctxt);
914}
915
916static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
917 int reg)
918{
919 ctxt->ops->get_fpu(ctxt);
920 switch (reg) {
89a87c67
MK		 921 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
922 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
923 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
924 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
925 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
926 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
927 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
928 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 929#ifdef CONFIG_X86_64
89a87c67
MK		 930 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
931 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
932 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
933 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
934 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
935 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
936 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
937 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 938#endif
939 default: BUG();
940 }
941 ctxt->ops->put_fpu(ctxt);
942}
943
cbe2c9d3
AK		 944static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
948 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
949 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
950 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
951 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
952 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
953 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
954 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
955 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
956 default: BUG();
957 }
958 ctxt->ops->put_fpu(ctxt);
959}
960
961static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
965 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
966 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
967 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
968 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
969 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
970 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
971 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
972 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
045a282c
GN		 978static int em_fninit(struct x86_emulate_ctxt *ctxt)
979{
980 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
981 return emulate_nm(ctxt);
982
983 ctxt->ops->get_fpu(ctxt);
984 asm volatile("fninit");
985 ctxt->ops->put_fpu(ctxt);
986 return X86EMUL_CONTINUE;
987}
988
989static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
990{
991 u16 fcw;
992
993 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
994 return emulate_nm(ctxt);
995
996 ctxt->ops->get_fpu(ctxt);
997 asm volatile("fnstcw %0": "+m"(fcw));
998 ctxt->ops->put_fpu(ctxt);
999
1000 /* force 2 byte destination */
1001 ctxt->dst.bytes = 2;
1002 ctxt->dst.val = fcw;
1003
1004 return X86EMUL_CONTINUE;
1005}
1006
1007static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1008{
1009 u16 fsw;
1010
1011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1012 return emulate_nm(ctxt);
1013
1014 ctxt->ops->get_fpu(ctxt);
1015 asm volatile("fnstsw %0": "+m"(fsw));
1016 ctxt->ops->put_fpu(ctxt);
1017
1018 /* force 2 byte destination */
1019 ctxt->dst.bytes = 2;
1020 ctxt->dst.val = fsw;
1021
1022 return X86EMUL_CONTINUE;
1023}
1024
1253791d 1025static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1026 struct operand *op)
3c118e24 1027{
9dac77fa 1028 unsigned reg = ctxt->modrm_reg;
33615aa9 1029
9dac77fa
AK		 1030 if (!(ctxt->d & ModRM))
1031 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1032
9dac77fa 1033 if (ctxt->d & Sse) {
1253791d
AK		 1034 op->type = OP_XMM;
1035 op->bytes = 16;
1036 op->addr.xmm = reg;
1037 read_sse_reg(ctxt, &op->vec_val, reg);
1038 return;
1039 }
cbe2c9d3
AK		 1040 if (ctxt->d & Mmx) {
1041 reg &= 7;
1042 op->type = OP_MM;
1043 op->bytes = 8;
1044 op->addr.mm = reg;
1045 return;
1046 }
1253791d 1047
3c118e24 1048 op->type = OP_REG;
6d4d85ec
GN		 1049 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1050 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1051
91ff3cb4 1052 fetch_register_operand(op);
3c118e24
AK		 1053 op->orig_val = op->val;
1054}
1055
a6e3407b
AK		 1056static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1057{
1058 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1059 ctxt->modrm_seg = VCPU_SREG_SS;
1060}
1061
1c73ef66 1062static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1063 struct operand *op)
1c73ef66 1064{
1c73ef66 1065 u8 sib;
f5b4edcd 1066 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1067 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1068 ulong modrm_ea = 0;
1c73ef66 1069
9dac77fa
AK		 1070 if (ctxt->rex_prefix) {
1071 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1072 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1073 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1074 }
1075
9dac77fa
AK		 1076 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1077 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1078 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1079 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1080
9b88ae99 1081 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1082 op->type = OP_REG;
9dac77fa 1083 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1084 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1085 ctxt->d & ByteOp);
9dac77fa 1086 if (ctxt->d & Sse) {
1253791d
AK		 1087 op->type = OP_XMM;
1088 op->bytes = 16;
9dac77fa
AK		 1089 op->addr.xmm = ctxt->modrm_rm;
1090 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1091 return rc;
1092 }
cbe2c9d3
AK		 1093 if (ctxt->d & Mmx) {
1094 op->type = OP_MM;
1095 op->bytes = 8;
1096 op->addr.xmm = ctxt->modrm_rm & 7;
1097 return rc;
1098 }
2dbd0dd7 1099 fetch_register_operand(op);
1c73ef66
AK		 1100 return rc;
1101 }
1102
2dbd0dd7
AK		 1103 op->type = OP_MEM;
1104
9dac77fa 1105 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1106 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1107 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1108 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1109 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1110
1111 /* 16-bit ModR/M decode. */
9dac77fa 1112 switch (ctxt->modrm_mod) {
1c73ef66 1113 case 0:
9dac77fa 1114 if (ctxt->modrm_rm == 6)
e85a1085 1115 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1116 break;
1117 case 1:
e85a1085 1118 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1119 break;
1120 case 2:
e85a1085 1121 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1122 break;
1123 }
9dac77fa 1124 switch (ctxt->modrm_rm) {
1c73ef66 1125 case 0:
2dbd0dd7 1126 modrm_ea += bx + si;
1c73ef66
AK		 1127 break;
1128 case 1:
2dbd0dd7 1129 modrm_ea += bx + di;
1c73ef66
AK		 1130 break;
1131 case 2:
2dbd0dd7 1132 modrm_ea += bp + si;
1c73ef66
AK		 1133 break;
1134 case 3:
2dbd0dd7 1135 modrm_ea += bp + di;
1c73ef66
AK		 1136 break;
1137 case 4:
2dbd0dd7 1138 modrm_ea += si;
1c73ef66
AK		 1139 break;
1140 case 5:
2dbd0dd7 1141 modrm_ea += di;
1c73ef66
AK		 1142 break;
1143 case 6:
9dac77fa 1144 if (ctxt->modrm_mod != 0)
2dbd0dd7 1145 modrm_ea += bp;
1c73ef66
AK		 1146 break;
1147 case 7:
2dbd0dd7 1148 modrm_ea += bx;
1c73ef66
AK		 1149 break;
1150 }
9dac77fa
AK		 1151 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1152 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1153 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1154 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1155 } else {
1156 /* 32/64-bit ModR/M decode. */
9dac77fa 1157 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1158 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1159 index_reg |= (sib >> 3) & 7;
1160 base_reg |= sib & 7;
1161 scale = sib >> 6;
1162
9dac77fa 1163 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1165 else {
dd856efa 1166 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1167 adjust_modrm_seg(ctxt, base_reg);
1168 }
dc71d0f1 1169 if (index_reg != 4)
dd856efa 1170 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1171 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1172 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1173 ctxt->rip_relative = 1;
a6e3407b
AK		 1174 } else {
1175 base_reg = ctxt->modrm_rm;
dd856efa 1176 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1177 adjust_modrm_seg(ctxt, base_reg);
1178 }
9dac77fa 1179 switch (ctxt->modrm_mod) {
1c73ef66 1180 case 0:
9dac77fa 1181 if (ctxt->modrm_rm == 5)
e85a1085 1182 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1183 break;
1184 case 1:
e85a1085 1185 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1186 break;
1187 case 2:
e85a1085 1188 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1189 break;
1190 }
1191 }
90de84f5 1192 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1193done:
1194 return rc;
1195}
1196
1197static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1198 struct operand *op)
1c73ef66 1199{
3e2815e9 1200 int rc = X86EMUL_CONTINUE;
1c73ef66 1201
2dbd0dd7 1202 op->type = OP_MEM;
9dac77fa 1203 switch (ctxt->ad_bytes) {
1c73ef66 1204 case 2:
e85a1085 1205 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1206 break;
1207 case 4:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1209 break;
1210 case 8:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1212 break;
1213 }
1214done:
1215 return rc;
1216}
1217
9dac77fa 1218static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1219{
7129eeca 1220 long sv = 0, mask;
35c843c4 1221
9dac77fa
AK		 1222 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1223 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1224
9dac77fa
AK		 1225 if (ctxt->src.bytes == 2)
1226 sv = (s16)ctxt->src.val & (s16)mask;
1227 else if (ctxt->src.bytes == 4)
1228 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1229
9dac77fa 1230 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1231 }
ba7ff2b7
WY		 1232
1233 /* only subword offset */
9dac77fa 1234 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1235}
1236
dde7e6d1 1237static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1238 unsigned long addr, void *dest, unsigned size)
6aa8b732 1239{
dde7e6d1 1240 int rc;
9dac77fa 1241 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1242
f23b070e
XG		 1243 if (mc->pos < mc->end)
1244 goto read_cached;
6aa8b732 1245
f23b070e
XG		 1246 WARN_ON((mc->end + size) >= sizeof(mc->data));
1247
1248 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1249 &ctxt->exception);
1250 if (rc != X86EMUL_CONTINUE)
1251 return rc;
1252
1253 mc->end += size;
1254
1255read_cached:
1256 memcpy(dest, mc->data + mc->pos, size);
1257 mc->pos += size;
dde7e6d1
AK		 1258 return X86EMUL_CONTINUE;
1259}
6aa8b732 1260
3ca3ac4d
AK		 1261static int segmented_read(struct x86_emulate_ctxt *ctxt,
1262 struct segmented_address addr,
1263 void *data,
1264 unsigned size)
1265{
9fa088f4
AK		 1266 int rc;
1267 ulong linear;
1268
83b8795a 1269 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
7b105ca2 1272 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1273}
1274
1275static int segmented_write(struct x86_emulate_ctxt *ctxt,
1276 struct segmented_address addr,
1277 const void *data,
1278 unsigned size)
1279{
9fa088f4
AK		 1280 int rc;
1281 ulong linear;
1282
83b8795a 1283 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
0f65dd70
AK		 1286 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1287 &ctxt->exception);
3ca3ac4d
AK		 1288}
1289
1290static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1291 struct segmented_address addr,
1292 const void *orig_data, const void *data,
1293 unsigned size)
1294{
9fa088f4
AK		 1295 int rc;
1296 ulong linear;
1297
83b8795a 1298 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
0f65dd70
AK		 1301 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1302 size, &ctxt->exception);
3ca3ac4d
AK		 1303}
1304
dde7e6d1 1305static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1306 unsigned int size, unsigned short port,
1307 void *dest)
1308{
9dac77fa 1309 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1310
dde7e6d1 1311 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1312 unsigned int in_page, n;
9dac77fa 1313 unsigned int count = ctxt->rep_prefix ?
dd856efa 1314 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1315 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1316 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1317 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1318 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1319 count);
1320 if (n == 0)
1321 n = 1;
1322 rc->pos = rc->end = 0;
7b105ca2 1323 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1324 return 0;
1325 rc->end = n * size;
6aa8b732
AK		 1326 }
1327
e6e39f04
NA		 1328 if (ctxt->rep_prefix && (ctxt->d & String) &&
1329 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1330 ctxt->dst.data = rc->data + rc->pos;
1331 ctxt->dst.type = OP_MEM_STR;
1332 ctxt->dst.count = (rc->end - rc->pos) / size;
1333 rc->pos = rc->end;
1334 } else {
1335 memcpy(dest, rc->data + rc->pos, size);
1336 rc->pos += size;
1337 }
dde7e6d1
AK		 1338 return 1;
1339}
6aa8b732 1340
7f3d35fd
KW		 1341static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1342 u16 index, struct desc_struct *desc)
1343{
1344 struct desc_ptr dt;
1345 ulong addr;
1346
1347 ctxt->ops->get_idt(ctxt, &dt);
1348
1349 if (dt.size < index * 8 + 7)
1350 return emulate_gp(ctxt, index << 3 | 0x2);
1351
1352 addr = dt.address + index * 8;
1353 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1354 &ctxt->exception);
1355}
1356
dde7e6d1 1357static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1358 u16 selector, struct desc_ptr *dt)
1359{
0225fb50 1360 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1361
dde7e6d1
AK		 1362 if (selector & 1 << 2) {
1363 struct desc_struct desc;
1aa36616
AK		 1364 u16 sel;
1365
dde7e6d1 1366 memset (dt, 0, sizeof *dt);
1aa36616 1367 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1368 return;
e09d082c 1369
dde7e6d1
AK		 1370 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1371 dt->address = get_desc_base(&desc);
1372 } else
4bff1e86 1373 ops->get_gdt(ctxt, dt);
dde7e6d1 1374}
120df890 1375
dde7e6d1
AK		 1376/* allowed just for 8 bytes segments */
1377static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1378 u16 selector, struct desc_struct *desc,
1379 ulong *desc_addr_p)
dde7e6d1
AK		 1380{
1381 struct desc_ptr dt;
1382 u16 index = selector >> 3;
dde7e6d1 1383 ulong addr;
120df890 1384
7b105ca2 1385 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1386
35d3d4a1
AK		 1387 if (dt.size < index * 8 + 7)
1388 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1389
e919464b 1390 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1391 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1392 &ctxt->exception);
dde7e6d1 1393}
ef65c889 1394
dde7e6d1
AK		 1395/* allowed just for 8 bytes segments */
1396static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1397 u16 selector, struct desc_struct *desc)
1398{
1399 struct desc_ptr dt;
1400 u16 index = selector >> 3;
dde7e6d1 1401 ulong addr;
6aa8b732 1402
7b105ca2 1403 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1404
35d3d4a1
AK		 1405 if (dt.size < index * 8 + 7)
1406 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1407
dde7e6d1 1408 addr = dt.address + index * 8;
7b105ca2
TY		 1409 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1410 &ctxt->exception);
dde7e6d1 1411}
c7e75a3d 1412
5601d05b 1413/* Does not support long mode */
2356aaeb 1414static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1415 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1416{
869be99c 1417 struct desc_struct seg_desc, old_desc;
2356aaeb 1418 u8 dpl, rpl;
dde7e6d1
AK		 1419 unsigned err_vec = GP_VECTOR;
1420 u32 err_code = 0;
1421 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1422 ulong desc_addr;
dde7e6d1 1423 int ret;
03ebebeb 1424 u16 dummy;
e37a75a1 1425 u32 base3 = 0;
69f55cb1 1426
dde7e6d1 1427 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1428
f8da94e9
KW		 1429 if (ctxt->mode == X86EMUL_MODE_REAL) {
1430 /* set real mode segment descriptor (keep limit etc. for
1431 * unreal mode) */
03ebebeb 1432 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1433 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1434 goto load;
f8da94e9
KW		 1435 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1436 /* VM86 needs a clean new segment descriptor */
1437 set_desc_base(&seg_desc, selector << 4);
1438 set_desc_limit(&seg_desc, 0xffff);
1439 seg_desc.type = 3;
1440 seg_desc.p = 1;
1441 seg_desc.s = 1;
1442 seg_desc.dpl = 3;
1443 goto load;
dde7e6d1
AK		 1444 }
1445
79d5b4c3 1446 rpl = selector & 3;
79d5b4c3
AK		 1447
1448 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1449 if ((seg == VCPU_SREG_CS
1450 || (seg == VCPU_SREG_SS
1451 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1452 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1453 && null_selector)
1454 goto exception;
1455
1456 /* TR should be in GDT only */
1457 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1458 goto exception;
1459
1460 if (null_selector) /* for NULL selector skip all following checks */
1461 goto load;
1462
e919464b 1463 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1464 if (ret != X86EMUL_CONTINUE)
1465 return ret;
1466
1467 err_code = selector & 0xfffc;
1468 err_vec = GP_VECTOR;
1469
fc058680 1470 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1471 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1472 goto exception;
1473
1474 if (!seg_desc.p) {
1475 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1476 goto exception;
1477 }
1478
dde7e6d1 1479 dpl = seg_desc.dpl;
dde7e6d1
AK		 1480
1481 switch (seg) {
1482 case VCPU_SREG_SS:
1483 /*
1484 * segment is not a writable data segment or segment
1485 * selector's RPL != CPL or segment selector's RPL != CPL
1486 */
1487 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1488 goto exception;
6aa8b732 1489 break;
dde7e6d1 1490 case VCPU_SREG_CS:
5045b468
PB		 1491 if (in_task_switch && rpl != dpl)
1492 goto exception;
1493
dde7e6d1
AK		 1494 if (!(seg_desc.type & 8))
1495 goto exception;
1496
1497 if (seg_desc.type & 4) {
1498 /* conforming */
1499 if (dpl > cpl)
1500 goto exception;
1501 } else {
1502 /* nonconforming */
1503 if (rpl > cpl || dpl != cpl)
1504 goto exception;
1505 }
1506 /* CS(RPL) <- CPL */
1507 selector = (selector & 0xfffc) | cpl;
6aa8b732 1508 break;
dde7e6d1
AK		 1509 case VCPU_SREG_TR:
1510 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1511 goto exception;
869be99c
AK		 1512 old_desc = seg_desc;
1513 seg_desc.type |= 2; /* busy */
1514 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1515 sizeof(seg_desc), &ctxt->exception);
1516 if (ret != X86EMUL_CONTINUE)
1517 return ret;
dde7e6d1
AK		 1518 break;
1519 case VCPU_SREG_LDTR:
1520 if (seg_desc.s || seg_desc.type != 2)
1521 goto exception;
1522 break;
1523 default: /* DS, ES, FS, or GS */
4e62417b 1524 /*
dde7e6d1
AK		 1525 * segment is not a data or readable code segment or
1526 * ((segment is a data or nonconforming code segment)
1527 * and (both RPL and CPL > DPL))
4e62417b 1528 */
dde7e6d1
AK		 1529 if ((seg_desc.type & 0xa) == 0x8 ||
1530 (((seg_desc.type & 0xc) != 0xc) &&
1531 (rpl > dpl && cpl > dpl)))
1532 goto exception;
6aa8b732 1533 break;
dde7e6d1
AK		 1534 }
1535
1536 if (seg_desc.s) {
1537 /* mark segment as accessed */
1538 seg_desc.type |= 1;
7b105ca2 1539 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1540 if (ret != X86EMUL_CONTINUE)
1541 return ret;
e37a75a1
NA		 1542 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1543 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1544 sizeof(base3), &ctxt->exception);
1545 if (ret != X86EMUL_CONTINUE)
1546 return ret;
dde7e6d1
AK		 1547 }
1548load:
e37a75a1 1549 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1550 return X86EMUL_CONTINUE;
1551exception:
1552 emulate_exception(ctxt, err_vec, err_code, true);
1553 return X86EMUL_PROPAGATE_FAULT;
1554}
1555
2356aaeb
PB		 1556static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1557 u16 selector, int seg)
1558{
1559 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1560 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1561}
1562
31be40b3
WY		 1563static void write_register_operand(struct operand *op)
1564{
1565 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1566 switch (op->bytes) {
1567 case 1:
1568 *(u8 *)op->addr.reg = (u8)op->val;
1569 break;
1570 case 2:
1571 *(u16 *)op->addr.reg = (u16)op->val;
1572 break;
1573 case 4:
1574 *op->addr.reg = (u32)op->val;
1575 break; /* 64b: zero-extend */
1576 case 8:
1577 *op->addr.reg = op->val;
1578 break;
1579 }
1580}
1581
fb32b1ed 1582static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1583{
1584 int rc;
dde7e6d1 1585
fb32b1ed 1586 switch (op->type) {
dde7e6d1 1587 case OP_REG:
fb32b1ed 1588 write_register_operand(op);
6aa8b732 1589 break;
dde7e6d1 1590 case OP_MEM:
9dac77fa 1591 if (ctxt->lock_prefix)
3ca3ac4d 1592 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1593 op->addr.mem,
1594 &op->orig_val,
1595 &op->val,
1596 op->bytes);
341de7e3 1597 else
3ca3ac4d 1598 rc = segmented_write(ctxt,
fb32b1ed
AK		 1599 op->addr.mem,
1600 &op->val,
1601 op->bytes);
dde7e6d1
AK		 1602 if (rc != X86EMUL_CONTINUE)
1603 return rc;
a682e354 1604 break;
b3356bf0
GN		 1605 case OP_MEM_STR:
1606 rc = segmented_write(ctxt,
fb32b1ed
AK		 1607 op->addr.mem,
1608 op->data,
1609 op->bytes * op->count);
b3356bf0
GN		 1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
1612 break;
1253791d 1613 case OP_XMM:
fb32b1ed 1614 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1615 break;
cbe2c9d3 1616 case OP_MM:
fb32b1ed 1617 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1618 break;
dde7e6d1
AK		 1619 case OP_NONE:
1620 /* no writeback */
414e6277 1621 break;
dde7e6d1 1622 default:
414e6277 1623 break;
6aa8b732 1624 }
dde7e6d1
AK		 1625 return X86EMUL_CONTINUE;
1626}
6aa8b732 1627
51ddff50 1628static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1629{
4179bb02 1630 struct segmented_address addr;
0dc8d10f 1631
5ad105e5 1632 rsp_increment(ctxt, -bytes);
dd856efa 1633 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1634 addr.seg = VCPU_SREG_SS;
1635
51ddff50
AK		 1636 return segmented_write(ctxt, addr, data, bytes);
1637}
1638
1639static int em_push(struct x86_emulate_ctxt *ctxt)
1640{
4179bb02 1641 /* Disable writeback. */
9dac77fa 1642 ctxt->dst.type = OP_NONE;
51ddff50 1643 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1644}
69f55cb1 1645
dde7e6d1 1646static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1647 void *dest, int len)
1648{
dde7e6d1 1649 int rc;
90de84f5 1650 struct segmented_address addr;
8b4caf66 1651
dd856efa 1652 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1653 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1654 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1655 if (rc != X86EMUL_CONTINUE)
1656 return rc;
1657
5ad105e5 1658 rsp_increment(ctxt, len);
dde7e6d1 1659 return rc;
8b4caf66
LV		 1660}
1661
c54fe504
TY		 1662static int em_pop(struct x86_emulate_ctxt *ctxt)
1663{
9dac77fa 1664 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1665}
1666
dde7e6d1 1667static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1668 void *dest, int len)
9de41573
GN		 1669{
1670 int rc;
dde7e6d1
AK		 1671 unsigned long val, change_mask;
1672 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1673 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1674
3b9be3bf 1675 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1676 if (rc != X86EMUL_CONTINUE)
1677 return rc;
9de41573 1678
dde7e6d1
AK		 1679 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1680 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1681
dde7e6d1
AK		 1682 switch(ctxt->mode) {
1683 case X86EMUL_MODE_PROT64:
1684 case X86EMUL_MODE_PROT32:
1685 case X86EMUL_MODE_PROT16:
1686 if (cpl == 0)
1687 change_mask |= EFLG_IOPL;
1688 if (cpl <= iopl)
1689 change_mask |= EFLG_IF;
1690 break;
1691 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1692 if (iopl < 3)
1693 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1694 change_mask |= EFLG_IF;
1695 break;
1696 default: /* real mode */
1697 change_mask |= (EFLG_IOPL | EFLG_IF);
1698 break;
9de41573 1699 }
dde7e6d1
AK		 1700
1701 *(unsigned long *)dest =
1702 (ctxt->eflags & ~change_mask) | (val & change_mask);
1703
1704 return rc;
9de41573
GN		 1705}
1706
62aaa2f0
TY		 1707static int em_popf(struct x86_emulate_ctxt *ctxt)
1708{
9dac77fa
AK		 1709 ctxt->dst.type = OP_REG;
1710 ctxt->dst.addr.reg = &ctxt->eflags;
1711 ctxt->dst.bytes = ctxt->op_bytes;
1712 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1713}
1714
612e89f0
AK		 1715static int em_enter(struct x86_emulate_ctxt *ctxt)
1716{
1717 int rc;
1718 unsigned frame_size = ctxt->src.val;
1719 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1720 ulong rbp;
612e89f0
AK		 1721
1722 if (nesting_level)
1723 return X86EMUL_UNHANDLEABLE;
1724
dd856efa
AK		 1725 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1726 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1727 if (rc != X86EMUL_CONTINUE)
1728 return rc;
dd856efa 1729 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1730 stack_mask(ctxt));
dd856efa
AK		 1731 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1732 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1733 stack_mask(ctxt));
1734 return X86EMUL_CONTINUE;
1735}
1736
f47cfa31
AK		 1737static int em_leave(struct x86_emulate_ctxt *ctxt)
1738{
dd856efa 1739 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1740 stack_mask(ctxt));
dd856efa 1741 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1742}
1743
1cd196ea 1744static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1745{
1cd196ea
AK		 1746 int seg = ctxt->src2.val;
1747
9dac77fa 1748 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1749
4487b3b4 1750 return em_push(ctxt);
7b262e90
GN		 1751}
1752
1cd196ea 1753static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1754{
1cd196ea 1755 int seg = ctxt->src2.val;
dde7e6d1
AK		 1756 unsigned long selector;
1757 int rc;
38ba30ba 1758
9dac77fa 1759 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1760 if (rc != X86EMUL_CONTINUE)
1761 return rc;
1762
7b105ca2 1763 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1764 return rc;
38ba30ba
GN		 1765}
1766
b96a7fad 1767static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1768{
dd856efa 1769 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1770 int rc = X86EMUL_CONTINUE;
1771 int reg = VCPU_REGS_RAX;
38ba30ba 1772
dde7e6d1
AK		 1773 while (reg <= VCPU_REGS_RDI) {
1774 (reg == VCPU_REGS_RSP) ?
dd856efa 1775 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1776
4487b3b4 1777 rc = em_push(ctxt);
dde7e6d1
AK		 1778 if (rc != X86EMUL_CONTINUE)
1779 return rc;
38ba30ba 1780
dde7e6d1 1781 ++reg;
38ba30ba 1782 }
38ba30ba 1783
dde7e6d1 1784 return rc;
38ba30ba
GN		 1785}
1786
62aaa2f0
TY		 1787static int em_pushf(struct x86_emulate_ctxt *ctxt)
1788{
9dac77fa 1789 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1790 return em_push(ctxt);
1791}
1792
b96a7fad 1793static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1794{
dde7e6d1
AK		 1795 int rc = X86EMUL_CONTINUE;
1796 int reg = VCPU_REGS_RDI;
38ba30ba 1797
dde7e6d1
AK		 1798 while (reg >= VCPU_REGS_RAX) {
1799 if (reg == VCPU_REGS_RSP) {
5ad105e5 1800 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1801 --reg;
1802 }
38ba30ba 1803
dd856efa 1804 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1805 if (rc != X86EMUL_CONTINUE)
1806 break;
1807 --reg;
38ba30ba 1808 }
dde7e6d1 1809 return rc;
38ba30ba
GN		 1810}
1811
dd856efa 1812static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1813{
0225fb50 1814 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1815 int rc;
6e154e56
MG		 1816 struct desc_ptr dt;
1817 gva_t cs_addr;
1818 gva_t eip_addr;
1819 u16 cs, eip;
6e154e56
MG		 1820
1821 /* TODO: Add limit checks */
9dac77fa 1822 ctxt->src.val = ctxt->eflags;
4487b3b4 1823 rc = em_push(ctxt);
5c56e1cf
AK		 1824 if (rc != X86EMUL_CONTINUE)
1825 return rc;
6e154e56
MG		 1826
1827 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1828
9dac77fa 1829 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1830 rc = em_push(ctxt);
5c56e1cf
AK		 1831 if (rc != X86EMUL_CONTINUE)
1832 return rc;
6e154e56 1833
9dac77fa 1834 ctxt->src.val = ctxt->_eip;
4487b3b4 1835 rc = em_push(ctxt);
5c56e1cf
AK		 1836 if (rc != X86EMUL_CONTINUE)
1837 return rc;
1838
4bff1e86 1839 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1840
1841 eip_addr = dt.address + (irq << 2);
1842 cs_addr = dt.address + (irq << 2) + 2;
1843
0f65dd70 1844 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1845 if (rc != X86EMUL_CONTINUE)
1846 return rc;
1847
0f65dd70 1848 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1849 if (rc != X86EMUL_CONTINUE)
1850 return rc;
1851
7b105ca2 1852 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1853 if (rc != X86EMUL_CONTINUE)
1854 return rc;
1855
9dac77fa 1856 ctxt->_eip = eip;
6e154e56
MG		 1857
1858 return rc;
1859}
1860
dd856efa
AK		 1861int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1862{
1863 int rc;
1864
1865 invalidate_registers(ctxt);
1866 rc = __emulate_int_real(ctxt, irq);
1867 if (rc == X86EMUL_CONTINUE)
1868 writeback_registers(ctxt);
1869 return rc;
1870}
1871
7b105ca2 1872static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1873{
1874 switch(ctxt->mode) {
1875 case X86EMUL_MODE_REAL:
dd856efa 1876 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1877 case X86EMUL_MODE_VM86:
1878 case X86EMUL_MODE_PROT16:
1879 case X86EMUL_MODE_PROT32:
1880 case X86EMUL_MODE_PROT64:
1881 default:
1882 /* Protected mode interrupts unimplemented yet */
1883 return X86EMUL_UNHANDLEABLE;
1884 }
1885}
1886
7b105ca2 1887static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1888{
dde7e6d1
AK		 1889 int rc = X86EMUL_CONTINUE;
1890 unsigned long temp_eip = 0;
1891 unsigned long temp_eflags = 0;
1892 unsigned long cs = 0;
1893 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1894 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1895 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1896 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1897
dde7e6d1 1898 /* TODO: Add stack limit check */
38ba30ba 1899
9dac77fa 1900 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1901
dde7e6d1
AK		 1902 if (rc != X86EMUL_CONTINUE)
1903 return rc;
38ba30ba 1904
35d3d4a1
AK		 1905 if (temp_eip & ~0xffff)
1906 return emulate_gp(ctxt, 0);
38ba30ba 1907
9dac77fa 1908 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1909
dde7e6d1
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
38ba30ba 1912
9dac77fa 1913 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1914
dde7e6d1
AK		 1915 if (rc != X86EMUL_CONTINUE)
1916 return rc;
38ba30ba 1917
7b105ca2 1918 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1919
dde7e6d1
AK		 1920 if (rc != X86EMUL_CONTINUE)
1921 return rc;
38ba30ba 1922
9dac77fa 1923 ctxt->_eip = temp_eip;
38ba30ba 1924
38ba30ba 1925
9dac77fa 1926 if (ctxt->op_bytes == 4)
dde7e6d1 1927 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1928 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1929 ctxt->eflags &= ~0xffff;
1930 ctxt->eflags |= temp_eflags;
38ba30ba 1931 }
dde7e6d1
AK		 1932
1933 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1934 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1935
1936 return rc;
38ba30ba
GN		 1937}
1938
e01991e7 1939static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1940{
dde7e6d1
AK		 1941 switch(ctxt->mode) {
1942 case X86EMUL_MODE_REAL:
7b105ca2 1943 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1944 case X86EMUL_MODE_VM86:
1945 case X86EMUL_MODE_PROT16:
1946 case X86EMUL_MODE_PROT32:
1947 case X86EMUL_MODE_PROT64:
c37eda13 1948 default:
dde7e6d1
AK		 1949 /* iret from protected mode unimplemented yet */
1950 return X86EMUL_UNHANDLEABLE;
c37eda13 1951 }
c37eda13
WY		 1952}
1953
d2f62766
TY		 1954static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1955{
d2f62766
TY		 1956 int rc;
1957 unsigned short sel;
1958
9dac77fa 1959 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1960
7b105ca2 1961 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1962 if (rc != X86EMUL_CONTINUE)
1963 return rc;
1964
9dac77fa
AK		 1965 ctxt->_eip = 0;
1966 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1967 return X86EMUL_CONTINUE;
1968}
1969
51187683 1970static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1971{
4179bb02 1972 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1973
9dac77fa 1974 switch (ctxt->modrm_reg) {
d19292e4
MG		 1975 case 2: /* call near abs */ {
1976 long int old_eip;
9dac77fa
AK		 1977 old_eip = ctxt->_eip;
1978 ctxt->_eip = ctxt->src.val;
1979 ctxt->src.val = old_eip;
4487b3b4 1980 rc = em_push(ctxt);
d19292e4
MG		 1981 break;
1982 }
8cdbd2c9 1983 case 4: /* jmp abs */
9dac77fa 1984 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1985 break;
d2f62766
TY		 1986 case 5: /* jmp far */
1987 rc = em_jmp_far(ctxt);
1988 break;
8cdbd2c9 1989 case 6: /* push */
4487b3b4 1990 rc = em_push(ctxt);
8cdbd2c9 1991 break;
8cdbd2c9 1992 }
4179bb02 1993 return rc;
8cdbd2c9
LV		 1994}
1995
e0dac408 1996static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1997{
9dac77fa 1998 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1999
dd856efa
AK		 2000 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2001 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2002 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2003 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2004 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2005 } else {
dd856efa
AK		 2006 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2007 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2008
05f086f8 2009 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2010 }
1b30eaa8 2011 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2012}
2013
ebda02c2
TY		 2014static int em_ret(struct x86_emulate_ctxt *ctxt)
2015{
9dac77fa
AK		 2016 ctxt->dst.type = OP_REG;
2017 ctxt->dst.addr.reg = &ctxt->_eip;
2018 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2019 return em_pop(ctxt);
2020}
2021
e01991e7 2022static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2023{
a77ab5ea
AK		 2024 int rc;
2025 unsigned long cs;
2026
9dac77fa 2027 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2028 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2029 return rc;
9dac77fa
AK		 2030 if (ctxt->op_bytes == 4)
2031 ctxt->_eip = (u32)ctxt->_eip;
2032 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2033 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2034 return rc;
7b105ca2 2035 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2036 return rc;
2037}
2038
3261107e
BR		 2039static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2040{
2041 int rc;
2042
2043 rc = em_ret_far(ctxt);
2044 if (rc != X86EMUL_CONTINUE)
2045 return rc;
2046 rsp_increment(ctxt, ctxt->src.val);
2047 return X86EMUL_CONTINUE;
2048}
2049
e940b5c2
TY		 2050static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2051{
2052 /* Save real source value, then compare EAX against destination. */
2053 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2054 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2055 fastop(ctxt, em_cmp);
e940b5c2
TY		 2056
2057 if (ctxt->eflags & EFLG_ZF) {
2058 /* Success: write back to memory. */
2059 ctxt->dst.val = ctxt->src.orig_val;
2060 } else {
2061 /* Failure: write the value we saw to EAX. */
2062 ctxt->dst.type = OP_REG;
dd856efa 2063 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2064 }
2065 return X86EMUL_CONTINUE;
2066}
2067
d4b4325f 2068static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2069{
d4b4325f 2070 int seg = ctxt->src2.val;
09b5f4d3
WY		 2071 unsigned short sel;
2072 int rc;
2073
9dac77fa 2074 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2075
7b105ca2 2076 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2077 if (rc != X86EMUL_CONTINUE)
2078 return rc;
2079
9dac77fa 2080 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2081 return rc;
2082}
2083
7b105ca2 2084static void
e66bb2cc 2085setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2086 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2087{
e66bb2cc 2088 cs->l = 0; /* will be adjusted later */
79168fd1 2089 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2090 cs->g = 1; /* 4kb granularity */
79168fd1 2091 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2092 cs->type = 0x0b; /* Read, Execute, Accessed */
2093 cs->s = 1;
2094 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2095 cs->p = 1;
2096 cs->d = 1;
99245b50 2097 cs->avl = 0;
e66bb2cc 2098
79168fd1
GN		 2099 set_desc_base(ss, 0); /* flat segment */
2100 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2101 ss->g = 1; /* 4kb granularity */
2102 ss->s = 1;
2103 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2104 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2105 ss->dpl = 0;
79168fd1 2106 ss->p = 1;
99245b50
GN		 2107 ss->l = 0;
2108 ss->avl = 0;
e66bb2cc
AP		 2109}
2110
1a18a69b
AK		 2111static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2112{
2113 u32 eax, ebx, ecx, edx;
2114
2115 eax = ecx = 0;
0017f93a
AK		 2116 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2117 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2118 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2119 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2120}
2121
c2226fc9
SB		 2122static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2123{
0225fb50 2124 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2125 u32 eax, ebx, ecx, edx;
2126
2127 /*
2128 * syscall should always be enabled in longmode - so only become
2129 * vendor specific (cpuid) if other modes are active...
2130 */
2131 if (ctxt->mode == X86EMUL_MODE_PROT64)
2132 return true;
2133
2134 eax = 0x00000000;
2135 ecx = 0x00000000;
0017f93a
AK		 2136 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2137 /*
2138 * Intel ("GenuineIntel")
2139 * remark: Intel CPUs only support "syscall" in 64bit
2140 * longmode. Also an 64bit guest with a
2141 * 32bit compat-app running will #UD !! While this
2142 * behaviour can be fixed (by emulating) into AMD
2143 * response - CPUs of AMD can't behave like Intel.
2144 */
2145 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2146 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2147 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2148 return false;
2149
2150 /* AMD ("AuthenticAMD") */
2151 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2152 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2153 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2154 return true;
2155
2156 /* AMD ("AMDisbetter!") */
2157 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2158 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2159 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2160 return true;
c2226fc9
SB		 2161
2162 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2163 return false;
2164}
2165
e01991e7 2166static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2167{
0225fb50 2168 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2169 struct desc_struct cs, ss;
e66bb2cc 2170 u64 msr_data;
79168fd1 2171 u16 cs_sel, ss_sel;
c2ad2bb3 2172 u64 efer = 0;
e66bb2cc
AP		 2173
2174 /* syscall is not available in real mode */
2e901c4c 2175 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2176 ctxt->mode == X86EMUL_MODE_VM86)
2177 return emulate_ud(ctxt);
e66bb2cc 2178
c2226fc9
SB		 2179 if (!(em_syscall_is_enabled(ctxt)))
2180 return emulate_ud(ctxt);
2181
c2ad2bb3 2182 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2183 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2184
c2226fc9
SB		 2185 if (!(efer & EFER_SCE))
2186 return emulate_ud(ctxt);
2187
717746e3 2188 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2189 msr_data >>= 32;
79168fd1
GN		 2190 cs_sel = (u16)(msr_data & 0xfffc);
2191 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2192
c2ad2bb3 2193 if (efer & EFER_LMA) {
79168fd1 2194 cs.d = 0;
e66bb2cc
AP		 2195 cs.l = 1;
2196 }
1aa36616
AK		 2197 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2198 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2199
dd856efa 2200 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2201 if (efer & EFER_LMA) {
e66bb2cc 2202#ifdef CONFIG_X86_64
dd856efa 2203 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2204
717746e3 2205 ops->get_msr(ctxt,
3fb1b5db
GN		 2206 ctxt->mode == X86EMUL_MODE_PROT64 ?
2207 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2208 ctxt->_eip = msr_data;
e66bb2cc 2209
717746e3 2210 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2211 ctxt->eflags &= ~(msr_data | EFLG_RF);
2212#endif
2213 } else {
2214 /* legacy mode */
717746e3 2215 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2216 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2217
2218 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2219 }
2220
e54cfa97 2221 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2222}
2223
e01991e7 2224static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2225{
0225fb50 2226 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2227 struct desc_struct cs, ss;
8c604352 2228 u64 msr_data;
79168fd1 2229 u16 cs_sel, ss_sel;
c2ad2bb3 2230 u64 efer = 0;
8c604352 2231
7b105ca2 2232 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2233 /* inject #GP if in real mode */
35d3d4a1
AK		 2234 if (ctxt->mode == X86EMUL_MODE_REAL)
2235 return emulate_gp(ctxt, 0);
8c604352 2236
1a18a69b
AK		 2237 /*
2238 * Not recognized on AMD in compat mode (but is recognized in legacy
2239 * mode).
2240 */
2241 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2242 && !vendor_intel(ctxt))
2243 return emulate_ud(ctxt);
2244
8c604352
AP		 2245 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2246 * Therefore, we inject an #UD.
2247 */
35d3d4a1
AK		 2248 if (ctxt->mode == X86EMUL_MODE_PROT64)
2249 return emulate_ud(ctxt);
8c604352 2250
7b105ca2 2251 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2252
717746e3 2253 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2254 switch (ctxt->mode) {
2255 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2256 if ((msr_data & 0xfffc) == 0x0)
2257 return emulate_gp(ctxt, 0);
8c604352
AP		 2258 break;
2259 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2260 if (msr_data == 0x0)
2261 return emulate_gp(ctxt, 0);
8c604352 2262 break;
9d1b39a9
GN		 2263 default:
2264 break;
8c604352
AP		 2265 }
2266
2267 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2268 cs_sel = (u16)msr_data;
2269 cs_sel &= ~SELECTOR_RPL_MASK;
2270 ss_sel = cs_sel + 8;
2271 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2272 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2273 cs.d = 0;
8c604352
AP		 2274 cs.l = 1;
2275 }
2276
1aa36616
AK		 2277 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2278 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2279
717746e3 2280 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2281 ctxt->_eip = msr_data;
8c604352 2282
717746e3 2283 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2284 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2285
e54cfa97 2286 return X86EMUL_CONTINUE;
8c604352
AP		 2287}
2288
e01991e7 2289static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2290{
0225fb50 2291 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2292 struct desc_struct cs, ss;
4668f050
AP		 2293 u64 msr_data;
2294 int usermode;
1249b96e 2295 u16 cs_sel = 0, ss_sel = 0;
4668f050 2296
a0044755
GN		 2297 /* inject #GP if in real mode or Virtual 8086 mode */
2298 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2299 ctxt->mode == X86EMUL_MODE_VM86)
2300 return emulate_gp(ctxt, 0);
4668f050 2301
7b105ca2 2302 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2303
9dac77fa 2304 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2305 usermode = X86EMUL_MODE_PROT64;
2306 else
2307 usermode = X86EMUL_MODE_PROT32;
2308
2309 cs.dpl = 3;
2310 ss.dpl = 3;
717746e3 2311 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2312 switch (usermode) {
2313 case X86EMUL_MODE_PROT32:
79168fd1 2314 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2315 if ((msr_data & 0xfffc) == 0x0)
2316 return emulate_gp(ctxt, 0);
79168fd1 2317 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2318 break;
2319 case X86EMUL_MODE_PROT64:
79168fd1 2320 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2321 if (msr_data == 0x0)
2322 return emulate_gp(ctxt, 0);
79168fd1
GN		 2323 ss_sel = cs_sel + 8;
2324 cs.d = 0;
4668f050
AP		 2325 cs.l = 1;
2326 break;
2327 }
79168fd1
GN		 2328 cs_sel |= SELECTOR_RPL_MASK;
2329 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2330
1aa36616
AK		 2331 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2332 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2333
dd856efa
AK		 2334 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2335 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2336
e54cfa97 2337 return X86EMUL_CONTINUE;
4668f050
AP		 2338}
2339
7b105ca2 2340static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2341{
2342 int iopl;
2343 if (ctxt->mode == X86EMUL_MODE_REAL)
2344 return false;
2345 if (ctxt->mode == X86EMUL_MODE_VM86)
2346 return true;
2347 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2348 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2349}
2350
2351static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2352 u16 port, u16 len)
2353{
0225fb50 2354 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2355 struct desc_struct tr_seg;
5601d05b 2356 u32 base3;
f850e2e6 2357 int r;
1aa36616 2358 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2359 unsigned mask = (1 << len) - 1;
5601d05b 2360 unsigned long base;
f850e2e6 2361
1aa36616 2362 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2363 if (!tr_seg.p)
f850e2e6 2364 return false;
79168fd1 2365 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2366 return false;
5601d05b
GN		 2367 base = get_desc_base(&tr_seg);
2368#ifdef CONFIG_X86_64
2369 base |= ((u64)base3) << 32;
2370#endif
0f65dd70 2371 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2372 if (r != X86EMUL_CONTINUE)
2373 return false;
79168fd1 2374 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2375 return false;
0f65dd70 2376 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2377 if (r != X86EMUL_CONTINUE)
2378 return false;
2379 if ((perm >> bit_idx) & mask)
2380 return false;
2381 return true;
2382}
2383
2384static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2385 u16 port, u16 len)
2386{
4fc40f07
GN		 2387 if (ctxt->perm_ok)
2388 return true;
2389
7b105ca2
TY		 2390 if (emulator_bad_iopl(ctxt))
2391 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2392 return false;
4fc40f07
GN		 2393
2394 ctxt->perm_ok = true;
2395
f850e2e6
GN		 2396 return true;
2397}
2398
38ba30ba 2399static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2400 struct tss_segment_16 *tss)
2401{
9dac77fa 2402 tss->ip = ctxt->_eip;
38ba30ba 2403 tss->flag = ctxt->eflags;
dd856efa
AK		 2404 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2405 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2406 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2407 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2408 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2409 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2410 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2411 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2412
1aa36616
AK		 2413 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2414 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2415 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2416 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2417 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2418}
2419
2420static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2421 struct tss_segment_16 *tss)
2422{
38ba30ba 2423 int ret;
2356aaeb 2424 u8 cpl;
38ba30ba 2425
9dac77fa 2426 ctxt->_eip = tss->ip;
38ba30ba 2427 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2428 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2429 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2430 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2431 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2432 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2433 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2434 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2435 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2436
2437 /*
2438 * SDM says that segment selectors are loaded before segment
2439 * descriptors
2440 */
1aa36616
AK		 2441 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2442 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2443 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2444 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2445 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2446
2356aaeb
PB		 2447 cpl = tss->cs & 3;
2448
38ba30ba 2449 /*
fc058680 2450 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2451 * it is handled in a context of new task
2452 */
5045b468 2453 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2454 if (ret != X86EMUL_CONTINUE)
2455 return ret;
5045b468 2456 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2457 if (ret != X86EMUL_CONTINUE)
2458 return ret;
5045b468 2459 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2460 if (ret != X86EMUL_CONTINUE)
2461 return ret;
5045b468 2462 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2463 if (ret != X86EMUL_CONTINUE)
2464 return ret;
5045b468 2465 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2466 if (ret != X86EMUL_CONTINUE)
2467 return ret;
2468
2469 return X86EMUL_CONTINUE;
2470}
2471
2472static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2473 u16 tss_selector, u16 old_tss_sel,
2474 ulong old_tss_base, struct desc_struct *new_desc)
2475{
0225fb50 2476 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2477 struct tss_segment_16 tss_seg;
2478 int ret;
bcc55cba 2479 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2480
0f65dd70 2481 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2482 &ctxt->exception);
db297e3d 2483 if (ret != X86EMUL_CONTINUE)
38ba30ba 2484 /* FIXME: need to provide precise fault address */
38ba30ba 2485 return ret;
38ba30ba 2486
7b105ca2 2487 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2488
0f65dd70 2489 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2490 &ctxt->exception);
db297e3d 2491 if (ret != X86EMUL_CONTINUE)
38ba30ba 2492 /* FIXME: need to provide precise fault address */
38ba30ba 2493 return ret;
38ba30ba 2494
0f65dd70 2495 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2496 &ctxt->exception);
db297e3d 2497 if (ret != X86EMUL_CONTINUE)
38ba30ba 2498 /* FIXME: need to provide precise fault address */
38ba30ba 2499 return ret;
38ba30ba
GN		 2500
2501 if (old_tss_sel != 0xffff) {
2502 tss_seg.prev_task_link = old_tss_sel;
2503
0f65dd70 2504 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2505 &tss_seg.prev_task_link,
2506 sizeof tss_seg.prev_task_link,
0f65dd70 2507 &ctxt->exception);
db297e3d 2508 if (ret != X86EMUL_CONTINUE)
38ba30ba 2509 /* FIXME: need to provide precise fault address */
38ba30ba 2510 return ret;
38ba30ba
GN		 2511 }
2512
7b105ca2 2513 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2514}
2515
2516static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2517 struct tss_segment_32 *tss)
2518{
5c7411e2 2519 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2520 tss->eip = ctxt->_eip;
38ba30ba 2521 tss->eflags = ctxt->eflags;
dd856efa
AK		 2522 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2523 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2524 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2525 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2526 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2527 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2528 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2529 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2530
1aa36616
AK		 2531 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2532 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2533 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2534 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2535 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2536 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2537}
2538
2539static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2540 struct tss_segment_32 *tss)
2541{
38ba30ba 2542 int ret;
2356aaeb 2543 u8 cpl;
38ba30ba 2544
7b105ca2 2545 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2546 return emulate_gp(ctxt, 0);
9dac77fa 2547 ctxt->_eip = tss->eip;
38ba30ba 2548 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2549
2550 /* General purpose registers */
dd856efa
AK		 2551 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2552 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2553 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2554 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2555 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2556 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2557 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2558 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2559
2560 /*
2561 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2562 * descriptors. This is important because CPL checks will
2563 * use CS.RPL.
38ba30ba 2564 */
1aa36616
AK		 2565 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2566 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2567 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2568 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2569 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2570 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2571 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2572
4cee4798
KW		 2573 /*
2574 * If we're switching between Protected Mode and VM86, we need to make
2575 * sure to update the mode before loading the segment descriptors so
2576 * that the selectors are interpreted correctly.
4cee4798 2577 */
2356aaeb 2578 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2579 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2580 cpl = 3;
2581 } else {
4cee4798 2582 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2583 cpl = tss->cs & 3;
2584 }
4cee4798 2585
38ba30ba
GN		 2586 /*
2587 * Now load segment descriptors. If fault happenes at this stage
2588 * it is handled in a context of new task
2589 */
5045b468 2590 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
5045b468 2593 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2594 if (ret != X86EMUL_CONTINUE)
2595 return ret;
5045b468 2596 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2597 if (ret != X86EMUL_CONTINUE)
2598 return ret;
5045b468 2599 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2600 if (ret != X86EMUL_CONTINUE)
2601 return ret;
5045b468 2602 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2603 if (ret != X86EMUL_CONTINUE)
2604 return ret;
5045b468 2605 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2606 if (ret != X86EMUL_CONTINUE)
2607 return ret;
5045b468 2608 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2609 if (ret != X86EMUL_CONTINUE)
2610 return ret;
2611
2612 return X86EMUL_CONTINUE;
2613}
2614
2615static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2616 u16 tss_selector, u16 old_tss_sel,
2617 ulong old_tss_base, struct desc_struct *new_desc)
2618{
0225fb50 2619 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2620 struct tss_segment_32 tss_seg;
2621 int ret;
bcc55cba 2622 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2623 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2624 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2625
0f65dd70 2626 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2627 &ctxt->exception);
db297e3d 2628 if (ret != X86EMUL_CONTINUE)
38ba30ba 2629 /* FIXME: need to provide precise fault address */
38ba30ba 2630 return ret;
38ba30ba 2631
7b105ca2 2632 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2633
5c7411e2
NA		 2634 /* Only GP registers and segment selectors are saved */
2635 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2636 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2637 if (ret != X86EMUL_CONTINUE)
38ba30ba 2638 /* FIXME: need to provide precise fault address */
38ba30ba 2639 return ret;
38ba30ba 2640
0f65dd70 2641 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2642 &ctxt->exception);
db297e3d 2643 if (ret != X86EMUL_CONTINUE)
38ba30ba 2644 /* FIXME: need to provide precise fault address */
38ba30ba 2645 return ret;
38ba30ba
GN		 2646
2647 if (old_tss_sel != 0xffff) {
2648 tss_seg.prev_task_link = old_tss_sel;
2649
0f65dd70 2650 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2651 &tss_seg.prev_task_link,
2652 sizeof tss_seg.prev_task_link,
0f65dd70 2653 &ctxt->exception);
db297e3d 2654 if (ret != X86EMUL_CONTINUE)
38ba30ba 2655 /* FIXME: need to provide precise fault address */
38ba30ba 2656 return ret;
38ba30ba
GN		 2657 }
2658
7b105ca2 2659 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2660}
2661
2662static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2663 u16 tss_selector, int idt_index, int reason,
e269fb21 2664 bool has_error_code, u32 error_code)
38ba30ba 2665{
0225fb50 2666 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2667 struct desc_struct curr_tss_desc, next_tss_desc;
2668 int ret;
1aa36616 2669 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2670 ulong old_tss_base =
4bff1e86 2671 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2672 u32 desc_limit;
e919464b 2673 ulong desc_addr;
38ba30ba
GN		 2674
2675 /* FIXME: old_tss_base == ~0 ? */
2676
e919464b 2677 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2678 if (ret != X86EMUL_CONTINUE)
2679 return ret;
e919464b 2680 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2681 if (ret != X86EMUL_CONTINUE)
2682 return ret;
2683
2684 /* FIXME: check that next_tss_desc is tss */
2685
7f3d35fd
KW		 2686 /*
2687 * Check privileges. The three cases are task switch caused by...
2688 *
2689 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2690 * 2. Exception/IRQ/iret: No check is performed
fc058680 2691 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2692 */
2693 if (reason == TASK_SWITCH_GATE) {
2694 if (idt_index != -1) {
2695 /* Software interrupts */
2696 struct desc_struct task_gate_desc;
2697 int dpl;
2698
2699 ret = read_interrupt_descriptor(ctxt, idt_index,
2700 &task_gate_desc);
2701 if (ret != X86EMUL_CONTINUE)
2702 return ret;
2703
2704 dpl = task_gate_desc.dpl;
2705 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2706 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2707 }
2708 } else if (reason != TASK_SWITCH_IRET) {
2709 int dpl = next_tss_desc.dpl;
2710 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2711 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2712 }
2713
7f3d35fd 2714
ceffb459
GN		 2715 desc_limit = desc_limit_scaled(&next_tss_desc);
2716 if (!next_tss_desc.p ||
2717 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2718 desc_limit < 0x2b)) {
54b8486f 2719 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2720 return X86EMUL_PROPAGATE_FAULT;
2721 }
2722
2723 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2724 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2725 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2726 }
2727
2728 if (reason == TASK_SWITCH_IRET)
2729 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2730
2731 /* set back link to prev task only if NT bit is set in eflags
fc058680 2732 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2733 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2734 old_tss_sel = 0xffff;
2735
2736 if (next_tss_desc.type & 8)
7b105ca2 2737 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2738 old_tss_base, &next_tss_desc);
2739 else
7b105ca2 2740 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2741 old_tss_base, &next_tss_desc);
0760d448
JK		 2742 if (ret != X86EMUL_CONTINUE)
2743 return ret;
38ba30ba
GN		 2744
2745 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2746 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2747
2748 if (reason != TASK_SWITCH_IRET) {
2749 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2750 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2751 }
2752
717746e3 2753 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2754 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2755
e269fb21 2756 if (has_error_code) {
9dac77fa
AK		 2757 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2758 ctxt->lock_prefix = 0;
2759 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2760 ret = em_push(ctxt);
e269fb21
JK		 2761 }
2762
38ba30ba
GN		 2763 return ret;
2764}
2765
2766int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2767 u16 tss_selector, int idt_index, int reason,
e269fb21 2768 bool has_error_code, u32 error_code)
38ba30ba 2769{
38ba30ba
GN		 2770 int rc;
2771
dd856efa 2772 invalidate_registers(ctxt);
9dac77fa
AK		 2773 ctxt->_eip = ctxt->eip;
2774 ctxt->dst.type = OP_NONE;
38ba30ba 2775
7f3d35fd 2776 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2777 has_error_code, error_code);
38ba30ba 2778
dd856efa 2779 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2780 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2781 writeback_registers(ctxt);
2782 }
38ba30ba 2783
a0c0ab2f 2784 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2785}
2786
f3bd64c6
GN		 2787static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2788 struct operand *op)
a682e354 2789{
b3356bf0 2790 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2791
dd856efa
AK		 2792 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2793 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2794}
2795
7af04fc0
AK		 2796static int em_das(struct x86_emulate_ctxt *ctxt)
2797{
7af04fc0
AK		 2798 u8 al, old_al;
2799 bool af, cf, old_cf;
2800
2801 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2802 al = ctxt->dst.val;
7af04fc0
AK		 2803
2804 old_al = al;
2805 old_cf = cf;
2806 cf = false;
2807 af = ctxt->eflags & X86_EFLAGS_AF;
2808 if ((al & 0x0f) > 9 || af) {
2809 al -= 6;
2810 cf = old_cf | (al >= 250);
2811 af = true;
2812 } else {
2813 af = false;
2814 }
2815 if (old_al > 0x99 || old_cf) {
2816 al -= 0x60;
2817 cf = true;
2818 }
2819
9dac77fa 2820 ctxt->dst.val = al;
7af04fc0 2821 /* Set PF, ZF, SF */
9dac77fa
AK		 2822 ctxt->src.type = OP_IMM;
2823 ctxt->src.val = 0;
2824 ctxt->src.bytes = 1;
158de57f 2825 fastop(ctxt, em_or);
7af04fc0
AK		 2826 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2827 if (cf)
2828 ctxt->eflags |= X86_EFLAGS_CF;
2829 if (af)
2830 ctxt->eflags |= X86_EFLAGS_AF;
2831 return X86EMUL_CONTINUE;
2832}
2833
a035d5c6
PB		 2834static int em_aam(struct x86_emulate_ctxt *ctxt)
2835{
2836 u8 al, ah;
2837
2838 if (ctxt->src.val == 0)
2839 return emulate_de(ctxt);
2840
2841 al = ctxt->dst.val & 0xff;
2842 ah = al / ctxt->src.val;
2843 al %= ctxt->src.val;
2844
2845 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2846
2847 /* Set PF, ZF, SF */
2848 ctxt->src.type = OP_IMM;
2849 ctxt->src.val = 0;
2850 ctxt->src.bytes = 1;
2851 fastop(ctxt, em_or);
2852
2853 return X86EMUL_CONTINUE;
2854}
2855
7f662273
GN		 2856static int em_aad(struct x86_emulate_ctxt *ctxt)
2857{
2858 u8 al = ctxt->dst.val & 0xff;
2859 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2860
2861 al = (al + (ah * ctxt->src.val)) & 0xff;
2862
2863 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2864
f583c29b
GN		 2865 /* Set PF, ZF, SF */
2866 ctxt->src.type = OP_IMM;
2867 ctxt->src.val = 0;
2868 ctxt->src.bytes = 1;
2869 fastop(ctxt, em_or);
7f662273
GN		 2870
2871 return X86EMUL_CONTINUE;
2872}
2873
d4ddafcd
TY		 2874static int em_call(struct x86_emulate_ctxt *ctxt)
2875{
2876 long rel = ctxt->src.val;
2877
2878 ctxt->src.val = (unsigned long)ctxt->_eip;
2879 jmp_rel(ctxt, rel);
2880 return em_push(ctxt);
2881}
2882
0ef753b8
AK		 2883static int em_call_far(struct x86_emulate_ctxt *ctxt)
2884{
0ef753b8
AK		 2885 u16 sel, old_cs;
2886 ulong old_eip;
2887 int rc;
2888
1aa36616 2889 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2890 old_eip = ctxt->_eip;
0ef753b8 2891
9dac77fa 2892 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2893 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2894 return X86EMUL_CONTINUE;
2895
9dac77fa
AK		 2896 ctxt->_eip = 0;
2897 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2898
9dac77fa 2899 ctxt->src.val = old_cs;
4487b3b4 2900 rc = em_push(ctxt);
0ef753b8
AK		 2901 if (rc != X86EMUL_CONTINUE)
2902 return rc;
2903
9dac77fa 2904 ctxt->src.val = old_eip;
4487b3b4 2905 return em_push(ctxt);
0ef753b8
AK		 2906}
2907
40ece7c7
AK		 2908static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2909{
40ece7c7
AK		 2910 int rc;
2911
9dac77fa
AK		 2912 ctxt->dst.type = OP_REG;
2913 ctxt->dst.addr.reg = &ctxt->_eip;
2914 ctxt->dst.bytes = ctxt->op_bytes;
2915 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2916 if (rc != X86EMUL_CONTINUE)
2917 return rc;
5ad105e5 2918 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2919 return X86EMUL_CONTINUE;
2920}
2921
e4f973ae
TY		 2922static int em_xchg(struct x86_emulate_ctxt *ctxt)
2923{
e4f973ae 2924 /* Write back the register source. */
9dac77fa
AK		 2925 ctxt->src.val = ctxt->dst.val;
2926 write_register_operand(&ctxt->src);
e4f973ae
TY		 2927
2928 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2929 ctxt->dst.val = ctxt->src.orig_val;
2930 ctxt->lock_prefix = 1;
e4f973ae
TY		 2931 return X86EMUL_CONTINUE;
2932}
2933
5c82aa29
AK		 2934static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2935{
9dac77fa 2936 ctxt->dst.val = ctxt->src2.val;
4d758349 2937 return fastop(ctxt, em_imul);
5c82aa29
AK		 2938}
2939
61429142
AK		 2940static int em_cwd(struct x86_emulate_ctxt *ctxt)
2941{
9dac77fa
AK		 2942 ctxt->dst.type = OP_REG;
2943 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2944 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2945 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2946
2947 return X86EMUL_CONTINUE;
2948}
2949
48bb5d3c
AK		 2950static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2951{
48bb5d3c
AK		 2952 u64 tsc = 0;
2953
717746e3 2954 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2955 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2956 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2957 return X86EMUL_CONTINUE;
2958}
2959
222d21aa
AK		 2960static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2961{
2962 u64 pmc;
2963
dd856efa 2964 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2965 return emulate_gp(ctxt, 0);
dd856efa
AK		 2966 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2967 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2968 return X86EMUL_CONTINUE;
2969}
2970
b9eac5f4
AK		 2971static int em_mov(struct x86_emulate_ctxt *ctxt)
2972{
49597d81 2973 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2974 return X86EMUL_CONTINUE;
2975}
2976
84cffe49
BP		 2977#define FFL(x) bit(X86_FEATURE_##x)
2978
2979static int em_movbe(struct x86_emulate_ctxt *ctxt)
2980{
2981 u32 ebx, ecx, edx, eax = 1;
2982 u16 tmp;
2983
2984 /*
2985 * Check MOVBE is set in the guest-visible CPUID leaf.
2986 */
2987 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2988 if (!(ecx & FFL(MOVBE)))
2989 return emulate_ud(ctxt);
2990
2991 switch (ctxt->op_bytes) {
2992 case 2:
2993 /*
2994 * From MOVBE definition: "...When the operand size is 16 bits,
2995 * the upper word of the destination register remains unchanged
2996 * ..."
2997 *
2998 * Both casting ->valptr and ->val to u16 breaks strict aliasing
2999 * rules so we have to do the operation almost per hand.
3000 */
3001 tmp = (u16)ctxt->src.val;
3002 ctxt->dst.val &= ~0xffffUL;
3003 ctxt->dst.val |= (unsigned long)swab16(tmp);
3004 break;
3005 case 4:
3006 ctxt->dst.val = swab32((u32)ctxt->src.val);
3007 break;
3008 case 8:
3009 ctxt->dst.val = swab64(ctxt->src.val);
3010 break;
3011 default:
3012 return X86EMUL_PROPAGATE_FAULT;
3013 }
3014 return X86EMUL_CONTINUE;
3015}
3016
bc00f8d2
TY		 3017static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3018{
3019 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3020 return emulate_gp(ctxt, 0);
3021
3022 /* Disable writeback. */
3023 ctxt->dst.type = OP_NONE;
3024 return X86EMUL_CONTINUE;
3025}
3026
3027static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3028{
3029 unsigned long val;
3030
3031 if (ctxt->mode == X86EMUL_MODE_PROT64)
3032 val = ctxt->src.val & ~0ULL;
3033 else
3034 val = ctxt->src.val & ~0U;
3035
3036 /* #UD condition is already handled. */
3037 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3038 return emulate_gp(ctxt, 0);
3039
3040 /* Disable writeback. */
3041 ctxt->dst.type = OP_NONE;
3042 return X86EMUL_CONTINUE;
3043}
3044
e1e210b0
TY		 3045static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3046{
3047 u64 msr_data;
3048
dd856efa
AK		 3049 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3050 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3051 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3052 return emulate_gp(ctxt, 0);
3053
3054 return X86EMUL_CONTINUE;
3055}
3056
3057static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3058{
3059 u64 msr_data;
3060
dd856efa 3061 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3062 return emulate_gp(ctxt, 0);
3063
dd856efa
AK		 3064 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3065 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3066 return X86EMUL_CONTINUE;
3067}
3068
1bd5f469
TY		 3069static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3070{
9dac77fa 3071 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3072 return emulate_ud(ctxt);
3073
9dac77fa 3074 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3075 return X86EMUL_CONTINUE;
3076}
3077
3078static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3079{
9dac77fa 3080 u16 sel = ctxt->src.val;
1bd5f469 3081
9dac77fa 3082 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3083 return emulate_ud(ctxt);
3084
9dac77fa 3085 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3086 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3087
3088 /* Disable writeback. */
9dac77fa
AK		 3089 ctxt->dst.type = OP_NONE;
3090 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3091}
3092
a14e579f
AK		 3093static int em_lldt(struct x86_emulate_ctxt *ctxt)
3094{
3095 u16 sel = ctxt->src.val;
3096
3097 /* Disable writeback. */
3098 ctxt->dst.type = OP_NONE;
3099 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3100}
3101
80890006
AK		 3102static int em_ltr(struct x86_emulate_ctxt *ctxt)
3103{
3104 u16 sel = ctxt->src.val;
3105
3106 /* Disable writeback. */
3107 ctxt->dst.type = OP_NONE;
3108 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3109}
3110
38503911
AK		 3111static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3112{
9fa088f4
AK		 3113 int rc;
3114 ulong linear;
3115
9dac77fa 3116 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3117 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3118 ctxt->ops->invlpg(ctxt, linear);
38503911 3119 /* Disable writeback. */
9dac77fa 3120 ctxt->dst.type = OP_NONE;
38503911
AK		 3121 return X86EMUL_CONTINUE;
3122}
3123
2d04a05b
AK		 3124static int em_clts(struct x86_emulate_ctxt *ctxt)
3125{
3126 ulong cr0;
3127
3128 cr0 = ctxt->ops->get_cr(ctxt, 0);
3129 cr0 &= ~X86_CR0_TS;
3130 ctxt->ops->set_cr(ctxt, 0, cr0);
3131 return X86EMUL_CONTINUE;
3132}
3133
26d05cc7
AK		 3134static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3135{
26d05cc7
AK		 3136 int rc;
3137
9dac77fa 3138 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3139 return X86EMUL_UNHANDLEABLE;
3140
3141 rc = ctxt->ops->fix_hypercall(ctxt);
3142 if (rc != X86EMUL_CONTINUE)
3143 return rc;
3144
3145 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3146 ctxt->_eip = ctxt->eip;
26d05cc7 3147 /* Disable writeback. */
9dac77fa 3148 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3149 return X86EMUL_CONTINUE;
3150}
3151
96051572
AK		 3152static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3153 void (*get)(struct x86_emulate_ctxt *ctxt,
3154 struct desc_ptr *ptr))
3155{
3156 struct desc_ptr desc_ptr;
3157
3158 if (ctxt->mode == X86EMUL_MODE_PROT64)
3159 ctxt->op_bytes = 8;
3160 get(ctxt, &desc_ptr);
3161 if (ctxt->op_bytes == 2) {
3162 ctxt->op_bytes = 4;
3163 desc_ptr.address &= 0x00ffffff;
3164 }
3165 /* Disable writeback. */
3166 ctxt->dst.type = OP_NONE;
3167 return segmented_write(ctxt, ctxt->dst.addr.mem,
3168 &desc_ptr, 2 + ctxt->op_bytes);
3169}
3170
3171static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3172{
3173 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3174}
3175
3176static int em_sidt(struct x86_emulate_ctxt *ctxt)
3177{
3178 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3179}
3180
26d05cc7
AK		 3181static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3182{
26d05cc7
AK		 3183 struct desc_ptr desc_ptr;
3184 int rc;
3185
510425ff
AK		 3186 if (ctxt->mode == X86EMUL_MODE_PROT64)
3187 ctxt->op_bytes = 8;
9dac77fa 3188 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3189 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3190 ctxt->op_bytes);
26d05cc7
AK		 3191 if (rc != X86EMUL_CONTINUE)
3192 return rc;
3193 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3194 /* Disable writeback. */
9dac77fa 3195 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3196 return X86EMUL_CONTINUE;
3197}
3198
5ef39c71 3199static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3200{
26d05cc7
AK		 3201 int rc;
3202
5ef39c71
AK		 3203 rc = ctxt->ops->fix_hypercall(ctxt);
3204
26d05cc7 3205 /* Disable writeback. */
9dac77fa 3206 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3207 return rc;
3208}
3209
3210static int em_lidt(struct x86_emulate_ctxt *ctxt)
3211{
26d05cc7
AK		 3212 struct desc_ptr desc_ptr;
3213 int rc;
3214
510425ff
AK		 3215 if (ctxt->mode == X86EMUL_MODE_PROT64)
3216 ctxt->op_bytes = 8;
9dac77fa 3217 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3218 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3219 ctxt->op_bytes);
26d05cc7
AK		 3220 if (rc != X86EMUL_CONTINUE)
3221 return rc;
3222 ctxt->ops->set_idt(ctxt, &desc_ptr);
3223 /* Disable writeback. */
9dac77fa 3224 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_smsw(struct x86_emulate_ctxt *ctxt)
3229{
9dac77fa
AK		 3230 ctxt->dst.bytes = 2;
3231 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3232 return X86EMUL_CONTINUE;
3233}
3234
3235static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3236{
26d05cc7 3237 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3238 | (ctxt->src.val & 0x0f));
3239 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3240 return X86EMUL_CONTINUE;
3241}
3242
d06e03ad
TY		 3243static int em_loop(struct x86_emulate_ctxt *ctxt)
3244{
dd856efa
AK		 3245 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3246 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3247 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3248 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3249
3250 return X86EMUL_CONTINUE;
3251}
3252
3253static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3254{
dd856efa 3255 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3256 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3257
3258 return X86EMUL_CONTINUE;
3259}
3260
d7841a4b
TY		 3261static int em_in(struct x86_emulate_ctxt *ctxt)
3262{
3263 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3264 &ctxt->dst.val))
3265 return X86EMUL_IO_NEEDED;
3266
3267 return X86EMUL_CONTINUE;
3268}
3269
3270static int em_out(struct x86_emulate_ctxt *ctxt)
3271{
3272 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3273 &ctxt->src.val, 1);
3274 /* Disable writeback. */
3275 ctxt->dst.type = OP_NONE;
3276 return X86EMUL_CONTINUE;
3277}
3278
f411e6cd
TY		 3279static int em_cli(struct x86_emulate_ctxt *ctxt)
3280{
3281 if (emulator_bad_iopl(ctxt))
3282 return emulate_gp(ctxt, 0);
3283
3284 ctxt->eflags &= ~X86_EFLAGS_IF;
3285 return X86EMUL_CONTINUE;
3286}
3287
3288static int em_sti(struct x86_emulate_ctxt *ctxt)
3289{
3290 if (emulator_bad_iopl(ctxt))
3291 return emulate_gp(ctxt, 0);
3292
3293 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3294 ctxt->eflags |= X86_EFLAGS_IF;
3295 return X86EMUL_CONTINUE;
3296}
3297
6d6eede4
AK		 3298static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3299{
3300 u32 eax, ebx, ecx, edx;
3301
dd856efa
AK		 3302 eax = reg_read(ctxt, VCPU_REGS_RAX);
3303 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3304 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3305 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3306 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3307 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3308 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3309 return X86EMUL_CONTINUE;
3310}
3311
98f73630
PB		 3312static int em_sahf(struct x86_emulate_ctxt *ctxt)
3313{
3314 u32 flags;
3315
3316 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3317 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3318
3319 ctxt->eflags &= ~0xffUL;
3320 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3321 return X86EMUL_CONTINUE;
3322}
3323
2dd7caa0
AK		 3324static int em_lahf(struct x86_emulate_ctxt *ctxt)
3325{
dd856efa
AK		 3326 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3327 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3328 return X86EMUL_CONTINUE;
3329}
3330
9299836e
AK		 3331static int em_bswap(struct x86_emulate_ctxt *ctxt)
3332{
3333 switch (ctxt->op_bytes) {
3334#ifdef CONFIG_X86_64
3335 case 8:
3336 asm("bswap %0" : "+r"(ctxt->dst.val));
3337 break;
3338#endif
3339 default:
3340 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3341 break;
3342 }
3343 return X86EMUL_CONTINUE;
3344}
3345
cfec82cb
JR		 3346static bool valid_cr(int nr)
3347{
3348 switch (nr) {
3349 case 0:
3350 case 2 ... 4:
3351 case 8:
3352 return true;
3353 default:
3354 return false;
3355 }
3356}
3357
3358static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3359{
9dac77fa 3360 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3361 return emulate_ud(ctxt);
3362
3363 return X86EMUL_CONTINUE;
3364}
3365
3366static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3367{
9dac77fa
AK		 3368 u64 new_val = ctxt->src.val64;
3369 int cr = ctxt->modrm_reg;
c2ad2bb3 3370 u64 efer = 0;
cfec82cb
JR		 3371
3372 static u64 cr_reserved_bits[] = {
3373 0xffffffff00000000ULL,
3374 0, 0, 0, /* CR3 checked later */
3375 CR4_RESERVED_BITS,
3376 0, 0, 0,
3377 CR8_RESERVED_BITS,
3378 };
3379
3380 if (!valid_cr(cr))
3381 return emulate_ud(ctxt);
3382
3383 if (new_val & cr_reserved_bits[cr])
3384 return emulate_gp(ctxt, 0);
3385
3386 switch (cr) {
3387 case 0: {
c2ad2bb3 3388 u64 cr4;
cfec82cb
JR		 3389 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3390 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3391 return emulate_gp(ctxt, 0);
3392
717746e3
AK		 3393 cr4 = ctxt->ops->get_cr(ctxt, 4);
3394 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3395
3396 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3397 !(cr4 & X86_CR4_PAE))
3398 return emulate_gp(ctxt, 0);
3399
3400 break;
3401 }
3402 case 3: {
3403 u64 rsvd = 0;
3404
c2ad2bb3
AK		 3405 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3406 if (efer & EFER_LMA)
cfec82cb 3407 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3408
3409 if (new_val & rsvd)
3410 return emulate_gp(ctxt, 0);
3411
3412 break;
3413 }
3414 case 4: {
717746e3 3415 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3416
3417 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3418 return emulate_gp(ctxt, 0);
3419
3420 break;
3421 }
3422 }
3423
3424 return X86EMUL_CONTINUE;
3425}
3426
3b88e41a
JR		 3427static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3428{
3429 unsigned long dr7;
3430
717746e3 3431 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3432
3433 /* Check if DR7.Global_Enable is set */
3434 return dr7 & (1 << 13);
3435}
3436
3437static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3438{
9dac77fa 3439 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3440 u64 cr4;
3441
3442 if (dr > 7)
3443 return emulate_ud(ctxt);
3444
717746e3 3445 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3446 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3447 return emulate_ud(ctxt);
3448
3449 if (check_dr7_gd(ctxt))
3450 return emulate_db(ctxt);
3451
3452 return X86EMUL_CONTINUE;
3453}
3454
3455static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3456{
9dac77fa
AK		 3457 u64 new_val = ctxt->src.val64;
3458 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3459
3460 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3461 return emulate_gp(ctxt, 0);
3462
3463 return check_dr_read(ctxt);
3464}
3465
01de8b09
JR		 3466static int check_svme(struct x86_emulate_ctxt *ctxt)
3467{
3468 u64 efer;
3469
717746e3 3470 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3471
3472 if (!(efer & EFER_SVME))
3473 return emulate_ud(ctxt);
3474
3475 return X86EMUL_CONTINUE;
3476}
3477
3478static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3479{
dd856efa 3480 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3481
3482 /* Valid physical address? */
d4224449 3483 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3484 return emulate_gp(ctxt, 0);
3485
3486 return check_svme(ctxt);
3487}
3488
d7eb8203
JR		 3489static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3490{
717746e3 3491 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3492
717746e3 3493 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3494 return emulate_ud(ctxt);
3495
3496 return X86EMUL_CONTINUE;
3497}
3498
8061252e
JR		 3499static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3500{
717746e3 3501 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3502 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3503
717746e3 3504 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3505 (rcx > 3))
3506 return emulate_gp(ctxt, 0);
3507
3508 return X86EMUL_CONTINUE;
3509}
3510
f6511935
JR		 3511static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3512{
9dac77fa
AK		 3513 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3514 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3515 return emulate_gp(ctxt, 0);
3516
3517 return X86EMUL_CONTINUE;
3518}
3519
3520static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3521{
9dac77fa
AK		 3522 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3523 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3524 return emulate_gp(ctxt, 0);
3525
3526 return X86EMUL_CONTINUE;
3527}
3528
73fba5f4 3529#define D(_y) { .flags = (_y) }
c4f035c6 3530#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3531#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3532 .check_perm = (_p) }
0b789eee 3533#define N D(NotImpl)
01de8b09 3534#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3535#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3536#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3537#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3538#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3539#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3540#define II(_f, _e, _i) \
3541 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3542#define IIP(_f, _e, _i, _p) \
3543 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3544 .check_perm = (_p) }
aa97bb48 3545#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3546
8d8f4e9f 3547#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3548#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3549#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3550#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3551#define I2bvIP(_f, _e, _i, _p) \
3552 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3553
fb864fbc
AK		 3554#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3555 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3556 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3557
fd0a0d82 3558static const struct opcode group7_rm1[] = {
1c2545be
TY		 3559 DI(SrcNone | Priv, monitor),
3560 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3561 N, N, N, N, N, N,
3562};
3563
fd0a0d82 3564static const struct opcode group7_rm3[] = {
1c2545be 3565 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3566 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3567 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3568 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3569 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3570 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3571 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3572 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3573};
6230f7fc 3574
fd0a0d82 3575static const struct opcode group7_rm7[] = {
d7eb8203 3576 N,
1c2545be 3577 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3578 N, N, N, N, N, N,
3579};
d67fc27a 3580
fd0a0d82 3581static const struct opcode group1[] = {
fb864fbc
AK		 3582 F(Lock, em_add),
3583 F(Lock | PageTable, em_or),
3584 F(Lock, em_adc),
3585 F(Lock, em_sbb),
3586 F(Lock | PageTable, em_and),
3587 F(Lock, em_sub),
3588 F(Lock, em_xor),
3589 F(NoWrite, em_cmp),
73fba5f4
AK		 3590};
3591
fd0a0d82 3592static const struct opcode group1A[] = {
1c2545be 3593 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3594};
3595
007a3b54
AK		 3596static const struct opcode group2[] = {
3597 F(DstMem | ModRM, em_rol),
3598 F(DstMem | ModRM, em_ror),
3599 F(DstMem | ModRM, em_rcl),
3600 F(DstMem | ModRM, em_rcr),
3601 F(DstMem | ModRM, em_shl),
3602 F(DstMem | ModRM, em_shr),
3603 F(DstMem | ModRM, em_shl),
3604 F(DstMem | ModRM, em_sar),
3605};
3606
fd0a0d82 3607static const struct opcode group3[] = {
fb864fbc
AK		 3608 F(DstMem | SrcImm | NoWrite, em_test),
3609 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3610 F(DstMem | SrcNone | Lock, em_not),
3611 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3612 F(DstXacc | Src2Mem, em_mul_ex),
3613 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3614 F(DstXacc | Src2Mem, em_div_ex),
3615 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3616};
3617
fd0a0d82 3618static const struct opcode group4[] = {
95413dc4
AK		 3619 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3620 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3621 N, N, N, N, N, N,
3622};
3623
fd0a0d82 3624static const struct opcode group5[] = {
95413dc4
AK		 3625 F(DstMem | SrcNone | Lock, em_inc),
3626 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3627 I(SrcMem | Stack, em_grp45),
3628 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3629 I(SrcMem | Stack, em_grp45),
3630 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3631 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3632};
3633
fd0a0d82 3634static const struct opcode group6[] = {
1c2545be
TY		 3635 DI(Prot, sldt),
3636 DI(Prot, str),
a14e579f 3637 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3638 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3639 N, N, N, N,
3640};
3641
fd0a0d82 3642static const struct group_dual group7 = { {
96051572
AK		 3643 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3644 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3645 II(SrcMem | Priv, em_lgdt, lgdt),
3646 II(SrcMem | Priv, em_lidt, lidt),
3647 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3648 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3649 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3650}, {
b51e974f 3651 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3652 EXT(0, group7_rm1),
01de8b09 3653 N, EXT(0, group7_rm3),
1c2545be
TY		 3654 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3655 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3656 EXT(0, group7_rm7),
73fba5f4
AK		 3657} };
3658
fd0a0d82 3659static const struct opcode group8[] = {
73fba5f4 3660 N, N, N, N,
11c363ba
AK		 3661 F(DstMem | SrcImmByte | NoWrite, em_bt),
3662 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3663 F(DstMem | SrcImmByte | Lock, em_btr),
3664 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3665};
3666
fd0a0d82 3667static const struct group_dual group9 = { {
1c2545be 3668 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3669}, {
3670 N, N, N, N, N, N, N, N,
3671} };
3672
fd0a0d82 3673static const struct opcode group11[] = {
1c2545be 3674 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3675 X7(D(Undefined)),
a4d4a7c1
AK		 3676};
3677
fd0a0d82 3678static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3679 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3680};
3681
fd0a0d82 3682static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3683 I(0, em_mov), N, N, N,
3684};
3685
27ce8258 3686static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3687 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3688};
3689
045a282c
GN		 3690static const struct escape escape_d9 = { {
3691 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3692}, {
3693 /* 0xC0 - 0xC7 */
3694 N, N, N, N, N, N, N, N,
3695 /* 0xC8 - 0xCF */
3696 N, N, N, N, N, N, N, N,
3697 /* 0xD0 - 0xC7 */
3698 N, N, N, N, N, N, N, N,
3699 /* 0xD8 - 0xDF */
3700 N, N, N, N, N, N, N, N,
3701 /* 0xE0 - 0xE7 */
3702 N, N, N, N, N, N, N, N,
3703 /* 0xE8 - 0xEF */
3704 N, N, N, N, N, N, N, N,
3705 /* 0xF0 - 0xF7 */
3706 N, N, N, N, N, N, N, N,
3707 /* 0xF8 - 0xFF */
3708 N, N, N, N, N, N, N, N,
3709} };
3710
3711static const struct escape escape_db = { {
3712 N, N, N, N, N, N, N, N,
3713}, {
3714 /* 0xC0 - 0xC7 */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xC8 - 0xCF */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xD0 - 0xC7 */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xD8 - 0xDF */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xE0 - 0xE7 */
3723 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3724 /* 0xE8 - 0xEF */
3725 N, N, N, N, N, N, N, N,
3726 /* 0xF0 - 0xF7 */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xF8 - 0xFF */
3729 N, N, N, N, N, N, N, N,
3730} };
3731
3732static const struct escape escape_dd = { {
3733 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3734}, {
3735 /* 0xC0 - 0xC7 */
3736 N, N, N, N, N, N, N, N,
3737 /* 0xC8 - 0xCF */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xD0 - 0xC7 */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xD8 - 0xDF */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xE0 - 0xE7 */
3744 N, N, N, N, N, N, N, N,
3745 /* 0xE8 - 0xEF */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xF0 - 0xF7 */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xF8 - 0xFF */
3750 N, N, N, N, N, N, N, N,
3751} };
3752
fd0a0d82 3753static const struct opcode opcode_table[256] = {
73fba5f4 3754 /* 0x00 - 0x07 */
fb864fbc 3755 F6ALU(Lock, em_add),
1cd196ea
AK		 3756 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3757 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3758 /* 0x08 - 0x0F */
fb864fbc 3759 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3760 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3761 N,
73fba5f4 3762 /* 0x10 - 0x17 */
fb864fbc 3763 F6ALU(Lock, em_adc),
1cd196ea
AK		 3764 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3765 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3766 /* 0x18 - 0x1F */
fb864fbc 3767 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3768 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3769 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3770 /* 0x20 - 0x27 */
fb864fbc 3771 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3772 /* 0x28 - 0x2F */
fb864fbc 3773 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3774 /* 0x30 - 0x37 */
fb864fbc 3775 F6ALU(Lock, em_xor), N, N,
73fba5f4 3776 /* 0x38 - 0x3F */
fb864fbc 3777 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3778 /* 0x40 - 0x4F */
95413dc4 3779 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3780 /* 0x50 - 0x57 */
63540382 3781 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3782 /* 0x58 - 0x5F */
c54fe504 3783 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3784 /* 0x60 - 0x67 */
b96a7fad
TY		 3785 I(ImplicitOps | Stack | No64, em_pusha),
3786 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3787 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3788 N, N, N, N,
3789 /* 0x68 - 0x6F */
d46164db
AK		 3790 I(SrcImm | Mov | Stack, em_push),
3791 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3792 I(SrcImmByte | Mov | Stack, em_push),
3793 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3794 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3795 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3796 /* 0x70 - 0x7F */
3797 X16(D(SrcImmByte)),
3798 /* 0x80 - 0x87 */
1c2545be
TY		 3799 G(ByteOp | DstMem | SrcImm, group1),
3800 G(DstMem | SrcImm, group1),
3801 G(ByteOp | DstMem | SrcImm | No64, group1),
3802 G(DstMem | SrcImmByte, group1),
fb864fbc 3803 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3804 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3805 /* 0x88 - 0x8F */
d5ae7ce8 3806 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3807 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3808 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3809 D(ModRM | SrcMem | NoAccess | DstReg),
3810 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3811 G(0, group1A),
73fba5f4 3812 /* 0x90 - 0x97 */
bf608f88 3813 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3814 /* 0x98 - 0x9F */
61429142 3815 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3816 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3817 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3818 II(ImplicitOps | Stack, em_popf, popf),
3819 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3820 /* 0xA0 - 0xA7 */
b9eac5f4 3821 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3822 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3823 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3824 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3825 /* 0xA8 - 0xAF */
fb864fbc 3826 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3827 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3828 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3829 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3830 /* 0xB0 - 0xB7 */
b9eac5f4 3831 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3832 /* 0xB8 - 0xBF */
5e2c6883 3833 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3834 /* 0xC0 - 0xC7 */
007a3b54 3835 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3836 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3837 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3838 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3839 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3840 G(ByteOp, group11), G(0, group11),
73fba5f4 3841 /* 0xC8 - 0xCF */
612e89f0 3842 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3843 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3844 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3845 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3846 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3847 /* 0xD0 - 0xD7 */
007a3b54
AK		 3848 G(Src2One | ByteOp, group2), G(Src2One, group2),
3849 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3850 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3851 I(DstAcc | SrcImmUByte | No64, em_aad),
3852 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3853 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3854 /* 0xD8 - 0xDF */
045a282c 3855 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3856 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3857 X3(I(SrcImmByte, em_loop)),
3858 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3859 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3860 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3861 /* 0xE8 - 0xEF */
d4ddafcd 3862 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3863 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3864 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3865 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3866 /* 0xF0 - 0xF7 */
bf608f88 3867 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3868 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3869 G(ByteOp, group3), G(0, group3),
73fba5f4 3870 /* 0xF8 - 0xFF */
f411e6cd
TY		 3871 D(ImplicitOps), D(ImplicitOps),
3872 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3873 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3874};
3875
fd0a0d82 3876static const struct opcode twobyte_table[256] = {
73fba5f4 3877 /* 0x00 - 0x0F */
dee6bb70 3878 G(0, group6), GD(0, &group7), N, N,
b51e974f 3879 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3880 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3881 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3882 N, D(ImplicitOps | ModRM), N, N,
3883 /* 0x10 - 0x1F */
103f98ea
PB		 3884 N, N, N, N, N, N, N, N,
3885 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3886 /* 0x20 - 0x2F */
9b88ae99
NA		 3887 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3888 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3889 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3890 check_cr_write),
3891 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3892 check_dr_write),
73fba5f4 3893 N, N, N, N,
27ce8258
IM		 3894 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3895 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3896 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3897 N, N, N, N,
73fba5f4 3898 /* 0x30 - 0x3F */
e1e210b0 3899 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3900 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3901 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3902 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3903 I(ImplicitOps | EmulateOnUD, em_sysenter),
3904 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3905 N, N,
73fba5f4
AK		 3906 N, N, N, N, N, N, N, N,
3907 /* 0x40 - 0x4F */
3908 X16(D(DstReg | SrcMem | ModRM | Mov)),
3909 /* 0x50 - 0x5F */
3910 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3911 /* 0x60 - 0x6F */
aa97bb48
AK		 3912 N, N, N, N,
3913 N, N, N, N,
3914 N, N, N, N,
3915 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3916 /* 0x70 - 0x7F */
aa97bb48
AK		 3917 N, N, N, N,
3918 N, N, N, N,
3919 N, N, N, N,
3920 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3921 /* 0x80 - 0x8F */
3922 X16(D(SrcImm)),
3923 /* 0x90 - 0x9F */
ee45b58e 3924 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3925 /* 0xA0 - 0xA7 */
1cd196ea 3926 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3927 II(ImplicitOps, em_cpuid, cpuid),
3928 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3929 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3930 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3931 /* 0xA8 - 0xAF */
1cd196ea 3932 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3933 DI(ImplicitOps, rsm),
11c363ba 3934 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3935 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3936 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3937 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3938 /* 0xB0 - 0xB7 */
e940b5c2 3939 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3940 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3941 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3942 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3943 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3944 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3945 /* 0xB8 - 0xBF */
3946 N, N,
ce7faab2 3947 G(BitOp, group8),
11c363ba
AK		 3948 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3949 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3950 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3951 /* 0xC0 - 0xC7 */
e47a5f5f 3952 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3953 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3954 N, N, N, GD(0, &group9),
9299836e
AK		 3955 /* 0xC8 - 0xCF */
3956 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3957 /* 0xD0 - 0xDF */
3958 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3959 /* 0xE0 - 0xEF */
3960 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3961 /* 0xF0 - 0xFF */
3962 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3963};
3964
0bc5eedb 3965static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3966 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3967};
3968
3969static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3970 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3971};
3972
3973/*
3974 * Insns below are selected by the prefix which indexed by the third opcode
3975 * byte.
3976 */
3977static const struct opcode opcode_map_0f_38[256] = {
3978 /* 0x00 - 0x7f */
3979 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3980 /* 0x80 - 0xef */
3981 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3982 /* 0xf0 - 0xf1 */
3983 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3984 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3985 /* 0xf2 - 0xff */
3986 N, N, X4(N), X8(N)
0bc5eedb
BP		 3987};
3988
73fba5f4
AK		 3989#undef D
3990#undef N
3991#undef G
3992#undef GD
3993#undef I
aa97bb48 3994#undef GP
01de8b09 3995#undef EXT
73fba5f4 3996
8d8f4e9f 3997#undef D2bv
f6511935 3998#undef D2bvIP
8d8f4e9f 3999#undef I2bv
d7841a4b 4000#undef I2bvIP
d67fc27a 4001#undef I6ALU
8d8f4e9f 4002
9dac77fa 4003static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4004{
4005 unsigned size;
4006
9dac77fa 4007 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4008 if (size == 8)
4009 size = 4;
4010 return size;
4011}
4012
4013static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4014 unsigned size, bool sign_extension)
4015{
39f21ee5
AK		 4016 int rc = X86EMUL_CONTINUE;
4017
4018 op->type = OP_IMM;
4019 op->bytes = size;
9dac77fa 4020 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4021 /* NB. Immediates are sign-extended as necessary. */
4022 switch (op->bytes) {
4023 case 1:
e85a1085 4024 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4025 break;
4026 case 2:
e85a1085 4027 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4028 break;
4029 case 4:
e85a1085 4030 op->val = insn_fetch(s32, ctxt);
39f21ee5 4031 break;
5e2c6883
NA		 4032 case 8:
4033 op->val = insn_fetch(s64, ctxt);
4034 break;
39f21ee5
AK		 4035 }
4036 if (!sign_extension) {
4037 switch (op->bytes) {
4038 case 1:
4039 op->val &= 0xff;
4040 break;
4041 case 2:
4042 op->val &= 0xffff;
4043 break;
4044 case 4:
4045 op->val &= 0xffffffff;
4046 break;
4047 }
4048 }
4049done:
4050 return rc;
4051}
4052
a9945549
AK		 4053static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4054 unsigned d)
4055{
4056 int rc = X86EMUL_CONTINUE;
4057
4058 switch (d) {
4059 case OpReg:
2adb5ad9 4060 decode_register_operand(ctxt, op);
a9945549
AK		 4061 break;
4062 case OpImmUByte:
608aabe3 4063 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4064 break;
4065 case OpMem:
41ddf978 4066 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4067 mem_common:
4068 *op = ctxt->memop;
4069 ctxt->memopp = op;
4070 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4071 fetch_bit_operand(ctxt);
4072 op->orig_val = op->val;
4073 break;
41ddf978
AK		 4074 case OpMem64:
4075 ctxt->memop.bytes = 8;
4076 goto mem_common;
a9945549
AK		 4077 case OpAcc:
4078 op->type = OP_REG;
4079 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4080 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4081 fetch_register_operand(op);
4082 op->orig_val = op->val;
4083 break;
820207c8
AK		 4084 case OpAccLo:
4085 op->type = OP_REG;
4086 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4087 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4088 fetch_register_operand(op);
4089 op->orig_val = op->val;
4090 break;
4091 case OpAccHi:
4092 if (ctxt->d & ByteOp) {
4093 op->type = OP_NONE;
4094 break;
4095 }
4096 op->type = OP_REG;
4097 op->bytes = ctxt->op_bytes;
4098 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4099 fetch_register_operand(op);
4100 op->orig_val = op->val;
4101 break;
a9945549
AK		 4102 case OpDI:
4103 op->type = OP_MEM;
4104 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4105 op->addr.mem.ea =
dd856efa 4106 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4107 op->addr.mem.seg = VCPU_SREG_ES;
4108 op->val = 0;
b3356bf0 4109 op->count = 1;
a9945549
AK		 4110 break;
4111 case OpDX:
4112 op->type = OP_REG;
4113 op->bytes = 2;
dd856efa 4114 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4115 fetch_register_operand(op);
4116 break;
4dd6a57d
AK		 4117 case OpCL:
4118 op->bytes = 1;
dd856efa 4119 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4120 break;
4121 case OpImmByte:
4122 rc = decode_imm(ctxt, op, 1, true);
4123 break;
4124 case OpOne:
4125 op->bytes = 1;
4126 op->val = 1;
4127 break;
4128 case OpImm:
4129 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4130 break;
5e2c6883
NA		 4131 case OpImm64:
4132 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4133 break;
28867cee
AK		 4134 case OpMem8:
4135 ctxt->memop.bytes = 1;
660696d1 4136 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4137 ctxt->memop.addr.reg = decode_register(ctxt,
4138 ctxt->modrm_rm, true);
660696d1
GN		 4139 fetch_register_operand(&ctxt->memop);
4140 }
28867cee 4141 goto mem_common;
0fe59128
AK		 4142 case OpMem16:
4143 ctxt->memop.bytes = 2;
4144 goto mem_common;
4145 case OpMem32:
4146 ctxt->memop.bytes = 4;
4147 goto mem_common;
4148 case OpImmU16:
4149 rc = decode_imm(ctxt, op, 2, false);
4150 break;
4151 case OpImmU:
4152 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4153 break;
4154 case OpSI:
4155 op->type = OP_MEM;
4156 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4157 op->addr.mem.ea =
dd856efa 4158 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4159 op->addr.mem.seg = seg_override(ctxt);
4160 op->val = 0;
b3356bf0 4161 op->count = 1;
0fe59128 4162 break;
7fa57952
PB		 4163 case OpXLat:
4164 op->type = OP_MEM;
4165 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4166 op->addr.mem.ea =
4167 register_address(ctxt,
4168 reg_read(ctxt, VCPU_REGS_RBX) +
4169 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4170 op->addr.mem.seg = seg_override(ctxt);
4171 op->val = 0;
4172 break;
0fe59128
AK		 4173 case OpImmFAddr:
4174 op->type = OP_IMM;
4175 op->addr.mem.ea = ctxt->_eip;
4176 op->bytes = ctxt->op_bytes + 2;
4177 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4178 break;
4179 case OpMemFAddr:
4180 ctxt->memop.bytes = ctxt->op_bytes + 2;
4181 goto mem_common;
c191a7a0
AK		 4182 case OpES:
4183 op->val = VCPU_SREG_ES;
4184 break;
4185 case OpCS:
4186 op->val = VCPU_SREG_CS;
4187 break;
4188 case OpSS:
4189 op->val = VCPU_SREG_SS;
4190 break;
4191 case OpDS:
4192 op->val = VCPU_SREG_DS;
4193 break;
4194 case OpFS:
4195 op->val = VCPU_SREG_FS;
4196 break;
4197 case OpGS:
4198 op->val = VCPU_SREG_GS;
4199 break;
a9945549
AK		 4200 case OpImplicit:
4201 /* Special instructions do their own operand decoding. */
4202 default:
4203 op->type = OP_NONE; /* Disable writeback. */
4204 break;
4205 }
4206
4207done:
4208 return rc;
4209}
4210
ef5d75cc 4211int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4212{
dde7e6d1
AK		 4213 int rc = X86EMUL_CONTINUE;
4214 int mode = ctxt->mode;
46561646 4215 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4216 bool op_prefix = false;
46561646 4217 struct opcode opcode;
dde7e6d1 4218
f09ed83e
AK		 4219 ctxt->memop.type = OP_NONE;
4220 ctxt->memopp = NULL;
9dac77fa
AK		 4221 ctxt->_eip = ctxt->eip;
4222 ctxt->fetch.start = ctxt->_eip;
4223 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4224 ctxt->opcode_len = 1;
dc25e89e 4225 if (insn_len > 0)
9dac77fa 4226 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4227
4228 switch (mode) {
4229 case X86EMUL_MODE_REAL:
4230 case X86EMUL_MODE_VM86:
4231 case X86EMUL_MODE_PROT16:
4232 def_op_bytes = def_ad_bytes = 2;
4233 break;
4234 case X86EMUL_MODE_PROT32:
4235 def_op_bytes = def_ad_bytes = 4;
4236 break;
4237#ifdef CONFIG_X86_64
4238 case X86EMUL_MODE_PROT64:
4239 def_op_bytes = 4;
4240 def_ad_bytes = 8;
4241 break;
4242#endif
4243 default:
1d2887e2 4244 return EMULATION_FAILED;
dde7e6d1
AK		 4245 }
4246
9dac77fa
AK		 4247 ctxt->op_bytes = def_op_bytes;
4248 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4249
4250 /* Legacy prefixes. */
4251 for (;;) {
e85a1085 4252 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4253 case 0x66: /* operand-size override */
0d7cdee8 4254 op_prefix = true;
dde7e6d1 4255 /* switch between 2/4 bytes */
9dac77fa 4256 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4257 break;
4258 case 0x67: /* address-size override */
4259 if (mode == X86EMUL_MODE_PROT64)
4260 /* switch between 4/8 bytes */
9dac77fa 4261 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4262 else
4263 /* switch between 2/4 bytes */
9dac77fa 4264 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4265 break;
4266 case 0x26: /* ES override */
4267 case 0x2e: /* CS override */
4268 case 0x36: /* SS override */
4269 case 0x3e: /* DS override */
9dac77fa 4270 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4271 break;
4272 case 0x64: /* FS override */
4273 case 0x65: /* GS override */
9dac77fa 4274 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4275 break;
4276 case 0x40 ... 0x4f: /* REX */
4277 if (mode != X86EMUL_MODE_PROT64)
4278 goto done_prefixes;
9dac77fa 4279 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4280 continue;
4281 case 0xf0: /* LOCK */
9dac77fa 4282 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4283 break;
4284 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4285 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4286 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4287 break;
4288 default:
4289 goto done_prefixes;
4290 }
4291
4292 /* Any legacy prefix after a REX prefix nullifies its effect. */
4293
9dac77fa 4294 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4295 }
4296
4297done_prefixes:
4298
4299 /* REX prefix. */
9dac77fa
AK		 4300 if (ctxt->rex_prefix & 8)
4301 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4302
4303 /* Opcode byte(s). */
9dac77fa 4304 opcode = opcode_table[ctxt->b];
d3ad6243 4305 /* Two-byte opcode? */
9dac77fa 4306 if (ctxt->b == 0x0f) {
1ce19dc1 4307 ctxt->opcode_len = 2;
e85a1085 4308 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4309 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4310
4311 /* 0F_38 opcode map */
4312 if (ctxt->b == 0x38) {
4313 ctxt->opcode_len = 3;
4314 ctxt->b = insn_fetch(u8, ctxt);
4315 opcode = opcode_map_0f_38[ctxt->b];
4316 }
dde7e6d1 4317 }
9dac77fa 4318 ctxt->d = opcode.flags;
dde7e6d1 4319
9f4260e7
TY		 4320 if (ctxt->d & ModRM)
4321 ctxt->modrm = insn_fetch(u8, ctxt);
4322
7fe864dc
NA		 4323 /* vex-prefix instructions are not implemented */
4324 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4325 (mode == X86EMUL_MODE_PROT64 ||
4326 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4327 ctxt->d = NotImpl;
4328 }
4329
9dac77fa
AK		 4330 while (ctxt->d & GroupMask) {
4331 switch (ctxt->d & GroupMask) {
46561646 4332 case Group:
9dac77fa 4333 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4334 opcode = opcode.u.group[goffset];
4335 break;
4336 case GroupDual:
9dac77fa
AK		 4337 goffset = (ctxt->modrm >> 3) & 7;
4338 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4339 opcode = opcode.u.gdual->mod3[goffset];
4340 else
4341 opcode = opcode.u.gdual->mod012[goffset];
4342 break;
4343 case RMExt:
9dac77fa 4344 goffset = ctxt->modrm & 7;
01de8b09 4345 opcode = opcode.u.group[goffset];
46561646
AK		 4346 break;
4347 case Prefix:
9dac77fa 4348 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4349 return EMULATION_FAILED;
9dac77fa 4350 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4351 switch (simd_prefix) {
4352 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4353 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4354 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4355 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4356 }
4357 break;
045a282c
GN		 4358 case Escape:
4359 if (ctxt->modrm > 0xbf)
4360 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4361 else
4362 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4363 break;
46561646 4364 default:
1d2887e2 4365 return EMULATION_FAILED;
0d7cdee8 4366 }
46561646 4367
b1ea50b2 4368 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4369 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4370 }
4371
9dac77fa
AK		 4372 ctxt->execute = opcode.u.execute;
4373 ctxt->check_perm = opcode.check_perm;
4374 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4375
4376 /* Unrecognised? */
1146a78b 4377 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4378 return EMULATION_FAILED;
dde7e6d1 4379
b51e974f 4380 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
1d2887e2 4381 return EMULATION_FAILED;
d867162c 4382
9dac77fa
AK		 4383 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4384 ctxt->op_bytes = 8;
dde7e6d1 4385
9dac77fa 4386 if (ctxt->d & Op3264) {
7f9b4b75 4387 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4388 ctxt->op_bytes = 8;
7f9b4b75 4389 else
9dac77fa 4390 ctxt->op_bytes = 4;
7f9b4b75
AK		 4391 }
4392
9dac77fa
AK		 4393 if (ctxt->d & Sse)
4394 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4395 else if (ctxt->d & Mmx)
4396 ctxt->op_bytes = 8;
1253791d 4397
dde7e6d1 4398 /* ModRM and SIB bytes. */
9dac77fa 4399 if (ctxt->d & ModRM) {
f09ed83e 4400 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4401 if (!ctxt->has_seg_override)
4402 set_seg_override(ctxt, ctxt->modrm_seg);
4403 } else if (ctxt->d & MemAbs)
f09ed83e 4404 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4405 if (rc != X86EMUL_CONTINUE)
4406 goto done;
4407
9dac77fa
AK		 4408 if (!ctxt->has_seg_override)
4409 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4410
f09ed83e 4411 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4412
f09ed83e
AK		 4413 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4414 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4415
dde7e6d1
AK		 4416 /*
4417 * Decode and fetch the source operand: register, memory
4418 * or immediate.
4419 */
0fe59128 4420 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4421 if (rc != X86EMUL_CONTINUE)
4422 goto done;
4423
dde7e6d1
AK		 4424 /*
4425 * Decode and fetch the second source operand: register, memory
4426 * or immediate.
4427 */
4dd6a57d 4428 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4429 if (rc != X86EMUL_CONTINUE)
4430 goto done;
4431
dde7e6d1 4432 /* Decode and fetch the destination operand: register or memory. */
a9945549 4433 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4434
4435done:
f09ed83e
AK		 4436 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4437 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4438
1d2887e2 4439 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4440}
4441
1cb3f3ae
XG		 4442bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4443{
4444 return ctxt->d & PageTable;
4445}
4446
3e2f65d5
GN		 4447static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4448{
3e2f65d5
GN		 4449 /* The second termination condition only applies for REPE
4450 * and REPNE. Test if the repeat string operation prefix is
4451 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4452 * corresponding termination condition according to:
4453 * - if REPE/REPZ and ZF = 0 then done
4454 * - if REPNE/REPNZ and ZF = 1 then done
4455 */
9dac77fa
AK		 4456 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4457 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4458 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4459 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4460 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4461 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4462 return true;
4463
4464 return false;
4465}
4466
cbe2c9d3
AK		 4467static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4468{
4469 bool fault = false;
4470
4471 ctxt->ops->get_fpu(ctxt);
4472 asm volatile("1: fwait \n\t"
4473 "2: \n\t"
4474 ".pushsection .fixup,\"ax\" \n\t"
4475 "3: \n\t"
4476 "movb $1, %[fault] \n\t"
4477 "jmp 2b \n\t"
4478 ".popsection \n\t"
4479 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4480 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4481 ctxt->ops->put_fpu(ctxt);
4482
4483 if (unlikely(fault))
4484 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4485
4486 return X86EMUL_CONTINUE;
4487}
4488
4489static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4490 struct operand *op)
4491{
4492 if (op->type == OP_MM)
4493 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4494}
4495
e28bbd44
AK		 4496static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4497{
4498 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4499 if (!(ctxt->d & ByteOp))
4500 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4501 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4502 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4503 [fastop]"+S"(fop)
4504 : "c"(ctxt->src2.val));
e28bbd44 4505 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4506 if (!fop) /* exception is returned in fop variable */
4507 return emulate_de(ctxt);
e28bbd44
AK		 4508 return X86EMUL_CONTINUE;
4509}
dd856efa 4510
7b105ca2 4511int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4512{
0225fb50 4513 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4514 int rc = X86EMUL_CONTINUE;
9dac77fa 4515 int saved_dst_type = ctxt->dst.type;
8b4caf66 4516
9dac77fa 4517 ctxt->mem_read.pos = 0;
310b5d30 4518
1146a78b
GN		 4519 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4520 (ctxt->d & Undefined)) {
35d3d4a1 4521 rc = emulate_ud(ctxt);
1161624f
GN		 4522 goto done;
4523 }
4524
d380a5e4 4525 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4526 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4527 rc = emulate_ud(ctxt);
d380a5e4
GN		 4528 goto done;
4529 }
4530
9dac77fa 4531 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4532 rc = emulate_ud(ctxt);
081bca0e
AK		 4533 goto done;
4534 }
4535
cbe2c9d3
AK		 4536 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4537 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4538 rc = emulate_ud(ctxt);
4539 goto done;
4540 }
4541
cbe2c9d3 4542 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4543 rc = emulate_nm(ctxt);
4544 goto done;
4545 }
4546
cbe2c9d3
AK		 4547 if (ctxt->d & Mmx) {
4548 rc = flush_pending_x87_faults(ctxt);
4549 if (rc != X86EMUL_CONTINUE)
4550 goto done;
4551 /*
4552 * Now that we know the fpu is exception safe, we can fetch
4553 * operands from it.
4554 */
4555 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4556 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4557 if (!(ctxt->d & Mov))
4558 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4559 }
4560
9dac77fa
AK		 4561 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4562 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4563 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4564 if (rc != X86EMUL_CONTINUE)
4565 goto done;
4566 }
4567
e92805ac 4568 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4569 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4570 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4571 goto done;
4572 }
4573
8ea7d6ae 4574 /* Instruction can only be executed in protected mode */
9d1b39a9 4575 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4576 rc = emulate_ud(ctxt);
4577 goto done;
4578 }
4579
d09beabd 4580 /* Do instruction specific permission checks */
9dac77fa
AK		 4581 if (ctxt->check_perm) {
4582 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4583 if (rc != X86EMUL_CONTINUE)
4584 goto done;
4585 }
4586
9dac77fa
AK		 4587 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4588 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4589 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4590 if (rc != X86EMUL_CONTINUE)
4591 goto done;
4592 }
4593
9dac77fa 4594 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4595 /* All REP prefixes have the same first termination condition */
dd856efa 4596 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4597 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4598 goto done;
4599 }
b9fa9d6b
AK		 4600 }
4601
9dac77fa
AK		 4602 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4603 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4604 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4605 if (rc != X86EMUL_CONTINUE)
8b4caf66 4606 goto done;
9dac77fa 4607 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4608 }
4609
9dac77fa
AK		 4610 if (ctxt->src2.type == OP_MEM) {
4611 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4612 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4613 if (rc != X86EMUL_CONTINUE)
4614 goto done;
4615 }
4616
9dac77fa 4617 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4618 goto special_insn;
4619
4620
9dac77fa 4621 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4622 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4623 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4624 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4625 if (rc != X86EMUL_CONTINUE)
4626 goto done;
038e51de 4627 }
9dac77fa 4628 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4629
018a98db
AK		 4630special_insn:
4631
9dac77fa
AK		 4632 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4633 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4634 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637 }
4638
9dac77fa 4639 if (ctxt->execute) {
e28bbd44
AK		 4640 if (ctxt->d & Fastop) {
4641 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4642 rc = fastop(ctxt, fop);
4643 if (rc != X86EMUL_CONTINUE)
4644 goto done;
4645 goto writeback;
4646 }
9dac77fa 4647 rc = ctxt->execute(ctxt);
ef65c889
AK		 4648 if (rc != X86EMUL_CONTINUE)
4649 goto done;
4650 goto writeback;
4651 }
4652
1ce19dc1 4653 if (ctxt->opcode_len == 2)
6aa8b732 4654 goto twobyte_insn;
0bc5eedb
BP		 4655 else if (ctxt->opcode_len == 3)
4656 goto threebyte_insn;
6aa8b732 4657
9dac77fa 4658 switch (ctxt->b) {
6aa8b732 4659 case 0x63: /* movsxd */
8b4caf66 4660 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4661 goto cannot_emulate;
9dac77fa 4662 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4663 break;
b2833e3c 4664 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4665 if (test_cc(ctxt->b, ctxt->eflags))
4666 jmp_rel(ctxt, ctxt->src.val);
018a98db 4667 break;
7e0b54b1 4668 case 0x8d: /* lea r16/r32, m */
9dac77fa 4669 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4670 break;
3d9e77df 4671 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4672 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4673 break;
e4f973ae
TY		 4674 rc = em_xchg(ctxt);
4675 break;
e8b6fa70 4676 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4677 switch (ctxt->op_bytes) {
4678 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4679 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4680 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4681 }
4682 break;
6e154e56 4683 case 0xcc: /* int3 */
5c5df76b
TY		 4684 rc = emulate_int(ctxt, 3);
4685 break;
6e154e56 4686 case 0xcd: /* int n */
9dac77fa 4687 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4688 break;
4689 case 0xce: /* into */
5c5df76b
TY		 4690 if (ctxt->eflags & EFLG_OF)
4691 rc = emulate_int(ctxt, 4);
6e154e56 4692 break;
1a52e051 4693 case 0xe9: /* jmp rel */
db5b0762 4694 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4695 jmp_rel(ctxt, ctxt->src.val);
4696 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4697 break;
111de5d6 4698 case 0xf4: /* hlt */
6c3287f7 4699 ctxt->ops->halt(ctxt);
19fdfa0d 4700 break;
111de5d6
AK		 4701 case 0xf5: /* cmc */
4702 /* complement carry flag from eflags reg */
4703 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4704 break;
4705 case 0xf8: /* clc */
4706 ctxt->eflags &= ~EFLG_CF;
111de5d6 4707 break;
8744aa9a
MG		 4708 case 0xf9: /* stc */
4709 ctxt->eflags |= EFLG_CF;
4710 break;
fb4616f4
MG		 4711 case 0xfc: /* cld */
4712 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4713 break;
4714 case 0xfd: /* std */
4715 ctxt->eflags |= EFLG_DF;
fb4616f4 4716 break;
91269b8f
AK		 4717 default:
4718 goto cannot_emulate;
6aa8b732 4719 }
018a98db 4720
7d9ddaed
AK		 4721 if (rc != X86EMUL_CONTINUE)
4722 goto done;
4723
018a98db 4724writeback:
fb32b1ed
AK		 4725 if (!(ctxt->d & NoWrite)) {
4726 rc = writeback(ctxt, &ctxt->dst);
4727 if (rc != X86EMUL_CONTINUE)
4728 goto done;
4729 }
4730 if (ctxt->d & SrcWrite) {
4731 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4732 rc = writeback(ctxt, &ctxt->src);
4733 if (rc != X86EMUL_CONTINUE)
4734 goto done;
4735 }
018a98db 4736
5cd21917
GN		 4737 /*
4738 * restore dst type in case the decoding will be reused
4739 * (happens for string instruction )
4740 */
9dac77fa 4741 ctxt->dst.type = saved_dst_type;
5cd21917 4742
9dac77fa 4743 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4744 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4745
9dac77fa 4746 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4747 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4748
9dac77fa 4749 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4750 unsigned int count;
9dac77fa 4751 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4752 if ((ctxt->d & SrcMask) == SrcSI)
4753 count = ctxt->src.count;
4754 else
4755 count = ctxt->dst.count;
4756 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4757 -count);
3e2f65d5 4758
d2ddd1c4
GN		 4759 if (!string_insn_completed(ctxt)) {
4760 /*
4761 * Re-enter guest when pio read ahead buffer is empty
4762 * or, if it is not used, after each 1024 iteration.
4763 */
dd856efa 4764 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4765 (r->end == 0 || r->end != r->pos)) {
4766 /*
4767 * Reset read cache. Usually happens before
4768 * decode, but since instruction is restarted
4769 * we have to do it here.
4770 */
9dac77fa 4771 ctxt->mem_read.end = 0;
dd856efa 4772 writeback_registers(ctxt);
d2ddd1c4
GN		 4773 return EMULATION_RESTART;
4774 }
4775 goto done; /* skip rip writeback */
0fa6ccbd 4776 }
5cd21917 4777 }
d2ddd1c4 4778
9dac77fa 4779 ctxt->eip = ctxt->_eip;
018a98db
AK		 4780
4781done:
da9cb575
AK		 4782 if (rc == X86EMUL_PROPAGATE_FAULT)
4783 ctxt->have_exception = true;
775fde86
JR		 4784 if (rc == X86EMUL_INTERCEPTED)
4785 return EMULATION_INTERCEPTED;
4786
dd856efa
AK		 4787 if (rc == X86EMUL_CONTINUE)
4788 writeback_registers(ctxt);
4789
d2ddd1c4 4790 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4791
4792twobyte_insn:
9dac77fa 4793 switch (ctxt->b) {
018a98db 4794 case 0x09: /* wbinvd */
cfb22375 4795 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4796 break;
4797 case 0x08: /* invd */
018a98db
AK		 4798 case 0x0d: /* GrpP (prefetch) */
4799 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4800 case 0x1f: /* nop */
018a98db
AK		 4801 break;
4802 case 0x20: /* mov cr, reg */
9dac77fa 4803 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4804 break;
6aa8b732 4805 case 0x21: /* mov from dr to reg */
9dac77fa 4806 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4807 break;
6aa8b732 4808 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4809 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4810 if (!test_cc(ctxt->b, ctxt->eflags))
4811 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4812 break;
b2833e3c 4813 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4814 if (test_cc(ctxt->b, ctxt->eflags))
4815 jmp_rel(ctxt, ctxt->src.val);
018a98db 4816 break;
ee45b58e 4817 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4818 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4819 break;
2a7c5b8b
GC		 4820 case 0xae: /* clflush */
4821 break;
6aa8b732 4822 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4823 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4824 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4825 : (u16) ctxt->src.val;
6aa8b732 4826 break;
6aa8b732 4827 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4828 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4829 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4830 (s16) ctxt->src.val;
6aa8b732 4831 break;
a012e65a 4832 case 0xc3: /* movnti */
9dac77fa
AK		 4833 ctxt->dst.bytes = ctxt->op_bytes;
4834 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4835 (u64) ctxt->src.val;
a012e65a 4836 break;
91269b8f
AK		 4837 default:
4838 goto cannot_emulate;
6aa8b732 4839 }
7d9ddaed 4840
0bc5eedb
BP		 4841threebyte_insn:
4842
7d9ddaed
AK		 4843 if (rc != X86EMUL_CONTINUE)
4844 goto done;
4845
6aa8b732
AK		 4846 goto writeback;
4847
4848cannot_emulate:
a0c0ab2f 4849 return EMULATION_FAILED;
6aa8b732 4850}
dd856efa
AK		 4851
4852void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4853{
4854 invalidate_registers(ctxt);
4855}
4856
4857void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4858{
4859 writeback_registers(ctxt);
4860}
Linux kernel - Deliverables
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