projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: Use opcode::execute for XCHG(86/87)
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
221192bd
MT		 50#define DstDX (8<<1) /* Destination is in DX register */
51#define DstMask (0xf<<1)
6aa8b732 52/* Source operand type. */
221192bd
MT		 53#define SrcNone (0<<5) /* No source operand. */
54#define SrcReg (1<<5) /* Register operand. */
55#define SrcMem (2<<5) /* Memory operand. */
56#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
58#define SrcImm (5<<5) /* Immediate operand. */
59#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
60#define SrcOne (7<<5) /* Implied '1' */
61#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
62#define SrcImmU (9<<5) /* Immediate operand, unsigned */
63#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
64#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
65#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
66#define SrcAcc (0xd<<5) /* Source Accumulator */
67#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
68#define SrcDX (0xf<<5) /* Source is in DX register */
69#define SrcMask (0xf<<5)
6aa8b732 70/* Generic ModRM decode. */
221192bd 71#define ModRM (1<<9)
6aa8b732 72/* Destination is only written; never read. */
221192bd
MT		 73#define Mov (1<<10)
74#define BitOp (1<<11)
75#define MemAbs (1<<12) /* Memory operand is absolute displacement */
76#define String (1<<13) /* String instruction (rep capable) */
77#define Stack (1<<14) /* Stack instruction (push/pop) */
78#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
79#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
81#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
82#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
83#define Sse (1<<18) /* SSE Vector instruction */
d8769fed 84/* Misc flags */
8ea7d6ae 85#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 86#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
c4f035c6 112 u8 intercept;
120df890 113 union {
ef65c889 114 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 115 struct opcode *group;
116 struct group_dual *gdual;
0d7cdee8 117 struct gprefix *gprefix;
120df890 118 } u;
d09beabd 119 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 120};
121
122struct group_dual {
123 struct opcode mod012[8];
124 struct opcode mod3[8];
d65b1dee
AK		 125};
126
0d7cdee8
AK		 127struct gprefix {
128 struct opcode pfx_no;
129 struct opcode pfx_66;
130 struct opcode pfx_f2;
131 struct opcode pfx_f3;
132};
133
6aa8b732 134/* EFLAGS bit definitions. */
d4c6a154
GN		 135#define EFLG_ID (1<<21)
136#define EFLG_VIP (1<<20)
137#define EFLG_VIF (1<<19)
138#define EFLG_AC (1<<18)
b1d86143
AP		 139#define EFLG_VM (1<<17)
140#define EFLG_RF (1<<16)
d4c6a154
GN		 141#define EFLG_IOPL (3<<12)
142#define EFLG_NT (1<<14)
6aa8b732
AK		 143#define EFLG_OF (1<<11)
144#define EFLG_DF (1<<10)
b1d86143 145#define EFLG_IF (1<<9)
d4c6a154 146#define EFLG_TF (1<<8)
6aa8b732
AK		 147#define EFLG_SF (1<<7)
148#define EFLG_ZF (1<<6)
149#define EFLG_AF (1<<4)
150#define EFLG_PF (1<<2)
151#define EFLG_CF (1<<0)
152
62bd430e
MG		 153#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
154#define EFLG_RESERVED_ONE_MASK 2
155
6aa8b732
AK		 156/*
157 * Instruction emulation:
158 * Most instructions are emulated directly via a fragment of inline assembly
159 * code. This allows us to save/restore EFLAGS and thus very easily pick up
160 * any modified flags.
161 */
162
05b3e0c2 163#if defined(CONFIG_X86_64)
6aa8b732
AK		 164#define _LO32 "k" /* force 32-bit operand */
165#define _STK "%%rsp" /* stack pointer */
166#elif defined(__i386__)
167#define _LO32 "" /* force 32-bit operand */
168#define _STK "%%esp" /* stack pointer */
169#endif
170
171/*
172 * These EFLAGS bits are restored from saved value during emulation, and
173 * any changes are written back to the saved value after emulation.
174 */
175#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
176
177/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 178#define _PRE_EFLAGS(_sav, _msk, _tmp) \
179 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
180 "movl %"_sav",%"_LO32 _tmp"; " \
181 "push %"_tmp"; " \
182 "push %"_tmp"; " \
183 "movl %"_msk",%"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "pushf; " \
186 "notl %"_LO32 _tmp"; " \
187 "andl %"_LO32 _tmp",("_STK"); " \
188 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
189 "pop %"_tmp"; " \
190 "orl %"_LO32 _tmp",("_STK"); " \
191 "popf; " \
192 "pop %"_sav"; "
6aa8b732
AK		 193
194/* After executing instruction: write-back necessary bits in EFLAGS. */
195#define _POST_EFLAGS(_sav, _msk, _tmp) \
196 /* _sav |= EFLAGS & _msk; */ \
197 "pushf; " \
198 "pop %"_tmp"; " \
199 "andl %"_msk",%"_LO32 _tmp"; " \
200 "orl %"_LO32 _tmp",%"_sav"; "
201
dda96d8f
AK		 202#ifdef CONFIG_X86_64
203#define ON64(x) x
204#else
205#define ON64(x)
206#endif
207
b3b3d25a 208#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 209 do { \
210 __asm__ __volatile__ ( \
211 _PRE_EFLAGS("0", "4", "2") \
212 _op _suffix " %"_x"3,%1; " \
213 _POST_EFLAGS("0", "4", "2") \
fb2c2641 214 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 215 "=&r" (_tmp) \
216 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 217 } while (0)
6b7ad61f
AK		 218
219
6aa8b732
AK		 220/* Raw emulation: instruction has two explicit operands. */
221#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 222 do { \
223 unsigned long _tmp; \
224 \
225 switch ((_dst).bytes) { \
226 case 2: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 228 break; \
229 case 4: \
b3b3d25a 230 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 231 break; \
232 case 8: \
b3b3d25a 233 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 234 break; \
235 } \
6aa8b732
AK		 236 } while (0)
237
238#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
239 do { \
6b7ad61f 240 unsigned long _tmp; \
d77c26fc 241 switch ((_dst).bytes) { \
6aa8b732 242 case 1: \
b3b3d25a 243 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 244 break; \
245 default: \
246 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
247 _wx, _wy, _lx, _ly, _qx, _qy); \
248 break; \
249 } \
250 } while (0)
251
252/* Source operand is byte-sized and may be restricted to just %cl. */
253#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
254 __emulate_2op(_op, _src, _dst, _eflags, \
255 "b", "c", "b", "c", "b", "c", "b", "c")
256
257/* Source operand is byte, word, long or quad sized. */
258#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
259 __emulate_2op(_op, _src, _dst, _eflags, \
260 "b", "q", "w", "r", _LO32, "r", "", "r")
261
262/* Source operand is word, long or quad sized. */
263#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
264 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
265 "w", "r", _LO32, "r", "", "r")
266
d175226a 267/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 268#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
269 do { \
270 unsigned long _tmp; \
271 _type _clv = (_cl).val; \
272 _type _srcv = (_src).val; \
273 _type _dstv = (_dst).val; \
274 \
275 __asm__ __volatile__ ( \
276 _PRE_EFLAGS("0", "5", "2") \
277 _op _suffix " %4,%1 \n" \
278 _POST_EFLAGS("0", "5", "2") \
279 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
280 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
281 ); \
282 \
283 (_cl).val = (unsigned long) _clv; \
284 (_src).val = (unsigned long) _srcv; \
285 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 286 } while (0)
287
7295261c
AK		 288#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
289 do { \
290 switch ((_dst).bytes) { \
291 case 2: \
292 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
293 "w", unsigned short); \
294 break; \
295 case 4: \
296 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
297 "l", unsigned int); \
298 break; \
299 case 8: \
300 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
301 "q", unsigned long)); \
302 break; \
303 } \
d175226a
GT		 304 } while (0)
305
dda96d8f 306#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 307 do { \
308 unsigned long _tmp; \
309 \
dda96d8f
AK		 310 __asm__ __volatile__ ( \
311 _PRE_EFLAGS("0", "3", "2") \
312 _op _suffix " %1; " \
313 _POST_EFLAGS("0", "3", "2") \
314 : "=m" (_eflags), "+m" ((_dst).val), \
315 "=&r" (_tmp) \
316 : "i" (EFLAGS_MASK)); \
317 } while (0)
318
319/* Instruction has only one explicit operand (no source operand). */
320#define emulate_1op(_op, _dst, _eflags) \
321 do { \
d77c26fc 322 switch ((_dst).bytes) { \
dda96d8f
AK		 323 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
324 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
325 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
326 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 327 } \
328 } while (0)
329
3f9f53b0
MG		 330#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
331 do { \
332 unsigned long _tmp; \
333 \
334 __asm__ __volatile__ ( \
335 _PRE_EFLAGS("0", "4", "1") \
336 _op _suffix " %5; " \
337 _POST_EFLAGS("0", "4", "1") \
338 : "=m" (_eflags), "=&r" (_tmp), \
339 "+a" (_rax), "+d" (_rdx) \
340 : "i" (EFLAGS_MASK), "m" ((_src).val), \
341 "a" (_rax), "d" (_rdx)); \
342 } while (0)
343
f6b3597b
AK		 344#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
345 do { \
346 unsigned long _tmp; \
347 \
348 __asm__ __volatile__ ( \
349 _PRE_EFLAGS("0", "5", "1") \
350 "1: \n\t" \
351 _op _suffix " %6; " \
352 "2: \n\t" \
353 _POST_EFLAGS("0", "5", "1") \
354 ".pushsection .fixup,\"ax\" \n\t" \
355 "3: movb $1, %4 \n\t" \
356 "jmp 2b \n\t" \
357 ".popsection \n\t" \
358 _ASM_EXTABLE(1b, 3b) \
359 : "=m" (_eflags), "=&r" (_tmp), \
360 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
361 : "i" (EFLAGS_MASK), "m" ((_src).val), \
362 "a" (_rax), "d" (_rdx)); \
363 } while (0)
364
3f9f53b0 365/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 366#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
367 do { \
368 switch((_src).bytes) { \
369 case 1: \
370 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
371 _eflags, "b"); \
372 break; \
373 case 2: \
374 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
375 _eflags, "w"); \
376 break; \
377 case 4: \
378 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
379 _eflags, "l"); \
380 break; \
381 case 8: \
382 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
383 _eflags, "q")); \
384 break; \
3f9f53b0
MG		 385 } \
386 } while (0)
387
f6b3597b
AK		 388#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
389 do { \
390 switch((_src).bytes) { \
391 case 1: \
392 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
393 _eflags, "b", _ex); \
394 break; \
395 case 2: \
396 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
397 _eflags, "w", _ex); \
398 break; \
399 case 4: \
400 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
401 _eflags, "l", _ex); \
402 break; \
403 case 8: ON64( \
404 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
405 _eflags, "q", _ex)); \
406 break; \
407 } \
408 } while (0)
409
8a76d7f2
JR		 410static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
411 enum x86_intercept intercept,
412 enum x86_intercept_stage stage)
413{
414 struct x86_instruction_info info = {
415 .intercept = intercept,
416 .rep_prefix = ctxt->decode.rep_prefix,
417 .modrm_mod = ctxt->decode.modrm_mod,
418 .modrm_reg = ctxt->decode.modrm_reg,
419 .modrm_rm = ctxt->decode.modrm_rm,
420 .src_val = ctxt->decode.src.val64,
421 .src_bytes = ctxt->decode.src.bytes,
422 .dst_bytes = ctxt->decode.dst.bytes,
423 .ad_bytes = ctxt->decode.ad_bytes,
424 .next_rip = ctxt->eip,
425 };
426
2953538e 427 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 428}
429
ddcb2885
HH		 430static inline unsigned long ad_mask(struct decode_cache *c)
431{
432 return (1UL << (c->ad_bytes << 3)) - 1;
433}
434
6aa8b732 435/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 436static inline unsigned long
437address_mask(struct decode_cache *c, unsigned long reg)
438{
439 if (c->ad_bytes == sizeof(unsigned long))
440 return reg;
441 else
442 return reg & ad_mask(c);
443}
444
445static inline unsigned long
90de84f5 446register_address(struct decode_cache *c, unsigned long reg)
e4706772 447{
90de84f5 448 return address_mask(c, reg);
e4706772
HH		 449}
450
7a957275
HH		 451static inline void
452register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 *reg += inc;
456 else
457 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
458}
6aa8b732 459
7a957275
HH		 460static inline void jmp_rel(struct decode_cache *c, int rel)
461{
462 register_address_increment(c, &c->eip, rel);
463}
098c937b 464
56697687
AK		 465static u32 desc_limit_scaled(struct desc_struct *desc)
466{
467 u32 limit = get_desc_limit(desc);
468
469 return desc->g ? (limit << 12) | 0xfff : limit;
470}
471
7a5b56df
AK		 472static void set_seg_override(struct decode_cache *c, int seg)
473{
474 c->has_seg_override = true;
475 c->seg_override = seg;
476}
477
7b105ca2 478static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 479{
480 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
481 return 0;
482
7b105ca2 483 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 484}
485
90de84f5 486static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
90de84f5 487 struct decode_cache *c)
7a5b56df
AK		 488{
489 if (!c->has_seg_override)
490 return 0;
491
90de84f5 492 return c->seg_override;
7a5b56df
AK		 493}
494
35d3d4a1
AK		 495static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
496 u32 error, bool valid)
54b8486f 497{
da9cb575
AK		 498 ctxt->exception.vector = vec;
499 ctxt->exception.error_code = error;
500 ctxt->exception.error_code_valid = valid;
35d3d4a1 501 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 502}
503
3b88e41a
JR		 504static int emulate_db(struct x86_emulate_ctxt *ctxt)
505{
506 return emulate_exception(ctxt, DB_VECTOR, 0, false);
507}
508
35d3d4a1 509static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 510{
35d3d4a1 511 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 512}
513
618ff15d
AK		 514static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
515{
516 return emulate_exception(ctxt, SS_VECTOR, err, true);
517}
518
35d3d4a1 519static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 520{
35d3d4a1 521 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 522}
523
35d3d4a1 524static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 525{
35d3d4a1 526 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 527}
528
34d1f490
AK		 529static int emulate_de(struct x86_emulate_ctxt *ctxt)
530{
35d3d4a1 531 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 532}
533
1253791d
AK		 534static int emulate_nm(struct x86_emulate_ctxt *ctxt)
535{
536 return emulate_exception(ctxt, NM_VECTOR, 0, false);
537}
538
1aa36616
AK		 539static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
540{
541 u16 selector;
542 struct desc_struct desc;
543
544 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
545 return selector;
546}
547
548static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
549 unsigned seg)
550{
551 u16 dummy;
552 u32 base3;
553 struct desc_struct desc;
554
555 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
556 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
557}
558
3d9b938e 559static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 560 struct segmented_address addr,
3d9b938e 561 unsigned size, bool write, bool fetch,
52fd8b44
AK		 562 ulong *linear)
563{
564 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 565 struct desc_struct desc;
566 bool usable;
52fd8b44 567 ulong la;
618ff15d 568 u32 lim;
1aa36616 569 u16 sel;
618ff15d 570 unsigned cpl, rpl;
52fd8b44 571
7b105ca2 572 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 573 switch (ctxt->mode) {
574 case X86EMUL_MODE_REAL:
575 break;
576 case X86EMUL_MODE_PROT64:
577 if (((signed long)la << 16) >> 16 != la)
578 return emulate_gp(ctxt, 0);
579 break;
580 default:
1aa36616
AK		 581 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
582 addr.seg);
618ff15d
AK		 583 if (!usable)
584 goto bad;
585 /* code segment or read-only data segment */
586 if (((desc.type & 8) || !(desc.type & 2)) && write)
587 goto bad;
588 /* unreadable code segment */
3d9b938e 589 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 590 goto bad;
591 lim = desc_limit_scaled(&desc);
592 if ((desc.type & 8) || !(desc.type & 4)) {
593 /* expand-up segment */
594 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
595 goto bad;
596 } else {
597 /* exapand-down segment */
598 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
599 goto bad;
600 lim = desc.d ? 0xffffffff : 0xffff;
601 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
602 goto bad;
603 }
717746e3 604 cpl = ctxt->ops->cpl(ctxt);
1aa36616 605 rpl = sel & 3;
618ff15d
AK		 606 cpl = max(cpl, rpl);
607 if (!(desc.type & 8)) {
608 /* data segment */
609 if (cpl > desc.dpl)
610 goto bad;
611 } else if ((desc.type & 8) && !(desc.type & 4)) {
612 /* nonconforming code segment */
613 if (cpl != desc.dpl)
614 goto bad;
615 } else if ((desc.type & 8) && (desc.type & 4)) {
616 /* conforming code segment */
617 if (cpl < desc.dpl)
618 goto bad;
619 }
620 break;
621 }
3d9b938e 622 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 623 la &= (u32)-1;
624 *linear = la;
625 return X86EMUL_CONTINUE;
618ff15d
AK		 626bad:
627 if (addr.seg == VCPU_SREG_SS)
628 return emulate_ss(ctxt, addr.seg);
629 else
630 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 631}
632
3d9b938e
NE		 633static int linearize(struct x86_emulate_ctxt *ctxt,
634 struct segmented_address addr,
635 unsigned size, bool write,
636 ulong *linear)
637{
638 return __linearize(ctxt, addr, size, write, false, linear);
639}
640
641
3ca3ac4d
AK		 642static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
643 struct segmented_address addr,
644 void *data,
645 unsigned size)
646{
9fa088f4
AK		 647 int rc;
648 ulong linear;
649
83b8795a 650 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 651 if (rc != X86EMUL_CONTINUE)
652 return rc;
0f65dd70 653 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 654}
655
67cbc90d 656static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt,
2fb53ad8 657 unsigned long eip, u8 *dest)
62266869
AK		 658{
659 struct fetch_cache *fc = &ctxt->decode.fetch;
660 int rc;
2fb53ad8 661 int size, cur_size;
62266869 662
2fb53ad8 663 if (eip == fc->end) {
3d9b938e
NE		 664 unsigned long linear;
665 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 666 cur_size = fc->end - fc->start;
667 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 668 rc = __linearize(ctxt, addr, size, false, true, &linear);
669 if (rc != X86EMUL_CONTINUE)
670 return rc;
ef5d75cc
TY		 671 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
672 size, &ctxt->exception);
3e2815e9 673 if (rc != X86EMUL_CONTINUE)
62266869 674 return rc;
2fb53ad8 675 fc->end += size;
62266869 676 }
2fb53ad8 677 *dest = fc->data[eip - fc->start];
3e2815e9 678 return X86EMUL_CONTINUE;
62266869
AK		 679}
680
681static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
62266869
AK		 682 unsigned long eip, void *dest, unsigned size)
683{
3e2815e9 684 int rc;
62266869 685
eb3c79e6 686 /* x86 instructions are limited to 15 bytes. */
063db061 687 if (eip + size - ctxt->eip > 15)
eb3c79e6 688 return X86EMUL_UNHANDLEABLE;
62266869 689 while (size--) {
ef5d75cc 690 rc = do_insn_fetch_byte(ctxt, eip++, dest++);
3e2815e9 691 if (rc != X86EMUL_CONTINUE)
62266869
AK		 692 return rc;
693 }
3e2815e9 694 return X86EMUL_CONTINUE;
62266869
AK		 695}
696
67cbc90d
TY		 697/* Fetch next part of the instruction being emulated. */
698#define insn_fetch(_type, _size, _eip) \
699({ unsigned long _x; \
ef5d75cc 700 rc = do_insn_fetch(ctxt, (_eip), &_x, (_size)); \
67cbc90d
TY		 701 if (rc != X86EMUL_CONTINUE) \
702 goto done; \
703 (_eip) += (_size); \
704 (_type)_x; \
705})
706
707#define insn_fetch_arr(_arr, _size, _eip) \
ef5d75cc 708({ rc = do_insn_fetch(ctxt, (_eip), _arr, (_size)); \
67cbc90d
TY		 709 if (rc != X86EMUL_CONTINUE) \
710 goto done; \
711 (_eip) += (_size); \
712})
713
1e3c5cb0
RR		 714/*
715 * Given the 'reg' portion of a ModRM byte, and a register block, return a
716 * pointer into the block that addresses the relevant register.
717 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
718 */
719static void *decode_register(u8 modrm_reg, unsigned long *regs,
720 int highbyte_regs)
6aa8b732
AK		 721{
722 void *p;
723
724 p = &regs[modrm_reg];
725 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
726 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
727 return p;
728}
729
730static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 731 struct segmented_address addr,
6aa8b732
AK		 732 u16 *size, unsigned long *address, int op_bytes)
733{
734 int rc;
735
736 if (op_bytes == 2)
737 op_bytes = 3;
738 *address = 0;
3ca3ac4d 739 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 740 if (rc != X86EMUL_CONTINUE)
6aa8b732 741 return rc;
30b31ab6 742 addr.ea += 2;
3ca3ac4d 743 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 744 return rc;
745}
746
bbe9abbd
NK		 747static int test_cc(unsigned int condition, unsigned int flags)
748{
749 int rc = 0;
750
751 switch ((condition & 15) >> 1) {
752 case 0: /* o */
753 rc |= (flags & EFLG_OF);
754 break;
755 case 1: /* b/c/nae */
756 rc |= (flags & EFLG_CF);
757 break;
758 case 2: /* z/e */
759 rc |= (flags & EFLG_ZF);
760 break;
761 case 3: /* be/na */
762 rc |= (flags & (EFLG_CF|EFLG_ZF));
763 break;
764 case 4: /* s */
765 rc |= (flags & EFLG_SF);
766 break;
767 case 5: /* p/pe */
768 rc |= (flags & EFLG_PF);
769 break;
770 case 7: /* le/ng */
771 rc |= (flags & EFLG_ZF);
772 /* fall through */
773 case 6: /* l/nge */
774 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
775 break;
776 }
777
778 /* Odd condition identifiers (lsb == 1) have inverted sense. */
779 return (!!rc ^ (condition & 1));
780}
781
91ff3cb4
AK		 782static void fetch_register_operand(struct operand *op)
783{
784 switch (op->bytes) {
785 case 1:
786 op->val = *(u8 *)op->addr.reg;
787 break;
788 case 2:
789 op->val = *(u16 *)op->addr.reg;
790 break;
791 case 4:
792 op->val = *(u32 *)op->addr.reg;
793 break;
794 case 8:
795 op->val = *(u64 *)op->addr.reg;
796 break;
797 }
798}
799
1253791d
AK		 800static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
801{
802 ctxt->ops->get_fpu(ctxt);
803 switch (reg) {
804 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
805 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
806 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
807 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
808 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
809 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
810 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
811 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
812#ifdef CONFIG_X86_64
813 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
814 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
815 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
816 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
817 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
818 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
819 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
820 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
821#endif
822 default: BUG();
823 }
824 ctxt->ops->put_fpu(ctxt);
825}
826
827static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
828 int reg)
829{
830 ctxt->ops->get_fpu(ctxt);
831 switch (reg) {
832 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
833 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
834 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
835 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
836 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
837 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
838 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
839 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
840#ifdef CONFIG_X86_64
841 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
842 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
843 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
844 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
845 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
846 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
847 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
848 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
849#endif
850 default: BUG();
851 }
852 ctxt->ops->put_fpu(ctxt);
853}
854
855static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
856 struct operand *op,
3c118e24 857 struct decode_cache *c,
3c118e24
AK		 858 int inhibit_bytereg)
859{
33615aa9 860 unsigned reg = c->modrm_reg;
9f1ef3f8 861 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 862
863 if (!(c->d & ModRM))
864 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 865
866 if (c->d & Sse) {
867 op->type = OP_XMM;
868 op->bytes = 16;
869 op->addr.xmm = reg;
870 read_sse_reg(ctxt, &op->vec_val, reg);
871 return;
872 }
873
3c118e24
AK		 874 op->type = OP_REG;
875 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 876 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 877 op->bytes = 1;
878 } else {
1a6440ae 879 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 880 op->bytes = c->op_bytes;
3c118e24 881 }
91ff3cb4 882 fetch_register_operand(op);
3c118e24
AK		 883 op->orig_val = op->val;
884}
885
1c73ef66 886static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 887 struct operand *op)
1c73ef66
AK		 888{
889 struct decode_cache *c = &ctxt->decode;
890 u8 sib;
f5b4edcd 891 int index_reg = 0, base_reg = 0, scale;
3e2815e9 892 int rc = X86EMUL_CONTINUE;
2dbd0dd7 893 ulong modrm_ea = 0;
1c73ef66
AK		 894
895 if (c->rex_prefix) {
896 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
897 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
898 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
899 }
900
901 c->modrm = insn_fetch(u8, 1, c->eip);
902 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
903 c->modrm_reg |= (c->modrm & 0x38) >> 3;
904 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 905 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 906
907 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 908 op->type = OP_REG;
909 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
910 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 911 c->regs, c->d & ByteOp);
1253791d
AK		 912 if (c->d & Sse) {
913 op->type = OP_XMM;
914 op->bytes = 16;
915 op->addr.xmm = c->modrm_rm;
916 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
917 return rc;
918 }
2dbd0dd7 919 fetch_register_operand(op);
1c73ef66
AK		 920 return rc;
921 }
922
2dbd0dd7
AK		 923 op->type = OP_MEM;
924
1c73ef66
AK		 925 if (c->ad_bytes == 2) {
926 unsigned bx = c->regs[VCPU_REGS_RBX];
927 unsigned bp = c->regs[VCPU_REGS_RBP];
928 unsigned si = c->regs[VCPU_REGS_RSI];
929 unsigned di = c->regs[VCPU_REGS_RDI];
930
931 /* 16-bit ModR/M decode. */
932 switch (c->modrm_mod) {
933 case 0:
934 if (c->modrm_rm == 6)
2dbd0dd7 935 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 936 break;
937 case 1:
2dbd0dd7 938 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 939 break;
940 case 2:
2dbd0dd7 941 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 942 break;
943 }
944 switch (c->modrm_rm) {
945 case 0:
2dbd0dd7 946 modrm_ea += bx + si;
1c73ef66
AK		 947 break;
948 case 1:
2dbd0dd7 949 modrm_ea += bx + di;
1c73ef66
AK		 950 break;
951 case 2:
2dbd0dd7 952 modrm_ea += bp + si;
1c73ef66
AK		 953 break;
954 case 3:
2dbd0dd7 955 modrm_ea += bp + di;
1c73ef66
AK		 956 break;
957 case 4:
2dbd0dd7 958 modrm_ea += si;
1c73ef66
AK		 959 break;
960 case 5:
2dbd0dd7 961 modrm_ea += di;
1c73ef66
AK		 962 break;
963 case 6:
964 if (c->modrm_mod != 0)
2dbd0dd7 965 modrm_ea += bp;
1c73ef66
AK		 966 break;
967 case 7:
2dbd0dd7 968 modrm_ea += bx;
1c73ef66
AK		 969 break;
970 }
971 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
972 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 973 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 974 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 975 } else {
976 /* 32/64-bit ModR/M decode. */
84411d85 977 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 978 sib = insn_fetch(u8, 1, c->eip);
979 index_reg |= (sib >> 3) & 7;
980 base_reg |= sib & 7;
981 scale = sib >> 6;
982
dc71d0f1 983 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 984 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 985 else
2dbd0dd7 986 modrm_ea += c->regs[base_reg];
dc71d0f1 987 if (index_reg != 4)
2dbd0dd7 988 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 989 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
990 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 991 c->rip_relative = 1;
84411d85 992 } else
2dbd0dd7 993 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 994 switch (c->modrm_mod) {
995 case 0:
996 if (c->modrm_rm == 5)
2dbd0dd7 997 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 998 break;
999 case 1:
2dbd0dd7 1000 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 1001 break;
1002 case 2:
2dbd0dd7 1003 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1004 break;
1005 }
1006 }
90de84f5 1007 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1008done:
1009 return rc;
1010}
1011
1012static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1013 struct operand *op)
1c73ef66
AK		 1014{
1015 struct decode_cache *c = &ctxt->decode;
3e2815e9 1016 int rc = X86EMUL_CONTINUE;
1c73ef66 1017
2dbd0dd7 1018 op->type = OP_MEM;
1c73ef66
AK		 1019 switch (c->ad_bytes) {
1020 case 2:
90de84f5 1021 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1022 break;
1023 case 4:
90de84f5 1024 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1025 break;
1026 case 8:
90de84f5 1027 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1028 break;
1029 }
1030done:
1031 return rc;
1032}
1033
35c843c4
WY		 1034static void fetch_bit_operand(struct decode_cache *c)
1035{
7129eeca 1036 long sv = 0, mask;
35c843c4 1037
3885f18f 1038 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1039 mask = ~(c->dst.bytes * 8 - 1);
1040
1041 if (c->src.bytes == 2)
1042 sv = (s16)c->src.val & (s16)mask;
1043 else if (c->src.bytes == 4)
1044 sv = (s32)c->src.val & (s32)mask;
1045
90de84f5 1046 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1047 }
ba7ff2b7
WY		 1048
1049 /* only subword offset */
1050 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1051}
1052
dde7e6d1 1053static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1054 unsigned long addr, void *dest, unsigned size)
6aa8b732 1055{
dde7e6d1
AK		 1056 int rc;
1057 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1058
dde7e6d1
AK		 1059 while (size) {
1060 int n = min(size, 8u);
1061 size -= n;
1062 if (mc->pos < mc->end)
1063 goto read_cached;
5cd21917 1064
7b105ca2
TY		 1065 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1066 &ctxt->exception);
dde7e6d1
AK		 1067 if (rc != X86EMUL_CONTINUE)
1068 return rc;
1069 mc->end += n;
6aa8b732 1070
dde7e6d1
AK		 1071 read_cached:
1072 memcpy(dest, mc->data + mc->pos, n);
1073 mc->pos += n;
1074 dest += n;
1075 addr += n;
6aa8b732 1076 }
dde7e6d1
AK		 1077 return X86EMUL_CONTINUE;
1078}
6aa8b732 1079
3ca3ac4d
AK		 1080static int segmented_read(struct x86_emulate_ctxt *ctxt,
1081 struct segmented_address addr,
1082 void *data,
1083 unsigned size)
1084{
9fa088f4
AK		 1085 int rc;
1086 ulong linear;
1087
83b8795a 1088 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1089 if (rc != X86EMUL_CONTINUE)
1090 return rc;
7b105ca2 1091 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1092}
1093
1094static int segmented_write(struct x86_emulate_ctxt *ctxt,
1095 struct segmented_address addr,
1096 const void *data,
1097 unsigned size)
1098{
9fa088f4
AK		 1099 int rc;
1100 ulong linear;
1101
83b8795a 1102 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1103 if (rc != X86EMUL_CONTINUE)
1104 return rc;
0f65dd70
AK		 1105 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1106 &ctxt->exception);
3ca3ac4d
AK		 1107}
1108
1109static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1110 struct segmented_address addr,
1111 const void *orig_data, const void *data,
1112 unsigned size)
1113{
9fa088f4
AK		 1114 int rc;
1115 ulong linear;
1116
83b8795a 1117 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1118 if (rc != X86EMUL_CONTINUE)
1119 return rc;
0f65dd70
AK		 1120 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1121 size, &ctxt->exception);
3ca3ac4d
AK		 1122}
1123
dde7e6d1 1124static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1125 unsigned int size, unsigned short port,
1126 void *dest)
1127{
1128 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1129
dde7e6d1
AK		 1130 if (rc->pos == rc->end) { /* refill pio read ahead */
1131 struct decode_cache *c = &ctxt->decode;
1132 unsigned int in_page, n;
1133 unsigned int count = c->rep_prefix ?
1134 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1135 in_page = (ctxt->eflags & EFLG_DF) ?
1136 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1137 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1138 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1139 count);
1140 if (n == 0)
1141 n = 1;
1142 rc->pos = rc->end = 0;
7b105ca2 1143 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1144 return 0;
1145 rc->end = n * size;
6aa8b732
AK		 1146 }
1147
dde7e6d1
AK		 1148 memcpy(dest, rc->data + rc->pos, size);
1149 rc->pos += size;
1150 return 1;
1151}
6aa8b732 1152
dde7e6d1 1153static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1154 u16 selector, struct desc_ptr *dt)
1155{
7b105ca2
TY		 1156 struct x86_emulate_ops *ops = ctxt->ops;
1157
dde7e6d1
AK		 1158 if (selector & 1 << 2) {
1159 struct desc_struct desc;
1aa36616
AK		 1160 u16 sel;
1161
dde7e6d1 1162 memset (dt, 0, sizeof *dt);
1aa36616 1163 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1164 return;
e09d082c 1165
dde7e6d1
AK		 1166 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1167 dt->address = get_desc_base(&desc);
1168 } else
4bff1e86 1169 ops->get_gdt(ctxt, dt);
dde7e6d1 1170}
120df890 1171
dde7e6d1
AK		 1172/* allowed just for 8 bytes segments */
1173static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1174 u16 selector, struct desc_struct *desc)
1175{
1176 struct desc_ptr dt;
1177 u16 index = selector >> 3;
dde7e6d1 1178 ulong addr;
120df890 1179
7b105ca2 1180 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1181
35d3d4a1
AK		 1182 if (dt.size < index * 8 + 7)
1183 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1184
7b105ca2
TY		 1185 addr = dt.address + index * 8;
1186 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1187 &ctxt->exception);
dde7e6d1 1188}
ef65c889 1189
dde7e6d1
AK		 1190/* allowed just for 8 bytes segments */
1191static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1192 u16 selector, struct desc_struct *desc)
1193{
1194 struct desc_ptr dt;
1195 u16 index = selector >> 3;
dde7e6d1 1196 ulong addr;
6aa8b732 1197
7b105ca2 1198 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1199
35d3d4a1
AK		 1200 if (dt.size < index * 8 + 7)
1201 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1202
dde7e6d1 1203 addr = dt.address + index * 8;
7b105ca2
TY		 1204 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1205 &ctxt->exception);
dde7e6d1 1206}
c7e75a3d 1207
5601d05b 1208/* Does not support long mode */
dde7e6d1 1209static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1210 u16 selector, int seg)
1211{
1212 struct desc_struct seg_desc;
1213 u8 dpl, rpl, cpl;
1214 unsigned err_vec = GP_VECTOR;
1215 u32 err_code = 0;
1216 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1217 int ret;
69f55cb1 1218
dde7e6d1 1219 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1220
dde7e6d1
AK		 1221 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1222 || ctxt->mode == X86EMUL_MODE_REAL) {
1223 /* set real mode segment descriptor */
1224 set_desc_base(&seg_desc, selector << 4);
1225 set_desc_limit(&seg_desc, 0xffff);
1226 seg_desc.type = 3;
1227 seg_desc.p = 1;
1228 seg_desc.s = 1;
1229 goto load;
1230 }
1231
1232 /* NULL selector is not valid for TR, CS and SS */
1233 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1234 && null_selector)
1235 goto exception;
1236
1237 /* TR should be in GDT only */
1238 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1239 goto exception;
1240
1241 if (null_selector) /* for NULL selector skip all following checks */
1242 goto load;
1243
7b105ca2 1244 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1245 if (ret != X86EMUL_CONTINUE)
1246 return ret;
1247
1248 err_code = selector & 0xfffc;
1249 err_vec = GP_VECTOR;
1250
1251 /* can't load system descriptor into segment selecor */
1252 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1253 goto exception;
1254
1255 if (!seg_desc.p) {
1256 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1257 goto exception;
1258 }
1259
1260 rpl = selector & 3;
1261 dpl = seg_desc.dpl;
7b105ca2 1262 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1263
1264 switch (seg) {
1265 case VCPU_SREG_SS:
1266 /*
1267 * segment is not a writable data segment or segment
1268 * selector's RPL != CPL or segment selector's RPL != CPL
1269 */
1270 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1271 goto exception;
6aa8b732 1272 break;
dde7e6d1
AK		 1273 case VCPU_SREG_CS:
1274 if (!(seg_desc.type & 8))
1275 goto exception;
1276
1277 if (seg_desc.type & 4) {
1278 /* conforming */
1279 if (dpl > cpl)
1280 goto exception;
1281 } else {
1282 /* nonconforming */
1283 if (rpl > cpl || dpl != cpl)
1284 goto exception;
1285 }
1286 /* CS(RPL) <- CPL */
1287 selector = (selector & 0xfffc) | cpl;
6aa8b732 1288 break;
dde7e6d1
AK		 1289 case VCPU_SREG_TR:
1290 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1291 goto exception;
1292 break;
1293 case VCPU_SREG_LDTR:
1294 if (seg_desc.s || seg_desc.type != 2)
1295 goto exception;
1296 break;
1297 default: /* DS, ES, FS, or GS */
4e62417b 1298 /*
dde7e6d1
AK		 1299 * segment is not a data or readable code segment or
1300 * ((segment is a data or nonconforming code segment)
1301 * and (both RPL and CPL > DPL))
4e62417b 1302 */
dde7e6d1
AK		 1303 if ((seg_desc.type & 0xa) == 0x8 ||
1304 (((seg_desc.type & 0xc) != 0xc) &&
1305 (rpl > dpl && cpl > dpl)))
1306 goto exception;
6aa8b732 1307 break;
dde7e6d1
AK		 1308 }
1309
1310 if (seg_desc.s) {
1311 /* mark segment as accessed */
1312 seg_desc.type |= 1;
7b105ca2 1313 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1314 if (ret != X86EMUL_CONTINUE)
1315 return ret;
1316 }
1317load:
7b105ca2 1318 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1319 return X86EMUL_CONTINUE;
1320exception:
1321 emulate_exception(ctxt, err_vec, err_code, true);
1322 return X86EMUL_PROPAGATE_FAULT;
1323}
1324
31be40b3
WY		 1325static void write_register_operand(struct operand *op)
1326{
1327 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1328 switch (op->bytes) {
1329 case 1:
1330 *(u8 *)op->addr.reg = (u8)op->val;
1331 break;
1332 case 2:
1333 *(u16 *)op->addr.reg = (u16)op->val;
1334 break;
1335 case 4:
1336 *op->addr.reg = (u32)op->val;
1337 break; /* 64b: zero-extend */
1338 case 8:
1339 *op->addr.reg = op->val;
1340 break;
1341 }
1342}
1343
adddcecf 1344static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1345{
1346 int rc;
1347 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1348
1349 switch (c->dst.type) {
1350 case OP_REG:
31be40b3 1351 write_register_operand(&c->dst);
6aa8b732 1352 break;
dde7e6d1
AK		 1353 case OP_MEM:
1354 if (c->lock_prefix)
3ca3ac4d
AK		 1355 rc = segmented_cmpxchg(ctxt,
1356 c->dst.addr.mem,
1357 &c->dst.orig_val,
1358 &c->dst.val,
1359 c->dst.bytes);
341de7e3 1360 else
3ca3ac4d
AK		 1361 rc = segmented_write(ctxt,
1362 c->dst.addr.mem,
1363 &c->dst.val,
1364 c->dst.bytes);
dde7e6d1
AK		 1365 if (rc != X86EMUL_CONTINUE)
1366 return rc;
a682e354 1367 break;
1253791d
AK		 1368 case OP_XMM:
1369 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1370 break;
dde7e6d1
AK		 1371 case OP_NONE:
1372 /* no writeback */
414e6277 1373 break;
dde7e6d1 1374 default:
414e6277 1375 break;
6aa8b732 1376 }
dde7e6d1
AK		 1377 return X86EMUL_CONTINUE;
1378}
6aa8b732 1379
4487b3b4 1380static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1381{
1382 struct decode_cache *c = &ctxt->decode;
4179bb02 1383 struct segmented_address addr;
0dc8d10f 1384
dde7e6d1 1385 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1386 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1387 addr.seg = VCPU_SREG_SS;
1388
1389 /* Disable writeback. */
1390 c->dst.type = OP_NONE;
1391 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1392}
69f55cb1 1393
dde7e6d1 1394static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1395 void *dest, int len)
1396{
1397 struct decode_cache *c = &ctxt->decode;
1398 int rc;
90de84f5 1399 struct segmented_address addr;
8b4caf66 1400
90de84f5
AK		 1401 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1402 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1403 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1404 if (rc != X86EMUL_CONTINUE)
1405 return rc;
1406
1407 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1408 return rc;
8b4caf66
LV		 1409}
1410
c54fe504
TY		 1411static int em_pop(struct x86_emulate_ctxt *ctxt)
1412{
1413 struct decode_cache *c = &ctxt->decode;
1414
3b9be3bf 1415 return emulate_pop(ctxt, &c->dst.val, c->op_bytes);
c54fe504
TY		 1416}
1417
dde7e6d1 1418static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1419 void *dest, int len)
9de41573
GN		 1420{
1421 int rc;
dde7e6d1
AK		 1422 unsigned long val, change_mask;
1423 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1424 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1425
3b9be3bf 1426 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1427 if (rc != X86EMUL_CONTINUE)
1428 return rc;
9de41573 1429
dde7e6d1
AK		 1430 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1431 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1432
dde7e6d1
AK		 1433 switch(ctxt->mode) {
1434 case X86EMUL_MODE_PROT64:
1435 case X86EMUL_MODE_PROT32:
1436 case X86EMUL_MODE_PROT16:
1437 if (cpl == 0)
1438 change_mask |= EFLG_IOPL;
1439 if (cpl <= iopl)
1440 change_mask |= EFLG_IF;
1441 break;
1442 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1443 if (iopl < 3)
1444 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1445 change_mask |= EFLG_IF;
1446 break;
1447 default: /* real mode */
1448 change_mask |= (EFLG_IOPL | EFLG_IF);
1449 break;
9de41573 1450 }
dde7e6d1
AK		 1451
1452 *(unsigned long *)dest =
1453 (ctxt->eflags & ~change_mask) | (val & change_mask);
1454
1455 return rc;
9de41573
GN		 1456}
1457
62aaa2f0
TY		 1458static int em_popf(struct x86_emulate_ctxt *ctxt)
1459{
1460 struct decode_cache *c = &ctxt->decode;
1461
1462 c->dst.type = OP_REG;
1463 c->dst.addr.reg = &ctxt->eflags;
1464 c->dst.bytes = c->op_bytes;
7b105ca2 1465 return emulate_popf(ctxt, &c->dst.val, c->op_bytes);
62aaa2f0
TY		 1466}
1467
7b105ca2 1468static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1469{
dde7e6d1 1470 struct decode_cache *c = &ctxt->decode;
7b262e90 1471
1aa36616 1472 c->src.val = get_segment_selector(ctxt, seg);
7b262e90 1473
4487b3b4 1474 return em_push(ctxt);
7b262e90
GN		 1475}
1476
7b105ca2 1477static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1478{
dde7e6d1
AK		 1479 struct decode_cache *c = &ctxt->decode;
1480 unsigned long selector;
1481 int rc;
38ba30ba 1482
3b9be3bf 1483 rc = emulate_pop(ctxt, &selector, c->op_bytes);
dde7e6d1
AK		 1484 if (rc != X86EMUL_CONTINUE)
1485 return rc;
1486
7b105ca2 1487 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1488 return rc;
38ba30ba
GN		 1489}
1490
b96a7fad 1491static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1492{
dde7e6d1
AK		 1493 struct decode_cache *c = &ctxt->decode;
1494 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1495 int rc = X86EMUL_CONTINUE;
1496 int reg = VCPU_REGS_RAX;
38ba30ba 1497
dde7e6d1
AK		 1498 while (reg <= VCPU_REGS_RDI) {
1499 (reg == VCPU_REGS_RSP) ?
1500 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1501
4487b3b4 1502 rc = em_push(ctxt);
dde7e6d1
AK		 1503 if (rc != X86EMUL_CONTINUE)
1504 return rc;
38ba30ba 1505
dde7e6d1 1506 ++reg;
38ba30ba 1507 }
38ba30ba 1508
dde7e6d1 1509 return rc;
38ba30ba
GN		 1510}
1511
62aaa2f0
TY		 1512static int em_pushf(struct x86_emulate_ctxt *ctxt)
1513{
1514 struct decode_cache *c = &ctxt->decode;
1515
1516 c->src.val = (unsigned long)ctxt->eflags;
1517 return em_push(ctxt);
1518}
1519
b96a7fad 1520static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1521{
dde7e6d1
AK		 1522 struct decode_cache *c = &ctxt->decode;
1523 int rc = X86EMUL_CONTINUE;
1524 int reg = VCPU_REGS_RDI;
38ba30ba 1525
dde7e6d1
AK		 1526 while (reg >= VCPU_REGS_RAX) {
1527 if (reg == VCPU_REGS_RSP) {
1528 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1529 c->op_bytes);
1530 --reg;
1531 }
38ba30ba 1532
3b9be3bf 1533 rc = emulate_pop(ctxt, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1534 if (rc != X86EMUL_CONTINUE)
1535 break;
1536 --reg;
38ba30ba 1537 }
dde7e6d1 1538 return rc;
38ba30ba
GN		 1539}
1540
7b105ca2 1541int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1542{
1543 struct decode_cache *c = &ctxt->decode;
7b105ca2 1544 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1545 int rc;
6e154e56
MG		 1546 struct desc_ptr dt;
1547 gva_t cs_addr;
1548 gva_t eip_addr;
1549 u16 cs, eip;
6e154e56
MG		 1550
1551 /* TODO: Add limit checks */
1552 c->src.val = ctxt->eflags;
4487b3b4 1553 rc = em_push(ctxt);
5c56e1cf
AK		 1554 if (rc != X86EMUL_CONTINUE)
1555 return rc;
6e154e56
MG		 1556
1557 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1558
1aa36616 1559 c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1560 rc = em_push(ctxt);
5c56e1cf
AK		 1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
6e154e56
MG		 1563
1564 c->src.val = c->eip;
4487b3b4 1565 rc = em_push(ctxt);
5c56e1cf
AK		 1566 if (rc != X86EMUL_CONTINUE)
1567 return rc;
1568
4bff1e86 1569 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1570
1571 eip_addr = dt.address + (irq << 2);
1572 cs_addr = dt.address + (irq << 2) + 2;
1573
0f65dd70 1574 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
1577
0f65dd70 1578 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
1581
7b105ca2 1582 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1583 if (rc != X86EMUL_CONTINUE)
1584 return rc;
1585
1586 c->eip = eip;
1587
1588 return rc;
1589}
1590
7b105ca2 1591static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1592{
1593 switch(ctxt->mode) {
1594 case X86EMUL_MODE_REAL:
7b105ca2 1595 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1596 case X86EMUL_MODE_VM86:
1597 case X86EMUL_MODE_PROT16:
1598 case X86EMUL_MODE_PROT32:
1599 case X86EMUL_MODE_PROT64:
1600 default:
1601 /* Protected mode interrupts unimplemented yet */
1602 return X86EMUL_UNHANDLEABLE;
1603 }
1604}
1605
7b105ca2 1606static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1607{
dde7e6d1
AK		 1608 struct decode_cache *c = &ctxt->decode;
1609 int rc = X86EMUL_CONTINUE;
1610 unsigned long temp_eip = 0;
1611 unsigned long temp_eflags = 0;
1612 unsigned long cs = 0;
1613 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1614 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1615 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1616 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1617
dde7e6d1 1618 /* TODO: Add stack limit check */
38ba30ba 1619
3b9be3bf 1620 rc = emulate_pop(ctxt, &temp_eip, c->op_bytes);
38ba30ba 1621
dde7e6d1
AK		 1622 if (rc != X86EMUL_CONTINUE)
1623 return rc;
38ba30ba 1624
35d3d4a1
AK		 1625 if (temp_eip & ~0xffff)
1626 return emulate_gp(ctxt, 0);
38ba30ba 1627
3b9be3bf 1628 rc = emulate_pop(ctxt, &cs, c->op_bytes);
38ba30ba 1629
dde7e6d1
AK		 1630 if (rc != X86EMUL_CONTINUE)
1631 return rc;
38ba30ba 1632
3b9be3bf 1633 rc = emulate_pop(ctxt, &temp_eflags, c->op_bytes);
38ba30ba 1634
dde7e6d1
AK		 1635 if (rc != X86EMUL_CONTINUE)
1636 return rc;
38ba30ba 1637
7b105ca2 1638 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1639
dde7e6d1
AK		 1640 if (rc != X86EMUL_CONTINUE)
1641 return rc;
38ba30ba 1642
dde7e6d1 1643 c->eip = temp_eip;
38ba30ba 1644
38ba30ba 1645
dde7e6d1
AK		 1646 if (c->op_bytes == 4)
1647 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1648 else if (c->op_bytes == 2) {
1649 ctxt->eflags &= ~0xffff;
1650 ctxt->eflags |= temp_eflags;
38ba30ba 1651 }
dde7e6d1
AK		 1652
1653 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1654 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1655
1656 return rc;
38ba30ba
GN		 1657}
1658
e01991e7 1659static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1660{
dde7e6d1
AK		 1661 switch(ctxt->mode) {
1662 case X86EMUL_MODE_REAL:
7b105ca2 1663 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1664 case X86EMUL_MODE_VM86:
1665 case X86EMUL_MODE_PROT16:
1666 case X86EMUL_MODE_PROT32:
1667 case X86EMUL_MODE_PROT64:
c37eda13 1668 default:
dde7e6d1
AK		 1669 /* iret from protected mode unimplemented yet */
1670 return X86EMUL_UNHANDLEABLE;
c37eda13 1671 }
c37eda13
WY		 1672}
1673
d2f62766
TY		 1674static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1675{
1676 struct decode_cache *c = &ctxt->decode;
1677 int rc;
1678 unsigned short sel;
1679
1680 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1681
7b105ca2 1682 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1683 if (rc != X86EMUL_CONTINUE)
1684 return rc;
1685
1686 c->eip = 0;
1687 memcpy(&c->eip, c->src.valptr, c->op_bytes);
1688 return X86EMUL_CONTINUE;
1689}
1690
51187683 1691static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1692{
1693 struct decode_cache *c = &ctxt->decode;
1694
3b9be3bf 1695 return emulate_pop(ctxt, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1696}
1697
51187683 1698static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1699{
05f086f8 1700 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1701 switch (c->modrm_reg) {
1702 case 0: /* rol */
05f086f8 1703 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1704 break;
1705 case 1: /* ror */
05f086f8 1706 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1707 break;
1708 case 2: /* rcl */
05f086f8 1709 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1710 break;
1711 case 3: /* rcr */
05f086f8 1712 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1713 break;
1714 case 4: /* sal/shl */
1715 case 6: /* sal/shl */
05f086f8 1716 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1717 break;
1718 case 5: /* shr */
05f086f8 1719 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1720 break;
1721 case 7: /* sar */
05f086f8 1722 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1723 break;
1724 }
51187683 1725 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1726}
1727
51187683 1728static int em_grp3(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1729{
1730 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1731 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1732 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1733 u8 de = 0;
8cdbd2c9
LV		 1734
1735 switch (c->modrm_reg) {
1736 case 0 ... 1: /* test */
05f086f8 1737 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1738 break;
1739 case 2: /* not */
1740 c->dst.val = ~c->dst.val;
1741 break;
1742 case 3: /* neg */
05f086f8 1743 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1744 break;
3f9f53b0
MG		 1745 case 4: /* mul */
1746 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1747 break;
1748 case 5: /* imul */
1749 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1750 break;
1751 case 6: /* div */
34d1f490
AK		 1752 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1753 ctxt->eflags, de);
3f9f53b0
MG		 1754 break;
1755 case 7: /* idiv */
34d1f490
AK		 1756 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1757 ctxt->eflags, de);
3f9f53b0 1758 break;
8cdbd2c9 1759 default:
8c5eee30 1760 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1761 }
34d1f490
AK		 1762 if (de)
1763 return emulate_de(ctxt);
8c5eee30 1764 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1765}
1766
51187683 1767static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1768{
1769 struct decode_cache *c = &ctxt->decode;
4179bb02 1770 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1771
1772 switch (c->modrm_reg) {
1773 case 0: /* inc */
05f086f8 1774 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1775 break;
1776 case 1: /* dec */
05f086f8 1777 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1778 break;
d19292e4
MG		 1779 case 2: /* call near abs */ {
1780 long int old_eip;
1781 old_eip = c->eip;
1782 c->eip = c->src.val;
1783 c->src.val = old_eip;
4487b3b4 1784 rc = em_push(ctxt);
d19292e4
MG		 1785 break;
1786 }
8cdbd2c9 1787 case 4: /* jmp abs */
fd60754e 1788 c->eip = c->src.val;
8cdbd2c9 1789 break;
d2f62766
TY		 1790 case 5: /* jmp far */
1791 rc = em_jmp_far(ctxt);
1792 break;
8cdbd2c9 1793 case 6: /* push */
4487b3b4 1794 rc = em_push(ctxt);
8cdbd2c9 1795 break;
8cdbd2c9 1796 }
4179bb02 1797 return rc;
8cdbd2c9
LV		 1798}
1799
51187683 1800static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1801{
1802 struct decode_cache *c = &ctxt->decode;
16518d5a 1803 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1804
1805 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1806 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1807 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1808 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1809 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1810 } else {
16518d5a
AK		 1811 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1812 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1813
05f086f8 1814 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1815 }
1b30eaa8 1816 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1817}
1818
e01991e7 1819static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea
AK		 1820{
1821 struct decode_cache *c = &ctxt->decode;
1822 int rc;
1823 unsigned long cs;
1824
3b9be3bf 1825 rc = emulate_pop(ctxt, &c->eip, c->op_bytes);
1b30eaa8 1826 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1827 return rc;
1828 if (c->op_bytes == 4)
1829 c->eip = (u32)c->eip;
3b9be3bf 1830 rc = emulate_pop(ctxt, &cs, c->op_bytes);
1b30eaa8 1831 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1832 return rc;
7b105ca2 1833 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1834 return rc;
1835}
1836
7b105ca2 1837static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
09b5f4d3
WY		 1838{
1839 struct decode_cache *c = &ctxt->decode;
1840 unsigned short sel;
1841 int rc;
1842
1843 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1844
7b105ca2 1845 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
1849 c->dst.val = c->src.val;
1850 return rc;
1851}
1852
7b105ca2 1853static void
e66bb2cc 1854setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1855 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1856{
1aa36616
AK		 1857 u16 selector;
1858
79168fd1 1859 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1860 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1861 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1862
1863 cs->l = 0; /* will be adjusted later */
79168fd1 1864 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1865 cs->g = 1; /* 4kb granularity */
79168fd1 1866 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1867 cs->type = 0x0b; /* Read, Execute, Accessed */
1868 cs->s = 1;
1869 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1870 cs->p = 1;
1871 cs->d = 1;
e66bb2cc 1872
79168fd1
GN		 1873 set_desc_base(ss, 0); /* flat segment */
1874 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1875 ss->g = 1; /* 4kb granularity */
1876 ss->s = 1;
1877 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1878 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1879 ss->dpl = 0;
79168fd1 1880 ss->p = 1;
e66bb2cc
AP		 1881}
1882
e01991e7 1883static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc
AP		 1884{
1885 struct decode_cache *c = &ctxt->decode;
7b105ca2 1886 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1887 struct desc_struct cs, ss;
e66bb2cc 1888 u64 msr_data;
79168fd1 1889 u16 cs_sel, ss_sel;
c2ad2bb3 1890 u64 efer = 0;
e66bb2cc
AP		 1891
1892 /* syscall is not available in real mode */
2e901c4c 1893 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1894 ctxt->mode == X86EMUL_MODE_VM86)
1895 return emulate_ud(ctxt);
e66bb2cc 1896
c2ad2bb3 1897 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1898 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1899
717746e3 1900 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1901 msr_data >>= 32;
79168fd1
GN		 1902 cs_sel = (u16)(msr_data & 0xfffc);
1903 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1904
c2ad2bb3 1905 if (efer & EFER_LMA) {
79168fd1 1906 cs.d = 0;
e66bb2cc
AP		 1907 cs.l = 1;
1908 }
1aa36616
AK		 1909 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1910 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc
AP		 1911
1912 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1913 if (efer & EFER_LMA) {
e66bb2cc
AP		 1914#ifdef CONFIG_X86_64
1915 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1916
717746e3 1917 ops->get_msr(ctxt,
3fb1b5db
GN		 1918 ctxt->mode == X86EMUL_MODE_PROT64 ?
1919 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1920 c->eip = msr_data;
1921
717746e3 1922 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1923 ctxt->eflags &= ~(msr_data | EFLG_RF);
1924#endif
1925 } else {
1926 /* legacy mode */
717746e3 1927 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1928 c->eip = (u32)msr_data;
1929
1930 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1931 }
1932
e54cfa97 1933 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1934}
1935
e01991e7 1936static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352
AP		 1937{
1938 struct decode_cache *c = &ctxt->decode;
7b105ca2 1939 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1940 struct desc_struct cs, ss;
8c604352 1941 u64 msr_data;
79168fd1 1942 u16 cs_sel, ss_sel;
c2ad2bb3 1943 u64 efer = 0;
8c604352 1944
7b105ca2 1945 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1946 /* inject #GP if in real mode */
35d3d4a1
AK		 1947 if (ctxt->mode == X86EMUL_MODE_REAL)
1948 return emulate_gp(ctxt, 0);
8c604352
AP		 1949
1950 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1951 * Therefore, we inject an #UD.
1952 */
35d3d4a1
AK		 1953 if (ctxt->mode == X86EMUL_MODE_PROT64)
1954 return emulate_ud(ctxt);
8c604352 1955
7b105ca2 1956 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1957
717746e3 1958 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1959 switch (ctxt->mode) {
1960 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1961 if ((msr_data & 0xfffc) == 0x0)
1962 return emulate_gp(ctxt, 0);
8c604352
AP		 1963 break;
1964 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1965 if (msr_data == 0x0)
1966 return emulate_gp(ctxt, 0);
8c604352
AP		 1967 break;
1968 }
1969
1970 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1971 cs_sel = (u16)msr_data;
1972 cs_sel &= ~SELECTOR_RPL_MASK;
1973 ss_sel = cs_sel + 8;
1974 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1975 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1976 cs.d = 0;
8c604352
AP		 1977 cs.l = 1;
1978 }
1979
1aa36616
AK		 1980 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1981 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1982
717746e3 1983 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1984 c->eip = msr_data;
1985
717746e3 1986 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1987 c->regs[VCPU_REGS_RSP] = msr_data;
1988
e54cfa97 1989 return X86EMUL_CONTINUE;
8c604352
AP		 1990}
1991
e01991e7 1992static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050
AP		 1993{
1994 struct decode_cache *c = &ctxt->decode;
7b105ca2 1995 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1996 struct desc_struct cs, ss;
4668f050
AP		 1997 u64 msr_data;
1998 int usermode;
1249b96e 1999 u16 cs_sel = 0, ss_sel = 0;
4668f050 2000
a0044755
GN		 2001 /* inject #GP if in real mode or Virtual 8086 mode */
2002 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2003 ctxt->mode == X86EMUL_MODE_VM86)
2004 return emulate_gp(ctxt, 0);
4668f050 2005
7b105ca2 2006 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050
AP		 2007
2008 if ((c->rex_prefix & 0x8) != 0x0)
2009 usermode = X86EMUL_MODE_PROT64;
2010 else
2011 usermode = X86EMUL_MODE_PROT32;
2012
2013 cs.dpl = 3;
2014 ss.dpl = 3;
717746e3 2015 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2016 switch (usermode) {
2017 case X86EMUL_MODE_PROT32:
79168fd1 2018 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2019 if ((msr_data & 0xfffc) == 0x0)
2020 return emulate_gp(ctxt, 0);
79168fd1 2021 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2022 break;
2023 case X86EMUL_MODE_PROT64:
79168fd1 2024 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2025 if (msr_data == 0x0)
2026 return emulate_gp(ctxt, 0);
79168fd1
GN		 2027 ss_sel = cs_sel + 8;
2028 cs.d = 0;
4668f050
AP		 2029 cs.l = 1;
2030 break;
2031 }
79168fd1
GN		 2032 cs_sel |= SELECTOR_RPL_MASK;
2033 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2034
1aa36616
AK		 2035 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2036 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2037
bdb475a3
GN		 2038 c->eip = c->regs[VCPU_REGS_RDX];
2039 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2040
e54cfa97 2041 return X86EMUL_CONTINUE;
4668f050
AP		 2042}
2043
7b105ca2 2044static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2045{
2046 int iopl;
2047 if (ctxt->mode == X86EMUL_MODE_REAL)
2048 return false;
2049 if (ctxt->mode == X86EMUL_MODE_VM86)
2050 return true;
2051 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2052 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2053}
2054
2055static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2056 u16 port, u16 len)
2057{
7b105ca2 2058 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2059 struct desc_struct tr_seg;
5601d05b 2060 u32 base3;
f850e2e6 2061 int r;
1aa36616 2062 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2063 unsigned mask = (1 << len) - 1;
5601d05b 2064 unsigned long base;
f850e2e6 2065
1aa36616 2066 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2067 if (!tr_seg.p)
f850e2e6 2068 return false;
79168fd1 2069 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2070 return false;
5601d05b
GN		 2071 base = get_desc_base(&tr_seg);
2072#ifdef CONFIG_X86_64
2073 base |= ((u64)base3) << 32;
2074#endif
0f65dd70 2075 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2076 if (r != X86EMUL_CONTINUE)
2077 return false;
79168fd1 2078 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2079 return false;
0f65dd70 2080 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2081 if (r != X86EMUL_CONTINUE)
2082 return false;
2083 if ((perm >> bit_idx) & mask)
2084 return false;
2085 return true;
2086}
2087
2088static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2089 u16 port, u16 len)
2090{
4fc40f07
GN		 2091 if (ctxt->perm_ok)
2092 return true;
2093
7b105ca2
TY		 2094 if (emulator_bad_iopl(ctxt))
2095 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2096 return false;
4fc40f07
GN		 2097
2098 ctxt->perm_ok = true;
2099
f850e2e6
GN		 2100 return true;
2101}
2102
38ba30ba 2103static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2104 struct tss_segment_16 *tss)
2105{
2106 struct decode_cache *c = &ctxt->decode;
2107
2108 tss->ip = c->eip;
2109 tss->flag = ctxt->eflags;
2110 tss->ax = c->regs[VCPU_REGS_RAX];
2111 tss->cx = c->regs[VCPU_REGS_RCX];
2112 tss->dx = c->regs[VCPU_REGS_RDX];
2113 tss->bx = c->regs[VCPU_REGS_RBX];
2114 tss->sp = c->regs[VCPU_REGS_RSP];
2115 tss->bp = c->regs[VCPU_REGS_RBP];
2116 tss->si = c->regs[VCPU_REGS_RSI];
2117 tss->di = c->regs[VCPU_REGS_RDI];
2118
1aa36616
AK		 2119 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2120 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2121 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2122 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2123 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2124}
2125
2126static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2127 struct tss_segment_16 *tss)
2128{
2129 struct decode_cache *c = &ctxt->decode;
2130 int ret;
2131
2132 c->eip = tss->ip;
2133 ctxt->eflags = tss->flag | 2;
2134 c->regs[VCPU_REGS_RAX] = tss->ax;
2135 c->regs[VCPU_REGS_RCX] = tss->cx;
2136 c->regs[VCPU_REGS_RDX] = tss->dx;
2137 c->regs[VCPU_REGS_RBX] = tss->bx;
2138 c->regs[VCPU_REGS_RSP] = tss->sp;
2139 c->regs[VCPU_REGS_RBP] = tss->bp;
2140 c->regs[VCPU_REGS_RSI] = tss->si;
2141 c->regs[VCPU_REGS_RDI] = tss->di;
2142
2143 /*
2144 * SDM says that segment selectors are loaded before segment
2145 * descriptors
2146 */
1aa36616
AK		 2147 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2148 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2149 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2150 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2151 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2152
2153 /*
2154 * Now load segment descriptors. If fault happenes at this stage
2155 * it is handled in a context of new task
2156 */
7b105ca2 2157 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2158 if (ret != X86EMUL_CONTINUE)
2159 return ret;
7b105ca2 2160 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2161 if (ret != X86EMUL_CONTINUE)
2162 return ret;
7b105ca2 2163 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2164 if (ret != X86EMUL_CONTINUE)
2165 return ret;
7b105ca2 2166 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2167 if (ret != X86EMUL_CONTINUE)
2168 return ret;
7b105ca2 2169 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2170 if (ret != X86EMUL_CONTINUE)
2171 return ret;
2172
2173 return X86EMUL_CONTINUE;
2174}
2175
2176static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2177 u16 tss_selector, u16 old_tss_sel,
2178 ulong old_tss_base, struct desc_struct *new_desc)
2179{
7b105ca2 2180 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2181 struct tss_segment_16 tss_seg;
2182 int ret;
bcc55cba 2183 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2184
0f65dd70 2185 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2186 &ctxt->exception);
db297e3d 2187 if (ret != X86EMUL_CONTINUE)
38ba30ba 2188 /* FIXME: need to provide precise fault address */
38ba30ba 2189 return ret;
38ba30ba 2190
7b105ca2 2191 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2192
0f65dd70 2193 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2194 &ctxt->exception);
db297e3d 2195 if (ret != X86EMUL_CONTINUE)
38ba30ba 2196 /* FIXME: need to provide precise fault address */
38ba30ba 2197 return ret;
38ba30ba 2198
0f65dd70 2199 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2200 &ctxt->exception);
db297e3d 2201 if (ret != X86EMUL_CONTINUE)
38ba30ba 2202 /* FIXME: need to provide precise fault address */
38ba30ba 2203 return ret;
38ba30ba
GN		 2204
2205 if (old_tss_sel != 0xffff) {
2206 tss_seg.prev_task_link = old_tss_sel;
2207
0f65dd70 2208 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2209 &tss_seg.prev_task_link,
2210 sizeof tss_seg.prev_task_link,
0f65dd70 2211 &ctxt->exception);
db297e3d 2212 if (ret != X86EMUL_CONTINUE)
38ba30ba 2213 /* FIXME: need to provide precise fault address */
38ba30ba 2214 return ret;
38ba30ba
GN		 2215 }
2216
7b105ca2 2217 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2218}
2219
2220static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2221 struct tss_segment_32 *tss)
2222{
2223 struct decode_cache *c = &ctxt->decode;
2224
7b105ca2 2225 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
38ba30ba
GN		 2226 tss->eip = c->eip;
2227 tss->eflags = ctxt->eflags;
2228 tss->eax = c->regs[VCPU_REGS_RAX];
2229 tss->ecx = c->regs[VCPU_REGS_RCX];
2230 tss->edx = c->regs[VCPU_REGS_RDX];
2231 tss->ebx = c->regs[VCPU_REGS_RBX];
2232 tss->esp = c->regs[VCPU_REGS_RSP];
2233 tss->ebp = c->regs[VCPU_REGS_RBP];
2234 tss->esi = c->regs[VCPU_REGS_RSI];
2235 tss->edi = c->regs[VCPU_REGS_RDI];
2236
1aa36616
AK		 2237 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2238 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2239 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2240 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2241 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2242 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2243 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2244}
2245
2246static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2247 struct tss_segment_32 *tss)
2248{
2249 struct decode_cache *c = &ctxt->decode;
2250 int ret;
2251
7b105ca2 2252 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2253 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2254 c->eip = tss->eip;
2255 ctxt->eflags = tss->eflags | 2;
2256 c->regs[VCPU_REGS_RAX] = tss->eax;
2257 c->regs[VCPU_REGS_RCX] = tss->ecx;
2258 c->regs[VCPU_REGS_RDX] = tss->edx;
2259 c->regs[VCPU_REGS_RBX] = tss->ebx;
2260 c->regs[VCPU_REGS_RSP] = tss->esp;
2261 c->regs[VCPU_REGS_RBP] = tss->ebp;
2262 c->regs[VCPU_REGS_RSI] = tss->esi;
2263 c->regs[VCPU_REGS_RDI] = tss->edi;
2264
2265 /*
2266 * SDM says that segment selectors are loaded before segment
2267 * descriptors
2268 */
1aa36616
AK		 2269 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2270 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2271 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2272 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2273 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2274 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2275 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2276
2277 /*
2278 * Now load segment descriptors. If fault happenes at this stage
2279 * it is handled in a context of new task
2280 */
7b105ca2 2281 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2282 if (ret != X86EMUL_CONTINUE)
2283 return ret;
7b105ca2 2284 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2285 if (ret != X86EMUL_CONTINUE)
2286 return ret;
7b105ca2 2287 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2288 if (ret != X86EMUL_CONTINUE)
2289 return ret;
7b105ca2 2290 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2291 if (ret != X86EMUL_CONTINUE)
2292 return ret;
7b105ca2 2293 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2294 if (ret != X86EMUL_CONTINUE)
2295 return ret;
7b105ca2 2296 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2297 if (ret != X86EMUL_CONTINUE)
2298 return ret;
7b105ca2 2299 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2300 if (ret != X86EMUL_CONTINUE)
2301 return ret;
2302
2303 return X86EMUL_CONTINUE;
2304}
2305
2306static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2307 u16 tss_selector, u16 old_tss_sel,
2308 ulong old_tss_base, struct desc_struct *new_desc)
2309{
7b105ca2 2310 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2311 struct tss_segment_32 tss_seg;
2312 int ret;
bcc55cba 2313 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2314
0f65dd70 2315 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2316 &ctxt->exception);
db297e3d 2317 if (ret != X86EMUL_CONTINUE)
38ba30ba 2318 /* FIXME: need to provide precise fault address */
38ba30ba 2319 return ret;
38ba30ba 2320
7b105ca2 2321 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2322
0f65dd70 2323 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2324 &ctxt->exception);
db297e3d 2325 if (ret != X86EMUL_CONTINUE)
38ba30ba 2326 /* FIXME: need to provide precise fault address */
38ba30ba 2327 return ret;
38ba30ba 2328
0f65dd70 2329 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2330 &ctxt->exception);
db297e3d 2331 if (ret != X86EMUL_CONTINUE)
38ba30ba 2332 /* FIXME: need to provide precise fault address */
38ba30ba 2333 return ret;
38ba30ba
GN		 2334
2335 if (old_tss_sel != 0xffff) {
2336 tss_seg.prev_task_link = old_tss_sel;
2337
0f65dd70 2338 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2339 &tss_seg.prev_task_link,
2340 sizeof tss_seg.prev_task_link,
0f65dd70 2341 &ctxt->exception);
db297e3d 2342 if (ret != X86EMUL_CONTINUE)
38ba30ba 2343 /* FIXME: need to provide precise fault address */
38ba30ba 2344 return ret;
38ba30ba
GN		 2345 }
2346
7b105ca2 2347 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2348}
2349
2350static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2351 u16 tss_selector, int reason,
2352 bool has_error_code, u32 error_code)
38ba30ba 2353{
7b105ca2 2354 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2355 struct desc_struct curr_tss_desc, next_tss_desc;
2356 int ret;
1aa36616 2357 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2358 ulong old_tss_base =
4bff1e86 2359 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2360 u32 desc_limit;
38ba30ba
GN		 2361
2362 /* FIXME: old_tss_base == ~0 ? */
2363
7b105ca2 2364 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2365 if (ret != X86EMUL_CONTINUE)
2366 return ret;
7b105ca2 2367 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2368 if (ret != X86EMUL_CONTINUE)
2369 return ret;
2370
2371 /* FIXME: check that next_tss_desc is tss */
2372
2373 if (reason != TASK_SWITCH_IRET) {
2374 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2375 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2376 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2377 }
2378
ceffb459
GN		 2379 desc_limit = desc_limit_scaled(&next_tss_desc);
2380 if (!next_tss_desc.p ||
2381 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2382 desc_limit < 0x2b)) {
54b8486f 2383 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2384 return X86EMUL_PROPAGATE_FAULT;
2385 }
2386
2387 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2388 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2389 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2390 }
2391
2392 if (reason == TASK_SWITCH_IRET)
2393 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2394
2395 /* set back link to prev task only if NT bit is set in eflags
2396 note that old_tss_sel is not used afetr this point */
2397 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2398 old_tss_sel = 0xffff;
2399
2400 if (next_tss_desc.type & 8)
7b105ca2 2401 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2402 old_tss_base, &next_tss_desc);
2403 else
7b105ca2 2404 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2405 old_tss_base, &next_tss_desc);
0760d448
JK		 2406 if (ret != X86EMUL_CONTINUE)
2407 return ret;
38ba30ba
GN		 2408
2409 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2410 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2411
2412 if (reason != TASK_SWITCH_IRET) {
2413 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2414 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2415 }
2416
717746e3 2417 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2418 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2419
e269fb21
JK		 2420 if (has_error_code) {
2421 struct decode_cache *c = &ctxt->decode;
2422
2423 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2424 c->lock_prefix = 0;
2425 c->src.val = (unsigned long) error_code;
4487b3b4 2426 ret = em_push(ctxt);
e269fb21
JK		 2427 }
2428
38ba30ba
GN		 2429 return ret;
2430}
2431
2432int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2433 u16 tss_selector, int reason,
2434 bool has_error_code, u32 error_code)
38ba30ba
GN		 2435{
2436 struct decode_cache *c = &ctxt->decode;
2437 int rc;
2438
38ba30ba 2439 c->eip = ctxt->eip;
e269fb21 2440 c->dst.type = OP_NONE;
38ba30ba 2441
7b105ca2 2442 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2443 has_error_code, error_code);
38ba30ba 2444
4179bb02
TY		 2445 if (rc == X86EMUL_CONTINUE)
2446 ctxt->eip = c->eip;
38ba30ba 2447
a0c0ab2f 2448 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2449}
2450
90de84f5 2451static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2452 int reg, struct operand *op)
a682e354
GN		 2453{
2454 struct decode_cache *c = &ctxt->decode;
2455 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2456
d9271123 2457 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2458 op->addr.mem.ea = register_address(c, c->regs[reg]);
2459 op->addr.mem.seg = seg;
a682e354
GN		 2460}
2461
7af04fc0
AK		 2462static int em_das(struct x86_emulate_ctxt *ctxt)
2463{
2464 struct decode_cache *c = &ctxt->decode;
2465 u8 al, old_al;
2466 bool af, cf, old_cf;
2467
2468 cf = ctxt->eflags & X86_EFLAGS_CF;
2469 al = c->dst.val;
2470
2471 old_al = al;
2472 old_cf = cf;
2473 cf = false;
2474 af = ctxt->eflags & X86_EFLAGS_AF;
2475 if ((al & 0x0f) > 9 || af) {
2476 al -= 6;
2477 cf = old_cf | (al >= 250);
2478 af = true;
2479 } else {
2480 af = false;
2481 }
2482 if (old_al > 0x99 || old_cf) {
2483 al -= 0x60;
2484 cf = true;
2485 }
2486
2487 c->dst.val = al;
2488 /* Set PF, ZF, SF */
2489 c->src.type = OP_IMM;
2490 c->src.val = 0;
2491 c->src.bytes = 1;
2492 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2493 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2494 if (cf)
2495 ctxt->eflags |= X86_EFLAGS_CF;
2496 if (af)
2497 ctxt->eflags |= X86_EFLAGS_AF;
2498 return X86EMUL_CONTINUE;
2499}
2500
0ef753b8
AK		 2501static int em_call_far(struct x86_emulate_ctxt *ctxt)
2502{
2503 struct decode_cache *c = &ctxt->decode;
2504 u16 sel, old_cs;
2505 ulong old_eip;
2506 int rc;
2507
1aa36616 2508 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2509 old_eip = c->eip;
2510
2511 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
7b105ca2 2512 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2513 return X86EMUL_CONTINUE;
2514
2515 c->eip = 0;
2516 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2517
2518 c->src.val = old_cs;
4487b3b4 2519 rc = em_push(ctxt);
0ef753b8
AK		 2520 if (rc != X86EMUL_CONTINUE)
2521 return rc;
2522
2523 c->src.val = old_eip;
4487b3b4 2524 return em_push(ctxt);
0ef753b8
AK		 2525}
2526
40ece7c7
AK		 2527static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2528{
2529 struct decode_cache *c = &ctxt->decode;
2530 int rc;
2531
2532 c->dst.type = OP_REG;
2533 c->dst.addr.reg = &c->eip;
2534 c->dst.bytes = c->op_bytes;
3b9be3bf 2535 rc = emulate_pop(ctxt, &c->dst.val, c->op_bytes);
40ece7c7
AK		 2536 if (rc != X86EMUL_CONTINUE)
2537 return rc;
2538 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2539 return X86EMUL_CONTINUE;
2540}
2541
d67fc27a
TY		 2542static int em_add(struct x86_emulate_ctxt *ctxt)
2543{
2544 struct decode_cache *c = &ctxt->decode;
2545
2546 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2547 return X86EMUL_CONTINUE;
2548}
2549
2550static int em_or(struct x86_emulate_ctxt *ctxt)
2551{
2552 struct decode_cache *c = &ctxt->decode;
2553
2554 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2555 return X86EMUL_CONTINUE;
2556}
2557
2558static int em_adc(struct x86_emulate_ctxt *ctxt)
2559{
2560 struct decode_cache *c = &ctxt->decode;
2561
2562 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2563 return X86EMUL_CONTINUE;
2564}
2565
2566static int em_sbb(struct x86_emulate_ctxt *ctxt)
2567{
2568 struct decode_cache *c = &ctxt->decode;
2569
2570 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2571 return X86EMUL_CONTINUE;
2572}
2573
2574static int em_and(struct x86_emulate_ctxt *ctxt)
2575{
2576 struct decode_cache *c = &ctxt->decode;
2577
2578 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2579 return X86EMUL_CONTINUE;
2580}
2581
2582static int em_sub(struct x86_emulate_ctxt *ctxt)
2583{
2584 struct decode_cache *c = &ctxt->decode;
2585
2586 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2587 return X86EMUL_CONTINUE;
2588}
2589
2590static int em_xor(struct x86_emulate_ctxt *ctxt)
2591{
2592 struct decode_cache *c = &ctxt->decode;
2593
2594 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2595 return X86EMUL_CONTINUE;
2596}
2597
2598static int em_cmp(struct x86_emulate_ctxt *ctxt)
2599{
2600 struct decode_cache *c = &ctxt->decode;
2601
2602 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2603 /* Disable writeback. */
2604 c->dst.type = OP_NONE;
2605 return X86EMUL_CONTINUE;
2606}
2607
9f21ca59
TY		 2608static int em_test(struct x86_emulate_ctxt *ctxt)
2609{
2610 struct decode_cache *c = &ctxt->decode;
2611
2612 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2613 return X86EMUL_CONTINUE;
2614}
2615
e4f973ae
TY		 2616static int em_xchg(struct x86_emulate_ctxt *ctxt)
2617{
2618 struct decode_cache *c = &ctxt->decode;
2619
2620 /* Write back the register source. */
2621 c->src.val = c->dst.val;
2622 write_register_operand(&c->src);
2623
2624 /* Write back the memory destination with implicit LOCK prefix. */
2625 c->dst.val = c->src.orig_val;
2626 c->lock_prefix = 1;
2627 return X86EMUL_CONTINUE;
2628}
2629
5c82aa29 2630static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2631{
2632 struct decode_cache *c = &ctxt->decode;
2633
f3a1b9f4
AK		 2634 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2635 return X86EMUL_CONTINUE;
2636}
2637
5c82aa29
AK		 2638static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2639{
2640 struct decode_cache *c = &ctxt->decode;
2641
2642 c->dst.val = c->src2.val;
2643 return em_imul(ctxt);
2644}
2645
61429142
AK		 2646static int em_cwd(struct x86_emulate_ctxt *ctxt)
2647{
2648 struct decode_cache *c = &ctxt->decode;
2649
2650 c->dst.type = OP_REG;
2651 c->dst.bytes = c->src.bytes;
2652 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2653 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2654
2655 return X86EMUL_CONTINUE;
2656}
2657
48bb5d3c
AK		 2658static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2659{
48bb5d3c
AK		 2660 struct decode_cache *c = &ctxt->decode;
2661 u64 tsc = 0;
2662
717746e3 2663 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2664 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2665 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2666 return X86EMUL_CONTINUE;
2667}
2668
b9eac5f4
AK		 2669static int em_mov(struct x86_emulate_ctxt *ctxt)
2670{
2671 struct decode_cache *c = &ctxt->decode;
2672 c->dst.val = c->src.val;
2673 return X86EMUL_CONTINUE;
2674}
2675
aa97bb48
AK		 2676static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2677{
2678 struct decode_cache *c = &ctxt->decode;
2679 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2680 return X86EMUL_CONTINUE;
2681}
2682
38503911
AK		 2683static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2684{
2685 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2686 int rc;
2687 ulong linear;
2688
83b8795a 2689 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2690 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2691 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2692 /* Disable writeback. */
2693 c->dst.type = OP_NONE;
2694 return X86EMUL_CONTINUE;
2695}
2696
2d04a05b
AK		 2697static int em_clts(struct x86_emulate_ctxt *ctxt)
2698{
2699 ulong cr0;
2700
2701 cr0 = ctxt->ops->get_cr(ctxt, 0);
2702 cr0 &= ~X86_CR0_TS;
2703 ctxt->ops->set_cr(ctxt, 0, cr0);
2704 return X86EMUL_CONTINUE;
2705}
2706
26d05cc7
AK		 2707static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2708{
2709 struct decode_cache *c = &ctxt->decode;
2710 int rc;
2711
2712 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2713 return X86EMUL_UNHANDLEABLE;
2714
2715 rc = ctxt->ops->fix_hypercall(ctxt);
2716 if (rc != X86EMUL_CONTINUE)
2717 return rc;
2718
2719 /* Let the processor re-execute the fixed hypercall */
2720 c->eip = ctxt->eip;
2721 /* Disable writeback. */
2722 c->dst.type = OP_NONE;
2723 return X86EMUL_CONTINUE;
2724}
2725
2726static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2727{
2728 struct decode_cache *c = &ctxt->decode;
2729 struct desc_ptr desc_ptr;
2730 int rc;
2731
509cf9fe 2732 rc = read_descriptor(ctxt, c->src.addr.mem,
26d05cc7
AK		 2733 &desc_ptr.size, &desc_ptr.address,
2734 c->op_bytes);
2735 if (rc != X86EMUL_CONTINUE)
2736 return rc;
2737 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2738 /* Disable writeback. */
2739 c->dst.type = OP_NONE;
2740 return X86EMUL_CONTINUE;
2741}
2742
5ef39c71 2743static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2744{
2745 struct decode_cache *c = &ctxt->decode;
2746 int rc;
2747
5ef39c71
AK		 2748 rc = ctxt->ops->fix_hypercall(ctxt);
2749
26d05cc7
AK		 2750 /* Disable writeback. */
2751 c->dst.type = OP_NONE;
2752 return rc;
2753}
2754
2755static int em_lidt(struct x86_emulate_ctxt *ctxt)
2756{
2757 struct decode_cache *c = &ctxt->decode;
2758 struct desc_ptr desc_ptr;
2759 int rc;
2760
509cf9fe
TY		 2761 rc = read_descriptor(ctxt, c->src.addr.mem,
2762 &desc_ptr.size, &desc_ptr.address,
26d05cc7
AK		 2763 c->op_bytes);
2764 if (rc != X86EMUL_CONTINUE)
2765 return rc;
2766 ctxt->ops->set_idt(ctxt, &desc_ptr);
2767 /* Disable writeback. */
2768 c->dst.type = OP_NONE;
2769 return X86EMUL_CONTINUE;
2770}
2771
2772static int em_smsw(struct x86_emulate_ctxt *ctxt)
2773{
2774 struct decode_cache *c = &ctxt->decode;
2775
2776 c->dst.bytes = 2;
2777 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2778 return X86EMUL_CONTINUE;
2779}
2780
2781static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2782{
2783 struct decode_cache *c = &ctxt->decode;
2784 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2785 | (c->src.val & 0x0f));
2786 c->dst.type = OP_NONE;
2787 return X86EMUL_CONTINUE;
2788}
2789
cfec82cb
JR		 2790static bool valid_cr(int nr)
2791{
2792 switch (nr) {
2793 case 0:
2794 case 2 ... 4:
2795 case 8:
2796 return true;
2797 default:
2798 return false;
2799 }
2800}
2801
2802static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2803{
2804 struct decode_cache *c = &ctxt->decode;
2805
2806 if (!valid_cr(c->modrm_reg))
2807 return emulate_ud(ctxt);
2808
2809 return X86EMUL_CONTINUE;
2810}
2811
2812static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2813{
2814 struct decode_cache *c = &ctxt->decode;
2815 u64 new_val = c->src.val64;
2816 int cr = c->modrm_reg;
c2ad2bb3 2817 u64 efer = 0;
cfec82cb
JR		 2818
2819 static u64 cr_reserved_bits[] = {
2820 0xffffffff00000000ULL,
2821 0, 0, 0, /* CR3 checked later */
2822 CR4_RESERVED_BITS,
2823 0, 0, 0,
2824 CR8_RESERVED_BITS,
2825 };
2826
2827 if (!valid_cr(cr))
2828 return emulate_ud(ctxt);
2829
2830 if (new_val & cr_reserved_bits[cr])
2831 return emulate_gp(ctxt, 0);
2832
2833 switch (cr) {
2834 case 0: {
c2ad2bb3 2835 u64 cr4;
cfec82cb
JR		 2836 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2837 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2838 return emulate_gp(ctxt, 0);
2839
717746e3
AK		 2840 cr4 = ctxt->ops->get_cr(ctxt, 4);
2841 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2842
2843 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2844 !(cr4 & X86_CR4_PAE))
2845 return emulate_gp(ctxt, 0);
2846
2847 break;
2848 }
2849 case 3: {
2850 u64 rsvd = 0;
2851
c2ad2bb3
AK		 2852 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2853 if (efer & EFER_LMA)
cfec82cb 2854 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2855 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2856 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2857 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2858 rsvd = CR3_NONPAE_RESERVED_BITS;
2859
2860 if (new_val & rsvd)
2861 return emulate_gp(ctxt, 0);
2862
2863 break;
2864 }
2865 case 4: {
c2ad2bb3 2866 u64 cr4;
cfec82cb 2867
717746e3
AK		 2868 cr4 = ctxt->ops->get_cr(ctxt, 4);
2869 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2870
2871 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2872 return emulate_gp(ctxt, 0);
2873
2874 break;
2875 }
2876 }
2877
2878 return X86EMUL_CONTINUE;
2879}
2880
3b88e41a
JR		 2881static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2882{
2883 unsigned long dr7;
2884
717746e3 2885 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2886
2887 /* Check if DR7.Global_Enable is set */
2888 return dr7 & (1 << 13);
2889}
2890
2891static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2892{
2893 struct decode_cache *c = &ctxt->decode;
2894 int dr = c->modrm_reg;
2895 u64 cr4;
2896
2897 if (dr > 7)
2898 return emulate_ud(ctxt);
2899
717746e3 2900 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2901 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2902 return emulate_ud(ctxt);
2903
2904 if (check_dr7_gd(ctxt))
2905 return emulate_db(ctxt);
2906
2907 return X86EMUL_CONTINUE;
2908}
2909
2910static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2911{
2912 struct decode_cache *c = &ctxt->decode;
2913 u64 new_val = c->src.val64;
2914 int dr = c->modrm_reg;
2915
2916 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2917 return emulate_gp(ctxt, 0);
2918
2919 return check_dr_read(ctxt);
2920}
2921
01de8b09
JR		 2922static int check_svme(struct x86_emulate_ctxt *ctxt)
2923{
2924 u64 efer;
2925
717746e3 2926 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2927
2928 if (!(efer & EFER_SVME))
2929 return emulate_ud(ctxt);
2930
2931 return X86EMUL_CONTINUE;
2932}
2933
2934static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2935{
fe870ab9 2936 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2937
2938 /* Valid physical address? */
d4224449 2939 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2940 return emulate_gp(ctxt, 0);
2941
2942 return check_svme(ctxt);
2943}
2944
d7eb8203
JR		 2945static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2946{
717746e3 2947 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2948
717746e3 2949 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2950 return emulate_ud(ctxt);
2951
2952 return X86EMUL_CONTINUE;
2953}
2954
8061252e
JR		 2955static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2956{
717746e3 2957 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2958 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2959
717746e3 2960 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2961 (rcx > 3))
2962 return emulate_gp(ctxt, 0);
2963
2964 return X86EMUL_CONTINUE;
2965}
2966
f6511935
JR		 2967static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2968{
2969 struct decode_cache *c = &ctxt->decode;
2970
2971 c->dst.bytes = min(c->dst.bytes, 4u);
7b105ca2 2972 if (!emulator_io_permited(ctxt, c->src.val, c->dst.bytes))
f6511935
JR		 2973 return emulate_gp(ctxt, 0);
2974
2975 return X86EMUL_CONTINUE;
2976}
2977
2978static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2979{
2980 struct decode_cache *c = &ctxt->decode;
2981
2982 c->src.bytes = min(c->src.bytes, 4u);
7b105ca2 2983 if (!emulator_io_permited(ctxt, c->dst.val, c->src.bytes))
f6511935
JR		 2984 return emulate_gp(ctxt, 0);
2985
2986 return X86EMUL_CONTINUE;
2987}
2988
73fba5f4 2989#define D(_y) { .flags = (_y) }
c4f035c6 2990#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2991#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2992 .check_perm = (_p) }
73fba5f4 2993#define N D(0)
01de8b09 2994#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2995#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2996#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2997#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2998#define II(_f, _e, _i) \
2999 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3000#define IIP(_f, _e, _i, _p) \
3001 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3002 .check_perm = (_p) }
aa97bb48 3003#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3004
8d8f4e9f 3005#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3006#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 3007#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3008
d67fc27a
TY		 3009#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3010 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3011 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3012
d7eb8203
JR		 3013static struct opcode group7_rm1[] = {
3014 DI(SrcNone | ModRM | Priv, monitor),
3015 DI(SrcNone | ModRM | Priv, mwait),
3016 N, N, N, N, N, N,
3017};
3018
01de8b09
JR		 3019static struct opcode group7_rm3[] = {
3020 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3021 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3022 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3023 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3024 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3025 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3026 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3027 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3028};
6230f7fc 3029
d7eb8203
JR		 3030static struct opcode group7_rm7[] = {
3031 N,
3032 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3033 N, N, N, N, N, N,
3034};
d67fc27a 3035
73fba5f4 3036static struct opcode group1[] = {
d67fc27a
TY		 3037 I(Lock, em_add),
3038 I(Lock, em_or),
3039 I(Lock, em_adc),
3040 I(Lock, em_sbb),
3041 I(Lock, em_and),
3042 I(Lock, em_sub),
3043 I(Lock, em_xor),
3044 I(0, em_cmp),
73fba5f4
AK		 3045};
3046
3047static struct opcode group1A[] = {
3048 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3049};
3050
3051static struct opcode group3[] = {
3052 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3053 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3054 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3055};
3056
3057static struct opcode group4[] = {
3058 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3059 N, N, N, N, N, N,
3060};
3061
3062static struct opcode group5[] = {
3063 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3064 D(SrcMem | ModRM | Stack),
3065 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3066 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3067 D(SrcMem | ModRM | Stack), N,
3068};
3069
dee6bb70
JR		 3070static struct opcode group6[] = {
3071 DI(ModRM | Prot, sldt),
3072 DI(ModRM | Prot, str),
3073 DI(ModRM | Prot | Priv, lldt),
3074 DI(ModRM | Prot | Priv, ltr),
3075 N, N, N, N,
3076};
3077
73fba5f4 3078static struct group_dual group7 = { {
dee6bb70
JR		 3079 DI(ModRM | Mov | DstMem | Priv, sgdt),
3080 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3081 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3082 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3083 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3084 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3085 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3086}, {
5ef39c71
AK		 3087 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3088 EXT(0, group7_rm1),
01de8b09 3089 N, EXT(0, group7_rm3),
5ef39c71
AK		 3090 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3091 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3092} };
3093
3094static struct opcode group8[] = {
3095 N, N, N, N,
3096 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3097 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3098};
3099
3100static struct group_dual group9 = { {
3101 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3102}, {
3103 N, N, N, N, N, N, N, N,
3104} };
3105
a4d4a7c1
AK		 3106static struct opcode group11[] = {
3107 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3108};
3109
aa97bb48
AK		 3110static struct gprefix pfx_0f_6f_0f_7f = {
3111 N, N, N, I(Sse, em_movdqu),
3112};
3113
73fba5f4
AK		 3114static struct opcode opcode_table[256] = {
3115 /* 0x00 - 0x07 */
d67fc27a 3116 I6ALU(Lock, em_add),
73fba5f4
AK		 3117 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3118 /* 0x08 - 0x0F */
d67fc27a 3119 I6ALU(Lock, em_or),
73fba5f4
AK		 3120 D(ImplicitOps | Stack | No64), N,
3121 /* 0x10 - 0x17 */
d67fc27a 3122 I6ALU(Lock, em_adc),
73fba5f4
AK		 3123 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3124 /* 0x18 - 0x1F */
d67fc27a 3125 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3126 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3127 /* 0x20 - 0x27 */
d67fc27a 3128 I6ALU(Lock, em_and), N, N,
73fba5f4 3129 /* 0x28 - 0x2F */
d67fc27a 3130 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3131 /* 0x30 - 0x37 */
d67fc27a 3132 I6ALU(Lock, em_xor), N, N,
73fba5f4 3133 /* 0x38 - 0x3F */
d67fc27a 3134 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3135 /* 0x40 - 0x4F */
3136 X16(D(DstReg)),
3137 /* 0x50 - 0x57 */
63540382 3138 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3139 /* 0x58 - 0x5F */
c54fe504 3140 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3141 /* 0x60 - 0x67 */
b96a7fad
TY		 3142 I(ImplicitOps | Stack | No64, em_pusha),
3143 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3144 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3145 N, N, N, N,
3146 /* 0x68 - 0x6F */
d46164db
AK		 3147 I(SrcImm | Mov | Stack, em_push),
3148 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3149 I(SrcImmByte | Mov | Stack, em_push),
3150 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3151 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3152 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3153 /* 0x70 - 0x7F */
3154 X16(D(SrcImmByte)),
3155 /* 0x80 - 0x87 */
3156 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3157 G(DstMem | SrcImm | ModRM | Group, group1),
3158 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3159 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3160 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3161 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3162 /* 0x88 - 0x8F */
b9eac5f4
AK		 3163 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3164 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3165 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3166 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3167 /* 0x90 - 0x97 */
bf608f88 3168 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3169 /* 0x98 - 0x9F */
61429142 3170 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3171 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3172 II(ImplicitOps | Stack, em_pushf, pushf),
3173 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3174 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3175 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3176 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3177 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3178 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3179 /* 0xA8 - 0xAF */
9f21ca59 3180 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3181 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3182 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3183 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3184 /* 0xB0 - 0xB7 */
b9eac5f4 3185 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3186 /* 0xB8 - 0xBF */
b9eac5f4 3187 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3188 /* 0xC0 - 0xC7 */
d2c6c7ad 3189 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3190 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3191 D(ImplicitOps | Stack),
09b5f4d3 3192 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3193 G(ByteOp, group11), G(0, group11),
73fba5f4 3194 /* 0xC8 - 0xCF */
db5b0762 3195 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3196 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3197 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3198 /* 0xD0 - 0xD7 */
d2c6c7ad 3199 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3200 N, N, N, N,
3201 /* 0xD8 - 0xDF */
3202 N, N, N, N, N, N, N, N,
3203 /* 0xE0 - 0xE7 */
e4abac67 3204 X4(D(SrcImmByte)),
f6511935
JR		 3205 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3206 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3207 /* 0xE8 - 0xEF */
3208 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3209 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3210 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3211 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3212 /* 0xF0 - 0xF7 */
bf608f88 3213 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3214 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3215 G(ByteOp, group3), G(0, group3),
73fba5f4 3216 /* 0xF8 - 0xFF */
8744aa9a 3217 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3218 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3219};
3220
3221static struct opcode twobyte_table[256] = {
3222 /* 0x00 - 0x0F */
dee6bb70 3223 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3224 N, I(ImplicitOps | VendorSpecific, em_syscall),
3225 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3226 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3227 N, D(ImplicitOps | ModRM), N, N,
3228 /* 0x10 - 0x1F */
3229 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3230 /* 0x20 - 0x2F */
cfec82cb 3231 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3232 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3233 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3234 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3235 N, N, N, N,
3236 N, N, N, N, N, N, N, N,
3237 /* 0x30 - 0x3F */
8061252e
JR		 3238 DI(ImplicitOps | Priv, wrmsr),
3239 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3240 DI(ImplicitOps | Priv, rdmsr),
3241 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3242 I(ImplicitOps | VendorSpecific, em_sysenter),
3243 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3244 N, N,
73fba5f4
AK		 3245 N, N, N, N, N, N, N, N,
3246 /* 0x40 - 0x4F */
3247 X16(D(DstReg | SrcMem | ModRM | Mov)),
3248 /* 0x50 - 0x5F */
3249 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3250 /* 0x60 - 0x6F */
aa97bb48
AK		 3251 N, N, N, N,
3252 N, N, N, N,
3253 N, N, N, N,
3254 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3255 /* 0x70 - 0x7F */
aa97bb48
AK		 3256 N, N, N, N,
3257 N, N, N, N,
3258 N, N, N, N,
3259 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3260 /* 0x80 - 0x8F */
3261 X16(D(SrcImm)),
3262 /* 0x90 - 0x9F */
ee45b58e 3263 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3264 /* 0xA0 - 0xA7 */
3265 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3266 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3267 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3268 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3269 /* 0xA8 - 0xAF */
3270 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3271 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3272 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3273 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3274 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3275 /* 0xB0 - 0xB7 */
739ae406 3276 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3277 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3278 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3279 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3280 /* 0xB8 - 0xBF */
3281 N, N,
ba7ff2b7 3282 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3283 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3284 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3285 /* 0xC0 - 0xCF */
739ae406 3286 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3287 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3288 N, N, N, GD(0, &group9),
3289 N, N, N, N, N, N, N, N,
3290 /* 0xD0 - 0xDF */
3291 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3292 /* 0xE0 - 0xEF */
3293 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3294 /* 0xF0 - 0xFF */
3295 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3296};
3297
3298#undef D
3299#undef N
3300#undef G
3301#undef GD
3302#undef I
aa97bb48 3303#undef GP
01de8b09 3304#undef EXT
73fba5f4 3305
8d8f4e9f 3306#undef D2bv
f6511935 3307#undef D2bvIP
8d8f4e9f 3308#undef I2bv
d67fc27a 3309#undef I6ALU
8d8f4e9f 3310
39f21ee5
AK		 3311static unsigned imm_size(struct decode_cache *c)
3312{
3313 unsigned size;
3314
3315 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3316 if (size == 8)
3317 size = 4;
3318 return size;
3319}
3320
3321static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3322 unsigned size, bool sign_extension)
3323{
3324 struct decode_cache *c = &ctxt->decode;
39f21ee5
AK		 3325 int rc = X86EMUL_CONTINUE;
3326
3327 op->type = OP_IMM;
3328 op->bytes = size;
90de84f5 3329 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3330 /* NB. Immediates are sign-extended as necessary. */
3331 switch (op->bytes) {
3332 case 1:
3333 op->val = insn_fetch(s8, 1, c->eip);
3334 break;
3335 case 2:
3336 op->val = insn_fetch(s16, 2, c->eip);
3337 break;
3338 case 4:
3339 op->val = insn_fetch(s32, 4, c->eip);
3340 break;
3341 }
3342 if (!sign_extension) {
3343 switch (op->bytes) {
3344 case 1:
3345 op->val &= 0xff;
3346 break;
3347 case 2:
3348 op->val &= 0xffff;
3349 break;
3350 case 4:
3351 op->val &= 0xffffffff;
3352 break;
3353 }
3354 }
3355done:
3356 return rc;
3357}
3358
ef5d75cc 3359int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3360{
dde7e6d1
AK		 3361 struct decode_cache *c = &ctxt->decode;
3362 int rc = X86EMUL_CONTINUE;
3363 int mode = ctxt->mode;
46561646 3364 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3365 bool op_prefix = false;
46561646 3366 struct opcode opcode;
cb16c348 3367 struct operand memop = { .type = OP_NONE }, *memopp = NULL;
dde7e6d1 3368
dde7e6d1 3369 c->eip = ctxt->eip;
dc25e89e
AP		 3370 c->fetch.start = c->eip;
3371 c->fetch.end = c->fetch.start + insn_len;
3372 if (insn_len > 0)
3373 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3374
3375 switch (mode) {
3376 case X86EMUL_MODE_REAL:
3377 case X86EMUL_MODE_VM86:
3378 case X86EMUL_MODE_PROT16:
3379 def_op_bytes = def_ad_bytes = 2;
3380 break;
3381 case X86EMUL_MODE_PROT32:
3382 def_op_bytes = def_ad_bytes = 4;
3383 break;
3384#ifdef CONFIG_X86_64
3385 case X86EMUL_MODE_PROT64:
3386 def_op_bytes = 4;
3387 def_ad_bytes = 8;
3388 break;
3389#endif
3390 default:
3391 return -1;
3392 }
3393
3394 c->op_bytes = def_op_bytes;
3395 c->ad_bytes = def_ad_bytes;
3396
3397 /* Legacy prefixes. */
3398 for (;;) {
3399 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3400 case 0x66: /* operand-size override */
0d7cdee8 3401 op_prefix = true;
dde7e6d1
AK		 3402 /* switch between 2/4 bytes */
3403 c->op_bytes = def_op_bytes ^ 6;
3404 break;
3405 case 0x67: /* address-size override */
3406 if (mode == X86EMUL_MODE_PROT64)
3407 /* switch between 4/8 bytes */
3408 c->ad_bytes = def_ad_bytes ^ 12;
3409 else
3410 /* switch between 2/4 bytes */
3411 c->ad_bytes = def_ad_bytes ^ 6;
3412 break;
3413 case 0x26: /* ES override */
3414 case 0x2e: /* CS override */
3415 case 0x36: /* SS override */
3416 case 0x3e: /* DS override */
3417 set_seg_override(c, (c->b >> 3) & 3);
3418 break;
3419 case 0x64: /* FS override */
3420 case 0x65: /* GS override */
3421 set_seg_override(c, c->b & 7);
3422 break;
3423 case 0x40 ... 0x4f: /* REX */
3424 if (mode != X86EMUL_MODE_PROT64)
3425 goto done_prefixes;
3426 c->rex_prefix = c->b;
3427 continue;
3428 case 0xf0: /* LOCK */
3429 c->lock_prefix = 1;
3430 break;
3431 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3432 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3433 c->rep_prefix = c->b;
dde7e6d1
AK		 3434 break;
3435 default:
3436 goto done_prefixes;
3437 }
3438
3439 /* Any legacy prefix after a REX prefix nullifies its effect. */
3440
3441 c->rex_prefix = 0;
3442 }
3443
3444done_prefixes:
3445
3446 /* REX prefix. */
1e87e3ef
AK		 3447 if (c->rex_prefix & 8)
3448 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3449
3450 /* Opcode byte(s). */
3451 opcode = opcode_table[c->b];
d3ad6243
WY		 3452 /* Two-byte opcode? */
3453 if (c->b == 0x0f) {
3454 c->twobyte = 1;
3455 c->b = insn_fetch(u8, 1, c->eip);
3456 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3457 }
3458 c->d = opcode.flags;
3459
46561646
AK		 3460 while (c->d & GroupMask) {
3461 switch (c->d & GroupMask) {
3462 case Group:
3463 c->modrm = insn_fetch(u8, 1, c->eip);
3464 --c->eip;
3465 goffset = (c->modrm >> 3) & 7;
3466 opcode = opcode.u.group[goffset];
3467 break;
3468 case GroupDual:
3469 c->modrm = insn_fetch(u8, 1, c->eip);
3470 --c->eip;
3471 goffset = (c->modrm >> 3) & 7;
3472 if ((c->modrm >> 6) == 3)
3473 opcode = opcode.u.gdual->mod3[goffset];
3474 else
3475 opcode = opcode.u.gdual->mod012[goffset];
3476 break;
3477 case RMExt:
01de8b09
JR		 3478 goffset = c->modrm & 7;
3479 opcode = opcode.u.group[goffset];
46561646
AK		 3480 break;
3481 case Prefix:
3482 if (c->rep_prefix && op_prefix)
3483 return X86EMUL_UNHANDLEABLE;
3484 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3485 switch (simd_prefix) {
3486 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3487 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3488 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3489 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3490 }
3491 break;
3492 default:
0d7cdee8 3493 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3494 }
46561646
AK		 3495
3496 c->d &= ~GroupMask;
0d7cdee8
AK		 3497 c->d |= opcode.flags;
3498 }
3499
dde7e6d1 3500 c->execute = opcode.u.execute;
d09beabd 3501 c->check_perm = opcode.check_perm;
c4f035c6 3502 c->intercept = opcode.intercept;
dde7e6d1
AK		 3503
3504 /* Unrecognised? */
d53db5ef 3505 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3506 return -1;
dde7e6d1 3507
d867162c
AK		 3508 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3509 return -1;
3510
dde7e6d1
AK		 3511 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3512 c->op_bytes = 8;
3513
7f9b4b75
AK		 3514 if (c->d & Op3264) {
3515 if (mode == X86EMUL_MODE_PROT64)
3516 c->op_bytes = 8;
3517 else
3518 c->op_bytes = 4;
3519 }
3520
1253791d
AK		 3521 if (c->d & Sse)
3522 c->op_bytes = 16;
3523
dde7e6d1 3524 /* ModRM and SIB bytes. */
09ee57cd 3525 if (c->d & ModRM) {
ef5d75cc 3526 rc = decode_modrm(ctxt, &memop);
09ee57cd
AK		 3527 if (!c->has_seg_override)
3528 set_seg_override(c, c->modrm_seg);
3529 } else if (c->d & MemAbs)
ef5d75cc 3530 rc = decode_abs(ctxt, &memop);
dde7e6d1
AK		 3531 if (rc != X86EMUL_CONTINUE)
3532 goto done;
3533
3534 if (!c->has_seg_override)
3535 set_seg_override(c, VCPU_SREG_DS);
3536
c1ed6dea 3537 memop.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1 3538
2dbd0dd7 3539 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3540 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3541
dde7e6d1
AK		 3542 /*
3543 * Decode and fetch the source operand: register, memory
3544 * or immediate.
3545 */
3546 switch (c->d & SrcMask) {
3547 case SrcNone:
3548 break;
3549 case SrcReg:
1253791d 3550 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3551 break;
3552 case SrcMem16:
2dbd0dd7 3553 memop.bytes = 2;
dde7e6d1
AK		 3554 goto srcmem_common;
3555 case SrcMem32:
2dbd0dd7 3556 memop.bytes = 4;
dde7e6d1
AK		 3557 goto srcmem_common;
3558 case SrcMem:
2dbd0dd7 3559 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3560 c->op_bytes;
dde7e6d1 3561 srcmem_common:
2dbd0dd7 3562 c->src = memop;
cb16c348 3563 memopp = &c->src;
dde7e6d1 3564 break;
b250e605 3565 case SrcImmU16:
39f21ee5
AK		 3566 rc = decode_imm(ctxt, &c->src, 2, false);
3567 break;
dde7e6d1 3568 case SrcImm:
39f21ee5
AK		 3569 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3570 break;
dde7e6d1 3571 case SrcImmU:
39f21ee5 3572 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3573 break;
3574 case SrcImmByte:
39f21ee5
AK		 3575 rc = decode_imm(ctxt, &c->src, 1, true);
3576 break;
dde7e6d1 3577 case SrcImmUByte:
39f21ee5 3578 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3579 break;
3580 case SrcAcc:
3581 c->src.type = OP_REG;
3582 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3583 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3584 fetch_register_operand(&c->src);
dde7e6d1
AK		 3585 break;
3586 case SrcOne:
3587 c->src.bytes = 1;
3588 c->src.val = 1;
3589 break;
3590 case SrcSI:
3591 c->src.type = OP_MEM;
3592 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3593 c->src.addr.mem.ea =
3594 register_address(c, c->regs[VCPU_REGS_RSI]);
c1ed6dea 3595 c->src.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1
AK		 3596 c->src.val = 0;
3597 break;
3598 case SrcImmFAddr:
3599 c->src.type = OP_IMM;
90de84f5 3600 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3601 c->src.bytes = c->op_bytes + 2;
3602 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3603 break;
3604 case SrcMemFAddr:
2dbd0dd7
AK		 3605 memop.bytes = c->op_bytes + 2;
3606 goto srcmem_common;
dde7e6d1 3607 break;
221192bd
MT		 3608 case SrcDX:
3609 c->src.type = OP_REG;
3610 c->src.bytes = 2;
3611 c->src.addr.reg = &c->regs[VCPU_REGS_RDX];
3612 fetch_register_operand(&c->src);
3613 break;
dde7e6d1
AK		 3614 }
3615
39f21ee5
AK		 3616 if (rc != X86EMUL_CONTINUE)
3617 goto done;
3618
dde7e6d1
AK		 3619 /*
3620 * Decode and fetch the second source operand: register, memory
3621 * or immediate.
3622 */
3623 switch (c->d & Src2Mask) {
3624 case Src2None:
3625 break;
3626 case Src2CL:
3627 c->src2.bytes = 1;
3628 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3629 break;
3630 case Src2ImmByte:
39f21ee5 3631 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3632 break;
3633 case Src2One:
3634 c->src2.bytes = 1;
3635 c->src2.val = 1;
3636 break;
7db41eb7
AK		 3637 case Src2Imm:
3638 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3639 break;
dde7e6d1
AK		 3640 }
3641
39f21ee5
AK		 3642 if (rc != X86EMUL_CONTINUE)
3643 goto done;
3644
dde7e6d1
AK		 3645 /* Decode and fetch the destination operand: register or memory. */
3646 switch (c->d & DstMask) {
dde7e6d1 3647 case DstReg:
1253791d 3648 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3649 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3650 break;
943858e2
WY		 3651 case DstImmUByte:
3652 c->dst.type = OP_IMM;
90de84f5 3653 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3654 c->dst.bytes = 1;
3655 c->dst.val = insn_fetch(u8, 1, c->eip);
3656 break;
dde7e6d1
AK		 3657 case DstMem:
3658 case DstMem64:
2dbd0dd7 3659 c->dst = memop;
cb16c348 3660 memopp = &c->dst;
dde7e6d1
AK		 3661 if ((c->d & DstMask) == DstMem64)
3662 c->dst.bytes = 8;
3663 else
3664 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3665 if (c->d & BitOp)
3666 fetch_bit_operand(c);
2dbd0dd7 3667 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3668 break;
3669 case DstAcc:
3670 c->dst.type = OP_REG;
3671 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3672 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3673 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3674 c->dst.orig_val = c->dst.val;
3675 break;
3676 case DstDI:
3677 c->dst.type = OP_MEM;
3678 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3679 c->dst.addr.mem.ea =
3680 register_address(c, c->regs[VCPU_REGS_RDI]);
3681 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3682 c->dst.val = 0;
3683 break;
221192bd
MT		 3684 case DstDX:
3685 c->dst.type = OP_REG;
3686 c->dst.bytes = 2;
3687 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
3688 fetch_register_operand(&c->dst);
3689 break;
36089fed
WY		 3690 case ImplicitOps:
3691 /* Special instructions do their own operand decoding. */
3692 default:
3693 c->dst.type = OP_NONE; /* Disable writeback. */
cb16c348 3694 break;
dde7e6d1
AK		 3695 }
3696
3697done:
cb16c348
AK		 3698 if (memopp && memopp->type == OP_MEM && c->rip_relative)
3699 memopp->addr.mem.ea += c->eip;
3700
a0c0ab2f 3701 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3702}
3703
3e2f65d5
GN		 3704static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3705{
3706 struct decode_cache *c = &ctxt->decode;
3707
3708 /* The second termination condition only applies for REPE
3709 * and REPNE. Test if the repeat string operation prefix is
3710 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3711 * corresponding termination condition according to:
3712 * - if REPE/REPZ and ZF = 0 then done
3713 * - if REPNE/REPNZ and ZF = 1 then done
3714 */
3715 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3716 (c->b == 0xae) || (c->b == 0xaf))
3717 && (((c->rep_prefix == REPE_PREFIX) &&
3718 ((ctxt->eflags & EFLG_ZF) == 0))
3719 || ((c->rep_prefix == REPNE_PREFIX) &&
3720 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3721 return true;
3722
3723 return false;
3724}
3725
7b105ca2 3726int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3727{
9aabc88f 3728 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3729 u64 msr_data;
8b4caf66 3730 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3731 int rc = X86EMUL_CONTINUE;
5cd21917 3732 int saved_dst_type = c->dst.type;
6e154e56 3733 int irq; /* Used for int 3, int, and into */
8b4caf66 3734
9d74191a 3735 c->mem_read.pos = 0;
310b5d30 3736
1161624f 3737 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3738 rc = emulate_ud(ctxt);
1161624f
GN		 3739 goto done;
3740 }
3741
d380a5e4 3742 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3743 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3744 rc = emulate_ud(ctxt);
d380a5e4
GN		 3745 goto done;
3746 }
3747
081bca0e 3748 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3749 rc = emulate_ud(ctxt);
081bca0e
AK		 3750 goto done;
3751 }
3752
1253791d 3753 if ((c->d & Sse)
717746e3
AK		 3754 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3755 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3756 rc = emulate_ud(ctxt);
3757 goto done;
3758 }
3759
717746e3 3760 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3761 rc = emulate_nm(ctxt);
3762 goto done;
3763 }
3764
c4f035c6 3765 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3766 rc = emulator_check_intercept(ctxt, c->intercept,
3767 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3768 if (rc != X86EMUL_CONTINUE)
3769 goto done;
3770 }
3771
e92805ac 3772 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3773 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3774 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3775 goto done;
3776 }
3777
8ea7d6ae
JR		 3778 /* Instruction can only be executed in protected mode */
3779 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3780 rc = emulate_ud(ctxt);
3781 goto done;
3782 }
3783
d09beabd
JR		 3784 /* Do instruction specific permission checks */
3785 if (c->check_perm) {
3786 rc = c->check_perm(ctxt);
3787 if (rc != X86EMUL_CONTINUE)
3788 goto done;
3789 }
3790
c4f035c6 3791 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3792 rc = emulator_check_intercept(ctxt, c->intercept,
3793 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3794 if (rc != X86EMUL_CONTINUE)
3795 goto done;
3796 }
3797
b9fa9d6b
AK		 3798 if (c->rep_prefix && (c->d & String)) {
3799 /* All REP prefixes have the same first termination condition */
c73e197b 3800 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3801 ctxt->eip = c->eip;
b9fa9d6b
AK		 3802 goto done;
3803 }
b9fa9d6b
AK		 3804 }
3805
c483c02a 3806 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3807 rc = segmented_read(ctxt, c->src.addr.mem,
3808 c->src.valptr, c->src.bytes);
b60d513c 3809 if (rc != X86EMUL_CONTINUE)
8b4caf66 3810 goto done;
16518d5a 3811 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3812 }
3813
e35b7b9c 3814 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3815 rc = segmented_read(ctxt, c->src2.addr.mem,
3816 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3817 if (rc != X86EMUL_CONTINUE)
3818 goto done;
3819 }
3820
8b4caf66
LV		 3821 if ((c->d & DstMask) == ImplicitOps)
3822 goto special_insn;
3823
3824
69f55cb1
GN		 3825 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3826 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3827 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3828 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3829 if (rc != X86EMUL_CONTINUE)
3830 goto done;
038e51de 3831 }
e4e03ded 3832 c->dst.orig_val = c->dst.val;
038e51de 3833
018a98db
AK		 3834special_insn:
3835
c4f035c6 3836 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3837 rc = emulator_check_intercept(ctxt, c->intercept,
3838 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3839 if (rc != X86EMUL_CONTINUE)
3840 goto done;
3841 }
3842
ef65c889
AK		 3843 if (c->execute) {
3844 rc = c->execute(ctxt);
3845 if (rc != X86EMUL_CONTINUE)
3846 goto done;
3847 goto writeback;
3848 }
3849
e4e03ded 3850 if (c->twobyte)
6aa8b732
AK		 3851 goto twobyte_insn;
3852
e4e03ded 3853 switch (c->b) {
0934ac9d 3854 case 0x06: /* push es */
7b105ca2 3855 rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
0934ac9d
MG		 3856 break;
3857 case 0x07: /* pop es */
7b105ca2 3858 rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
0934ac9d 3859 break;
0934ac9d 3860 case 0x0e: /* push cs */
7b105ca2 3861 rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
0934ac9d 3862 break;
0934ac9d 3863 case 0x16: /* push ss */
7b105ca2 3864 rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
0934ac9d
MG		 3865 break;
3866 case 0x17: /* pop ss */
7b105ca2 3867 rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
0934ac9d 3868 break;
0934ac9d 3869 case 0x1e: /* push ds */
7b105ca2 3870 rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
0934ac9d
MG		 3871 break;
3872 case 0x1f: /* pop ds */
7b105ca2 3873 rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
0934ac9d 3874 break;
33615aa9
AK		 3875 case 0x40 ... 0x47: /* inc r16/r32 */
3876 emulate_1op("inc", c->dst, ctxt->eflags);
3877 break;
3878 case 0x48 ... 0x4f: /* dec r16/r32 */
3879 emulate_1op("dec", c->dst, ctxt->eflags);
3880 break;
6aa8b732 3881 case 0x63: /* movsxd */
8b4caf66 3882 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3883 goto cannot_emulate;
e4e03ded 3884 c->dst.val = (s32) c->src.val;
6aa8b732 3885 break;
018a98db
AK		 3886 case 0x6c: /* insb */
3887 case 0x6d: /* insw/insd */
a13a63fa
WY		 3888 c->src.val = c->regs[VCPU_REGS_RDX];
3889 goto do_io_in;
018a98db
AK		 3890 case 0x6e: /* outsb */
3891 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3892 c->dst.val = c->regs[VCPU_REGS_RDX];
3893 goto do_io_out;
7972995b 3894 break;
b2833e3c 3895 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3896 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3897 jmp_rel(c, c->src.val);
018a98db 3898 break;
79168fd1
GN		 3899 case 0x8c: /* mov r/m, sreg */
3900 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3901 rc = emulate_ud(ctxt);
5e3ae6c5 3902 goto done;
38d5bc6d 3903 }
1aa36616 3904 c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3905 break;
7e0b54b1 3906 case 0x8d: /* lea r16/r32, m */
90de84f5 3907 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3908 break;
4257198a
GT		 3909 case 0x8e: { /* mov seg, r/m16 */
3910 uint16_t sel;
4257198a
GT		 3911
3912 sel = c->src.val;
8b9f4414 3913
c697518a
GN		 3914 if (c->modrm_reg == VCPU_SREG_CS ||
3915 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3916 rc = emulate_ud(ctxt);
8b9f4414
GN		 3917 goto done;
3918 }
3919
310b5d30 3920 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3921 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3922
7b105ca2 3923 rc = load_segment_descriptor(ctxt, sel, c->modrm_reg);
4257198a
GT		 3924
3925 c->dst.type = OP_NONE; /* Disable writeback. */
3926 break;
3927 }
6aa8b732 3928 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3929 rc = em_grp1a(ctxt);
6aa8b732 3930 break;
3d9e77df
AK		 3931 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3932 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3933 break;
e4f973ae
TY		 3934 rc = em_xchg(ctxt);
3935 break;
e8b6fa70
WY		 3936 case 0x98: /* cbw/cwde/cdqe */
3937 switch (c->op_bytes) {
3938 case 2: c->dst.val = (s8)c->dst.val; break;
3939 case 4: c->dst.val = (s16)c->dst.val; break;
3940 case 8: c->dst.val = (s32)c->dst.val; break;
3941 }
3942 break;
018a98db 3943 case 0xc0 ... 0xc1:
51187683 3944 rc = em_grp2(ctxt);
018a98db 3945 break;
111de5d6 3946 case 0xc3: /* ret */
cf5de4f8 3947 c->dst.type = OP_REG;
1a6440ae 3948 c->dst.addr.reg = &c->eip;
cf5de4f8 3949 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3950 rc = em_pop(ctxt);
3951 break;
09b5f4d3 3952 case 0xc4: /* les */
7b105ca2 3953 rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
09b5f4d3
WY		 3954 break;
3955 case 0xc5: /* lds */
7b105ca2 3956 rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
09b5f4d3 3957 break;
6e154e56
MG		 3958 case 0xcc: /* int3 */
3959 irq = 3;
3960 goto do_interrupt;
3961 case 0xcd: /* int n */
3962 irq = c->src.val;
3963 do_interrupt:
7b105ca2 3964 rc = emulate_int(ctxt, irq);
6e154e56
MG		 3965 break;
3966 case 0xce: /* into */
3967 if (ctxt->eflags & EFLG_OF) {
3968 irq = 4;
3969 goto do_interrupt;
3970 }
3971 break;
018a98db 3972 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3973 rc = em_grp2(ctxt);
018a98db
AK		 3974 break;
3975 case 0xd2 ... 0xd3: /* Grp2 */
3976 c->src.val = c->regs[VCPU_REGS_RCX];
51187683 3977 rc = em_grp2(ctxt);
018a98db 3978 break;
f2f31845
WY		 3979 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3980 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3981 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3982 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3983 jmp_rel(c, c->src.val);
3984 break;
e4abac67
WY		 3985 case 0xe3: /* jcxz/jecxz/jrcxz */
3986 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3987 jmp_rel(c, c->src.val);
3988 break;
a6a3034c
MG		 3989 case 0xe4: /* inb */
3990 case 0xe5: /* in */
cf8f70bf 3991 goto do_io_in;
a6a3034c
MG		 3992 case 0xe6: /* outb */
3993 case 0xe7: /* out */
cf8f70bf 3994 goto do_io_out;
1a52e051 3995 case 0xe8: /* call (near) */ {
d53c4777 3996 long int rel = c->src.val;
e4e03ded 3997 c->src.val = (unsigned long) c->eip;
7a957275 3998 jmp_rel(c, rel);
4487b3b4 3999 rc = em_push(ctxt);
8cdbd2c9 4000 break;
1a52e051
NK		 4001 }
4002 case 0xe9: /* jmp rel */
db5b0762 4003 case 0xeb: /* jmp rel short */
7a957275 4004 jmp_rel(c, c->src.val);
a01af5ec 4005 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4006 break;
a6a3034c
MG		 4007 case 0xec: /* in al,dx */
4008 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 4009 do_io_in:
7b105ca2 4010 if (!pio_in_emulated(ctxt, c->dst.bytes, c->src.val,
7b262e90 4011 &c->dst.val))
cf8f70bf
GN		 4012 goto done; /* IO is needed */
4013 break;
ce7a0ad3
WY		 4014 case 0xee: /* out dx,al */
4015 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 4016 do_io_out:
ca1d4a9e
AK		 4017 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4018 &c->src.val, 1);
cf8f70bf 4019 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4020 break;
111de5d6 4021 case 0xf4: /* hlt */
6c3287f7 4022 ctxt->ops->halt(ctxt);
19fdfa0d 4023 break;
111de5d6
AK		 4024 case 0xf5: /* cmc */
4025 /* complement carry flag from eflags reg */
4026 ctxt->eflags ^= EFLG_CF;
111de5d6 4027 break;
018a98db 4028 case 0xf6 ... 0xf7: /* Grp3 */
51187683 4029 rc = em_grp3(ctxt);
018a98db 4030 break;
111de5d6
AK		 4031 case 0xf8: /* clc */
4032 ctxt->eflags &= ~EFLG_CF;
111de5d6 4033 break;
8744aa9a
MG		 4034 case 0xf9: /* stc */
4035 ctxt->eflags |= EFLG_CF;
4036 break;
111de5d6 4037 case 0xfa: /* cli */
7b105ca2 4038 if (emulator_bad_iopl(ctxt)) {
35d3d4a1 4039 rc = emulate_gp(ctxt, 0);
07cbc6c1 4040 goto done;
36089fed 4041 } else
f850e2e6 4042 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4043 break;
4044 case 0xfb: /* sti */
7b105ca2 4045 if (emulator_bad_iopl(ctxt)) {
35d3d4a1 4046 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4047 goto done;
4048 } else {
95cb2295 4049 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4050 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4051 }
111de5d6 4052 break;
fb4616f4
MG		 4053 case 0xfc: /* cld */
4054 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4055 break;
4056 case 0xfd: /* std */
4057 ctxt->eflags |= EFLG_DF;
fb4616f4 4058 break;
ea79849d 4059 case 0xfe: /* Grp4 */
51187683 4060 rc = em_grp45(ctxt);
018a98db 4061 break;
ea79849d 4062 case 0xff: /* Grp5 */
51187683
TY		 4063 rc = em_grp45(ctxt);
4064 break;
91269b8f
AK		 4065 default:
4066 goto cannot_emulate;
6aa8b732 4067 }
018a98db 4068
7d9ddaed
AK		 4069 if (rc != X86EMUL_CONTINUE)
4070 goto done;
4071
018a98db 4072writeback:
adddcecf 4073 rc = writeback(ctxt);
1b30eaa8 4074 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4075 goto done;
4076
5cd21917
GN		 4077 /*
4078 * restore dst type in case the decoding will be reused
4079 * (happens for string instruction )
4080 */
4081 c->dst.type = saved_dst_type;
4082
a682e354 4083 if ((c->d & SrcMask) == SrcSI)
c1ed6dea 4084 string_addr_inc(ctxt, seg_override(ctxt, c),
79168fd1 4085 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4086
4087 if ((c->d & DstMask) == DstDI)
90de84f5 4088 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4089 &c->dst);
d9271123 4090
5cd21917 4091 if (c->rep_prefix && (c->d & String)) {
9d74191a 4092 struct read_cache *r = &c->io_read;
d9271123 4093 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4094
d2ddd1c4
GN		 4095 if (!string_insn_completed(ctxt)) {
4096 /*
4097 * Re-enter guest when pio read ahead buffer is empty
4098 * or, if it is not used, after each 1024 iteration.
4099 */
4100 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4101 (r->end == 0 || r->end != r->pos)) {
4102 /*
4103 * Reset read cache. Usually happens before
4104 * decode, but since instruction is restarted
4105 * we have to do it here.
4106 */
9d74191a 4107 c->mem_read.end = 0;
d2ddd1c4
GN		 4108 return EMULATION_RESTART;
4109 }
4110 goto done; /* skip rip writeback */
0fa6ccbd 4111 }
5cd21917 4112 }
d2ddd1c4
GN		 4113
4114 ctxt->eip = c->eip;
018a98db
AK		 4115
4116done:
da9cb575
AK		 4117 if (rc == X86EMUL_PROPAGATE_FAULT)
4118 ctxt->have_exception = true;
775fde86
JR		 4119 if (rc == X86EMUL_INTERCEPTED)
4120 return EMULATION_INTERCEPTED;
4121
d2ddd1c4 4122 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4123
4124twobyte_insn:
e4e03ded 4125 switch (c->b) {
018a98db 4126 case 0x09: /* wbinvd */
cfb22375 4127 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4128 break;
4129 case 0x08: /* invd */
018a98db
AK		 4130 case 0x0d: /* GrpP (prefetch) */
4131 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4132 break;
4133 case 0x20: /* mov cr, reg */
717746e3 4134 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4135 break;
6aa8b732 4136 case 0x21: /* mov from dr to reg */
717746e3 4137 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4138 break;
018a98db 4139 case 0x22: /* mov reg, cr */
717746e3 4140 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4141 emulate_gp(ctxt, 0);
da9cb575 4142 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4143 goto done;
4144 }
018a98db
AK		 4145 c->dst.type = OP_NONE;
4146 break;
6aa8b732 4147 case 0x23: /* mov from reg to dr */
717746e3 4148 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4149 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4150 ~0ULL : ~0U)) < 0) {
338dbc97 4151 /* #UD condition is already handled by the code above */
54b8486f 4152 emulate_gp(ctxt, 0);
da9cb575 4153 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4154 goto done;
4155 }
4156
a01af5ec 4157 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4158 break;
018a98db
AK		 4159 case 0x30:
4160 /* wrmsr */
4161 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4162 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4163 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4164 emulate_gp(ctxt, 0);
da9cb575 4165 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4166 goto done;
018a98db
AK		 4167 }
4168 rc = X86EMUL_CONTINUE;
018a98db
AK		 4169 break;
4170 case 0x32:
4171 /* rdmsr */
717746e3 4172 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4173 emulate_gp(ctxt, 0);
da9cb575 4174 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4175 goto done;
018a98db
AK		 4176 } else {
4177 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4178 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4179 }
4180 rc = X86EMUL_CONTINUE;
018a98db 4181 break;
6aa8b732 4182 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4183 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4184 if (!test_cc(c->b, ctxt->eflags))
4185 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4186 break;
b2833e3c 4187 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4188 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4189 jmp_rel(c, c->src.val);
018a98db 4190 break;
ee45b58e
WY		 4191 case 0x90 ... 0x9f: /* setcc r/m8 */
4192 c->dst.val = test_cc(c->b, ctxt->eflags);
4193 break;
0934ac9d 4194 case 0xa0: /* push fs */
7b105ca2 4195 rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
0934ac9d
MG		 4196 break;
4197 case 0xa1: /* pop fs */
7b105ca2 4198 rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
0934ac9d 4199 break;
7de75248
NK		 4200 case 0xa3:
4201 bt: /* bt */
e4f8e039 4202 c->dst.type = OP_NONE;
e4e03ded
LV		 4203 /* only subword offset */
4204 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4205 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4206 break;
9bf8ea42
GT		 4207 case 0xa4: /* shld imm8, r, r/m */
4208 case 0xa5: /* shld cl, r, r/m */
4209 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4210 break;
0934ac9d 4211 case 0xa8: /* push gs */
7b105ca2 4212 rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
0934ac9d
MG		 4213 break;
4214 case 0xa9: /* pop gs */
7b105ca2 4215 rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
0934ac9d 4216 break;
7de75248
NK		 4217 case 0xab:
4218 bts: /* bts */
05f086f8 4219 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4220 break;
9bf8ea42
GT		 4221 case 0xac: /* shrd imm8, r, r/m */
4222 case 0xad: /* shrd cl, r, r/m */
4223 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4224 break;
2a7c5b8b
GC		 4225 case 0xae: /* clflush */
4226 break;
6aa8b732
AK		 4227 case 0xb0 ... 0xb1: /* cmpxchg */
4228 /*
4229 * Save real source value, then compare EAX against
4230 * destination.
4231 */
e4e03ded
LV		 4232 c->src.orig_val = c->src.val;
4233 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4234 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4235 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4236 /* Success: write back to memory. */
e4e03ded 4237 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4238 } else {
4239 /* Failure: write the value we saw to EAX. */
e4e03ded 4240 c->dst.type = OP_REG;
1a6440ae 4241 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4242 }
4243 break;
09b5f4d3 4244 case 0xb2: /* lss */
7b105ca2 4245 rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
09b5f4d3 4246 break;
6aa8b732
AK		 4247 case 0xb3:
4248 btr: /* btr */
05f086f8 4249 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4250 break;
09b5f4d3 4251 case 0xb4: /* lfs */
7b105ca2 4252 rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
09b5f4d3
WY		 4253 break;
4254 case 0xb5: /* lgs */
7b105ca2 4255 rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
09b5f4d3 4256 break;
6aa8b732 4257 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4258 c->dst.bytes = c->op_bytes;
4259 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4260 : (u16) c->src.val;
6aa8b732 4261 break;
6aa8b732 4262 case 0xba: /* Grp8 */
e4e03ded 4263 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4264 case 0:
4265 goto bt;
4266 case 1:
4267 goto bts;
4268 case 2:
4269 goto btr;
4270 case 3:
4271 goto btc;
4272 }
4273 break;
7de75248
NK		 4274 case 0xbb:
4275 btc: /* btc */
05f086f8 4276 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4277 break;
d9574a25
WY		 4278 case 0xbc: { /* bsf */
4279 u8 zf;
4280 __asm__ ("bsf %2, %0; setz %1"
4281 : "=r"(c->dst.val), "=q"(zf)
4282 : "r"(c->src.val));
4283 ctxt->eflags &= ~X86_EFLAGS_ZF;
4284 if (zf) {
4285 ctxt->eflags |= X86_EFLAGS_ZF;
4286 c->dst.type = OP_NONE; /* Disable writeback. */
4287 }
4288 break;
4289 }
4290 case 0xbd: { /* bsr */
4291 u8 zf;
4292 __asm__ ("bsr %2, %0; setz %1"
4293 : "=r"(c->dst.val), "=q"(zf)
4294 : "r"(c->src.val));
4295 ctxt->eflags &= ~X86_EFLAGS_ZF;
4296 if (zf) {
4297 ctxt->eflags |= X86_EFLAGS_ZF;
4298 c->dst.type = OP_NONE; /* Disable writeback. */
4299 }
4300 break;
4301 }
6aa8b732 4302 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4303 c->dst.bytes = c->op_bytes;
4304 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4305 (s16) c->src.val;
6aa8b732 4306 break;
92f738a5
WY		 4307 case 0xc0 ... 0xc1: /* xadd */
4308 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4309 /* Write back the register source. */
4310 c->src.val = c->dst.orig_val;
4311 write_register_operand(&c->src);
4312 break;
a012e65a 4313 case 0xc3: /* movnti */
e4e03ded
LV		 4314 c->dst.bytes = c->op_bytes;
4315 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4316 (u64) c->src.val;
a012e65a 4317 break;
6aa8b732 4318 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4319 rc = em_grp9(ctxt);
8cdbd2c9 4320 break;
91269b8f
AK		 4321 default:
4322 goto cannot_emulate;
6aa8b732 4323 }
7d9ddaed
AK		 4324
4325 if (rc != X86EMUL_CONTINUE)
4326 goto done;
4327
6aa8b732
AK		 4328 goto writeback;
4329
4330cannot_emulate:
a0c0ab2f 4331 return EMULATION_FAILED;
6aa8b732 4332}
Linux kernel - Deliverables
This page took 0.731603 seconds and 5 git commands to generate.