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KVM: x86 emulator: convert group 3 to new style
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
ea9ef04e
AK		 98#define X2(x) x, x
99#define X3(x) X2(x), x
83babbca 100#define X4(x) X2(x), X2(x)
ea9ef04e 101#define X5(x) X4(x), x
83babbca
AK		 102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
ee70ea30 108 NoGrp, Group4, Group5, Group7, Group8, Group9,
43bb19cd
AK		 109};
110
d65b1dee
AK		 111struct opcode {
112 u32 flags;
120df890
AK		 113 union {
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
fd853310
AK		 124#define D(_y) { .flags = (_y) }
125#define N D(0)
120df890
AK		 126#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
127#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
fd853310 128
5b92b5fa
AK		 129static struct opcode group1[] = {
130 X7(D(Lock)), N
131};
132
99880c5c 133static struct opcode group1A[] = {
42a1c520 134 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
99880c5c
AK		 135};
136
ee70ea30 137static struct opcode group3[] = {
42a1c520
AK		 138 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
139 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
140 X4(D(Undefined)),
ee70ea30
AK		 141};
142
143static struct opcode group_table[] = {
42a1c520
AK		 144 [Group4*8] =
145 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
146 N, N, N, N, N, N,
147 [Group5*8] =
148 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
149 D(SrcMem | ModRM | Stack), N,
150 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
151 D(SrcMem | ModRM | Stack), N,
152 [Group7*8] =
153 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
154 D(SrcNone | ModRM | DstMem | Mov), N,
155 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
156 [Group8*8] =
157 N, N, N, N,
158 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
159 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
160 [Group9*8] =
161 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
162};
163
164static struct opcode group2_table[] = {
165 [Group7*8] =
166 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
167 D(SrcNone | ModRM | DstMem | Mov), N,
168 D(SrcMem16 | ModRM | Mov | Priv), N,
169 [Group9*8] =
170 N, N, N, N, N, N, N, N,
171};
172
d65b1dee 173static struct opcode opcode_table[256] = {
6aa8b732 174 /* 0x00 - 0x07 */
fd853310
AK		 175 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
176 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
177 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
178 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 179 /* 0x08 - 0x0F */
fd853310
AK		 180 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
181 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
182 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
183 D(ImplicitOps | Stack | No64), N,
6aa8b732 184 /* 0x10 - 0x17 */
fd853310
AK		 185 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
186 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
187 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
188 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 189 /* 0x18 - 0x1F */
fd853310
AK		 190 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
191 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
192 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
193 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 194 /* 0x20 - 0x27 */
fd853310
AK		 195 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
196 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
197 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 198 /* 0x28 - 0x2F */
fd853310
AK		 199 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
200 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
201 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 202 /* 0x30 - 0x37 */
fd853310
AK		 203 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
204 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
205 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 206 /* 0x38 - 0x3F */
fd853310
AK		 207 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
208 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
209 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
210 N, N,
749358a6 211 /* 0x40 - 0x4F */
fd853310 212 X16(D(DstReg)),
7f0aaee0 213 /* 0x50 - 0x57 */
fd853310 214 X8(D(SrcReg | Stack)),
7f0aaee0 215 /* 0x58 - 0x5F */
fd853310 216 X8(D(DstReg | Stack)),
7d316911 217 /* 0x60 - 0x67 */
fd853310
AK		 218 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
219 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
220 N, N, N, N,
7d316911 221 /* 0x68 - 0x6F */
fd853310
AK		 222 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
223 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
224 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 225 /* 0x70 - 0x7F */
fd853310 226 X16(D(SrcImmByte)),
6aa8b732 227 /* 0x80 - 0x87 */
5b92b5fa
AK		 228 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
229 G(DstMem | SrcImm | ModRM | Group, group1),
230 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
231 G(DstMem | SrcImmByte | ModRM | Group, group1),
fd853310
AK		 232 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
233 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 234 /* 0x88 - 0x8F */
fd853310
AK		 235 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
236 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
237 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
99880c5c 238 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
b13354f8 239 /* 0x90 - 0x97 */
fd853310 240 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 241 /* 0x98 - 0x9F */
fd853310
AK		 242 N, N, D(SrcImmFAddr | No64), N,
243 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 244 /* 0xA0 - 0xA7 */
fd853310
AK		 245 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
246 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
247 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
248 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 249 /* 0xA8 - 0xAF */
fd853310
AK		 250 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
251 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
252 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 253 /* 0xB0 - 0xB7 */
fd853310 254 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 255 /* 0xB8 - 0xBF */
fd853310 256 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 257 /* 0xC0 - 0xC7 */
fd853310
AK		 258 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
259 N, D(ImplicitOps | Stack), N, N,
260 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 261 /* 0xC8 - 0xCF */
fd853310
AK		 262 N, N, N, D(ImplicitOps | Stack),
263 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 264 /* 0xD0 - 0xD7 */
fd853310
AK		 265 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
266 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
267 N, N, N, N,
6aa8b732 268 /* 0xD8 - 0xDF */
fd853310 269 N, N, N, N, N, N, N, N,
098c937b 270 /* 0xE0 - 0xE7 */
fd853310
AK		 271 N, N, N, N,
272 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
273 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 274 /* 0xE8 - 0xEF */
fd853310
AK		 275 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
276 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
277 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
278 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 279 /* 0xF0 - 0xF7 */
fd853310 280 N, N, N, N,
ee70ea30 281 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
6aa8b732 282 /* 0xF8 - 0xFF */
fd853310
AK		 283 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
284 D(ImplicitOps), D(ImplicitOps), D(Group | Group4), D(Group | Group5),
6aa8b732
AK		 285};
286
d65b1dee 287static struct opcode twobyte_table[256] = {
6aa8b732 288 /* 0x00 - 0x0F */
fd853310
AK		 289 N, D(Group | GroupDual | Group7), N, N,
290 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
291 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
292 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 293 /* 0x10 - 0x1F */
fd853310 294 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 295 /* 0x20 - 0x2F */
fd853310
AK		 296 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
297 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
298 N, N, N, N,
299 N, N, N, N, N, N, N, N,
6aa8b732 300 /* 0x30 - 0x3F */
fd853310
AK		 301 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
302 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
303 N, N, N, N, N, N, N, N,
be8eacdd 304 /* 0x40 - 0x4F */
fd853310 305 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 306 /* 0x50 - 0x5F */
fd853310 307 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 308 /* 0x60 - 0x6F */
fd853310 309 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 310 /* 0x70 - 0x7F */
fd853310 311 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 312 /* 0x80 - 0x8F */
fd853310 313 X16(D(SrcImm)),
6aa8b732 314 /* 0x90 - 0x9F */
fd853310 315 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 316 /* 0xA0 - 0xA7 */
fd853310
AK		 317 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
318 N, D(DstMem | SrcReg | ModRM | BitOp),
319 D(DstMem | SrcReg | Src2ImmByte | ModRM),
320 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 321 /* 0xA8 - 0xAF */
fd853310
AK		 322 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
323 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
324 D(DstMem | SrcReg | Src2ImmByte | ModRM),
325 D(DstMem | SrcReg | Src2CL | ModRM),
326 D(ModRM), N,
6aa8b732 327 /* 0xB0 - 0xB7 */
fd853310
AK		 328 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
329 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
330 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
331 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 332 /* 0xB8 - 0xBF */
fd853310
AK		 333 N, N,
334 D(Group | Group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
335 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
336 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 337 /* 0xC0 - 0xCF */
fd853310
AK		 338 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
339 N, N, N, D(Group | GroupDual | Group9),
340 N, N, N, N, N, N, N, N,
6aa8b732 341 /* 0xD0 - 0xDF */
fd853310 342 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 343 /* 0xE0 - 0xEF */
fd853310 344 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 345 /* 0xF0 - 0xFF */
fd853310 346 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 347};
348
fd853310
AK		 349#undef D
350#undef N
120df890
AK		 351#undef G
352#undef GD
fd853310 353
6aa8b732 354/* EFLAGS bit definitions. */
d4c6a154
GN		 355#define EFLG_ID (1<<21)
356#define EFLG_VIP (1<<20)
357#define EFLG_VIF (1<<19)
358#define EFLG_AC (1<<18)
b1d86143
AP		 359#define EFLG_VM (1<<17)
360#define EFLG_RF (1<<16)
d4c6a154
GN		 361#define EFLG_IOPL (3<<12)
362#define EFLG_NT (1<<14)
6aa8b732
AK		 363#define EFLG_OF (1<<11)
364#define EFLG_DF (1<<10)
b1d86143 365#define EFLG_IF (1<<9)
d4c6a154 366#define EFLG_TF (1<<8)
6aa8b732
AK		 367#define EFLG_SF (1<<7)
368#define EFLG_ZF (1<<6)
369#define EFLG_AF (1<<4)
370#define EFLG_PF (1<<2)
371#define EFLG_CF (1<<0)
372
62bd430e
MG		 373#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
374#define EFLG_RESERVED_ONE_MASK 2
375
6aa8b732
AK		 376/*
377 * Instruction emulation:
378 * Most instructions are emulated directly via a fragment of inline assembly
379 * code. This allows us to save/restore EFLAGS and thus very easily pick up
380 * any modified flags.
381 */
382
05b3e0c2 383#if defined(CONFIG_X86_64)
6aa8b732
AK		 384#define _LO32 "k" /* force 32-bit operand */
385#define _STK "%%rsp" /* stack pointer */
386#elif defined(__i386__)
387#define _LO32 "" /* force 32-bit operand */
388#define _STK "%%esp" /* stack pointer */
389#endif
390
391/*
392 * These EFLAGS bits are restored from saved value during emulation, and
393 * any changes are written back to the saved value after emulation.
394 */
395#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
396
397/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 398#define _PRE_EFLAGS(_sav, _msk, _tmp) \
399 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
400 "movl %"_sav",%"_LO32 _tmp"; " \
401 "push %"_tmp"; " \
402 "push %"_tmp"; " \
403 "movl %"_msk",%"_LO32 _tmp"; " \
404 "andl %"_LO32 _tmp",("_STK"); " \
405 "pushf; " \
406 "notl %"_LO32 _tmp"; " \
407 "andl %"_LO32 _tmp",("_STK"); " \
408 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
409 "pop %"_tmp"; " \
410 "orl %"_LO32 _tmp",("_STK"); " \
411 "popf; " \
412 "pop %"_sav"; "
6aa8b732
AK		 413
414/* After executing instruction: write-back necessary bits in EFLAGS. */
415#define _POST_EFLAGS(_sav, _msk, _tmp) \
416 /* _sav |= EFLAGS & _msk; */ \
417 "pushf; " \
418 "pop %"_tmp"; " \
419 "andl %"_msk",%"_LO32 _tmp"; " \
420 "orl %"_LO32 _tmp",%"_sav"; "
421
dda96d8f
AK		 422#ifdef CONFIG_X86_64
423#define ON64(x) x
424#else
425#define ON64(x)
426#endif
427
6b7ad61f
AK		 428#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
429 do { \
430 __asm__ __volatile__ ( \
431 _PRE_EFLAGS("0", "4", "2") \
432 _op _suffix " %"_x"3,%1; " \
433 _POST_EFLAGS("0", "4", "2") \
434 : "=m" (_eflags), "=m" ((_dst).val), \
435 "=&r" (_tmp) \
436 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 437 } while (0)
6b7ad61f
AK		 438
439
6aa8b732
AK		 440/* Raw emulation: instruction has two explicit operands. */
441#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 442 do { \
443 unsigned long _tmp; \
444 \
445 switch ((_dst).bytes) { \
446 case 2: \
447 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
448 break; \
449 case 4: \
450 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
451 break; \
452 case 8: \
453 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
454 break; \
455 } \
6aa8b732
AK		 456 } while (0)
457
458#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
459 do { \
6b7ad61f 460 unsigned long _tmp; \
d77c26fc 461 switch ((_dst).bytes) { \
6aa8b732 462 case 1: \
6b7ad61f 463 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 464 break; \
465 default: \
466 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
467 _wx, _wy, _lx, _ly, _qx, _qy); \
468 break; \
469 } \
470 } while (0)
471
472/* Source operand is byte-sized and may be restricted to just %cl. */
473#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
474 __emulate_2op(_op, _src, _dst, _eflags, \
475 "b", "c", "b", "c", "b", "c", "b", "c")
476
477/* Source operand is byte, word, long or quad sized. */
478#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
479 __emulate_2op(_op, _src, _dst, _eflags, \
480 "b", "q", "w", "r", _LO32, "r", "", "r")
481
482/* Source operand is word, long or quad sized. */
483#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
484 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
485 "w", "r", _LO32, "r", "", "r")
486
d175226a
GT		 487/* Instruction has three operands and one operand is stored in ECX register */
488#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
489 do { \
490 unsigned long _tmp; \
491 _type _clv = (_cl).val; \
492 _type _srcv = (_src).val; \
493 _type _dstv = (_dst).val; \
494 \
495 __asm__ __volatile__ ( \
496 _PRE_EFLAGS("0", "5", "2") \
497 _op _suffix " %4,%1 \n" \
498 _POST_EFLAGS("0", "5", "2") \
499 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
500 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
501 ); \
502 \
503 (_cl).val = (unsigned long) _clv; \
504 (_src).val = (unsigned long) _srcv; \
505 (_dst).val = (unsigned long) _dstv; \
506 } while (0)
507
508#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
509 do { \
510 switch ((_dst).bytes) { \
511 case 2: \
512 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
513 "w", unsigned short); \
514 break; \
515 case 4: \
516 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
517 "l", unsigned int); \
518 break; \
519 case 8: \
520 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
521 "q", unsigned long)); \
522 break; \
523 } \
524 } while (0)
525
dda96d8f 526#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 527 do { \
528 unsigned long _tmp; \
529 \
dda96d8f
AK		 530 __asm__ __volatile__ ( \
531 _PRE_EFLAGS("0", "3", "2") \
532 _op _suffix " %1; " \
533 _POST_EFLAGS("0", "3", "2") \
534 : "=m" (_eflags), "+m" ((_dst).val), \
535 "=&r" (_tmp) \
536 : "i" (EFLAGS_MASK)); \
537 } while (0)
538
539/* Instruction has only one explicit operand (no source operand). */
540#define emulate_1op(_op, _dst, _eflags) \
541 do { \
d77c26fc 542 switch ((_dst).bytes) { \
dda96d8f
AK		 543 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
544 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
545 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
546 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 547 } \
548 } while (0)
549
6aa8b732
AK		 550/* Fetch next part of the instruction being emulated. */
551#define insn_fetch(_type, _size, _eip) \
552({ unsigned long _x; \
62266869 553 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 554 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 555 goto done; \
556 (_eip) += (_size); \
557 (_type)_x; \
558})
559
414e6277
GN		 560#define insn_fetch_arr(_arr, _size, _eip) \
561({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
562 if (rc != X86EMUL_CONTINUE) \
563 goto done; \
564 (_eip) += (_size); \
565})
566
ddcb2885
HH		 567static inline unsigned long ad_mask(struct decode_cache *c)
568{
569 return (1UL << (c->ad_bytes << 3)) - 1;
570}
571
6aa8b732 572/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 573static inline unsigned long
574address_mask(struct decode_cache *c, unsigned long reg)
575{
576 if (c->ad_bytes == sizeof(unsigned long))
577 return reg;
578 else
579 return reg & ad_mask(c);
580}
581
582static inline unsigned long
583register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
584{
585 return base + address_mask(c, reg);
586}
587
7a957275
HH		 588static inline void
589register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
590{
591 if (c->ad_bytes == sizeof(unsigned long))
592 *reg += inc;
593 else
594 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
595}
6aa8b732 596
7a957275
HH		 597static inline void jmp_rel(struct decode_cache *c, int rel)
598{
599 register_address_increment(c, &c->eip, rel);
600}
098c937b 601
7a5b56df
AK		 602static void set_seg_override(struct decode_cache *c, int seg)
603{
604 c->has_seg_override = true;
605 c->seg_override = seg;
606}
607
79168fd1
GN		 608static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
609 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 610{
611 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
612 return 0;
613
79168fd1 614 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 615}
616
617static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 618 struct x86_emulate_ops *ops,
7a5b56df
AK		 619 struct decode_cache *c)
620{
621 if (!c->has_seg_override)
622 return 0;
623
79168fd1 624 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 625}
626
79168fd1
GN		 627static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
628 struct x86_emulate_ops *ops)
7a5b56df 629{
79168fd1 630 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 631}
632
79168fd1
GN		 633static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
634 struct x86_emulate_ops *ops)
7a5b56df 635{
79168fd1 636 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 637}
638
54b8486f
GN		 639static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
640 u32 error, bool valid)
641{
642 ctxt->exception = vec;
643 ctxt->error_code = error;
644 ctxt->error_code_valid = valid;
645 ctxt->restart = false;
646}
647
648static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
649{
650 emulate_exception(ctxt, GP_VECTOR, err, true);
651}
652
653static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
654 int err)
655{
656 ctxt->cr2 = addr;
657 emulate_exception(ctxt, PF_VECTOR, err, true);
658}
659
660static void emulate_ud(struct x86_emulate_ctxt *ctxt)
661{
662 emulate_exception(ctxt, UD_VECTOR, 0, false);
663}
664
665static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
666{
667 emulate_exception(ctxt, TS_VECTOR, err, true);
668}
669
62266869
AK		 670static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
671 struct x86_emulate_ops *ops,
2fb53ad8 672 unsigned long eip, u8 *dest)
62266869
AK		 673{
674 struct fetch_cache *fc = &ctxt->decode.fetch;
675 int rc;
2fb53ad8 676 int size, cur_size;
62266869 677
2fb53ad8
AK		 678 if (eip == fc->end) {
679 cur_size = fc->end - fc->start;
680 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
681 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
682 size, ctxt->vcpu, NULL);
3e2815e9 683 if (rc != X86EMUL_CONTINUE)
62266869 684 return rc;
2fb53ad8 685 fc->end += size;
62266869 686 }
2fb53ad8 687 *dest = fc->data[eip - fc->start];
3e2815e9 688 return X86EMUL_CONTINUE;
62266869
AK		 689}
690
691static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
692 struct x86_emulate_ops *ops,
693 unsigned long eip, void *dest, unsigned size)
694{
3e2815e9 695 int rc;
62266869 696
eb3c79e6 697 /* x86 instructions are limited to 15 bytes. */
063db061 698 if (eip + size - ctxt->eip > 15)
eb3c79e6 699 return X86EMUL_UNHANDLEABLE;
62266869
AK		 700 while (size--) {
701 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 702 if (rc != X86EMUL_CONTINUE)
62266869
AK		 703 return rc;
704 }
3e2815e9 705 return X86EMUL_CONTINUE;
62266869
AK		 706}
707
1e3c5cb0
RR		 708/*
709 * Given the 'reg' portion of a ModRM byte, and a register block, return a
710 * pointer into the block that addresses the relevant register.
711 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
712 */
713static void *decode_register(u8 modrm_reg, unsigned long *regs,
714 int highbyte_regs)
6aa8b732
AK		 715{
716 void *p;
717
718 p = &regs[modrm_reg];
719 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
720 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
721 return p;
722}
723
724static int read_descriptor(struct x86_emulate_ctxt *ctxt,
725 struct x86_emulate_ops *ops,
726 void *ptr,
727 u16 *size, unsigned long *address, int op_bytes)
728{
729 int rc;
730
731 if (op_bytes == 2)
732 op_bytes = 3;
733 *address = 0;
cebff02b 734 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 735 ctxt->vcpu, NULL);
1b30eaa8 736 if (rc != X86EMUL_CONTINUE)
6aa8b732 737 return rc;
cebff02b 738 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 739 ctxt->vcpu, NULL);
6aa8b732
AK		 740 return rc;
741}
742
bbe9abbd
NK		 743static int test_cc(unsigned int condition, unsigned int flags)
744{
745 int rc = 0;
746
747 switch ((condition & 15) >> 1) {
748 case 0: /* o */
749 rc |= (flags & EFLG_OF);
750 break;
751 case 1: /* b/c/nae */
752 rc |= (flags & EFLG_CF);
753 break;
754 case 2: /* z/e */
755 rc |= (flags & EFLG_ZF);
756 break;
757 case 3: /* be/na */
758 rc |= (flags & (EFLG_CF|EFLG_ZF));
759 break;
760 case 4: /* s */
761 rc |= (flags & EFLG_SF);
762 break;
763 case 5: /* p/pe */
764 rc |= (flags & EFLG_PF);
765 break;
766 case 7: /* le/ng */
767 rc |= (flags & EFLG_ZF);
768 /* fall through */
769 case 6: /* l/nge */
770 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
771 break;
772 }
773
774 /* Odd condition identifiers (lsb == 1) have inverted sense. */
775 return (!!rc ^ (condition & 1));
776}
777
3c118e24
AK		 778static void decode_register_operand(struct operand *op,
779 struct decode_cache *c,
3c118e24
AK		 780 int inhibit_bytereg)
781{
33615aa9 782 unsigned reg = c->modrm_reg;
9f1ef3f8 783 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 784
785 if (!(c->d & ModRM))
786 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 787 op->type = OP_REG;
788 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 789 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 790 op->val = *(u8 *)op->ptr;
791 op->bytes = 1;
792 } else {
33615aa9 793 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 794 op->bytes = c->op_bytes;
795 switch (op->bytes) {
796 case 2:
797 op->val = *(u16 *)op->ptr;
798 break;
799 case 4:
800 op->val = *(u32 *)op->ptr;
801 break;
802 case 8:
803 op->val = *(u64 *) op->ptr;
804 break;
805 }
806 }
807 op->orig_val = op->val;
808}
809
1c73ef66
AK		 810static int decode_modrm(struct x86_emulate_ctxt *ctxt,
811 struct x86_emulate_ops *ops)
812{
813 struct decode_cache *c = &ctxt->decode;
814 u8 sib;
f5b4edcd 815 int index_reg = 0, base_reg = 0, scale;
3e2815e9 816 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 817
818 if (c->rex_prefix) {
819 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
820 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
821 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
822 }
823
824 c->modrm = insn_fetch(u8, 1, c->eip);
825 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
826 c->modrm_reg |= (c->modrm & 0x38) >> 3;
827 c->modrm_rm |= (c->modrm & 0x07);
828 c->modrm_ea = 0;
829 c->use_modrm_ea = 1;
830
831 if (c->modrm_mod == 3) {
107d6d2e
AK		 832 c->modrm_ptr = decode_register(c->modrm_rm,
833 c->regs, c->d & ByteOp);
834 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 835 return rc;
836 }
837
838 if (c->ad_bytes == 2) {
839 unsigned bx = c->regs[VCPU_REGS_RBX];
840 unsigned bp = c->regs[VCPU_REGS_RBP];
841 unsigned si = c->regs[VCPU_REGS_RSI];
842 unsigned di = c->regs[VCPU_REGS_RDI];
843
844 /* 16-bit ModR/M decode. */
845 switch (c->modrm_mod) {
846 case 0:
847 if (c->modrm_rm == 6)
848 c->modrm_ea += insn_fetch(u16, 2, c->eip);
849 break;
850 case 1:
851 c->modrm_ea += insn_fetch(s8, 1, c->eip);
852 break;
853 case 2:
854 c->modrm_ea += insn_fetch(u16, 2, c->eip);
855 break;
856 }
857 switch (c->modrm_rm) {
858 case 0:
859 c->modrm_ea += bx + si;
860 break;
861 case 1:
862 c->modrm_ea += bx + di;
863 break;
864 case 2:
865 c->modrm_ea += bp + si;
866 break;
867 case 3:
868 c->modrm_ea += bp + di;
869 break;
870 case 4:
871 c->modrm_ea += si;
872 break;
873 case 5:
874 c->modrm_ea += di;
875 break;
876 case 6:
877 if (c->modrm_mod != 0)
878 c->modrm_ea += bp;
879 break;
880 case 7:
881 c->modrm_ea += bx;
882 break;
883 }
884 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
885 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 886 if (!c->has_seg_override)
887 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 888 c->modrm_ea = (u16)c->modrm_ea;
889 } else {
890 /* 32/64-bit ModR/M decode. */
84411d85 891 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 892 sib = insn_fetch(u8, 1, c->eip);
893 index_reg |= (sib >> 3) & 7;
894 base_reg |= sib & 7;
895 scale = sib >> 6;
896
dc71d0f1
AK		 897 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
898 c->modrm_ea += insn_fetch(s32, 4, c->eip);
899 else
1c73ef66 900 c->modrm_ea += c->regs[base_reg];
dc71d0f1 901 if (index_reg != 4)
1c73ef66 902 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 903 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
904 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 905 c->rip_relative = 1;
84411d85 906 } else
1c73ef66 907 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 908 switch (c->modrm_mod) {
909 case 0:
910 if (c->modrm_rm == 5)
911 c->modrm_ea += insn_fetch(s32, 4, c->eip);
912 break;
913 case 1:
914 c->modrm_ea += insn_fetch(s8, 1, c->eip);
915 break;
916 case 2:
917 c->modrm_ea += insn_fetch(s32, 4, c->eip);
918 break;
919 }
920 }
1c73ef66
AK		 921done:
922 return rc;
923}
924
925static int decode_abs(struct x86_emulate_ctxt *ctxt,
926 struct x86_emulate_ops *ops)
927{
928 struct decode_cache *c = &ctxt->decode;
3e2815e9 929 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 930
931 switch (c->ad_bytes) {
932 case 2:
933 c->modrm_ea = insn_fetch(u16, 2, c->eip);
934 break;
935 case 4:
936 c->modrm_ea = insn_fetch(u32, 4, c->eip);
937 break;
938 case 8:
939 c->modrm_ea = insn_fetch(u64, 8, c->eip);
940 break;
941 }
942done:
943 return rc;
944}
945
6aa8b732 946int
8b4caf66 947x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 948{
e4e03ded 949 struct decode_cache *c = &ctxt->decode;
3e2815e9 950 int rc = X86EMUL_CONTINUE;
6aa8b732 951 int mode = ctxt->mode;
120df890
AK		 952 int def_op_bytes, def_ad_bytes, group, dual, goffset;
953 struct opcode opcode, *g_mod012, *g_mod3;
6aa8b732 954
5cd21917
GN		 955 /* we cannot decode insn before we complete previous rep insn */
956 WARN_ON(ctxt->restart);
957
063db061 958 c->eip = ctxt->eip;
2fb53ad8 959 c->fetch.start = c->fetch.end = c->eip;
79168fd1 960 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 961
962 switch (mode) {
963 case X86EMUL_MODE_REAL:
a0044755 964 case X86EMUL_MODE_VM86:
6aa8b732 965 case X86EMUL_MODE_PROT16:
f21b8bf4 966 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 967 break;
968 case X86EMUL_MODE_PROT32:
f21b8bf4 969 def_op_bytes = def_ad_bytes = 4;
6aa8b732 970 break;
05b3e0c2 971#ifdef CONFIG_X86_64
6aa8b732 972 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 973 def_op_bytes = 4;
974 def_ad_bytes = 8;
6aa8b732
AK		 975 break;
976#endif
977 default:
978 return -1;
979 }
980
f21b8bf4
AK		 981 c->op_bytes = def_op_bytes;
982 c->ad_bytes = def_ad_bytes;
983
6aa8b732 984 /* Legacy prefixes. */
b4c6abfe 985 for (;;) {
e4e03ded 986 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 987 case 0x66: /* operand-size override */
f21b8bf4
AK		 988 /* switch between 2/4 bytes */
989 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 990 break;
991 case 0x67: /* address-size override */
992 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 993 /* switch between 4/8 bytes */
f21b8bf4 994 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 995 else
e4e03ded 996 /* switch between 2/4 bytes */
f21b8bf4 997 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 998 break;
7a5b56df 999 case 0x26: /* ES override */
6aa8b732 1000 case 0x2e: /* CS override */
7a5b56df 1001 case 0x36: /* SS override */
6aa8b732 1002 case 0x3e: /* DS override */
7a5b56df 1003 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1004 break;
1005 case 0x64: /* FS override */
6aa8b732 1006 case 0x65: /* GS override */
7a5b56df 1007 set_seg_override(c, c->b & 7);
6aa8b732 1008 break;
b4c6abfe
LV		 1009 case 0x40 ... 0x4f: /* REX */
1010 if (mode != X86EMUL_MODE_PROT64)
1011 goto done_prefixes;
33615aa9 1012 c->rex_prefix = c->b;
b4c6abfe 1013 continue;
6aa8b732 1014 case 0xf0: /* LOCK */
e4e03ded 1015 c->lock_prefix = 1;
6aa8b732 1016 break;
ae6200ba 1017 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1018 c->rep_prefix = REPNE_PREFIX;
1019 break;
6aa8b732 1020 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1021 c->rep_prefix = REPE_PREFIX;
6aa8b732 1022 break;
6aa8b732
AK		 1023 default:
1024 goto done_prefixes;
1025 }
b4c6abfe
LV		 1026
1027 /* Any legacy prefix after a REX prefix nullifies its effect. */
1028
33615aa9 1029 c->rex_prefix = 0;
6aa8b732
AK		 1030 }
1031
1032done_prefixes:
1033
1034 /* REX prefix. */
1c73ef66 1035 if (c->rex_prefix)
33615aa9 1036 if (c->rex_prefix & 8)
e4e03ded 1037 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1038
1039 /* Opcode byte(s). */
120df890
AK		 1040 opcode = opcode_table[c->b];
1041 if (opcode.flags == 0) {
6aa8b732 1042 /* Two-byte opcode? */
e4e03ded
LV		 1043 if (c->b == 0x0f) {
1044 c->twobyte = 1;
1045 c->b = insn_fetch(u8, 1, c->eip);
120df890 1046 opcode = twobyte_table[c->b];
6aa8b732 1047 }
e09d082c 1048 }
120df890 1049 c->d = opcode.flags;
6aa8b732 1050
e09d082c
AK		 1051 if (c->d & Group) {
1052 group = c->d & GroupMask;
52811d7d 1053 dual = c->d & GroupDual;
e09d082c
AK		 1054 c->modrm = insn_fetch(u8, 1, c->eip);
1055 --c->eip;
1056
120df890
AK		 1057 if (group) {
1058 g_mod012 = g_mod3 = &group_table[group * 8];
1059 if (c->d & GroupDual)
1060 g_mod3 = &group2_table[group * 8];
1061 } else {
1062 if (c->d & GroupDual) {
1063 g_mod012 = opcode.u.gdual->mod012;
1064 g_mod3 = opcode.u.gdual->mod3;
1065 } else
1066 g_mod012 = g_mod3 = opcode.u.group;
1067 }
1068
52811d7d 1069 c->d &= ~(Group | GroupDual | GroupMask);
120df890
AK		 1070
1071 goffset = (c->modrm >> 3) & 7;
1072
1073 if ((c->modrm >> 6) == 3)
1074 opcode = g_mod3[goffset];
e09d082c 1075 else
120df890
AK		 1076 opcode = g_mod012[goffset];
1077 c->d |= opcode.flags;
e09d082c
AK		 1078 }
1079
1080 /* Unrecognised? */
047a4818 1081 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1082 DPRINTF("Cannot emulate %02x\n", c->b);
1083 return -1;
6aa8b732
AK		 1084 }
1085
6e3d5dfb
AK		 1086 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1087 c->op_bytes = 8;
1088
6aa8b732 1089 /* ModRM and SIB bytes. */
1c73ef66
AK		 1090 if (c->d & ModRM)
1091 rc = decode_modrm(ctxt, ops);
1092 else if (c->d & MemAbs)
1093 rc = decode_abs(ctxt, ops);
3e2815e9 1094 if (rc != X86EMUL_CONTINUE)
1c73ef66 1095 goto done;
6aa8b732 1096
7a5b56df
AK		 1097 if (!c->has_seg_override)
1098 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1099
7a5b56df 1100 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1101 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1102
1103 if (c->ad_bytes != 8)
1104 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1105
1106 if (c->rip_relative)
1107 c->modrm_ea += c->eip;
1108
6aa8b732
AK		 1109 /*
1110 * Decode and fetch the source operand: register, memory
1111 * or immediate.
1112 */
e4e03ded 1113 switch (c->d & SrcMask) {
6aa8b732
AK		 1114 case SrcNone:
1115 break;
1116 case SrcReg:
9f1ef3f8 1117 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1118 break;
1119 case SrcMem16:
e4e03ded 1120 c->src.bytes = 2;
6aa8b732
AK		 1121 goto srcmem_common;
1122 case SrcMem32:
e4e03ded 1123 c->src.bytes = 4;
6aa8b732
AK		 1124 goto srcmem_common;
1125 case SrcMem:
e4e03ded
LV		 1126 c->src.bytes = (c->d & ByteOp) ? 1 :
1127 c->op_bytes;
b85b9ee9 1128 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1129 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1130 break;
d77c26fc 1131 srcmem_common:
4e62417b
AJ		 1132 /*
1133 * For instructions with a ModR/M byte, switch to register
1134 * access if Mod = 3.
1135 */
e4e03ded
LV		 1136 if ((c->d & ModRM) && c->modrm_mod == 3) {
1137 c->src.type = OP_REG;
66b85505 1138 c->src.val = c->modrm_val;
107d6d2e 1139 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1140 break;
1141 }
e4e03ded 1142 c->src.type = OP_MEM;
69f55cb1
GN		 1143 c->src.ptr = (unsigned long *)c->modrm_ea;
1144 c->src.val = 0;
6aa8b732
AK		 1145 break;
1146 case SrcImm:
c9eaf20f 1147 case SrcImmU:
e4e03ded
LV		 1148 c->src.type = OP_IMM;
1149 c->src.ptr = (unsigned long *)c->eip;
1150 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1151 if (c->src.bytes == 8)
1152 c->src.bytes = 4;
6aa8b732 1153 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1154 switch (c->src.bytes) {
6aa8b732 1155 case 1:
e4e03ded 1156 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1157 break;
1158 case 2:
e4e03ded 1159 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1160 break;
1161 case 4:
e4e03ded 1162 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1163 break;
1164 }
c9eaf20f
AK		 1165 if ((c->d & SrcMask) == SrcImmU) {
1166 switch (c->src.bytes) {
1167 case 1:
1168 c->src.val &= 0xff;
1169 break;
1170 case 2:
1171 c->src.val &= 0xffff;
1172 break;
1173 case 4:
1174 c->src.val &= 0xffffffff;
1175 break;
1176 }
1177 }
6aa8b732
AK		 1178 break;
1179 case SrcImmByte:
341de7e3 1180 case SrcImmUByte:
e4e03ded
LV		 1181 c->src.type = OP_IMM;
1182 c->src.ptr = (unsigned long *)c->eip;
1183 c->src.bytes = 1;
341de7e3
GN		 1184 if ((c->d & SrcMask) == SrcImmByte)
1185 c->src.val = insn_fetch(s8, 1, c->eip);
1186 else
1187 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1188 break;
5d55f299
WY		 1189 case SrcAcc:
1190 c->src.type = OP_REG;
1191 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1192 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1193 switch (c->src.bytes) {
1194 case 1:
1195 c->src.val = *(u8 *)c->src.ptr;
1196 break;
1197 case 2:
1198 c->src.val = *(u16 *)c->src.ptr;
1199 break;
1200 case 4:
1201 c->src.val = *(u32 *)c->src.ptr;
1202 break;
1203 case 8:
1204 c->src.val = *(u64 *)c->src.ptr;
1205 break;
1206 }
1207 break;
bfcadf83
GT		 1208 case SrcOne:
1209 c->src.bytes = 1;
1210 c->src.val = 1;
1211 break;
a682e354
GN		 1212 case SrcSI:
1213 c->src.type = OP_MEM;
1214 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1215 c->src.ptr = (unsigned long *)
79168fd1 1216 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1217 c->regs[VCPU_REGS_RSI]);
1218 c->src.val = 0;
1219 break;
414e6277
GN		 1220 case SrcImmFAddr:
1221 c->src.type = OP_IMM;
1222 c->src.ptr = (unsigned long *)c->eip;
1223 c->src.bytes = c->op_bytes + 2;
1224 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1225 break;
1226 case SrcMemFAddr:
1227 c->src.type = OP_MEM;
1228 c->src.ptr = (unsigned long *)c->modrm_ea;
1229 c->src.bytes = c->op_bytes + 2;
1230 break;
6aa8b732
AK		 1231 }
1232
0dc8d10f
GT		 1233 /*
1234 * Decode and fetch the second source operand: register, memory
1235 * or immediate.
1236 */
1237 switch (c->d & Src2Mask) {
1238 case Src2None:
1239 break;
1240 case Src2CL:
1241 c->src2.bytes = 1;
1242 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1243 break;
1244 case Src2ImmByte:
1245 c->src2.type = OP_IMM;
1246 c->src2.ptr = (unsigned long *)c->eip;
1247 c->src2.bytes = 1;
1248 c->src2.val = insn_fetch(u8, 1, c->eip);
1249 break;
1250 case Src2One:
1251 c->src2.bytes = 1;
1252 c->src2.val = 1;
1253 break;
1254 }
1255
038e51de 1256 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1257 switch (c->d & DstMask) {
038e51de
AK		 1258 case ImplicitOps:
1259 /* Special instructions do their own operand decoding. */
8b4caf66 1260 return 0;
038e51de 1261 case DstReg:
9f1ef3f8 1262 decode_register_operand(&c->dst, c,
3c118e24 1263 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1264 break;
1265 case DstMem:
6550e1f1 1266 case DstMem64:
e4e03ded 1267 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1268 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1269 c->dst.type = OP_REG;
66b85505 1270 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1271 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1272 break;
1273 }
8b4caf66 1274 c->dst.type = OP_MEM;
69f55cb1 1275 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1276 if ((c->d & DstMask) == DstMem64)
1277 c->dst.bytes = 8;
1278 else
1279 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1280 c->dst.val = 0;
1281 if (c->d & BitOp) {
1282 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1283
1284 c->dst.ptr = (void *)c->dst.ptr +
1285 (c->src.val & mask) / 8;
1286 }
8b4caf66 1287 break;
9c9fddd0
GT		 1288 case DstAcc:
1289 c->dst.type = OP_REG;
d6d367d6 1290 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1291 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1292 switch (c->dst.bytes) {
9c9fddd0
GT		 1293 case 1:
1294 c->dst.val = *(u8 *)c->dst.ptr;
1295 break;
1296 case 2:
1297 c->dst.val = *(u16 *)c->dst.ptr;
1298 break;
1299 case 4:
1300 c->dst.val = *(u32 *)c->dst.ptr;
1301 break;
d6d367d6
GN		 1302 case 8:
1303 c->dst.val = *(u64 *)c->dst.ptr;
1304 break;
9c9fddd0
GT		 1305 }
1306 c->dst.orig_val = c->dst.val;
1307 break;
a682e354
GN		 1308 case DstDI:
1309 c->dst.type = OP_MEM;
1310 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1311 c->dst.ptr = (unsigned long *)
79168fd1 1312 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1313 c->regs[VCPU_REGS_RDI]);
1314 c->dst.val = 0;
1315 break;
8b4caf66
LV		 1316 }
1317
1318done:
1319 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1320}
1321
9de41573
GN		 1322static int read_emulated(struct x86_emulate_ctxt *ctxt,
1323 struct x86_emulate_ops *ops,
1324 unsigned long addr, void *dest, unsigned size)
1325{
1326 int rc;
1327 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1328 u32 err;
9de41573
GN		 1329
1330 while (size) {
1331 int n = min(size, 8u);
1332 size -= n;
1333 if (mc->pos < mc->end)
1334 goto read_cached;
1335
8fe681e9
GN		 1336 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1337 ctxt->vcpu);
1338 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1339 emulate_pf(ctxt, addr, err);
9de41573
GN		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
1342 mc->end += n;
1343
1344 read_cached:
1345 memcpy(dest, mc->data + mc->pos, n);
1346 mc->pos += n;
1347 dest += n;
1348 addr += n;
1349 }
1350 return X86EMUL_CONTINUE;
1351}
1352
7b262e90
GN		 1353static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1354 struct x86_emulate_ops *ops,
1355 unsigned int size, unsigned short port,
1356 void *dest)
1357{
1358 struct read_cache *rc = &ctxt->decode.io_read;
1359
1360 if (rc->pos == rc->end) { /* refill pio read ahead */
1361 struct decode_cache *c = &ctxt->decode;
1362 unsigned int in_page, n;
1363 unsigned int count = c->rep_prefix ?
1364 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1365 in_page = (ctxt->eflags & EFLG_DF) ?
1366 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1367 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1368 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1369 count);
1370 if (n == 0)
1371 n = 1;
1372 rc->pos = rc->end = 0;
1373 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1374 return 0;
1375 rc->end = n * size;
1376 }
1377
1378 memcpy(dest, rc->data + rc->pos, size);
1379 rc->pos += size;
1380 return 1;
1381}
1382
38ba30ba
GN		 1383static u32 desc_limit_scaled(struct desc_struct *desc)
1384{
1385 u32 limit = get_desc_limit(desc);
1386
1387 return desc->g ? (limit << 12) | 0xfff : limit;
1388}
1389
1390static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1391 struct x86_emulate_ops *ops,
1392 u16 selector, struct desc_ptr *dt)
1393{
1394 if (selector & 1 << 2) {
1395 struct desc_struct desc;
1396 memset (dt, 0, sizeof *dt);
1397 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1398 return;
1399
1400 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1401 dt->address = get_desc_base(&desc);
1402 } else
1403 ops->get_gdt(dt, ctxt->vcpu);
1404}
1405
1406/* allowed just for 8 bytes segments */
1407static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1408 struct x86_emulate_ops *ops,
1409 u16 selector, struct desc_struct *desc)
1410{
1411 struct desc_ptr dt;
1412 u16 index = selector >> 3;
1413 int ret;
1414 u32 err;
1415 ulong addr;
1416
1417 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1418
1419 if (dt.size < index * 8 + 7) {
54b8486f 1420 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1421 return X86EMUL_PROPAGATE_FAULT;
1422 }
1423 addr = dt.address + index * 8;
1424 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1425 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1426 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1427
1428 return ret;
1429}
1430
1431/* allowed just for 8 bytes segments */
1432static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1433 struct x86_emulate_ops *ops,
1434 u16 selector, struct desc_struct *desc)
1435{
1436 struct desc_ptr dt;
1437 u16 index = selector >> 3;
1438 u32 err;
1439 ulong addr;
1440 int ret;
1441
1442 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1443
1444 if (dt.size < index * 8 + 7) {
54b8486f 1445 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1446 return X86EMUL_PROPAGATE_FAULT;
1447 }
1448
1449 addr = dt.address + index * 8;
1450 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1451 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1452 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1453
1454 return ret;
1455}
1456
1457static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1458 struct x86_emulate_ops *ops,
1459 u16 selector, int seg)
1460{
1461 struct desc_struct seg_desc;
1462 u8 dpl, rpl, cpl;
1463 unsigned err_vec = GP_VECTOR;
1464 u32 err_code = 0;
1465 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1466 int ret;
1467
1468 memset(&seg_desc, 0, sizeof seg_desc);
1469
1470 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1471 || ctxt->mode == X86EMUL_MODE_REAL) {
1472 /* set real mode segment descriptor */
1473 set_desc_base(&seg_desc, selector << 4);
1474 set_desc_limit(&seg_desc, 0xffff);
1475 seg_desc.type = 3;
1476 seg_desc.p = 1;
1477 seg_desc.s = 1;
1478 goto load;
1479 }
1480
1481 /* NULL selector is not valid for TR, CS and SS */
1482 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1483 && null_selector)
1484 goto exception;
1485
1486 /* TR should be in GDT only */
1487 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1488 goto exception;
1489
1490 if (null_selector) /* for NULL selector skip all following checks */
1491 goto load;
1492
1493 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1494 if (ret != X86EMUL_CONTINUE)
1495 return ret;
1496
1497 err_code = selector & 0xfffc;
1498 err_vec = GP_VECTOR;
1499
1500 /* can't load system descriptor into segment selecor */
1501 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1502 goto exception;
1503
1504 if (!seg_desc.p) {
1505 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1506 goto exception;
1507 }
1508
1509 rpl = selector & 3;
1510 dpl = seg_desc.dpl;
1511 cpl = ops->cpl(ctxt->vcpu);
1512
1513 switch (seg) {
1514 case VCPU_SREG_SS:
1515 /*
1516 * segment is not a writable data segment or segment
1517 * selector's RPL != CPL or segment selector's RPL != CPL
1518 */
1519 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1520 goto exception;
1521 break;
1522 case VCPU_SREG_CS:
1523 if (!(seg_desc.type & 8))
1524 goto exception;
1525
1526 if (seg_desc.type & 4) {
1527 /* conforming */
1528 if (dpl > cpl)
1529 goto exception;
1530 } else {
1531 /* nonconforming */
1532 if (rpl > cpl || dpl != cpl)
1533 goto exception;
1534 }
1535 /* CS(RPL) <- CPL */
1536 selector = (selector & 0xfffc) | cpl;
1537 break;
1538 case VCPU_SREG_TR:
1539 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1540 goto exception;
1541 break;
1542 case VCPU_SREG_LDTR:
1543 if (seg_desc.s || seg_desc.type != 2)
1544 goto exception;
1545 break;
1546 default: /* DS, ES, FS, or GS */
1547 /*
1548 * segment is not a data or readable code segment or
1549 * ((segment is a data or nonconforming code segment)
1550 * and (both RPL and CPL > DPL))
1551 */
1552 if ((seg_desc.type & 0xa) == 0x8 ||
1553 (((seg_desc.type & 0xc) != 0xc) &&
1554 (rpl > dpl && cpl > dpl)))
1555 goto exception;
1556 break;
1557 }
1558
1559 if (seg_desc.s) {
1560 /* mark segment as accessed */
1561 seg_desc.type |= 1;
1562 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1563 if (ret != X86EMUL_CONTINUE)
1564 return ret;
1565 }
1566load:
1567 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1568 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1569 return X86EMUL_CONTINUE;
1570exception:
54b8486f 1571 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1572 return X86EMUL_PROPAGATE_FAULT;
1573}
1574
c37eda13
WY		 1575static inline int writeback(struct x86_emulate_ctxt *ctxt,
1576 struct x86_emulate_ops *ops)
1577{
1578 int rc;
1579 struct decode_cache *c = &ctxt->decode;
1580 u32 err;
1581
1582 switch (c->dst.type) {
1583 case OP_REG:
1584 /* The 4-byte case *is* correct:
1585 * in 64-bit mode we zero-extend.
1586 */
1587 switch (c->dst.bytes) {
1588 case 1:
1589 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1590 break;
1591 case 2:
1592 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1593 break;
1594 case 4:
1595 *c->dst.ptr = (u32)c->dst.val;
1596 break; /* 64b: zero-ext */
1597 case 8:
1598 *c->dst.ptr = c->dst.val;
1599 break;
1600 }
1601 break;
1602 case OP_MEM:
1603 if (c->lock_prefix)
1604 rc = ops->cmpxchg_emulated(
1605 (unsigned long)c->dst.ptr,
1606 &c->dst.orig_val,
1607 &c->dst.val,
1608 c->dst.bytes,
1609 &err,
1610 ctxt->vcpu);
1611 else
1612 rc = ops->write_emulated(
1613 (unsigned long)c->dst.ptr,
1614 &c->dst.val,
1615 c->dst.bytes,
1616 &err,
1617 ctxt->vcpu);
1618 if (rc == X86EMUL_PROPAGATE_FAULT)
1619 emulate_pf(ctxt,
1620 (unsigned long)c->dst.ptr, err);
1621 if (rc != X86EMUL_CONTINUE)
1622 return rc;
1623 break;
1624 case OP_NONE:
1625 /* no writeback */
1626 break;
1627 default:
1628 break;
1629 }
1630 return X86EMUL_CONTINUE;
1631}
1632
79168fd1
GN		 1633static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1634 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1635{
1636 struct decode_cache *c = &ctxt->decode;
1637
1638 c->dst.type = OP_MEM;
1639 c->dst.bytes = c->op_bytes;
1640 c->dst.val = c->src.val;
7a957275 1641 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1642 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1643 c->regs[VCPU_REGS_RSP]);
1644}
1645
faa5a3ae 1646static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1647 struct x86_emulate_ops *ops,
1648 void *dest, int len)
8cdbd2c9
LV		 1649{
1650 struct decode_cache *c = &ctxt->decode;
1651 int rc;
1652
79168fd1 1653 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1654 c->regs[VCPU_REGS_RSP]),
1655 dest, len);
b60d513c 1656 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1657 return rc;
1658
350f69dc 1659 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1660 return rc;
1661}
8cdbd2c9 1662
d4c6a154
GN		 1663static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1664 struct x86_emulate_ops *ops,
1665 void *dest, int len)
1666{
1667 int rc;
1668 unsigned long val, change_mask;
1669 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1670 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1671
1672 rc = emulate_pop(ctxt, ops, &val, len);
1673 if (rc != X86EMUL_CONTINUE)
1674 return rc;
1675
1676 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1677 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1678
1679 switch(ctxt->mode) {
1680 case X86EMUL_MODE_PROT64:
1681 case X86EMUL_MODE_PROT32:
1682 case X86EMUL_MODE_PROT16:
1683 if (cpl == 0)
1684 change_mask |= EFLG_IOPL;
1685 if (cpl <= iopl)
1686 change_mask |= EFLG_IF;
1687 break;
1688 case X86EMUL_MODE_VM86:
1689 if (iopl < 3) {
54b8486f 1690 emulate_gp(ctxt, 0);
d4c6a154
GN		 1691 return X86EMUL_PROPAGATE_FAULT;
1692 }
1693 change_mask |= EFLG_IF;
1694 break;
1695 default: /* real mode */
1696 change_mask |= (EFLG_IOPL | EFLG_IF);
1697 break;
1698 }
1699
1700 *(unsigned long *)dest =
1701 (ctxt->eflags & ~change_mask) | (val & change_mask);
1702
1703 return rc;
1704}
1705
79168fd1
GN		 1706static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1707 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1708{
1709 struct decode_cache *c = &ctxt->decode;
0934ac9d 1710
79168fd1 1711 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1712
79168fd1 1713 emulate_push(ctxt, ops);
0934ac9d
MG		 1714}
1715
1716static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1717 struct x86_emulate_ops *ops, int seg)
1718{
1719 struct decode_cache *c = &ctxt->decode;
1720 unsigned long selector;
1721 int rc;
1722
1723 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1724 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1725 return rc;
1726
2e873022 1727 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1728 return rc;
1729}
1730
c37eda13 1731static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1732 struct x86_emulate_ops *ops)
abcf14b5
MG		 1733{
1734 struct decode_cache *c = &ctxt->decode;
1735 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1736 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1737 int reg = VCPU_REGS_RAX;
1738
1739 while (reg <= VCPU_REGS_RDI) {
1740 (reg == VCPU_REGS_RSP) ?
1741 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1742
79168fd1 1743 emulate_push(ctxt, ops);
c37eda13
WY		 1744
1745 rc = writeback(ctxt, ops);
1746 if (rc != X86EMUL_CONTINUE)
1747 return rc;
1748
abcf14b5
MG		 1749 ++reg;
1750 }
c37eda13
WY		 1751
1752 /* Disable writeback. */
1753 c->dst.type = OP_NONE;
1754
1755 return rc;
abcf14b5
MG		 1756}
1757
1758static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1759 struct x86_emulate_ops *ops)
1760{
1761 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1762 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1763 int reg = VCPU_REGS_RDI;
1764
1765 while (reg >= VCPU_REGS_RAX) {
1766 if (reg == VCPU_REGS_RSP) {
1767 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1768 c->op_bytes);
1769 --reg;
1770 }
1771
1772 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1773 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1774 break;
1775 --reg;
1776 }
1777 return rc;
1778}
1779
62bd430e
MG		 1780static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1781 struct x86_emulate_ops *ops)
1782{
1783 struct decode_cache *c = &ctxt->decode;
1784 int rc = X86EMUL_CONTINUE;
1785 unsigned long temp_eip = 0;
1786 unsigned long temp_eflags = 0;
1787 unsigned long cs = 0;
1788 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1789 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1790 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1791 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1792
1793 /* TODO: Add stack limit check */
1794
1795 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1796
1797 if (rc != X86EMUL_CONTINUE)
1798 return rc;
1799
1800 if (temp_eip & ~0xffff) {
1801 emulate_gp(ctxt, 0);
1802 return X86EMUL_PROPAGATE_FAULT;
1803 }
1804
1805 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1806
1807 if (rc != X86EMUL_CONTINUE)
1808 return rc;
1809
1810 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1811
1812 if (rc != X86EMUL_CONTINUE)
1813 return rc;
1814
1815 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1816
1817 if (rc != X86EMUL_CONTINUE)
1818 return rc;
1819
1820 c->eip = temp_eip;
1821
1822
1823 if (c->op_bytes == 4)
1824 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1825 else if (c->op_bytes == 2) {
1826 ctxt->eflags &= ~0xffff;
1827 ctxt->eflags |= temp_eflags;
1828 }
1829
1830 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1831 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1832
1833 return rc;
1834}
1835
1836static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1837 struct x86_emulate_ops* ops)
1838{
1839 switch(ctxt->mode) {
1840 case X86EMUL_MODE_REAL:
1841 return emulate_iret_real(ctxt, ops);
1842 case X86EMUL_MODE_VM86:
1843 case X86EMUL_MODE_PROT16:
1844 case X86EMUL_MODE_PROT32:
1845 case X86EMUL_MODE_PROT64:
1846 default:
1847 /* iret from protected mode unimplemented yet */
1848 return X86EMUL_UNHANDLEABLE;
1849 }
1850}
1851
faa5a3ae
AK		 1852static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1853 struct x86_emulate_ops *ops)
1854{
1855 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1856
1b30eaa8 1857 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1858}
1859
05f086f8 1860static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1861{
05f086f8 1862 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1863 switch (c->modrm_reg) {
1864 case 0: /* rol */
05f086f8 1865 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1866 break;
1867 case 1: /* ror */
05f086f8 1868 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1869 break;
1870 case 2: /* rcl */
05f086f8 1871 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1872 break;
1873 case 3: /* rcr */
05f086f8 1874 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1875 break;
1876 case 4: /* sal/shl */
1877 case 6: /* sal/shl */
05f086f8 1878 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1879 break;
1880 case 5: /* shr */
05f086f8 1881 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1882 break;
1883 case 7: /* sar */
05f086f8 1884 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1885 break;
1886 }
1887}
1888
1889static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1890 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1891{
1892 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1893
1894 switch (c->modrm_reg) {
1895 case 0 ... 1: /* test */
05f086f8 1896 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1897 break;
1898 case 2: /* not */
1899 c->dst.val = ~c->dst.val;
1900 break;
1901 case 3: /* neg */
05f086f8 1902 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1903 break;
1904 default:
aca06a83 1905 return 0;
8cdbd2c9 1906 }
aca06a83 1907 return 1;
8cdbd2c9
LV		 1908}
1909
1910static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1911 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1912{
1913 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1914
1915 switch (c->modrm_reg) {
1916 case 0: /* inc */
05f086f8 1917 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1918 break;
1919 case 1: /* dec */
05f086f8 1920 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1921 break;
d19292e4
MG		 1922 case 2: /* call near abs */ {
1923 long int old_eip;
1924 old_eip = c->eip;
1925 c->eip = c->src.val;
1926 c->src.val = old_eip;
79168fd1 1927 emulate_push(ctxt, ops);
d19292e4
MG		 1928 break;
1929 }
8cdbd2c9 1930 case 4: /* jmp abs */
fd60754e 1931 c->eip = c->src.val;
8cdbd2c9
LV		 1932 break;
1933 case 6: /* push */
79168fd1 1934 emulate_push(ctxt, ops);
8cdbd2c9 1935 break;
8cdbd2c9 1936 }
1b30eaa8 1937 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1938}
1939
1940static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1941 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1942{
1943 struct decode_cache *c = &ctxt->decode;
16518d5a 1944 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1945
1946 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1947 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1948 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1949 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1950 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1951 } else {
16518d5a
AK		 1952 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1953 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1954
05f086f8 1955 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1956 }
1b30eaa8 1957 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1958}
1959
a77ab5ea
AK		 1960static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1961 struct x86_emulate_ops *ops)
1962{
1963 struct decode_cache *c = &ctxt->decode;
1964 int rc;
1965 unsigned long cs;
1966
1967 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1968 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1969 return rc;
1970 if (c->op_bytes == 4)
1971 c->eip = (u32)c->eip;
1972 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1973 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1974 return rc;
2e873022 1975 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1976 return rc;
1977}
1978
e66bb2cc
AP		 1979static inline void
1980setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1981 struct x86_emulate_ops *ops, struct desc_struct *cs,
1982 struct desc_struct *ss)
e66bb2cc 1983{
79168fd1
GN		 1984 memset(cs, 0, sizeof(struct desc_struct));
1985 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1986 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1987
1988 cs->l = 0; /* will be adjusted later */
79168fd1 1989 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1990 cs->g = 1; /* 4kb granularity */
79168fd1 1991 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1992 cs->type = 0x0b; /* Read, Execute, Accessed */
1993 cs->s = 1;
1994 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1995 cs->p = 1;
1996 cs->d = 1;
e66bb2cc 1997
79168fd1
GN		 1998 set_desc_base(ss, 0); /* flat segment */
1999 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2000 ss->g = 1; /* 4kb granularity */
2001 ss->s = 1;
2002 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2003 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2004 ss->dpl = 0;
79168fd1 2005 ss->p = 1;
e66bb2cc
AP		 2006}
2007
2008static int
3fb1b5db 2009emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 2010{
2011 struct decode_cache *c = &ctxt->decode;
79168fd1 2012 struct desc_struct cs, ss;
e66bb2cc 2013 u64 msr_data;
79168fd1 2014 u16 cs_sel, ss_sel;
e66bb2cc
AP		 2015
2016 /* syscall is not available in real mode */
2e901c4c
GN		 2017 if (ctxt->mode == X86EMUL_MODE_REAL ||
2018 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2019 emulate_ud(ctxt);
2e901c4c
GN		 2020 return X86EMUL_PROPAGATE_FAULT;
2021 }
e66bb2cc 2022
79168fd1 2023 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 2024
3fb1b5db 2025 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 2026 msr_data >>= 32;
79168fd1
GN		 2027 cs_sel = (u16)(msr_data & 0xfffc);
2028 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 2029
2030 if (is_long_mode(ctxt->vcpu)) {
79168fd1 2031 cs.d = 0;
e66bb2cc
AP		 2032 cs.l = 1;
2033 }
79168fd1
GN		 2034 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2035 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2036 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2037 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2038
2039 c->regs[VCPU_REGS_RCX] = c->eip;
2040 if (is_long_mode(ctxt->vcpu)) {
2041#ifdef CONFIG_X86_64
2042 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2043
3fb1b5db
GN		 2044 ops->get_msr(ctxt->vcpu,
2045 ctxt->mode == X86EMUL_MODE_PROT64 ?
2046 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2047 c->eip = msr_data;
2048
3fb1b5db 2049 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2050 ctxt->eflags &= ~(msr_data | EFLG_RF);
2051#endif
2052 } else {
2053 /* legacy mode */
3fb1b5db 2054 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2055 c->eip = (u32)msr_data;
2056
2057 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2058 }
2059
e54cfa97 2060 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2061}
2062
8c604352 2063static int
3fb1b5db 2064emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2065{
2066 struct decode_cache *c = &ctxt->decode;
79168fd1 2067 struct desc_struct cs, ss;
8c604352 2068 u64 msr_data;
79168fd1 2069 u16 cs_sel, ss_sel;
8c604352 2070
a0044755
GN		 2071 /* inject #GP if in real mode */
2072 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2073 emulate_gp(ctxt, 0);
2e901c4c 2074 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2075 }
2076
2077 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2078 * Therefore, we inject an #UD.
2079 */
2e901c4c 2080 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2081 emulate_ud(ctxt);
2e901c4c
GN		 2082 return X86EMUL_PROPAGATE_FAULT;
2083 }
8c604352 2084
79168fd1 2085 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2086
3fb1b5db 2087 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2088 switch (ctxt->mode) {
2089 case X86EMUL_MODE_PROT32:
2090 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2091 emulate_gp(ctxt, 0);
e54cfa97 2092 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2093 }
2094 break;
2095 case X86EMUL_MODE_PROT64:
2096 if (msr_data == 0x0) {
54b8486f 2097 emulate_gp(ctxt, 0);
e54cfa97 2098 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2099 }
2100 break;
2101 }
2102
2103 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2104 cs_sel = (u16)msr_data;
2105 cs_sel &= ~SELECTOR_RPL_MASK;
2106 ss_sel = cs_sel + 8;
2107 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2108 if (ctxt->mode == X86EMUL_MODE_PROT64
2109 || is_long_mode(ctxt->vcpu)) {
79168fd1 2110 cs.d = 0;
8c604352
AP		 2111 cs.l = 1;
2112 }
2113
79168fd1
GN		 2114 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2115 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2116 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2117 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2118
3fb1b5db 2119 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2120 c->eip = msr_data;
2121
3fb1b5db 2122 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2123 c->regs[VCPU_REGS_RSP] = msr_data;
2124
e54cfa97 2125 return X86EMUL_CONTINUE;
8c604352
AP		 2126}
2127
4668f050 2128static int
3fb1b5db 2129emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2130{
2131 struct decode_cache *c = &ctxt->decode;
79168fd1 2132 struct desc_struct cs, ss;
4668f050
AP		 2133 u64 msr_data;
2134 int usermode;
79168fd1 2135 u16 cs_sel, ss_sel;
4668f050 2136
a0044755
GN		 2137 /* inject #GP if in real mode or Virtual 8086 mode */
2138 if (ctxt->mode == X86EMUL_MODE_REAL ||
2139 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2140 emulate_gp(ctxt, 0);
2e901c4c 2141 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2142 }
2143
79168fd1 2144 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2145
2146 if ((c->rex_prefix & 0x8) != 0x0)
2147 usermode = X86EMUL_MODE_PROT64;
2148 else
2149 usermode = X86EMUL_MODE_PROT32;
2150
2151 cs.dpl = 3;
2152 ss.dpl = 3;
3fb1b5db 2153 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2154 switch (usermode) {
2155 case X86EMUL_MODE_PROT32:
79168fd1 2156 cs_sel = (u16)(msr_data + 16);
4668f050 2157 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2158 emulate_gp(ctxt, 0);
e54cfa97 2159 return X86EMUL_PROPAGATE_FAULT;
4668f050 2160 }
79168fd1 2161 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2162 break;
2163 case X86EMUL_MODE_PROT64:
79168fd1 2164 cs_sel = (u16)(msr_data + 32);
4668f050 2165 if (msr_data == 0x0) {
54b8486f 2166 emulate_gp(ctxt, 0);
e54cfa97 2167 return X86EMUL_PROPAGATE_FAULT;
4668f050 2168 }
79168fd1
GN		 2169 ss_sel = cs_sel + 8;
2170 cs.d = 0;
4668f050
AP		 2171 cs.l = 1;
2172 break;
2173 }
79168fd1
GN		 2174 cs_sel |= SELECTOR_RPL_MASK;
2175 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2176
79168fd1
GN		 2177 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2178 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2179 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2180 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2181
bdb475a3
GN		 2182 c->eip = c->regs[VCPU_REGS_RDX];
2183 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2184
e54cfa97 2185 return X86EMUL_CONTINUE;
4668f050
AP		 2186}
2187
9c537244
GN		 2188static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2189 struct x86_emulate_ops *ops)
f850e2e6
GN		 2190{
2191 int iopl;
2192 if (ctxt->mode == X86EMUL_MODE_REAL)
2193 return false;
2194 if (ctxt->mode == X86EMUL_MODE_VM86)
2195 return true;
2196 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2197 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2198}
2199
2200static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2201 struct x86_emulate_ops *ops,
2202 u16 port, u16 len)
2203{
79168fd1 2204 struct desc_struct tr_seg;
f850e2e6
GN		 2205 int r;
2206 u16 io_bitmap_ptr;
2207 u8 perm, bit_idx = port & 0x7;
2208 unsigned mask = (1 << len) - 1;
2209
79168fd1
GN		 2210 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2211 if (!tr_seg.p)
f850e2e6 2212 return false;
79168fd1 2213 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2214 return false;
79168fd1
GN		 2215 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2216 ctxt->vcpu, NULL);
f850e2e6
GN		 2217 if (r != X86EMUL_CONTINUE)
2218 return false;
79168fd1 2219 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2220 return false;
79168fd1
GN		 2221 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2222 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2223 if (r != X86EMUL_CONTINUE)
2224 return false;
2225 if ((perm >> bit_idx) & mask)
2226 return false;
2227 return true;
2228}
2229
2230static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2231 struct x86_emulate_ops *ops,
2232 u16 port, u16 len)
2233{
9c537244 2234 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2235 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2236 return false;
2237 return true;
2238}
2239
38ba30ba
GN		 2240static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2241 struct x86_emulate_ops *ops,
2242 struct tss_segment_16 *tss)
2243{
2244 struct decode_cache *c = &ctxt->decode;
2245
2246 tss->ip = c->eip;
2247 tss->flag = ctxt->eflags;
2248 tss->ax = c->regs[VCPU_REGS_RAX];
2249 tss->cx = c->regs[VCPU_REGS_RCX];
2250 tss->dx = c->regs[VCPU_REGS_RDX];
2251 tss->bx = c->regs[VCPU_REGS_RBX];
2252 tss->sp = c->regs[VCPU_REGS_RSP];
2253 tss->bp = c->regs[VCPU_REGS_RBP];
2254 tss->si = c->regs[VCPU_REGS_RSI];
2255 tss->di = c->regs[VCPU_REGS_RDI];
2256
2257 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2258 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2259 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2260 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2261 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2262}
2263
2264static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2265 struct x86_emulate_ops *ops,
2266 struct tss_segment_16 *tss)
2267{
2268 struct decode_cache *c = &ctxt->decode;
2269 int ret;
2270
2271 c->eip = tss->ip;
2272 ctxt->eflags = tss->flag | 2;
2273 c->regs[VCPU_REGS_RAX] = tss->ax;
2274 c->regs[VCPU_REGS_RCX] = tss->cx;
2275 c->regs[VCPU_REGS_RDX] = tss->dx;
2276 c->regs[VCPU_REGS_RBX] = tss->bx;
2277 c->regs[VCPU_REGS_RSP] = tss->sp;
2278 c->regs[VCPU_REGS_RBP] = tss->bp;
2279 c->regs[VCPU_REGS_RSI] = tss->si;
2280 c->regs[VCPU_REGS_RDI] = tss->di;
2281
2282 /*
2283 * SDM says that segment selectors are loaded before segment
2284 * descriptors
2285 */
2286 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2287 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2288 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2289 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2290 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2291
2292 /*
2293 * Now load segment descriptors. If fault happenes at this stage
2294 * it is handled in a context of new task
2295 */
2296 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2297 if (ret != X86EMUL_CONTINUE)
2298 return ret;
2299 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2300 if (ret != X86EMUL_CONTINUE)
2301 return ret;
2302 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2303 if (ret != X86EMUL_CONTINUE)
2304 return ret;
2305 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2306 if (ret != X86EMUL_CONTINUE)
2307 return ret;
2308 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2309 if (ret != X86EMUL_CONTINUE)
2310 return ret;
2311
2312 return X86EMUL_CONTINUE;
2313}
2314
2315static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2316 struct x86_emulate_ops *ops,
2317 u16 tss_selector, u16 old_tss_sel,
2318 ulong old_tss_base, struct desc_struct *new_desc)
2319{
2320 struct tss_segment_16 tss_seg;
2321 int ret;
2322 u32 err, new_tss_base = get_desc_base(new_desc);
2323
2324 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2325 &err);
2326 if (ret == X86EMUL_PROPAGATE_FAULT) {
2327 /* FIXME: need to provide precise fault address */
54b8486f 2328 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2329 return ret;
2330 }
2331
2332 save_state_to_tss16(ctxt, ops, &tss_seg);
2333
2334 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2335 &err);
2336 if (ret == X86EMUL_PROPAGATE_FAULT) {
2337 /* FIXME: need to provide precise fault address */
54b8486f 2338 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2339 return ret;
2340 }
2341
2342 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2343 &err);
2344 if (ret == X86EMUL_PROPAGATE_FAULT) {
2345 /* FIXME: need to provide precise fault address */
54b8486f 2346 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2347 return ret;
2348 }
2349
2350 if (old_tss_sel != 0xffff) {
2351 tss_seg.prev_task_link = old_tss_sel;
2352
2353 ret = ops->write_std(new_tss_base,
2354 &tss_seg.prev_task_link,
2355 sizeof tss_seg.prev_task_link,
2356 ctxt->vcpu, &err);
2357 if (ret == X86EMUL_PROPAGATE_FAULT) {
2358 /* FIXME: need to provide precise fault address */
54b8486f 2359 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2360 return ret;
2361 }
2362 }
2363
2364 return load_state_from_tss16(ctxt, ops, &tss_seg);
2365}
2366
2367static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2368 struct x86_emulate_ops *ops,
2369 struct tss_segment_32 *tss)
2370{
2371 struct decode_cache *c = &ctxt->decode;
2372
2373 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2374 tss->eip = c->eip;
2375 tss->eflags = ctxt->eflags;
2376 tss->eax = c->regs[VCPU_REGS_RAX];
2377 tss->ecx = c->regs[VCPU_REGS_RCX];
2378 tss->edx = c->regs[VCPU_REGS_RDX];
2379 tss->ebx = c->regs[VCPU_REGS_RBX];
2380 tss->esp = c->regs[VCPU_REGS_RSP];
2381 tss->ebp = c->regs[VCPU_REGS_RBP];
2382 tss->esi = c->regs[VCPU_REGS_RSI];
2383 tss->edi = c->regs[VCPU_REGS_RDI];
2384
2385 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2386 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2387 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2388 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2389 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2390 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2391 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2392}
2393
2394static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2395 struct x86_emulate_ops *ops,
2396 struct tss_segment_32 *tss)
2397{
2398 struct decode_cache *c = &ctxt->decode;
2399 int ret;
2400
0f12244f 2401 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2402 emulate_gp(ctxt, 0);
0f12244f
GN		 2403 return X86EMUL_PROPAGATE_FAULT;
2404 }
38ba30ba
GN		 2405 c->eip = tss->eip;
2406 ctxt->eflags = tss->eflags | 2;
2407 c->regs[VCPU_REGS_RAX] = tss->eax;
2408 c->regs[VCPU_REGS_RCX] = tss->ecx;
2409 c->regs[VCPU_REGS_RDX] = tss->edx;
2410 c->regs[VCPU_REGS_RBX] = tss->ebx;
2411 c->regs[VCPU_REGS_RSP] = tss->esp;
2412 c->regs[VCPU_REGS_RBP] = tss->ebp;
2413 c->regs[VCPU_REGS_RSI] = tss->esi;
2414 c->regs[VCPU_REGS_RDI] = tss->edi;
2415
2416 /*
2417 * SDM says that segment selectors are loaded before segment
2418 * descriptors
2419 */
2420 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2421 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2422 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2423 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2424 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2425 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2426 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2427
2428 /*
2429 * Now load segment descriptors. If fault happenes at this stage
2430 * it is handled in a context of new task
2431 */
2432 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2433 if (ret != X86EMUL_CONTINUE)
2434 return ret;
2435 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2436 if (ret != X86EMUL_CONTINUE)
2437 return ret;
2438 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2439 if (ret != X86EMUL_CONTINUE)
2440 return ret;
2441 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2442 if (ret != X86EMUL_CONTINUE)
2443 return ret;
2444 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2445 if (ret != X86EMUL_CONTINUE)
2446 return ret;
2447 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2448 if (ret != X86EMUL_CONTINUE)
2449 return ret;
2450 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2451 if (ret != X86EMUL_CONTINUE)
2452 return ret;
2453
2454 return X86EMUL_CONTINUE;
2455}
2456
2457static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2458 struct x86_emulate_ops *ops,
2459 u16 tss_selector, u16 old_tss_sel,
2460 ulong old_tss_base, struct desc_struct *new_desc)
2461{
2462 struct tss_segment_32 tss_seg;
2463 int ret;
2464 u32 err, new_tss_base = get_desc_base(new_desc);
2465
2466 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2467 &err);
2468 if (ret == X86EMUL_PROPAGATE_FAULT) {
2469 /* FIXME: need to provide precise fault address */
54b8486f 2470 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2471 return ret;
2472 }
2473
2474 save_state_to_tss32(ctxt, ops, &tss_seg);
2475
2476 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2477 &err);
2478 if (ret == X86EMUL_PROPAGATE_FAULT) {
2479 /* FIXME: need to provide precise fault address */
54b8486f 2480 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2481 return ret;
2482 }
2483
2484 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2485 &err);
2486 if (ret == X86EMUL_PROPAGATE_FAULT) {
2487 /* FIXME: need to provide precise fault address */
54b8486f 2488 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2489 return ret;
2490 }
2491
2492 if (old_tss_sel != 0xffff) {
2493 tss_seg.prev_task_link = old_tss_sel;
2494
2495 ret = ops->write_std(new_tss_base,
2496 &tss_seg.prev_task_link,
2497 sizeof tss_seg.prev_task_link,
2498 ctxt->vcpu, &err);
2499 if (ret == X86EMUL_PROPAGATE_FAULT) {
2500 /* FIXME: need to provide precise fault address */
54b8486f 2501 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2502 return ret;
2503 }
2504 }
2505
2506 return load_state_from_tss32(ctxt, ops, &tss_seg);
2507}
2508
2509static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2510 struct x86_emulate_ops *ops,
2511 u16 tss_selector, int reason,
2512 bool has_error_code, u32 error_code)
38ba30ba
GN		 2513{
2514 struct desc_struct curr_tss_desc, next_tss_desc;
2515 int ret;
2516 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2517 ulong old_tss_base =
5951c442 2518 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2519 u32 desc_limit;
38ba30ba
GN		 2520
2521 /* FIXME: old_tss_base == ~0 ? */
2522
2523 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2524 if (ret != X86EMUL_CONTINUE)
2525 return ret;
2526 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2527 if (ret != X86EMUL_CONTINUE)
2528 return ret;
2529
2530 /* FIXME: check that next_tss_desc is tss */
2531
2532 if (reason != TASK_SWITCH_IRET) {
2533 if ((tss_selector & 3) > next_tss_desc.dpl ||
2534 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2535 emulate_gp(ctxt, 0);
38ba30ba
GN		 2536 return X86EMUL_PROPAGATE_FAULT;
2537 }
2538 }
2539
ceffb459
GN		 2540 desc_limit = desc_limit_scaled(&next_tss_desc);
2541 if (!next_tss_desc.p ||
2542 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2543 desc_limit < 0x2b)) {
54b8486f 2544 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2545 return X86EMUL_PROPAGATE_FAULT;
2546 }
2547
2548 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2549 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2550 write_segment_descriptor(ctxt, ops, old_tss_sel,
2551 &curr_tss_desc);
2552 }
2553
2554 if (reason == TASK_SWITCH_IRET)
2555 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2556
2557 /* set back link to prev task only if NT bit is set in eflags
2558 note that old_tss_sel is not used afetr this point */
2559 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2560 old_tss_sel = 0xffff;
2561
2562 if (next_tss_desc.type & 8)
2563 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2564 old_tss_base, &next_tss_desc);
2565 else
2566 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2567 old_tss_base, &next_tss_desc);
0760d448
JK		 2568 if (ret != X86EMUL_CONTINUE)
2569 return ret;
38ba30ba
GN		 2570
2571 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2572 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2573
2574 if (reason != TASK_SWITCH_IRET) {
2575 next_tss_desc.type |= (1 << 1); /* set busy flag */
2576 write_segment_descriptor(ctxt, ops, tss_selector,
2577 &next_tss_desc);
2578 }
2579
2580 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2581 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2582 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2583
e269fb21
JK		 2584 if (has_error_code) {
2585 struct decode_cache *c = &ctxt->decode;
2586
2587 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2588 c->lock_prefix = 0;
2589 c->src.val = (unsigned long) error_code;
79168fd1 2590 emulate_push(ctxt, ops);
e269fb21
JK		 2591 }
2592
38ba30ba
GN		 2593 return ret;
2594}
2595
2596int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2597 struct x86_emulate_ops *ops,
e269fb21
JK		 2598 u16 tss_selector, int reason,
2599 bool has_error_code, u32 error_code)
38ba30ba
GN		 2600{
2601 struct decode_cache *c = &ctxt->decode;
2602 int rc;
2603
38ba30ba 2604 c->eip = ctxt->eip;
e269fb21 2605 c->dst.type = OP_NONE;
38ba30ba 2606
e269fb21
JK		 2607 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2608 has_error_code, error_code);
38ba30ba
GN		 2609
2610 if (rc == X86EMUL_CONTINUE) {
e269fb21 2611 rc = writeback(ctxt, ops);
95c55886
GN		 2612 if (rc == X86EMUL_CONTINUE)
2613 ctxt->eip = c->eip;
38ba30ba
GN		 2614 }
2615
19d04437 2616 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2617}
2618
a682e354 2619static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2620 int reg, struct operand *op)
a682e354
GN		 2621{
2622 struct decode_cache *c = &ctxt->decode;
2623 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2624
d9271123
GN		 2625 register_address_increment(c, &c->regs[reg], df * op->bytes);
2626 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2627}
2628
8b4caf66 2629int
1be3aa47 2630x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2631{
8b4caf66 2632 u64 msr_data;
8b4caf66 2633 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2634 int rc = X86EMUL_CONTINUE;
5cd21917 2635 int saved_dst_type = c->dst.type;
8b4caf66 2636
9de41573 2637 ctxt->decode.mem_read.pos = 0;
310b5d30 2638
1161624f 2639 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2640 emulate_ud(ctxt);
1161624f
GN		 2641 goto done;
2642 }
2643
d380a5e4 2644 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2645 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2646 emulate_ud(ctxt);
d380a5e4
GN		 2647 goto done;
2648 }
2649
e92805ac 2650 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2651 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2652 emulate_gp(ctxt, 0);
e92805ac
GN		 2653 goto done;
2654 }
2655
b9fa9d6b 2656 if (c->rep_prefix && (c->d & String)) {
5cd21917 2657 ctxt->restart = true;
b9fa9d6b 2658 /* All REP prefixes have the same first termination condition */
c73e197b 2659 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2660 string_done:
2661 ctxt->restart = false;
95c55886 2662 ctxt->eip = c->eip;
b9fa9d6b
AK		 2663 goto done;
2664 }
2665 /* The second termination condition only applies for REPE
2666 * and REPNE. Test if the repeat string operation prefix is
2667 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2668 * corresponding termination condition according to:
2669 * - if REPE/REPZ and ZF = 0 then done
2670 * - if REPNE/REPNZ and ZF = 1 then done
2671 */
2672 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2673 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2674 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2675 ((ctxt->eflags & EFLG_ZF) == 0))
2676 goto string_done;
b9fa9d6b 2677 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2678 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2679 goto string_done;
b9fa9d6b 2680 }
063db061 2681 c->eip = ctxt->eip;
b9fa9d6b
AK		 2682 }
2683
8b4caf66 2684 if (c->src.type == OP_MEM) {
9de41573 2685 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2686 c->src.valptr, c->src.bytes);
b60d513c 2687 if (rc != X86EMUL_CONTINUE)
8b4caf66 2688 goto done;
16518d5a 2689 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2690 }
2691
e35b7b9c 2692 if (c->src2.type == OP_MEM) {
9de41573
GN		 2693 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2694 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2695 if (rc != X86EMUL_CONTINUE)
2696 goto done;
2697 }
2698
8b4caf66
LV		 2699 if ((c->d & DstMask) == ImplicitOps)
2700 goto special_insn;
2701
2702
69f55cb1
GN		 2703 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2704 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2705 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2706 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2707 if (rc != X86EMUL_CONTINUE)
2708 goto done;
038e51de 2709 }
e4e03ded 2710 c->dst.orig_val = c->dst.val;
038e51de 2711
018a98db
AK		 2712special_insn:
2713
e4e03ded 2714 if (c->twobyte)
6aa8b732
AK		 2715 goto twobyte_insn;
2716
e4e03ded 2717 switch (c->b) {
6aa8b732
AK		 2718 case 0x00 ... 0x05:
2719 add: /* add */
05f086f8 2720 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2721 break;
0934ac9d 2722 case 0x06: /* push es */
79168fd1 2723 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2724 break;
2725 case 0x07: /* pop es */
0934ac9d 2726 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2727 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2728 goto done;
2729 break;
6aa8b732
AK		 2730 case 0x08 ... 0x0d:
2731 or: /* or */
05f086f8 2732 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2733 break;
0934ac9d 2734 case 0x0e: /* push cs */
79168fd1 2735 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2736 break;
6aa8b732
AK		 2737 case 0x10 ... 0x15:
2738 adc: /* adc */
05f086f8 2739 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2740 break;
0934ac9d 2741 case 0x16: /* push ss */
79168fd1 2742 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2743 break;
2744 case 0x17: /* pop ss */
0934ac9d 2745 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2746 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2747 goto done;
2748 break;
6aa8b732
AK		 2749 case 0x18 ... 0x1d:
2750 sbb: /* sbb */
05f086f8 2751 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2752 break;
0934ac9d 2753 case 0x1e: /* push ds */
79168fd1 2754 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2755 break;
2756 case 0x1f: /* pop ds */
0934ac9d 2757 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2758 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2759 goto done;
2760 break;
aa3a816b 2761 case 0x20 ... 0x25:
6aa8b732 2762 and: /* and */
05f086f8 2763 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2764 break;
2765 case 0x28 ... 0x2d:
2766 sub: /* sub */
05f086f8 2767 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2768 break;
2769 case 0x30 ... 0x35:
2770 xor: /* xor */
05f086f8 2771 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2772 break;
2773 case 0x38 ... 0x3d:
2774 cmp: /* cmp */
05f086f8 2775 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2776 break;
33615aa9
AK		 2777 case 0x40 ... 0x47: /* inc r16/r32 */
2778 emulate_1op("inc", c->dst, ctxt->eflags);
2779 break;
2780 case 0x48 ... 0x4f: /* dec r16/r32 */
2781 emulate_1op("dec", c->dst, ctxt->eflags);
2782 break;
2783 case 0x50 ... 0x57: /* push reg */
79168fd1 2784 emulate_push(ctxt, ops);
33615aa9
AK		 2785 break;
2786 case 0x58 ... 0x5f: /* pop reg */
2787 pop_instruction:
350f69dc 2788 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2789 if (rc != X86EMUL_CONTINUE)
33615aa9 2790 goto done;
33615aa9 2791 break;
abcf14b5 2792 case 0x60: /* pusha */
c37eda13
WY		 2793 rc = emulate_pusha(ctxt, ops);
2794 if (rc != X86EMUL_CONTINUE)
2795 goto done;
abcf14b5
MG		 2796 break;
2797 case 0x61: /* popa */
2798 rc = emulate_popa(ctxt, ops);
1b30eaa8 2799 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2800 goto done;
2801 break;
6aa8b732 2802 case 0x63: /* movsxd */
8b4caf66 2803 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2804 goto cannot_emulate;
e4e03ded 2805 c->dst.val = (s32) c->src.val;
6aa8b732 2806 break;
91ed7a0e 2807 case 0x68: /* push imm */
018a98db 2808 case 0x6a: /* push imm8 */
79168fd1 2809 emulate_push(ctxt, ops);
018a98db
AK		 2810 break;
2811 case 0x6c: /* insb */
2812 case 0x6d: /* insw/insd */
7972995b 2813 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2814 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2815 c->dst.bytes)) {
54b8486f 2816 emulate_gp(ctxt, 0);
f850e2e6
GN		 2817 goto done;
2818 }
7b262e90
GN		 2819 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2820 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2821 goto done; /* IO is needed, skip writeback */
2822 break;
018a98db
AK		 2823 case 0x6e: /* outsb */
2824 case 0x6f: /* outsw/outsd */
7972995b 2825 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2826 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2827 c->src.bytes)) {
54b8486f 2828 emulate_gp(ctxt, 0);
f850e2e6
GN		 2829 goto done;
2830 }
7972995b
GN		 2831 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2832 &c->src.val, 1, ctxt->vcpu);
2833
2834 c->dst.type = OP_NONE; /* nothing to writeback */
2835 break;
b2833e3c 2836 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2837 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2838 jmp_rel(c, c->src.val);
018a98db 2839 break;
6aa8b732 2840 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2841 switch (c->modrm_reg) {
6aa8b732
AK		 2842 case 0:
2843 goto add;
2844 case 1:
2845 goto or;
2846 case 2:
2847 goto adc;
2848 case 3:
2849 goto sbb;
2850 case 4:
2851 goto and;
2852 case 5:
2853 goto sub;
2854 case 6:
2855 goto xor;
2856 case 7:
2857 goto cmp;
2858 }
2859 break;
2860 case 0x84 ... 0x85:
dfb507c4 2861 test:
05f086f8 2862 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2863 break;
2864 case 0x86 ... 0x87: /* xchg */
b13354f8 2865 xchg:
6aa8b732 2866 /* Write back the register source. */
e4e03ded 2867 switch (c->dst.bytes) {
6aa8b732 2868 case 1:
e4e03ded 2869 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2870 break;
2871 case 2:
e4e03ded 2872 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2873 break;
2874 case 4:
e4e03ded 2875 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2876 break; /* 64b reg: zero-extend */
2877 case 8:
e4e03ded 2878 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2879 break;
2880 }
2881 /*
2882 * Write back the memory destination with implicit LOCK
2883 * prefix.
2884 */
e4e03ded
LV		 2885 c->dst.val = c->src.val;
2886 c->lock_prefix = 1;
6aa8b732 2887 break;
6aa8b732 2888 case 0x88 ... 0x8b: /* mov */
7de75248 2889 goto mov;
79168fd1
GN		 2890 case 0x8c: /* mov r/m, sreg */
2891 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2892 emulate_ud(ctxt);
5e3ae6c5 2893 goto done;
38d5bc6d 2894 }
79168fd1 2895 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2896 break;
7e0b54b1 2897 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2898 c->dst.val = c->modrm_ea;
7e0b54b1 2899 break;
4257198a
GT		 2900 case 0x8e: { /* mov seg, r/m16 */
2901 uint16_t sel;
4257198a
GT		 2902
2903 sel = c->src.val;
8b9f4414 2904
c697518a
GN		 2905 if (c->modrm_reg == VCPU_SREG_CS ||
2906 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2907 emulate_ud(ctxt);
8b9f4414
GN		 2908 goto done;
2909 }
2910
310b5d30 2911 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2912 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2913
2e873022 2914 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2915
2916 c->dst.type = OP_NONE; /* Disable writeback. */
2917 break;
2918 }
6aa8b732 2919 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2920 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2921 if (rc != X86EMUL_CONTINUE)
6aa8b732 2922 goto done;
6aa8b732 2923 break;
b13354f8 2924 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2925 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2926 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2927 break;
2928 }
2929 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2930 c->src.type = OP_REG;
2931 c->src.bytes = c->op_bytes;
b13354f8
MG		 2932 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2933 c->src.val = *(c->src.ptr);
2934 goto xchg;
fd2a7608 2935 case 0x9c: /* pushf */
05f086f8 2936 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2937 emulate_push(ctxt, ops);
8cdbd2c9 2938 break;
535eabcf 2939 case 0x9d: /* popf */
2b48cc75 2940 c->dst.type = OP_REG;
05f086f8 2941 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2942 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2943 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2944 if (rc != X86EMUL_CONTINUE)
2945 goto done;
2946 break;
5d55f299 2947 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2948 case 0xa4 ... 0xa5: /* movs */
a682e354 2949 goto mov;
6aa8b732 2950 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2951 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2952 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2953 goto cmp;
dfb507c4
MG		 2954 case 0xa8 ... 0xa9: /* test ax, imm */
2955 goto test;
6aa8b732 2956 case 0xaa ... 0xab: /* stos */
e4e03ded 2957 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2958 break;
2959 case 0xac ... 0xad: /* lods */
a682e354 2960 goto mov;
6aa8b732
AK		 2961 case 0xae ... 0xaf: /* scas */
2962 DPRINTF("Urk! I don't handle SCAS.\n");
2963 goto cannot_emulate;
a5e2e82b 2964 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2965 goto mov;
018a98db
AK		 2966 case 0xc0 ... 0xc1:
2967 emulate_grp2(ctxt);
2968 break;
111de5d6 2969 case 0xc3: /* ret */
cf5de4f8 2970 c->dst.type = OP_REG;
111de5d6 2971 c->dst.ptr = &c->eip;
cf5de4f8 2972 c->dst.bytes = c->op_bytes;
111de5d6 2973 goto pop_instruction;
018a98db
AK		 2974 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2975 mov:
2976 c->dst.val = c->src.val;
2977 break;
a77ab5ea
AK		 2978 case 0xcb: /* ret far */
2979 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2980 if (rc != X86EMUL_CONTINUE)
2981 goto done;
2982 break;
2983 case 0xcf: /* iret */
2984 rc = emulate_iret(ctxt, ops);
2985
1b30eaa8 2986 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2987 goto done;
2988 break;
018a98db
AK		 2989 case 0xd0 ... 0xd1: /* Grp2 */
2990 c->src.val = 1;
2991 emulate_grp2(ctxt);
2992 break;
2993 case 0xd2 ... 0xd3: /* Grp2 */
2994 c->src.val = c->regs[VCPU_REGS_RCX];
2995 emulate_grp2(ctxt);
2996 break;
a6a3034c
MG		 2997 case 0xe4: /* inb */
2998 case 0xe5: /* in */
cf8f70bf 2999 goto do_io_in;
a6a3034c
MG		 3000 case 0xe6: /* outb */
3001 case 0xe7: /* out */
cf8f70bf 3002 goto do_io_out;
1a52e051 3003 case 0xe8: /* call (near) */ {
d53c4777 3004 long int rel = c->src.val;
e4e03ded 3005 c->src.val = (unsigned long) c->eip;
7a957275 3006 jmp_rel(c, rel);
79168fd1 3007 emulate_push(ctxt, ops);
8cdbd2c9 3008 break;
1a52e051
NK		 3009 }
3010 case 0xe9: /* jmp rel */
954cd36f 3011 goto jmp;
414e6277
GN		 3012 case 0xea: { /* jmp far */
3013 unsigned short sel;
ea79849d 3014 jump_far:
414e6277
GN		 3015 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3016
3017 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3018 goto done;
954cd36f 3019
414e6277
GN		 3020 c->eip = 0;
3021 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3022 break;
414e6277 3023 }
954cd36f
GT		 3024 case 0xeb:
3025 jmp: /* jmp rel short */
7a957275 3026 jmp_rel(c, c->src.val);
a01af5ec 3027 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3028 break;
a6a3034c
MG		 3029 case 0xec: /* in al,dx */
3030 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3031 c->src.val = c->regs[VCPU_REGS_RDX];
3032 do_io_in:
3033 c->dst.bytes = min(c->dst.bytes, 4u);
3034 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3035 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3036 goto done;
3037 }
7b262e90
GN		 3038 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3039 &c->dst.val))
cf8f70bf
GN		 3040 goto done; /* IO is needed */
3041 break;
ce7a0ad3
WY		 3042 case 0xee: /* out dx,al */
3043 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3044 c->src.val = c->regs[VCPU_REGS_RDX];
3045 do_io_out:
3046 c->dst.bytes = min(c->dst.bytes, 4u);
3047 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3048 emulate_gp(ctxt, 0);
f850e2e6
GN		 3049 goto done;
3050 }
cf8f70bf
GN		 3051 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3052 ctxt->vcpu);
3053 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3054 break;
111de5d6 3055 case 0xf4: /* hlt */
ad312c7c 3056 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3057 break;
111de5d6
AK		 3058 case 0xf5: /* cmc */
3059 /* complement carry flag from eflags reg */
3060 ctxt->eflags ^= EFLG_CF;
3061 c->dst.type = OP_NONE; /* Disable writeback. */
3062 break;
018a98db 3063 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3064 if (!emulate_grp3(ctxt, ops))
3065 goto cannot_emulate;
018a98db 3066 break;
111de5d6
AK		 3067 case 0xf8: /* clc */
3068 ctxt->eflags &= ~EFLG_CF;
3069 c->dst.type = OP_NONE; /* Disable writeback. */
3070 break;
3071 case 0xfa: /* cli */
07cbc6c1 3072 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3073 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3074 goto done;
3075 } else {
f850e2e6
GN		 3076 ctxt->eflags &= ~X86_EFLAGS_IF;
3077 c->dst.type = OP_NONE; /* Disable writeback. */
3078 }
111de5d6
AK		 3079 break;
3080 case 0xfb: /* sti */
07cbc6c1 3081 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3082 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3083 goto done;
3084 } else {
95cb2295 3085 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3086 ctxt->eflags |= X86_EFLAGS_IF;
3087 c->dst.type = OP_NONE; /* Disable writeback. */
3088 }
111de5d6 3089 break;
fb4616f4
MG		 3090 case 0xfc: /* cld */
3091 ctxt->eflags &= ~EFLG_DF;
3092 c->dst.type = OP_NONE; /* Disable writeback. */
3093 break;
3094 case 0xfd: /* std */
3095 ctxt->eflags |= EFLG_DF;
3096 c->dst.type = OP_NONE; /* Disable writeback. */
3097 break;
ea79849d
GN		 3098 case 0xfe: /* Grp4 */
3099 grp45:
018a98db 3100 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3101 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3102 goto done;
3103 break;
ea79849d
GN		 3104 case 0xff: /* Grp5 */
3105 if (c->modrm_reg == 5)
3106 goto jump_far;
3107 goto grp45;
91269b8f
AK		 3108 default:
3109 goto cannot_emulate;
6aa8b732 3110 }
018a98db
AK		 3111
3112writeback:
3113 rc = writeback(ctxt, ops);
1b30eaa8 3114 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3115 goto done;
3116
5cd21917
GN		 3117 /*
3118 * restore dst type in case the decoding will be reused
3119 * (happens for string instruction )
3120 */
3121 c->dst.type = saved_dst_type;
3122
a682e354 3123 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3124 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3125 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3126
3127 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3128 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3129 &c->dst);
d9271123 3130
5cd21917 3131 if (c->rep_prefix && (c->d & String)) {
7b262e90 3132 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3133 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3134 /*
3135 * Re-enter guest when pio read ahead buffer is empty or,
3136 * if it is not used, after each 1024 iteration.
3137 */
3138 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3139 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3140 ctxt->restart = false;
3141 }
9de41573
GN		 3142 /*
3143 * reset read cache here in case string instruction is restared
3144 * without decoding
3145 */
3146 ctxt->decode.mem_read.end = 0;
95c55886 3147 ctxt->eip = c->eip;
018a98db
AK		 3148
3149done:
cb404fe0 3150 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3151
3152twobyte_insn:
e4e03ded 3153 switch (c->b) {
6aa8b732 3154 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3155 switch (c->modrm_reg) {
6aa8b732
AK		 3156 u16 size;
3157 unsigned long address;
3158
aca7f966 3159 case 0: /* vmcall */
e4e03ded 3160 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3161 goto cannot_emulate;
3162
7aa81cc0 3163 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3164 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3165 goto done;
3166
33e3885d 3167 /* Let the processor re-execute the fixed hypercall */
063db061 3168 c->eip = ctxt->eip;
16286d08
AK		 3169 /* Disable writeback. */
3170 c->dst.type = OP_NONE;
aca7f966 3171 break;
6aa8b732 3172 case 2: /* lgdt */
e4e03ded
LV		 3173 rc = read_descriptor(ctxt, ops, c->src.ptr,
3174 &size, &address, c->op_bytes);
1b30eaa8 3175 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3176 goto done;
3177 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3178 /* Disable writeback. */
3179 c->dst.type = OP_NONE;
6aa8b732 3180 break;
aca7f966 3181 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3182 if (c->modrm_mod == 3) {
3183 switch (c->modrm_rm) {
3184 case 1:
3185 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3186 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3187 goto done;
3188 break;
3189 default:
3190 goto cannot_emulate;
3191 }
aca7f966 3192 } else {
e4e03ded 3193 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3194 &size, &address,
e4e03ded 3195 c->op_bytes);
1b30eaa8 3196 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3197 goto done;
3198 realmode_lidt(ctxt->vcpu, size, address);
3199 }
16286d08
AK		 3200 /* Disable writeback. */
3201 c->dst.type = OP_NONE;
6aa8b732
AK		 3202 break;
3203 case 4: /* smsw */
16286d08 3204 c->dst.bytes = 2;
52a46617 3205 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3206 break;
3207 case 6: /* lmsw */
93a152be
GN		 3208 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3209 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3210 c->dst.type = OP_NONE;
6aa8b732 3211 break;
6e1e5ffe 3212 case 5: /* not defined */
54b8486f 3213 emulate_ud(ctxt);
6e1e5ffe 3214 goto done;
6aa8b732 3215 case 7: /* invlpg*/
69f55cb1 3216 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3217 /* Disable writeback. */
3218 c->dst.type = OP_NONE;
6aa8b732
AK		 3219 break;
3220 default:
3221 goto cannot_emulate;
3222 }
3223 break;
e99f0507 3224 case 0x05: /* syscall */
3fb1b5db 3225 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3226 if (rc != X86EMUL_CONTINUE)
3227 goto done;
e66bb2cc
AP		 3228 else
3229 goto writeback;
e99f0507 3230 break;
018a98db
AK		 3231 case 0x06:
3232 emulate_clts(ctxt->vcpu);
3233 c->dst.type = OP_NONE;
3234 break;
018a98db 3235 case 0x09: /* wbinvd */
f5f48ee1
SY		 3236 kvm_emulate_wbinvd(ctxt->vcpu);
3237 c->dst.type = OP_NONE;
3238 break;
3239 case 0x08: /* invd */
018a98db
AK		 3240 case 0x0d: /* GrpP (prefetch) */
3241 case 0x18: /* Grp16 (prefetch/nop) */
3242 c->dst.type = OP_NONE;
3243 break;
3244 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3245 switch (c->modrm_reg) {
3246 case 1:
3247 case 5 ... 7:
3248 case 9 ... 15:
54b8486f 3249 emulate_ud(ctxt);
6aebfa6e
GN		 3250 goto done;
3251 }
52a46617 3252 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3253 c->dst.type = OP_NONE; /* no writeback */
3254 break;
6aa8b732 3255 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3256 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3257 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3258 emulate_ud(ctxt);
1e470be5
GN		 3259 goto done;
3260 }
35aa5375 3261 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3262 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3263 break;
018a98db 3264 case 0x22: /* mov reg, cr */
0f12244f 3265 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3266 emulate_gp(ctxt, 0);
0f12244f
GN		 3267 goto done;
3268 }
018a98db
AK		 3269 c->dst.type = OP_NONE;
3270 break;
6aa8b732 3271 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3272 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3273 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3274 emulate_ud(ctxt);
1e470be5
GN		 3275 goto done;
3276 }
35aa5375 3277
338dbc97
GN		 3278 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3279 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3280 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3281 /* #UD condition is already handled by the code above */
54b8486f 3282 emulate_gp(ctxt, 0);
338dbc97
GN		 3283 goto done;
3284 }
3285
a01af5ec 3286 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3287 break;
018a98db
AK		 3288 case 0x30:
3289 /* wrmsr */
3290 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3291 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3292 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3293 emulate_gp(ctxt, 0);
fd525365 3294 goto done;
018a98db
AK		 3295 }
3296 rc = X86EMUL_CONTINUE;
3297 c->dst.type = OP_NONE;
3298 break;
3299 case 0x32:
3300 /* rdmsr */
3fb1b5db 3301 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3302 emulate_gp(ctxt, 0);
fd525365 3303 goto done;
018a98db
AK		 3304 } else {
3305 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3306 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3307 }
3308 rc = X86EMUL_CONTINUE;
3309 c->dst.type = OP_NONE;
3310 break;
e99f0507 3311 case 0x34: /* sysenter */
3fb1b5db 3312 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3313 if (rc != X86EMUL_CONTINUE)
3314 goto done;
8c604352
AP		 3315 else
3316 goto writeback;
e99f0507
AP		 3317 break;
3318 case 0x35: /* sysexit */
3fb1b5db 3319 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3320 if (rc != X86EMUL_CONTINUE)
3321 goto done;
4668f050
AP		 3322 else
3323 goto writeback;
e99f0507 3324 break;
6aa8b732 3325 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3326 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3327 if (!test_cc(c->b, ctxt->eflags))
3328 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3329 break;
b2833e3c 3330 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3331 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3332 jmp_rel(c, c->src.val);
018a98db
AK		 3333 c->dst.type = OP_NONE;
3334 break;
0934ac9d 3335 case 0xa0: /* push fs */
79168fd1 3336 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3337 break;
3338 case 0xa1: /* pop fs */
3339 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3340 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3341 goto done;
3342 break;
7de75248
NK		 3343 case 0xa3:
3344 bt: /* bt */
e4f8e039 3345 c->dst.type = OP_NONE;
e4e03ded
LV		 3346 /* only subword offset */
3347 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3348 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3349 break;
9bf8ea42
GT		 3350 case 0xa4: /* shld imm8, r, r/m */
3351 case 0xa5: /* shld cl, r, r/m */
3352 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3353 break;
0934ac9d 3354 case 0xa8: /* push gs */
79168fd1 3355 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3356 break;
3357 case 0xa9: /* pop gs */
3358 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3359 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3360 goto done;
3361 break;
7de75248
NK		 3362 case 0xab:
3363 bts: /* bts */
e4e03ded
LV		 3364 /* only subword offset */
3365 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3366 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3367 break;
9bf8ea42
GT		 3368 case 0xac: /* shrd imm8, r, r/m */
3369 case 0xad: /* shrd cl, r, r/m */
3370 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3371 break;
2a7c5b8b
GC		 3372 case 0xae: /* clflush */
3373 break;
6aa8b732
AK		 3374 case 0xb0 ... 0xb1: /* cmpxchg */
3375 /*
3376 * Save real source value, then compare EAX against
3377 * destination.
3378 */
e4e03ded
LV		 3379 c->src.orig_val = c->src.val;
3380 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3381 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3382 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3383 /* Success: write back to memory. */
e4e03ded 3384 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3385 } else {
3386 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3387 c->dst.type = OP_REG;
3388 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3389 }
3390 break;
6aa8b732
AK		 3391 case 0xb3:
3392 btr: /* btr */
e4e03ded
LV		 3393 /* only subword offset */
3394 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3395 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3396 break;
6aa8b732 3397 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3398 c->dst.bytes = c->op_bytes;
3399 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3400 : (u16) c->src.val;
6aa8b732 3401 break;
6aa8b732 3402 case 0xba: /* Grp8 */
e4e03ded 3403 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3404 case 0:
3405 goto bt;
3406 case 1:
3407 goto bts;
3408 case 2:
3409 goto btr;
3410 case 3:
3411 goto btc;
3412 }
3413 break;
7de75248
NK		 3414 case 0xbb:
3415 btc: /* btc */
e4e03ded
LV		 3416 /* only subword offset */
3417 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3418 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3419 break;
6aa8b732 3420 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3421 c->dst.bytes = c->op_bytes;
3422 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3423 (s16) c->src.val;
6aa8b732 3424 break;
a012e65a 3425 case 0xc3: /* movnti */
e4e03ded
LV		 3426 c->dst.bytes = c->op_bytes;
3427 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3428 (u64) c->src.val;
a012e65a 3429 break;
6aa8b732 3430 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3431 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3432 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3433 goto done;
3434 break;
91269b8f
AK		 3435 default:
3436 goto cannot_emulate;
6aa8b732
AK		 3437 }
3438 goto writeback;
3439
3440cannot_emulate:
e4e03ded 3441 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3442 return -1;
3443}
Linux kernel - Deliverables
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