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KVM: x86 emulator: Stop passing ctxt->ops as arg of decode helpers
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
221192bd
MT		 50#define DstDX (8<<1) /* Destination is in DX register */
51#define DstMask (0xf<<1)
6aa8b732 52/* Source operand type. */
221192bd
MT		 53#define SrcNone (0<<5) /* No source operand. */
54#define SrcReg (1<<5) /* Register operand. */
55#define SrcMem (2<<5) /* Memory operand. */
56#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
58#define SrcImm (5<<5) /* Immediate operand. */
59#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
60#define SrcOne (7<<5) /* Implied '1' */
61#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
62#define SrcImmU (9<<5) /* Immediate operand, unsigned */
63#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
64#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
65#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
66#define SrcAcc (0xd<<5) /* Source Accumulator */
67#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
68#define SrcDX (0xf<<5) /* Source is in DX register */
69#define SrcMask (0xf<<5)
6aa8b732 70/* Generic ModRM decode. */
221192bd 71#define ModRM (1<<9)
6aa8b732 72/* Destination is only written; never read. */
221192bd
MT		 73#define Mov (1<<10)
74#define BitOp (1<<11)
75#define MemAbs (1<<12) /* Memory operand is absolute displacement */
76#define String (1<<13) /* String instruction (rep capable) */
77#define Stack (1<<14) /* Stack instruction (push/pop) */
78#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
79#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
81#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
82#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
83#define Sse (1<<18) /* SSE Vector instruction */
d8769fed 84/* Misc flags */
8ea7d6ae 85#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 86#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
c4f035c6 112 u8 intercept;
120df890 113 union {
ef65c889 114 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 115 struct opcode *group;
116 struct group_dual *gdual;
0d7cdee8 117 struct gprefix *gprefix;
120df890 118 } u;
d09beabd 119 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 120};
121
122struct group_dual {
123 struct opcode mod012[8];
124 struct opcode mod3[8];
d65b1dee
AK		 125};
126
0d7cdee8
AK		 127struct gprefix {
128 struct opcode pfx_no;
129 struct opcode pfx_66;
130 struct opcode pfx_f2;
131 struct opcode pfx_f3;
132};
133
6aa8b732 134/* EFLAGS bit definitions. */
d4c6a154
GN		 135#define EFLG_ID (1<<21)
136#define EFLG_VIP (1<<20)
137#define EFLG_VIF (1<<19)
138#define EFLG_AC (1<<18)
b1d86143
AP		 139#define EFLG_VM (1<<17)
140#define EFLG_RF (1<<16)
d4c6a154
GN		 141#define EFLG_IOPL (3<<12)
142#define EFLG_NT (1<<14)
6aa8b732
AK		 143#define EFLG_OF (1<<11)
144#define EFLG_DF (1<<10)
b1d86143 145#define EFLG_IF (1<<9)
d4c6a154 146#define EFLG_TF (1<<8)
6aa8b732
AK		 147#define EFLG_SF (1<<7)
148#define EFLG_ZF (1<<6)
149#define EFLG_AF (1<<4)
150#define EFLG_PF (1<<2)
151#define EFLG_CF (1<<0)
152
62bd430e
MG		 153#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
154#define EFLG_RESERVED_ONE_MASK 2
155
6aa8b732
AK		 156/*
157 * Instruction emulation:
158 * Most instructions are emulated directly via a fragment of inline assembly
159 * code. This allows us to save/restore EFLAGS and thus very easily pick up
160 * any modified flags.
161 */
162
05b3e0c2 163#if defined(CONFIG_X86_64)
6aa8b732
AK		 164#define _LO32 "k" /* force 32-bit operand */
165#define _STK "%%rsp" /* stack pointer */
166#elif defined(__i386__)
167#define _LO32 "" /* force 32-bit operand */
168#define _STK "%%esp" /* stack pointer */
169#endif
170
171/*
172 * These EFLAGS bits are restored from saved value during emulation, and
173 * any changes are written back to the saved value after emulation.
174 */
175#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
176
177/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 178#define _PRE_EFLAGS(_sav, _msk, _tmp) \
179 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
180 "movl %"_sav",%"_LO32 _tmp"; " \
181 "push %"_tmp"; " \
182 "push %"_tmp"; " \
183 "movl %"_msk",%"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "pushf; " \
186 "notl %"_LO32 _tmp"; " \
187 "andl %"_LO32 _tmp",("_STK"); " \
188 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
189 "pop %"_tmp"; " \
190 "orl %"_LO32 _tmp",("_STK"); " \
191 "popf; " \
192 "pop %"_sav"; "
6aa8b732
AK		 193
194/* After executing instruction: write-back necessary bits in EFLAGS. */
195#define _POST_EFLAGS(_sav, _msk, _tmp) \
196 /* _sav |= EFLAGS & _msk; */ \
197 "pushf; " \
198 "pop %"_tmp"; " \
199 "andl %"_msk",%"_LO32 _tmp"; " \
200 "orl %"_LO32 _tmp",%"_sav"; "
201
dda96d8f
AK		 202#ifdef CONFIG_X86_64
203#define ON64(x) x
204#else
205#define ON64(x)
206#endif
207
b3b3d25a 208#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 209 do { \
210 __asm__ __volatile__ ( \
211 _PRE_EFLAGS("0", "4", "2") \
212 _op _suffix " %"_x"3,%1; " \
213 _POST_EFLAGS("0", "4", "2") \
fb2c2641 214 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 215 "=&r" (_tmp) \
216 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 217 } while (0)
6b7ad61f
AK		 218
219
6aa8b732
AK		 220/* Raw emulation: instruction has two explicit operands. */
221#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 222 do { \
223 unsigned long _tmp; \
224 \
225 switch ((_dst).bytes) { \
226 case 2: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 228 break; \
229 case 4: \
b3b3d25a 230 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 231 break; \
232 case 8: \
b3b3d25a 233 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 234 break; \
235 } \
6aa8b732
AK		 236 } while (0)
237
238#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
239 do { \
6b7ad61f 240 unsigned long _tmp; \
d77c26fc 241 switch ((_dst).bytes) { \
6aa8b732 242 case 1: \
b3b3d25a 243 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 244 break; \
245 default: \
246 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
247 _wx, _wy, _lx, _ly, _qx, _qy); \
248 break; \
249 } \
250 } while (0)
251
252/* Source operand is byte-sized and may be restricted to just %cl. */
253#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
254 __emulate_2op(_op, _src, _dst, _eflags, \
255 "b", "c", "b", "c", "b", "c", "b", "c")
256
257/* Source operand is byte, word, long or quad sized. */
258#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
259 __emulate_2op(_op, _src, _dst, _eflags, \
260 "b", "q", "w", "r", _LO32, "r", "", "r")
261
262/* Source operand is word, long or quad sized. */
263#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
264 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
265 "w", "r", _LO32, "r", "", "r")
266
d175226a 267/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 268#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
269 do { \
270 unsigned long _tmp; \
271 _type _clv = (_cl).val; \
272 _type _srcv = (_src).val; \
273 _type _dstv = (_dst).val; \
274 \
275 __asm__ __volatile__ ( \
276 _PRE_EFLAGS("0", "5", "2") \
277 _op _suffix " %4,%1 \n" \
278 _POST_EFLAGS("0", "5", "2") \
279 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
280 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
281 ); \
282 \
283 (_cl).val = (unsigned long) _clv; \
284 (_src).val = (unsigned long) _srcv; \
285 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 286 } while (0)
287
7295261c
AK		 288#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
289 do { \
290 switch ((_dst).bytes) { \
291 case 2: \
292 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
293 "w", unsigned short); \
294 break; \
295 case 4: \
296 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
297 "l", unsigned int); \
298 break; \
299 case 8: \
300 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
301 "q", unsigned long)); \
302 break; \
303 } \
d175226a
GT		 304 } while (0)
305
dda96d8f 306#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 307 do { \
308 unsigned long _tmp; \
309 \
dda96d8f
AK		 310 __asm__ __volatile__ ( \
311 _PRE_EFLAGS("0", "3", "2") \
312 _op _suffix " %1; " \
313 _POST_EFLAGS("0", "3", "2") \
314 : "=m" (_eflags), "+m" ((_dst).val), \
315 "=&r" (_tmp) \
316 : "i" (EFLAGS_MASK)); \
317 } while (0)
318
319/* Instruction has only one explicit operand (no source operand). */
320#define emulate_1op(_op, _dst, _eflags) \
321 do { \
d77c26fc 322 switch ((_dst).bytes) { \
dda96d8f
AK		 323 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
324 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
325 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
326 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 327 } \
328 } while (0)
329
3f9f53b0
MG		 330#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
331 do { \
332 unsigned long _tmp; \
333 \
334 __asm__ __volatile__ ( \
335 _PRE_EFLAGS("0", "4", "1") \
336 _op _suffix " %5; " \
337 _POST_EFLAGS("0", "4", "1") \
338 : "=m" (_eflags), "=&r" (_tmp), \
339 "+a" (_rax), "+d" (_rdx) \
340 : "i" (EFLAGS_MASK), "m" ((_src).val), \
341 "a" (_rax), "d" (_rdx)); \
342 } while (0)
343
f6b3597b
AK		 344#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
345 do { \
346 unsigned long _tmp; \
347 \
348 __asm__ __volatile__ ( \
349 _PRE_EFLAGS("0", "5", "1") \
350 "1: \n\t" \
351 _op _suffix " %6; " \
352 "2: \n\t" \
353 _POST_EFLAGS("0", "5", "1") \
354 ".pushsection .fixup,\"ax\" \n\t" \
355 "3: movb $1, %4 \n\t" \
356 "jmp 2b \n\t" \
357 ".popsection \n\t" \
358 _ASM_EXTABLE(1b, 3b) \
359 : "=m" (_eflags), "=&r" (_tmp), \
360 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
361 : "i" (EFLAGS_MASK), "m" ((_src).val), \
362 "a" (_rax), "d" (_rdx)); \
363 } while (0)
364
3f9f53b0 365/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 366#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
367 do { \
368 switch((_src).bytes) { \
369 case 1: \
370 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
371 _eflags, "b"); \
372 break; \
373 case 2: \
374 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
375 _eflags, "w"); \
376 break; \
377 case 4: \
378 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
379 _eflags, "l"); \
380 break; \
381 case 8: \
382 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
383 _eflags, "q")); \
384 break; \
3f9f53b0
MG		 385 } \
386 } while (0)
387
f6b3597b
AK		 388#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
389 do { \
390 switch((_src).bytes) { \
391 case 1: \
392 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
393 _eflags, "b", _ex); \
394 break; \
395 case 2: \
396 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
397 _eflags, "w", _ex); \
398 break; \
399 case 4: \
400 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
401 _eflags, "l", _ex); \
402 break; \
403 case 8: ON64( \
404 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
405 _eflags, "q", _ex)); \
406 break; \
407 } \
408 } while (0)
409
8a76d7f2
JR		 410static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
411 enum x86_intercept intercept,
412 enum x86_intercept_stage stage)
413{
414 struct x86_instruction_info info = {
415 .intercept = intercept,
416 .rep_prefix = ctxt->decode.rep_prefix,
417 .modrm_mod = ctxt->decode.modrm_mod,
418 .modrm_reg = ctxt->decode.modrm_reg,
419 .modrm_rm = ctxt->decode.modrm_rm,
420 .src_val = ctxt->decode.src.val64,
421 .src_bytes = ctxt->decode.src.bytes,
422 .dst_bytes = ctxt->decode.dst.bytes,
423 .ad_bytes = ctxt->decode.ad_bytes,
424 .next_rip = ctxt->eip,
425 };
426
2953538e 427 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 428}
429
ddcb2885
HH		 430static inline unsigned long ad_mask(struct decode_cache *c)
431{
432 return (1UL << (c->ad_bytes << 3)) - 1;
433}
434
6aa8b732 435/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 436static inline unsigned long
437address_mask(struct decode_cache *c, unsigned long reg)
438{
439 if (c->ad_bytes == sizeof(unsigned long))
440 return reg;
441 else
442 return reg & ad_mask(c);
443}
444
445static inline unsigned long
90de84f5 446register_address(struct decode_cache *c, unsigned long reg)
e4706772 447{
90de84f5 448 return address_mask(c, reg);
e4706772
HH		 449}
450
7a957275
HH		 451static inline void
452register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 *reg += inc;
456 else
457 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
458}
6aa8b732 459
7a957275
HH		 460static inline void jmp_rel(struct decode_cache *c, int rel)
461{
462 register_address_increment(c, &c->eip, rel);
463}
098c937b 464
56697687
AK		 465static u32 desc_limit_scaled(struct desc_struct *desc)
466{
467 u32 limit = get_desc_limit(desc);
468
469 return desc->g ? (limit << 12) | 0xfff : limit;
470}
471
7a5b56df
AK		 472static void set_seg_override(struct decode_cache *c, int seg)
473{
474 c->has_seg_override = true;
475 c->seg_override = seg;
476}
477
79168fd1
GN		 478static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
479 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 480{
481 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
482 return 0;
483
4bff1e86 484 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 485}
486
90de84f5 487static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
90de84f5 488 struct decode_cache *c)
7a5b56df
AK		 489{
490 if (!c->has_seg_override)
491 return 0;
492
90de84f5 493 return c->seg_override;
7a5b56df
AK		 494}
495
35d3d4a1
AK		 496static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
497 u32 error, bool valid)
54b8486f 498{
da9cb575
AK		 499 ctxt->exception.vector = vec;
500 ctxt->exception.error_code = error;
501 ctxt->exception.error_code_valid = valid;
35d3d4a1 502 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 503}
504
3b88e41a
JR		 505static int emulate_db(struct x86_emulate_ctxt *ctxt)
506{
507 return emulate_exception(ctxt, DB_VECTOR, 0, false);
508}
509
35d3d4a1 510static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 511{
35d3d4a1 512 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 513}
514
618ff15d
AK		 515static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
516{
517 return emulate_exception(ctxt, SS_VECTOR, err, true);
518}
519
35d3d4a1 520static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 521{
35d3d4a1 522 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 523}
524
35d3d4a1 525static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 528}
529
34d1f490
AK		 530static int emulate_de(struct x86_emulate_ctxt *ctxt)
531{
35d3d4a1 532 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 533}
534
1253791d
AK		 535static int emulate_nm(struct x86_emulate_ctxt *ctxt)
536{
537 return emulate_exception(ctxt, NM_VECTOR, 0, false);
538}
539
1aa36616
AK		 540static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
541{
542 u16 selector;
543 struct desc_struct desc;
544
545 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
546 return selector;
547}
548
549static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
550 unsigned seg)
551{
552 u16 dummy;
553 u32 base3;
554 struct desc_struct desc;
555
556 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
557 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
558}
559
3d9b938e 560static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 561 struct segmented_address addr,
3d9b938e 562 unsigned size, bool write, bool fetch,
52fd8b44
AK		 563 ulong *linear)
564{
565 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 566 struct desc_struct desc;
567 bool usable;
52fd8b44 568 ulong la;
618ff15d 569 u32 lim;
1aa36616 570 u16 sel;
618ff15d 571 unsigned cpl, rpl;
52fd8b44
AK		 572
573 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 574 switch (ctxt->mode) {
575 case X86EMUL_MODE_REAL:
576 break;
577 case X86EMUL_MODE_PROT64:
578 if (((signed long)la << 16) >> 16 != la)
579 return emulate_gp(ctxt, 0);
580 break;
581 default:
1aa36616
AK		 582 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
583 addr.seg);
618ff15d
AK		 584 if (!usable)
585 goto bad;
586 /* code segment or read-only data segment */
587 if (((desc.type & 8) || !(desc.type & 2)) && write)
588 goto bad;
589 /* unreadable code segment */
3d9b938e 590 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 591 goto bad;
592 lim = desc_limit_scaled(&desc);
593 if ((desc.type & 8) || !(desc.type & 4)) {
594 /* expand-up segment */
595 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
596 goto bad;
597 } else {
598 /* exapand-down segment */
599 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
600 goto bad;
601 lim = desc.d ? 0xffffffff : 0xffff;
602 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
603 goto bad;
604 }
717746e3 605 cpl = ctxt->ops->cpl(ctxt);
1aa36616 606 rpl = sel & 3;
618ff15d
AK		 607 cpl = max(cpl, rpl);
608 if (!(desc.type & 8)) {
609 /* data segment */
610 if (cpl > desc.dpl)
611 goto bad;
612 } else if ((desc.type & 8) && !(desc.type & 4)) {
613 /* nonconforming code segment */
614 if (cpl != desc.dpl)
615 goto bad;
616 } else if ((desc.type & 8) && (desc.type & 4)) {
617 /* conforming code segment */
618 if (cpl < desc.dpl)
619 goto bad;
620 }
621 break;
622 }
3d9b938e 623 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 624 la &= (u32)-1;
625 *linear = la;
626 return X86EMUL_CONTINUE;
618ff15d
AK		 627bad:
628 if (addr.seg == VCPU_SREG_SS)
629 return emulate_ss(ctxt, addr.seg);
630 else
631 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 632}
633
3d9b938e
NE		 634static int linearize(struct x86_emulate_ctxt *ctxt,
635 struct segmented_address addr,
636 unsigned size, bool write,
637 ulong *linear)
638{
639 return __linearize(ctxt, addr, size, write, false, linear);
640}
641
642
3ca3ac4d
AK		 643static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
644 struct segmented_address addr,
645 void *data,
646 unsigned size)
647{
9fa088f4
AK		 648 int rc;
649 ulong linear;
650
83b8795a 651 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 652 if (rc != X86EMUL_CONTINUE)
653 return rc;
0f65dd70 654 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 655}
656
67cbc90d 657static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt,
2fb53ad8 658 unsigned long eip, u8 *dest)
62266869
AK		 659{
660 struct fetch_cache *fc = &ctxt->decode.fetch;
661 int rc;
2fb53ad8 662 int size, cur_size;
62266869 663
2fb53ad8 664 if (eip == fc->end) {
3d9b938e
NE		 665 unsigned long linear;
666 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 667 cur_size = fc->end - fc->start;
668 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 669 rc = __linearize(ctxt, addr, size, false, true, &linear);
670 if (rc != X86EMUL_CONTINUE)
671 return rc;
ef5d75cc
TY		 672 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
673 size, &ctxt->exception);
3e2815e9 674 if (rc != X86EMUL_CONTINUE)
62266869 675 return rc;
2fb53ad8 676 fc->end += size;
62266869 677 }
2fb53ad8 678 *dest = fc->data[eip - fc->start];
3e2815e9 679 return X86EMUL_CONTINUE;
62266869
AK		 680}
681
682static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
62266869
AK		 683 unsigned long eip, void *dest, unsigned size)
684{
3e2815e9 685 int rc;
62266869 686
eb3c79e6 687 /* x86 instructions are limited to 15 bytes. */
063db061 688 if (eip + size - ctxt->eip > 15)
eb3c79e6 689 return X86EMUL_UNHANDLEABLE;
62266869 690 while (size--) {
ef5d75cc 691 rc = do_insn_fetch_byte(ctxt, eip++, dest++);
3e2815e9 692 if (rc != X86EMUL_CONTINUE)
62266869
AK		 693 return rc;
694 }
3e2815e9 695 return X86EMUL_CONTINUE;
62266869
AK		 696}
697
67cbc90d
TY		 698/* Fetch next part of the instruction being emulated. */
699#define insn_fetch(_type, _size, _eip) \
700({ unsigned long _x; \
ef5d75cc 701 rc = do_insn_fetch(ctxt, (_eip), &_x, (_size)); \
67cbc90d
TY		 702 if (rc != X86EMUL_CONTINUE) \
703 goto done; \
704 (_eip) += (_size); \
705 (_type)_x; \
706})
707
708#define insn_fetch_arr(_arr, _size, _eip) \
ef5d75cc 709({ rc = do_insn_fetch(ctxt, (_eip), _arr, (_size)); \
67cbc90d
TY		 710 if (rc != X86EMUL_CONTINUE) \
711 goto done; \
712 (_eip) += (_size); \
713})
714
1e3c5cb0
RR		 715/*
716 * Given the 'reg' portion of a ModRM byte, and a register block, return a
717 * pointer into the block that addresses the relevant register.
718 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
719 */
720static void *decode_register(u8 modrm_reg, unsigned long *regs,
721 int highbyte_regs)
6aa8b732
AK		 722{
723 void *p;
724
725 p = &regs[modrm_reg];
726 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
727 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
728 return p;
729}
730
731static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 732 struct segmented_address addr,
6aa8b732
AK		 733 u16 *size, unsigned long *address, int op_bytes)
734{
735 int rc;
736
737 if (op_bytes == 2)
738 op_bytes = 3;
739 *address = 0;
3ca3ac4d 740 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 741 if (rc != X86EMUL_CONTINUE)
6aa8b732 742 return rc;
30b31ab6 743 addr.ea += 2;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 745 return rc;
746}
747
bbe9abbd
NK		 748static int test_cc(unsigned int condition, unsigned int flags)
749{
750 int rc = 0;
751
752 switch ((condition & 15) >> 1) {
753 case 0: /* o */
754 rc |= (flags & EFLG_OF);
755 break;
756 case 1: /* b/c/nae */
757 rc |= (flags & EFLG_CF);
758 break;
759 case 2: /* z/e */
760 rc |= (flags & EFLG_ZF);
761 break;
762 case 3: /* be/na */
763 rc |= (flags & (EFLG_CF|EFLG_ZF));
764 break;
765 case 4: /* s */
766 rc |= (flags & EFLG_SF);
767 break;
768 case 5: /* p/pe */
769 rc |= (flags & EFLG_PF);
770 break;
771 case 7: /* le/ng */
772 rc |= (flags & EFLG_ZF);
773 /* fall through */
774 case 6: /* l/nge */
775 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
776 break;
777 }
778
779 /* Odd condition identifiers (lsb == 1) have inverted sense. */
780 return (!!rc ^ (condition & 1));
781}
782
91ff3cb4
AK		 783static void fetch_register_operand(struct operand *op)
784{
785 switch (op->bytes) {
786 case 1:
787 op->val = *(u8 *)op->addr.reg;
788 break;
789 case 2:
790 op->val = *(u16 *)op->addr.reg;
791 break;
792 case 4:
793 op->val = *(u32 *)op->addr.reg;
794 break;
795 case 8:
796 op->val = *(u64 *)op->addr.reg;
797 break;
798 }
799}
800
1253791d
AK		 801static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
802{
803 ctxt->ops->get_fpu(ctxt);
804 switch (reg) {
805 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
806 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
807 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
808 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
809 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
810 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
811 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
812 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
813#ifdef CONFIG_X86_64
814 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
815 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
816 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
817 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
818 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
819 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
820 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
821 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
822#endif
823 default: BUG();
824 }
825 ctxt->ops->put_fpu(ctxt);
826}
827
828static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
829 int reg)
830{
831 ctxt->ops->get_fpu(ctxt);
832 switch (reg) {
833 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
834 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
835 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
836 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
837 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
838 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
839 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
840 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
841#ifdef CONFIG_X86_64
842 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
843 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
844 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
845 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
846 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
847 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
848 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
849 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
850#endif
851 default: BUG();
852 }
853 ctxt->ops->put_fpu(ctxt);
854}
855
856static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
857 struct operand *op,
3c118e24 858 struct decode_cache *c,
3c118e24
AK		 859 int inhibit_bytereg)
860{
33615aa9 861 unsigned reg = c->modrm_reg;
9f1ef3f8 862 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 863
864 if (!(c->d & ModRM))
865 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 866
867 if (c->d & Sse) {
868 op->type = OP_XMM;
869 op->bytes = 16;
870 op->addr.xmm = reg;
871 read_sse_reg(ctxt, &op->vec_val, reg);
872 return;
873 }
874
3c118e24
AK		 875 op->type = OP_REG;
876 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 877 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 878 op->bytes = 1;
879 } else {
1a6440ae 880 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 881 op->bytes = c->op_bytes;
3c118e24 882 }
91ff3cb4 883 fetch_register_operand(op);
3c118e24
AK		 884 op->orig_val = op->val;
885}
886
1c73ef66 887static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 888 struct operand *op)
1c73ef66
AK		 889{
890 struct decode_cache *c = &ctxt->decode;
891 u8 sib;
f5b4edcd 892 int index_reg = 0, base_reg = 0, scale;
3e2815e9 893 int rc = X86EMUL_CONTINUE;
2dbd0dd7 894 ulong modrm_ea = 0;
1c73ef66
AK		 895
896 if (c->rex_prefix) {
897 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
898 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
899 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
900 }
901
902 c->modrm = insn_fetch(u8, 1, c->eip);
903 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
904 c->modrm_reg |= (c->modrm & 0x38) >> 3;
905 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 906 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 907
908 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 909 op->type = OP_REG;
910 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
911 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 912 c->regs, c->d & ByteOp);
1253791d
AK		 913 if (c->d & Sse) {
914 op->type = OP_XMM;
915 op->bytes = 16;
916 op->addr.xmm = c->modrm_rm;
917 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
918 return rc;
919 }
2dbd0dd7 920 fetch_register_operand(op);
1c73ef66
AK		 921 return rc;
922 }
923
2dbd0dd7
AK		 924 op->type = OP_MEM;
925
1c73ef66
AK		 926 if (c->ad_bytes == 2) {
927 unsigned bx = c->regs[VCPU_REGS_RBX];
928 unsigned bp = c->regs[VCPU_REGS_RBP];
929 unsigned si = c->regs[VCPU_REGS_RSI];
930 unsigned di = c->regs[VCPU_REGS_RDI];
931
932 /* 16-bit ModR/M decode. */
933 switch (c->modrm_mod) {
934 case 0:
935 if (c->modrm_rm == 6)
2dbd0dd7 936 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 937 break;
938 case 1:
2dbd0dd7 939 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 940 break;
941 case 2:
2dbd0dd7 942 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 943 break;
944 }
945 switch (c->modrm_rm) {
946 case 0:
2dbd0dd7 947 modrm_ea += bx + si;
1c73ef66
AK		 948 break;
949 case 1:
2dbd0dd7 950 modrm_ea += bx + di;
1c73ef66
AK		 951 break;
952 case 2:
2dbd0dd7 953 modrm_ea += bp + si;
1c73ef66
AK		 954 break;
955 case 3:
2dbd0dd7 956 modrm_ea += bp + di;
1c73ef66
AK		 957 break;
958 case 4:
2dbd0dd7 959 modrm_ea += si;
1c73ef66
AK		 960 break;
961 case 5:
2dbd0dd7 962 modrm_ea += di;
1c73ef66
AK		 963 break;
964 case 6:
965 if (c->modrm_mod != 0)
2dbd0dd7 966 modrm_ea += bp;
1c73ef66
AK		 967 break;
968 case 7:
2dbd0dd7 969 modrm_ea += bx;
1c73ef66
AK		 970 break;
971 }
972 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
973 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 974 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 975 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 976 } else {
977 /* 32/64-bit ModR/M decode. */
84411d85 978 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 979 sib = insn_fetch(u8, 1, c->eip);
980 index_reg |= (sib >> 3) & 7;
981 base_reg |= sib & 7;
982 scale = sib >> 6;
983
dc71d0f1 984 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 985 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 986 else
2dbd0dd7 987 modrm_ea += c->regs[base_reg];
dc71d0f1 988 if (index_reg != 4)
2dbd0dd7 989 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 990 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
991 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 992 c->rip_relative = 1;
84411d85 993 } else
2dbd0dd7 994 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 995 switch (c->modrm_mod) {
996 case 0:
997 if (c->modrm_rm == 5)
2dbd0dd7 998 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 999 break;
1000 case 1:
2dbd0dd7 1001 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 1002 break;
1003 case 2:
2dbd0dd7 1004 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1005 break;
1006 }
1007 }
90de84f5 1008 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1009done:
1010 return rc;
1011}
1012
1013static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1014 struct operand *op)
1c73ef66
AK		 1015{
1016 struct decode_cache *c = &ctxt->decode;
3e2815e9 1017 int rc = X86EMUL_CONTINUE;
1c73ef66 1018
2dbd0dd7 1019 op->type = OP_MEM;
1c73ef66
AK		 1020 switch (c->ad_bytes) {
1021 case 2:
90de84f5 1022 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1023 break;
1024 case 4:
90de84f5 1025 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1026 break;
1027 case 8:
90de84f5 1028 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1029 break;
1030 }
1031done:
1032 return rc;
1033}
1034
35c843c4
WY		 1035static void fetch_bit_operand(struct decode_cache *c)
1036{
7129eeca 1037 long sv = 0, mask;
35c843c4 1038
3885f18f 1039 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1040 mask = ~(c->dst.bytes * 8 - 1);
1041
1042 if (c->src.bytes == 2)
1043 sv = (s16)c->src.val & (s16)mask;
1044 else if (c->src.bytes == 4)
1045 sv = (s32)c->src.val & (s32)mask;
1046
90de84f5 1047 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1048 }
ba7ff2b7
WY		 1049
1050 /* only subword offset */
1051 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1052}
1053
dde7e6d1
AK		 1054static int read_emulated(struct x86_emulate_ctxt *ctxt,
1055 struct x86_emulate_ops *ops,
1056 unsigned long addr, void *dest, unsigned size)
6aa8b732 1057{
dde7e6d1
AK		 1058 int rc;
1059 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1060
dde7e6d1
AK		 1061 while (size) {
1062 int n = min(size, 8u);
1063 size -= n;
1064 if (mc->pos < mc->end)
1065 goto read_cached;
5cd21917 1066
0f65dd70
AK		 1067 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1068 &ctxt->exception);
dde7e6d1
AK		 1069 if (rc != X86EMUL_CONTINUE)
1070 return rc;
1071 mc->end += n;
6aa8b732 1072
dde7e6d1
AK		 1073 read_cached:
1074 memcpy(dest, mc->data + mc->pos, n);
1075 mc->pos += n;
1076 dest += n;
1077 addr += n;
6aa8b732 1078 }
dde7e6d1
AK		 1079 return X86EMUL_CONTINUE;
1080}
6aa8b732 1081
3ca3ac4d
AK		 1082static int segmented_read(struct x86_emulate_ctxt *ctxt,
1083 struct segmented_address addr,
1084 void *data,
1085 unsigned size)
1086{
9fa088f4
AK		 1087 int rc;
1088 ulong linear;
1089
83b8795a 1090 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1091 if (rc != X86EMUL_CONTINUE)
1092 return rc;
1093 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1094}
1095
1096static int segmented_write(struct x86_emulate_ctxt *ctxt,
1097 struct segmented_address addr,
1098 const void *data,
1099 unsigned size)
1100{
9fa088f4
AK		 1101 int rc;
1102 ulong linear;
1103
83b8795a 1104 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1105 if (rc != X86EMUL_CONTINUE)
1106 return rc;
0f65dd70
AK		 1107 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1108 &ctxt->exception);
3ca3ac4d
AK		 1109}
1110
1111static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1112 struct segmented_address addr,
1113 const void *orig_data, const void *data,
1114 unsigned size)
1115{
9fa088f4
AK		 1116 int rc;
1117 ulong linear;
1118
83b8795a 1119 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1120 if (rc != X86EMUL_CONTINUE)
1121 return rc;
0f65dd70
AK		 1122 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1123 size, &ctxt->exception);
3ca3ac4d
AK		 1124}
1125
dde7e6d1
AK		 1126static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1127 struct x86_emulate_ops *ops,
1128 unsigned int size, unsigned short port,
1129 void *dest)
1130{
1131 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1132
dde7e6d1
AK		 1133 if (rc->pos == rc->end) { /* refill pio read ahead */
1134 struct decode_cache *c = &ctxt->decode;
1135 unsigned int in_page, n;
1136 unsigned int count = c->rep_prefix ?
1137 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1138 in_page = (ctxt->eflags & EFLG_DF) ?
1139 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1140 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1141 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1142 count);
1143 if (n == 0)
1144 n = 1;
1145 rc->pos = rc->end = 0;
ca1d4a9e 1146 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1147 return 0;
1148 rc->end = n * size;
6aa8b732
AK		 1149 }
1150
dde7e6d1
AK		 1151 memcpy(dest, rc->data + rc->pos, size);
1152 rc->pos += size;
1153 return 1;
1154}
6aa8b732 1155
dde7e6d1
AK		 1156static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_ptr *dt)
1159{
1160 if (selector & 1 << 2) {
1161 struct desc_struct desc;
1aa36616
AK		 1162 u16 sel;
1163
dde7e6d1 1164 memset (dt, 0, sizeof *dt);
1aa36616 1165 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1166 return;
e09d082c 1167
dde7e6d1
AK		 1168 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1169 dt->address = get_desc_base(&desc);
1170 } else
4bff1e86 1171 ops->get_gdt(ctxt, dt);
dde7e6d1 1172}
120df890 1173
dde7e6d1
AK		 1174/* allowed just for 8 bytes segments */
1175static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1176 struct x86_emulate_ops *ops,
1177 u16 selector, struct desc_struct *desc)
1178{
1179 struct desc_ptr dt;
1180 u16 index = selector >> 3;
1181 int ret;
dde7e6d1 1182 ulong addr;
120df890 1183
dde7e6d1 1184 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1185
35d3d4a1
AK		 1186 if (dt.size < index * 8 + 7)
1187 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1188 addr = dt.address + index * 8;
0f65dd70 1189 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1190
dde7e6d1
AK		 1191 return ret;
1192}
ef65c889 1193
dde7e6d1
AK		 1194/* allowed just for 8 bytes segments */
1195static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1196 struct x86_emulate_ops *ops,
1197 u16 selector, struct desc_struct *desc)
1198{
1199 struct desc_ptr dt;
1200 u16 index = selector >> 3;
dde7e6d1
AK		 1201 ulong addr;
1202 int ret;
6aa8b732 1203
dde7e6d1 1204 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1205
35d3d4a1
AK		 1206 if (dt.size < index * 8 + 7)
1207 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1208
dde7e6d1 1209 addr = dt.address + index * 8;
0f65dd70 1210 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1211
dde7e6d1
AK		 1212 return ret;
1213}
c7e75a3d 1214
5601d05b 1215/* Does not support long mode */
dde7e6d1
AK		 1216static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1217 struct x86_emulate_ops *ops,
1218 u16 selector, int seg)
1219{
1220 struct desc_struct seg_desc;
1221 u8 dpl, rpl, cpl;
1222 unsigned err_vec = GP_VECTOR;
1223 u32 err_code = 0;
1224 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1225 int ret;
69f55cb1 1226
dde7e6d1 1227 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1228
dde7e6d1
AK		 1229 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1230 || ctxt->mode == X86EMUL_MODE_REAL) {
1231 /* set real mode segment descriptor */
1232 set_desc_base(&seg_desc, selector << 4);
1233 set_desc_limit(&seg_desc, 0xffff);
1234 seg_desc.type = 3;
1235 seg_desc.p = 1;
1236 seg_desc.s = 1;
1237 goto load;
1238 }
1239
1240 /* NULL selector is not valid for TR, CS and SS */
1241 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1242 && null_selector)
1243 goto exception;
1244
1245 /* TR should be in GDT only */
1246 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1247 goto exception;
1248
1249 if (null_selector) /* for NULL selector skip all following checks */
1250 goto load;
1251
1252 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1253 if (ret != X86EMUL_CONTINUE)
1254 return ret;
1255
1256 err_code = selector & 0xfffc;
1257 err_vec = GP_VECTOR;
1258
1259 /* can't load system descriptor into segment selecor */
1260 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1261 goto exception;
1262
1263 if (!seg_desc.p) {
1264 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1265 goto exception;
1266 }
1267
1268 rpl = selector & 3;
1269 dpl = seg_desc.dpl;
717746e3 1270 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1271
1272 switch (seg) {
1273 case VCPU_SREG_SS:
1274 /*
1275 * segment is not a writable data segment or segment
1276 * selector's RPL != CPL or segment selector's RPL != CPL
1277 */
1278 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1279 goto exception;
6aa8b732 1280 break;
dde7e6d1
AK		 1281 case VCPU_SREG_CS:
1282 if (!(seg_desc.type & 8))
1283 goto exception;
1284
1285 if (seg_desc.type & 4) {
1286 /* conforming */
1287 if (dpl > cpl)
1288 goto exception;
1289 } else {
1290 /* nonconforming */
1291 if (rpl > cpl || dpl != cpl)
1292 goto exception;
1293 }
1294 /* CS(RPL) <- CPL */
1295 selector = (selector & 0xfffc) | cpl;
6aa8b732 1296 break;
dde7e6d1
AK		 1297 case VCPU_SREG_TR:
1298 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1299 goto exception;
1300 break;
1301 case VCPU_SREG_LDTR:
1302 if (seg_desc.s || seg_desc.type != 2)
1303 goto exception;
1304 break;
1305 default: /* DS, ES, FS, or GS */
4e62417b 1306 /*
dde7e6d1
AK		 1307 * segment is not a data or readable code segment or
1308 * ((segment is a data or nonconforming code segment)
1309 * and (both RPL and CPL > DPL))
4e62417b 1310 */
dde7e6d1
AK		 1311 if ((seg_desc.type & 0xa) == 0x8 ||
1312 (((seg_desc.type & 0xc) != 0xc) &&
1313 (rpl > dpl && cpl > dpl)))
1314 goto exception;
6aa8b732 1315 break;
dde7e6d1
AK		 1316 }
1317
1318 if (seg_desc.s) {
1319 /* mark segment as accessed */
1320 seg_desc.type |= 1;
1321 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1322 if (ret != X86EMUL_CONTINUE)
1323 return ret;
1324 }
1325load:
1aa36616 1326 ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1327 return X86EMUL_CONTINUE;
1328exception:
1329 emulate_exception(ctxt, err_vec, err_code, true);
1330 return X86EMUL_PROPAGATE_FAULT;
1331}
1332
31be40b3
WY		 1333static void write_register_operand(struct operand *op)
1334{
1335 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1336 switch (op->bytes) {
1337 case 1:
1338 *(u8 *)op->addr.reg = (u8)op->val;
1339 break;
1340 case 2:
1341 *(u16 *)op->addr.reg = (u16)op->val;
1342 break;
1343 case 4:
1344 *op->addr.reg = (u32)op->val;
1345 break; /* 64b: zero-extend */
1346 case 8:
1347 *op->addr.reg = op->val;
1348 break;
1349 }
1350}
1351
adddcecf 1352static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1353{
1354 int rc;
1355 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1356
1357 switch (c->dst.type) {
1358 case OP_REG:
31be40b3 1359 write_register_operand(&c->dst);
6aa8b732 1360 break;
dde7e6d1
AK		 1361 case OP_MEM:
1362 if (c->lock_prefix)
3ca3ac4d
AK		 1363 rc = segmented_cmpxchg(ctxt,
1364 c->dst.addr.mem,
1365 &c->dst.orig_val,
1366 &c->dst.val,
1367 c->dst.bytes);
341de7e3 1368 else
3ca3ac4d
AK		 1369 rc = segmented_write(ctxt,
1370 c->dst.addr.mem,
1371 &c->dst.val,
1372 c->dst.bytes);
dde7e6d1
AK		 1373 if (rc != X86EMUL_CONTINUE)
1374 return rc;
a682e354 1375 break;
1253791d
AK		 1376 case OP_XMM:
1377 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1378 break;
dde7e6d1
AK		 1379 case OP_NONE:
1380 /* no writeback */
414e6277 1381 break;
dde7e6d1 1382 default:
414e6277 1383 break;
6aa8b732 1384 }
dde7e6d1
AK		 1385 return X86EMUL_CONTINUE;
1386}
6aa8b732 1387
4487b3b4 1388static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1389{
1390 struct decode_cache *c = &ctxt->decode;
4179bb02 1391 struct segmented_address addr;
0dc8d10f 1392
dde7e6d1 1393 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1394 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1395 addr.seg = VCPU_SREG_SS;
1396
1397 /* Disable writeback. */
1398 c->dst.type = OP_NONE;
1399 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1400}
69f55cb1 1401
dde7e6d1 1402static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1403 void *dest, int len)
1404{
1405 struct decode_cache *c = &ctxt->decode;
1406 int rc;
90de84f5 1407 struct segmented_address addr;
8b4caf66 1408
90de84f5
AK		 1409 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1410 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1411 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1412 if (rc != X86EMUL_CONTINUE)
1413 return rc;
1414
1415 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1416 return rc;
8b4caf66
LV		 1417}
1418
c54fe504
TY		 1419static int em_pop(struct x86_emulate_ctxt *ctxt)
1420{
1421 struct decode_cache *c = &ctxt->decode;
1422
3b9be3bf 1423 return emulate_pop(ctxt, &c->dst.val, c->op_bytes);
c54fe504
TY		 1424}
1425
dde7e6d1
AK		 1426static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1427 struct x86_emulate_ops *ops,
1428 void *dest, int len)
9de41573
GN		 1429{
1430 int rc;
dde7e6d1
AK		 1431 unsigned long val, change_mask;
1432 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1433 int cpl = ops->cpl(ctxt);
9de41573 1434
3b9be3bf 1435 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1436 if (rc != X86EMUL_CONTINUE)
1437 return rc;
9de41573 1438
dde7e6d1
AK		 1439 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1440 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1441
dde7e6d1
AK		 1442 switch(ctxt->mode) {
1443 case X86EMUL_MODE_PROT64:
1444 case X86EMUL_MODE_PROT32:
1445 case X86EMUL_MODE_PROT16:
1446 if (cpl == 0)
1447 change_mask |= EFLG_IOPL;
1448 if (cpl <= iopl)
1449 change_mask |= EFLG_IF;
1450 break;
1451 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1452 if (iopl < 3)
1453 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1454 change_mask |= EFLG_IF;
1455 break;
1456 default: /* real mode */
1457 change_mask |= (EFLG_IOPL | EFLG_IF);
1458 break;
9de41573 1459 }
dde7e6d1
AK		 1460
1461 *(unsigned long *)dest =
1462 (ctxt->eflags & ~change_mask) | (val & change_mask);
1463
1464 return rc;
9de41573
GN		 1465}
1466
62aaa2f0
TY		 1467static int em_popf(struct x86_emulate_ctxt *ctxt)
1468{
1469 struct decode_cache *c = &ctxt->decode;
1470
1471 c->dst.type = OP_REG;
1472 c->dst.addr.reg = &ctxt->eflags;
1473 c->dst.bytes = c->op_bytes;
1474 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1475}
1476
4179bb02
TY		 1477static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1478 struct x86_emulate_ops *ops, int seg)
7b262e90 1479{
dde7e6d1 1480 struct decode_cache *c = &ctxt->decode;
7b262e90 1481
1aa36616 1482 c->src.val = get_segment_selector(ctxt, seg);
7b262e90 1483
4487b3b4 1484 return em_push(ctxt);
7b262e90
GN		 1485}
1486
dde7e6d1
AK		 1487static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1488 struct x86_emulate_ops *ops, int seg)
38ba30ba 1489{
dde7e6d1
AK		 1490 struct decode_cache *c = &ctxt->decode;
1491 unsigned long selector;
1492 int rc;
38ba30ba 1493
3b9be3bf 1494 rc = emulate_pop(ctxt, &selector, c->op_bytes);
dde7e6d1
AK		 1495 if (rc != X86EMUL_CONTINUE)
1496 return rc;
1497
1498 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1499 return rc;
38ba30ba
GN		 1500}
1501
b96a7fad 1502static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1503{
dde7e6d1
AK		 1504 struct decode_cache *c = &ctxt->decode;
1505 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1506 int rc = X86EMUL_CONTINUE;
1507 int reg = VCPU_REGS_RAX;
38ba30ba 1508
dde7e6d1
AK		 1509 while (reg <= VCPU_REGS_RDI) {
1510 (reg == VCPU_REGS_RSP) ?
1511 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1512
4487b3b4 1513 rc = em_push(ctxt);
dde7e6d1
AK		 1514 if (rc != X86EMUL_CONTINUE)
1515 return rc;
38ba30ba 1516
dde7e6d1 1517 ++reg;
38ba30ba 1518 }
38ba30ba 1519
dde7e6d1 1520 return rc;
38ba30ba
GN		 1521}
1522
62aaa2f0
TY		 1523static int em_pushf(struct x86_emulate_ctxt *ctxt)
1524{
1525 struct decode_cache *c = &ctxt->decode;
1526
1527 c->src.val = (unsigned long)ctxt->eflags;
1528 return em_push(ctxt);
1529}
1530
b96a7fad 1531static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1532{
dde7e6d1
AK		 1533 struct decode_cache *c = &ctxt->decode;
1534 int rc = X86EMUL_CONTINUE;
1535 int reg = VCPU_REGS_RDI;
38ba30ba 1536
dde7e6d1
AK		 1537 while (reg >= VCPU_REGS_RAX) {
1538 if (reg == VCPU_REGS_RSP) {
1539 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1540 c->op_bytes);
1541 --reg;
1542 }
38ba30ba 1543
3b9be3bf 1544 rc = emulate_pop(ctxt, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1545 if (rc != X86EMUL_CONTINUE)
1546 break;
1547 --reg;
38ba30ba 1548 }
dde7e6d1 1549 return rc;
38ba30ba
GN		 1550}
1551
6e154e56
MG		 1552int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1553 struct x86_emulate_ops *ops, int irq)
1554{
1555 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1556 int rc;
6e154e56
MG		 1557 struct desc_ptr dt;
1558 gva_t cs_addr;
1559 gva_t eip_addr;
1560 u16 cs, eip;
6e154e56
MG		 1561
1562 /* TODO: Add limit checks */
1563 c->src.val = ctxt->eflags;
4487b3b4 1564 rc = em_push(ctxt);
5c56e1cf
AK		 1565 if (rc != X86EMUL_CONTINUE)
1566 return rc;
6e154e56
MG		 1567
1568 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1569
1aa36616 1570 c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1571 rc = em_push(ctxt);
5c56e1cf
AK		 1572 if (rc != X86EMUL_CONTINUE)
1573 return rc;
6e154e56
MG		 1574
1575 c->src.val = c->eip;
4487b3b4 1576 rc = em_push(ctxt);
5c56e1cf
AK		 1577 if (rc != X86EMUL_CONTINUE)
1578 return rc;
1579
4bff1e86 1580 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1581
1582 eip_addr = dt.address + (irq << 2);
1583 cs_addr = dt.address + (irq << 2) + 2;
1584
0f65dd70 1585 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
1588
0f65dd70 1589 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1590 if (rc != X86EMUL_CONTINUE)
1591 return rc;
1592
1593 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
1596
1597 c->eip = eip;
1598
1599 return rc;
1600}
1601
1602static int emulate_int(struct x86_emulate_ctxt *ctxt,
1603 struct x86_emulate_ops *ops, int irq)
1604{
1605 switch(ctxt->mode) {
1606 case X86EMUL_MODE_REAL:
1607 return emulate_int_real(ctxt, ops, irq);
1608 case X86EMUL_MODE_VM86:
1609 case X86EMUL_MODE_PROT16:
1610 case X86EMUL_MODE_PROT32:
1611 case X86EMUL_MODE_PROT64:
1612 default:
1613 /* Protected mode interrupts unimplemented yet */
1614 return X86EMUL_UNHANDLEABLE;
1615 }
1616}
1617
dde7e6d1
AK		 1618static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1619 struct x86_emulate_ops *ops)
38ba30ba 1620{
dde7e6d1
AK		 1621 struct decode_cache *c = &ctxt->decode;
1622 int rc = X86EMUL_CONTINUE;
1623 unsigned long temp_eip = 0;
1624 unsigned long temp_eflags = 0;
1625 unsigned long cs = 0;
1626 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1627 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1628 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1629 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1630
dde7e6d1 1631 /* TODO: Add stack limit check */
38ba30ba 1632
3b9be3bf 1633 rc = emulate_pop(ctxt, &temp_eip, c->op_bytes);
38ba30ba 1634
dde7e6d1
AK		 1635 if (rc != X86EMUL_CONTINUE)
1636 return rc;
38ba30ba 1637
35d3d4a1
AK		 1638 if (temp_eip & ~0xffff)
1639 return emulate_gp(ctxt, 0);
38ba30ba 1640
3b9be3bf 1641 rc = emulate_pop(ctxt, &cs, c->op_bytes);
38ba30ba 1642
dde7e6d1
AK		 1643 if (rc != X86EMUL_CONTINUE)
1644 return rc;
38ba30ba 1645
3b9be3bf 1646 rc = emulate_pop(ctxt, &temp_eflags, c->op_bytes);
38ba30ba 1647
dde7e6d1
AK		 1648 if (rc != X86EMUL_CONTINUE)
1649 return rc;
38ba30ba 1650
dde7e6d1 1651 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1652
dde7e6d1
AK		 1653 if (rc != X86EMUL_CONTINUE)
1654 return rc;
38ba30ba 1655
dde7e6d1 1656 c->eip = temp_eip;
38ba30ba 1657
38ba30ba 1658
dde7e6d1
AK		 1659 if (c->op_bytes == 4)
1660 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1661 else if (c->op_bytes == 2) {
1662 ctxt->eflags &= ~0xffff;
1663 ctxt->eflags |= temp_eflags;
38ba30ba 1664 }
dde7e6d1
AK		 1665
1666 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1667 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1668
1669 return rc;
38ba30ba
GN		 1670}
1671
dde7e6d1
AK		 1672static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1673 struct x86_emulate_ops* ops)
c37eda13 1674{
dde7e6d1
AK		 1675 switch(ctxt->mode) {
1676 case X86EMUL_MODE_REAL:
1677 return emulate_iret_real(ctxt, ops);
1678 case X86EMUL_MODE_VM86:
1679 case X86EMUL_MODE_PROT16:
1680 case X86EMUL_MODE_PROT32:
1681 case X86EMUL_MODE_PROT64:
c37eda13 1682 default:
dde7e6d1
AK		 1683 /* iret from protected mode unimplemented yet */
1684 return X86EMUL_UNHANDLEABLE;
c37eda13 1685 }
c37eda13
WY		 1686}
1687
d2f62766
TY		 1688static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1689{
1690 struct decode_cache *c = &ctxt->decode;
1691 int rc;
1692 unsigned short sel;
1693
1694 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1695
1696 rc = load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS);
1697 if (rc != X86EMUL_CONTINUE)
1698 return rc;
1699
1700 c->eip = 0;
1701 memcpy(&c->eip, c->src.valptr, c->op_bytes);
1702 return X86EMUL_CONTINUE;
1703}
1704
51187683 1705static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1706{
1707 struct decode_cache *c = &ctxt->decode;
1708
3b9be3bf 1709 return emulate_pop(ctxt, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1710}
1711
51187683 1712static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1713{
05f086f8 1714 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1715 switch (c->modrm_reg) {
1716 case 0: /* rol */
05f086f8 1717 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1718 break;
1719 case 1: /* ror */
05f086f8 1720 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1721 break;
1722 case 2: /* rcl */
05f086f8 1723 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1724 break;
1725 case 3: /* rcr */
05f086f8 1726 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1727 break;
1728 case 4: /* sal/shl */
1729 case 6: /* sal/shl */
05f086f8 1730 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1731 break;
1732 case 5: /* shr */
05f086f8 1733 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1734 break;
1735 case 7: /* sar */
05f086f8 1736 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1737 break;
1738 }
51187683 1739 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1740}
1741
51187683 1742static int em_grp3(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1743{
1744 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1745 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1746 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1747 u8 de = 0;
8cdbd2c9
LV		 1748
1749 switch (c->modrm_reg) {
1750 case 0 ... 1: /* test */
05f086f8 1751 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1752 break;
1753 case 2: /* not */
1754 c->dst.val = ~c->dst.val;
1755 break;
1756 case 3: /* neg */
05f086f8 1757 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1758 break;
3f9f53b0
MG		 1759 case 4: /* mul */
1760 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1761 break;
1762 case 5: /* imul */
1763 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1764 break;
1765 case 6: /* div */
34d1f490
AK		 1766 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1767 ctxt->eflags, de);
3f9f53b0
MG		 1768 break;
1769 case 7: /* idiv */
34d1f490
AK		 1770 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1771 ctxt->eflags, de);
3f9f53b0 1772 break;
8cdbd2c9 1773 default:
8c5eee30 1774 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1775 }
34d1f490
AK		 1776 if (de)
1777 return emulate_de(ctxt);
8c5eee30 1778 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1779}
1780
51187683 1781static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1782{
1783 struct decode_cache *c = &ctxt->decode;
4179bb02 1784 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1785
1786 switch (c->modrm_reg) {
1787 case 0: /* inc */
05f086f8 1788 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1789 break;
1790 case 1: /* dec */
05f086f8 1791 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1792 break;
d19292e4
MG		 1793 case 2: /* call near abs */ {
1794 long int old_eip;
1795 old_eip = c->eip;
1796 c->eip = c->src.val;
1797 c->src.val = old_eip;
4487b3b4 1798 rc = em_push(ctxt);
d19292e4
MG		 1799 break;
1800 }
8cdbd2c9 1801 case 4: /* jmp abs */
fd60754e 1802 c->eip = c->src.val;
8cdbd2c9 1803 break;
d2f62766
TY		 1804 case 5: /* jmp far */
1805 rc = em_jmp_far(ctxt);
1806 break;
8cdbd2c9 1807 case 6: /* push */
4487b3b4 1808 rc = em_push(ctxt);
8cdbd2c9 1809 break;
8cdbd2c9 1810 }
4179bb02 1811 return rc;
8cdbd2c9
LV		 1812}
1813
51187683 1814static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1815{
1816 struct decode_cache *c = &ctxt->decode;
16518d5a 1817 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1818
1819 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1820 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1821 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1822 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1823 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1824 } else {
16518d5a
AK		 1825 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1826 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1827
05f086f8 1828 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1829 }
1b30eaa8 1830 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1831}
1832
a77ab5ea
AK		 1833static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1834 struct x86_emulate_ops *ops)
1835{
1836 struct decode_cache *c = &ctxt->decode;
1837 int rc;
1838 unsigned long cs;
1839
3b9be3bf 1840 rc = emulate_pop(ctxt, &c->eip, c->op_bytes);
1b30eaa8 1841 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1842 return rc;
1843 if (c->op_bytes == 4)
1844 c->eip = (u32)c->eip;
3b9be3bf 1845 rc = emulate_pop(ctxt, &cs, c->op_bytes);
1b30eaa8 1846 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1847 return rc;
2e873022 1848 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1849 return rc;
1850}
1851
09b5f4d3
WY		 1852static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1853 struct x86_emulate_ops *ops, int seg)
1854{
1855 struct decode_cache *c = &ctxt->decode;
1856 unsigned short sel;
1857 int rc;
1858
1859 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1860
1861 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1862 if (rc != X86EMUL_CONTINUE)
1863 return rc;
1864
1865 c->dst.val = c->src.val;
1866 return rc;
1867}
1868
e66bb2cc
AP		 1869static inline void
1870setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1871 struct x86_emulate_ops *ops, struct desc_struct *cs,
1872 struct desc_struct *ss)
e66bb2cc 1873{
1aa36616
AK		 1874 u16 selector;
1875
79168fd1 1876 memset(cs, 0, sizeof(struct desc_struct));
1aa36616 1877 ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1878 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1879
1880 cs->l = 0; /* will be adjusted later */
79168fd1 1881 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1882 cs->g = 1; /* 4kb granularity */
79168fd1 1883 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1884 cs->type = 0x0b; /* Read, Execute, Accessed */
1885 cs->s = 1;
1886 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1887 cs->p = 1;
1888 cs->d = 1;
e66bb2cc 1889
79168fd1
GN		 1890 set_desc_base(ss, 0); /* flat segment */
1891 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1892 ss->g = 1; /* 4kb granularity */
1893 ss->s = 1;
1894 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1895 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1896 ss->dpl = 0;
79168fd1 1897 ss->p = 1;
e66bb2cc
AP		 1898}
1899
1900static int
3fb1b5db 1901emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1902{
1903 struct decode_cache *c = &ctxt->decode;
79168fd1 1904 struct desc_struct cs, ss;
e66bb2cc 1905 u64 msr_data;
79168fd1 1906 u16 cs_sel, ss_sel;
c2ad2bb3 1907 u64 efer = 0;
e66bb2cc
AP		 1908
1909 /* syscall is not available in real mode */
2e901c4c 1910 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1911 ctxt->mode == X86EMUL_MODE_VM86)
1912 return emulate_ud(ctxt);
e66bb2cc 1913
c2ad2bb3 1914 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1915 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1916
717746e3 1917 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1918 msr_data >>= 32;
79168fd1
GN		 1919 cs_sel = (u16)(msr_data & 0xfffc);
1920 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1921
c2ad2bb3 1922 if (efer & EFER_LMA) {
79168fd1 1923 cs.d = 0;
e66bb2cc
AP		 1924 cs.l = 1;
1925 }
1aa36616
AK		 1926 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1927 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc
AP		 1928
1929 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1930 if (efer & EFER_LMA) {
e66bb2cc
AP		 1931#ifdef CONFIG_X86_64
1932 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1933
717746e3 1934 ops->get_msr(ctxt,
3fb1b5db
GN		 1935 ctxt->mode == X86EMUL_MODE_PROT64 ?
1936 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1937 c->eip = msr_data;
1938
717746e3 1939 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1940 ctxt->eflags &= ~(msr_data | EFLG_RF);
1941#endif
1942 } else {
1943 /* legacy mode */
717746e3 1944 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1945 c->eip = (u32)msr_data;
1946
1947 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1948 }
1949
e54cfa97 1950 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1951}
1952
8c604352 1953static int
3fb1b5db 1954emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1955{
1956 struct decode_cache *c = &ctxt->decode;
79168fd1 1957 struct desc_struct cs, ss;
8c604352 1958 u64 msr_data;
79168fd1 1959 u16 cs_sel, ss_sel;
c2ad2bb3 1960 u64 efer = 0;
8c604352 1961
c2ad2bb3 1962 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1963 /* inject #GP if in real mode */
35d3d4a1
AK		 1964 if (ctxt->mode == X86EMUL_MODE_REAL)
1965 return emulate_gp(ctxt, 0);
8c604352
AP		 1966
1967 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1968 * Therefore, we inject an #UD.
1969 */
35d3d4a1
AK		 1970 if (ctxt->mode == X86EMUL_MODE_PROT64)
1971 return emulate_ud(ctxt);
8c604352 1972
79168fd1 1973 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1974
717746e3 1975 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1976 switch (ctxt->mode) {
1977 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1978 if ((msr_data & 0xfffc) == 0x0)
1979 return emulate_gp(ctxt, 0);
8c604352
AP		 1980 break;
1981 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1982 if (msr_data == 0x0)
1983 return emulate_gp(ctxt, 0);
8c604352
AP		 1984 break;
1985 }
1986
1987 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1988 cs_sel = (u16)msr_data;
1989 cs_sel &= ~SELECTOR_RPL_MASK;
1990 ss_sel = cs_sel + 8;
1991 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1992 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1993 cs.d = 0;
8c604352
AP		 1994 cs.l = 1;
1995 }
1996
1aa36616
AK		 1997 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1998 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1999
717746e3 2000 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2001 c->eip = msr_data;
2002
717746e3 2003 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2004 c->regs[VCPU_REGS_RSP] = msr_data;
2005
e54cfa97 2006 return X86EMUL_CONTINUE;
8c604352
AP		 2007}
2008
4668f050 2009static int
3fb1b5db 2010emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2011{
2012 struct decode_cache *c = &ctxt->decode;
79168fd1 2013 struct desc_struct cs, ss;
4668f050
AP		 2014 u64 msr_data;
2015 int usermode;
79168fd1 2016 u16 cs_sel, ss_sel;
4668f050 2017
a0044755
GN		 2018 /* inject #GP if in real mode or Virtual 8086 mode */
2019 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2020 ctxt->mode == X86EMUL_MODE_VM86)
2021 return emulate_gp(ctxt, 0);
4668f050 2022
79168fd1 2023 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2024
2025 if ((c->rex_prefix & 0x8) != 0x0)
2026 usermode = X86EMUL_MODE_PROT64;
2027 else
2028 usermode = X86EMUL_MODE_PROT32;
2029
2030 cs.dpl = 3;
2031 ss.dpl = 3;
717746e3 2032 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2033 switch (usermode) {
2034 case X86EMUL_MODE_PROT32:
79168fd1 2035 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2036 if ((msr_data & 0xfffc) == 0x0)
2037 return emulate_gp(ctxt, 0);
79168fd1 2038 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2039 break;
2040 case X86EMUL_MODE_PROT64:
79168fd1 2041 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2042 if (msr_data == 0x0)
2043 return emulate_gp(ctxt, 0);
79168fd1
GN		 2044 ss_sel = cs_sel + 8;
2045 cs.d = 0;
4668f050
AP		 2046 cs.l = 1;
2047 break;
2048 }
79168fd1
GN		 2049 cs_sel |= SELECTOR_RPL_MASK;
2050 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2051
1aa36616
AK		 2052 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2053 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2054
bdb475a3
GN		 2055 c->eip = c->regs[VCPU_REGS_RDX];
2056 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2057
e54cfa97 2058 return X86EMUL_CONTINUE;
4668f050
AP		 2059}
2060
9c537244
GN		 2061static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2062 struct x86_emulate_ops *ops)
f850e2e6
GN		 2063{
2064 int iopl;
2065 if (ctxt->mode == X86EMUL_MODE_REAL)
2066 return false;
2067 if (ctxt->mode == X86EMUL_MODE_VM86)
2068 return true;
2069 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2070 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2071}
2072
2073static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2074 struct x86_emulate_ops *ops,
2075 u16 port, u16 len)
2076{
79168fd1 2077 struct desc_struct tr_seg;
5601d05b 2078 u32 base3;
f850e2e6 2079 int r;
1aa36616 2080 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2081 unsigned mask = (1 << len) - 1;
5601d05b 2082 unsigned long base;
f850e2e6 2083
1aa36616 2084 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2085 if (!tr_seg.p)
f850e2e6 2086 return false;
79168fd1 2087 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2088 return false;
5601d05b
GN		 2089 base = get_desc_base(&tr_seg);
2090#ifdef CONFIG_X86_64
2091 base |= ((u64)base3) << 32;
2092#endif
0f65dd70 2093 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2094 if (r != X86EMUL_CONTINUE)
2095 return false;
79168fd1 2096 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2097 return false;
0f65dd70 2098 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2099 if (r != X86EMUL_CONTINUE)
2100 return false;
2101 if ((perm >> bit_idx) & mask)
2102 return false;
2103 return true;
2104}
2105
2106static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2107 struct x86_emulate_ops *ops,
2108 u16 port, u16 len)
2109{
4fc40f07
GN		 2110 if (ctxt->perm_ok)
2111 return true;
2112
9c537244 2113 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2114 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2115 return false;
4fc40f07
GN		 2116
2117 ctxt->perm_ok = true;
2118
f850e2e6
GN		 2119 return true;
2120}
2121
38ba30ba
GN		 2122static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2123 struct x86_emulate_ops *ops,
2124 struct tss_segment_16 *tss)
2125{
2126 struct decode_cache *c = &ctxt->decode;
2127
2128 tss->ip = c->eip;
2129 tss->flag = ctxt->eflags;
2130 tss->ax = c->regs[VCPU_REGS_RAX];
2131 tss->cx = c->regs[VCPU_REGS_RCX];
2132 tss->dx = c->regs[VCPU_REGS_RDX];
2133 tss->bx = c->regs[VCPU_REGS_RBX];
2134 tss->sp = c->regs[VCPU_REGS_RSP];
2135 tss->bp = c->regs[VCPU_REGS_RBP];
2136 tss->si = c->regs[VCPU_REGS_RSI];
2137 tss->di = c->regs[VCPU_REGS_RDI];
2138
1aa36616
AK		 2139 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2140 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2141 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2142 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2143 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2144}
2145
2146static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2147 struct x86_emulate_ops *ops,
2148 struct tss_segment_16 *tss)
2149{
2150 struct decode_cache *c = &ctxt->decode;
2151 int ret;
2152
2153 c->eip = tss->ip;
2154 ctxt->eflags = tss->flag | 2;
2155 c->regs[VCPU_REGS_RAX] = tss->ax;
2156 c->regs[VCPU_REGS_RCX] = tss->cx;
2157 c->regs[VCPU_REGS_RDX] = tss->dx;
2158 c->regs[VCPU_REGS_RBX] = tss->bx;
2159 c->regs[VCPU_REGS_RSP] = tss->sp;
2160 c->regs[VCPU_REGS_RBP] = tss->bp;
2161 c->regs[VCPU_REGS_RSI] = tss->si;
2162 c->regs[VCPU_REGS_RDI] = tss->di;
2163
2164 /*
2165 * SDM says that segment selectors are loaded before segment
2166 * descriptors
2167 */
1aa36616
AK		 2168 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2169 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2170 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2171 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2172 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2173
2174 /*
2175 * Now load segment descriptors. If fault happenes at this stage
2176 * it is handled in a context of new task
2177 */
2178 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2179 if (ret != X86EMUL_CONTINUE)
2180 return ret;
2181 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2182 if (ret != X86EMUL_CONTINUE)
2183 return ret;
2184 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2185 if (ret != X86EMUL_CONTINUE)
2186 return ret;
2187 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2188 if (ret != X86EMUL_CONTINUE)
2189 return ret;
2190 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2191 if (ret != X86EMUL_CONTINUE)
2192 return ret;
2193
2194 return X86EMUL_CONTINUE;
2195}
2196
2197static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2198 struct x86_emulate_ops *ops,
2199 u16 tss_selector, u16 old_tss_sel,
2200 ulong old_tss_base, struct desc_struct *new_desc)
2201{
2202 struct tss_segment_16 tss_seg;
2203 int ret;
bcc55cba 2204 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2205
0f65dd70 2206 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2207 &ctxt->exception);
db297e3d 2208 if (ret != X86EMUL_CONTINUE)
38ba30ba 2209 /* FIXME: need to provide precise fault address */
38ba30ba 2210 return ret;
38ba30ba
GN		 2211
2212 save_state_to_tss16(ctxt, ops, &tss_seg);
2213
0f65dd70 2214 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2215 &ctxt->exception);
db297e3d 2216 if (ret != X86EMUL_CONTINUE)
38ba30ba 2217 /* FIXME: need to provide precise fault address */
38ba30ba 2218 return ret;
38ba30ba 2219
0f65dd70 2220 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2221 &ctxt->exception);
db297e3d 2222 if (ret != X86EMUL_CONTINUE)
38ba30ba 2223 /* FIXME: need to provide precise fault address */
38ba30ba 2224 return ret;
38ba30ba
GN		 2225
2226 if (old_tss_sel != 0xffff) {
2227 tss_seg.prev_task_link = old_tss_sel;
2228
0f65dd70 2229 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2230 &tss_seg.prev_task_link,
2231 sizeof tss_seg.prev_task_link,
0f65dd70 2232 &ctxt->exception);
db297e3d 2233 if (ret != X86EMUL_CONTINUE)
38ba30ba 2234 /* FIXME: need to provide precise fault address */
38ba30ba 2235 return ret;
38ba30ba
GN		 2236 }
2237
2238 return load_state_from_tss16(ctxt, ops, &tss_seg);
2239}
2240
2241static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2242 struct x86_emulate_ops *ops,
2243 struct tss_segment_32 *tss)
2244{
2245 struct decode_cache *c = &ctxt->decode;
2246
717746e3 2247 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2248 tss->eip = c->eip;
2249 tss->eflags = ctxt->eflags;
2250 tss->eax = c->regs[VCPU_REGS_RAX];
2251 tss->ecx = c->regs[VCPU_REGS_RCX];
2252 tss->edx = c->regs[VCPU_REGS_RDX];
2253 tss->ebx = c->regs[VCPU_REGS_RBX];
2254 tss->esp = c->regs[VCPU_REGS_RSP];
2255 tss->ebp = c->regs[VCPU_REGS_RBP];
2256 tss->esi = c->regs[VCPU_REGS_RSI];
2257 tss->edi = c->regs[VCPU_REGS_RDI];
2258
1aa36616
AK		 2259 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2260 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2261 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2262 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2263 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2264 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2265 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2266}
2267
2268static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2269 struct x86_emulate_ops *ops,
2270 struct tss_segment_32 *tss)
2271{
2272 struct decode_cache *c = &ctxt->decode;
2273 int ret;
2274
717746e3 2275 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2276 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2277 c->eip = tss->eip;
2278 ctxt->eflags = tss->eflags | 2;
2279 c->regs[VCPU_REGS_RAX] = tss->eax;
2280 c->regs[VCPU_REGS_RCX] = tss->ecx;
2281 c->regs[VCPU_REGS_RDX] = tss->edx;
2282 c->regs[VCPU_REGS_RBX] = tss->ebx;
2283 c->regs[VCPU_REGS_RSP] = tss->esp;
2284 c->regs[VCPU_REGS_RBP] = tss->ebp;
2285 c->regs[VCPU_REGS_RSI] = tss->esi;
2286 c->regs[VCPU_REGS_RDI] = tss->edi;
2287
2288 /*
2289 * SDM says that segment selectors are loaded before segment
2290 * descriptors
2291 */
1aa36616
AK		 2292 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2293 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2294 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2295 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2296 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2297 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2298 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2299
2300 /*
2301 * Now load segment descriptors. If fault happenes at this stage
2302 * it is handled in a context of new task
2303 */
2304 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2308 if (ret != X86EMUL_CONTINUE)
2309 return ret;
2310 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2311 if (ret != X86EMUL_CONTINUE)
2312 return ret;
2313 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2314 if (ret != X86EMUL_CONTINUE)
2315 return ret;
2316 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2317 if (ret != X86EMUL_CONTINUE)
2318 return ret;
2319 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2320 if (ret != X86EMUL_CONTINUE)
2321 return ret;
2322 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2323 if (ret != X86EMUL_CONTINUE)
2324 return ret;
2325
2326 return X86EMUL_CONTINUE;
2327}
2328
2329static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2330 struct x86_emulate_ops *ops,
2331 u16 tss_selector, u16 old_tss_sel,
2332 ulong old_tss_base, struct desc_struct *new_desc)
2333{
2334 struct tss_segment_32 tss_seg;
2335 int ret;
bcc55cba 2336 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2337
0f65dd70 2338 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2339 &ctxt->exception);
db297e3d 2340 if (ret != X86EMUL_CONTINUE)
38ba30ba 2341 /* FIXME: need to provide precise fault address */
38ba30ba 2342 return ret;
38ba30ba
GN		 2343
2344 save_state_to_tss32(ctxt, ops, &tss_seg);
2345
0f65dd70 2346 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2347 &ctxt->exception);
db297e3d 2348 if (ret != X86EMUL_CONTINUE)
38ba30ba 2349 /* FIXME: need to provide precise fault address */
38ba30ba 2350 return ret;
38ba30ba 2351
0f65dd70 2352 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2353 &ctxt->exception);
db297e3d 2354 if (ret != X86EMUL_CONTINUE)
38ba30ba 2355 /* FIXME: need to provide precise fault address */
38ba30ba 2356 return ret;
38ba30ba
GN		 2357
2358 if (old_tss_sel != 0xffff) {
2359 tss_seg.prev_task_link = old_tss_sel;
2360
0f65dd70 2361 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2362 &tss_seg.prev_task_link,
2363 sizeof tss_seg.prev_task_link,
0f65dd70 2364 &ctxt->exception);
db297e3d 2365 if (ret != X86EMUL_CONTINUE)
38ba30ba 2366 /* FIXME: need to provide precise fault address */
38ba30ba 2367 return ret;
38ba30ba
GN		 2368 }
2369
2370 return load_state_from_tss32(ctxt, ops, &tss_seg);
2371}
2372
2373static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2374 struct x86_emulate_ops *ops,
2375 u16 tss_selector, int reason,
2376 bool has_error_code, u32 error_code)
38ba30ba
GN		 2377{
2378 struct desc_struct curr_tss_desc, next_tss_desc;
2379 int ret;
1aa36616 2380 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2381 ulong old_tss_base =
4bff1e86 2382 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2383 u32 desc_limit;
38ba30ba
GN		 2384
2385 /* FIXME: old_tss_base == ~0 ? */
2386
2387 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2388 if (ret != X86EMUL_CONTINUE)
2389 return ret;
2390 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2391 if (ret != X86EMUL_CONTINUE)
2392 return ret;
2393
2394 /* FIXME: check that next_tss_desc is tss */
2395
2396 if (reason != TASK_SWITCH_IRET) {
2397 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2398 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2399 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2400 }
2401
ceffb459
GN		 2402 desc_limit = desc_limit_scaled(&next_tss_desc);
2403 if (!next_tss_desc.p ||
2404 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2405 desc_limit < 0x2b)) {
54b8486f 2406 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2407 return X86EMUL_PROPAGATE_FAULT;
2408 }
2409
2410 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2411 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2412 write_segment_descriptor(ctxt, ops, old_tss_sel,
2413 &curr_tss_desc);
2414 }
2415
2416 if (reason == TASK_SWITCH_IRET)
2417 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2418
2419 /* set back link to prev task only if NT bit is set in eflags
2420 note that old_tss_sel is not used afetr this point */
2421 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2422 old_tss_sel = 0xffff;
2423
2424 if (next_tss_desc.type & 8)
2425 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2426 old_tss_base, &next_tss_desc);
2427 else
2428 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2429 old_tss_base, &next_tss_desc);
0760d448
JK		 2430 if (ret != X86EMUL_CONTINUE)
2431 return ret;
38ba30ba
GN		 2432
2433 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2434 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2435
2436 if (reason != TASK_SWITCH_IRET) {
2437 next_tss_desc.type |= (1 << 1); /* set busy flag */
2438 write_segment_descriptor(ctxt, ops, tss_selector,
2439 &next_tss_desc);
2440 }
2441
717746e3 2442 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2443 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2444
e269fb21
JK		 2445 if (has_error_code) {
2446 struct decode_cache *c = &ctxt->decode;
2447
2448 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2449 c->lock_prefix = 0;
2450 c->src.val = (unsigned long) error_code;
4487b3b4 2451 ret = em_push(ctxt);
e269fb21
JK		 2452 }
2453
38ba30ba
GN		 2454 return ret;
2455}
2456
2457int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2458 u16 tss_selector, int reason,
2459 bool has_error_code, u32 error_code)
38ba30ba 2460{
9aabc88f 2461 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2462 struct decode_cache *c = &ctxt->decode;
2463 int rc;
2464
38ba30ba 2465 c->eip = ctxt->eip;
e269fb21 2466 c->dst.type = OP_NONE;
38ba30ba 2467
e269fb21
JK		 2468 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2469 has_error_code, error_code);
38ba30ba 2470
4179bb02
TY		 2471 if (rc == X86EMUL_CONTINUE)
2472 ctxt->eip = c->eip;
38ba30ba 2473
a0c0ab2f 2474 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2475}
2476
90de84f5 2477static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2478 int reg, struct operand *op)
a682e354
GN		 2479{
2480 struct decode_cache *c = &ctxt->decode;
2481 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2482
d9271123 2483 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2484 op->addr.mem.ea = register_address(c, c->regs[reg]);
2485 op->addr.mem.seg = seg;
a682e354
GN		 2486}
2487
7af04fc0
AK		 2488static int em_das(struct x86_emulate_ctxt *ctxt)
2489{
2490 struct decode_cache *c = &ctxt->decode;
2491 u8 al, old_al;
2492 bool af, cf, old_cf;
2493
2494 cf = ctxt->eflags & X86_EFLAGS_CF;
2495 al = c->dst.val;
2496
2497 old_al = al;
2498 old_cf = cf;
2499 cf = false;
2500 af = ctxt->eflags & X86_EFLAGS_AF;
2501 if ((al & 0x0f) > 9 || af) {
2502 al -= 6;
2503 cf = old_cf | (al >= 250);
2504 af = true;
2505 } else {
2506 af = false;
2507 }
2508 if (old_al > 0x99 || old_cf) {
2509 al -= 0x60;
2510 cf = true;
2511 }
2512
2513 c->dst.val = al;
2514 /* Set PF, ZF, SF */
2515 c->src.type = OP_IMM;
2516 c->src.val = 0;
2517 c->src.bytes = 1;
2518 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2519 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2520 if (cf)
2521 ctxt->eflags |= X86_EFLAGS_CF;
2522 if (af)
2523 ctxt->eflags |= X86_EFLAGS_AF;
2524 return X86EMUL_CONTINUE;
2525}
2526
0ef753b8
AK		 2527static int em_call_far(struct x86_emulate_ctxt *ctxt)
2528{
2529 struct decode_cache *c = &ctxt->decode;
2530 u16 sel, old_cs;
2531 ulong old_eip;
2532 int rc;
2533
1aa36616 2534 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2535 old_eip = c->eip;
2536
2537 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2538 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2539 return X86EMUL_CONTINUE;
2540
2541 c->eip = 0;
2542 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2543
2544 c->src.val = old_cs;
4487b3b4 2545 rc = em_push(ctxt);
0ef753b8
AK		 2546 if (rc != X86EMUL_CONTINUE)
2547 return rc;
2548
2549 c->src.val = old_eip;
4487b3b4 2550 return em_push(ctxt);
0ef753b8
AK		 2551}
2552
40ece7c7
AK		 2553static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2554{
2555 struct decode_cache *c = &ctxt->decode;
2556 int rc;
2557
2558 c->dst.type = OP_REG;
2559 c->dst.addr.reg = &c->eip;
2560 c->dst.bytes = c->op_bytes;
3b9be3bf 2561 rc = emulate_pop(ctxt, &c->dst.val, c->op_bytes);
40ece7c7
AK		 2562 if (rc != X86EMUL_CONTINUE)
2563 return rc;
2564 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2565 return X86EMUL_CONTINUE;
2566}
2567
d67fc27a
TY		 2568static int em_add(struct x86_emulate_ctxt *ctxt)
2569{
2570 struct decode_cache *c = &ctxt->decode;
2571
2572 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2573 return X86EMUL_CONTINUE;
2574}
2575
2576static int em_or(struct x86_emulate_ctxt *ctxt)
2577{
2578 struct decode_cache *c = &ctxt->decode;
2579
2580 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2581 return X86EMUL_CONTINUE;
2582}
2583
2584static int em_adc(struct x86_emulate_ctxt *ctxt)
2585{
2586 struct decode_cache *c = &ctxt->decode;
2587
2588 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2589 return X86EMUL_CONTINUE;
2590}
2591
2592static int em_sbb(struct x86_emulate_ctxt *ctxt)
2593{
2594 struct decode_cache *c = &ctxt->decode;
2595
2596 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2597 return X86EMUL_CONTINUE;
2598}
2599
2600static int em_and(struct x86_emulate_ctxt *ctxt)
2601{
2602 struct decode_cache *c = &ctxt->decode;
2603
2604 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2605 return X86EMUL_CONTINUE;
2606}
2607
2608static int em_sub(struct x86_emulate_ctxt *ctxt)
2609{
2610 struct decode_cache *c = &ctxt->decode;
2611
2612 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2613 return X86EMUL_CONTINUE;
2614}
2615
2616static int em_xor(struct x86_emulate_ctxt *ctxt)
2617{
2618 struct decode_cache *c = &ctxt->decode;
2619
2620 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2621 return X86EMUL_CONTINUE;
2622}
2623
2624static int em_cmp(struct x86_emulate_ctxt *ctxt)
2625{
2626 struct decode_cache *c = &ctxt->decode;
2627
2628 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2629 /* Disable writeback. */
2630 c->dst.type = OP_NONE;
2631 return X86EMUL_CONTINUE;
2632}
2633
5c82aa29 2634static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2635{
2636 struct decode_cache *c = &ctxt->decode;
2637
f3a1b9f4
AK		 2638 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2639 return X86EMUL_CONTINUE;
2640}
2641
5c82aa29
AK		 2642static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2643{
2644 struct decode_cache *c = &ctxt->decode;
2645
2646 c->dst.val = c->src2.val;
2647 return em_imul(ctxt);
2648}
2649
61429142
AK		 2650static int em_cwd(struct x86_emulate_ctxt *ctxt)
2651{
2652 struct decode_cache *c = &ctxt->decode;
2653
2654 c->dst.type = OP_REG;
2655 c->dst.bytes = c->src.bytes;
2656 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2657 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2658
2659 return X86EMUL_CONTINUE;
2660}
2661
48bb5d3c
AK		 2662static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2663{
48bb5d3c
AK		 2664 struct decode_cache *c = &ctxt->decode;
2665 u64 tsc = 0;
2666
717746e3 2667 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2668 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2669 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2670 return X86EMUL_CONTINUE;
2671}
2672
b9eac5f4
AK		 2673static int em_mov(struct x86_emulate_ctxt *ctxt)
2674{
2675 struct decode_cache *c = &ctxt->decode;
2676 c->dst.val = c->src.val;
2677 return X86EMUL_CONTINUE;
2678}
2679
aa97bb48
AK		 2680static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2681{
2682 struct decode_cache *c = &ctxt->decode;
2683 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2684 return X86EMUL_CONTINUE;
2685}
2686
38503911
AK		 2687static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2688{
2689 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2690 int rc;
2691 ulong linear;
2692
83b8795a 2693 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2694 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2695 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2696 /* Disable writeback. */
2697 c->dst.type = OP_NONE;
2698 return X86EMUL_CONTINUE;
2699}
2700
2d04a05b
AK		 2701static int em_clts(struct x86_emulate_ctxt *ctxt)
2702{
2703 ulong cr0;
2704
2705 cr0 = ctxt->ops->get_cr(ctxt, 0);
2706 cr0 &= ~X86_CR0_TS;
2707 ctxt->ops->set_cr(ctxt, 0, cr0);
2708 return X86EMUL_CONTINUE;
2709}
2710
26d05cc7
AK		 2711static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2712{
2713 struct decode_cache *c = &ctxt->decode;
2714 int rc;
2715
2716 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2717 return X86EMUL_UNHANDLEABLE;
2718
2719 rc = ctxt->ops->fix_hypercall(ctxt);
2720 if (rc != X86EMUL_CONTINUE)
2721 return rc;
2722
2723 /* Let the processor re-execute the fixed hypercall */
2724 c->eip = ctxt->eip;
2725 /* Disable writeback. */
2726 c->dst.type = OP_NONE;
2727 return X86EMUL_CONTINUE;
2728}
2729
2730static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2731{
2732 struct decode_cache *c = &ctxt->decode;
2733 struct desc_ptr desc_ptr;
2734 int rc;
2735
509cf9fe 2736 rc = read_descriptor(ctxt, c->src.addr.mem,
26d05cc7
AK		 2737 &desc_ptr.size, &desc_ptr.address,
2738 c->op_bytes);
2739 if (rc != X86EMUL_CONTINUE)
2740 return rc;
2741 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2742 /* Disable writeback. */
2743 c->dst.type = OP_NONE;
2744 return X86EMUL_CONTINUE;
2745}
2746
5ef39c71 2747static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2748{
2749 struct decode_cache *c = &ctxt->decode;
2750 int rc;
2751
5ef39c71
AK		 2752 rc = ctxt->ops->fix_hypercall(ctxt);
2753
26d05cc7
AK		 2754 /* Disable writeback. */
2755 c->dst.type = OP_NONE;
2756 return rc;
2757}
2758
2759static int em_lidt(struct x86_emulate_ctxt *ctxt)
2760{
2761 struct decode_cache *c = &ctxt->decode;
2762 struct desc_ptr desc_ptr;
2763 int rc;
2764
509cf9fe
TY		 2765 rc = read_descriptor(ctxt, c->src.addr.mem,
2766 &desc_ptr.size, &desc_ptr.address,
26d05cc7
AK		 2767 c->op_bytes);
2768 if (rc != X86EMUL_CONTINUE)
2769 return rc;
2770 ctxt->ops->set_idt(ctxt, &desc_ptr);
2771 /* Disable writeback. */
2772 c->dst.type = OP_NONE;
2773 return X86EMUL_CONTINUE;
2774}
2775
2776static int em_smsw(struct x86_emulate_ctxt *ctxt)
2777{
2778 struct decode_cache *c = &ctxt->decode;
2779
2780 c->dst.bytes = 2;
2781 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2782 return X86EMUL_CONTINUE;
2783}
2784
2785static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2786{
2787 struct decode_cache *c = &ctxt->decode;
2788 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2789 | (c->src.val & 0x0f));
2790 c->dst.type = OP_NONE;
2791 return X86EMUL_CONTINUE;
2792}
2793
cfec82cb
JR		 2794static bool valid_cr(int nr)
2795{
2796 switch (nr) {
2797 case 0:
2798 case 2 ... 4:
2799 case 8:
2800 return true;
2801 default:
2802 return false;
2803 }
2804}
2805
2806static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2807{
2808 struct decode_cache *c = &ctxt->decode;
2809
2810 if (!valid_cr(c->modrm_reg))
2811 return emulate_ud(ctxt);
2812
2813 return X86EMUL_CONTINUE;
2814}
2815
2816static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2817{
2818 struct decode_cache *c = &ctxt->decode;
2819 u64 new_val = c->src.val64;
2820 int cr = c->modrm_reg;
c2ad2bb3 2821 u64 efer = 0;
cfec82cb
JR		 2822
2823 static u64 cr_reserved_bits[] = {
2824 0xffffffff00000000ULL,
2825 0, 0, 0, /* CR3 checked later */
2826 CR4_RESERVED_BITS,
2827 0, 0, 0,
2828 CR8_RESERVED_BITS,
2829 };
2830
2831 if (!valid_cr(cr))
2832 return emulate_ud(ctxt);
2833
2834 if (new_val & cr_reserved_bits[cr])
2835 return emulate_gp(ctxt, 0);
2836
2837 switch (cr) {
2838 case 0: {
c2ad2bb3 2839 u64 cr4;
cfec82cb
JR		 2840 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2841 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2842 return emulate_gp(ctxt, 0);
2843
717746e3
AK		 2844 cr4 = ctxt->ops->get_cr(ctxt, 4);
2845 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2846
2847 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2848 !(cr4 & X86_CR4_PAE))
2849 return emulate_gp(ctxt, 0);
2850
2851 break;
2852 }
2853 case 3: {
2854 u64 rsvd = 0;
2855
c2ad2bb3
AK		 2856 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2857 if (efer & EFER_LMA)
cfec82cb 2858 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2859 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2860 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2861 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2862 rsvd = CR3_NONPAE_RESERVED_BITS;
2863
2864 if (new_val & rsvd)
2865 return emulate_gp(ctxt, 0);
2866
2867 break;
2868 }
2869 case 4: {
c2ad2bb3 2870 u64 cr4;
cfec82cb 2871
717746e3
AK		 2872 cr4 = ctxt->ops->get_cr(ctxt, 4);
2873 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2874
2875 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2876 return emulate_gp(ctxt, 0);
2877
2878 break;
2879 }
2880 }
2881
2882 return X86EMUL_CONTINUE;
2883}
2884
3b88e41a
JR		 2885static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2886{
2887 unsigned long dr7;
2888
717746e3 2889 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2890
2891 /* Check if DR7.Global_Enable is set */
2892 return dr7 & (1 << 13);
2893}
2894
2895static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2896{
2897 struct decode_cache *c = &ctxt->decode;
2898 int dr = c->modrm_reg;
2899 u64 cr4;
2900
2901 if (dr > 7)
2902 return emulate_ud(ctxt);
2903
717746e3 2904 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2905 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2906 return emulate_ud(ctxt);
2907
2908 if (check_dr7_gd(ctxt))
2909 return emulate_db(ctxt);
2910
2911 return X86EMUL_CONTINUE;
2912}
2913
2914static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2915{
2916 struct decode_cache *c = &ctxt->decode;
2917 u64 new_val = c->src.val64;
2918 int dr = c->modrm_reg;
2919
2920 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2921 return emulate_gp(ctxt, 0);
2922
2923 return check_dr_read(ctxt);
2924}
2925
01de8b09
JR		 2926static int check_svme(struct x86_emulate_ctxt *ctxt)
2927{
2928 u64 efer;
2929
717746e3 2930 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2931
2932 if (!(efer & EFER_SVME))
2933 return emulate_ud(ctxt);
2934
2935 return X86EMUL_CONTINUE;
2936}
2937
2938static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2939{
fe870ab9 2940 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2941
2942 /* Valid physical address? */
d4224449 2943 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2944 return emulate_gp(ctxt, 0);
2945
2946 return check_svme(ctxt);
2947}
2948
d7eb8203
JR		 2949static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2950{
717746e3 2951 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2952
717746e3 2953 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2954 return emulate_ud(ctxt);
2955
2956 return X86EMUL_CONTINUE;
2957}
2958
8061252e
JR		 2959static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2960{
717746e3 2961 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2962 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2963
717746e3 2964 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2965 (rcx > 3))
2966 return emulate_gp(ctxt, 0);
2967
2968 return X86EMUL_CONTINUE;
2969}
2970
f6511935
JR		 2971static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2972{
2973 struct decode_cache *c = &ctxt->decode;
2974
2975 c->dst.bytes = min(c->dst.bytes, 4u);
2976 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2977 return emulate_gp(ctxt, 0);
2978
2979 return X86EMUL_CONTINUE;
2980}
2981
2982static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2983{
2984 struct decode_cache *c = &ctxt->decode;
2985
2986 c->src.bytes = min(c->src.bytes, 4u);
2987 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2988 return emulate_gp(ctxt, 0);
2989
2990 return X86EMUL_CONTINUE;
2991}
2992
73fba5f4 2993#define D(_y) { .flags = (_y) }
c4f035c6 2994#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2995#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2996 .check_perm = (_p) }
73fba5f4 2997#define N D(0)
01de8b09 2998#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2999#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3000#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3001#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3002#define II(_f, _e, _i) \
3003 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3004#define IIP(_f, _e, _i, _p) \
3005 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3006 .check_perm = (_p) }
aa97bb48 3007#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3008
8d8f4e9f 3009#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3010#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 3011#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3012
d67fc27a
TY		 3013#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3014 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3015 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3016
d7eb8203
JR		 3017static struct opcode group7_rm1[] = {
3018 DI(SrcNone | ModRM | Priv, monitor),
3019 DI(SrcNone | ModRM | Priv, mwait),
3020 N, N, N, N, N, N,
3021};
3022
01de8b09
JR		 3023static struct opcode group7_rm3[] = {
3024 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3025 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3026 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3027 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3028 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3029 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3030 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3031 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3032};
6230f7fc 3033
d7eb8203
JR		 3034static struct opcode group7_rm7[] = {
3035 N,
3036 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3037 N, N, N, N, N, N,
3038};
d67fc27a 3039
73fba5f4 3040static struct opcode group1[] = {
d67fc27a
TY		 3041 I(Lock, em_add),
3042 I(Lock, em_or),
3043 I(Lock, em_adc),
3044 I(Lock, em_sbb),
3045 I(Lock, em_and),
3046 I(Lock, em_sub),
3047 I(Lock, em_xor),
3048 I(0, em_cmp),
73fba5f4
AK		 3049};
3050
3051static struct opcode group1A[] = {
3052 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3053};
3054
3055static struct opcode group3[] = {
3056 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3057 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3058 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3059};
3060
3061static struct opcode group4[] = {
3062 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3063 N, N, N, N, N, N,
3064};
3065
3066static struct opcode group5[] = {
3067 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3068 D(SrcMem | ModRM | Stack),
3069 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3070 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3071 D(SrcMem | ModRM | Stack), N,
3072};
3073
dee6bb70
JR		 3074static struct opcode group6[] = {
3075 DI(ModRM | Prot, sldt),
3076 DI(ModRM | Prot, str),
3077 DI(ModRM | Prot | Priv, lldt),
3078 DI(ModRM | Prot | Priv, ltr),
3079 N, N, N, N,
3080};
3081
73fba5f4 3082static struct group_dual group7 = { {
dee6bb70
JR		 3083 DI(ModRM | Mov | DstMem | Priv, sgdt),
3084 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3085 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3086 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3087 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3088 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3089 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3090}, {
5ef39c71
AK		 3091 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3092 EXT(0, group7_rm1),
01de8b09 3093 N, EXT(0, group7_rm3),
5ef39c71
AK		 3094 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3095 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3096} };
3097
3098static struct opcode group8[] = {
3099 N, N, N, N,
3100 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3101 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3102};
3103
3104static struct group_dual group9 = { {
3105 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3106}, {
3107 N, N, N, N, N, N, N, N,
3108} };
3109
a4d4a7c1
AK		 3110static struct opcode group11[] = {
3111 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3112};
3113
aa97bb48
AK		 3114static struct gprefix pfx_0f_6f_0f_7f = {
3115 N, N, N, I(Sse, em_movdqu),
3116};
3117
73fba5f4
AK		 3118static struct opcode opcode_table[256] = {
3119 /* 0x00 - 0x07 */
d67fc27a 3120 I6ALU(Lock, em_add),
73fba5f4
AK		 3121 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3122 /* 0x08 - 0x0F */
d67fc27a 3123 I6ALU(Lock, em_or),
73fba5f4
AK		 3124 D(ImplicitOps | Stack | No64), N,
3125 /* 0x10 - 0x17 */
d67fc27a 3126 I6ALU(Lock, em_adc),
73fba5f4
AK		 3127 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3128 /* 0x18 - 0x1F */
d67fc27a 3129 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3130 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3131 /* 0x20 - 0x27 */
d67fc27a 3132 I6ALU(Lock, em_and), N, N,
73fba5f4 3133 /* 0x28 - 0x2F */
d67fc27a 3134 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3135 /* 0x30 - 0x37 */
d67fc27a 3136 I6ALU(Lock, em_xor), N, N,
73fba5f4 3137 /* 0x38 - 0x3F */
d67fc27a 3138 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3139 /* 0x40 - 0x4F */
3140 X16(D(DstReg)),
3141 /* 0x50 - 0x57 */
63540382 3142 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3143 /* 0x58 - 0x5F */
c54fe504 3144 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3145 /* 0x60 - 0x67 */
b96a7fad
TY		 3146 I(ImplicitOps | Stack | No64, em_pusha),
3147 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3148 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3149 N, N, N, N,
3150 /* 0x68 - 0x6F */
d46164db
AK		 3151 I(SrcImm | Mov | Stack, em_push),
3152 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3153 I(SrcImmByte | Mov | Stack, em_push),
3154 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3155 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3156 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3157 /* 0x70 - 0x7F */
3158 X16(D(SrcImmByte)),
3159 /* 0x80 - 0x87 */
3160 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3161 G(DstMem | SrcImm | ModRM | Group, group1),
3162 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3163 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3164 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3165 /* 0x88 - 0x8F */
b9eac5f4
AK		 3166 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3167 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3168 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3169 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3170 /* 0x90 - 0x97 */
bf608f88 3171 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3172 /* 0x98 - 0x9F */
61429142 3173 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3174 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3175 II(ImplicitOps | Stack, em_pushf, pushf),
3176 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3177 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3178 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3179 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3180 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3181 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3182 /* 0xA8 - 0xAF */
50748613 3183 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3184 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3185 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3186 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3187 /* 0xB0 - 0xB7 */
b9eac5f4 3188 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3189 /* 0xB8 - 0xBF */
b9eac5f4 3190 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3191 /* 0xC0 - 0xC7 */
d2c6c7ad 3192 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3193 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3194 D(ImplicitOps | Stack),
09b5f4d3 3195 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3196 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3197 /* 0xC8 - 0xCF */
3198 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3199 D(ImplicitOps), DI(SrcImmByte, intn),
3200 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3201 /* 0xD0 - 0xD7 */
d2c6c7ad 3202 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3203 N, N, N, N,
3204 /* 0xD8 - 0xDF */
3205 N, N, N, N, N, N, N, N,
3206 /* 0xE0 - 0xE7 */
e4abac67 3207 X4(D(SrcImmByte)),
f6511935
JR		 3208 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3209 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3210 /* 0xE8 - 0xEF */
3211 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3212 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3213 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3214 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3215 /* 0xF0 - 0xF7 */
bf608f88 3216 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3217 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3218 G(ByteOp, group3), G(0, group3),
73fba5f4 3219 /* 0xF8 - 0xFF */
8744aa9a 3220 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3221 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3222};
3223
3224static struct opcode twobyte_table[256] = {
3225 /* 0x00 - 0x0F */
dee6bb70 3226 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3227 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3228 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3229 N, D(ImplicitOps | ModRM), N, N,
3230 /* 0x10 - 0x1F */
3231 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3232 /* 0x20 - 0x2F */
cfec82cb 3233 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3234 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3235 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3236 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3237 N, N, N, N,
3238 N, N, N, N, N, N, N, N,
3239 /* 0x30 - 0x3F */
8061252e
JR		 3240 DI(ImplicitOps | Priv, wrmsr),
3241 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3242 DI(ImplicitOps | Priv, rdmsr),
3243 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3244 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3245 N, N,
73fba5f4
AK		 3246 N, N, N, N, N, N, N, N,
3247 /* 0x40 - 0x4F */
3248 X16(D(DstReg | SrcMem | ModRM | Mov)),
3249 /* 0x50 - 0x5F */
3250 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3251 /* 0x60 - 0x6F */
aa97bb48
AK		 3252 N, N, N, N,
3253 N, N, N, N,
3254 N, N, N, N,
3255 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3256 /* 0x70 - 0x7F */
aa97bb48
AK		 3257 N, N, N, N,
3258 N, N, N, N,
3259 N, N, N, N,
3260 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3261 /* 0x80 - 0x8F */
3262 X16(D(SrcImm)),
3263 /* 0x90 - 0x9F */
ee45b58e 3264 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3265 /* 0xA0 - 0xA7 */
3266 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3267 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3268 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3269 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3270 /* 0xA8 - 0xAF */
3271 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3272 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3273 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3274 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3275 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3276 /* 0xB0 - 0xB7 */
739ae406 3277 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3278 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3279 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3280 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3281 /* 0xB8 - 0xBF */
3282 N, N,
ba7ff2b7 3283 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3284 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3285 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3286 /* 0xC0 - 0xCF */
739ae406 3287 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3288 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3289 N, N, N, GD(0, &group9),
3290 N, N, N, N, N, N, N, N,
3291 /* 0xD0 - 0xDF */
3292 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3293 /* 0xE0 - 0xEF */
3294 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3295 /* 0xF0 - 0xFF */
3296 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3297};
3298
3299#undef D
3300#undef N
3301#undef G
3302#undef GD
3303#undef I
aa97bb48 3304#undef GP
01de8b09 3305#undef EXT
73fba5f4 3306
8d8f4e9f 3307#undef D2bv
f6511935 3308#undef D2bvIP
8d8f4e9f 3309#undef I2bv
d67fc27a 3310#undef I6ALU
8d8f4e9f 3311
39f21ee5
AK		 3312static unsigned imm_size(struct decode_cache *c)
3313{
3314 unsigned size;
3315
3316 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3317 if (size == 8)
3318 size = 4;
3319 return size;
3320}
3321
3322static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3323 unsigned size, bool sign_extension)
3324{
3325 struct decode_cache *c = &ctxt->decode;
39f21ee5
AK		 3326 int rc = X86EMUL_CONTINUE;
3327
3328 op->type = OP_IMM;
3329 op->bytes = size;
90de84f5 3330 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3331 /* NB. Immediates are sign-extended as necessary. */
3332 switch (op->bytes) {
3333 case 1:
3334 op->val = insn_fetch(s8, 1, c->eip);
3335 break;
3336 case 2:
3337 op->val = insn_fetch(s16, 2, c->eip);
3338 break;
3339 case 4:
3340 op->val = insn_fetch(s32, 4, c->eip);
3341 break;
3342 }
3343 if (!sign_extension) {
3344 switch (op->bytes) {
3345 case 1:
3346 op->val &= 0xff;
3347 break;
3348 case 2:
3349 op->val &= 0xffff;
3350 break;
3351 case 4:
3352 op->val &= 0xffffffff;
3353 break;
3354 }
3355 }
3356done:
3357 return rc;
3358}
3359
ef5d75cc 3360int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3361{
dde7e6d1
AK		 3362 struct decode_cache *c = &ctxt->decode;
3363 int rc = X86EMUL_CONTINUE;
3364 int mode = ctxt->mode;
46561646 3365 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3366 bool op_prefix = false;
46561646 3367 struct opcode opcode;
cb16c348 3368 struct operand memop = { .type = OP_NONE }, *memopp = NULL;
dde7e6d1 3369
dde7e6d1 3370 c->eip = ctxt->eip;
dc25e89e
AP		 3371 c->fetch.start = c->eip;
3372 c->fetch.end = c->fetch.start + insn_len;
3373 if (insn_len > 0)
3374 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3375
3376 switch (mode) {
3377 case X86EMUL_MODE_REAL:
3378 case X86EMUL_MODE_VM86:
3379 case X86EMUL_MODE_PROT16:
3380 def_op_bytes = def_ad_bytes = 2;
3381 break;
3382 case X86EMUL_MODE_PROT32:
3383 def_op_bytes = def_ad_bytes = 4;
3384 break;
3385#ifdef CONFIG_X86_64
3386 case X86EMUL_MODE_PROT64:
3387 def_op_bytes = 4;
3388 def_ad_bytes = 8;
3389 break;
3390#endif
3391 default:
3392 return -1;
3393 }
3394
3395 c->op_bytes = def_op_bytes;
3396 c->ad_bytes = def_ad_bytes;
3397
3398 /* Legacy prefixes. */
3399 for (;;) {
3400 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3401 case 0x66: /* operand-size override */
0d7cdee8 3402 op_prefix = true;
dde7e6d1
AK		 3403 /* switch between 2/4 bytes */
3404 c->op_bytes = def_op_bytes ^ 6;
3405 break;
3406 case 0x67: /* address-size override */
3407 if (mode == X86EMUL_MODE_PROT64)
3408 /* switch between 4/8 bytes */
3409 c->ad_bytes = def_ad_bytes ^ 12;
3410 else
3411 /* switch between 2/4 bytes */
3412 c->ad_bytes = def_ad_bytes ^ 6;
3413 break;
3414 case 0x26: /* ES override */
3415 case 0x2e: /* CS override */
3416 case 0x36: /* SS override */
3417 case 0x3e: /* DS override */
3418 set_seg_override(c, (c->b >> 3) & 3);
3419 break;
3420 case 0x64: /* FS override */
3421 case 0x65: /* GS override */
3422 set_seg_override(c, c->b & 7);
3423 break;
3424 case 0x40 ... 0x4f: /* REX */
3425 if (mode != X86EMUL_MODE_PROT64)
3426 goto done_prefixes;
3427 c->rex_prefix = c->b;
3428 continue;
3429 case 0xf0: /* LOCK */
3430 c->lock_prefix = 1;
3431 break;
3432 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3433 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3434 c->rep_prefix = c->b;
dde7e6d1
AK		 3435 break;
3436 default:
3437 goto done_prefixes;
3438 }
3439
3440 /* Any legacy prefix after a REX prefix nullifies its effect. */
3441
3442 c->rex_prefix = 0;
3443 }
3444
3445done_prefixes:
3446
3447 /* REX prefix. */
1e87e3ef
AK		 3448 if (c->rex_prefix & 8)
3449 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3450
3451 /* Opcode byte(s). */
3452 opcode = opcode_table[c->b];
d3ad6243
WY		 3453 /* Two-byte opcode? */
3454 if (c->b == 0x0f) {
3455 c->twobyte = 1;
3456 c->b = insn_fetch(u8, 1, c->eip);
3457 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3458 }
3459 c->d = opcode.flags;
3460
46561646
AK		 3461 while (c->d & GroupMask) {
3462 switch (c->d & GroupMask) {
3463 case Group:
3464 c->modrm = insn_fetch(u8, 1, c->eip);
3465 --c->eip;
3466 goffset = (c->modrm >> 3) & 7;
3467 opcode = opcode.u.group[goffset];
3468 break;
3469 case GroupDual:
3470 c->modrm = insn_fetch(u8, 1, c->eip);
3471 --c->eip;
3472 goffset = (c->modrm >> 3) & 7;
3473 if ((c->modrm >> 6) == 3)
3474 opcode = opcode.u.gdual->mod3[goffset];
3475 else
3476 opcode = opcode.u.gdual->mod012[goffset];
3477 break;
3478 case RMExt:
01de8b09
JR		 3479 goffset = c->modrm & 7;
3480 opcode = opcode.u.group[goffset];
46561646
AK		 3481 break;
3482 case Prefix:
3483 if (c->rep_prefix && op_prefix)
3484 return X86EMUL_UNHANDLEABLE;
3485 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3486 switch (simd_prefix) {
3487 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3488 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3489 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3490 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3491 }
3492 break;
3493 default:
0d7cdee8 3494 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3495 }
46561646
AK		 3496
3497 c->d &= ~GroupMask;
0d7cdee8
AK		 3498 c->d |= opcode.flags;
3499 }
3500
dde7e6d1 3501 c->execute = opcode.u.execute;
d09beabd 3502 c->check_perm = opcode.check_perm;
c4f035c6 3503 c->intercept = opcode.intercept;
dde7e6d1
AK		 3504
3505 /* Unrecognised? */
d53db5ef 3506 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3507 return -1;
dde7e6d1 3508
d867162c
AK		 3509 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3510 return -1;
3511
dde7e6d1
AK		 3512 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3513 c->op_bytes = 8;
3514
7f9b4b75
AK		 3515 if (c->d & Op3264) {
3516 if (mode == X86EMUL_MODE_PROT64)
3517 c->op_bytes = 8;
3518 else
3519 c->op_bytes = 4;
3520 }
3521
1253791d
AK		 3522 if (c->d & Sse)
3523 c->op_bytes = 16;
3524
dde7e6d1 3525 /* ModRM and SIB bytes. */
09ee57cd 3526 if (c->d & ModRM) {
ef5d75cc 3527 rc = decode_modrm(ctxt, &memop);
09ee57cd
AK		 3528 if (!c->has_seg_override)
3529 set_seg_override(c, c->modrm_seg);
3530 } else if (c->d & MemAbs)
ef5d75cc 3531 rc = decode_abs(ctxt, &memop);
dde7e6d1
AK		 3532 if (rc != X86EMUL_CONTINUE)
3533 goto done;
3534
3535 if (!c->has_seg_override)
3536 set_seg_override(c, VCPU_SREG_DS);
3537
c1ed6dea 3538 memop.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1 3539
2dbd0dd7 3540 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3541 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3542
dde7e6d1
AK		 3543 /*
3544 * Decode and fetch the source operand: register, memory
3545 * or immediate.
3546 */
3547 switch (c->d & SrcMask) {
3548 case SrcNone:
3549 break;
3550 case SrcReg:
1253791d 3551 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3552 break;
3553 case SrcMem16:
2dbd0dd7 3554 memop.bytes = 2;
dde7e6d1
AK		 3555 goto srcmem_common;
3556 case SrcMem32:
2dbd0dd7 3557 memop.bytes = 4;
dde7e6d1
AK		 3558 goto srcmem_common;
3559 case SrcMem:
2dbd0dd7 3560 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3561 c->op_bytes;
dde7e6d1 3562 srcmem_common:
2dbd0dd7 3563 c->src = memop;
cb16c348 3564 memopp = &c->src;
dde7e6d1 3565 break;
b250e605 3566 case SrcImmU16:
39f21ee5
AK		 3567 rc = decode_imm(ctxt, &c->src, 2, false);
3568 break;
dde7e6d1 3569 case SrcImm:
39f21ee5
AK		 3570 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3571 break;
dde7e6d1 3572 case SrcImmU:
39f21ee5 3573 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3574 break;
3575 case SrcImmByte:
39f21ee5
AK		 3576 rc = decode_imm(ctxt, &c->src, 1, true);
3577 break;
dde7e6d1 3578 case SrcImmUByte:
39f21ee5 3579 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3580 break;
3581 case SrcAcc:
3582 c->src.type = OP_REG;
3583 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3584 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3585 fetch_register_operand(&c->src);
dde7e6d1
AK		 3586 break;
3587 case SrcOne:
3588 c->src.bytes = 1;
3589 c->src.val = 1;
3590 break;
3591 case SrcSI:
3592 c->src.type = OP_MEM;
3593 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3594 c->src.addr.mem.ea =
3595 register_address(c, c->regs[VCPU_REGS_RSI]);
c1ed6dea 3596 c->src.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1
AK		 3597 c->src.val = 0;
3598 break;
3599 case SrcImmFAddr:
3600 c->src.type = OP_IMM;
90de84f5 3601 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3602 c->src.bytes = c->op_bytes + 2;
3603 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3604 break;
3605 case SrcMemFAddr:
2dbd0dd7
AK		 3606 memop.bytes = c->op_bytes + 2;
3607 goto srcmem_common;
dde7e6d1 3608 break;
221192bd
MT		 3609 case SrcDX:
3610 c->src.type = OP_REG;
3611 c->src.bytes = 2;
3612 c->src.addr.reg = &c->regs[VCPU_REGS_RDX];
3613 fetch_register_operand(&c->src);
3614 break;
dde7e6d1
AK		 3615 }
3616
39f21ee5
AK		 3617 if (rc != X86EMUL_CONTINUE)
3618 goto done;
3619
dde7e6d1
AK		 3620 /*
3621 * Decode and fetch the second source operand: register, memory
3622 * or immediate.
3623 */
3624 switch (c->d & Src2Mask) {
3625 case Src2None:
3626 break;
3627 case Src2CL:
3628 c->src2.bytes = 1;
3629 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3630 break;
3631 case Src2ImmByte:
39f21ee5 3632 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3633 break;
3634 case Src2One:
3635 c->src2.bytes = 1;
3636 c->src2.val = 1;
3637 break;
7db41eb7
AK		 3638 case Src2Imm:
3639 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3640 break;
dde7e6d1
AK		 3641 }
3642
39f21ee5
AK		 3643 if (rc != X86EMUL_CONTINUE)
3644 goto done;
3645
dde7e6d1
AK		 3646 /* Decode and fetch the destination operand: register or memory. */
3647 switch (c->d & DstMask) {
dde7e6d1 3648 case DstReg:
1253791d 3649 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3650 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3651 break;
943858e2
WY		 3652 case DstImmUByte:
3653 c->dst.type = OP_IMM;
90de84f5 3654 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3655 c->dst.bytes = 1;
3656 c->dst.val = insn_fetch(u8, 1, c->eip);
3657 break;
dde7e6d1
AK		 3658 case DstMem:
3659 case DstMem64:
2dbd0dd7 3660 c->dst = memop;
cb16c348 3661 memopp = &c->dst;
dde7e6d1
AK		 3662 if ((c->d & DstMask) == DstMem64)
3663 c->dst.bytes = 8;
3664 else
3665 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3666 if (c->d & BitOp)
3667 fetch_bit_operand(c);
2dbd0dd7 3668 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3669 break;
3670 case DstAcc:
3671 c->dst.type = OP_REG;
3672 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3673 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3674 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3675 c->dst.orig_val = c->dst.val;
3676 break;
3677 case DstDI:
3678 c->dst.type = OP_MEM;
3679 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3680 c->dst.addr.mem.ea =
3681 register_address(c, c->regs[VCPU_REGS_RDI]);
3682 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3683 c->dst.val = 0;
3684 break;
221192bd
MT		 3685 case DstDX:
3686 c->dst.type = OP_REG;
3687 c->dst.bytes = 2;
3688 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
3689 fetch_register_operand(&c->dst);
3690 break;
36089fed
WY		 3691 case ImplicitOps:
3692 /* Special instructions do their own operand decoding. */
3693 default:
3694 c->dst.type = OP_NONE; /* Disable writeback. */
cb16c348 3695 break;
dde7e6d1
AK		 3696 }
3697
3698done:
cb16c348
AK		 3699 if (memopp && memopp->type == OP_MEM && c->rip_relative)
3700 memopp->addr.mem.ea += c->eip;
3701
a0c0ab2f 3702 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3703}
3704
3e2f65d5
GN		 3705static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3706{
3707 struct decode_cache *c = &ctxt->decode;
3708
3709 /* The second termination condition only applies for REPE
3710 * and REPNE. Test if the repeat string operation prefix is
3711 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3712 * corresponding termination condition according to:
3713 * - if REPE/REPZ and ZF = 0 then done
3714 * - if REPNE/REPNZ and ZF = 1 then done
3715 */
3716 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3717 (c->b == 0xae) || (c->b == 0xaf))
3718 && (((c->rep_prefix == REPE_PREFIX) &&
3719 ((ctxt->eflags & EFLG_ZF) == 0))
3720 || ((c->rep_prefix == REPNE_PREFIX) &&
3721 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3722 return true;
3723
3724 return false;
3725}
3726
8b4caf66 3727int
9aabc88f 3728x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3729{
9aabc88f 3730 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3731 u64 msr_data;
8b4caf66 3732 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3733 int rc = X86EMUL_CONTINUE;
5cd21917 3734 int saved_dst_type = c->dst.type;
6e154e56 3735 int irq; /* Used for int 3, int, and into */
8b4caf66 3736
9de41573 3737 ctxt->decode.mem_read.pos = 0;
310b5d30 3738
1161624f 3739 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3740 rc = emulate_ud(ctxt);
1161624f
GN		 3741 goto done;
3742 }
3743
d380a5e4 3744 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3745 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3746 rc = emulate_ud(ctxt);
d380a5e4
GN		 3747 goto done;
3748 }
3749
081bca0e 3750 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3751 rc = emulate_ud(ctxt);
081bca0e
AK		 3752 goto done;
3753 }
3754
1253791d 3755 if ((c->d & Sse)
717746e3
AK		 3756 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3757 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3758 rc = emulate_ud(ctxt);
3759 goto done;
3760 }
3761
717746e3 3762 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3763 rc = emulate_nm(ctxt);
3764 goto done;
3765 }
3766
c4f035c6 3767 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3768 rc = emulator_check_intercept(ctxt, c->intercept,
3769 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3770 if (rc != X86EMUL_CONTINUE)
3771 goto done;
3772 }
3773
e92805ac 3774 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3775 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3776 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3777 goto done;
3778 }
3779
8ea7d6ae
JR		 3780 /* Instruction can only be executed in protected mode */
3781 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3782 rc = emulate_ud(ctxt);
3783 goto done;
3784 }
3785
d09beabd
JR		 3786 /* Do instruction specific permission checks */
3787 if (c->check_perm) {
3788 rc = c->check_perm(ctxt);
3789 if (rc != X86EMUL_CONTINUE)
3790 goto done;
3791 }
3792
c4f035c6 3793 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3794 rc = emulator_check_intercept(ctxt, c->intercept,
3795 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3796 if (rc != X86EMUL_CONTINUE)
3797 goto done;
3798 }
3799
b9fa9d6b
AK		 3800 if (c->rep_prefix && (c->d & String)) {
3801 /* All REP prefixes have the same first termination condition */
c73e197b 3802 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3803 ctxt->eip = c->eip;
b9fa9d6b
AK		 3804 goto done;
3805 }
b9fa9d6b
AK		 3806 }
3807
c483c02a 3808 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3809 rc = segmented_read(ctxt, c->src.addr.mem,
3810 c->src.valptr, c->src.bytes);
b60d513c 3811 if (rc != X86EMUL_CONTINUE)
8b4caf66 3812 goto done;
16518d5a 3813 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3814 }
3815
e35b7b9c 3816 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3817 rc = segmented_read(ctxt, c->src2.addr.mem,
3818 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3819 if (rc != X86EMUL_CONTINUE)
3820 goto done;
3821 }
3822
8b4caf66
LV		 3823 if ((c->d & DstMask) == ImplicitOps)
3824 goto special_insn;
3825
3826
69f55cb1
GN		 3827 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3828 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3829 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3830 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3831 if (rc != X86EMUL_CONTINUE)
3832 goto done;
038e51de 3833 }
e4e03ded 3834 c->dst.orig_val = c->dst.val;
038e51de 3835
018a98db
AK		 3836special_insn:
3837
c4f035c6 3838 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3839 rc = emulator_check_intercept(ctxt, c->intercept,
3840 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3841 if (rc != X86EMUL_CONTINUE)
3842 goto done;
3843 }
3844
ef65c889
AK		 3845 if (c->execute) {
3846 rc = c->execute(ctxt);
3847 if (rc != X86EMUL_CONTINUE)
3848 goto done;
3849 goto writeback;
3850 }
3851
e4e03ded 3852 if (c->twobyte)
6aa8b732
AK		 3853 goto twobyte_insn;
3854
e4e03ded 3855 switch (c->b) {
0934ac9d 3856 case 0x06: /* push es */
4179bb02 3857 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3858 break;
3859 case 0x07: /* pop es */
0934ac9d 3860 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3861 break;
0934ac9d 3862 case 0x0e: /* push cs */
4179bb02 3863 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3864 break;
0934ac9d 3865 case 0x16: /* push ss */
4179bb02 3866 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3867 break;
3868 case 0x17: /* pop ss */
0934ac9d 3869 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3870 break;
0934ac9d 3871 case 0x1e: /* push ds */
4179bb02 3872 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3873 break;
3874 case 0x1f: /* pop ds */
0934ac9d 3875 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3876 break;
33615aa9
AK		 3877 case 0x40 ... 0x47: /* inc r16/r32 */
3878 emulate_1op("inc", c->dst, ctxt->eflags);
3879 break;
3880 case 0x48 ... 0x4f: /* dec r16/r32 */
3881 emulate_1op("dec", c->dst, ctxt->eflags);
3882 break;
6aa8b732 3883 case 0x63: /* movsxd */
8b4caf66 3884 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3885 goto cannot_emulate;
e4e03ded 3886 c->dst.val = (s32) c->src.val;
6aa8b732 3887 break;
018a98db
AK		 3888 case 0x6c: /* insb */
3889 case 0x6d: /* insw/insd */
a13a63fa
WY		 3890 c->src.val = c->regs[VCPU_REGS_RDX];
3891 goto do_io_in;
018a98db
AK		 3892 case 0x6e: /* outsb */
3893 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3894 c->dst.val = c->regs[VCPU_REGS_RDX];
3895 goto do_io_out;
7972995b 3896 break;
b2833e3c 3897 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3898 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3899 jmp_rel(c, c->src.val);
018a98db 3900 break;
6aa8b732 3901 case 0x84 ... 0x85:
dfb507c4 3902 test:
05f086f8 3903 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3904 break;
3905 case 0x86 ... 0x87: /* xchg */
b13354f8 3906 xchg:
6aa8b732 3907 /* Write back the register source. */
31be40b3
WY		 3908 c->src.val = c->dst.val;
3909 write_register_operand(&c->src);
6aa8b732
AK		 3910 /*
3911 * Write back the memory destination with implicit LOCK
3912 * prefix.
3913 */
31be40b3 3914 c->dst.val = c->src.orig_val;
e4e03ded 3915 c->lock_prefix = 1;
6aa8b732 3916 break;
79168fd1
GN		 3917 case 0x8c: /* mov r/m, sreg */
3918 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3919 rc = emulate_ud(ctxt);
5e3ae6c5 3920 goto done;
38d5bc6d 3921 }
1aa36616 3922 c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3923 break;
7e0b54b1 3924 case 0x8d: /* lea r16/r32, m */
90de84f5 3925 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3926 break;
4257198a
GT		 3927 case 0x8e: { /* mov seg, r/m16 */
3928 uint16_t sel;
4257198a
GT		 3929
3930 sel = c->src.val;
8b9f4414 3931
c697518a
GN		 3932 if (c->modrm_reg == VCPU_SREG_CS ||
3933 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3934 rc = emulate_ud(ctxt);
8b9f4414
GN		 3935 goto done;
3936 }
3937
310b5d30 3938 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3939 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3940
2e873022 3941 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3942
3943 c->dst.type = OP_NONE; /* Disable writeback. */
3944 break;
3945 }
6aa8b732 3946 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3947 rc = em_grp1a(ctxt);
6aa8b732 3948 break;
3d9e77df
AK		 3949 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3950 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3951 break;
b13354f8 3952 goto xchg;
e8b6fa70
WY		 3953 case 0x98: /* cbw/cwde/cdqe */
3954 switch (c->op_bytes) {
3955 case 2: c->dst.val = (s8)c->dst.val; break;
3956 case 4: c->dst.val = (s16)c->dst.val; break;
3957 case 8: c->dst.val = (s32)c->dst.val; break;
3958 }
3959 break;
dfb507c4
MG		 3960 case 0xa8 ... 0xa9: /* test ax, imm */
3961 goto test;
018a98db 3962 case 0xc0 ... 0xc1:
51187683 3963 rc = em_grp2(ctxt);
018a98db 3964 break;
111de5d6 3965 case 0xc3: /* ret */
cf5de4f8 3966 c->dst.type = OP_REG;
1a6440ae 3967 c->dst.addr.reg = &c->eip;
cf5de4f8 3968 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3969 rc = em_pop(ctxt);
3970 break;
09b5f4d3
WY		 3971 case 0xc4: /* les */
3972 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3973 break;
3974 case 0xc5: /* lds */
3975 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3976 break;
a77ab5ea
AK		 3977 case 0xcb: /* ret far */
3978 rc = emulate_ret_far(ctxt, ops);
62bd430e 3979 break;
6e154e56
MG		 3980 case 0xcc: /* int3 */
3981 irq = 3;
3982 goto do_interrupt;
3983 case 0xcd: /* int n */
3984 irq = c->src.val;
3985 do_interrupt:
3986 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3987 break;
3988 case 0xce: /* into */
3989 if (ctxt->eflags & EFLG_OF) {
3990 irq = 4;
3991 goto do_interrupt;
3992 }
3993 break;
62bd430e
MG		 3994 case 0xcf: /* iret */
3995 rc = emulate_iret(ctxt, ops);
a77ab5ea 3996 break;
018a98db 3997 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3998 rc = em_grp2(ctxt);
018a98db
AK		 3999 break;
4000 case 0xd2 ... 0xd3: /* Grp2 */
4001 c->src.val = c->regs[VCPU_REGS_RCX];
51187683 4002 rc = em_grp2(ctxt);
018a98db 4003 break;
f2f31845
WY		 4004 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
4005 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4006 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
4007 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
4008 jmp_rel(c, c->src.val);
4009 break;
e4abac67
WY		 4010 case 0xe3: /* jcxz/jecxz/jrcxz */
4011 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
4012 jmp_rel(c, c->src.val);
4013 break;
a6a3034c
MG		 4014 case 0xe4: /* inb */
4015 case 0xe5: /* in */
cf8f70bf 4016 goto do_io_in;
a6a3034c
MG		 4017 case 0xe6: /* outb */
4018 case 0xe7: /* out */
cf8f70bf 4019 goto do_io_out;
1a52e051 4020 case 0xe8: /* call (near) */ {
d53c4777 4021 long int rel = c->src.val;
e4e03ded 4022 c->src.val = (unsigned long) c->eip;
7a957275 4023 jmp_rel(c, rel);
4487b3b4 4024 rc = em_push(ctxt);
8cdbd2c9 4025 break;
1a52e051
NK		 4026 }
4027 case 0xe9: /* jmp rel */
954cd36f 4028 goto jmp;
d2f62766
TY		 4029 case 0xea: /* jmp far */
4030 rc = em_jmp_far(ctxt);
954cd36f 4031 break;
954cd36f
GT		 4032 case 0xeb:
4033 jmp: /* jmp rel short */
7a957275 4034 jmp_rel(c, c->src.val);
a01af5ec 4035 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4036 break;
a6a3034c
MG		 4037 case 0xec: /* in al,dx */
4038 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 4039 do_io_in:
7b262e90
GN		 4040 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4041 &c->dst.val))
cf8f70bf
GN		 4042 goto done; /* IO is needed */
4043 break;
ce7a0ad3
WY		 4044 case 0xee: /* out dx,al */
4045 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 4046 do_io_out:
ca1d4a9e
AK		 4047 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4048 &c->src.val, 1);
cf8f70bf 4049 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4050 break;
111de5d6 4051 case 0xf4: /* hlt */
6c3287f7 4052 ctxt->ops->halt(ctxt);
19fdfa0d 4053 break;
111de5d6
AK		 4054 case 0xf5: /* cmc */
4055 /* complement carry flag from eflags reg */
4056 ctxt->eflags ^= EFLG_CF;
111de5d6 4057 break;
018a98db 4058 case 0xf6 ... 0xf7: /* Grp3 */
51187683 4059 rc = em_grp3(ctxt);
018a98db 4060 break;
111de5d6
AK		 4061 case 0xf8: /* clc */
4062 ctxt->eflags &= ~EFLG_CF;
111de5d6 4063 break;
8744aa9a
MG		 4064 case 0xf9: /* stc */
4065 ctxt->eflags |= EFLG_CF;
4066 break;
111de5d6 4067 case 0xfa: /* cli */
07cbc6c1 4068 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4069 rc = emulate_gp(ctxt, 0);
07cbc6c1 4070 goto done;
36089fed 4071 } else
f850e2e6 4072 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4073 break;
4074 case 0xfb: /* sti */
07cbc6c1 4075 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4076 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4077 goto done;
4078 } else {
95cb2295 4079 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4080 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4081 }
111de5d6 4082 break;
fb4616f4
MG		 4083 case 0xfc: /* cld */
4084 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4085 break;
4086 case 0xfd: /* std */
4087 ctxt->eflags |= EFLG_DF;
fb4616f4 4088 break;
ea79849d 4089 case 0xfe: /* Grp4 */
51187683 4090 rc = em_grp45(ctxt);
018a98db 4091 break;
ea79849d 4092 case 0xff: /* Grp5 */
51187683
TY		 4093 rc = em_grp45(ctxt);
4094 break;
91269b8f
AK		 4095 default:
4096 goto cannot_emulate;
6aa8b732 4097 }
018a98db 4098
7d9ddaed
AK		 4099 if (rc != X86EMUL_CONTINUE)
4100 goto done;
4101
018a98db 4102writeback:
adddcecf 4103 rc = writeback(ctxt);
1b30eaa8 4104 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4105 goto done;
4106
5cd21917
GN		 4107 /*
4108 * restore dst type in case the decoding will be reused
4109 * (happens for string instruction )
4110 */
4111 c->dst.type = saved_dst_type;
4112
a682e354 4113 if ((c->d & SrcMask) == SrcSI)
c1ed6dea 4114 string_addr_inc(ctxt, seg_override(ctxt, c),
79168fd1 4115 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4116
4117 if ((c->d & DstMask) == DstDI)
90de84f5 4118 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4119 &c->dst);
d9271123 4120
5cd21917 4121 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4122 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4123 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4124
d2ddd1c4
GN		 4125 if (!string_insn_completed(ctxt)) {
4126 /*
4127 * Re-enter guest when pio read ahead buffer is empty
4128 * or, if it is not used, after each 1024 iteration.
4129 */
4130 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4131 (r->end == 0 || r->end != r->pos)) {
4132 /*
4133 * Reset read cache. Usually happens before
4134 * decode, but since instruction is restarted
4135 * we have to do it here.
4136 */
4137 ctxt->decode.mem_read.end = 0;
4138 return EMULATION_RESTART;
4139 }
4140 goto done; /* skip rip writeback */
0fa6ccbd 4141 }
5cd21917 4142 }
d2ddd1c4
GN		 4143
4144 ctxt->eip = c->eip;
018a98db
AK		 4145
4146done:
da9cb575
AK		 4147 if (rc == X86EMUL_PROPAGATE_FAULT)
4148 ctxt->have_exception = true;
775fde86
JR		 4149 if (rc == X86EMUL_INTERCEPTED)
4150 return EMULATION_INTERCEPTED;
4151
d2ddd1c4 4152 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4153
4154twobyte_insn:
e4e03ded 4155 switch (c->b) {
e99f0507 4156 case 0x05: /* syscall */
3fb1b5db 4157 rc = emulate_syscall(ctxt, ops);
e99f0507 4158 break;
018a98db 4159 case 0x06:
2d04a05b 4160 rc = em_clts(ctxt);
018a98db 4161 break;
018a98db 4162 case 0x09: /* wbinvd */
cfb22375 4163 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4164 break;
4165 case 0x08: /* invd */
018a98db
AK		 4166 case 0x0d: /* GrpP (prefetch) */
4167 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4168 break;
4169 case 0x20: /* mov cr, reg */
717746e3 4170 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4171 break;
6aa8b732 4172 case 0x21: /* mov from dr to reg */
717746e3 4173 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4174 break;
018a98db 4175 case 0x22: /* mov reg, cr */
717746e3 4176 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4177 emulate_gp(ctxt, 0);
da9cb575 4178 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4179 goto done;
4180 }
018a98db
AK		 4181 c->dst.type = OP_NONE;
4182 break;
6aa8b732 4183 case 0x23: /* mov from reg to dr */
717746e3 4184 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4185 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4186 ~0ULL : ~0U)) < 0) {
338dbc97 4187 /* #UD condition is already handled by the code above */
54b8486f 4188 emulate_gp(ctxt, 0);
da9cb575 4189 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4190 goto done;
4191 }
4192
a01af5ec 4193 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4194 break;
018a98db
AK		 4195 case 0x30:
4196 /* wrmsr */
4197 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4198 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4199 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4200 emulate_gp(ctxt, 0);
da9cb575 4201 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4202 goto done;
018a98db
AK		 4203 }
4204 rc = X86EMUL_CONTINUE;
018a98db
AK		 4205 break;
4206 case 0x32:
4207 /* rdmsr */
717746e3 4208 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4209 emulate_gp(ctxt, 0);
da9cb575 4210 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4211 goto done;
018a98db
AK		 4212 } else {
4213 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4214 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4215 }
4216 rc = X86EMUL_CONTINUE;
018a98db 4217 break;
e99f0507 4218 case 0x34: /* sysenter */
3fb1b5db 4219 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4220 break;
4221 case 0x35: /* sysexit */
3fb1b5db 4222 rc = emulate_sysexit(ctxt, ops);
e99f0507 4223 break;
6aa8b732 4224 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4225 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4226 if (!test_cc(c->b, ctxt->eflags))
4227 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4228 break;
b2833e3c 4229 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4230 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4231 jmp_rel(c, c->src.val);
018a98db 4232 break;
ee45b58e
WY		 4233 case 0x90 ... 0x9f: /* setcc r/m8 */
4234 c->dst.val = test_cc(c->b, ctxt->eflags);
4235 break;
0934ac9d 4236 case 0xa0: /* push fs */
4179bb02 4237 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4238 break;
4239 case 0xa1: /* pop fs */
4240 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4241 break;
7de75248
NK		 4242 case 0xa3:
4243 bt: /* bt */
e4f8e039 4244 c->dst.type = OP_NONE;
e4e03ded
LV		 4245 /* only subword offset */
4246 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4247 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4248 break;
9bf8ea42
GT		 4249 case 0xa4: /* shld imm8, r, r/m */
4250 case 0xa5: /* shld cl, r, r/m */
4251 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4252 break;
0934ac9d 4253 case 0xa8: /* push gs */
4179bb02 4254 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4255 break;
4256 case 0xa9: /* pop gs */
4257 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4258 break;
7de75248
NK		 4259 case 0xab:
4260 bts: /* bts */
05f086f8 4261 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4262 break;
9bf8ea42
GT		 4263 case 0xac: /* shrd imm8, r, r/m */
4264 case 0xad: /* shrd cl, r, r/m */
4265 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4266 break;
2a7c5b8b
GC		 4267 case 0xae: /* clflush */
4268 break;
6aa8b732
AK		 4269 case 0xb0 ... 0xb1: /* cmpxchg */
4270 /*
4271 * Save real source value, then compare EAX against
4272 * destination.
4273 */
e4e03ded
LV		 4274 c->src.orig_val = c->src.val;
4275 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4276 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4277 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4278 /* Success: write back to memory. */
e4e03ded 4279 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4280 } else {
4281 /* Failure: write the value we saw to EAX. */
e4e03ded 4282 c->dst.type = OP_REG;
1a6440ae 4283 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4284 }
4285 break;
09b5f4d3
WY		 4286 case 0xb2: /* lss */
4287 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4288 break;
6aa8b732
AK		 4289 case 0xb3:
4290 btr: /* btr */
05f086f8 4291 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4292 break;
09b5f4d3
WY		 4293 case 0xb4: /* lfs */
4294 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4295 break;
4296 case 0xb5: /* lgs */
4297 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4298 break;
6aa8b732 4299 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4300 c->dst.bytes = c->op_bytes;
4301 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4302 : (u16) c->src.val;
6aa8b732 4303 break;
6aa8b732 4304 case 0xba: /* Grp8 */
e4e03ded 4305 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4306 case 0:
4307 goto bt;
4308 case 1:
4309 goto bts;
4310 case 2:
4311 goto btr;
4312 case 3:
4313 goto btc;
4314 }
4315 break;
7de75248
NK		 4316 case 0xbb:
4317 btc: /* btc */
05f086f8 4318 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4319 break;
d9574a25
WY		 4320 case 0xbc: { /* bsf */
4321 u8 zf;
4322 __asm__ ("bsf %2, %0; setz %1"
4323 : "=r"(c->dst.val), "=q"(zf)
4324 : "r"(c->src.val));
4325 ctxt->eflags &= ~X86_EFLAGS_ZF;
4326 if (zf) {
4327 ctxt->eflags |= X86_EFLAGS_ZF;
4328 c->dst.type = OP_NONE; /* Disable writeback. */
4329 }
4330 break;
4331 }
4332 case 0xbd: { /* bsr */
4333 u8 zf;
4334 __asm__ ("bsr %2, %0; setz %1"
4335 : "=r"(c->dst.val), "=q"(zf)
4336 : "r"(c->src.val));
4337 ctxt->eflags &= ~X86_EFLAGS_ZF;
4338 if (zf) {
4339 ctxt->eflags |= X86_EFLAGS_ZF;
4340 c->dst.type = OP_NONE; /* Disable writeback. */
4341 }
4342 break;
4343 }
6aa8b732 4344 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4345 c->dst.bytes = c->op_bytes;
4346 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4347 (s16) c->src.val;
6aa8b732 4348 break;
92f738a5
WY		 4349 case 0xc0 ... 0xc1: /* xadd */
4350 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4351 /* Write back the register source. */
4352 c->src.val = c->dst.orig_val;
4353 write_register_operand(&c->src);
4354 break;
a012e65a 4355 case 0xc3: /* movnti */
e4e03ded
LV		 4356 c->dst.bytes = c->op_bytes;
4357 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4358 (u64) c->src.val;
a012e65a 4359 break;
6aa8b732 4360 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4361 rc = em_grp9(ctxt);
8cdbd2c9 4362 break;
91269b8f
AK		 4363 default:
4364 goto cannot_emulate;
6aa8b732 4365 }
7d9ddaed
AK		 4366
4367 if (rc != X86EMUL_CONTINUE)
4368 goto done;
4369
6aa8b732
AK		 4370 goto writeback;
4371
4372cannot_emulate:
a0c0ab2f 4373 return EMULATION_FAILED;
6aa8b732 4374}
Linux kernel - Deliverables
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