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KVM: x86 emulator: allow storing emulator execution function in decode tables
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
57#define DstMask (7<<1)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 85/* Misc flags */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Mask (7<<29)
6aa8b732 96
ea9ef04e
AK		 97#define X2(x) x, x
98#define X3(x) X2(x), x
83babbca 99#define X4(x) X2(x), X2(x)
ea9ef04e 100#define X5(x) X4(x), x
83babbca
AK		 101#define X6(x) X4(x), X2(x)
102#define X7(x) X4(x), X3(x)
103#define X8(x) X4(x), X4(x)
104#define X16(x) X8(x), X8(x)
105
d65b1dee
AK		 106struct opcode {
107 u32 flags;
120df890 108 union {
ef65c889 109 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 110 struct opcode *group;
111 struct group_dual *gdual;
112 } u;
113};
114
115struct group_dual {
116 struct opcode mod012[8];
117 struct opcode mod3[8];
d65b1dee
AK		 118};
119
fd853310
AK		 120#define D(_y) { .flags = (_y) }
121#define N D(0)
120df890
AK		 122#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
123#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
ef65c889 124#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
fd853310 125
5b92b5fa
AK		 126static struct opcode group1[] = {
127 X7(D(Lock)), N
128};
129
99880c5c 130static struct opcode group1A[] = {
42a1c520 131 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
99880c5c
AK		 132};
133
ee70ea30 134static struct opcode group3[] = {
42a1c520
AK		 135 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
136 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
137 X4(D(Undefined)),
ee70ea30
AK		 138};
139
591c9d20 140static struct opcode group4[] = {
42a1c520
AK		 141 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
142 N, N, N, N, N, N,
591c9d20
AK		 143};
144
b67f9f07 145static struct opcode group5[] = {
42a1c520
AK		 146 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
147 D(SrcMem | ModRM | Stack), N,
148 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
149 D(SrcMem | ModRM | Stack), N,
b67f9f07
AK		 150};
151
2f3a9bc9 152static struct group_dual group7 = { {
42a1c520
AK		 153 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
154 D(SrcNone | ModRM | DstMem | Mov), N,
155 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2f3a9bc9
AK		 156}, {
157 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
158 D(SrcNone | ModRM | DstMem | Mov), N,
159 D(SrcMem16 | ModRM | Mov | Priv), N,
160} };
161
2cb20bc8 162static struct opcode group8[] = {
42a1c520
AK		 163 N, N, N, N,
164 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
165 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2cb20bc8
AK		 166};
167
9f5d3220 168static struct group_dual group9 = { {
42a1c520 169 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
9f5d3220
AK		 170}, {
171 N, N, N, N, N, N, N, N,
172} };
173
d65b1dee 174static struct opcode opcode_table[256] = {
6aa8b732 175 /* 0x00 - 0x07 */
fd853310
AK		 176 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
177 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
178 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
179 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 180 /* 0x08 - 0x0F */
fd853310
AK		 181 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
182 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
183 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
184 D(ImplicitOps | Stack | No64), N,
6aa8b732 185 /* 0x10 - 0x17 */
fd853310
AK		 186 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
187 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
188 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
189 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 190 /* 0x18 - 0x1F */
fd853310
AK		 191 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
192 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
193 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
194 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 195 /* 0x20 - 0x27 */
fd853310
AK		 196 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
197 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
198 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 199 /* 0x28 - 0x2F */
fd853310
AK		 200 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
201 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
202 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 203 /* 0x30 - 0x37 */
fd853310
AK		 204 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
205 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
206 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 207 /* 0x38 - 0x3F */
fd853310
AK		 208 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
209 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
210 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
211 N, N,
749358a6 212 /* 0x40 - 0x4F */
fd853310 213 X16(D(DstReg)),
7f0aaee0 214 /* 0x50 - 0x57 */
fd853310 215 X8(D(SrcReg | Stack)),
7f0aaee0 216 /* 0x58 - 0x5F */
fd853310 217 X8(D(DstReg | Stack)),
7d316911 218 /* 0x60 - 0x67 */
fd853310
AK		 219 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
220 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
221 N, N, N, N,
7d316911 222 /* 0x68 - 0x6F */
fd853310
AK		 223 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
224 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
225 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 226 /* 0x70 - 0x7F */
fd853310 227 X16(D(SrcImmByte)),
6aa8b732 228 /* 0x80 - 0x87 */
5b92b5fa
AK		 229 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
230 G(DstMem | SrcImm | ModRM | Group, group1),
231 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
232 G(DstMem | SrcImmByte | ModRM | Group, group1),
fd853310
AK		 233 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
234 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 235 /* 0x88 - 0x8F */
fd853310
AK		 236 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
237 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
238 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
99880c5c 239 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
b13354f8 240 /* 0x90 - 0x97 */
fd853310 241 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 242 /* 0x98 - 0x9F */
fd853310
AK		 243 N, N, D(SrcImmFAddr | No64), N,
244 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 245 /* 0xA0 - 0xA7 */
fd853310
AK		 246 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
247 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
248 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
249 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 250 /* 0xA8 - 0xAF */
fd853310
AK		 251 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
252 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
253 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 254 /* 0xB0 - 0xB7 */
fd853310 255 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 256 /* 0xB8 - 0xBF */
fd853310 257 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 258 /* 0xC0 - 0xC7 */
fd853310
AK		 259 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
260 N, D(ImplicitOps | Stack), N, N,
261 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 262 /* 0xC8 - 0xCF */
fd853310
AK		 263 N, N, N, D(ImplicitOps | Stack),
264 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 265 /* 0xD0 - 0xD7 */
fd853310
AK		 266 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
267 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
268 N, N, N, N,
6aa8b732 269 /* 0xD8 - 0xDF */
fd853310 270 N, N, N, N, N, N, N, N,
098c937b 271 /* 0xE0 - 0xE7 */
fd853310
AK		 272 N, N, N, N,
273 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
274 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 275 /* 0xE8 - 0xEF */
fd853310
AK		 276 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
277 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
278 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
279 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 280 /* 0xF0 - 0xF7 */
fd853310 281 N, N, N, N,
ee70ea30 282 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
6aa8b732 283 /* 0xF8 - 0xFF */
fd853310 284 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
b67f9f07 285 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
6aa8b732
AK		 286};
287
d65b1dee 288static struct opcode twobyte_table[256] = {
6aa8b732 289 /* 0x00 - 0x0F */
2f3a9bc9 290 N, GD(0, &group7), N, N,
fd853310
AK		 291 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
292 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
293 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 294 /* 0x10 - 0x1F */
fd853310 295 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 296 /* 0x20 - 0x2F */
fd853310
AK		 297 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
298 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
299 N, N, N, N,
300 N, N, N, N, N, N, N, N,
6aa8b732 301 /* 0x30 - 0x3F */
fd853310
AK		 302 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
303 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
304 N, N, N, N, N, N, N, N,
be8eacdd 305 /* 0x40 - 0x4F */
fd853310 306 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 307 /* 0x50 - 0x5F */
fd853310 308 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 309 /* 0x60 - 0x6F */
fd853310 310 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 311 /* 0x70 - 0x7F */
fd853310 312 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 313 /* 0x80 - 0x8F */
fd853310 314 X16(D(SrcImm)),
6aa8b732 315 /* 0x90 - 0x9F */
fd853310 316 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 317 /* 0xA0 - 0xA7 */
fd853310
AK		 318 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
319 N, D(DstMem | SrcReg | ModRM | BitOp),
320 D(DstMem | SrcReg | Src2ImmByte | ModRM),
321 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 322 /* 0xA8 - 0xAF */
fd853310
AK		 323 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
324 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
325 D(DstMem | SrcReg | Src2ImmByte | ModRM),
326 D(DstMem | SrcReg | Src2CL | ModRM),
327 D(ModRM), N,
6aa8b732 328 /* 0xB0 - 0xB7 */
fd853310
AK		 329 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
330 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
331 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
332 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 333 /* 0xB8 - 0xBF */
fd853310 334 N, N,
2cb20bc8 335 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
fd853310
AK		 336 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
337 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 338 /* 0xC0 - 0xCF */
fd853310 339 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
9f5d3220 340 N, N, N, GD(0, &group9),
fd853310 341 N, N, N, N, N, N, N, N,
6aa8b732 342 /* 0xD0 - 0xDF */
fd853310 343 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 344 /* 0xE0 - 0xEF */
fd853310 345 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 346 /* 0xF0 - 0xFF */
fd853310 347 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 348};
349
fd853310
AK		 350#undef D
351#undef N
120df890
AK		 352#undef G
353#undef GD
ef65c889 354#undef I
fd853310 355
6aa8b732 356/* EFLAGS bit definitions. */
d4c6a154
GN		 357#define EFLG_ID (1<<21)
358#define EFLG_VIP (1<<20)
359#define EFLG_VIF (1<<19)
360#define EFLG_AC (1<<18)
b1d86143
AP		 361#define EFLG_VM (1<<17)
362#define EFLG_RF (1<<16)
d4c6a154
GN		 363#define EFLG_IOPL (3<<12)
364#define EFLG_NT (1<<14)
6aa8b732
AK		 365#define EFLG_OF (1<<11)
366#define EFLG_DF (1<<10)
b1d86143 367#define EFLG_IF (1<<9)
d4c6a154 368#define EFLG_TF (1<<8)
6aa8b732
AK		 369#define EFLG_SF (1<<7)
370#define EFLG_ZF (1<<6)
371#define EFLG_AF (1<<4)
372#define EFLG_PF (1<<2)
373#define EFLG_CF (1<<0)
374
62bd430e
MG		 375#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
376#define EFLG_RESERVED_ONE_MASK 2
377
6aa8b732
AK		 378/*
379 * Instruction emulation:
380 * Most instructions are emulated directly via a fragment of inline assembly
381 * code. This allows us to save/restore EFLAGS and thus very easily pick up
382 * any modified flags.
383 */
384
05b3e0c2 385#if defined(CONFIG_X86_64)
6aa8b732
AK		 386#define _LO32 "k" /* force 32-bit operand */
387#define _STK "%%rsp" /* stack pointer */
388#elif defined(__i386__)
389#define _LO32 "" /* force 32-bit operand */
390#define _STK "%%esp" /* stack pointer */
391#endif
392
393/*
394 * These EFLAGS bits are restored from saved value during emulation, and
395 * any changes are written back to the saved value after emulation.
396 */
397#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
398
399/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 400#define _PRE_EFLAGS(_sav, _msk, _tmp) \
401 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
402 "movl %"_sav",%"_LO32 _tmp"; " \
403 "push %"_tmp"; " \
404 "push %"_tmp"; " \
405 "movl %"_msk",%"_LO32 _tmp"; " \
406 "andl %"_LO32 _tmp",("_STK"); " \
407 "pushf; " \
408 "notl %"_LO32 _tmp"; " \
409 "andl %"_LO32 _tmp",("_STK"); " \
410 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
411 "pop %"_tmp"; " \
412 "orl %"_LO32 _tmp",("_STK"); " \
413 "popf; " \
414 "pop %"_sav"; "
6aa8b732
AK		 415
416/* After executing instruction: write-back necessary bits in EFLAGS. */
417#define _POST_EFLAGS(_sav, _msk, _tmp) \
418 /* _sav |= EFLAGS & _msk; */ \
419 "pushf; " \
420 "pop %"_tmp"; " \
421 "andl %"_msk",%"_LO32 _tmp"; " \
422 "orl %"_LO32 _tmp",%"_sav"; "
423
dda96d8f
AK		 424#ifdef CONFIG_X86_64
425#define ON64(x) x
426#else
427#define ON64(x)
428#endif
429
6b7ad61f
AK		 430#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
431 do { \
432 __asm__ __volatile__ ( \
433 _PRE_EFLAGS("0", "4", "2") \
434 _op _suffix " %"_x"3,%1; " \
435 _POST_EFLAGS("0", "4", "2") \
436 : "=m" (_eflags), "=m" ((_dst).val), \
437 "=&r" (_tmp) \
438 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 439 } while (0)
6b7ad61f
AK		 440
441
6aa8b732
AK		 442/* Raw emulation: instruction has two explicit operands. */
443#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 444 do { \
445 unsigned long _tmp; \
446 \
447 switch ((_dst).bytes) { \
448 case 2: \
449 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
450 break; \
451 case 4: \
452 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
453 break; \
454 case 8: \
455 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
456 break; \
457 } \
6aa8b732
AK		 458 } while (0)
459
460#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
461 do { \
6b7ad61f 462 unsigned long _tmp; \
d77c26fc 463 switch ((_dst).bytes) { \
6aa8b732 464 case 1: \
6b7ad61f 465 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 466 break; \
467 default: \
468 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
469 _wx, _wy, _lx, _ly, _qx, _qy); \
470 break; \
471 } \
472 } while (0)
473
474/* Source operand is byte-sized and may be restricted to just %cl. */
475#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
476 __emulate_2op(_op, _src, _dst, _eflags, \
477 "b", "c", "b", "c", "b", "c", "b", "c")
478
479/* Source operand is byte, word, long or quad sized. */
480#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
481 __emulate_2op(_op, _src, _dst, _eflags, \
482 "b", "q", "w", "r", _LO32, "r", "", "r")
483
484/* Source operand is word, long or quad sized. */
485#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
486 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
487 "w", "r", _LO32, "r", "", "r")
488
d175226a
GT		 489/* Instruction has three operands and one operand is stored in ECX register */
490#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
491 do { \
492 unsigned long _tmp; \
493 _type _clv = (_cl).val; \
494 _type _srcv = (_src).val; \
495 _type _dstv = (_dst).val; \
496 \
497 __asm__ __volatile__ ( \
498 _PRE_EFLAGS("0", "5", "2") \
499 _op _suffix " %4,%1 \n" \
500 _POST_EFLAGS("0", "5", "2") \
501 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
502 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
503 ); \
504 \
505 (_cl).val = (unsigned long) _clv; \
506 (_src).val = (unsigned long) _srcv; \
507 (_dst).val = (unsigned long) _dstv; \
508 } while (0)
509
510#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
511 do { \
512 switch ((_dst).bytes) { \
513 case 2: \
514 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
515 "w", unsigned short); \
516 break; \
517 case 4: \
518 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
519 "l", unsigned int); \
520 break; \
521 case 8: \
522 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
523 "q", unsigned long)); \
524 break; \
525 } \
526 } while (0)
527
dda96d8f 528#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 529 do { \
530 unsigned long _tmp; \
531 \
dda96d8f
AK		 532 __asm__ __volatile__ ( \
533 _PRE_EFLAGS("0", "3", "2") \
534 _op _suffix " %1; " \
535 _POST_EFLAGS("0", "3", "2") \
536 : "=m" (_eflags), "+m" ((_dst).val), \
537 "=&r" (_tmp) \
538 : "i" (EFLAGS_MASK)); \
539 } while (0)
540
541/* Instruction has only one explicit operand (no source operand). */
542#define emulate_1op(_op, _dst, _eflags) \
543 do { \
d77c26fc 544 switch ((_dst).bytes) { \
dda96d8f
AK		 545 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
546 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
547 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
548 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 549 } \
550 } while (0)
551
6aa8b732
AK		 552/* Fetch next part of the instruction being emulated. */
553#define insn_fetch(_type, _size, _eip) \
554({ unsigned long _x; \
62266869 555 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 556 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 557 goto done; \
558 (_eip) += (_size); \
559 (_type)_x; \
560})
561
414e6277
GN		 562#define insn_fetch_arr(_arr, _size, _eip) \
563({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
564 if (rc != X86EMUL_CONTINUE) \
565 goto done; \
566 (_eip) += (_size); \
567})
568
ddcb2885
HH		 569static inline unsigned long ad_mask(struct decode_cache *c)
570{
571 return (1UL << (c->ad_bytes << 3)) - 1;
572}
573
6aa8b732 574/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 575static inline unsigned long
576address_mask(struct decode_cache *c, unsigned long reg)
577{
578 if (c->ad_bytes == sizeof(unsigned long))
579 return reg;
580 else
581 return reg & ad_mask(c);
582}
583
584static inline unsigned long
585register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
586{
587 return base + address_mask(c, reg);
588}
589
7a957275
HH		 590static inline void
591register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
592{
593 if (c->ad_bytes == sizeof(unsigned long))
594 *reg += inc;
595 else
596 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
597}
6aa8b732 598
7a957275
HH		 599static inline void jmp_rel(struct decode_cache *c, int rel)
600{
601 register_address_increment(c, &c->eip, rel);
602}
098c937b 603
7a5b56df
AK		 604static void set_seg_override(struct decode_cache *c, int seg)
605{
606 c->has_seg_override = true;
607 c->seg_override = seg;
608}
609
79168fd1
GN		 610static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
611 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 612{
613 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
614 return 0;
615
79168fd1 616 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 617}
618
619static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 620 struct x86_emulate_ops *ops,
7a5b56df
AK		 621 struct decode_cache *c)
622{
623 if (!c->has_seg_override)
624 return 0;
625
79168fd1 626 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 627}
628
79168fd1
GN		 629static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
630 struct x86_emulate_ops *ops)
7a5b56df 631{
79168fd1 632 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 633}
634
79168fd1
GN		 635static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
636 struct x86_emulate_ops *ops)
7a5b56df 637{
79168fd1 638 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 639}
640
54b8486f
GN		 641static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
642 u32 error, bool valid)
643{
644 ctxt->exception = vec;
645 ctxt->error_code = error;
646 ctxt->error_code_valid = valid;
647 ctxt->restart = false;
648}
649
650static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
651{
652 emulate_exception(ctxt, GP_VECTOR, err, true);
653}
654
655static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
656 int err)
657{
658 ctxt->cr2 = addr;
659 emulate_exception(ctxt, PF_VECTOR, err, true);
660}
661
662static void emulate_ud(struct x86_emulate_ctxt *ctxt)
663{
664 emulate_exception(ctxt, UD_VECTOR, 0, false);
665}
666
667static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
668{
669 emulate_exception(ctxt, TS_VECTOR, err, true);
670}
671
62266869
AK		 672static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
2fb53ad8 674 unsigned long eip, u8 *dest)
62266869
AK		 675{
676 struct fetch_cache *fc = &ctxt->decode.fetch;
677 int rc;
2fb53ad8 678 int size, cur_size;
62266869 679
2fb53ad8
AK		 680 if (eip == fc->end) {
681 cur_size = fc->end - fc->start;
682 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
683 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
684 size, ctxt->vcpu, NULL);
3e2815e9 685 if (rc != X86EMUL_CONTINUE)
62266869 686 return rc;
2fb53ad8 687 fc->end += size;
62266869 688 }
2fb53ad8 689 *dest = fc->data[eip - fc->start];
3e2815e9 690 return X86EMUL_CONTINUE;
62266869
AK		 691}
692
693static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
694 struct x86_emulate_ops *ops,
695 unsigned long eip, void *dest, unsigned size)
696{
3e2815e9 697 int rc;
62266869 698
eb3c79e6 699 /* x86 instructions are limited to 15 bytes. */
063db061 700 if (eip + size - ctxt->eip > 15)
eb3c79e6 701 return X86EMUL_UNHANDLEABLE;
62266869
AK		 702 while (size--) {
703 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 704 if (rc != X86EMUL_CONTINUE)
62266869
AK		 705 return rc;
706 }
3e2815e9 707 return X86EMUL_CONTINUE;
62266869
AK		 708}
709
1e3c5cb0
RR		 710/*
711 * Given the 'reg' portion of a ModRM byte, and a register block, return a
712 * pointer into the block that addresses the relevant register.
713 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
714 */
715static void *decode_register(u8 modrm_reg, unsigned long *regs,
716 int highbyte_regs)
6aa8b732
AK		 717{
718 void *p;
719
720 p = &regs[modrm_reg];
721 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
722 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
723 return p;
724}
725
726static int read_descriptor(struct x86_emulate_ctxt *ctxt,
727 struct x86_emulate_ops *ops,
728 void *ptr,
729 u16 *size, unsigned long *address, int op_bytes)
730{
731 int rc;
732
733 if (op_bytes == 2)
734 op_bytes = 3;
735 *address = 0;
cebff02b 736 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 737 ctxt->vcpu, NULL);
1b30eaa8 738 if (rc != X86EMUL_CONTINUE)
6aa8b732 739 return rc;
cebff02b 740 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 741 ctxt->vcpu, NULL);
6aa8b732
AK		 742 return rc;
743}
744
bbe9abbd
NK		 745static int test_cc(unsigned int condition, unsigned int flags)
746{
747 int rc = 0;
748
749 switch ((condition & 15) >> 1) {
750 case 0: /* o */
751 rc |= (flags & EFLG_OF);
752 break;
753 case 1: /* b/c/nae */
754 rc |= (flags & EFLG_CF);
755 break;
756 case 2: /* z/e */
757 rc |= (flags & EFLG_ZF);
758 break;
759 case 3: /* be/na */
760 rc |= (flags & (EFLG_CF|EFLG_ZF));
761 break;
762 case 4: /* s */
763 rc |= (flags & EFLG_SF);
764 break;
765 case 5: /* p/pe */
766 rc |= (flags & EFLG_PF);
767 break;
768 case 7: /* le/ng */
769 rc |= (flags & EFLG_ZF);
770 /* fall through */
771 case 6: /* l/nge */
772 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
773 break;
774 }
775
776 /* Odd condition identifiers (lsb == 1) have inverted sense. */
777 return (!!rc ^ (condition & 1));
778}
779
3c118e24
AK		 780static void decode_register_operand(struct operand *op,
781 struct decode_cache *c,
3c118e24
AK		 782 int inhibit_bytereg)
783{
33615aa9 784 unsigned reg = c->modrm_reg;
9f1ef3f8 785 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 786
787 if (!(c->d & ModRM))
788 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 789 op->type = OP_REG;
790 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 791 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 792 op->val = *(u8 *)op->ptr;
793 op->bytes = 1;
794 } else {
33615aa9 795 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 796 op->bytes = c->op_bytes;
797 switch (op->bytes) {
798 case 2:
799 op->val = *(u16 *)op->ptr;
800 break;
801 case 4:
802 op->val = *(u32 *)op->ptr;
803 break;
804 case 8:
805 op->val = *(u64 *) op->ptr;
806 break;
807 }
808 }
809 op->orig_val = op->val;
810}
811
1c73ef66
AK		 812static int decode_modrm(struct x86_emulate_ctxt *ctxt,
813 struct x86_emulate_ops *ops)
814{
815 struct decode_cache *c = &ctxt->decode;
816 u8 sib;
f5b4edcd 817 int index_reg = 0, base_reg = 0, scale;
3e2815e9 818 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 819
820 if (c->rex_prefix) {
821 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
822 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
823 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
824 }
825
826 c->modrm = insn_fetch(u8, 1, c->eip);
827 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
828 c->modrm_reg |= (c->modrm & 0x38) >> 3;
829 c->modrm_rm |= (c->modrm & 0x07);
830 c->modrm_ea = 0;
831 c->use_modrm_ea = 1;
832
833 if (c->modrm_mod == 3) {
107d6d2e
AK		 834 c->modrm_ptr = decode_register(c->modrm_rm,
835 c->regs, c->d & ByteOp);
836 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 837 return rc;
838 }
839
840 if (c->ad_bytes == 2) {
841 unsigned bx = c->regs[VCPU_REGS_RBX];
842 unsigned bp = c->regs[VCPU_REGS_RBP];
843 unsigned si = c->regs[VCPU_REGS_RSI];
844 unsigned di = c->regs[VCPU_REGS_RDI];
845
846 /* 16-bit ModR/M decode. */
847 switch (c->modrm_mod) {
848 case 0:
849 if (c->modrm_rm == 6)
850 c->modrm_ea += insn_fetch(u16, 2, c->eip);
851 break;
852 case 1:
853 c->modrm_ea += insn_fetch(s8, 1, c->eip);
854 break;
855 case 2:
856 c->modrm_ea += insn_fetch(u16, 2, c->eip);
857 break;
858 }
859 switch (c->modrm_rm) {
860 case 0:
861 c->modrm_ea += bx + si;
862 break;
863 case 1:
864 c->modrm_ea += bx + di;
865 break;
866 case 2:
867 c->modrm_ea += bp + si;
868 break;
869 case 3:
870 c->modrm_ea += bp + di;
871 break;
872 case 4:
873 c->modrm_ea += si;
874 break;
875 case 5:
876 c->modrm_ea += di;
877 break;
878 case 6:
879 if (c->modrm_mod != 0)
880 c->modrm_ea += bp;
881 break;
882 case 7:
883 c->modrm_ea += bx;
884 break;
885 }
886 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
887 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 888 if (!c->has_seg_override)
889 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 890 c->modrm_ea = (u16)c->modrm_ea;
891 } else {
892 /* 32/64-bit ModR/M decode. */
84411d85 893 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 894 sib = insn_fetch(u8, 1, c->eip);
895 index_reg |= (sib >> 3) & 7;
896 base_reg |= sib & 7;
897 scale = sib >> 6;
898
dc71d0f1
AK		 899 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
900 c->modrm_ea += insn_fetch(s32, 4, c->eip);
901 else
1c73ef66 902 c->modrm_ea += c->regs[base_reg];
dc71d0f1 903 if (index_reg != 4)
1c73ef66 904 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 905 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
906 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 907 c->rip_relative = 1;
84411d85 908 } else
1c73ef66 909 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 910 switch (c->modrm_mod) {
911 case 0:
912 if (c->modrm_rm == 5)
913 c->modrm_ea += insn_fetch(s32, 4, c->eip);
914 break;
915 case 1:
916 c->modrm_ea += insn_fetch(s8, 1, c->eip);
917 break;
918 case 2:
919 c->modrm_ea += insn_fetch(s32, 4, c->eip);
920 break;
921 }
922 }
1c73ef66
AK		 923done:
924 return rc;
925}
926
927static int decode_abs(struct x86_emulate_ctxt *ctxt,
928 struct x86_emulate_ops *ops)
929{
930 struct decode_cache *c = &ctxt->decode;
3e2815e9 931 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 932
933 switch (c->ad_bytes) {
934 case 2:
935 c->modrm_ea = insn_fetch(u16, 2, c->eip);
936 break;
937 case 4:
938 c->modrm_ea = insn_fetch(u32, 4, c->eip);
939 break;
940 case 8:
941 c->modrm_ea = insn_fetch(u64, 8, c->eip);
942 break;
943 }
944done:
945 return rc;
946}
947
6aa8b732 948int
9aabc88f 949x86_decode_insn(struct x86_emulate_ctxt *ctxt)
6aa8b732 950{
9aabc88f 951 struct x86_emulate_ops *ops = ctxt->ops;
e4e03ded 952 struct decode_cache *c = &ctxt->decode;
3e2815e9 953 int rc = X86EMUL_CONTINUE;
6aa8b732 954 int mode = ctxt->mode;
3885d530 955 int def_op_bytes, def_ad_bytes, dual, goffset;
120df890 956 struct opcode opcode, *g_mod012, *g_mod3;
6aa8b732 957
5cd21917
GN		 958 /* we cannot decode insn before we complete previous rep insn */
959 WARN_ON(ctxt->restart);
960
063db061 961 c->eip = ctxt->eip;
2fb53ad8 962 c->fetch.start = c->fetch.end = c->eip;
79168fd1 963 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 964
965 switch (mode) {
966 case X86EMUL_MODE_REAL:
a0044755 967 case X86EMUL_MODE_VM86:
6aa8b732 968 case X86EMUL_MODE_PROT16:
f21b8bf4 969 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 970 break;
971 case X86EMUL_MODE_PROT32:
f21b8bf4 972 def_op_bytes = def_ad_bytes = 4;
6aa8b732 973 break;
05b3e0c2 974#ifdef CONFIG_X86_64
6aa8b732 975 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 976 def_op_bytes = 4;
977 def_ad_bytes = 8;
6aa8b732
AK		 978 break;
979#endif
980 default:
981 return -1;
982 }
983
f21b8bf4
AK		 984 c->op_bytes = def_op_bytes;
985 c->ad_bytes = def_ad_bytes;
986
6aa8b732 987 /* Legacy prefixes. */
b4c6abfe 988 for (;;) {
e4e03ded 989 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 990 case 0x66: /* operand-size override */
f21b8bf4
AK		 991 /* switch between 2/4 bytes */
992 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 993 break;
994 case 0x67: /* address-size override */
995 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 996 /* switch between 4/8 bytes */
f21b8bf4 997 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 998 else
e4e03ded 999 /* switch between 2/4 bytes */
f21b8bf4 1000 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 1001 break;
7a5b56df 1002 case 0x26: /* ES override */
6aa8b732 1003 case 0x2e: /* CS override */
7a5b56df 1004 case 0x36: /* SS override */
6aa8b732 1005 case 0x3e: /* DS override */
7a5b56df 1006 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1007 break;
1008 case 0x64: /* FS override */
6aa8b732 1009 case 0x65: /* GS override */
7a5b56df 1010 set_seg_override(c, c->b & 7);
6aa8b732 1011 break;
b4c6abfe
LV		 1012 case 0x40 ... 0x4f: /* REX */
1013 if (mode != X86EMUL_MODE_PROT64)
1014 goto done_prefixes;
33615aa9 1015 c->rex_prefix = c->b;
b4c6abfe 1016 continue;
6aa8b732 1017 case 0xf0: /* LOCK */
e4e03ded 1018 c->lock_prefix = 1;
6aa8b732 1019 break;
ae6200ba 1020 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1021 c->rep_prefix = REPNE_PREFIX;
1022 break;
6aa8b732 1023 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1024 c->rep_prefix = REPE_PREFIX;
6aa8b732 1025 break;
6aa8b732
AK		 1026 default:
1027 goto done_prefixes;
1028 }
b4c6abfe
LV		 1029
1030 /* Any legacy prefix after a REX prefix nullifies its effect. */
1031
33615aa9 1032 c->rex_prefix = 0;
6aa8b732
AK		 1033 }
1034
1035done_prefixes:
1036
1037 /* REX prefix. */
1c73ef66 1038 if (c->rex_prefix)
33615aa9 1039 if (c->rex_prefix & 8)
e4e03ded 1040 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1041
1042 /* Opcode byte(s). */
120df890
AK		 1043 opcode = opcode_table[c->b];
1044 if (opcode.flags == 0) {
6aa8b732 1045 /* Two-byte opcode? */
e4e03ded
LV		 1046 if (c->b == 0x0f) {
1047 c->twobyte = 1;
1048 c->b = insn_fetch(u8, 1, c->eip);
120df890 1049 opcode = twobyte_table[c->b];
6aa8b732 1050 }
e09d082c 1051 }
120df890 1052 c->d = opcode.flags;
6aa8b732 1053
e09d082c 1054 if (c->d & Group) {
52811d7d 1055 dual = c->d & GroupDual;
e09d082c
AK		 1056 c->modrm = insn_fetch(u8, 1, c->eip);
1057 --c->eip;
1058
3885d530
AK		 1059 if (c->d & GroupDual) {
1060 g_mod012 = opcode.u.gdual->mod012;
1061 g_mod3 = opcode.u.gdual->mod3;
1062 } else
1063 g_mod012 = g_mod3 = opcode.u.group;
120df890 1064
3885d530 1065 c->d &= ~(Group | GroupDual);
120df890
AK		 1066
1067 goffset = (c->modrm >> 3) & 7;
1068
1069 if ((c->modrm >> 6) == 3)
1070 opcode = g_mod3[goffset];
e09d082c 1071 else
120df890
AK		 1072 opcode = g_mod012[goffset];
1073 c->d |= opcode.flags;
e09d082c
AK		 1074 }
1075
ef65c889
AK		 1076 c->execute = opcode.u.execute;
1077
e09d082c 1078 /* Unrecognised? */
047a4818 1079 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1080 DPRINTF("Cannot emulate %02x\n", c->b);
1081 return -1;
6aa8b732
AK		 1082 }
1083
6e3d5dfb
AK		 1084 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1085 c->op_bytes = 8;
1086
6aa8b732 1087 /* ModRM and SIB bytes. */
1c73ef66
AK		 1088 if (c->d & ModRM)
1089 rc = decode_modrm(ctxt, ops);
1090 else if (c->d & MemAbs)
1091 rc = decode_abs(ctxt, ops);
3e2815e9 1092 if (rc != X86EMUL_CONTINUE)
1c73ef66 1093 goto done;
6aa8b732 1094
7a5b56df
AK		 1095 if (!c->has_seg_override)
1096 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1097
7a5b56df 1098 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1099 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1100
1101 if (c->ad_bytes != 8)
1102 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1103
1104 if (c->rip_relative)
1105 c->modrm_ea += c->eip;
1106
6aa8b732
AK		 1107 /*
1108 * Decode and fetch the source operand: register, memory
1109 * or immediate.
1110 */
e4e03ded 1111 switch (c->d & SrcMask) {
6aa8b732
AK		 1112 case SrcNone:
1113 break;
1114 case SrcReg:
9f1ef3f8 1115 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1116 break;
1117 case SrcMem16:
e4e03ded 1118 c->src.bytes = 2;
6aa8b732
AK		 1119 goto srcmem_common;
1120 case SrcMem32:
e4e03ded 1121 c->src.bytes = 4;
6aa8b732
AK		 1122 goto srcmem_common;
1123 case SrcMem:
e4e03ded
LV		 1124 c->src.bytes = (c->d & ByteOp) ? 1 :
1125 c->op_bytes;
b85b9ee9 1126 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1127 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1128 break;
d77c26fc 1129 srcmem_common:
4e62417b
AJ		 1130 /*
1131 * For instructions with a ModR/M byte, switch to register
1132 * access if Mod = 3.
1133 */
e4e03ded
LV		 1134 if ((c->d & ModRM) && c->modrm_mod == 3) {
1135 c->src.type = OP_REG;
66b85505 1136 c->src.val = c->modrm_val;
107d6d2e 1137 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1138 break;
1139 }
e4e03ded 1140 c->src.type = OP_MEM;
69f55cb1
GN		 1141 c->src.ptr = (unsigned long *)c->modrm_ea;
1142 c->src.val = 0;
6aa8b732
AK		 1143 break;
1144 case SrcImm:
c9eaf20f 1145 case SrcImmU:
e4e03ded
LV		 1146 c->src.type = OP_IMM;
1147 c->src.ptr = (unsigned long *)c->eip;
1148 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1149 if (c->src.bytes == 8)
1150 c->src.bytes = 4;
6aa8b732 1151 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1152 switch (c->src.bytes) {
6aa8b732 1153 case 1:
e4e03ded 1154 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1155 break;
1156 case 2:
e4e03ded 1157 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1158 break;
1159 case 4:
e4e03ded 1160 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1161 break;
1162 }
c9eaf20f
AK		 1163 if ((c->d & SrcMask) == SrcImmU) {
1164 switch (c->src.bytes) {
1165 case 1:
1166 c->src.val &= 0xff;
1167 break;
1168 case 2:
1169 c->src.val &= 0xffff;
1170 break;
1171 case 4:
1172 c->src.val &= 0xffffffff;
1173 break;
1174 }
1175 }
6aa8b732
AK		 1176 break;
1177 case SrcImmByte:
341de7e3 1178 case SrcImmUByte:
e4e03ded
LV		 1179 c->src.type = OP_IMM;
1180 c->src.ptr = (unsigned long *)c->eip;
1181 c->src.bytes = 1;
341de7e3
GN		 1182 if ((c->d & SrcMask) == SrcImmByte)
1183 c->src.val = insn_fetch(s8, 1, c->eip);
1184 else
1185 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1186 break;
5d55f299
WY		 1187 case SrcAcc:
1188 c->src.type = OP_REG;
1189 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1190 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1191 switch (c->src.bytes) {
1192 case 1:
1193 c->src.val = *(u8 *)c->src.ptr;
1194 break;
1195 case 2:
1196 c->src.val = *(u16 *)c->src.ptr;
1197 break;
1198 case 4:
1199 c->src.val = *(u32 *)c->src.ptr;
1200 break;
1201 case 8:
1202 c->src.val = *(u64 *)c->src.ptr;
1203 break;
1204 }
1205 break;
bfcadf83
GT		 1206 case SrcOne:
1207 c->src.bytes = 1;
1208 c->src.val = 1;
1209 break;
a682e354
GN		 1210 case SrcSI:
1211 c->src.type = OP_MEM;
1212 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1213 c->src.ptr = (unsigned long *)
79168fd1 1214 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1215 c->regs[VCPU_REGS_RSI]);
1216 c->src.val = 0;
1217 break;
414e6277
GN		 1218 case SrcImmFAddr:
1219 c->src.type = OP_IMM;
1220 c->src.ptr = (unsigned long *)c->eip;
1221 c->src.bytes = c->op_bytes + 2;
1222 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1223 break;
1224 case SrcMemFAddr:
1225 c->src.type = OP_MEM;
1226 c->src.ptr = (unsigned long *)c->modrm_ea;
1227 c->src.bytes = c->op_bytes + 2;
1228 break;
6aa8b732
AK		 1229 }
1230
0dc8d10f
GT		 1231 /*
1232 * Decode and fetch the second source operand: register, memory
1233 * or immediate.
1234 */
1235 switch (c->d & Src2Mask) {
1236 case Src2None:
1237 break;
1238 case Src2CL:
1239 c->src2.bytes = 1;
1240 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1241 break;
1242 case Src2ImmByte:
1243 c->src2.type = OP_IMM;
1244 c->src2.ptr = (unsigned long *)c->eip;
1245 c->src2.bytes = 1;
1246 c->src2.val = insn_fetch(u8, 1, c->eip);
1247 break;
1248 case Src2One:
1249 c->src2.bytes = 1;
1250 c->src2.val = 1;
1251 break;
1252 }
1253
038e51de 1254 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1255 switch (c->d & DstMask) {
038e51de
AK		 1256 case ImplicitOps:
1257 /* Special instructions do their own operand decoding. */
8b4caf66 1258 return 0;
038e51de 1259 case DstReg:
9f1ef3f8 1260 decode_register_operand(&c->dst, c,
3c118e24 1261 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1262 break;
1263 case DstMem:
6550e1f1 1264 case DstMem64:
e4e03ded 1265 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1266 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1267 c->dst.type = OP_REG;
66b85505 1268 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1269 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1270 break;
1271 }
8b4caf66 1272 c->dst.type = OP_MEM;
69f55cb1 1273 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1274 if ((c->d & DstMask) == DstMem64)
1275 c->dst.bytes = 8;
1276 else
1277 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1278 c->dst.val = 0;
1279 if (c->d & BitOp) {
1280 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1281
1282 c->dst.ptr = (void *)c->dst.ptr +
1283 (c->src.val & mask) / 8;
1284 }
8b4caf66 1285 break;
9c9fddd0
GT		 1286 case DstAcc:
1287 c->dst.type = OP_REG;
d6d367d6 1288 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1289 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1290 switch (c->dst.bytes) {
9c9fddd0
GT		 1291 case 1:
1292 c->dst.val = *(u8 *)c->dst.ptr;
1293 break;
1294 case 2:
1295 c->dst.val = *(u16 *)c->dst.ptr;
1296 break;
1297 case 4:
1298 c->dst.val = *(u32 *)c->dst.ptr;
1299 break;
d6d367d6
GN		 1300 case 8:
1301 c->dst.val = *(u64 *)c->dst.ptr;
1302 break;
9c9fddd0
GT		 1303 }
1304 c->dst.orig_val = c->dst.val;
1305 break;
a682e354
GN		 1306 case DstDI:
1307 c->dst.type = OP_MEM;
1308 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1309 c->dst.ptr = (unsigned long *)
79168fd1 1310 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1311 c->regs[VCPU_REGS_RDI]);
1312 c->dst.val = 0;
1313 break;
8b4caf66
LV		 1314 }
1315
1316done:
1317 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1318}
1319
9de41573
GN		 1320static int read_emulated(struct x86_emulate_ctxt *ctxt,
1321 struct x86_emulate_ops *ops,
1322 unsigned long addr, void *dest, unsigned size)
1323{
1324 int rc;
1325 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1326 u32 err;
9de41573
GN		 1327
1328 while (size) {
1329 int n = min(size, 8u);
1330 size -= n;
1331 if (mc->pos < mc->end)
1332 goto read_cached;
1333
8fe681e9
GN		 1334 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1335 ctxt->vcpu);
1336 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1337 emulate_pf(ctxt, addr, err);
9de41573
GN		 1338 if (rc != X86EMUL_CONTINUE)
1339 return rc;
1340 mc->end += n;
1341
1342 read_cached:
1343 memcpy(dest, mc->data + mc->pos, n);
1344 mc->pos += n;
1345 dest += n;
1346 addr += n;
1347 }
1348 return X86EMUL_CONTINUE;
1349}
1350
7b262e90
GN		 1351static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1352 struct x86_emulate_ops *ops,
1353 unsigned int size, unsigned short port,
1354 void *dest)
1355{
1356 struct read_cache *rc = &ctxt->decode.io_read;
1357
1358 if (rc->pos == rc->end) { /* refill pio read ahead */
1359 struct decode_cache *c = &ctxt->decode;
1360 unsigned int in_page, n;
1361 unsigned int count = c->rep_prefix ?
1362 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1363 in_page = (ctxt->eflags & EFLG_DF) ?
1364 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1365 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1366 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1367 count);
1368 if (n == 0)
1369 n = 1;
1370 rc->pos = rc->end = 0;
1371 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1372 return 0;
1373 rc->end = n * size;
1374 }
1375
1376 memcpy(dest, rc->data + rc->pos, size);
1377 rc->pos += size;
1378 return 1;
1379}
1380
38ba30ba
GN		 1381static u32 desc_limit_scaled(struct desc_struct *desc)
1382{
1383 u32 limit = get_desc_limit(desc);
1384
1385 return desc->g ? (limit << 12) | 0xfff : limit;
1386}
1387
1388static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1389 struct x86_emulate_ops *ops,
1390 u16 selector, struct desc_ptr *dt)
1391{
1392 if (selector & 1 << 2) {
1393 struct desc_struct desc;
1394 memset (dt, 0, sizeof *dt);
1395 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1396 return;
1397
1398 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1399 dt->address = get_desc_base(&desc);
1400 } else
1401 ops->get_gdt(dt, ctxt->vcpu);
1402}
1403
1404/* allowed just for 8 bytes segments */
1405static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1406 struct x86_emulate_ops *ops,
1407 u16 selector, struct desc_struct *desc)
1408{
1409 struct desc_ptr dt;
1410 u16 index = selector >> 3;
1411 int ret;
1412 u32 err;
1413 ulong addr;
1414
1415 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1416
1417 if (dt.size < index * 8 + 7) {
54b8486f 1418 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1419 return X86EMUL_PROPAGATE_FAULT;
1420 }
1421 addr = dt.address + index * 8;
1422 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1423 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1424 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1425
1426 return ret;
1427}
1428
1429/* allowed just for 8 bytes segments */
1430static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1431 struct x86_emulate_ops *ops,
1432 u16 selector, struct desc_struct *desc)
1433{
1434 struct desc_ptr dt;
1435 u16 index = selector >> 3;
1436 u32 err;
1437 ulong addr;
1438 int ret;
1439
1440 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1441
1442 if (dt.size < index * 8 + 7) {
54b8486f 1443 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1444 return X86EMUL_PROPAGATE_FAULT;
1445 }
1446
1447 addr = dt.address + index * 8;
1448 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1449 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1450 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1451
1452 return ret;
1453}
1454
1455static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1456 struct x86_emulate_ops *ops,
1457 u16 selector, int seg)
1458{
1459 struct desc_struct seg_desc;
1460 u8 dpl, rpl, cpl;
1461 unsigned err_vec = GP_VECTOR;
1462 u32 err_code = 0;
1463 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1464 int ret;
1465
1466 memset(&seg_desc, 0, sizeof seg_desc);
1467
1468 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1469 || ctxt->mode == X86EMUL_MODE_REAL) {
1470 /* set real mode segment descriptor */
1471 set_desc_base(&seg_desc, selector << 4);
1472 set_desc_limit(&seg_desc, 0xffff);
1473 seg_desc.type = 3;
1474 seg_desc.p = 1;
1475 seg_desc.s = 1;
1476 goto load;
1477 }
1478
1479 /* NULL selector is not valid for TR, CS and SS */
1480 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1481 && null_selector)
1482 goto exception;
1483
1484 /* TR should be in GDT only */
1485 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1486 goto exception;
1487
1488 if (null_selector) /* for NULL selector skip all following checks */
1489 goto load;
1490
1491 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1492 if (ret != X86EMUL_CONTINUE)
1493 return ret;
1494
1495 err_code = selector & 0xfffc;
1496 err_vec = GP_VECTOR;
1497
1498 /* can't load system descriptor into segment selecor */
1499 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1500 goto exception;
1501
1502 if (!seg_desc.p) {
1503 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1504 goto exception;
1505 }
1506
1507 rpl = selector & 3;
1508 dpl = seg_desc.dpl;
1509 cpl = ops->cpl(ctxt->vcpu);
1510
1511 switch (seg) {
1512 case VCPU_SREG_SS:
1513 /*
1514 * segment is not a writable data segment or segment
1515 * selector's RPL != CPL or segment selector's RPL != CPL
1516 */
1517 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1518 goto exception;
1519 break;
1520 case VCPU_SREG_CS:
1521 if (!(seg_desc.type & 8))
1522 goto exception;
1523
1524 if (seg_desc.type & 4) {
1525 /* conforming */
1526 if (dpl > cpl)
1527 goto exception;
1528 } else {
1529 /* nonconforming */
1530 if (rpl > cpl || dpl != cpl)
1531 goto exception;
1532 }
1533 /* CS(RPL) <- CPL */
1534 selector = (selector & 0xfffc) | cpl;
1535 break;
1536 case VCPU_SREG_TR:
1537 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1538 goto exception;
1539 break;
1540 case VCPU_SREG_LDTR:
1541 if (seg_desc.s || seg_desc.type != 2)
1542 goto exception;
1543 break;
1544 default: /* DS, ES, FS, or GS */
1545 /*
1546 * segment is not a data or readable code segment or
1547 * ((segment is a data or nonconforming code segment)
1548 * and (both RPL and CPL > DPL))
1549 */
1550 if ((seg_desc.type & 0xa) == 0x8 ||
1551 (((seg_desc.type & 0xc) != 0xc) &&
1552 (rpl > dpl && cpl > dpl)))
1553 goto exception;
1554 break;
1555 }
1556
1557 if (seg_desc.s) {
1558 /* mark segment as accessed */
1559 seg_desc.type |= 1;
1560 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1561 if (ret != X86EMUL_CONTINUE)
1562 return ret;
1563 }
1564load:
1565 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1566 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1567 return X86EMUL_CONTINUE;
1568exception:
54b8486f 1569 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1570 return X86EMUL_PROPAGATE_FAULT;
1571}
1572
c37eda13
WY		 1573static inline int writeback(struct x86_emulate_ctxt *ctxt,
1574 struct x86_emulate_ops *ops)
1575{
1576 int rc;
1577 struct decode_cache *c = &ctxt->decode;
1578 u32 err;
1579
1580 switch (c->dst.type) {
1581 case OP_REG:
1582 /* The 4-byte case *is* correct:
1583 * in 64-bit mode we zero-extend.
1584 */
1585 switch (c->dst.bytes) {
1586 case 1:
1587 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1588 break;
1589 case 2:
1590 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1591 break;
1592 case 4:
1593 *c->dst.ptr = (u32)c->dst.val;
1594 break; /* 64b: zero-ext */
1595 case 8:
1596 *c->dst.ptr = c->dst.val;
1597 break;
1598 }
1599 break;
1600 case OP_MEM:
1601 if (c->lock_prefix)
1602 rc = ops->cmpxchg_emulated(
1603 (unsigned long)c->dst.ptr,
1604 &c->dst.orig_val,
1605 &c->dst.val,
1606 c->dst.bytes,
1607 &err,
1608 ctxt->vcpu);
1609 else
1610 rc = ops->write_emulated(
1611 (unsigned long)c->dst.ptr,
1612 &c->dst.val,
1613 c->dst.bytes,
1614 &err,
1615 ctxt->vcpu);
1616 if (rc == X86EMUL_PROPAGATE_FAULT)
1617 emulate_pf(ctxt,
1618 (unsigned long)c->dst.ptr, err);
1619 if (rc != X86EMUL_CONTINUE)
1620 return rc;
1621 break;
1622 case OP_NONE:
1623 /* no writeback */
1624 break;
1625 default:
1626 break;
1627 }
1628 return X86EMUL_CONTINUE;
1629}
1630
79168fd1
GN		 1631static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1632 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1633{
1634 struct decode_cache *c = &ctxt->decode;
1635
1636 c->dst.type = OP_MEM;
1637 c->dst.bytes = c->op_bytes;
1638 c->dst.val = c->src.val;
7a957275 1639 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1640 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1641 c->regs[VCPU_REGS_RSP]);
1642}
1643
faa5a3ae 1644static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1645 struct x86_emulate_ops *ops,
1646 void *dest, int len)
8cdbd2c9
LV		 1647{
1648 struct decode_cache *c = &ctxt->decode;
1649 int rc;
1650
79168fd1 1651 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1652 c->regs[VCPU_REGS_RSP]),
1653 dest, len);
b60d513c 1654 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1655 return rc;
1656
350f69dc 1657 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1658 return rc;
1659}
8cdbd2c9 1660
d4c6a154
GN		 1661static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1662 struct x86_emulate_ops *ops,
1663 void *dest, int len)
1664{
1665 int rc;
1666 unsigned long val, change_mask;
1667 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1668 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1669
1670 rc = emulate_pop(ctxt, ops, &val, len);
1671 if (rc != X86EMUL_CONTINUE)
1672 return rc;
1673
1674 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1675 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1676
1677 switch(ctxt->mode) {
1678 case X86EMUL_MODE_PROT64:
1679 case X86EMUL_MODE_PROT32:
1680 case X86EMUL_MODE_PROT16:
1681 if (cpl == 0)
1682 change_mask |= EFLG_IOPL;
1683 if (cpl <= iopl)
1684 change_mask |= EFLG_IF;
1685 break;
1686 case X86EMUL_MODE_VM86:
1687 if (iopl < 3) {
54b8486f 1688 emulate_gp(ctxt, 0);
d4c6a154
GN		 1689 return X86EMUL_PROPAGATE_FAULT;
1690 }
1691 change_mask |= EFLG_IF;
1692 break;
1693 default: /* real mode */
1694 change_mask |= (EFLG_IOPL | EFLG_IF);
1695 break;
1696 }
1697
1698 *(unsigned long *)dest =
1699 (ctxt->eflags & ~change_mask) | (val & change_mask);
1700
1701 return rc;
1702}
1703
79168fd1
GN		 1704static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1705 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1706{
1707 struct decode_cache *c = &ctxt->decode;
0934ac9d 1708
79168fd1 1709 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1710
79168fd1 1711 emulate_push(ctxt, ops);
0934ac9d
MG		 1712}
1713
1714static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1715 struct x86_emulate_ops *ops, int seg)
1716{
1717 struct decode_cache *c = &ctxt->decode;
1718 unsigned long selector;
1719 int rc;
1720
1721 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1722 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1723 return rc;
1724
2e873022 1725 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1726 return rc;
1727}
1728
c37eda13 1729static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1730 struct x86_emulate_ops *ops)
abcf14b5
MG		 1731{
1732 struct decode_cache *c = &ctxt->decode;
1733 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1734 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1735 int reg = VCPU_REGS_RAX;
1736
1737 while (reg <= VCPU_REGS_RDI) {
1738 (reg == VCPU_REGS_RSP) ?
1739 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1740
79168fd1 1741 emulate_push(ctxt, ops);
c37eda13
WY		 1742
1743 rc = writeback(ctxt, ops);
1744 if (rc != X86EMUL_CONTINUE)
1745 return rc;
1746
abcf14b5
MG		 1747 ++reg;
1748 }
c37eda13
WY		 1749
1750 /* Disable writeback. */
1751 c->dst.type = OP_NONE;
1752
1753 return rc;
abcf14b5
MG		 1754}
1755
1756static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1757 struct x86_emulate_ops *ops)
1758{
1759 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1760 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1761 int reg = VCPU_REGS_RDI;
1762
1763 while (reg >= VCPU_REGS_RAX) {
1764 if (reg == VCPU_REGS_RSP) {
1765 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1766 c->op_bytes);
1767 --reg;
1768 }
1769
1770 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1771 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1772 break;
1773 --reg;
1774 }
1775 return rc;
1776}
1777
62bd430e
MG		 1778static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1779 struct x86_emulate_ops *ops)
1780{
1781 struct decode_cache *c = &ctxt->decode;
1782 int rc = X86EMUL_CONTINUE;
1783 unsigned long temp_eip = 0;
1784 unsigned long temp_eflags = 0;
1785 unsigned long cs = 0;
1786 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1787 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1788 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1789 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1790
1791 /* TODO: Add stack limit check */
1792
1793 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1794
1795 if (rc != X86EMUL_CONTINUE)
1796 return rc;
1797
1798 if (temp_eip & ~0xffff) {
1799 emulate_gp(ctxt, 0);
1800 return X86EMUL_PROPAGATE_FAULT;
1801 }
1802
1803 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1804
1805 if (rc != X86EMUL_CONTINUE)
1806 return rc;
1807
1808 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1809
1810 if (rc != X86EMUL_CONTINUE)
1811 return rc;
1812
1813 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1814
1815 if (rc != X86EMUL_CONTINUE)
1816 return rc;
1817
1818 c->eip = temp_eip;
1819
1820
1821 if (c->op_bytes == 4)
1822 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1823 else if (c->op_bytes == 2) {
1824 ctxt->eflags &= ~0xffff;
1825 ctxt->eflags |= temp_eflags;
1826 }
1827
1828 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1829 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1830
1831 return rc;
1832}
1833
1834static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1835 struct x86_emulate_ops* ops)
1836{
1837 switch(ctxt->mode) {
1838 case X86EMUL_MODE_REAL:
1839 return emulate_iret_real(ctxt, ops);
1840 case X86EMUL_MODE_VM86:
1841 case X86EMUL_MODE_PROT16:
1842 case X86EMUL_MODE_PROT32:
1843 case X86EMUL_MODE_PROT64:
1844 default:
1845 /* iret from protected mode unimplemented yet */
1846 return X86EMUL_UNHANDLEABLE;
1847 }
1848}
1849
faa5a3ae
AK		 1850static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1851 struct x86_emulate_ops *ops)
1852{
1853 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1854
1b30eaa8 1855 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1856}
1857
05f086f8 1858static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1859{
05f086f8 1860 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1861 switch (c->modrm_reg) {
1862 case 0: /* rol */
05f086f8 1863 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1864 break;
1865 case 1: /* ror */
05f086f8 1866 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1867 break;
1868 case 2: /* rcl */
05f086f8 1869 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1870 break;
1871 case 3: /* rcr */
05f086f8 1872 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1873 break;
1874 case 4: /* sal/shl */
1875 case 6: /* sal/shl */
05f086f8 1876 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1877 break;
1878 case 5: /* shr */
05f086f8 1879 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1880 break;
1881 case 7: /* sar */
05f086f8 1882 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1883 break;
1884 }
1885}
1886
1887static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1888 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1889{
1890 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1891
1892 switch (c->modrm_reg) {
1893 case 0 ... 1: /* test */
05f086f8 1894 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1895 break;
1896 case 2: /* not */
1897 c->dst.val = ~c->dst.val;
1898 break;
1899 case 3: /* neg */
05f086f8 1900 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1901 break;
1902 default:
aca06a83 1903 return 0;
8cdbd2c9 1904 }
aca06a83 1905 return 1;
8cdbd2c9
LV		 1906}
1907
1908static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1909 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1910{
1911 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1912
1913 switch (c->modrm_reg) {
1914 case 0: /* inc */
05f086f8 1915 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1916 break;
1917 case 1: /* dec */
05f086f8 1918 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1919 break;
d19292e4
MG		 1920 case 2: /* call near abs */ {
1921 long int old_eip;
1922 old_eip = c->eip;
1923 c->eip = c->src.val;
1924 c->src.val = old_eip;
79168fd1 1925 emulate_push(ctxt, ops);
d19292e4
MG		 1926 break;
1927 }
8cdbd2c9 1928 case 4: /* jmp abs */
fd60754e 1929 c->eip = c->src.val;
8cdbd2c9
LV		 1930 break;
1931 case 6: /* push */
79168fd1 1932 emulate_push(ctxt, ops);
8cdbd2c9 1933 break;
8cdbd2c9 1934 }
1b30eaa8 1935 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1936}
1937
1938static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1939 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1940{
1941 struct decode_cache *c = &ctxt->decode;
16518d5a 1942 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1943
1944 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1945 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1946 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1947 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1948 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1949 } else {
16518d5a
AK		 1950 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1951 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1952
05f086f8 1953 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1954 }
1b30eaa8 1955 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1956}
1957
a77ab5ea
AK		 1958static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1959 struct x86_emulate_ops *ops)
1960{
1961 struct decode_cache *c = &ctxt->decode;
1962 int rc;
1963 unsigned long cs;
1964
1965 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1966 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1967 return rc;
1968 if (c->op_bytes == 4)
1969 c->eip = (u32)c->eip;
1970 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1971 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1972 return rc;
2e873022 1973 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1974 return rc;
1975}
1976
e66bb2cc
AP		 1977static inline void
1978setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1979 struct x86_emulate_ops *ops, struct desc_struct *cs,
1980 struct desc_struct *ss)
e66bb2cc 1981{
79168fd1
GN		 1982 memset(cs, 0, sizeof(struct desc_struct));
1983 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1984 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1985
1986 cs->l = 0; /* will be adjusted later */
79168fd1 1987 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1988 cs->g = 1; /* 4kb granularity */
79168fd1 1989 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1990 cs->type = 0x0b; /* Read, Execute, Accessed */
1991 cs->s = 1;
1992 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1993 cs->p = 1;
1994 cs->d = 1;
e66bb2cc 1995
79168fd1
GN		 1996 set_desc_base(ss, 0); /* flat segment */
1997 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1998 ss->g = 1; /* 4kb granularity */
1999 ss->s = 1;
2000 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2001 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2002 ss->dpl = 0;
79168fd1 2003 ss->p = 1;
e66bb2cc
AP		 2004}
2005
2006static int
3fb1b5db 2007emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 2008{
2009 struct decode_cache *c = &ctxt->decode;
79168fd1 2010 struct desc_struct cs, ss;
e66bb2cc 2011 u64 msr_data;
79168fd1 2012 u16 cs_sel, ss_sel;
e66bb2cc
AP		 2013
2014 /* syscall is not available in real mode */
2e901c4c
GN		 2015 if (ctxt->mode == X86EMUL_MODE_REAL ||
2016 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2017 emulate_ud(ctxt);
2e901c4c
GN		 2018 return X86EMUL_PROPAGATE_FAULT;
2019 }
e66bb2cc 2020
79168fd1 2021 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 2022
3fb1b5db 2023 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 2024 msr_data >>= 32;
79168fd1
GN		 2025 cs_sel = (u16)(msr_data & 0xfffc);
2026 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 2027
2028 if (is_long_mode(ctxt->vcpu)) {
79168fd1 2029 cs.d = 0;
e66bb2cc
AP		 2030 cs.l = 1;
2031 }
79168fd1
GN		 2032 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2033 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2034 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2035 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2036
2037 c->regs[VCPU_REGS_RCX] = c->eip;
2038 if (is_long_mode(ctxt->vcpu)) {
2039#ifdef CONFIG_X86_64
2040 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2041
3fb1b5db
GN		 2042 ops->get_msr(ctxt->vcpu,
2043 ctxt->mode == X86EMUL_MODE_PROT64 ?
2044 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2045 c->eip = msr_data;
2046
3fb1b5db 2047 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2048 ctxt->eflags &= ~(msr_data | EFLG_RF);
2049#endif
2050 } else {
2051 /* legacy mode */
3fb1b5db 2052 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2053 c->eip = (u32)msr_data;
2054
2055 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2056 }
2057
e54cfa97 2058 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2059}
2060
8c604352 2061static int
3fb1b5db 2062emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2063{
2064 struct decode_cache *c = &ctxt->decode;
79168fd1 2065 struct desc_struct cs, ss;
8c604352 2066 u64 msr_data;
79168fd1 2067 u16 cs_sel, ss_sel;
8c604352 2068
a0044755
GN		 2069 /* inject #GP if in real mode */
2070 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2071 emulate_gp(ctxt, 0);
2e901c4c 2072 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2073 }
2074
2075 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2076 * Therefore, we inject an #UD.
2077 */
2e901c4c 2078 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2079 emulate_ud(ctxt);
2e901c4c
GN		 2080 return X86EMUL_PROPAGATE_FAULT;
2081 }
8c604352 2082
79168fd1 2083 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2084
3fb1b5db 2085 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2086 switch (ctxt->mode) {
2087 case X86EMUL_MODE_PROT32:
2088 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2089 emulate_gp(ctxt, 0);
e54cfa97 2090 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2091 }
2092 break;
2093 case X86EMUL_MODE_PROT64:
2094 if (msr_data == 0x0) {
54b8486f 2095 emulate_gp(ctxt, 0);
e54cfa97 2096 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2097 }
2098 break;
2099 }
2100
2101 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2102 cs_sel = (u16)msr_data;
2103 cs_sel &= ~SELECTOR_RPL_MASK;
2104 ss_sel = cs_sel + 8;
2105 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2106 if (ctxt->mode == X86EMUL_MODE_PROT64
2107 || is_long_mode(ctxt->vcpu)) {
79168fd1 2108 cs.d = 0;
8c604352
AP		 2109 cs.l = 1;
2110 }
2111
79168fd1
GN		 2112 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2113 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2114 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2115 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2116
3fb1b5db 2117 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2118 c->eip = msr_data;
2119
3fb1b5db 2120 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2121 c->regs[VCPU_REGS_RSP] = msr_data;
2122
e54cfa97 2123 return X86EMUL_CONTINUE;
8c604352
AP		 2124}
2125
4668f050 2126static int
3fb1b5db 2127emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2128{
2129 struct decode_cache *c = &ctxt->decode;
79168fd1 2130 struct desc_struct cs, ss;
4668f050
AP		 2131 u64 msr_data;
2132 int usermode;
79168fd1 2133 u16 cs_sel, ss_sel;
4668f050 2134
a0044755
GN		 2135 /* inject #GP if in real mode or Virtual 8086 mode */
2136 if (ctxt->mode == X86EMUL_MODE_REAL ||
2137 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2138 emulate_gp(ctxt, 0);
2e901c4c 2139 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2140 }
2141
79168fd1 2142 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2143
2144 if ((c->rex_prefix & 0x8) != 0x0)
2145 usermode = X86EMUL_MODE_PROT64;
2146 else
2147 usermode = X86EMUL_MODE_PROT32;
2148
2149 cs.dpl = 3;
2150 ss.dpl = 3;
3fb1b5db 2151 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2152 switch (usermode) {
2153 case X86EMUL_MODE_PROT32:
79168fd1 2154 cs_sel = (u16)(msr_data + 16);
4668f050 2155 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2156 emulate_gp(ctxt, 0);
e54cfa97 2157 return X86EMUL_PROPAGATE_FAULT;
4668f050 2158 }
79168fd1 2159 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2160 break;
2161 case X86EMUL_MODE_PROT64:
79168fd1 2162 cs_sel = (u16)(msr_data + 32);
4668f050 2163 if (msr_data == 0x0) {
54b8486f 2164 emulate_gp(ctxt, 0);
e54cfa97 2165 return X86EMUL_PROPAGATE_FAULT;
4668f050 2166 }
79168fd1
GN		 2167 ss_sel = cs_sel + 8;
2168 cs.d = 0;
4668f050
AP		 2169 cs.l = 1;
2170 break;
2171 }
79168fd1
GN		 2172 cs_sel |= SELECTOR_RPL_MASK;
2173 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2174
79168fd1
GN		 2175 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2176 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2177 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2178 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2179
bdb475a3
GN		 2180 c->eip = c->regs[VCPU_REGS_RDX];
2181 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2182
e54cfa97 2183 return X86EMUL_CONTINUE;
4668f050
AP		 2184}
2185
9c537244
GN		 2186static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2187 struct x86_emulate_ops *ops)
f850e2e6
GN		 2188{
2189 int iopl;
2190 if (ctxt->mode == X86EMUL_MODE_REAL)
2191 return false;
2192 if (ctxt->mode == X86EMUL_MODE_VM86)
2193 return true;
2194 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2195 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2196}
2197
2198static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2199 struct x86_emulate_ops *ops,
2200 u16 port, u16 len)
2201{
79168fd1 2202 struct desc_struct tr_seg;
f850e2e6
GN		 2203 int r;
2204 u16 io_bitmap_ptr;
2205 u8 perm, bit_idx = port & 0x7;
2206 unsigned mask = (1 << len) - 1;
2207
79168fd1
GN		 2208 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2209 if (!tr_seg.p)
f850e2e6 2210 return false;
79168fd1 2211 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2212 return false;
79168fd1
GN		 2213 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2214 ctxt->vcpu, NULL);
f850e2e6
GN		 2215 if (r != X86EMUL_CONTINUE)
2216 return false;
79168fd1 2217 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2218 return false;
79168fd1
GN		 2219 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2220 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2221 if (r != X86EMUL_CONTINUE)
2222 return false;
2223 if ((perm >> bit_idx) & mask)
2224 return false;
2225 return true;
2226}
2227
2228static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2229 struct x86_emulate_ops *ops,
2230 u16 port, u16 len)
2231{
9c537244 2232 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2233 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2234 return false;
2235 return true;
2236}
2237
38ba30ba
GN		 2238static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2239 struct x86_emulate_ops *ops,
2240 struct tss_segment_16 *tss)
2241{
2242 struct decode_cache *c = &ctxt->decode;
2243
2244 tss->ip = c->eip;
2245 tss->flag = ctxt->eflags;
2246 tss->ax = c->regs[VCPU_REGS_RAX];
2247 tss->cx = c->regs[VCPU_REGS_RCX];
2248 tss->dx = c->regs[VCPU_REGS_RDX];
2249 tss->bx = c->regs[VCPU_REGS_RBX];
2250 tss->sp = c->regs[VCPU_REGS_RSP];
2251 tss->bp = c->regs[VCPU_REGS_RBP];
2252 tss->si = c->regs[VCPU_REGS_RSI];
2253 tss->di = c->regs[VCPU_REGS_RDI];
2254
2255 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2256 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2257 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2258 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2259 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2260}
2261
2262static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2263 struct x86_emulate_ops *ops,
2264 struct tss_segment_16 *tss)
2265{
2266 struct decode_cache *c = &ctxt->decode;
2267 int ret;
2268
2269 c->eip = tss->ip;
2270 ctxt->eflags = tss->flag | 2;
2271 c->regs[VCPU_REGS_RAX] = tss->ax;
2272 c->regs[VCPU_REGS_RCX] = tss->cx;
2273 c->regs[VCPU_REGS_RDX] = tss->dx;
2274 c->regs[VCPU_REGS_RBX] = tss->bx;
2275 c->regs[VCPU_REGS_RSP] = tss->sp;
2276 c->regs[VCPU_REGS_RBP] = tss->bp;
2277 c->regs[VCPU_REGS_RSI] = tss->si;
2278 c->regs[VCPU_REGS_RDI] = tss->di;
2279
2280 /*
2281 * SDM says that segment selectors are loaded before segment
2282 * descriptors
2283 */
2284 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2285 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2286 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2287 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2288 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2289
2290 /*
2291 * Now load segment descriptors. If fault happenes at this stage
2292 * it is handled in a context of new task
2293 */
2294 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2295 if (ret != X86EMUL_CONTINUE)
2296 return ret;
2297 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2298 if (ret != X86EMUL_CONTINUE)
2299 return ret;
2300 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2301 if (ret != X86EMUL_CONTINUE)
2302 return ret;
2303 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2304 if (ret != X86EMUL_CONTINUE)
2305 return ret;
2306 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2307 if (ret != X86EMUL_CONTINUE)
2308 return ret;
2309
2310 return X86EMUL_CONTINUE;
2311}
2312
2313static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2314 struct x86_emulate_ops *ops,
2315 u16 tss_selector, u16 old_tss_sel,
2316 ulong old_tss_base, struct desc_struct *new_desc)
2317{
2318 struct tss_segment_16 tss_seg;
2319 int ret;
2320 u32 err, new_tss_base = get_desc_base(new_desc);
2321
2322 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2323 &err);
2324 if (ret == X86EMUL_PROPAGATE_FAULT) {
2325 /* FIXME: need to provide precise fault address */
54b8486f 2326 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2327 return ret;
2328 }
2329
2330 save_state_to_tss16(ctxt, ops, &tss_seg);
2331
2332 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2333 &err);
2334 if (ret == X86EMUL_PROPAGATE_FAULT) {
2335 /* FIXME: need to provide precise fault address */
54b8486f 2336 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2337 return ret;
2338 }
2339
2340 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2341 &err);
2342 if (ret == X86EMUL_PROPAGATE_FAULT) {
2343 /* FIXME: need to provide precise fault address */
54b8486f 2344 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2345 return ret;
2346 }
2347
2348 if (old_tss_sel != 0xffff) {
2349 tss_seg.prev_task_link = old_tss_sel;
2350
2351 ret = ops->write_std(new_tss_base,
2352 &tss_seg.prev_task_link,
2353 sizeof tss_seg.prev_task_link,
2354 ctxt->vcpu, &err);
2355 if (ret == X86EMUL_PROPAGATE_FAULT) {
2356 /* FIXME: need to provide precise fault address */
54b8486f 2357 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2358 return ret;
2359 }
2360 }
2361
2362 return load_state_from_tss16(ctxt, ops, &tss_seg);
2363}
2364
2365static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2366 struct x86_emulate_ops *ops,
2367 struct tss_segment_32 *tss)
2368{
2369 struct decode_cache *c = &ctxt->decode;
2370
2371 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2372 tss->eip = c->eip;
2373 tss->eflags = ctxt->eflags;
2374 tss->eax = c->regs[VCPU_REGS_RAX];
2375 tss->ecx = c->regs[VCPU_REGS_RCX];
2376 tss->edx = c->regs[VCPU_REGS_RDX];
2377 tss->ebx = c->regs[VCPU_REGS_RBX];
2378 tss->esp = c->regs[VCPU_REGS_RSP];
2379 tss->ebp = c->regs[VCPU_REGS_RBP];
2380 tss->esi = c->regs[VCPU_REGS_RSI];
2381 tss->edi = c->regs[VCPU_REGS_RDI];
2382
2383 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2384 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2385 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2386 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2387 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2388 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2389 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2390}
2391
2392static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2393 struct x86_emulate_ops *ops,
2394 struct tss_segment_32 *tss)
2395{
2396 struct decode_cache *c = &ctxt->decode;
2397 int ret;
2398
0f12244f 2399 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2400 emulate_gp(ctxt, 0);
0f12244f
GN		 2401 return X86EMUL_PROPAGATE_FAULT;
2402 }
38ba30ba
GN		 2403 c->eip = tss->eip;
2404 ctxt->eflags = tss->eflags | 2;
2405 c->regs[VCPU_REGS_RAX] = tss->eax;
2406 c->regs[VCPU_REGS_RCX] = tss->ecx;
2407 c->regs[VCPU_REGS_RDX] = tss->edx;
2408 c->regs[VCPU_REGS_RBX] = tss->ebx;
2409 c->regs[VCPU_REGS_RSP] = tss->esp;
2410 c->regs[VCPU_REGS_RBP] = tss->ebp;
2411 c->regs[VCPU_REGS_RSI] = tss->esi;
2412 c->regs[VCPU_REGS_RDI] = tss->edi;
2413
2414 /*
2415 * SDM says that segment selectors are loaded before segment
2416 * descriptors
2417 */
2418 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2419 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2420 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2421 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2422 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2423 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2424 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2425
2426 /*
2427 * Now load segment descriptors. If fault happenes at this stage
2428 * it is handled in a context of new task
2429 */
2430 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2431 if (ret != X86EMUL_CONTINUE)
2432 return ret;
2433 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2434 if (ret != X86EMUL_CONTINUE)
2435 return ret;
2436 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2437 if (ret != X86EMUL_CONTINUE)
2438 return ret;
2439 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2440 if (ret != X86EMUL_CONTINUE)
2441 return ret;
2442 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2443 if (ret != X86EMUL_CONTINUE)
2444 return ret;
2445 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2446 if (ret != X86EMUL_CONTINUE)
2447 return ret;
2448 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2449 if (ret != X86EMUL_CONTINUE)
2450 return ret;
2451
2452 return X86EMUL_CONTINUE;
2453}
2454
2455static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2456 struct x86_emulate_ops *ops,
2457 u16 tss_selector, u16 old_tss_sel,
2458 ulong old_tss_base, struct desc_struct *new_desc)
2459{
2460 struct tss_segment_32 tss_seg;
2461 int ret;
2462 u32 err, new_tss_base = get_desc_base(new_desc);
2463
2464 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2465 &err);
2466 if (ret == X86EMUL_PROPAGATE_FAULT) {
2467 /* FIXME: need to provide precise fault address */
54b8486f 2468 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2469 return ret;
2470 }
2471
2472 save_state_to_tss32(ctxt, ops, &tss_seg);
2473
2474 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2475 &err);
2476 if (ret == X86EMUL_PROPAGATE_FAULT) {
2477 /* FIXME: need to provide precise fault address */
54b8486f 2478 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2479 return ret;
2480 }
2481
2482 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2483 &err);
2484 if (ret == X86EMUL_PROPAGATE_FAULT) {
2485 /* FIXME: need to provide precise fault address */
54b8486f 2486 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2487 return ret;
2488 }
2489
2490 if (old_tss_sel != 0xffff) {
2491 tss_seg.prev_task_link = old_tss_sel;
2492
2493 ret = ops->write_std(new_tss_base,
2494 &tss_seg.prev_task_link,
2495 sizeof tss_seg.prev_task_link,
2496 ctxt->vcpu, &err);
2497 if (ret == X86EMUL_PROPAGATE_FAULT) {
2498 /* FIXME: need to provide precise fault address */
54b8486f 2499 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2500 return ret;
2501 }
2502 }
2503
2504 return load_state_from_tss32(ctxt, ops, &tss_seg);
2505}
2506
2507static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2508 struct x86_emulate_ops *ops,
2509 u16 tss_selector, int reason,
2510 bool has_error_code, u32 error_code)
38ba30ba
GN		 2511{
2512 struct desc_struct curr_tss_desc, next_tss_desc;
2513 int ret;
2514 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2515 ulong old_tss_base =
5951c442 2516 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2517 u32 desc_limit;
38ba30ba
GN		 2518
2519 /* FIXME: old_tss_base == ~0 ? */
2520
2521 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2522 if (ret != X86EMUL_CONTINUE)
2523 return ret;
2524 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2525 if (ret != X86EMUL_CONTINUE)
2526 return ret;
2527
2528 /* FIXME: check that next_tss_desc is tss */
2529
2530 if (reason != TASK_SWITCH_IRET) {
2531 if ((tss_selector & 3) > next_tss_desc.dpl ||
2532 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2533 emulate_gp(ctxt, 0);
38ba30ba
GN		 2534 return X86EMUL_PROPAGATE_FAULT;
2535 }
2536 }
2537
ceffb459
GN		 2538 desc_limit = desc_limit_scaled(&next_tss_desc);
2539 if (!next_tss_desc.p ||
2540 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2541 desc_limit < 0x2b)) {
54b8486f 2542 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2543 return X86EMUL_PROPAGATE_FAULT;
2544 }
2545
2546 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2547 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2548 write_segment_descriptor(ctxt, ops, old_tss_sel,
2549 &curr_tss_desc);
2550 }
2551
2552 if (reason == TASK_SWITCH_IRET)
2553 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2554
2555 /* set back link to prev task only if NT bit is set in eflags
2556 note that old_tss_sel is not used afetr this point */
2557 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2558 old_tss_sel = 0xffff;
2559
2560 if (next_tss_desc.type & 8)
2561 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2562 old_tss_base, &next_tss_desc);
2563 else
2564 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2565 old_tss_base, &next_tss_desc);
0760d448
JK		 2566 if (ret != X86EMUL_CONTINUE)
2567 return ret;
38ba30ba
GN		 2568
2569 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2570 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2571
2572 if (reason != TASK_SWITCH_IRET) {
2573 next_tss_desc.type |= (1 << 1); /* set busy flag */
2574 write_segment_descriptor(ctxt, ops, tss_selector,
2575 &next_tss_desc);
2576 }
2577
2578 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2579 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2580 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2581
e269fb21
JK		 2582 if (has_error_code) {
2583 struct decode_cache *c = &ctxt->decode;
2584
2585 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2586 c->lock_prefix = 0;
2587 c->src.val = (unsigned long) error_code;
79168fd1 2588 emulate_push(ctxt, ops);
e269fb21
JK		 2589 }
2590
38ba30ba
GN		 2591 return ret;
2592}
2593
2594int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2595 u16 tss_selector, int reason,
2596 bool has_error_code, u32 error_code)
38ba30ba 2597{
9aabc88f 2598 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2599 struct decode_cache *c = &ctxt->decode;
2600 int rc;
2601
38ba30ba 2602 c->eip = ctxt->eip;
e269fb21 2603 c->dst.type = OP_NONE;
38ba30ba 2604
e269fb21
JK		 2605 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2606 has_error_code, error_code);
38ba30ba
GN		 2607
2608 if (rc == X86EMUL_CONTINUE) {
e269fb21 2609 rc = writeback(ctxt, ops);
95c55886
GN		 2610 if (rc == X86EMUL_CONTINUE)
2611 ctxt->eip = c->eip;
38ba30ba
GN		 2612 }
2613
19d04437 2614 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2615}
2616
a682e354 2617static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2618 int reg, struct operand *op)
a682e354
GN		 2619{
2620 struct decode_cache *c = &ctxt->decode;
2621 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2622
d9271123
GN		 2623 register_address_increment(c, &c->regs[reg], df * op->bytes);
2624 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2625}
2626
8b4caf66 2627int
9aabc88f 2628x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2629{
9aabc88f 2630 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2631 u64 msr_data;
8b4caf66 2632 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2633 int rc = X86EMUL_CONTINUE;
5cd21917 2634 int saved_dst_type = c->dst.type;
8b4caf66 2635
9de41573 2636 ctxt->decode.mem_read.pos = 0;
310b5d30 2637
1161624f 2638 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2639 emulate_ud(ctxt);
1161624f
GN		 2640 goto done;
2641 }
2642
d380a5e4 2643 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2644 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2645 emulate_ud(ctxt);
d380a5e4
GN		 2646 goto done;
2647 }
2648
e92805ac 2649 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2650 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2651 emulate_gp(ctxt, 0);
e92805ac
GN		 2652 goto done;
2653 }
2654
b9fa9d6b 2655 if (c->rep_prefix && (c->d & String)) {
5cd21917 2656 ctxt->restart = true;
b9fa9d6b 2657 /* All REP prefixes have the same first termination condition */
c73e197b 2658 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2659 string_done:
2660 ctxt->restart = false;
95c55886 2661 ctxt->eip = c->eip;
b9fa9d6b
AK		 2662 goto done;
2663 }
2664 /* The second termination condition only applies for REPE
2665 * and REPNE. Test if the repeat string operation prefix is
2666 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2667 * corresponding termination condition according to:
2668 * - if REPE/REPZ and ZF = 0 then done
2669 * - if REPNE/REPNZ and ZF = 1 then done
2670 */
2671 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2672 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2673 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2674 ((ctxt->eflags & EFLG_ZF) == 0))
2675 goto string_done;
b9fa9d6b 2676 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2677 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2678 goto string_done;
b9fa9d6b 2679 }
063db061 2680 c->eip = ctxt->eip;
b9fa9d6b
AK		 2681 }
2682
8b4caf66 2683 if (c->src.type == OP_MEM) {
9de41573 2684 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2685 c->src.valptr, c->src.bytes);
b60d513c 2686 if (rc != X86EMUL_CONTINUE)
8b4caf66 2687 goto done;
16518d5a 2688 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2689 }
2690
e35b7b9c 2691 if (c->src2.type == OP_MEM) {
9de41573
GN		 2692 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2693 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2694 if (rc != X86EMUL_CONTINUE)
2695 goto done;
2696 }
2697
8b4caf66
LV		 2698 if ((c->d & DstMask) == ImplicitOps)
2699 goto special_insn;
2700
2701
69f55cb1
GN		 2702 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2703 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2704 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2705 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2706 if (rc != X86EMUL_CONTINUE)
2707 goto done;
038e51de 2708 }
e4e03ded 2709 c->dst.orig_val = c->dst.val;
038e51de 2710
018a98db
AK		 2711special_insn:
2712
ef65c889
AK		 2713 if (c->execute) {
2714 rc = c->execute(ctxt);
2715 if (rc != X86EMUL_CONTINUE)
2716 goto done;
2717 goto writeback;
2718 }
2719
e4e03ded 2720 if (c->twobyte)
6aa8b732
AK		 2721 goto twobyte_insn;
2722
e4e03ded 2723 switch (c->b) {
6aa8b732
AK		 2724 case 0x00 ... 0x05:
2725 add: /* add */
05f086f8 2726 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2727 break;
0934ac9d 2728 case 0x06: /* push es */
79168fd1 2729 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2730 break;
2731 case 0x07: /* pop es */
0934ac9d 2732 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2733 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2734 goto done;
2735 break;
6aa8b732
AK		 2736 case 0x08 ... 0x0d:
2737 or: /* or */
05f086f8 2738 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2739 break;
0934ac9d 2740 case 0x0e: /* push cs */
79168fd1 2741 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2742 break;
6aa8b732
AK		 2743 case 0x10 ... 0x15:
2744 adc: /* adc */
05f086f8 2745 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2746 break;
0934ac9d 2747 case 0x16: /* push ss */
79168fd1 2748 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2749 break;
2750 case 0x17: /* pop ss */
0934ac9d 2751 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2752 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2753 goto done;
2754 break;
6aa8b732
AK		 2755 case 0x18 ... 0x1d:
2756 sbb: /* sbb */
05f086f8 2757 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2758 break;
0934ac9d 2759 case 0x1e: /* push ds */
79168fd1 2760 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2761 break;
2762 case 0x1f: /* pop ds */
0934ac9d 2763 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2764 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2765 goto done;
2766 break;
aa3a816b 2767 case 0x20 ... 0x25:
6aa8b732 2768 and: /* and */
05f086f8 2769 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2770 break;
2771 case 0x28 ... 0x2d:
2772 sub: /* sub */
05f086f8 2773 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2774 break;
2775 case 0x30 ... 0x35:
2776 xor: /* xor */
05f086f8 2777 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2778 break;
2779 case 0x38 ... 0x3d:
2780 cmp: /* cmp */
05f086f8 2781 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2782 break;
33615aa9
AK		 2783 case 0x40 ... 0x47: /* inc r16/r32 */
2784 emulate_1op("inc", c->dst, ctxt->eflags);
2785 break;
2786 case 0x48 ... 0x4f: /* dec r16/r32 */
2787 emulate_1op("dec", c->dst, ctxt->eflags);
2788 break;
2789 case 0x50 ... 0x57: /* push reg */
79168fd1 2790 emulate_push(ctxt, ops);
33615aa9
AK		 2791 break;
2792 case 0x58 ... 0x5f: /* pop reg */
2793 pop_instruction:
350f69dc 2794 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2795 if (rc != X86EMUL_CONTINUE)
33615aa9 2796 goto done;
33615aa9 2797 break;
abcf14b5 2798 case 0x60: /* pusha */
c37eda13
WY		 2799 rc = emulate_pusha(ctxt, ops);
2800 if (rc != X86EMUL_CONTINUE)
2801 goto done;
abcf14b5
MG		 2802 break;
2803 case 0x61: /* popa */
2804 rc = emulate_popa(ctxt, ops);
1b30eaa8 2805 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2806 goto done;
2807 break;
6aa8b732 2808 case 0x63: /* movsxd */
8b4caf66 2809 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2810 goto cannot_emulate;
e4e03ded 2811 c->dst.val = (s32) c->src.val;
6aa8b732 2812 break;
91ed7a0e 2813 case 0x68: /* push imm */
018a98db 2814 case 0x6a: /* push imm8 */
79168fd1 2815 emulate_push(ctxt, ops);
018a98db
AK		 2816 break;
2817 case 0x6c: /* insb */
2818 case 0x6d: /* insw/insd */
7972995b 2819 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2820 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2821 c->dst.bytes)) {
54b8486f 2822 emulate_gp(ctxt, 0);
f850e2e6
GN		 2823 goto done;
2824 }
7b262e90
GN		 2825 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2826 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2827 goto done; /* IO is needed, skip writeback */
2828 break;
018a98db
AK		 2829 case 0x6e: /* outsb */
2830 case 0x6f: /* outsw/outsd */
7972995b 2831 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2832 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2833 c->src.bytes)) {
54b8486f 2834 emulate_gp(ctxt, 0);
f850e2e6
GN		 2835 goto done;
2836 }
7972995b
GN		 2837 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2838 &c->src.val, 1, ctxt->vcpu);
2839
2840 c->dst.type = OP_NONE; /* nothing to writeback */
2841 break;
b2833e3c 2842 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2843 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2844 jmp_rel(c, c->src.val);
018a98db 2845 break;
6aa8b732 2846 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2847 switch (c->modrm_reg) {
6aa8b732
AK		 2848 case 0:
2849 goto add;
2850 case 1:
2851 goto or;
2852 case 2:
2853 goto adc;
2854 case 3:
2855 goto sbb;
2856 case 4:
2857 goto and;
2858 case 5:
2859 goto sub;
2860 case 6:
2861 goto xor;
2862 case 7:
2863 goto cmp;
2864 }
2865 break;
2866 case 0x84 ... 0x85:
dfb507c4 2867 test:
05f086f8 2868 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2869 break;
2870 case 0x86 ... 0x87: /* xchg */
b13354f8 2871 xchg:
6aa8b732 2872 /* Write back the register source. */
e4e03ded 2873 switch (c->dst.bytes) {
6aa8b732 2874 case 1:
e4e03ded 2875 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2876 break;
2877 case 2:
e4e03ded 2878 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2879 break;
2880 case 4:
e4e03ded 2881 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2882 break; /* 64b reg: zero-extend */
2883 case 8:
e4e03ded 2884 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2885 break;
2886 }
2887 /*
2888 * Write back the memory destination with implicit LOCK
2889 * prefix.
2890 */
e4e03ded
LV		 2891 c->dst.val = c->src.val;
2892 c->lock_prefix = 1;
6aa8b732 2893 break;
6aa8b732 2894 case 0x88 ... 0x8b: /* mov */
7de75248 2895 goto mov;
79168fd1
GN		 2896 case 0x8c: /* mov r/m, sreg */
2897 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2898 emulate_ud(ctxt);
5e3ae6c5 2899 goto done;
38d5bc6d 2900 }
79168fd1 2901 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2902 break;
7e0b54b1 2903 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2904 c->dst.val = c->modrm_ea;
7e0b54b1 2905 break;
4257198a
GT		 2906 case 0x8e: { /* mov seg, r/m16 */
2907 uint16_t sel;
4257198a
GT		 2908
2909 sel = c->src.val;
8b9f4414 2910
c697518a
GN		 2911 if (c->modrm_reg == VCPU_SREG_CS ||
2912 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2913 emulate_ud(ctxt);
8b9f4414
GN		 2914 goto done;
2915 }
2916
310b5d30 2917 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2918 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2919
2e873022 2920 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2921
2922 c->dst.type = OP_NONE; /* Disable writeback. */
2923 break;
2924 }
6aa8b732 2925 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2926 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2927 if (rc != X86EMUL_CONTINUE)
6aa8b732 2928 goto done;
6aa8b732 2929 break;
b13354f8 2930 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2931 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2932 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2933 break;
2934 }
2935 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2936 c->src.type = OP_REG;
2937 c->src.bytes = c->op_bytes;
b13354f8
MG		 2938 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2939 c->src.val = *(c->src.ptr);
2940 goto xchg;
fd2a7608 2941 case 0x9c: /* pushf */
05f086f8 2942 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2943 emulate_push(ctxt, ops);
8cdbd2c9 2944 break;
535eabcf 2945 case 0x9d: /* popf */
2b48cc75 2946 c->dst.type = OP_REG;
05f086f8 2947 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2948 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2949 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2950 if (rc != X86EMUL_CONTINUE)
2951 goto done;
2952 break;
5d55f299 2953 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2954 case 0xa4 ... 0xa5: /* movs */
a682e354 2955 goto mov;
6aa8b732 2956 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2957 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2958 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2959 goto cmp;
dfb507c4
MG		 2960 case 0xa8 ... 0xa9: /* test ax, imm */
2961 goto test;
6aa8b732 2962 case 0xaa ... 0xab: /* stos */
e4e03ded 2963 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2964 break;
2965 case 0xac ... 0xad: /* lods */
a682e354 2966 goto mov;
6aa8b732
AK		 2967 case 0xae ... 0xaf: /* scas */
2968 DPRINTF("Urk! I don't handle SCAS.\n");
2969 goto cannot_emulate;
a5e2e82b 2970 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2971 goto mov;
018a98db
AK		 2972 case 0xc0 ... 0xc1:
2973 emulate_grp2(ctxt);
2974 break;
111de5d6 2975 case 0xc3: /* ret */
cf5de4f8 2976 c->dst.type = OP_REG;
111de5d6 2977 c->dst.ptr = &c->eip;
cf5de4f8 2978 c->dst.bytes = c->op_bytes;
111de5d6 2979 goto pop_instruction;
018a98db
AK		 2980 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2981 mov:
2982 c->dst.val = c->src.val;
2983 break;
a77ab5ea
AK		 2984 case 0xcb: /* ret far */
2985 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2986 if (rc != X86EMUL_CONTINUE)
2987 goto done;
2988 break;
2989 case 0xcf: /* iret */
2990 rc = emulate_iret(ctxt, ops);
2991
1b30eaa8 2992 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2993 goto done;
2994 break;
018a98db
AK		 2995 case 0xd0 ... 0xd1: /* Grp2 */
2996 c->src.val = 1;
2997 emulate_grp2(ctxt);
2998 break;
2999 case 0xd2 ... 0xd3: /* Grp2 */
3000 c->src.val = c->regs[VCPU_REGS_RCX];
3001 emulate_grp2(ctxt);
3002 break;
a6a3034c
MG		 3003 case 0xe4: /* inb */
3004 case 0xe5: /* in */
cf8f70bf 3005 goto do_io_in;
a6a3034c
MG		 3006 case 0xe6: /* outb */
3007 case 0xe7: /* out */
cf8f70bf 3008 goto do_io_out;
1a52e051 3009 case 0xe8: /* call (near) */ {
d53c4777 3010 long int rel = c->src.val;
e4e03ded 3011 c->src.val = (unsigned long) c->eip;
7a957275 3012 jmp_rel(c, rel);
79168fd1 3013 emulate_push(ctxt, ops);
8cdbd2c9 3014 break;
1a52e051
NK		 3015 }
3016 case 0xe9: /* jmp rel */
954cd36f 3017 goto jmp;
414e6277
GN		 3018 case 0xea: { /* jmp far */
3019 unsigned short sel;
ea79849d 3020 jump_far:
414e6277
GN		 3021 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3022
3023 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3024 goto done;
954cd36f 3025
414e6277
GN		 3026 c->eip = 0;
3027 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3028 break;
414e6277 3029 }
954cd36f
GT		 3030 case 0xeb:
3031 jmp: /* jmp rel short */
7a957275 3032 jmp_rel(c, c->src.val);
a01af5ec 3033 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3034 break;
a6a3034c
MG		 3035 case 0xec: /* in al,dx */
3036 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3037 c->src.val = c->regs[VCPU_REGS_RDX];
3038 do_io_in:
3039 c->dst.bytes = min(c->dst.bytes, 4u);
3040 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3041 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3042 goto done;
3043 }
7b262e90
GN		 3044 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3045 &c->dst.val))
cf8f70bf
GN		 3046 goto done; /* IO is needed */
3047 break;
ce7a0ad3
WY		 3048 case 0xee: /* out dx,al */
3049 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3050 c->src.val = c->regs[VCPU_REGS_RDX];
3051 do_io_out:
3052 c->dst.bytes = min(c->dst.bytes, 4u);
3053 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3054 emulate_gp(ctxt, 0);
f850e2e6
GN		 3055 goto done;
3056 }
cf8f70bf
GN		 3057 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3058 ctxt->vcpu);
3059 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3060 break;
111de5d6 3061 case 0xf4: /* hlt */
ad312c7c 3062 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3063 break;
111de5d6
AK		 3064 case 0xf5: /* cmc */
3065 /* complement carry flag from eflags reg */
3066 ctxt->eflags ^= EFLG_CF;
3067 c->dst.type = OP_NONE; /* Disable writeback. */
3068 break;
018a98db 3069 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3070 if (!emulate_grp3(ctxt, ops))
3071 goto cannot_emulate;
018a98db 3072 break;
111de5d6
AK		 3073 case 0xf8: /* clc */
3074 ctxt->eflags &= ~EFLG_CF;
3075 c->dst.type = OP_NONE; /* Disable writeback. */
3076 break;
3077 case 0xfa: /* cli */
07cbc6c1 3078 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3079 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3080 goto done;
3081 } else {
f850e2e6
GN		 3082 ctxt->eflags &= ~X86_EFLAGS_IF;
3083 c->dst.type = OP_NONE; /* Disable writeback. */
3084 }
111de5d6
AK		 3085 break;
3086 case 0xfb: /* sti */
07cbc6c1 3087 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3088 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3089 goto done;
3090 } else {
95cb2295 3091 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3092 ctxt->eflags |= X86_EFLAGS_IF;
3093 c->dst.type = OP_NONE; /* Disable writeback. */
3094 }
111de5d6 3095 break;
fb4616f4
MG		 3096 case 0xfc: /* cld */
3097 ctxt->eflags &= ~EFLG_DF;
3098 c->dst.type = OP_NONE; /* Disable writeback. */
3099 break;
3100 case 0xfd: /* std */
3101 ctxt->eflags |= EFLG_DF;
3102 c->dst.type = OP_NONE; /* Disable writeback. */
3103 break;
ea79849d
GN		 3104 case 0xfe: /* Grp4 */
3105 grp45:
018a98db 3106 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3107 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3108 goto done;
3109 break;
ea79849d
GN		 3110 case 0xff: /* Grp5 */
3111 if (c->modrm_reg == 5)
3112 goto jump_far;
3113 goto grp45;
91269b8f
AK		 3114 default:
3115 goto cannot_emulate;
6aa8b732 3116 }
018a98db
AK		 3117
3118writeback:
3119 rc = writeback(ctxt, ops);
1b30eaa8 3120 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3121 goto done;
3122
5cd21917
GN		 3123 /*
3124 * restore dst type in case the decoding will be reused
3125 * (happens for string instruction )
3126 */
3127 c->dst.type = saved_dst_type;
3128
a682e354 3129 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3130 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3131 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3132
3133 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3134 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3135 &c->dst);
d9271123 3136
5cd21917 3137 if (c->rep_prefix && (c->d & String)) {
7b262e90 3138 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3139 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3140 /*
3141 * Re-enter guest when pio read ahead buffer is empty or,
3142 * if it is not used, after each 1024 iteration.
3143 */
3144 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3145 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3146 ctxt->restart = false;
3147 }
9de41573
GN		 3148 /*
3149 * reset read cache here in case string instruction is restared
3150 * without decoding
3151 */
3152 ctxt->decode.mem_read.end = 0;
95c55886 3153 ctxt->eip = c->eip;
018a98db
AK		 3154
3155done:
cb404fe0 3156 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3157
3158twobyte_insn:
e4e03ded 3159 switch (c->b) {
6aa8b732 3160 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3161 switch (c->modrm_reg) {
6aa8b732
AK		 3162 u16 size;
3163 unsigned long address;
3164
aca7f966 3165 case 0: /* vmcall */
e4e03ded 3166 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3167 goto cannot_emulate;
3168
7aa81cc0 3169 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3170 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3171 goto done;
3172
33e3885d 3173 /* Let the processor re-execute the fixed hypercall */
063db061 3174 c->eip = ctxt->eip;
16286d08
AK		 3175 /* Disable writeback. */
3176 c->dst.type = OP_NONE;
aca7f966 3177 break;
6aa8b732 3178 case 2: /* lgdt */
e4e03ded
LV		 3179 rc = read_descriptor(ctxt, ops, c->src.ptr,
3180 &size, &address, c->op_bytes);
1b30eaa8 3181 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3182 goto done;
3183 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3184 /* Disable writeback. */
3185 c->dst.type = OP_NONE;
6aa8b732 3186 break;
aca7f966 3187 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3188 if (c->modrm_mod == 3) {
3189 switch (c->modrm_rm) {
3190 case 1:
3191 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3192 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3193 goto done;
3194 break;
3195 default:
3196 goto cannot_emulate;
3197 }
aca7f966 3198 } else {
e4e03ded 3199 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3200 &size, &address,
e4e03ded 3201 c->op_bytes);
1b30eaa8 3202 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3203 goto done;
3204 realmode_lidt(ctxt->vcpu, size, address);
3205 }
16286d08
AK		 3206 /* Disable writeback. */
3207 c->dst.type = OP_NONE;
6aa8b732
AK		 3208 break;
3209 case 4: /* smsw */
16286d08 3210 c->dst.bytes = 2;
52a46617 3211 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3212 break;
3213 case 6: /* lmsw */
93a152be
GN		 3214 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3215 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3216 c->dst.type = OP_NONE;
6aa8b732 3217 break;
6e1e5ffe 3218 case 5: /* not defined */
54b8486f 3219 emulate_ud(ctxt);
6e1e5ffe 3220 goto done;
6aa8b732 3221 case 7: /* invlpg*/
69f55cb1 3222 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3223 /* Disable writeback. */
3224 c->dst.type = OP_NONE;
6aa8b732
AK		 3225 break;
3226 default:
3227 goto cannot_emulate;
3228 }
3229 break;
e99f0507 3230 case 0x05: /* syscall */
3fb1b5db 3231 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3232 if (rc != X86EMUL_CONTINUE)
3233 goto done;
e66bb2cc
AP		 3234 else
3235 goto writeback;
e99f0507 3236 break;
018a98db
AK		 3237 case 0x06:
3238 emulate_clts(ctxt->vcpu);
3239 c->dst.type = OP_NONE;
3240 break;
018a98db 3241 case 0x09: /* wbinvd */
f5f48ee1
SY		 3242 kvm_emulate_wbinvd(ctxt->vcpu);
3243 c->dst.type = OP_NONE;
3244 break;
3245 case 0x08: /* invd */
018a98db
AK		 3246 case 0x0d: /* GrpP (prefetch) */
3247 case 0x18: /* Grp16 (prefetch/nop) */
3248 c->dst.type = OP_NONE;
3249 break;
3250 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3251 switch (c->modrm_reg) {
3252 case 1:
3253 case 5 ... 7:
3254 case 9 ... 15:
54b8486f 3255 emulate_ud(ctxt);
6aebfa6e
GN		 3256 goto done;
3257 }
52a46617 3258 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3259 c->dst.type = OP_NONE; /* no writeback */
3260 break;
6aa8b732 3261 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3262 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3263 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3264 emulate_ud(ctxt);
1e470be5
GN		 3265 goto done;
3266 }
35aa5375 3267 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3268 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3269 break;
018a98db 3270 case 0x22: /* mov reg, cr */
0f12244f 3271 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3272 emulate_gp(ctxt, 0);
0f12244f
GN		 3273 goto done;
3274 }
018a98db
AK		 3275 c->dst.type = OP_NONE;
3276 break;
6aa8b732 3277 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3278 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3279 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3280 emulate_ud(ctxt);
1e470be5
GN		 3281 goto done;
3282 }
35aa5375 3283
338dbc97
GN		 3284 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3285 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3286 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3287 /* #UD condition is already handled by the code above */
54b8486f 3288 emulate_gp(ctxt, 0);
338dbc97
GN		 3289 goto done;
3290 }
3291
a01af5ec 3292 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3293 break;
018a98db
AK		 3294 case 0x30:
3295 /* wrmsr */
3296 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3297 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3298 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3299 emulate_gp(ctxt, 0);
fd525365 3300 goto done;
018a98db
AK		 3301 }
3302 rc = X86EMUL_CONTINUE;
3303 c->dst.type = OP_NONE;
3304 break;
3305 case 0x32:
3306 /* rdmsr */
3fb1b5db 3307 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3308 emulate_gp(ctxt, 0);
fd525365 3309 goto done;
018a98db
AK		 3310 } else {
3311 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3312 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3313 }
3314 rc = X86EMUL_CONTINUE;
3315 c->dst.type = OP_NONE;
3316 break;
e99f0507 3317 case 0x34: /* sysenter */
3fb1b5db 3318 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3319 if (rc != X86EMUL_CONTINUE)
3320 goto done;
8c604352
AP		 3321 else
3322 goto writeback;
e99f0507
AP		 3323 break;
3324 case 0x35: /* sysexit */
3fb1b5db 3325 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3326 if (rc != X86EMUL_CONTINUE)
3327 goto done;
4668f050
AP		 3328 else
3329 goto writeback;
e99f0507 3330 break;
6aa8b732 3331 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3332 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3333 if (!test_cc(c->b, ctxt->eflags))
3334 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3335 break;
b2833e3c 3336 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3337 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3338 jmp_rel(c, c->src.val);
018a98db
AK		 3339 c->dst.type = OP_NONE;
3340 break;
0934ac9d 3341 case 0xa0: /* push fs */
79168fd1 3342 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3343 break;
3344 case 0xa1: /* pop fs */
3345 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3346 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3347 goto done;
3348 break;
7de75248
NK		 3349 case 0xa3:
3350 bt: /* bt */
e4f8e039 3351 c->dst.type = OP_NONE;
e4e03ded
LV		 3352 /* only subword offset */
3353 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3354 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3355 break;
9bf8ea42
GT		 3356 case 0xa4: /* shld imm8, r, r/m */
3357 case 0xa5: /* shld cl, r, r/m */
3358 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3359 break;
0934ac9d 3360 case 0xa8: /* push gs */
79168fd1 3361 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3362 break;
3363 case 0xa9: /* pop gs */
3364 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3365 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3366 goto done;
3367 break;
7de75248
NK		 3368 case 0xab:
3369 bts: /* bts */
e4e03ded
LV		 3370 /* only subword offset */
3371 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3372 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3373 break;
9bf8ea42
GT		 3374 case 0xac: /* shrd imm8, r, r/m */
3375 case 0xad: /* shrd cl, r, r/m */
3376 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3377 break;
2a7c5b8b
GC		 3378 case 0xae: /* clflush */
3379 break;
6aa8b732
AK		 3380 case 0xb0 ... 0xb1: /* cmpxchg */
3381 /*
3382 * Save real source value, then compare EAX against
3383 * destination.
3384 */
e4e03ded
LV		 3385 c->src.orig_val = c->src.val;
3386 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3387 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3388 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3389 /* Success: write back to memory. */
e4e03ded 3390 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3391 } else {
3392 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3393 c->dst.type = OP_REG;
3394 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3395 }
3396 break;
6aa8b732
AK		 3397 case 0xb3:
3398 btr: /* btr */
e4e03ded
LV		 3399 /* only subword offset */
3400 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3401 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3402 break;
6aa8b732 3403 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3404 c->dst.bytes = c->op_bytes;
3405 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3406 : (u16) c->src.val;
6aa8b732 3407 break;
6aa8b732 3408 case 0xba: /* Grp8 */
e4e03ded 3409 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3410 case 0:
3411 goto bt;
3412 case 1:
3413 goto bts;
3414 case 2:
3415 goto btr;
3416 case 3:
3417 goto btc;
3418 }
3419 break;
7de75248
NK		 3420 case 0xbb:
3421 btc: /* btc */
e4e03ded
LV		 3422 /* only subword offset */
3423 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3424 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3425 break;
6aa8b732 3426 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3427 c->dst.bytes = c->op_bytes;
3428 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3429 (s16) c->src.val;
6aa8b732 3430 break;
a012e65a 3431 case 0xc3: /* movnti */
e4e03ded
LV		 3432 c->dst.bytes = c->op_bytes;
3433 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3434 (u64) c->src.val;
a012e65a 3435 break;
6aa8b732 3436 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3437 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3438 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3439 goto done;
3440 break;
91269b8f
AK		 3441 default:
3442 goto cannot_emulate;
6aa8b732
AK		 3443 }
3444 goto writeback;
3445
3446cannot_emulate:
e4e03ded 3447 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3448 return -1;
3449}
Linux kernel - Deliverables
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