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KVM: x86 emulator: Check IOPL level during io instruction emulation
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
e99f0507 36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed
MG		 78/* Misc flags */
79#define No64 (1<<28)
0dc8d10f
GT		 80/* Source 2 operand type */
81#define Src2None (0<<29)
82#define Src2CL (1<<29)
83#define Src2ImmByte (2<<29)
84#define Src2One (3<<29)
a5f868bd 85#define Src2Imm16 (4<<29)
0dc8d10f 86#define Src2Mask (7<<29)
6aa8b732 87
43bb19cd 88enum {
1d6ad207 89 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 90 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 91 Group8, Group9,
43bb19cd
AK		 92};
93
45ed60b3 94static u32 opcode_table[256] = {
6aa8b732
AK		 95 /* 0x00 - 0x07 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 98 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 99 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 100 /* 0x08 - 0x0F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 103 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
104 ImplicitOps | Stack | No64, 0,
6aa8b732
AK		 105 /* 0x10 - 0x17 */
106 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
107 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 108 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 109 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 110 /* 0x18 - 0x1F */
111 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
112 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 113 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 114 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 115 /* 0x20 - 0x27 */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 118 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 119 /* 0x28 - 0x2F */
120 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
122 0, 0, 0, 0,
123 /* 0x30 - 0x37 */
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
126 0, 0, 0, 0,
127 /* 0x38 - 0x3F */
128 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
129 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 130 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
131 0, 0,
d77a2507 132 /* 0x40 - 0x47 */
33615aa9 133 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 134 /* 0x48 - 0x4F */
33615aa9 135 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 136 /* 0x50 - 0x57 */
6e3d5dfb
AK		 137 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
138 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 139 /* 0x58 - 0x5F */
6e3d5dfb
AK		 140 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
141 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 142 /* 0x60 - 0x67 */
abcf14b5
MG		 143 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
144 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 145 0, 0, 0, 0,
146 /* 0x68 - 0x6F */
91ed7a0e 147 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 148 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
149 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 150 /* 0x70 - 0x77 */
b2833e3c
GN		 151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
152 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 153 /* 0x78 - 0x7F */
b2833e3c
GN		 154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
155 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 156 /* 0x80 - 0x87 */
1d6ad207
AK		 157 Group | Group1_80, Group | Group1_81,
158 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 159 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
160 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
161 /* 0x88 - 0x8F */
162 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
163 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 164 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 165 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 166 /* 0x90 - 0x97 */
167 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
168 /* 0x98 - 0x9F */
d8769fed 169 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 170 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 171 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 172 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
173 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 174 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
175 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 176 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 177 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
178 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
179 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 180 /* 0xB0 - 0xB7 */
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
185 /* 0xB8 - 0xBF */
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 190 /* 0xC0 - 0xC7 */
d9413cd7 191 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 192 0, ImplicitOps | Stack, 0, 0,
d9413cd7 193 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 194 /* 0xC8 - 0xCF */
e637b823 195 0, 0, 0, ImplicitOps | Stack,
d8769fed 196 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 197 /* 0xD0 - 0xD7 */
198 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
199 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
200 0, 0, 0, 0,
201 /* 0xD8 - 0xDF */
202 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 203 /* 0xE0 - 0xE7 */
a6a3034c 204 0, 0, 0, 0,
84ce66a6
GN		 205 ByteOp | SrcImmUByte, SrcImmUByte,
206 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 207 /* 0xE8 - 0xEF */
d53c4777 208 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 209 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 210 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
211 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 212 /* 0xF0 - 0xF7 */
213 0, 0, 0, 0,
7d858a19 214 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 215 /* 0xF8 - 0xFF */
b284be57 216 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 217 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 218};
219
45ed60b3 220static u32 twobyte_table[256] = {
6aa8b732 221 /* 0x00 - 0x0F */
e99f0507 222 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
651a3e29 223 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 224 /* 0x10 - 0x1F */
225 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
226 /* 0x20 - 0x2F */
227 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0,
229 /* 0x30 - 0x3F */
e99f0507
AP		 230 ImplicitOps, 0, ImplicitOps, 0,
231 ImplicitOps, ImplicitOps, 0, 0,
232 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 233 /* 0x40 - 0x47 */
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
238 /* 0x48 - 0x4F */
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
243 /* 0x50 - 0x5F */
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
245 /* 0x60 - 0x6F */
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
247 /* 0x70 - 0x7F */
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
249 /* 0x80 - 0x8F */
b2833e3c
GN		 250 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
251 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 252 /* 0x90 - 0x9F */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0xA0 - 0xA7 */
0934ac9d
MG		 255 ImplicitOps | Stack, ImplicitOps | Stack,
256 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 257 DstMem | SrcReg | Src2ImmByte | ModRM,
258 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 259 /* 0xA8 - 0xAF */
0934ac9d
MG		 260 ImplicitOps | Stack, ImplicitOps | Stack,
261 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 262 DstMem | SrcReg | Src2ImmByte | ModRM,
263 DstMem | SrcReg | Src2CL | ModRM,
264 ModRM, 0,
6aa8b732
AK		 265 /* 0xB0 - 0xB7 */
266 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 267 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 268 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
269 DstReg | SrcMem16 | ModRM | Mov,
270 /* 0xB8 - 0xBF */
2db2c2eb 271 0, 0, Group | Group8, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 272 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
273 DstReg | SrcMem16 | ModRM | Mov,
274 /* 0xC0 - 0xCF */
60a29d4e
GN		 275 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
276 0, 0, 0, Group | GroupDual | Group9,
a012e65a 277 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 278 /* 0xD0 - 0xDF */
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
280 /* 0xE0 - 0xEF */
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
282 /* 0xF0 - 0xFF */
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
284};
285
45ed60b3 286static u32 group_table[] = {
1d6ad207
AK		 287 [Group1_80*8] =
288 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
289 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
290 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
291 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
292 [Group1_81*8] =
293 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
294 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
295 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
296 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
297 [Group1_82*8] =
298 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
299 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
300 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
301 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
302 [Group1_83*8] =
303 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
304 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
305 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
306 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 307 [Group1A*8] =
308 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 309 [Group3_Byte*8] =
310 ByteOp | SrcImm | DstMem | ModRM, 0,
311 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
312 0, 0, 0, 0,
313 [Group3*8] =
41afa025 314 DstMem | SrcImm | ModRM, 0,
6eb06cb2 315 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 316 0, 0, 0, 0,
fd60754e
AK		 317 [Group4*8] =
318 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
319 0, 0, 0, 0, 0, 0,
320 [Group5*8] =
d19292e4
MG		 321 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
322 SrcMem | ModRM | Stack, 0,
ef46f18e 323 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 324 [Group7*8] =
325 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 326 SrcNone | ModRM | DstMem | Mov, 0,
327 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
2db2c2eb
GN		 328 [Group8*8] =
329 0, 0, 0, 0,
330 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
331 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
60a29d4e
GN		 332 [Group9*8] =
333 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 334};
335
45ed60b3 336static u32 group2_table[] = {
d95058a1 337 [Group7*8] =
fbce554e 338 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 339 SrcNone | ModRM | DstMem | Mov, 0,
340 SrcMem16 | ModRM | Mov, 0,
60a29d4e
GN		 341 [Group9*8] =
342 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 343};
344
6aa8b732 345/* EFLAGS bit definitions. */
b1d86143
AP		 346#define EFLG_VM (1<<17)
347#define EFLG_RF (1<<16)
6aa8b732
AK		 348#define EFLG_OF (1<<11)
349#define EFLG_DF (1<<10)
b1d86143 350#define EFLG_IF (1<<9)
6aa8b732
AK		 351#define EFLG_SF (1<<7)
352#define EFLG_ZF (1<<6)
353#define EFLG_AF (1<<4)
354#define EFLG_PF (1<<2)
355#define EFLG_CF (1<<0)
356
357/*
358 * Instruction emulation:
359 * Most instructions are emulated directly via a fragment of inline assembly
360 * code. This allows us to save/restore EFLAGS and thus very easily pick up
361 * any modified flags.
362 */
363
05b3e0c2 364#if defined(CONFIG_X86_64)
6aa8b732
AK		 365#define _LO32 "k" /* force 32-bit operand */
366#define _STK "%%rsp" /* stack pointer */
367#elif defined(__i386__)
368#define _LO32 "" /* force 32-bit operand */
369#define _STK "%%esp" /* stack pointer */
370#endif
371
372/*
373 * These EFLAGS bits are restored from saved value during emulation, and
374 * any changes are written back to the saved value after emulation.
375 */
376#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
377
378/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 379#define _PRE_EFLAGS(_sav, _msk, _tmp) \
380 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
381 "movl %"_sav",%"_LO32 _tmp"; " \
382 "push %"_tmp"; " \
383 "push %"_tmp"; " \
384 "movl %"_msk",%"_LO32 _tmp"; " \
385 "andl %"_LO32 _tmp",("_STK"); " \
386 "pushf; " \
387 "notl %"_LO32 _tmp"; " \
388 "andl %"_LO32 _tmp",("_STK"); " \
389 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
390 "pop %"_tmp"; " \
391 "orl %"_LO32 _tmp",("_STK"); " \
392 "popf; " \
393 "pop %"_sav"; "
6aa8b732
AK		 394
395/* After executing instruction: write-back necessary bits in EFLAGS. */
396#define _POST_EFLAGS(_sav, _msk, _tmp) \
397 /* _sav |= EFLAGS & _msk; */ \
398 "pushf; " \
399 "pop %"_tmp"; " \
400 "andl %"_msk",%"_LO32 _tmp"; " \
401 "orl %"_LO32 _tmp",%"_sav"; "
402
dda96d8f
AK		 403#ifdef CONFIG_X86_64
404#define ON64(x) x
405#else
406#define ON64(x)
407#endif
408
6b7ad61f
AK		 409#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
410 do { \
411 __asm__ __volatile__ ( \
412 _PRE_EFLAGS("0", "4", "2") \
413 _op _suffix " %"_x"3,%1; " \
414 _POST_EFLAGS("0", "4", "2") \
415 : "=m" (_eflags), "=m" ((_dst).val), \
416 "=&r" (_tmp) \
417 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 418 } while (0)
6b7ad61f
AK		 419
420
6aa8b732
AK		 421/* Raw emulation: instruction has two explicit operands. */
422#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 423 do { \
424 unsigned long _tmp; \
425 \
426 switch ((_dst).bytes) { \
427 case 2: \
428 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
429 break; \
430 case 4: \
431 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
432 break; \
433 case 8: \
434 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
435 break; \
436 } \
6aa8b732
AK		 437 } while (0)
438
439#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
440 do { \
6b7ad61f 441 unsigned long _tmp; \
d77c26fc 442 switch ((_dst).bytes) { \
6aa8b732 443 case 1: \
6b7ad61f 444 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 445 break; \
446 default: \
447 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
448 _wx, _wy, _lx, _ly, _qx, _qy); \
449 break; \
450 } \
451 } while (0)
452
453/* Source operand is byte-sized and may be restricted to just %cl. */
454#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
455 __emulate_2op(_op, _src, _dst, _eflags, \
456 "b", "c", "b", "c", "b", "c", "b", "c")
457
458/* Source operand is byte, word, long or quad sized. */
459#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
460 __emulate_2op(_op, _src, _dst, _eflags, \
461 "b", "q", "w", "r", _LO32, "r", "", "r")
462
463/* Source operand is word, long or quad sized. */
464#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
465 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
466 "w", "r", _LO32, "r", "", "r")
467
d175226a
GT		 468/* Instruction has three operands and one operand is stored in ECX register */
469#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
470 do { \
471 unsigned long _tmp; \
472 _type _clv = (_cl).val; \
473 _type _srcv = (_src).val; \
474 _type _dstv = (_dst).val; \
475 \
476 __asm__ __volatile__ ( \
477 _PRE_EFLAGS("0", "5", "2") \
478 _op _suffix " %4,%1 \n" \
479 _POST_EFLAGS("0", "5", "2") \
480 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
481 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
482 ); \
483 \
484 (_cl).val = (unsigned long) _clv; \
485 (_src).val = (unsigned long) _srcv; \
486 (_dst).val = (unsigned long) _dstv; \
487 } while (0)
488
489#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
490 do { \
491 switch ((_dst).bytes) { \
492 case 2: \
493 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
494 "w", unsigned short); \
495 break; \
496 case 4: \
497 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
498 "l", unsigned int); \
499 break; \
500 case 8: \
501 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
502 "q", unsigned long)); \
503 break; \
504 } \
505 } while (0)
506
dda96d8f 507#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 508 do { \
509 unsigned long _tmp; \
510 \
dda96d8f
AK		 511 __asm__ __volatile__ ( \
512 _PRE_EFLAGS("0", "3", "2") \
513 _op _suffix " %1; " \
514 _POST_EFLAGS("0", "3", "2") \
515 : "=m" (_eflags), "+m" ((_dst).val), \
516 "=&r" (_tmp) \
517 : "i" (EFLAGS_MASK)); \
518 } while (0)
519
520/* Instruction has only one explicit operand (no source operand). */
521#define emulate_1op(_op, _dst, _eflags) \
522 do { \
d77c26fc 523 switch ((_dst).bytes) { \
dda96d8f
AK		 524 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
525 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
526 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
527 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 528 } \
529 } while (0)
530
6aa8b732
AK		 531/* Fetch next part of the instruction being emulated. */
532#define insn_fetch(_type, _size, _eip) \
533({ unsigned long _x; \
62266869 534 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 535 if (rc != 0) \
6aa8b732
AK		 536 goto done; \
537 (_eip) += (_size); \
538 (_type)_x; \
539})
540
ddcb2885
HH		 541static inline unsigned long ad_mask(struct decode_cache *c)
542{
543 return (1UL << (c->ad_bytes << 3)) - 1;
544}
545
6aa8b732 546/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 547static inline unsigned long
548address_mask(struct decode_cache *c, unsigned long reg)
549{
550 if (c->ad_bytes == sizeof(unsigned long))
551 return reg;
552 else
553 return reg & ad_mask(c);
554}
555
556static inline unsigned long
557register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
558{
559 return base + address_mask(c, reg);
560}
561
7a957275
HH		 562static inline void
563register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
564{
565 if (c->ad_bytes == sizeof(unsigned long))
566 *reg += inc;
567 else
568 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
569}
6aa8b732 570
7a957275
HH		 571static inline void jmp_rel(struct decode_cache *c, int rel)
572{
573 register_address_increment(c, &c->eip, rel);
574}
098c937b 575
7a5b56df
AK		 576static void set_seg_override(struct decode_cache *c, int seg)
577{
578 c->has_seg_override = true;
579 c->seg_override = seg;
580}
581
582static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
583{
584 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
585 return 0;
586
587 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
588}
589
590static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
591 struct decode_cache *c)
592{
593 if (!c->has_seg_override)
594 return 0;
595
596 return seg_base(ctxt, c->seg_override);
597}
598
599static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
600{
601 return seg_base(ctxt, VCPU_SREG_ES);
602}
603
604static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
605{
606 return seg_base(ctxt, VCPU_SREG_SS);
607}
608
62266869
AK		 609static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
610 struct x86_emulate_ops *ops,
611 unsigned long linear, u8 *dest)
612{
613 struct fetch_cache *fc = &ctxt->decode.fetch;
614 int rc;
615 int size;
616
617 if (linear < fc->start || linear >= fc->end) {
618 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
1871c602 619 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
62266869
AK		 620 if (rc)
621 return rc;
622 fc->start = linear;
623 fc->end = linear + size;
624 }
625 *dest = fc->data[linear - fc->start];
626 return 0;
627}
628
629static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
630 struct x86_emulate_ops *ops,
631 unsigned long eip, void *dest, unsigned size)
632{
633 int rc = 0;
634
eb3c79e6
AK		 635 /* x86 instructions are limited to 15 bytes. */
636 if (eip + size - ctxt->decode.eip_orig > 15)
637 return X86EMUL_UNHANDLEABLE;
62266869
AK		 638 eip += ctxt->cs_base;
639 while (size--) {
640 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
641 if (rc)
642 return rc;
643 }
644 return 0;
645}
646
1e3c5cb0
RR		 647/*
648 * Given the 'reg' portion of a ModRM byte, and a register block, return a
649 * pointer into the block that addresses the relevant register.
650 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
651 */
652static void *decode_register(u8 modrm_reg, unsigned long *regs,
653 int highbyte_regs)
6aa8b732
AK		 654{
655 void *p;
656
657 p = &regs[modrm_reg];
658 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
659 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
660 return p;
661}
662
663static int read_descriptor(struct x86_emulate_ctxt *ctxt,
664 struct x86_emulate_ops *ops,
665 void *ptr,
666 u16 *size, unsigned long *address, int op_bytes)
667{
668 int rc;
669
670 if (op_bytes == 2)
671 op_bytes = 3;
672 *address = 0;
cebff02b 673 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 674 ctxt->vcpu, NULL);
6aa8b732
AK		 675 if (rc)
676 return rc;
cebff02b 677 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 678 ctxt->vcpu, NULL);
6aa8b732
AK		 679 return rc;
680}
681
bbe9abbd
NK		 682static int test_cc(unsigned int condition, unsigned int flags)
683{
684 int rc = 0;
685
686 switch ((condition & 15) >> 1) {
687 case 0: /* o */
688 rc |= (flags & EFLG_OF);
689 break;
690 case 1: /* b/c/nae */
691 rc |= (flags & EFLG_CF);
692 break;
693 case 2: /* z/e */
694 rc |= (flags & EFLG_ZF);
695 break;
696 case 3: /* be/na */
697 rc |= (flags & (EFLG_CF|EFLG_ZF));
698 break;
699 case 4: /* s */
700 rc |= (flags & EFLG_SF);
701 break;
702 case 5: /* p/pe */
703 rc |= (flags & EFLG_PF);
704 break;
705 case 7: /* le/ng */
706 rc |= (flags & EFLG_ZF);
707 /* fall through */
708 case 6: /* l/nge */
709 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
710 break;
711 }
712
713 /* Odd condition identifiers (lsb == 1) have inverted sense. */
714 return (!!rc ^ (condition & 1));
715}
716
3c118e24
AK		 717static void decode_register_operand(struct operand *op,
718 struct decode_cache *c,
3c118e24
AK		 719 int inhibit_bytereg)
720{
33615aa9 721 unsigned reg = c->modrm_reg;
9f1ef3f8 722 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 723
724 if (!(c->d & ModRM))
725 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 726 op->type = OP_REG;
727 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 728 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 729 op->val = *(u8 *)op->ptr;
730 op->bytes = 1;
731 } else {
33615aa9 732 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 733 op->bytes = c->op_bytes;
734 switch (op->bytes) {
735 case 2:
736 op->val = *(u16 *)op->ptr;
737 break;
738 case 4:
739 op->val = *(u32 *)op->ptr;
740 break;
741 case 8:
742 op->val = *(u64 *) op->ptr;
743 break;
744 }
745 }
746 op->orig_val = op->val;
747}
748
1c73ef66
AK		 749static int decode_modrm(struct x86_emulate_ctxt *ctxt,
750 struct x86_emulate_ops *ops)
751{
752 struct decode_cache *c = &ctxt->decode;
753 u8 sib;
f5b4edcd 754 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 755 int rc = 0;
756
757 if (c->rex_prefix) {
758 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
759 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
760 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
761 }
762
763 c->modrm = insn_fetch(u8, 1, c->eip);
764 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
765 c->modrm_reg |= (c->modrm & 0x38) >> 3;
766 c->modrm_rm |= (c->modrm & 0x07);
767 c->modrm_ea = 0;
768 c->use_modrm_ea = 1;
769
770 if (c->modrm_mod == 3) {
107d6d2e
AK		 771 c->modrm_ptr = decode_register(c->modrm_rm,
772 c->regs, c->d & ByteOp);
773 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 774 return rc;
775 }
776
777 if (c->ad_bytes == 2) {
778 unsigned bx = c->regs[VCPU_REGS_RBX];
779 unsigned bp = c->regs[VCPU_REGS_RBP];
780 unsigned si = c->regs[VCPU_REGS_RSI];
781 unsigned di = c->regs[VCPU_REGS_RDI];
782
783 /* 16-bit ModR/M decode. */
784 switch (c->modrm_mod) {
785 case 0:
786 if (c->modrm_rm == 6)
787 c->modrm_ea += insn_fetch(u16, 2, c->eip);
788 break;
789 case 1:
790 c->modrm_ea += insn_fetch(s8, 1, c->eip);
791 break;
792 case 2:
793 c->modrm_ea += insn_fetch(u16, 2, c->eip);
794 break;
795 }
796 switch (c->modrm_rm) {
797 case 0:
798 c->modrm_ea += bx + si;
799 break;
800 case 1:
801 c->modrm_ea += bx + di;
802 break;
803 case 2:
804 c->modrm_ea += bp + si;
805 break;
806 case 3:
807 c->modrm_ea += bp + di;
808 break;
809 case 4:
810 c->modrm_ea += si;
811 break;
812 case 5:
813 c->modrm_ea += di;
814 break;
815 case 6:
816 if (c->modrm_mod != 0)
817 c->modrm_ea += bp;
818 break;
819 case 7:
820 c->modrm_ea += bx;
821 break;
822 }
823 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
824 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 825 if (!c->has_seg_override)
826 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 827 c->modrm_ea = (u16)c->modrm_ea;
828 } else {
829 /* 32/64-bit ModR/M decode. */
84411d85 830 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 831 sib = insn_fetch(u8, 1, c->eip);
832 index_reg |= (sib >> 3) & 7;
833 base_reg |= sib & 7;
834 scale = sib >> 6;
835
dc71d0f1
AK		 836 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
837 c->modrm_ea += insn_fetch(s32, 4, c->eip);
838 else
1c73ef66 839 c->modrm_ea += c->regs[base_reg];
dc71d0f1 840 if (index_reg != 4)
1c73ef66 841 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 842 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
843 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 844 c->rip_relative = 1;
84411d85 845 } else
1c73ef66 846 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 847 switch (c->modrm_mod) {
848 case 0:
849 if (c->modrm_rm == 5)
850 c->modrm_ea += insn_fetch(s32, 4, c->eip);
851 break;
852 case 1:
853 c->modrm_ea += insn_fetch(s8, 1, c->eip);
854 break;
855 case 2:
856 c->modrm_ea += insn_fetch(s32, 4, c->eip);
857 break;
858 }
859 }
1c73ef66
AK		 860done:
861 return rc;
862}
863
864static int decode_abs(struct x86_emulate_ctxt *ctxt,
865 struct x86_emulate_ops *ops)
866{
867 struct decode_cache *c = &ctxt->decode;
868 int rc = 0;
869
870 switch (c->ad_bytes) {
871 case 2:
872 c->modrm_ea = insn_fetch(u16, 2, c->eip);
873 break;
874 case 4:
875 c->modrm_ea = insn_fetch(u32, 4, c->eip);
876 break;
877 case 8:
878 c->modrm_ea = insn_fetch(u64, 8, c->eip);
879 break;
880 }
881done:
882 return rc;
883}
884
6aa8b732 885int
8b4caf66 886x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 887{
e4e03ded 888 struct decode_cache *c = &ctxt->decode;
6aa8b732 889 int rc = 0;
6aa8b732 890 int mode = ctxt->mode;
e09d082c 891 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 892
893 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 894
e4e03ded 895 memset(c, 0, sizeof(struct decode_cache));
eb3c79e6 896 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
7a5b56df 897 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 898 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 899
900 switch (mode) {
901 case X86EMUL_MODE_REAL:
a0044755 902 case X86EMUL_MODE_VM86:
6aa8b732 903 case X86EMUL_MODE_PROT16:
f21b8bf4 904 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 905 break;
906 case X86EMUL_MODE_PROT32:
f21b8bf4 907 def_op_bytes = def_ad_bytes = 4;
6aa8b732 908 break;
05b3e0c2 909#ifdef CONFIG_X86_64
6aa8b732 910 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 911 def_op_bytes = 4;
912 def_ad_bytes = 8;
6aa8b732
AK		 913 break;
914#endif
915 default:
916 return -1;
917 }
918
f21b8bf4
AK		 919 c->op_bytes = def_op_bytes;
920 c->ad_bytes = def_ad_bytes;
921
6aa8b732 922 /* Legacy prefixes. */
b4c6abfe 923 for (;;) {
e4e03ded 924 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 925 case 0x66: /* operand-size override */
f21b8bf4
AK		 926 /* switch between 2/4 bytes */
927 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 928 break;
929 case 0x67: /* address-size override */
930 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 931 /* switch between 4/8 bytes */
f21b8bf4 932 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 933 else
e4e03ded 934 /* switch between 2/4 bytes */
f21b8bf4 935 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 936 break;
7a5b56df 937 case 0x26: /* ES override */
6aa8b732 938 case 0x2e: /* CS override */
7a5b56df 939 case 0x36: /* SS override */
6aa8b732 940 case 0x3e: /* DS override */
7a5b56df 941 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 942 break;
943 case 0x64: /* FS override */
6aa8b732 944 case 0x65: /* GS override */
7a5b56df 945 set_seg_override(c, c->b & 7);
6aa8b732 946 break;
b4c6abfe
LV		 947 case 0x40 ... 0x4f: /* REX */
948 if (mode != X86EMUL_MODE_PROT64)
949 goto done_prefixes;
33615aa9 950 c->rex_prefix = c->b;
b4c6abfe 951 continue;
6aa8b732 952 case 0xf0: /* LOCK */
e4e03ded 953 c->lock_prefix = 1;
6aa8b732 954 break;
ae6200ba 955 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 956 c->rep_prefix = REPNE_PREFIX;
957 break;
6aa8b732 958 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 959 c->rep_prefix = REPE_PREFIX;
6aa8b732 960 break;
6aa8b732
AK		 961 default:
962 goto done_prefixes;
963 }
b4c6abfe
LV		 964
965 /* Any legacy prefix after a REX prefix nullifies its effect. */
966
33615aa9 967 c->rex_prefix = 0;
6aa8b732
AK		 968 }
969
970done_prefixes:
971
972 /* REX prefix. */
1c73ef66 973 if (c->rex_prefix)
33615aa9 974 if (c->rex_prefix & 8)
e4e03ded 975 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 976
977 /* Opcode byte(s). */
e4e03ded
LV		 978 c->d = opcode_table[c->b];
979 if (c->d == 0) {
6aa8b732 980 /* Two-byte opcode? */
e4e03ded
LV		 981 if (c->b == 0x0f) {
982 c->twobyte = 1;
983 c->b = insn_fetch(u8, 1, c->eip);
984 c->d = twobyte_table[c->b];
6aa8b732 985 }
e09d082c 986 }
6aa8b732 987
d8769fed
MG		 988 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
989 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
990 return -1;
991 }
992
e09d082c
AK		 993 if (c->d & Group) {
994 group = c->d & GroupMask;
995 c->modrm = insn_fetch(u8, 1, c->eip);
996 --c->eip;
997
998 group = (group << 3) + ((c->modrm >> 3) & 7);
999 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1000 c->d = group2_table[group];
1001 else
1002 c->d = group_table[group];
1003 }
1004
1005 /* Unrecognised? */
1006 if (c->d == 0) {
1007 DPRINTF("Cannot emulate %02x\n", c->b);
1008 return -1;
6aa8b732
AK		 1009 }
1010
6e3d5dfb
AK		 1011 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1012 c->op_bytes = 8;
1013
6aa8b732 1014 /* ModRM and SIB bytes. */
1c73ef66
AK		 1015 if (c->d & ModRM)
1016 rc = decode_modrm(ctxt, ops);
1017 else if (c->d & MemAbs)
1018 rc = decode_abs(ctxt, ops);
1019 if (rc)
1020 goto done;
6aa8b732 1021
7a5b56df
AK		 1022 if (!c->has_seg_override)
1023 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1024
7a5b56df
AK		 1025 if (!(!c->twobyte && c->b == 0x8d))
1026 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1027
1028 if (c->ad_bytes != 8)
1029 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1030 /*
1031 * Decode and fetch the source operand: register, memory
1032 * or immediate.
1033 */
e4e03ded 1034 switch (c->d & SrcMask) {
6aa8b732
AK		 1035 case SrcNone:
1036 break;
1037 case SrcReg:
9f1ef3f8 1038 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1039 break;
1040 case SrcMem16:
e4e03ded 1041 c->src.bytes = 2;
6aa8b732
AK		 1042 goto srcmem_common;
1043 case SrcMem32:
e4e03ded 1044 c->src.bytes = 4;
6aa8b732
AK		 1045 goto srcmem_common;
1046 case SrcMem:
e4e03ded
LV		 1047 c->src.bytes = (c->d & ByteOp) ? 1 :
1048 c->op_bytes;
b85b9ee9 1049 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1050 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1051 break;
d77c26fc 1052 srcmem_common:
4e62417b
AJ		 1053 /*
1054 * For instructions with a ModR/M byte, switch to register
1055 * access if Mod = 3.
1056 */
e4e03ded
LV		 1057 if ((c->d & ModRM) && c->modrm_mod == 3) {
1058 c->src.type = OP_REG;
66b85505 1059 c->src.val = c->modrm_val;
107d6d2e 1060 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1061 break;
1062 }
e4e03ded 1063 c->src.type = OP_MEM;
6aa8b732
AK		 1064 break;
1065 case SrcImm:
c9eaf20f 1066 case SrcImmU:
e4e03ded
LV		 1067 c->src.type = OP_IMM;
1068 c->src.ptr = (unsigned long *)c->eip;
1069 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1070 if (c->src.bytes == 8)
1071 c->src.bytes = 4;
6aa8b732 1072 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1073 switch (c->src.bytes) {
6aa8b732 1074 case 1:
e4e03ded 1075 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1076 break;
1077 case 2:
e4e03ded 1078 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1079 break;
1080 case 4:
e4e03ded 1081 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1082 break;
1083 }
c9eaf20f
AK		 1084 if ((c->d & SrcMask) == SrcImmU) {
1085 switch (c->src.bytes) {
1086 case 1:
1087 c->src.val &= 0xff;
1088 break;
1089 case 2:
1090 c->src.val &= 0xffff;
1091 break;
1092 case 4:
1093 c->src.val &= 0xffffffff;
1094 break;
1095 }
1096 }
6aa8b732
AK		 1097 break;
1098 case SrcImmByte:
341de7e3 1099 case SrcImmUByte:
e4e03ded
LV		 1100 c->src.type = OP_IMM;
1101 c->src.ptr = (unsigned long *)c->eip;
1102 c->src.bytes = 1;
341de7e3
GN		 1103 if ((c->d & SrcMask) == SrcImmByte)
1104 c->src.val = insn_fetch(s8, 1, c->eip);
1105 else
1106 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1107 break;
bfcadf83
GT		 1108 case SrcOne:
1109 c->src.bytes = 1;
1110 c->src.val = 1;
1111 break;
6aa8b732
AK		 1112 }
1113
0dc8d10f
GT		 1114 /*
1115 * Decode and fetch the second source operand: register, memory
1116 * or immediate.
1117 */
1118 switch (c->d & Src2Mask) {
1119 case Src2None:
1120 break;
1121 case Src2CL:
1122 c->src2.bytes = 1;
1123 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1124 break;
1125 case Src2ImmByte:
1126 c->src2.type = OP_IMM;
1127 c->src2.ptr = (unsigned long *)c->eip;
1128 c->src2.bytes = 1;
1129 c->src2.val = insn_fetch(u8, 1, c->eip);
1130 break;
a5f868bd
GN		 1131 case Src2Imm16:
1132 c->src2.type = OP_IMM;
1133 c->src2.ptr = (unsigned long *)c->eip;
1134 c->src2.bytes = 2;
1135 c->src2.val = insn_fetch(u16, 2, c->eip);
1136 break;
0dc8d10f
GT		 1137 case Src2One:
1138 c->src2.bytes = 1;
1139 c->src2.val = 1;
1140 break;
1141 }
1142
038e51de 1143 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1144 switch (c->d & DstMask) {
038e51de
AK		 1145 case ImplicitOps:
1146 /* Special instructions do their own operand decoding. */
8b4caf66 1147 return 0;
038e51de 1148 case DstReg:
9f1ef3f8 1149 decode_register_operand(&c->dst, c,
3c118e24 1150 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1151 break;
1152 case DstMem:
e4e03ded 1153 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1154 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1155 c->dst.type = OP_REG;
66b85505 1156 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1157 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1158 break;
1159 }
8b4caf66
LV		 1160 c->dst.type = OP_MEM;
1161 break;
9c9fddd0
GT		 1162 case DstAcc:
1163 c->dst.type = OP_REG;
1164 c->dst.bytes = c->op_bytes;
1165 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1166 switch (c->op_bytes) {
1167 case 1:
1168 c->dst.val = *(u8 *)c->dst.ptr;
1169 break;
1170 case 2:
1171 c->dst.val = *(u16 *)c->dst.ptr;
1172 break;
1173 case 4:
1174 c->dst.val = *(u32 *)c->dst.ptr;
1175 break;
1176 }
1177 c->dst.orig_val = c->dst.val;
1178 break;
8b4caf66
LV		 1179 }
1180
f5b4edcd
AK		 1181 if (c->rip_relative)
1182 c->modrm_ea += c->eip;
1183
8b4caf66
LV		 1184done:
1185 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1186}
1187
8cdbd2c9
LV		 1188static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1189{
1190 struct decode_cache *c = &ctxt->decode;
1191
1192 c->dst.type = OP_MEM;
1193 c->dst.bytes = c->op_bytes;
1194 c->dst.val = c->src.val;
7a957275 1195 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1196 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1197 c->regs[VCPU_REGS_RSP]);
1198}
1199
faa5a3ae 1200static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1201 struct x86_emulate_ops *ops,
1202 void *dest, int len)
8cdbd2c9
LV		 1203{
1204 struct decode_cache *c = &ctxt->decode;
1205 int rc;
1206
781d0edc
AK		 1207 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1208 c->regs[VCPU_REGS_RSP]),
350f69dc 1209 dest, len, ctxt->vcpu);
b60d513c 1210 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1211 return rc;
1212
350f69dc 1213 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1214 return rc;
1215}
8cdbd2c9 1216
0934ac9d
MG		 1217static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1218{
1219 struct decode_cache *c = &ctxt->decode;
1220 struct kvm_segment segment;
1221
1222 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1223
1224 c->src.val = segment.selector;
1225 emulate_push(ctxt);
1226}
1227
1228static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1229 struct x86_emulate_ops *ops, int seg)
1230{
1231 struct decode_cache *c = &ctxt->decode;
1232 unsigned long selector;
1233 int rc;
1234
1235 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1236 if (rc != 0)
1237 return rc;
1238
1239 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1240 return rc;
1241}
1242
abcf14b5
MG		 1243static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1244{
1245 struct decode_cache *c = &ctxt->decode;
1246 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1247 int reg = VCPU_REGS_RAX;
1248
1249 while (reg <= VCPU_REGS_RDI) {
1250 (reg == VCPU_REGS_RSP) ?
1251 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1252
1253 emulate_push(ctxt);
1254 ++reg;
1255 }
1256}
1257
1258static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1259 struct x86_emulate_ops *ops)
1260{
1261 struct decode_cache *c = &ctxt->decode;
1262 int rc = 0;
1263 int reg = VCPU_REGS_RDI;
1264
1265 while (reg >= VCPU_REGS_RAX) {
1266 if (reg == VCPU_REGS_RSP) {
1267 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1268 c->op_bytes);
1269 --reg;
1270 }
1271
1272 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1273 if (rc != 0)
1274 break;
1275 --reg;
1276 }
1277 return rc;
1278}
1279
faa5a3ae
AK		 1280static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1281 struct x86_emulate_ops *ops)
1282{
1283 struct decode_cache *c = &ctxt->decode;
1284 int rc;
1285
350f69dc 1286 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1287 if (rc != 0)
1288 return rc;
8cdbd2c9
LV		 1289 return 0;
1290}
1291
05f086f8 1292static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1293{
05f086f8 1294 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1295 switch (c->modrm_reg) {
1296 case 0: /* rol */
05f086f8 1297 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1298 break;
1299 case 1: /* ror */
05f086f8 1300 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1301 break;
1302 case 2: /* rcl */
05f086f8 1303 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1304 break;
1305 case 3: /* rcr */
05f086f8 1306 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1307 break;
1308 case 4: /* sal/shl */
1309 case 6: /* sal/shl */
05f086f8 1310 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1311 break;
1312 case 5: /* shr */
05f086f8 1313 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1314 break;
1315 case 7: /* sar */
05f086f8 1316 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1317 break;
1318 }
1319}
1320
1321static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1322 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1323{
1324 struct decode_cache *c = &ctxt->decode;
1325 int rc = 0;
1326
1327 switch (c->modrm_reg) {
1328 case 0 ... 1: /* test */
05f086f8 1329 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1330 break;
1331 case 2: /* not */
1332 c->dst.val = ~c->dst.val;
1333 break;
1334 case 3: /* neg */
05f086f8 1335 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1336 break;
1337 default:
1338 DPRINTF("Cannot emulate %02x\n", c->b);
1339 rc = X86EMUL_UNHANDLEABLE;
1340 break;
1341 }
8cdbd2c9
LV		 1342 return rc;
1343}
1344
1345static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1346 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1347{
1348 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1349
1350 switch (c->modrm_reg) {
1351 case 0: /* inc */
05f086f8 1352 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1353 break;
1354 case 1: /* dec */
05f086f8 1355 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1356 break;
d19292e4
MG		 1357 case 2: /* call near abs */ {
1358 long int old_eip;
1359 old_eip = c->eip;
1360 c->eip = c->src.val;
1361 c->src.val = old_eip;
1362 emulate_push(ctxt);
1363 break;
1364 }
8cdbd2c9 1365 case 4: /* jmp abs */
fd60754e 1366 c->eip = c->src.val;
8cdbd2c9
LV		 1367 break;
1368 case 6: /* push */
fd60754e 1369 emulate_push(ctxt);
8cdbd2c9 1370 break;
8cdbd2c9
LV		 1371 }
1372 return 0;
1373}
1374
1375static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1376 struct x86_emulate_ops *ops,
e8d8d7fe 1377 unsigned long memop)
8cdbd2c9
LV		 1378{
1379 struct decode_cache *c = &ctxt->decode;
1380 u64 old, new;
1381 int rc;
1382
e8d8d7fe 1383 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1384 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1385 return rc;
1386
1387 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1388 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1389
1390 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1391 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1392 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1393
1394 } else {
1395 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1396 (u32) c->regs[VCPU_REGS_RBX];
1397
e8d8d7fe 1398 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1399 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1400 return rc;
05f086f8 1401 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1402 }
1403 return 0;
1404}
1405
a77ab5ea
AK		 1406static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1407 struct x86_emulate_ops *ops)
1408{
1409 struct decode_cache *c = &ctxt->decode;
1410 int rc;
1411 unsigned long cs;
1412
1413 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1414 if (rc)
1415 return rc;
1416 if (c->op_bytes == 4)
1417 c->eip = (u32)c->eip;
1418 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1419 if (rc)
1420 return rc;
1421 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1422 return rc;
1423}
1424
8cdbd2c9
LV		 1425static inline int writeback(struct x86_emulate_ctxt *ctxt,
1426 struct x86_emulate_ops *ops)
1427{
1428 int rc;
1429 struct decode_cache *c = &ctxt->decode;
1430
1431 switch (c->dst.type) {
1432 case OP_REG:
1433 /* The 4-byte case *is* correct:
1434 * in 64-bit mode we zero-extend.
1435 */
1436 switch (c->dst.bytes) {
1437 case 1:
1438 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1439 break;
1440 case 2:
1441 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1442 break;
1443 case 4:
1444 *c->dst.ptr = (u32)c->dst.val;
1445 break; /* 64b: zero-ext */
1446 case 8:
1447 *c->dst.ptr = c->dst.val;
1448 break;
1449 }
1450 break;
1451 case OP_MEM:
1452 if (c->lock_prefix)
1453 rc = ops->cmpxchg_emulated(
1454 (unsigned long)c->dst.ptr,
1455 &c->dst.orig_val,
1456 &c->dst.val,
1457 c->dst.bytes,
1458 ctxt->vcpu);
1459 else
1460 rc = ops->write_emulated(
1461 (unsigned long)c->dst.ptr,
1462 &c->dst.val,
1463 c->dst.bytes,
1464 ctxt->vcpu);
b60d513c 1465 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1466 return rc;
a01af5ec
LV		 1467 break;
1468 case OP_NONE:
1469 /* no writeback */
1470 break;
8cdbd2c9
LV		 1471 default:
1472 break;
1473 }
1474 return 0;
1475}
1476
a3f9d398 1477static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1478{
1479 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1480 /*
1481 * an sti; sti; sequence only disable interrupts for the first
1482 * instruction. So, if the last instruction, be it emulated or
1483 * not, left the system with the INT_STI flag enabled, it
1484 * means that the last instruction is an sti. We should not
1485 * leave the flag on in this case. The same goes for mov ss
1486 */
1487 if (!(int_shadow & mask))
1488 ctxt->interruptibility = mask;
1489}
1490
e66bb2cc
AP		 1491static inline void
1492setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1493 struct kvm_segment *cs, struct kvm_segment *ss)
1494{
1495 memset(cs, 0, sizeof(struct kvm_segment));
1496 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1497 memset(ss, 0, sizeof(struct kvm_segment));
1498
1499 cs->l = 0; /* will be adjusted later */
1500 cs->base = 0; /* flat segment */
1501 cs->g = 1; /* 4kb granularity */
1502 cs->limit = 0xffffffff; /* 4GB limit */
1503 cs->type = 0x0b; /* Read, Execute, Accessed */
1504 cs->s = 1;
1505 cs->dpl = 0; /* will be adjusted later */
1506 cs->present = 1;
1507 cs->db = 1;
1508
1509 ss->unusable = 0;
1510 ss->base = 0; /* flat segment */
1511 ss->limit = 0xffffffff; /* 4GB limit */
1512 ss->g = 1; /* 4kb granularity */
1513 ss->s = 1;
1514 ss->type = 0x03; /* Read/Write, Accessed */
1515 ss->db = 1; /* 32bit stack segment */
1516 ss->dpl = 0;
1517 ss->present = 1;
1518}
1519
1520static int
1521emulate_syscall(struct x86_emulate_ctxt *ctxt)
1522{
1523 struct decode_cache *c = &ctxt->decode;
1524 struct kvm_segment cs, ss;
1525 u64 msr_data;
1526
1527 /* syscall is not available in real mode */
1528 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
a0044755 1529 || ctxt->mode == X86EMUL_MODE_VM86)
e66bb2cc
AP		 1530 return -1;
1531
1532 setup_syscalls_segments(ctxt, &cs, &ss);
1533
1534 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1535 msr_data >>= 32;
1536 cs.selector = (u16)(msr_data & 0xfffc);
1537 ss.selector = (u16)(msr_data + 8);
1538
1539 if (is_long_mode(ctxt->vcpu)) {
1540 cs.db = 0;
1541 cs.l = 1;
1542 }
1543 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1544 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1545
1546 c->regs[VCPU_REGS_RCX] = c->eip;
1547 if (is_long_mode(ctxt->vcpu)) {
1548#ifdef CONFIG_X86_64
1549 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1550
1551 kvm_x86_ops->get_msr(ctxt->vcpu,
1552 ctxt->mode == X86EMUL_MODE_PROT64 ?
1553 MSR_LSTAR : MSR_CSTAR, &msr_data);
1554 c->eip = msr_data;
1555
1556 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1557 ctxt->eflags &= ~(msr_data | EFLG_RF);
1558#endif
1559 } else {
1560 /* legacy mode */
1561 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1562 c->eip = (u32)msr_data;
1563
1564 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1565 }
1566
1567 return 0;
1568}
1569
8c604352
AP		 1570static int
1571emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1572{
1573 struct decode_cache *c = &ctxt->decode;
1574 struct kvm_segment cs, ss;
1575 u64 msr_data;
1576
1577 /* inject #UD if LOCK prefix is used */
1578 if (c->lock_prefix)
1579 return -1;
1580
a0044755
GN		 1581 /* inject #GP if in real mode */
1582 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352
AP		 1583 kvm_inject_gp(ctxt->vcpu, 0);
1584 return -1;
1585 }
1586
1587 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1588 * Therefore, we inject an #UD.
1589 */
1590 if (ctxt->mode == X86EMUL_MODE_PROT64)
1591 return -1;
1592
1593 setup_syscalls_segments(ctxt, &cs, &ss);
1594
1595 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1596 switch (ctxt->mode) {
1597 case X86EMUL_MODE_PROT32:
1598 if ((msr_data & 0xfffc) == 0x0) {
1599 kvm_inject_gp(ctxt->vcpu, 0);
1600 return -1;
1601 }
1602 break;
1603 case X86EMUL_MODE_PROT64:
1604 if (msr_data == 0x0) {
1605 kvm_inject_gp(ctxt->vcpu, 0);
1606 return -1;
1607 }
1608 break;
1609 }
1610
1611 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1612 cs.selector = (u16)msr_data;
1613 cs.selector &= ~SELECTOR_RPL_MASK;
1614 ss.selector = cs.selector + 8;
1615 ss.selector &= ~SELECTOR_RPL_MASK;
1616 if (ctxt->mode == X86EMUL_MODE_PROT64
1617 || is_long_mode(ctxt->vcpu)) {
1618 cs.db = 0;
1619 cs.l = 1;
1620 }
1621
1622 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1623 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1624
1625 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1626 c->eip = msr_data;
1627
1628 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1629 c->regs[VCPU_REGS_RSP] = msr_data;
1630
1631 return 0;
1632}
1633
4668f050
AP		 1634static int
1635emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1636{
1637 struct decode_cache *c = &ctxt->decode;
1638 struct kvm_segment cs, ss;
1639 u64 msr_data;
1640 int usermode;
1641
1642 /* inject #UD if LOCK prefix is used */
1643 if (c->lock_prefix)
1644 return -1;
1645
a0044755
GN		 1646 /* inject #GP if in real mode or Virtual 8086 mode */
1647 if (ctxt->mode == X86EMUL_MODE_REAL ||
1648 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050
AP		 1649 kvm_inject_gp(ctxt->vcpu, 0);
1650 return -1;
1651 }
1652
1653 /* sysexit must be called from CPL 0 */
1654 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1655 kvm_inject_gp(ctxt->vcpu, 0);
1656 return -1;
1657 }
1658
1659 setup_syscalls_segments(ctxt, &cs, &ss);
1660
1661 if ((c->rex_prefix & 0x8) != 0x0)
1662 usermode = X86EMUL_MODE_PROT64;
1663 else
1664 usermode = X86EMUL_MODE_PROT32;
1665
1666 cs.dpl = 3;
1667 ss.dpl = 3;
1668 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1669 switch (usermode) {
1670 case X86EMUL_MODE_PROT32:
1671 cs.selector = (u16)(msr_data + 16);
1672 if ((msr_data & 0xfffc) == 0x0) {
1673 kvm_inject_gp(ctxt->vcpu, 0);
1674 return -1;
1675 }
1676 ss.selector = (u16)(msr_data + 24);
1677 break;
1678 case X86EMUL_MODE_PROT64:
1679 cs.selector = (u16)(msr_data + 32);
1680 if (msr_data == 0x0) {
1681 kvm_inject_gp(ctxt->vcpu, 0);
1682 return -1;
1683 }
1684 ss.selector = cs.selector + 8;
1685 cs.db = 0;
1686 cs.l = 1;
1687 break;
1688 }
1689 cs.selector |= SELECTOR_RPL_MASK;
1690 ss.selector |= SELECTOR_RPL_MASK;
1691
1692 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1693 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1694
1695 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1696 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1697
1698 return 0;
1699}
1700
f850e2e6
GN		 1701static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
1702{
1703 int iopl;
1704 if (ctxt->mode == X86EMUL_MODE_REAL)
1705 return false;
1706 if (ctxt->mode == X86EMUL_MODE_VM86)
1707 return true;
1708 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1709 return kvm_x86_ops->get_cpl(ctxt->vcpu) > iopl;
1710}
1711
1712static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1713 struct x86_emulate_ops *ops,
1714 u16 port, u16 len)
1715{
1716 struct kvm_segment tr_seg;
1717 int r;
1718 u16 io_bitmap_ptr;
1719 u8 perm, bit_idx = port & 0x7;
1720 unsigned mask = (1 << len) - 1;
1721
1722 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
1723 if (tr_seg.unusable)
1724 return false;
1725 if (tr_seg.limit < 103)
1726 return false;
1727 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
1728 NULL);
1729 if (r != X86EMUL_CONTINUE)
1730 return false;
1731 if (io_bitmap_ptr + port/8 > tr_seg.limit)
1732 return false;
1733 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
1734 ctxt->vcpu, NULL);
1735 if (r != X86EMUL_CONTINUE)
1736 return false;
1737 if ((perm >> bit_idx) & mask)
1738 return false;
1739 return true;
1740}
1741
1742static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1743 struct x86_emulate_ops *ops,
1744 u16 port, u16 len)
1745{
1746 if (emulator_bad_iopl(ctxt))
1747 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1748 return false;
1749 return true;
1750}
1751
8b4caf66 1752int
1be3aa47 1753x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1754{
e8d8d7fe 1755 unsigned long memop = 0;
8b4caf66 1756 u64 msr_data;
3427318f 1757 unsigned long saved_eip = 0;
8b4caf66 1758 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1759 unsigned int port;
1760 int io_dir_in;
1be3aa47 1761 int rc = 0;
8b4caf66 1762
310b5d30
GC		 1763 ctxt->interruptibility = 0;
1764
3427318f
LV		 1765 /* Shadow copy of register state. Committed on successful emulation.
1766 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1767 * modify them.
1768 */
1769
ad312c7c 1770 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1771 saved_eip = c->eip;
1772
c7e75a3d 1773 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1774 memop = c->modrm_ea;
8b4caf66 1775
b9fa9d6b
AK		 1776 if (c->rep_prefix && (c->d & String)) {
1777 /* All REP prefixes have the same first termination condition */
1778 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1779 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1780 goto done;
1781 }
1782 /* The second termination condition only applies for REPE
1783 * and REPNE. Test if the repeat string operation prefix is
1784 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1785 * corresponding termination condition according to:
1786 * - if REPE/REPZ and ZF = 0 then done
1787 * - if REPNE/REPNZ and ZF = 1 then done
1788 */
1789 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1790 (c->b == 0xae) || (c->b == 0xaf)) {
1791 if ((c->rep_prefix == REPE_PREFIX) &&
1792 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1793 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1794 goto done;
1795 }
1796 if ((c->rep_prefix == REPNE_PREFIX) &&
1797 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1798 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1799 goto done;
1800 }
1801 }
1802 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1803 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1804 }
1805
8b4caf66 1806 if (c->src.type == OP_MEM) {
e8d8d7fe 1807 c->src.ptr = (unsigned long *)memop;
8b4caf66 1808 c->src.val = 0;
d77c26fc
MD		 1809 rc = ops->read_emulated((unsigned long)c->src.ptr,
1810 &c->src.val,
1811 c->src.bytes,
1812 ctxt->vcpu);
b60d513c 1813 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 1814 goto done;
1815 c->src.orig_val = c->src.val;
1816 }
1817
1818 if ((c->d & DstMask) == ImplicitOps)
1819 goto special_insn;
1820
1821
1822 if (c->dst.type == OP_MEM) {
e8d8d7fe 1823 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1824 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1825 c->dst.val = 0;
e4e03ded
LV		 1826 if (c->d & BitOp) {
1827 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1828
e4e03ded
LV		 1829 c->dst.ptr = (void *)c->dst.ptr +
1830 (c->src.val & mask) / 8;
038e51de 1831 }
b60d513c
TY		 1832 if (!(c->d & Mov)) {
1833 /* optimisation - avoid slow emulated read */
1834 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1835 &c->dst.val,
1836 c->dst.bytes,
1837 ctxt->vcpu);
1838 if (rc != X86EMUL_CONTINUE)
1839 goto done;
1840 }
038e51de 1841 }
e4e03ded 1842 c->dst.orig_val = c->dst.val;
038e51de 1843
018a98db
AK		 1844special_insn:
1845
e4e03ded 1846 if (c->twobyte)
6aa8b732
AK		 1847 goto twobyte_insn;
1848
e4e03ded 1849 switch (c->b) {
6aa8b732
AK		 1850 case 0x00 ... 0x05:
1851 add: /* add */
05f086f8 1852 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1853 break;
0934ac9d 1854 case 0x06: /* push es */
0934ac9d
MG		 1855 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1856 break;
1857 case 0x07: /* pop es */
0934ac9d
MG		 1858 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1859 if (rc != 0)
1860 goto done;
1861 break;
6aa8b732
AK		 1862 case 0x08 ... 0x0d:
1863 or: /* or */
05f086f8 1864 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1865 break;
0934ac9d 1866 case 0x0e: /* push cs */
0934ac9d
MG		 1867 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1868 break;
6aa8b732
AK		 1869 case 0x10 ... 0x15:
1870 adc: /* adc */
05f086f8 1871 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1872 break;
0934ac9d 1873 case 0x16: /* push ss */
0934ac9d
MG		 1874 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1875 break;
1876 case 0x17: /* pop ss */
0934ac9d
MG		 1877 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1878 if (rc != 0)
1879 goto done;
1880 break;
6aa8b732
AK		 1881 case 0x18 ... 0x1d:
1882 sbb: /* sbb */
05f086f8 1883 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1884 break;
0934ac9d 1885 case 0x1e: /* push ds */
0934ac9d
MG		 1886 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1887 break;
1888 case 0x1f: /* pop ds */
0934ac9d
MG		 1889 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1890 if (rc != 0)
1891 goto done;
1892 break;
aa3a816b 1893 case 0x20 ... 0x25:
6aa8b732 1894 and: /* and */
05f086f8 1895 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1896 break;
1897 case 0x28 ... 0x2d:
1898 sub: /* sub */
05f086f8 1899 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1900 break;
1901 case 0x30 ... 0x35:
1902 xor: /* xor */
05f086f8 1903 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1904 break;
1905 case 0x38 ... 0x3d:
1906 cmp: /* cmp */
05f086f8 1907 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1908 break;
33615aa9
AK		 1909 case 0x40 ... 0x47: /* inc r16/r32 */
1910 emulate_1op("inc", c->dst, ctxt->eflags);
1911 break;
1912 case 0x48 ... 0x4f: /* dec r16/r32 */
1913 emulate_1op("dec", c->dst, ctxt->eflags);
1914 break;
1915 case 0x50 ... 0x57: /* push reg */
2786b014 1916 emulate_push(ctxt);
33615aa9
AK		 1917 break;
1918 case 0x58 ... 0x5f: /* pop reg */
1919 pop_instruction:
350f69dc 1920 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1921 if (rc != 0)
33615aa9 1922 goto done;
33615aa9 1923 break;
abcf14b5
MG		 1924 case 0x60: /* pusha */
1925 emulate_pusha(ctxt);
1926 break;
1927 case 0x61: /* popa */
1928 rc = emulate_popa(ctxt, ops);
1929 if (rc != 0)
1930 goto done;
1931 break;
6aa8b732 1932 case 0x63: /* movsxd */
8b4caf66 1933 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1934 goto cannot_emulate;
e4e03ded 1935 c->dst.val = (s32) c->src.val;
6aa8b732 1936 break;
91ed7a0e 1937 case 0x68: /* push imm */
018a98db 1938 case 0x6a: /* push imm8 */
018a98db
AK		 1939 emulate_push(ctxt);
1940 break;
1941 case 0x6c: /* insb */
1942 case 0x6d: /* insw/insd */
f850e2e6
GN		 1943 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
1944 (c->d & ByteOp) ? 1 : c->op_bytes)) {
1945 kvm_inject_gp(ctxt->vcpu, 0);
1946 goto done;
1947 }
1948 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1949 1,
1950 (c->d & ByteOp) ? 1 : c->op_bytes,
1951 c->rep_prefix ?
e4706772 1952 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1953 (ctxt->eflags & EFLG_DF),
7a5b56df 1954 register_address(c, es_base(ctxt),
018a98db
AK		 1955 c->regs[VCPU_REGS_RDI]),
1956 c->rep_prefix,
1957 c->regs[VCPU_REGS_RDX]) == 0) {
1958 c->eip = saved_eip;
1959 return -1;
1960 }
1961 return 0;
1962 case 0x6e: /* outsb */
1963 case 0x6f: /* outsw/outsd */
f850e2e6
GN		 1964 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
1965 (c->d & ByteOp) ? 1 : c->op_bytes)) {
1966 kvm_inject_gp(ctxt->vcpu, 0);
1967 goto done;
1968 }
851ba692 1969 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1970 0,
1971 (c->d & ByteOp) ? 1 : c->op_bytes,
1972 c->rep_prefix ?
e4706772 1973 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1974 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1975 register_address(c,
1976 seg_override_base(ctxt, c),
018a98db
AK		 1977 c->regs[VCPU_REGS_RSI]),
1978 c->rep_prefix,
1979 c->regs[VCPU_REGS_RDX]) == 0) {
1980 c->eip = saved_eip;
1981 return -1;
1982 }
1983 return 0;
b2833e3c 1984 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1985 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1986 jmp_rel(c, c->src.val);
018a98db 1987 break;
6aa8b732 1988 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1989 switch (c->modrm_reg) {
6aa8b732
AK		 1990 case 0:
1991 goto add;
1992 case 1:
1993 goto or;
1994 case 2:
1995 goto adc;
1996 case 3:
1997 goto sbb;
1998 case 4:
1999 goto and;
2000 case 5:
2001 goto sub;
2002 case 6:
2003 goto xor;
2004 case 7:
2005 goto cmp;
2006 }
2007 break;
2008 case 0x84 ... 0x85:
05f086f8 2009 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2010 break;
2011 case 0x86 ... 0x87: /* xchg */
b13354f8 2012 xchg:
6aa8b732 2013 /* Write back the register source. */
e4e03ded 2014 switch (c->dst.bytes) {
6aa8b732 2015 case 1:
e4e03ded 2016 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2017 break;
2018 case 2:
e4e03ded 2019 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2020 break;
2021 case 4:
e4e03ded 2022 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2023 break; /* 64b reg: zero-extend */
2024 case 8:
e4e03ded 2025 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2026 break;
2027 }
2028 /*
2029 * Write back the memory destination with implicit LOCK
2030 * prefix.
2031 */
e4e03ded
LV		 2032 c->dst.val = c->src.val;
2033 c->lock_prefix = 1;
6aa8b732 2034 break;
6aa8b732 2035 case 0x88 ... 0x8b: /* mov */
7de75248 2036 goto mov;
38d5bc6d
GT		 2037 case 0x8c: { /* mov r/m, sreg */
2038 struct kvm_segment segreg;
2039
2040 if (c->modrm_reg <= 5)
2041 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2042 else {
2043 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
2044 c->modrm);
2045 goto cannot_emulate;
2046 }
2047 c->dst.val = segreg.selector;
2048 break;
2049 }
7e0b54b1 2050 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2051 c->dst.val = c->modrm_ea;
7e0b54b1 2052 break;
4257198a
GT		 2053 case 0x8e: { /* mov seg, r/m16 */
2054 uint16_t sel;
2055 int type_bits;
2056 int err;
2057
2058 sel = c->src.val;
310b5d30
GC		 2059 if (c->modrm_reg == VCPU_SREG_SS)
2060 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
2061
4257198a
GT		 2062 if (c->modrm_reg <= 5) {
2063 type_bits = (c->modrm_reg == 1) ? 9 : 1;
2064 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
2065 type_bits, c->modrm_reg);
2066 } else {
2067 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
2068 c->modrm);
2069 goto cannot_emulate;
2070 }
2071
2072 if (err < 0)
2073 goto cannot_emulate;
2074
2075 c->dst.type = OP_NONE; /* Disable writeback. */
2076 break;
2077 }
6aa8b732 2078 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 2079 rc = emulate_grp1a(ctxt, ops);
2080 if (rc != 0)
6aa8b732 2081 goto done;
6aa8b732 2082 break;
b13354f8
MG		 2083 case 0x90: /* nop / xchg r8,rax */
2084 if (!(c->rex_prefix & 1)) { /* nop */
2085 c->dst.type = OP_NONE;
2086 break;
2087 }
2088 case 0x91 ... 0x97: /* xchg reg,rax */
2089 c->src.type = c->dst.type = OP_REG;
2090 c->src.bytes = c->dst.bytes = c->op_bytes;
2091 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2092 c->src.val = *(c->src.ptr);
2093 goto xchg;
fd2a7608 2094 case 0x9c: /* pushf */
05f086f8 2095 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2096 emulate_push(ctxt);
2097 break;
535eabcf 2098 case 0x9d: /* popf */
2b48cc75 2099 c->dst.type = OP_REG;
05f086f8 2100 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2101 c->dst.bytes = c->op_bytes;
535eabcf 2102 goto pop_instruction;
018a98db
AK		 2103 case 0xa0 ... 0xa1: /* mov */
2104 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2105 c->dst.val = c->src.val;
2106 break;
2107 case 0xa2 ... 0xa3: /* mov */
2108 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2109 break;
6aa8b732 2110 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2111 c->dst.type = OP_MEM;
2112 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2113 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2114 es_base(ctxt),
e4e03ded 2115 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2116 rc = ops->read_emulated(register_address(c,
2117 seg_override_base(ctxt, c),
2118 c->regs[VCPU_REGS_RSI]),
e4e03ded 2119 &c->dst.val,
b60d513c
TY		 2120 c->dst.bytes, ctxt->vcpu);
2121 if (rc != X86EMUL_CONTINUE)
6aa8b732 2122 goto done;
7a957275 2123 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2124 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2125 : c->dst.bytes);
7a957275 2126 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2127 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2128 : c->dst.bytes);
6aa8b732
AK		 2129 break;
2130 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2131 c->src.type = OP_NONE; /* Disable writeback. */
2132 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2133 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2134 seg_override_base(ctxt, c),
d7e5117a 2135 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2136 rc = ops->read_emulated((unsigned long)c->src.ptr,
2137 &c->src.val,
2138 c->src.bytes,
2139 ctxt->vcpu);
2140 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2141 goto done;
2142
2143 c->dst.type = OP_NONE; /* Disable writeback. */
2144 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2145 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2146 es_base(ctxt),
d7e5117a 2147 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2148 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2149 &c->dst.val,
2150 c->dst.bytes,
2151 ctxt->vcpu);
2152 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2153 goto done;
2154
2155 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2156
2157 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2158
7a957275 2159 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2160 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2161 : c->src.bytes);
7a957275 2162 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2163 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2164 : c->dst.bytes);
2165
2166 break;
6aa8b732 2167 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2168 c->dst.type = OP_MEM;
2169 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2170 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2171 es_base(ctxt),
a7e6c88a 2172 c->regs[VCPU_REGS_RDI]);
e4e03ded 2173 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2174 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2175 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2176 : c->dst.bytes);
6aa8b732
AK		 2177 break;
2178 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2179 c->dst.type = OP_REG;
2180 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2181 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2182 rc = ops->read_emulated(register_address(c,
2183 seg_override_base(ctxt, c),
2184 c->regs[VCPU_REGS_RSI]),
2185 &c->dst.val,
2186 c->dst.bytes,
2187 ctxt->vcpu);
2188 if (rc != X86EMUL_CONTINUE)
6aa8b732 2189 goto done;
7a957275 2190 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2191 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2192 : c->dst.bytes);
6aa8b732
AK		 2193 break;
2194 case 0xae ... 0xaf: /* scas */
2195 DPRINTF("Urk! I don't handle SCAS.\n");
2196 goto cannot_emulate;
a5e2e82b 2197 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2198 goto mov;
018a98db
AK		 2199 case 0xc0 ... 0xc1:
2200 emulate_grp2(ctxt);
2201 break;
111de5d6 2202 case 0xc3: /* ret */
cf5de4f8 2203 c->dst.type = OP_REG;
111de5d6 2204 c->dst.ptr = &c->eip;
cf5de4f8 2205 c->dst.bytes = c->op_bytes;
111de5d6 2206 goto pop_instruction;
018a98db
AK		 2207 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2208 mov:
2209 c->dst.val = c->src.val;
2210 break;
a77ab5ea
AK		 2211 case 0xcb: /* ret far */
2212 rc = emulate_ret_far(ctxt, ops);
2213 if (rc)
2214 goto done;
2215 break;
018a98db
AK		 2216 case 0xd0 ... 0xd1: /* Grp2 */
2217 c->src.val = 1;
2218 emulate_grp2(ctxt);
2219 break;
2220 case 0xd2 ... 0xd3: /* Grp2 */
2221 c->src.val = c->regs[VCPU_REGS_RCX];
2222 emulate_grp2(ctxt);
2223 break;
a6a3034c
MG		 2224 case 0xe4: /* inb */
2225 case 0xe5: /* in */
84ce66a6 2226 port = c->src.val;
a6a3034c
MG		 2227 io_dir_in = 1;
2228 goto do_io;
2229 case 0xe6: /* outb */
2230 case 0xe7: /* out */
84ce66a6 2231 port = c->src.val;
a6a3034c
MG		 2232 io_dir_in = 0;
2233 goto do_io;
1a52e051 2234 case 0xe8: /* call (near) */ {
d53c4777 2235 long int rel = c->src.val;
e4e03ded 2236 c->src.val = (unsigned long) c->eip;
7a957275 2237 jmp_rel(c, rel);
8cdbd2c9
LV		 2238 emulate_push(ctxt);
2239 break;
1a52e051
NK		 2240 }
2241 case 0xe9: /* jmp rel */
954cd36f 2242 goto jmp;
782b877c
GN		 2243 case 0xea: /* jmp far */
2244 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2245 VCPU_SREG_CS) < 0) {
954cd36f
GT		 2246 DPRINTF("jmp far: Failed to load CS descriptor\n");
2247 goto cannot_emulate;
2248 }
2249
782b877c 2250 c->eip = c->src.val;
954cd36f 2251 break;
954cd36f
GT		 2252 case 0xeb:
2253 jmp: /* jmp rel short */
7a957275 2254 jmp_rel(c, c->src.val);
a01af5ec 2255 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2256 break;
a6a3034c
MG		 2257 case 0xec: /* in al,dx */
2258 case 0xed: /* in (e/r)ax,dx */
2259 port = c->regs[VCPU_REGS_RDX];
2260 io_dir_in = 1;
2261 goto do_io;
2262 case 0xee: /* out al,dx */
2263 case 0xef: /* out (e/r)ax,dx */
2264 port = c->regs[VCPU_REGS_RDX];
2265 io_dir_in = 0;
f850e2e6
GN		 2266 do_io:
2267 if (!emulator_io_permited(ctxt, ops, port,
2268 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2269 kvm_inject_gp(ctxt->vcpu, 0);
2270 goto done;
2271 }
2272 if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2273 (c->d & ByteOp) ? 1 : c->op_bytes,
2274 port) != 0) {
2275 c->eip = saved_eip;
2276 goto cannot_emulate;
2277 }
e93f36bc 2278 break;
111de5d6 2279 case 0xf4: /* hlt */
ad312c7c 2280 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2281 break;
111de5d6
AK		 2282 case 0xf5: /* cmc */
2283 /* complement carry flag from eflags reg */
2284 ctxt->eflags ^= EFLG_CF;
2285 c->dst.type = OP_NONE; /* Disable writeback. */
2286 break;
018a98db
AK		 2287 case 0xf6 ... 0xf7: /* Grp3 */
2288 rc = emulate_grp3(ctxt, ops);
2289 if (rc != 0)
2290 goto done;
2291 break;
111de5d6
AK		 2292 case 0xf8: /* clc */
2293 ctxt->eflags &= ~EFLG_CF;
2294 c->dst.type = OP_NONE; /* Disable writeback. */
2295 break;
2296 case 0xfa: /* cli */
f850e2e6
GN		 2297 if (emulator_bad_iopl(ctxt))
2298 kvm_inject_gp(ctxt->vcpu, 0);
2299 else {
2300 ctxt->eflags &= ~X86_EFLAGS_IF;
2301 c->dst.type = OP_NONE; /* Disable writeback. */
2302 }
111de5d6
AK		 2303 break;
2304 case 0xfb: /* sti */
f850e2e6
GN		 2305 if (emulator_bad_iopl(ctxt))
2306 kvm_inject_gp(ctxt->vcpu, 0);
2307 else {
2308 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
2309 ctxt->eflags |= X86_EFLAGS_IF;
2310 c->dst.type = OP_NONE; /* Disable writeback. */
2311 }
111de5d6 2312 break;
fb4616f4
MG		 2313 case 0xfc: /* cld */
2314 ctxt->eflags &= ~EFLG_DF;
2315 c->dst.type = OP_NONE; /* Disable writeback. */
2316 break;
2317 case 0xfd: /* std */
2318 ctxt->eflags |= EFLG_DF;
2319 c->dst.type = OP_NONE; /* Disable writeback. */
2320 break;
018a98db
AK		 2321 case 0xfe ... 0xff: /* Grp4/Grp5 */
2322 rc = emulate_grp45(ctxt, ops);
2323 if (rc != 0)
2324 goto done;
2325 break;
6aa8b732 2326 }
018a98db
AK		 2327
2328writeback:
2329 rc = writeback(ctxt, ops);
2330 if (rc != 0)
2331 goto done;
2332
2333 /* Commit shadow register state. */
ad312c7c 2334 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2335 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2336
2337done:
2338 if (rc == X86EMUL_UNHANDLEABLE) {
2339 c->eip = saved_eip;
2340 return -1;
2341 }
2342 return 0;
6aa8b732
AK		 2343
2344twobyte_insn:
e4e03ded 2345 switch (c->b) {
6aa8b732 2346 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2347 switch (c->modrm_reg) {
6aa8b732
AK		 2348 u16 size;
2349 unsigned long address;
2350
aca7f966 2351 case 0: /* vmcall */
e4e03ded 2352 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2353 goto cannot_emulate;
2354
7aa81cc0
AL		 2355 rc = kvm_fix_hypercall(ctxt->vcpu);
2356 if (rc)
2357 goto done;
2358
33e3885d 2359 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2360 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2361 /* Disable writeback. */
2362 c->dst.type = OP_NONE;
aca7f966 2363 break;
6aa8b732 2364 case 2: /* lgdt */
e4e03ded
LV		 2365 rc = read_descriptor(ctxt, ops, c->src.ptr,
2366 &size, &address, c->op_bytes);
6aa8b732
AK		 2367 if (rc)
2368 goto done;
2369 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2370 /* Disable writeback. */
2371 c->dst.type = OP_NONE;
6aa8b732 2372 break;
aca7f966 2373 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2374 if (c->modrm_mod == 3) {
2375 switch (c->modrm_rm) {
2376 case 1:
2377 rc = kvm_fix_hypercall(ctxt->vcpu);
2378 if (rc)
2379 goto done;
2380 break;
2381 default:
2382 goto cannot_emulate;
2383 }
aca7f966 2384 } else {
e4e03ded 2385 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2386 &size, &address,
e4e03ded 2387 c->op_bytes);
aca7f966
AL		 2388 if (rc)
2389 goto done;
2390 realmode_lidt(ctxt->vcpu, size, address);
2391 }
16286d08
AK		 2392 /* Disable writeback. */
2393 c->dst.type = OP_NONE;
6aa8b732
AK		 2394 break;
2395 case 4: /* smsw */
16286d08
AK		 2396 c->dst.bytes = 2;
2397 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2398 break;
2399 case 6: /* lmsw */
16286d08
AK		 2400 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2401 &ctxt->eflags);
dc7457ea 2402 c->dst.type = OP_NONE;
6aa8b732
AK		 2403 break;
2404 case 7: /* invlpg*/
e8d8d7fe 2405 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2406 /* Disable writeback. */
2407 c->dst.type = OP_NONE;
6aa8b732
AK		 2408 break;
2409 default:
2410 goto cannot_emulate;
2411 }
2412 break;
e99f0507 2413 case 0x05: /* syscall */
e66bb2cc
AP		 2414 if (emulate_syscall(ctxt) == -1)
2415 goto cannot_emulate;
2416 else
2417 goto writeback;
e99f0507 2418 break;
018a98db
AK		 2419 case 0x06:
2420 emulate_clts(ctxt->vcpu);
2421 c->dst.type = OP_NONE;
2422 break;
2423 case 0x08: /* invd */
2424 case 0x09: /* wbinvd */
2425 case 0x0d: /* GrpP (prefetch) */
2426 case 0x18: /* Grp16 (prefetch/nop) */
2427 c->dst.type = OP_NONE;
2428 break;
2429 case 0x20: /* mov cr, reg */
2430 if (c->modrm_mod != 3)
2431 goto cannot_emulate;
2432 c->regs[c->modrm_rm] =
2433 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2434 c->dst.type = OP_NONE; /* no writeback */
2435 break;
6aa8b732 2436 case 0x21: /* mov from dr to reg */
e4e03ded 2437 if (c->modrm_mod != 3)
6aa8b732 2438 goto cannot_emulate;
8cdbd2c9 2439 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2440 if (rc)
2441 goto cannot_emulate;
2442 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2443 break;
018a98db
AK		 2444 case 0x22: /* mov reg, cr */
2445 if (c->modrm_mod != 3)
2446 goto cannot_emulate;
2447 realmode_set_cr(ctxt->vcpu,
2448 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2449 c->dst.type = OP_NONE;
2450 break;
6aa8b732 2451 case 0x23: /* mov from reg to dr */
e4e03ded 2452 if (c->modrm_mod != 3)
6aa8b732 2453 goto cannot_emulate;
e4e03ded
LV		 2454 rc = emulator_set_dr(ctxt, c->modrm_reg,
2455 c->regs[c->modrm_rm]);
a01af5ec
LV		 2456 if (rc)
2457 goto cannot_emulate;
2458 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2459 break;
018a98db
AK		 2460 case 0x30:
2461 /* wrmsr */
2462 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2463 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2464 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2465 if (rc) {
c1a5d4f9 2466 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2467 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2468 }
2469 rc = X86EMUL_CONTINUE;
2470 c->dst.type = OP_NONE;
2471 break;
2472 case 0x32:
2473 /* rdmsr */
2474 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2475 if (rc) {
c1a5d4f9 2476 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2477 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2478 } else {
2479 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2480 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2481 }
2482 rc = X86EMUL_CONTINUE;
2483 c->dst.type = OP_NONE;
2484 break;
e99f0507 2485 case 0x34: /* sysenter */
8c604352
AP		 2486 if (emulate_sysenter(ctxt) == -1)
2487 goto cannot_emulate;
2488 else
2489 goto writeback;
e99f0507
AP		 2490 break;
2491 case 0x35: /* sysexit */
4668f050
AP		 2492 if (emulate_sysexit(ctxt) == -1)
2493 goto cannot_emulate;
2494 else
2495 goto writeback;
e99f0507 2496 break;
6aa8b732 2497 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2498 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2499 if (!test_cc(c->b, ctxt->eflags))
2500 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2501 break;
b2833e3c 2502 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2503 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2504 jmp_rel(c, c->src.val);
018a98db
AK		 2505 c->dst.type = OP_NONE;
2506 break;
0934ac9d
MG		 2507 case 0xa0: /* push fs */
2508 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2509 break;
2510 case 0xa1: /* pop fs */
2511 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2512 if (rc != 0)
2513 goto done;
2514 break;
7de75248
NK		 2515 case 0xa3:
2516 bt: /* bt */
e4f8e039 2517 c->dst.type = OP_NONE;
e4e03ded
LV		 2518 /* only subword offset */
2519 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2520 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2521 break;
9bf8ea42
GT		 2522 case 0xa4: /* shld imm8, r, r/m */
2523 case 0xa5: /* shld cl, r, r/m */
2524 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2525 break;
0934ac9d
MG		 2526 case 0xa8: /* push gs */
2527 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2528 break;
2529 case 0xa9: /* pop gs */
2530 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2531 if (rc != 0)
2532 goto done;
2533 break;
7de75248
NK		 2534 case 0xab:
2535 bts: /* bts */
e4e03ded
LV		 2536 /* only subword offset */
2537 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2538 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2539 break;
9bf8ea42
GT		 2540 case 0xac: /* shrd imm8, r, r/m */
2541 case 0xad: /* shrd cl, r, r/m */
2542 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2543 break;
2a7c5b8b
GC		 2544 case 0xae: /* clflush */
2545 break;
6aa8b732
AK		 2546 case 0xb0 ... 0xb1: /* cmpxchg */
2547 /*
2548 * Save real source value, then compare EAX against
2549 * destination.
2550 */
e4e03ded
LV		 2551 c->src.orig_val = c->src.val;
2552 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2553 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2554 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2555 /* Success: write back to memory. */
e4e03ded 2556 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2557 } else {
2558 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2559 c->dst.type = OP_REG;
2560 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2561 }
2562 break;
6aa8b732
AK		 2563 case 0xb3:
2564 btr: /* btr */
e4e03ded
LV		 2565 /* only subword offset */
2566 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2567 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2568 break;
6aa8b732 2569 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2570 c->dst.bytes = c->op_bytes;
2571 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2572 : (u16) c->src.val;
6aa8b732 2573 break;
6aa8b732 2574 case 0xba: /* Grp8 */
e4e03ded 2575 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2576 case 0:
2577 goto bt;
2578 case 1:
2579 goto bts;
2580 case 2:
2581 goto btr;
2582 case 3:
2583 goto btc;
2584 }
2585 break;
7de75248
NK		 2586 case 0xbb:
2587 btc: /* btc */
e4e03ded
LV		 2588 /* only subword offset */
2589 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2590 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2591 break;
6aa8b732 2592 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2593 c->dst.bytes = c->op_bytes;
2594 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2595 (s16) c->src.val;
6aa8b732 2596 break;
a012e65a 2597 case 0xc3: /* movnti */
e4e03ded
LV		 2598 c->dst.bytes = c->op_bytes;
2599 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2600 (u64) c->src.val;
a012e65a 2601 break;
6aa8b732 2602 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2603 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2604 if (rc != 0)
2605 goto done;
018a98db 2606 c->dst.type = OP_NONE;
8cdbd2c9 2607 break;
6aa8b732
AK		 2608 }
2609 goto writeback;
2610
2611cannot_emulate:
e4e03ded 2612 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2613 c->eip = saved_eip;
6aa8b732
AK		 2614 return -1;
2615}
Linux kernel - Deliverables
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